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path: root/drivers/usb/host/ehci-pci.c
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Diffstat (limited to 'drivers/usb/host/ehci-pci.c')
-rw-r--r--drivers/usb/host/ehci-pci.c59
1 files changed, 24 insertions, 35 deletions
diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c
index a1bd2bea6deb..cadffacd945b 100644
--- a/drivers/usb/host/ehci-pci.c
+++ b/drivers/usb/host/ehci-pci.c
@@ -76,6 +76,30 @@ static int ehci_pci_setup(struct usb_hcd *hcd)
76 dbg_hcs_params(ehci, "reset"); 76 dbg_hcs_params(ehci, "reset");
77 dbg_hcc_params(ehci, "reset"); 77 dbg_hcc_params(ehci, "reset");
78 78
79 /* ehci_init() causes memory for DMA transfers to be
80 * allocated. Thus, any vendor-specific workarounds based on
81 * limiting the type of memory used for DMA transfers must
82 * happen before ehci_init() is called. */
83 switch (pdev->vendor) {
84 case PCI_VENDOR_ID_NVIDIA:
85 /* NVidia reports that certain chips don't handle
86 * QH, ITD, or SITD addresses above 2GB. (But TD,
87 * data buffer, and periodic schedule are normal.)
88 */
89 switch (pdev->device) {
90 case 0x003c: /* MCP04 */
91 case 0x005b: /* CK804 */
92 case 0x00d8: /* CK8 */
93 case 0x00e8: /* CK8S */
94 if (pci_set_consistent_dma_mask(pdev,
95 DMA_31BIT_MASK) < 0)
96 ehci_warn(ehci, "can't enable NVidia "
97 "workaround for >2GB RAM\n");
98 break;
99 }
100 break;
101 }
102
79 /* cache this readonly data; minimize chip reads */ 103 /* cache this readonly data; minimize chip reads */
80 ehci->hcs_params = readl(&ehci->caps->hcs_params); 104 ehci->hcs_params = readl(&ehci->caps->hcs_params);
81 105
@@ -88,8 +112,6 @@ static int ehci_pci_setup(struct usb_hcd *hcd)
88 if (retval) 112 if (retval)
89 return retval; 113 return retval;
90 114
91 /* NOTE: only the parts below this line are PCI-specific */
92
93 switch (pdev->vendor) { 115 switch (pdev->vendor) {
94 case PCI_VENDOR_ID_TDI: 116 case PCI_VENDOR_ID_TDI:
95 if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) { 117 if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) {
@@ -107,19 +129,6 @@ static int ehci_pci_setup(struct usb_hcd *hcd)
107 break; 129 break;
108 case PCI_VENDOR_ID_NVIDIA: 130 case PCI_VENDOR_ID_NVIDIA:
109 switch (pdev->device) { 131 switch (pdev->device) {
110 /* NVidia reports that certain chips don't handle
111 * QH, ITD, or SITD addresses above 2GB. (But TD,
112 * data buffer, and periodic schedule are normal.)
113 */
114 case 0x003c: /* MCP04 */
115 case 0x005b: /* CK804 */
116 case 0x00d8: /* CK8 */
117 case 0x00e8: /* CK8S */
118 if (pci_set_consistent_dma_mask(pdev,
119 DMA_31BIT_MASK) < 0)
120 ehci_warn(ehci, "can't enable NVidia "
121 "workaround for >2GB RAM\n");
122 break;
123 /* Some NForce2 chips have problems with selective suspend; 132 /* Some NForce2 chips have problems with selective suspend;
124 * fixed in newer silicon. 133 * fixed in newer silicon.
125 */ 134 */
@@ -370,23 +379,3 @@ static struct pci_driver ehci_pci_driver = {
370 .resume = usb_hcd_pci_resume, 379 .resume = usb_hcd_pci_resume,
371#endif 380#endif
372}; 381};
373
374static int __init ehci_hcd_pci_init(void)
375{
376 if (usb_disabled())
377 return -ENODEV;
378
379 pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n",
380 hcd_name,
381 sizeof(struct ehci_qh), sizeof(struct ehci_qtd),
382 sizeof(struct ehci_itd), sizeof(struct ehci_sitd));
383
384 return pci_register_driver(&ehci_pci_driver);
385}
386module_init(ehci_hcd_pci_init);
387
388static void __exit ehci_hcd_pci_cleanup(void)
389{
390 pci_unregister_driver(&ehci_pci_driver);
391}
392module_exit(ehci_hcd_pci_cleanup);