aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/usb/host/ehci-hcd.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/usb/host/ehci-hcd.c')
-rw-r--r--drivers/usb/host/ehci-hcd.c1261
1 files changed, 1261 insertions, 0 deletions
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
new file mode 100644
index 000000000000..a63bb792e2c7
--- /dev/null
+++ b/drivers/usb/host/ehci-hcd.c
@@ -0,0 +1,1261 @@
1/*
2 * Copyright (c) 2000-2004 by David Brownell
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software Foundation,
16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 */
18
19#include <linux/config.h>
20
21#ifdef CONFIG_USB_DEBUG
22 #define DEBUG
23#else
24 #undef DEBUG
25#endif
26
27#include <linux/module.h>
28#include <linux/pci.h>
29#include <linux/dmapool.h>
30#include <linux/kernel.h>
31#include <linux/delay.h>
32#include <linux/ioport.h>
33#include <linux/sched.h>
34#include <linux/slab.h>
35#include <linux/smp_lock.h>
36#include <linux/errno.h>
37#include <linux/init.h>
38#include <linux/timer.h>
39#include <linux/list.h>
40#include <linux/interrupt.h>
41#include <linux/reboot.h>
42#include <linux/usb.h>
43#include <linux/moduleparam.h>
44#include <linux/dma-mapping.h>
45
46#include "../core/hcd.h"
47
48#include <asm/byteorder.h>
49#include <asm/io.h>
50#include <asm/irq.h>
51#include <asm/system.h>
52#include <asm/unaligned.h>
53
54
55/*-------------------------------------------------------------------------*/
56
57/*
58 * EHCI hc_driver implementation ... experimental, incomplete.
59 * Based on the final 1.0 register interface specification.
60 *
61 * USB 2.0 shows up in upcoming www.pcmcia.org technology.
62 * First was PCMCIA, like ISA; then CardBus, which is PCI.
63 * Next comes "CardBay", using USB 2.0 signals.
64 *
65 * Contains additional contributions by Brad Hards, Rory Bolt, and others.
66 * Special thanks to Intel and VIA for providing host controllers to
67 * test this driver on, and Cypress (including In-System Design) for
68 * providing early devices for those host controllers to talk to!
69 *
70 * HISTORY:
71 *
72 * 2004-05-10 Root hub and PCI suspend/resume support; remote wakeup. (db)
73 * 2004-02-24 Replace pci_* with generic dma_* API calls (dsaxena@plexity.net)
74 * 2003-12-29 Rewritten high speed iso transfer support (by Michal Sojka,
75 * <sojkam@centrum.cz>, updates by DB).
76 *
77 * 2002-11-29 Correct handling for hw async_next register.
78 * 2002-08-06 Handling for bulk and interrupt transfers is mostly shared;
79 * only scheduling is different, no arbitrary limitations.
80 * 2002-07-25 Sanity check PCI reads, mostly for better cardbus support,
81 * clean up HC run state handshaking.
82 * 2002-05-24 Preliminary FS/LS interrupts, using scheduling shortcuts
83 * 2002-05-11 Clear TT errors for FS/LS ctrl/bulk. Fill in some other
84 * missing pieces: enabling 64bit dma, handoff from BIOS/SMM.
85 * 2002-05-07 Some error path cleanups to report better errors; wmb();
86 * use non-CVS version id; better iso bandwidth claim.
87 * 2002-04-19 Control/bulk/interrupt submit no longer uses giveback() on
88 * errors in submit path. Bugfixes to interrupt scheduling/processing.
89 * 2002-03-05 Initial high-speed ISO support; reduce ITD memory; shift
90 * more checking to generic hcd framework (db). Make it work with
91 * Philips EHCI; reduce PCI traffic; shorten IRQ path (Rory Bolt).
92 * 2002-01-14 Minor cleanup; version synch.
93 * 2002-01-08 Fix roothub handoff of FS/LS to companion controllers.
94 * 2002-01-04 Control/Bulk queuing behaves.
95 *
96 * 2001-12-12 Initial patch version for Linux 2.5.1 kernel.
97 * 2001-June Works with usb-storage and NEC EHCI on 2.4
98 */
99
100#define DRIVER_VERSION "10 Dec 2004"
101#define DRIVER_AUTHOR "David Brownell"
102#define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver"
103
104static const char hcd_name [] = "ehci_hcd";
105
106
107#undef EHCI_VERBOSE_DEBUG
108#undef EHCI_URB_TRACE
109
110#ifdef DEBUG
111#define EHCI_STATS
112#endif
113
114/* magic numbers that can affect system performance */
115#define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
116#define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
117#define EHCI_TUNE_RL_TT 0
118#define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
119#define EHCI_TUNE_MULT_TT 1
120#define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */
121
122#define EHCI_IAA_JIFFIES (HZ/100) /* arbitrary; ~10 msec */
123#define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */
124#define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */
125#define EHCI_SHRINK_JIFFIES (HZ/200) /* async qh unlink delay */
126
127/* Initial IRQ latency: faster than hw default */
128static int log2_irq_thresh = 0; // 0 to 6
129module_param (log2_irq_thresh, int, S_IRUGO);
130MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes");
131
132/* initial park setting: slower than hw default */
133static unsigned park = 0;
134module_param (park, uint, S_IRUGO);
135MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets");
136
137#define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
138
139/*-------------------------------------------------------------------------*/
140
141#include "ehci.h"
142#include "ehci-dbg.c"
143
144/*-------------------------------------------------------------------------*/
145
146/*
147 * handshake - spin reading hc until handshake completes or fails
148 * @ptr: address of hc register to be read
149 * @mask: bits to look at in result of read
150 * @done: value of those bits when handshake succeeds
151 * @usec: timeout in microseconds
152 *
153 * Returns negative errno, or zero on success
154 *
155 * Success happens when the "mask" bits have the specified value (hardware
156 * handshake done). There are two failure modes: "usec" have passed (major
157 * hardware flakeout), or the register reads as all-ones (hardware removed).
158 *
159 * That last failure should_only happen in cases like physical cardbus eject
160 * before driver shutdown. But it also seems to be caused by bugs in cardbus
161 * bridge shutdown: shutting down the bridge before the devices using it.
162 */
163static int handshake (void __iomem *ptr, u32 mask, u32 done, int usec)
164{
165 u32 result;
166
167 do {
168 result = readl (ptr);
169 if (result == ~(u32)0) /* card removed */
170 return -ENODEV;
171 result &= mask;
172 if (result == done)
173 return 0;
174 udelay (1);
175 usec--;
176 } while (usec > 0);
177 return -ETIMEDOUT;
178}
179
180/* force HC to halt state from unknown (EHCI spec section 2.3) */
181static int ehci_halt (struct ehci_hcd *ehci)
182{
183 u32 temp = readl (&ehci->regs->status);
184
185 if ((temp & STS_HALT) != 0)
186 return 0;
187
188 temp = readl (&ehci->regs->command);
189 temp &= ~CMD_RUN;
190 writel (temp, &ehci->regs->command);
191 return handshake (&ehci->regs->status, STS_HALT, STS_HALT, 16 * 125);
192}
193
194/* put TDI/ARC silicon into EHCI mode */
195static void tdi_reset (struct ehci_hcd *ehci)
196{
197 u32 __iomem *reg_ptr;
198 u32 tmp;
199
200 reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + 0x68);
201 tmp = readl (reg_ptr);
202 tmp |= 0x3;
203 writel (tmp, reg_ptr);
204}
205
206/* reset a non-running (STS_HALT == 1) controller */
207static int ehci_reset (struct ehci_hcd *ehci)
208{
209 int retval;
210 u32 command = readl (&ehci->regs->command);
211
212 command |= CMD_RESET;
213 dbg_cmd (ehci, "reset", command);
214 writel (command, &ehci->regs->command);
215 ehci_to_hcd(ehci)->state = HC_STATE_HALT;
216 ehci->next_statechange = jiffies;
217 retval = handshake (&ehci->regs->command, CMD_RESET, 0, 250 * 1000);
218
219 if (retval)
220 return retval;
221
222 if (ehci_is_TDI(ehci))
223 tdi_reset (ehci);
224
225 return retval;
226}
227
228/* idle the controller (from running) */
229static void ehci_quiesce (struct ehci_hcd *ehci)
230{
231 u32 temp;
232
233#ifdef DEBUG
234 if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state))
235 BUG ();
236#endif
237
238 /* wait for any schedule enables/disables to take effect */
239 temp = readl (&ehci->regs->command) << 10;
240 temp &= STS_ASS | STS_PSS;
241 if (handshake (&ehci->regs->status, STS_ASS | STS_PSS,
242 temp, 16 * 125) != 0) {
243 ehci_to_hcd(ehci)->state = HC_STATE_HALT;
244 return;
245 }
246
247 /* then disable anything that's still active */
248 temp = readl (&ehci->regs->command);
249 temp &= ~(CMD_ASE | CMD_IAAD | CMD_PSE);
250 writel (temp, &ehci->regs->command);
251
252 /* hardware can take 16 microframes to turn off ... */
253 if (handshake (&ehci->regs->status, STS_ASS | STS_PSS,
254 0, 16 * 125) != 0) {
255 ehci_to_hcd(ehci)->state = HC_STATE_HALT;
256 return;
257 }
258}
259
260/*-------------------------------------------------------------------------*/
261
262static void ehci_work(struct ehci_hcd *ehci, struct pt_regs *regs);
263
264#include "ehci-hub.c"
265#include "ehci-mem.c"
266#include "ehci-q.c"
267#include "ehci-sched.c"
268
269/*-------------------------------------------------------------------------*/
270
271static void ehci_watchdog (unsigned long param)
272{
273 struct ehci_hcd *ehci = (struct ehci_hcd *) param;
274 unsigned long flags;
275
276 spin_lock_irqsave (&ehci->lock, flags);
277
278 /* lost IAA irqs wedge things badly; seen with a vt8235 */
279 if (ehci->reclaim) {
280 u32 status = readl (&ehci->regs->status);
281
282 if (status & STS_IAA) {
283 ehci_vdbg (ehci, "lost IAA\n");
284 COUNT (ehci->stats.lost_iaa);
285 writel (STS_IAA, &ehci->regs->status);
286 ehci->reclaim_ready = 1;
287 }
288 }
289
290 /* stop async processing after it's idled a bit */
291 if (test_bit (TIMER_ASYNC_OFF, &ehci->actions))
292 start_unlink_async (ehci, ehci->async);
293
294 /* ehci could run by timer, without IRQs ... */
295 ehci_work (ehci, NULL);
296
297 spin_unlock_irqrestore (&ehci->lock, flags);
298}
299
300#ifdef CONFIG_PCI
301
302/* EHCI 0.96 (and later) section 5.1 says how to kick BIOS/SMM/...
303 * off the controller (maybe it can boot from highspeed USB disks).
304 */
305static int bios_handoff (struct ehci_hcd *ehci, int where, u32 cap)
306{
307 if (cap & (1 << 16)) {
308 int msec = 5000;
309 struct pci_dev *pdev =
310 to_pci_dev(ehci_to_hcd(ehci)->self.controller);
311
312 /* request handoff to OS */
313 cap |= 1 << 24;
314 pci_write_config_dword(pdev, where, cap);
315
316 /* and wait a while for it to happen */
317 do {
318 msleep(10);
319 msec -= 10;
320 pci_read_config_dword(pdev, where, &cap);
321 } while ((cap & (1 << 16)) && msec);
322 if (cap & (1 << 16)) {
323 ehci_err (ehci, "BIOS handoff failed (%d, %04x)\n",
324 where, cap);
325 // some BIOS versions seem buggy...
326 // return 1;
327 ehci_warn (ehci, "continuing after BIOS bug...\n");
328 return 0;
329 }
330 ehci_dbg (ehci, "BIOS handoff succeeded\n");
331 }
332 return 0;
333}
334
335#endif
336
337static int
338ehci_reboot (struct notifier_block *self, unsigned long code, void *null)
339{
340 struct ehci_hcd *ehci;
341
342 ehci = container_of (self, struct ehci_hcd, reboot_notifier);
343
344 /* make BIOS/etc use companion controller during reboot */
345 writel (0, &ehci->regs->configured_flag);
346 return 0;
347}
348
349
350/* called by khubd or root hub init threads */
351
352static int ehci_hc_reset (struct usb_hcd *hcd)
353{
354 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
355 u32 temp;
356 unsigned count = 256/4;
357
358 spin_lock_init (&ehci->lock);
359
360 ehci->caps = hcd->regs;
361 ehci->regs = hcd->regs + HC_LENGTH (readl (&ehci->caps->hc_capbase));
362 dbg_hcs_params (ehci, "reset");
363 dbg_hcc_params (ehci, "reset");
364
365#ifdef CONFIG_PCI
366 /* EHCI 0.96 and later may have "extended capabilities" */
367 if (hcd->self.controller->bus == &pci_bus_type) {
368 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
369
370 switch (pdev->vendor) {
371 case PCI_VENDOR_ID_TDI:
372 if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) {
373 ehci->is_tdi_rh_tt = 1;
374 tdi_reset (ehci);
375 }
376 break;
377 case PCI_VENDOR_ID_AMD:
378 /* AMD8111 EHCI doesn't work, according to AMD errata */
379 if (pdev->device == 0x7463) {
380 ehci_info (ehci, "ignoring AMD8111 (errata)\n");
381 return -EIO;
382 }
383 break;
384 }
385
386 temp = HCC_EXT_CAPS (readl (&ehci->caps->hcc_params));
387 } else
388 temp = 0;
389 while (temp && count--) {
390 u32 cap;
391
392 pci_read_config_dword (to_pci_dev(hcd->self.controller),
393 temp, &cap);
394 ehci_dbg (ehci, "capability %04x at %02x\n", cap, temp);
395 switch (cap & 0xff) {
396 case 1: /* BIOS/SMM/... handoff */
397 if (bios_handoff (ehci, temp, cap) != 0)
398 return -EOPNOTSUPP;
399 break;
400 case 0: /* illegal reserved capability */
401 ehci_warn (ehci, "illegal capability!\n");
402 cap = 0;
403 /* FALLTHROUGH */
404 default: /* unknown */
405 break;
406 }
407 temp = (cap >> 8) & 0xff;
408 }
409 if (!count) {
410 ehci_err (ehci, "bogus capabilities ... PCI problems!\n");
411 return -EIO;
412 }
413 if (ehci_is_TDI(ehci))
414 ehci_reset (ehci);
415#endif
416
417 /* cache this readonly data; minimize PCI reads */
418 ehci->hcs_params = readl (&ehci->caps->hcs_params);
419
420 /* at least the Genesys GL880S needs fixup here */
421 temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
422 temp &= 0x0f;
423 if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
424 ehci_dbg (ehci, "bogus port configuration: "
425 "cc=%d x pcc=%d < ports=%d\n",
426 HCS_N_CC(ehci->hcs_params),
427 HCS_N_PCC(ehci->hcs_params),
428 HCS_N_PORTS(ehci->hcs_params));
429
430#ifdef CONFIG_PCI
431 if (hcd->self.controller->bus == &pci_bus_type) {
432 struct pci_dev *pdev;
433
434 pdev = to_pci_dev(hcd->self.controller);
435 switch (pdev->vendor) {
436 case 0x17a0: /* GENESYS */
437 /* GL880S: should be PORTS=2 */
438 temp |= (ehci->hcs_params & ~0xf);
439 ehci->hcs_params = temp;
440 break;
441 case PCI_VENDOR_ID_NVIDIA:
442 /* NF4: should be PCC=10 */
443 break;
444 }
445 }
446#endif
447 }
448
449 /* force HC to halt state */
450 return ehci_halt (ehci);
451}
452
453static int ehci_start (struct usb_hcd *hcd)
454{
455 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
456 u32 temp;
457 struct usb_device *udev;
458 struct usb_bus *bus;
459 int retval;
460 u32 hcc_params;
461 u8 sbrn = 0;
462 int first;
463
464 /* skip some things on restart paths */
465 first = (ehci->watchdog.data == 0);
466 if (first) {
467 init_timer (&ehci->watchdog);
468 ehci->watchdog.function = ehci_watchdog;
469 ehci->watchdog.data = (unsigned long) ehci;
470 }
471
472 /*
473 * hw default: 1K periodic list heads, one per frame.
474 * periodic_size can shrink by USBCMD update if hcc_params allows.
475 */
476 ehci->periodic_size = DEFAULT_I_TDPS;
477 if (first && (retval = ehci_mem_init (ehci, GFP_KERNEL)) < 0)
478 return retval;
479
480 /* controllers may cache some of the periodic schedule ... */
481 hcc_params = readl (&ehci->caps->hcc_params);
482 if (HCC_ISOC_CACHE (hcc_params)) // full frame cache
483 ehci->i_thresh = 8;
484 else // N microframes cached
485 ehci->i_thresh = 2 + HCC_ISOC_THRES (hcc_params);
486
487 ehci->reclaim = NULL;
488 ehci->reclaim_ready = 0;
489 ehci->next_uframe = -1;
490
491 /* controller state: unknown --> reset */
492
493 /* EHCI spec section 4.1 */
494 if ((retval = ehci_reset (ehci)) != 0) {
495 ehci_mem_cleanup (ehci);
496 return retval;
497 }
498 writel (ehci->periodic_dma, &ehci->regs->frame_list);
499
500#ifdef CONFIG_PCI
501 if (hcd->self.controller->bus == &pci_bus_type) {
502 struct pci_dev *pdev;
503 u16 port_wake;
504
505 pdev = to_pci_dev(hcd->self.controller);
506
507 /* Serial Bus Release Number is at PCI 0x60 offset */
508 pci_read_config_byte(pdev, 0x60, &sbrn);
509
510 /* port wake capability, reported by boot firmware */
511 pci_read_config_word(pdev, 0x62, &port_wake);
512 hcd->can_wakeup = (port_wake & 1) != 0;
513
514 /* help hc dma work well with cachelines */
515 pci_set_mwi (pdev);
516 }
517#endif
518
519 /*
520 * dedicate a qh for the async ring head, since we couldn't unlink
521 * a 'real' qh without stopping the async schedule [4.8]. use it
522 * as the 'reclamation list head' too.
523 * its dummy is used in hw_alt_next of many tds, to prevent the qh
524 * from automatically advancing to the next td after short reads.
525 */
526 if (first) {
527 ehci->async->qh_next.qh = NULL;
528 ehci->async->hw_next = QH_NEXT (ehci->async->qh_dma);
529 ehci->async->hw_info1 = cpu_to_le32 (QH_HEAD);
530 ehci->async->hw_token = cpu_to_le32 (QTD_STS_HALT);
531 ehci->async->hw_qtd_next = EHCI_LIST_END;
532 ehci->async->qh_state = QH_STATE_LINKED;
533 ehci->async->hw_alt_next = QTD_NEXT (ehci->async->dummy->qtd_dma);
534 }
535 writel ((u32)ehci->async->qh_dma, &ehci->regs->async_next);
536
537 /*
538 * hcc_params controls whether ehci->regs->segment must (!!!)
539 * be used; it constrains QH/ITD/SITD and QTD locations.
540 * pci_pool consistent memory always uses segment zero.
541 * streaming mappings for I/O buffers, like pci_map_single(),
542 * can return segments above 4GB, if the device allows.
543 *
544 * NOTE: the dma mask is visible through dma_supported(), so
545 * drivers can pass this info along ... like NETIF_F_HIGHDMA,
546 * Scsi_Host.highmem_io, and so forth. It's readonly to all
547 * host side drivers though.
548 */
549 if (HCC_64BIT_ADDR (hcc_params)) {
550 writel (0, &ehci->regs->segment);
551#if 0
552// this is deeply broken on almost all architectures
553 if (!pci_set_dma_mask (to_pci_dev(hcd->self.controller), 0xffffffffffffffffULL))
554 ehci_info (ehci, "enabled 64bit PCI DMA\n");
555#endif
556 }
557
558 /* clear interrupt enables, set irq latency */
559 if (log2_irq_thresh < 0 || log2_irq_thresh > 6)
560 log2_irq_thresh = 0;
561 temp = 1 << (16 + log2_irq_thresh);
562 if (HCC_CANPARK(hcc_params)) {
563 /* HW default park == 3, on hardware that supports it (like
564 * NVidia and ALI silicon), maximizes throughput on the async
565 * schedule by avoiding QH fetches between transfers.
566 *
567 * With fast usb storage devices and NForce2, "park" seems to
568 * make problems: throughput reduction (!), data errors...
569 */
570 if (park) {
571 park = min (park, (unsigned) 3);
572 temp |= CMD_PARK;
573 temp |= park << 8;
574 }
575 ehci_info (ehci, "park %d\n", park);
576 }
577 if (HCC_PGM_FRAMELISTLEN (hcc_params)) {
578 /* periodic schedule size can be smaller than default */
579 temp &= ~(3 << 2);
580 temp |= (EHCI_TUNE_FLS << 2);
581 switch (EHCI_TUNE_FLS) {
582 case 0: ehci->periodic_size = 1024; break;
583 case 1: ehci->periodic_size = 512; break;
584 case 2: ehci->periodic_size = 256; break;
585 default: BUG ();
586 }
587 }
588 // Philips, Intel, and maybe others need CMD_RUN before the
589 // root hub will detect new devices (why?); NEC doesn't
590 temp |= CMD_RUN;
591 writel (temp, &ehci->regs->command);
592 dbg_cmd (ehci, "init", temp);
593
594 /* set async sleep time = 10 us ... ? */
595
596 /* wire up the root hub */
597 bus = hcd_to_bus (hcd);
598 udev = first ? usb_alloc_dev (NULL, bus, 0) : bus->root_hub;
599 if (!udev) {
600done2:
601 ehci_mem_cleanup (ehci);
602 return -ENOMEM;
603 }
604 udev->speed = USB_SPEED_HIGH;
605 udev->state = first ? USB_STATE_ATTACHED : USB_STATE_CONFIGURED;
606
607 /*
608 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
609 * are explicitly handed to companion controller(s), so no TT is
610 * involved with the root hub. (Except where one is integrated,
611 * and there's no companion controller unless maybe for USB OTG.)
612 */
613 if (first) {
614 ehci->reboot_notifier.notifier_call = ehci_reboot;
615 register_reboot_notifier (&ehci->reboot_notifier);
616 }
617
618 hcd->state = HC_STATE_RUNNING;
619 writel (FLAG_CF, &ehci->regs->configured_flag);
620 readl (&ehci->regs->command); /* unblock posted write */
621
622 temp = HC_VERSION(readl (&ehci->caps->hc_capbase));
623 ehci_info (ehci,
624 "USB %x.%x %s, EHCI %x.%02x, driver %s\n",
625 ((sbrn & 0xf0)>>4), (sbrn & 0x0f),
626 first ? "initialized" : "restarted",
627 temp >> 8, temp & 0xff, DRIVER_VERSION);
628
629 /*
630 * From here on, khubd concurrently accesses the root
631 * hub; drivers will be talking to enumerated devices.
632 * (On restart paths, khubd already knows about the root
633 * hub and could find work as soon as we wrote FLAG_CF.)
634 *
635 * Before this point the HC was idle/ready. After, khubd
636 * and device drivers may start it running.
637 */
638 if (first && usb_hcd_register_root_hub (udev, hcd) != 0) {
639 if (hcd->state == HC_STATE_RUNNING)
640 ehci_quiesce (ehci);
641 ehci_reset (ehci);
642 usb_put_dev (udev);
643 retval = -ENODEV;
644 goto done2;
645 }
646
647 writel (INTR_MASK, &ehci->regs->intr_enable); /* Turn On Interrupts */
648
649 if (first)
650 create_debug_files (ehci);
651
652 return 0;
653}
654
655/* always called by thread; normally rmmod */
656
657static void ehci_stop (struct usb_hcd *hcd)
658{
659 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
660 u8 rh_ports, port;
661
662 ehci_dbg (ehci, "stop\n");
663
664 /* Turn off port power on all root hub ports. */
665 rh_ports = HCS_N_PORTS (ehci->hcs_params);
666 for (port = 1; port <= rh_ports; port++)
667 (void) ehci_hub_control(hcd,
668 ClearPortFeature, USB_PORT_FEAT_POWER,
669 port, NULL, 0);
670
671 /* no more interrupts ... */
672 del_timer_sync (&ehci->watchdog);
673
674 spin_lock_irq(&ehci->lock);
675 if (HC_IS_RUNNING (hcd->state))
676 ehci_quiesce (ehci);
677
678 ehci_reset (ehci);
679 writel (0, &ehci->regs->intr_enable);
680 spin_unlock_irq(&ehci->lock);
681
682 /* let companion controllers work when we aren't */
683 writel (0, &ehci->regs->configured_flag);
684 unregister_reboot_notifier (&ehci->reboot_notifier);
685
686 remove_debug_files (ehci);
687
688 /* root hub is shut down separately (first, when possible) */
689 spin_lock_irq (&ehci->lock);
690 if (ehci->async)
691 ehci_work (ehci, NULL);
692 spin_unlock_irq (&ehci->lock);
693 ehci_mem_cleanup (ehci);
694
695#ifdef EHCI_STATS
696 ehci_dbg (ehci, "irq normal %ld err %ld reclaim %ld (lost %ld)\n",
697 ehci->stats.normal, ehci->stats.error, ehci->stats.reclaim,
698 ehci->stats.lost_iaa);
699 ehci_dbg (ehci, "complete %ld unlink %ld\n",
700 ehci->stats.complete, ehci->stats.unlink);
701#endif
702
703 dbg_status (ehci, "ehci_stop completed", readl (&ehci->regs->status));
704}
705
706static int ehci_get_frame (struct usb_hcd *hcd)
707{
708 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
709 return (readl (&ehci->regs->frame_index) >> 3) % ehci->periodic_size;
710}
711
712/*-------------------------------------------------------------------------*/
713
714#ifdef CONFIG_PM
715
716/* suspend/resume, section 4.3 */
717
718/* These routines rely on the bus (pci, platform, etc)
719 * to handle powerdown and wakeup, and currently also on
720 * transceivers that don't need any software attention to set up
721 * the right sort of wakeup.
722 */
723
724static int ehci_suspend (struct usb_hcd *hcd, u32 state)
725{
726 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
727
728 if (time_before (jiffies, ehci->next_statechange))
729 msleep (100);
730
731#ifdef CONFIG_USB_SUSPEND
732 (void) usb_suspend_device (hcd->self.root_hub, state);
733#else
734 usb_lock_device (hcd->self.root_hub);
735 (void) ehci_hub_suspend (hcd);
736 usb_unlock_device (hcd->self.root_hub);
737#endif
738
739 // save (PCI) FLADJ in case of Vaux power loss
740 // ... we'd only use it to handle clock skew
741
742 return 0;
743}
744
745static int ehci_resume (struct usb_hcd *hcd)
746{
747 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
748 unsigned port;
749 struct usb_device *root = hcd->self.root_hub;
750 int retval = -EINVAL;
751 int powerup = 0;
752
753 // maybe restore (PCI) FLADJ
754
755 if (time_before (jiffies, ehci->next_statechange))
756 msleep (100);
757
758 /* If any port is suspended, we know we can/must resume the HC. */
759 for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; ) {
760 u32 status;
761 port--;
762 status = readl (&ehci->regs->port_status [port]);
763 if (status & PORT_SUSPEND) {
764 down (&hcd->self.root_hub->serialize);
765 retval = ehci_hub_resume (hcd);
766 up (&hcd->self.root_hub->serialize);
767 break;
768 }
769 if ((status & PORT_POWER) == 0)
770 powerup = 1;
771 if (!root->children [port])
772 continue;
773 dbg_port (ehci, __FUNCTION__, port + 1, status);
774 usb_set_device_state (root->children[port],
775 USB_STATE_NOTATTACHED);
776 }
777
778 /* Else reset, to cope with power loss or flush-to-storage
779 * style "resume" having activated BIOS during reboot.
780 */
781 if (port == 0) {
782 (void) ehci_halt (ehci);
783 (void) ehci_reset (ehci);
784 (void) ehci_hc_reset (hcd);
785
786 /* emptying the schedule aborts any urbs */
787 spin_lock_irq (&ehci->lock);
788 if (ehci->reclaim)
789 ehci->reclaim_ready = 1;
790 ehci_work (ehci, NULL);
791 spin_unlock_irq (&ehci->lock);
792
793 /* restart; khubd will disconnect devices */
794 retval = ehci_start (hcd);
795
796 /* here we "know" root ports should always stay powered;
797 * but some controllers may lost all power.
798 */
799 if (powerup) {
800 ehci_dbg (ehci, "...powerup ports...\n");
801 for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; )
802 (void) ehci_hub_control(hcd,
803 SetPortFeature, USB_PORT_FEAT_POWER,
804 port--, NULL, 0);
805 msleep(20);
806 }
807 }
808
809 return retval;
810}
811
812#endif
813
814/*-------------------------------------------------------------------------*/
815
816/*
817 * ehci_work is called from some interrupts, timers, and so on.
818 * it calls driver completion functions, after dropping ehci->lock.
819 */
820static void ehci_work (struct ehci_hcd *ehci, struct pt_regs *regs)
821{
822 timer_action_done (ehci, TIMER_IO_WATCHDOG);
823 if (ehci->reclaim_ready)
824 end_unlink_async (ehci, regs);
825
826 /* another CPU may drop ehci->lock during a schedule scan while
827 * it reports urb completions. this flag guards against bogus
828 * attempts at re-entrant schedule scanning.
829 */
830 if (ehci->scanning)
831 return;
832 ehci->scanning = 1;
833 scan_async (ehci, regs);
834 if (ehci->next_uframe != -1)
835 scan_periodic (ehci, regs);
836 ehci->scanning = 0;
837
838 /* the IO watchdog guards against hardware or driver bugs that
839 * misplace IRQs, and should let us run completely without IRQs.
840 * such lossage has been observed on both VT6202 and VT8235.
841 */
842 if (HC_IS_RUNNING (ehci_to_hcd(ehci)->state) &&
843 (ehci->async->qh_next.ptr != NULL ||
844 ehci->periodic_sched != 0))
845 timer_action (ehci, TIMER_IO_WATCHDOG);
846}
847
848/*-------------------------------------------------------------------------*/
849
850static irqreturn_t ehci_irq (struct usb_hcd *hcd, struct pt_regs *regs)
851{
852 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
853 u32 status;
854 int bh;
855
856 spin_lock (&ehci->lock);
857
858 status = readl (&ehci->regs->status);
859
860 /* e.g. cardbus physical eject */
861 if (status == ~(u32) 0) {
862 ehci_dbg (ehci, "device removed\n");
863 goto dead;
864 }
865
866 status &= INTR_MASK;
867 if (!status) { /* irq sharing? */
868 spin_unlock(&ehci->lock);
869 return IRQ_NONE;
870 }
871
872 /* clear (just) interrupts */
873 writel (status, &ehci->regs->status);
874 readl (&ehci->regs->command); /* unblock posted write */
875 bh = 0;
876
877#ifdef EHCI_VERBOSE_DEBUG
878 /* unrequested/ignored: Frame List Rollover */
879 dbg_status (ehci, "irq", status);
880#endif
881
882 /* INT, ERR, and IAA interrupt rates can be throttled */
883
884 /* normal [4.15.1.2] or error [4.15.1.1] completion */
885 if (likely ((status & (STS_INT|STS_ERR)) != 0)) {
886 if (likely ((status & STS_ERR) == 0))
887 COUNT (ehci->stats.normal);
888 else
889 COUNT (ehci->stats.error);
890 bh = 1;
891 }
892
893 /* complete the unlinking of some qh [4.15.2.3] */
894 if (status & STS_IAA) {
895 COUNT (ehci->stats.reclaim);
896 ehci->reclaim_ready = 1;
897 bh = 1;
898 }
899
900 /* remote wakeup [4.3.1] */
901 if ((status & STS_PCD) && hcd->remote_wakeup) {
902 unsigned i = HCS_N_PORTS (ehci->hcs_params);
903
904 /* resume root hub? */
905 status = readl (&ehci->regs->command);
906 if (!(status & CMD_RUN))
907 writel (status | CMD_RUN, &ehci->regs->command);
908
909 while (i--) {
910 status = readl (&ehci->regs->port_status [i]);
911 if (status & PORT_OWNER)
912 continue;
913 if (!(status & PORT_RESUME)
914 || ehci->reset_done [i] != 0)
915 continue;
916
917 /* start 20 msec resume signaling from this port,
918 * and make khubd collect PORT_STAT_C_SUSPEND to
919 * stop that signaling.
920 */
921 ehci->reset_done [i] = jiffies + msecs_to_jiffies (20);
922 mod_timer (&hcd->rh_timer,
923 ehci->reset_done [i] + 1);
924 ehci_dbg (ehci, "port %d remote wakeup\n", i + 1);
925 }
926 }
927
928 /* PCI errors [4.15.2.4] */
929 if (unlikely ((status & STS_FATAL) != 0)) {
930 /* bogus "fatal" IRQs appear on some chips... why? */
931 status = readl (&ehci->regs->status);
932 dbg_cmd (ehci, "fatal", readl (&ehci->regs->command));
933 dbg_status (ehci, "fatal", status);
934 if (status & STS_HALT) {
935 ehci_err (ehci, "fatal error\n");
936dead:
937 ehci_reset (ehci);
938 writel (0, &ehci->regs->configured_flag);
939 /* generic layer kills/unlinks all urbs, then
940 * uses ehci_stop to clean up the rest
941 */
942 bh = 1;
943 }
944 }
945
946 if (bh)
947 ehci_work (ehci, regs);
948 spin_unlock (&ehci->lock);
949 return IRQ_HANDLED;
950}
951
952/*-------------------------------------------------------------------------*/
953
954/*
955 * non-error returns are a promise to giveback() the urb later
956 * we drop ownership so next owner (or urb unlink) can get it
957 *
958 * urb + dev is in hcd.self.controller.urb_list
959 * we're queueing TDs onto software and hardware lists
960 *
961 * hcd-specific init for hcpriv hasn't been done yet
962 *
963 * NOTE: control, bulk, and interrupt share the same code to append TDs
964 * to a (possibly active) QH, and the same QH scanning code.
965 */
966static int ehci_urb_enqueue (
967 struct usb_hcd *hcd,
968 struct usb_host_endpoint *ep,
969 struct urb *urb,
970 int mem_flags
971) {
972 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
973 struct list_head qtd_list;
974
975 INIT_LIST_HEAD (&qtd_list);
976
977 switch (usb_pipetype (urb->pipe)) {
978 // case PIPE_CONTROL:
979 // case PIPE_BULK:
980 default:
981 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
982 return -ENOMEM;
983 return submit_async (ehci, ep, urb, &qtd_list, mem_flags);
984
985 case PIPE_INTERRUPT:
986 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
987 return -ENOMEM;
988 return intr_submit (ehci, ep, urb, &qtd_list, mem_flags);
989
990 case PIPE_ISOCHRONOUS:
991 if (urb->dev->speed == USB_SPEED_HIGH)
992 return itd_submit (ehci, urb, mem_flags);
993 else
994 return sitd_submit (ehci, urb, mem_flags);
995 }
996}
997
998static void unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh)
999{
1000 /* if we need to use IAA and it's busy, defer */
1001 if (qh->qh_state == QH_STATE_LINKED
1002 && ehci->reclaim
1003 && HC_IS_RUNNING (ehci_to_hcd(ehci)->state)) {
1004 struct ehci_qh *last;
1005
1006 for (last = ehci->reclaim;
1007 last->reclaim;
1008 last = last->reclaim)
1009 continue;
1010 qh->qh_state = QH_STATE_UNLINK_WAIT;
1011 last->reclaim = qh;
1012
1013 /* bypass IAA if the hc can't care */
1014 } else if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state) && ehci->reclaim)
1015 end_unlink_async (ehci, NULL);
1016
1017 /* something else might have unlinked the qh by now */
1018 if (qh->qh_state == QH_STATE_LINKED)
1019 start_unlink_async (ehci, qh);
1020}
1021
1022/* remove from hardware lists
1023 * completions normally happen asynchronously
1024 */
1025
1026static int ehci_urb_dequeue (struct usb_hcd *hcd, struct urb *urb)
1027{
1028 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
1029 struct ehci_qh *qh;
1030 unsigned long flags;
1031
1032 spin_lock_irqsave (&ehci->lock, flags);
1033 switch (usb_pipetype (urb->pipe)) {
1034 // case PIPE_CONTROL:
1035 // case PIPE_BULK:
1036 default:
1037 qh = (struct ehci_qh *) urb->hcpriv;
1038 if (!qh)
1039 break;
1040 unlink_async (ehci, qh);
1041 break;
1042
1043 case PIPE_INTERRUPT:
1044 qh = (struct ehci_qh *) urb->hcpriv;
1045 if (!qh)
1046 break;
1047 switch (qh->qh_state) {
1048 case QH_STATE_LINKED:
1049 intr_deschedule (ehci, qh);
1050 /* FALL THROUGH */
1051 case QH_STATE_IDLE:
1052 qh_completions (ehci, qh, NULL);
1053 break;
1054 default:
1055 ehci_dbg (ehci, "bogus qh %p state %d\n",
1056 qh, qh->qh_state);
1057 goto done;
1058 }
1059
1060 /* reschedule QH iff another request is queued */
1061 if (!list_empty (&qh->qtd_list)
1062 && HC_IS_RUNNING (hcd->state)) {
1063 int status;
1064
1065 status = qh_schedule (ehci, qh);
1066 spin_unlock_irqrestore (&ehci->lock, flags);
1067
1068 if (status != 0) {
1069 // shouldn't happen often, but ...
1070 // FIXME kill those tds' urbs
1071 err ("can't reschedule qh %p, err %d",
1072 qh, status);
1073 }
1074 return status;
1075 }
1076 break;
1077
1078 case PIPE_ISOCHRONOUS:
1079 // itd or sitd ...
1080
1081 // wait till next completion, do it then.
1082 // completion irqs can wait up to 1024 msec,
1083 break;
1084 }
1085done:
1086 spin_unlock_irqrestore (&ehci->lock, flags);
1087 return 0;
1088}
1089
1090/*-------------------------------------------------------------------------*/
1091
1092// bulk qh holds the data toggle
1093
1094static void
1095ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
1096{
1097 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
1098 unsigned long flags;
1099 struct ehci_qh *qh, *tmp;
1100
1101 /* ASSERT: any requests/urbs are being unlinked */
1102 /* ASSERT: nobody can be submitting urbs for this any more */
1103
1104rescan:
1105 spin_lock_irqsave (&ehci->lock, flags);
1106 qh = ep->hcpriv;
1107 if (!qh)
1108 goto done;
1109
1110 /* endpoints can be iso streams. for now, we don't
1111 * accelerate iso completions ... so spin a while.
1112 */
1113 if (qh->hw_info1 == 0) {
1114 ehci_vdbg (ehci, "iso delay\n");
1115 goto idle_timeout;
1116 }
1117
1118 if (!HC_IS_RUNNING (hcd->state))
1119 qh->qh_state = QH_STATE_IDLE;
1120 switch (qh->qh_state) {
1121 case QH_STATE_LINKED:
1122 for (tmp = ehci->async->qh_next.qh;
1123 tmp && tmp != qh;
1124 tmp = tmp->qh_next.qh)
1125 continue;
1126 /* periodic qh self-unlinks on empty */
1127 if (!tmp)
1128 goto nogood;
1129 unlink_async (ehci, qh);
1130 /* FALL THROUGH */
1131 case QH_STATE_UNLINK: /* wait for hw to finish? */
1132idle_timeout:
1133 spin_unlock_irqrestore (&ehci->lock, flags);
1134 set_current_state (TASK_UNINTERRUPTIBLE);
1135 schedule_timeout (1);
1136 goto rescan;
1137 case QH_STATE_IDLE: /* fully unlinked */
1138 if (list_empty (&qh->qtd_list)) {
1139 qh_put (qh);
1140 break;
1141 }
1142 /* else FALL THROUGH */
1143 default:
1144nogood:
1145 /* caller was supposed to have unlinked any requests;
1146 * that's not our job. just leak this memory.
1147 */
1148 ehci_err (ehci, "qh %p (#%02x) state %d%s\n",
1149 qh, ep->desc.bEndpointAddress, qh->qh_state,
1150 list_empty (&qh->qtd_list) ? "" : "(has tds)");
1151 break;
1152 }
1153 ep->hcpriv = NULL;
1154done:
1155 spin_unlock_irqrestore (&ehci->lock, flags);
1156 return;
1157}
1158
1159/*-------------------------------------------------------------------------*/
1160
1161static const struct hc_driver ehci_driver = {
1162 .description = hcd_name,
1163 .product_desc = "EHCI Host Controller",
1164 .hcd_priv_size = sizeof(struct ehci_hcd),
1165
1166 /*
1167 * generic hardware linkage
1168 */
1169 .irq = ehci_irq,
1170 .flags = HCD_MEMORY | HCD_USB2,
1171
1172 /*
1173 * basic lifecycle operations
1174 */
1175 .reset = ehci_hc_reset,
1176 .start = ehci_start,
1177#ifdef CONFIG_PM
1178 .suspend = ehci_suspend,
1179 .resume = ehci_resume,
1180#endif
1181 .stop = ehci_stop,
1182
1183 /*
1184 * managing i/o requests and associated device resources
1185 */
1186 .urb_enqueue = ehci_urb_enqueue,
1187 .urb_dequeue = ehci_urb_dequeue,
1188 .endpoint_disable = ehci_endpoint_disable,
1189
1190 /*
1191 * scheduling support
1192 */
1193 .get_frame_number = ehci_get_frame,
1194
1195 /*
1196 * root hub support
1197 */
1198 .hub_status_data = ehci_hub_status_data,
1199 .hub_control = ehci_hub_control,
1200 .hub_suspend = ehci_hub_suspend,
1201 .hub_resume = ehci_hub_resume,
1202};
1203
1204/*-------------------------------------------------------------------------*/
1205
1206/* EHCI 1.0 doesn't require PCI */
1207
1208#ifdef CONFIG_PCI
1209
1210/* PCI driver selection metadata; PCI hotplugging uses this */
1211static const struct pci_device_id pci_ids [] = { {
1212 /* handle any USB 2.0 EHCI controller */
1213 PCI_DEVICE_CLASS(((PCI_CLASS_SERIAL_USB << 8) | 0x20), ~0),
1214 .driver_data = (unsigned long) &ehci_driver,
1215 },
1216 { /* end: all zeroes */ }
1217};
1218MODULE_DEVICE_TABLE (pci, pci_ids);
1219
1220/* pci driver glue; this is a "new style" PCI driver module */
1221static struct pci_driver ehci_pci_driver = {
1222 .name = (char *) hcd_name,
1223 .id_table = pci_ids,
1224
1225 .probe = usb_hcd_pci_probe,
1226 .remove = usb_hcd_pci_remove,
1227
1228#ifdef CONFIG_PM
1229 .suspend = usb_hcd_pci_suspend,
1230 .resume = usb_hcd_pci_resume,
1231#endif
1232};
1233
1234#endif /* PCI */
1235
1236
1237#define DRIVER_INFO DRIVER_VERSION " " DRIVER_DESC
1238
1239MODULE_DESCRIPTION (DRIVER_INFO);
1240MODULE_AUTHOR (DRIVER_AUTHOR);
1241MODULE_LICENSE ("GPL");
1242
1243static int __init init (void)
1244{
1245 if (usb_disabled())
1246 return -ENODEV;
1247
1248 pr_debug ("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n",
1249 hcd_name,
1250 sizeof (struct ehci_qh), sizeof (struct ehci_qtd),
1251 sizeof (struct ehci_itd), sizeof (struct ehci_sitd));
1252
1253 return pci_register_driver (&ehci_pci_driver);
1254}
1255module_init (init);
1256
1257static void __exit cleanup (void)
1258{
1259 pci_unregister_driver (&ehci_pci_driver);
1260}
1261module_exit (cleanup);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-15 18:43:37 -0500