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path: root/drivers/usb/host/ehci-fsl.c
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Diffstat (limited to 'drivers/usb/host/ehci-fsl.c')
-rw-r--r--drivers/usb/host/ehci-fsl.c315
1 files changed, 281 insertions, 34 deletions
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index a416421abfa2..f380bf97e5af 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -52,7 +52,6 @@ static int usb_hcd_fsl_probe(const struct hc_driver *driver,
52 struct resource *res; 52 struct resource *res;
53 int irq; 53 int irq;
54 int retval; 54 int retval;
55 unsigned int temp;
56 55
57 pr_debug("initializing FSL-SOC USB Controller\n"); 56 pr_debug("initializing FSL-SOC USB Controller\n");
58 57
@@ -116,17 +115,52 @@ static int usb_hcd_fsl_probe(const struct hc_driver *driver,
116 goto err3; 115 goto err3;
117 } 116 }
118 117
119 /* Enable USB controller */ 118 pdata->regs = hcd->regs;
120 temp = in_be32(hcd->regs + 0x500);
121 out_be32(hcd->regs + 0x500, temp | 0x4);
122 119
123 /* Set to Host mode */ 120 if (pdata->power_budget)
124 temp = in_le32(hcd->regs + 0x1a8); 121 hcd->power_budget = pdata->power_budget;
125 out_le32(hcd->regs + 0x1a8, temp | 0x3); 122
123 /*
124 * do platform specific init: check the clock, grab/config pins, etc.
125 */
126 if (pdata->init && pdata->init(pdev)) {
127 retval = -ENODEV;
128 goto err3;
129 }
130
131 /* Enable USB controller, 83xx or 8536 */
132 if (pdata->have_sysif_regs)
133 setbits32(hcd->regs + FSL_SOC_USB_CTRL, 0x4);
134
135 /* Don't need to set host mode here. It will be done by tdi_reset() */
126 136
127 retval = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED); 137 retval = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED);
128 if (retval != 0) 138 if (retval != 0)
129 goto err4; 139 goto err4;
140
141#ifdef CONFIG_USB_OTG
142 if (pdata->operating_mode == FSL_USB2_DR_OTG) {
143 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
144
145 ehci->transceiver = otg_get_transceiver();
146 dev_dbg(&pdev->dev, "hcd=0x%p ehci=0x%p, transceiver=0x%p\n",
147 hcd, ehci, ehci->transceiver);
148
149 if (ehci->transceiver) {
150 retval = otg_set_host(ehci->transceiver,
151 &ehci_to_hcd(ehci)->self);
152 if (retval) {
153 if (ehci->transceiver)
154 put_device(ehci->transceiver->dev);
155 goto err4;
156 }
157 } else {
158 dev_err(&pdev->dev, "can't find transceiver\n");
159 retval = -ENODEV;
160 goto err4;
161 }
162 }
163#endif
130 return retval; 164 return retval;
131 165
132 err4: 166 err4:
@@ -137,6 +171,8 @@ static int usb_hcd_fsl_probe(const struct hc_driver *driver,
137 usb_put_hcd(hcd); 171 usb_put_hcd(hcd);
138 err1: 172 err1:
139 dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), retval); 173 dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), retval);
174 if (pdata->exit)
175 pdata->exit(pdev);
140 return retval; 176 return retval;
141} 177}
142 178
@@ -154,17 +190,36 @@ static int usb_hcd_fsl_probe(const struct hc_driver *driver,
154static void usb_hcd_fsl_remove(struct usb_hcd *hcd, 190static void usb_hcd_fsl_remove(struct usb_hcd *hcd,
155 struct platform_device *pdev) 191 struct platform_device *pdev)
156{ 192{
193 struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
194 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
195
196 if (ehci->transceiver) {
197 otg_set_host(ehci->transceiver, NULL);
198 put_device(ehci->transceiver->dev);
199 }
200
157 usb_remove_hcd(hcd); 201 usb_remove_hcd(hcd);
202
203 /*
204 * do platform specific un-initialization:
205 * release iomux pins, disable clock, etc.
206 */
207 if (pdata->exit)
208 pdata->exit(pdev);
158 iounmap(hcd->regs); 209 iounmap(hcd->regs);
159 release_mem_region(hcd->rsrc_start, hcd->rsrc_len); 210 release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
160 usb_put_hcd(hcd); 211 usb_put_hcd(hcd);
161} 212}
162 213
163static void mpc83xx_setup_phy(struct ehci_hcd *ehci, 214static void ehci_fsl_setup_phy(struct ehci_hcd *ehci,
164 enum fsl_usb2_phy_modes phy_mode, 215 enum fsl_usb2_phy_modes phy_mode,
165 unsigned int port_offset) 216 unsigned int port_offset)
166{ 217{
167 u32 portsc = 0; 218 u32 portsc;
219
220 portsc = ehci_readl(ehci, &ehci->regs->port_status[port_offset]);
221 portsc &= ~(PORT_PTS_MSK | PORT_PTS_PTW);
222
168 switch (phy_mode) { 223 switch (phy_mode) {
169 case FSL_USB2_PHY_ULPI: 224 case FSL_USB2_PHY_ULPI:
170 portsc |= PORT_PTS_ULPI; 225 portsc |= PORT_PTS_ULPI;
@@ -184,20 +239,21 @@ static void mpc83xx_setup_phy(struct ehci_hcd *ehci,
184 ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]); 239 ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]);
185} 240}
186 241
187static void mpc83xx_usb_setup(struct usb_hcd *hcd) 242static void ehci_fsl_usb_setup(struct ehci_hcd *ehci)
188{ 243{
189 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 244 struct usb_hcd *hcd = ehci_to_hcd(ehci);
190 struct fsl_usb2_platform_data *pdata; 245 struct fsl_usb2_platform_data *pdata;
191 void __iomem *non_ehci = hcd->regs; 246 void __iomem *non_ehci = hcd->regs;
192 u32 temp; 247 u32 temp;
193 248
194 pdata = 249 pdata = hcd->self.controller->platform_data;
195 (struct fsl_usb2_platform_data *)hcd->self.controller-> 250
196 platform_data;
197 /* Enable PHY interface in the control reg. */ 251 /* Enable PHY interface in the control reg. */
198 temp = in_be32(non_ehci + FSL_SOC_USB_CTRL); 252 if (pdata->have_sysif_regs) {
199 out_be32(non_ehci + FSL_SOC_USB_CTRL, temp | 0x00000004); 253 temp = in_be32(non_ehci + FSL_SOC_USB_CTRL);
200 out_be32(non_ehci + FSL_SOC_USB_SNOOP1, 0x0000001b); 254 out_be32(non_ehci + FSL_SOC_USB_CTRL, temp | 0x00000004);
255 out_be32(non_ehci + FSL_SOC_USB_SNOOP1, 0x0000001b);
256 }
201 257
202#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) 258#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
203 /* 259 /*
@@ -214,7 +270,7 @@ static void mpc83xx_usb_setup(struct usb_hcd *hcd)
214 270
215 if ((pdata->operating_mode == FSL_USB2_DR_HOST) || 271 if ((pdata->operating_mode == FSL_USB2_DR_HOST) ||
216 (pdata->operating_mode == FSL_USB2_DR_OTG)) 272 (pdata->operating_mode == FSL_USB2_DR_OTG))
217 mpc83xx_setup_phy(ehci, pdata->phy_mode, 0); 273 ehci_fsl_setup_phy(ehci, pdata->phy_mode, 0);
218 274
219 if (pdata->operating_mode == FSL_USB2_MPH_HOST) { 275 if (pdata->operating_mode == FSL_USB2_MPH_HOST) {
220 unsigned int chip, rev, svr; 276 unsigned int chip, rev, svr;
@@ -228,27 +284,27 @@ static void mpc83xx_usb_setup(struct usb_hcd *hcd)
228 ehci->has_fsl_port_bug = 1; 284 ehci->has_fsl_port_bug = 1;
229 285
230 if (pdata->port_enables & FSL_USB2_PORT0_ENABLED) 286 if (pdata->port_enables & FSL_USB2_PORT0_ENABLED)
231 mpc83xx_setup_phy(ehci, pdata->phy_mode, 0); 287 ehci_fsl_setup_phy(ehci, pdata->phy_mode, 0);
232 if (pdata->port_enables & FSL_USB2_PORT1_ENABLED) 288 if (pdata->port_enables & FSL_USB2_PORT1_ENABLED)
233 mpc83xx_setup_phy(ehci, pdata->phy_mode, 1); 289 ehci_fsl_setup_phy(ehci, pdata->phy_mode, 1);
234 } 290 }
235 291
236 /* put controller in host mode. */ 292 if (pdata->have_sysif_regs) {
237 ehci_writel(ehci, 0x00000003, non_ehci + FSL_SOC_USB_USBMODE);
238#ifdef CONFIG_PPC_85xx 293#ifdef CONFIG_PPC_85xx
239 out_be32(non_ehci + FSL_SOC_USB_PRICTRL, 0x00000008); 294 out_be32(non_ehci + FSL_SOC_USB_PRICTRL, 0x00000008);
240 out_be32(non_ehci + FSL_SOC_USB_AGECNTTHRSH, 0x00000080); 295 out_be32(non_ehci + FSL_SOC_USB_AGECNTTHRSH, 0x00000080);
241#else 296#else
242 out_be32(non_ehci + FSL_SOC_USB_PRICTRL, 0x0000000c); 297 out_be32(non_ehci + FSL_SOC_USB_PRICTRL, 0x0000000c);
243 out_be32(non_ehci + FSL_SOC_USB_AGECNTTHRSH, 0x00000040); 298 out_be32(non_ehci + FSL_SOC_USB_AGECNTTHRSH, 0x00000040);
244#endif 299#endif
245 out_be32(non_ehci + FSL_SOC_USB_SICTRL, 0x00000001); 300 out_be32(non_ehci + FSL_SOC_USB_SICTRL, 0x00000001);
301 }
246} 302}
247 303
248/* called after powerup, by probe or system-pm "wakeup" */ 304/* called after powerup, by probe or system-pm "wakeup" */
249static int ehci_fsl_reinit(struct ehci_hcd *ehci) 305static int ehci_fsl_reinit(struct ehci_hcd *ehci)
250{ 306{
251 mpc83xx_usb_setup(ehci_to_hcd(ehci)); 307 ehci_fsl_usb_setup(ehci);
252 ehci_port_power(ehci, 0); 308 ehci_port_power(ehci, 0);
253 309
254 return 0; 310 return 0;
@@ -259,17 +315,24 @@ static int ehci_fsl_setup(struct usb_hcd *hcd)
259{ 315{
260 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 316 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
261 int retval; 317 int retval;
318 struct fsl_usb2_platform_data *pdata;
319
320 pdata = hcd->self.controller->platform_data;
321 ehci->big_endian_desc = pdata->big_endian_desc;
322 ehci->big_endian_mmio = pdata->big_endian_mmio;
262 323
263 /* EHCI registers start at offset 0x100 */ 324 /* EHCI registers start at offset 0x100 */
264 ehci->caps = hcd->regs + 0x100; 325 ehci->caps = hcd->regs + 0x100;
265 ehci->regs = hcd->regs + 0x100 + 326 ehci->regs = hcd->regs + 0x100 +
266 HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); 327 HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
267 dbg_hcs_params(ehci, "reset"); 328 dbg_hcs_params(ehci, "reset");
268 dbg_hcc_params(ehci, "reset"); 329 dbg_hcc_params(ehci, "reset");
269 330
270 /* cache this readonly data; minimize chip reads */ 331 /* cache this readonly data; minimize chip reads */
271 ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); 332 ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
272 333
334 hcd->has_tt = 1;
335
273 retval = ehci_halt(ehci); 336 retval = ehci_halt(ehci);
274 if (retval) 337 if (retval)
275 return retval; 338 return retval;
@@ -279,8 +342,6 @@ static int ehci_fsl_setup(struct usb_hcd *hcd)
279 if (retval) 342 if (retval)
280 return retval; 343 return retval;
281 344
282 hcd->has_tt = 1;
283
284 ehci->sbrn = 0x20; 345 ehci->sbrn = 0x20;
285 346
286 ehci_reset(ehci); 347 ehci_reset(ehci);
@@ -300,6 +361,149 @@ struct ehci_fsl {
300 361
301#ifdef CONFIG_PM 362#ifdef CONFIG_PM
302 363
364#ifdef CONFIG_PPC_MPC512x
365static int ehci_fsl_mpc512x_drv_suspend(struct device *dev)
366{
367 struct usb_hcd *hcd = dev_get_drvdata(dev);
368 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
369 struct fsl_usb2_platform_data *pdata = dev->platform_data;
370 u32 tmp;
371
372#ifdef DEBUG
373 u32 mode = ehci_readl(ehci, hcd->regs + FSL_SOC_USB_USBMODE);
374 mode &= USBMODE_CM_MASK;
375 tmp = ehci_readl(ehci, hcd->regs + 0x140); /* usbcmd */
376
377 dev_dbg(dev, "suspend=%d already_suspended=%d "
378 "mode=%d usbcmd %08x\n", pdata->suspended,
379 pdata->already_suspended, mode, tmp);
380#endif
381
382 /*
383 * If the controller is already suspended, then this must be a
384 * PM suspend. Remember this fact, so that we will leave the
385 * controller suspended at PM resume time.
386 */
387 if (pdata->suspended) {
388 dev_dbg(dev, "already suspended, leaving early\n");
389 pdata->already_suspended = 1;
390 return 0;
391 }
392
393 dev_dbg(dev, "suspending...\n");
394
395 hcd->state = HC_STATE_SUSPENDED;
396 dev->power.power_state = PMSG_SUSPEND;
397
398 /* ignore non-host interrupts */
399 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
400
401 /* stop the controller */
402 tmp = ehci_readl(ehci, &ehci->regs->command);
403 tmp &= ~CMD_RUN;
404 ehci_writel(ehci, tmp, &ehci->regs->command);
405
406 /* save EHCI registers */
407 pdata->pm_command = ehci_readl(ehci, &ehci->regs->command);
408 pdata->pm_command &= ~CMD_RUN;
409 pdata->pm_status = ehci_readl(ehci, &ehci->regs->status);
410 pdata->pm_intr_enable = ehci_readl(ehci, &ehci->regs->intr_enable);
411 pdata->pm_frame_index = ehci_readl(ehci, &ehci->regs->frame_index);
412 pdata->pm_segment = ehci_readl(ehci, &ehci->regs->segment);
413 pdata->pm_frame_list = ehci_readl(ehci, &ehci->regs->frame_list);
414 pdata->pm_async_next = ehci_readl(ehci, &ehci->regs->async_next);
415 pdata->pm_configured_flag =
416 ehci_readl(ehci, &ehci->regs->configured_flag);
417 pdata->pm_portsc = ehci_readl(ehci, &ehci->regs->port_status[0]);
418 pdata->pm_usbgenctrl = ehci_readl(ehci,
419 hcd->regs + FSL_SOC_USB_USBGENCTRL);
420
421 /* clear the W1C bits */
422 pdata->pm_portsc &= cpu_to_hc32(ehci, ~PORT_RWC_BITS);
423
424 pdata->suspended = 1;
425
426 /* clear PP to cut power to the port */
427 tmp = ehci_readl(ehci, &ehci->regs->port_status[0]);
428 tmp &= ~PORT_POWER;
429 ehci_writel(ehci, tmp, &ehci->regs->port_status[0]);
430
431 return 0;
432}
433
434static int ehci_fsl_mpc512x_drv_resume(struct device *dev)
435{
436 struct usb_hcd *hcd = dev_get_drvdata(dev);
437 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
438 struct fsl_usb2_platform_data *pdata = dev->platform_data;
439 u32 tmp;
440
441 dev_dbg(dev, "suspend=%d already_suspended=%d\n",
442 pdata->suspended, pdata->already_suspended);
443
444 /*
445 * If the controller was already suspended at suspend time,
446 * then don't resume it now.
447 */
448 if (pdata->already_suspended) {
449 dev_dbg(dev, "already suspended, leaving early\n");
450 pdata->already_suspended = 0;
451 return 0;
452 }
453
454 if (!pdata->suspended) {
455 dev_dbg(dev, "not suspended, leaving early\n");
456 return 0;
457 }
458
459 pdata->suspended = 0;
460
461 dev_dbg(dev, "resuming...\n");
462
463 /* set host mode */
464 tmp = USBMODE_CM_HOST | (pdata->es ? USBMODE_ES : 0);
465 ehci_writel(ehci, tmp, hcd->regs + FSL_SOC_USB_USBMODE);
466
467 ehci_writel(ehci, pdata->pm_usbgenctrl,
468 hcd->regs + FSL_SOC_USB_USBGENCTRL);
469 ehci_writel(ehci, ISIPHYCTRL_PXE | ISIPHYCTRL_PHYE,
470 hcd->regs + FSL_SOC_USB_ISIPHYCTRL);
471
472 /* restore EHCI registers */
473 ehci_writel(ehci, pdata->pm_command, &ehci->regs->command);
474 ehci_writel(ehci, pdata->pm_intr_enable, &ehci->regs->intr_enable);
475 ehci_writel(ehci, pdata->pm_frame_index, &ehci->regs->frame_index);
476 ehci_writel(ehci, pdata->pm_segment, &ehci->regs->segment);
477 ehci_writel(ehci, pdata->pm_frame_list, &ehci->regs->frame_list);
478 ehci_writel(ehci, pdata->pm_async_next, &ehci->regs->async_next);
479 ehci_writel(ehci, pdata->pm_configured_flag,
480 &ehci->regs->configured_flag);
481 ehci_writel(ehci, pdata->pm_portsc, &ehci->regs->port_status[0]);
482
483 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
484 hcd->state = HC_STATE_RUNNING;
485 dev->power.power_state = PMSG_ON;
486
487 tmp = ehci_readl(ehci, &ehci->regs->command);
488 tmp |= CMD_RUN;
489 ehci_writel(ehci, tmp, &ehci->regs->command);
490
491 usb_hcd_resume_root_hub(hcd);
492
493 return 0;
494}
495#else
496static inline int ehci_fsl_mpc512x_drv_suspend(struct device *dev)
497{
498 return 0;
499}
500
501static inline int ehci_fsl_mpc512x_drv_resume(struct device *dev)
502{
503 return 0;
504}
505#endif /* CONFIG_PPC_MPC512x */
506
303static struct ehci_fsl *hcd_to_ehci_fsl(struct usb_hcd *hcd) 507static struct ehci_fsl *hcd_to_ehci_fsl(struct usb_hcd *hcd)
304{ 508{
305 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 509 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
@@ -313,6 +517,11 @@ static int ehci_fsl_drv_suspend(struct device *dev)
313 struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd); 517 struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
314 void __iomem *non_ehci = hcd->regs; 518 void __iomem *non_ehci = hcd->regs;
315 519
520 if (of_device_is_compatible(dev->parent->of_node,
521 "fsl,mpc5121-usb2-dr")) {
522 return ehci_fsl_mpc512x_drv_suspend(dev);
523 }
524
316 ehci_prepare_ports_for_controller_suspend(hcd_to_ehci(hcd), 525 ehci_prepare_ports_for_controller_suspend(hcd_to_ehci(hcd),
317 device_may_wakeup(dev)); 526 device_may_wakeup(dev));
318 if (!fsl_deep_sleep()) 527 if (!fsl_deep_sleep())
@@ -329,6 +538,11 @@ static int ehci_fsl_drv_resume(struct device *dev)
329 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 538 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
330 void __iomem *non_ehci = hcd->regs; 539 void __iomem *non_ehci = hcd->regs;
331 540
541 if (of_device_is_compatible(dev->parent->of_node,
542 "fsl,mpc5121-usb2-dr")) {
543 return ehci_fsl_mpc512x_drv_resume(dev);
544 }
545
332 ehci_prepare_ports_for_controller_resume(ehci); 546 ehci_prepare_ports_for_controller_resume(ehci);
333 if (!fsl_deep_sleep()) 547 if (!fsl_deep_sleep())
334 return 0; 548 return 0;
@@ -363,6 +577,38 @@ static struct dev_pm_ops ehci_fsl_pm_ops = {
363#define EHCI_FSL_PM_OPS NULL 577#define EHCI_FSL_PM_OPS NULL
364#endif /* CONFIG_PM */ 578#endif /* CONFIG_PM */
365 579
580#ifdef CONFIG_USB_OTG
581static int ehci_start_port_reset(struct usb_hcd *hcd, unsigned port)
582{
583 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
584 u32 status;
585
586 if (!port)
587 return -EINVAL;
588
589 port--;
590
591 /* start port reset before HNP protocol time out */
592 status = readl(&ehci->regs->port_status[port]);
593 if (!(status & PORT_CONNECT))
594 return -ENODEV;
595
596 /* khubd will finish the reset later */
597 if (ehci_is_TDI(ehci)) {
598 writel(PORT_RESET |
599 (status & ~(PORT_CSC | PORT_PEC | PORT_OCC)),
600 &ehci->regs->port_status[port]);
601 } else {
602 writel(PORT_RESET, &ehci->regs->port_status[port]);
603 }
604
605 return 0;
606}
607#else
608#define ehci_start_port_reset NULL
609#endif /* CONFIG_USB_OTG */
610
611
366static const struct hc_driver ehci_fsl_hc_driver = { 612static const struct hc_driver ehci_fsl_hc_driver = {
367 .description = hcd_name, 613 .description = hcd_name,
368 .product_desc = "Freescale On-Chip EHCI Host Controller", 614 .product_desc = "Freescale On-Chip EHCI Host Controller",
@@ -372,7 +618,7 @@ static const struct hc_driver ehci_fsl_hc_driver = {
372 * generic hardware linkage 618 * generic hardware linkage
373 */ 619 */
374 .irq = ehci_irq, 620 .irq = ehci_irq,
375 .flags = HCD_USB2, 621 .flags = HCD_USB2 | HCD_MEMORY,
376 622
377 /* 623 /*
378 * basic lifecycle operations 624 * basic lifecycle operations
@@ -402,6 +648,7 @@ static const struct hc_driver ehci_fsl_hc_driver = {
402 .hub_control = ehci_hub_control, 648 .hub_control = ehci_hub_control,
403 .bus_suspend = ehci_bus_suspend, 649 .bus_suspend = ehci_bus_suspend,
404 .bus_resume = ehci_bus_resume, 650 .bus_resume = ehci_bus_resume,
651 .start_port_reset = ehci_start_port_reset,
405 .relinquish_port = ehci_relinquish_port, 652 .relinquish_port = ehci_relinquish_port,
406 .port_handed_over = ehci_port_handed_over, 653 .port_handed_over = ehci_port_handed_over,
407 654