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path: root/drivers/usb/gadget/omap_udc.c
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Diffstat (limited to 'drivers/usb/gadget/omap_udc.c')
-rw-r--r--drivers/usb/gadget/omap_udc.c510
1 files changed, 267 insertions, 243 deletions
diff --git a/drivers/usb/gadget/omap_udc.c b/drivers/usb/gadget/omap_udc.c
index 881d74c3d964..03a7f49d207d 100644
--- a/drivers/usb/gadget/omap_udc.c
+++ b/drivers/usb/gadget/omap_udc.c
@@ -135,13 +135,17 @@ static void use_ep(struct omap_ep *ep, u16 select)
135 135
136 if (ep->bEndpointAddress & USB_DIR_IN) 136 if (ep->bEndpointAddress & USB_DIR_IN)
137 num |= UDC_EP_DIR; 137 num |= UDC_EP_DIR;
138 UDC_EP_NUM_REG = num | select; 138 omap_writew(num | select, UDC_EP_NUM);
139 /* when select, MUST deselect later !! */ 139 /* when select, MUST deselect later !! */
140} 140}
141 141
142static inline void deselect_ep(void) 142static inline void deselect_ep(void)
143{ 143{
144 UDC_EP_NUM_REG &= ~UDC_EP_SEL; 144 u16 w;
145
146 w = omap_readw(UDC_EP_NUM);
147 w &= ~UDC_EP_SEL;
148 omap_writew(w, UDC_EP_NUM);
145 /* 6 wait states before TX will happen */ 149 /* 6 wait states before TX will happen */
146} 150}
147 151
@@ -216,7 +220,7 @@ static int omap_ep_enable(struct usb_ep *_ep,
216 ep->has_dma = 0; 220 ep->has_dma = 0;
217 ep->lch = -1; 221 ep->lch = -1;
218 use_ep(ep, UDC_EP_SEL); 222 use_ep(ep, UDC_EP_SEL);
219 UDC_CTRL_REG = udc->clr_halt; 223 omap_writew(udc->clr_halt, UDC_CTRL);
220 ep->ackwait = 0; 224 ep->ackwait = 0;
221 deselect_ep(); 225 deselect_ep();
222 226
@@ -232,7 +236,7 @@ static int omap_ep_enable(struct usb_ep *_ep,
232 if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC 236 if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC
233 && !ep->has_dma 237 && !ep->has_dma
234 && !(ep->bEndpointAddress & USB_DIR_IN)) { 238 && !(ep->bEndpointAddress & USB_DIR_IN)) {
235 UDC_CTRL_REG = UDC_SET_FIFO_EN; 239 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
236 ep->ackwait = 1 + ep->double_buf; 240 ep->ackwait = 1 + ep->double_buf;
237 } 241 }
238 242
@@ -259,7 +263,7 @@ static int omap_ep_disable(struct usb_ep *_ep)
259 nuke (ep, -ESHUTDOWN); 263 nuke (ep, -ESHUTDOWN);
260 ep->ep.maxpacket = ep->maxpacket; 264 ep->ep.maxpacket = ep->maxpacket;
261 ep->has_dma = 0; 265 ep->has_dma = 0;
262 UDC_CTRL_REG = UDC_SET_HALT; 266 omap_writew(UDC_SET_HALT, UDC_CTRL);
263 list_del_init(&ep->iso); 267 list_del_init(&ep->iso);
264 del_timer(&ep->timer); 268 del_timer(&ep->timer);
265 269
@@ -360,13 +364,13 @@ write_packet(u8 *buf, struct omap_req *req, unsigned max)
360 if (likely((((int)buf) & 1) == 0)) { 364 if (likely((((int)buf) & 1) == 0)) {
361 wp = (u16 *)buf; 365 wp = (u16 *)buf;
362 while (max >= 2) { 366 while (max >= 2) {
363 UDC_DATA_REG = *wp++; 367 omap_writew(*wp++, UDC_DATA);
364 max -= 2; 368 max -= 2;
365 } 369 }
366 buf = (u8 *)wp; 370 buf = (u8 *)wp;
367 } 371 }
368 while (max--) 372 while (max--)
369 *(volatile u8 *)&UDC_DATA_REG = *buf++; 373 omap_writeb(*buf++, UDC_DATA);
370 return len; 374 return len;
371} 375}
372 376
@@ -385,13 +389,13 @@ static int write_fifo(struct omap_ep *ep, struct omap_req *req)
385 prefetch(buf); 389 prefetch(buf);
386 390
387 /* PIO-IN isn't double buffered except for iso */ 391 /* PIO-IN isn't double buffered except for iso */
388 ep_stat = UDC_STAT_FLG_REG; 392 ep_stat = omap_readw(UDC_STAT_FLG);
389 if (ep_stat & UDC_FIFO_UNWRITABLE) 393 if (ep_stat & UDC_FIFO_UNWRITABLE)
390 return 0; 394 return 0;
391 395
392 count = ep->ep.maxpacket; 396 count = ep->ep.maxpacket;
393 count = write_packet(buf, req, count); 397 count = write_packet(buf, req, count);
394 UDC_CTRL_REG = UDC_SET_FIFO_EN; 398 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
395 ep->ackwait = 1; 399 ep->ackwait = 1;
396 400
397 /* last packet is often short (sometimes a zlp) */ 401 /* last packet is often short (sometimes a zlp) */
@@ -425,13 +429,13 @@ read_packet(u8 *buf, struct omap_req *req, unsigned avail)
425 if (likely((((int)buf) & 1) == 0)) { 429 if (likely((((int)buf) & 1) == 0)) {
426 wp = (u16 *)buf; 430 wp = (u16 *)buf;
427 while (avail >= 2) { 431 while (avail >= 2) {
428 *wp++ = UDC_DATA_REG; 432 *wp++ = omap_readw(UDC_DATA);
429 avail -= 2; 433 avail -= 2;
430 } 434 }
431 buf = (u8 *)wp; 435 buf = (u8 *)wp;
432 } 436 }
433 while (avail--) 437 while (avail--)
434 *buf++ = *(volatile u8 *)&UDC_DATA_REG; 438 *buf++ = omap_readb(UDC_DATA);
435 return len; 439 return len;
436} 440}
437 441
@@ -446,7 +450,7 @@ static int read_fifo(struct omap_ep *ep, struct omap_req *req)
446 prefetchw(buf); 450 prefetchw(buf);
447 451
448 for (;;) { 452 for (;;) {
449 u16 ep_stat = UDC_STAT_FLG_REG; 453 u16 ep_stat = omap_readw(UDC_STAT_FLG);
450 454
451 is_last = 0; 455 is_last = 0;
452 if (ep_stat & FIFO_EMPTY) { 456 if (ep_stat & FIFO_EMPTY) {
@@ -460,7 +464,7 @@ static int read_fifo(struct omap_ep *ep, struct omap_req *req)
460 if (ep_stat & UDC_FIFO_FULL) 464 if (ep_stat & UDC_FIFO_FULL)
461 avail = ep->ep.maxpacket; 465 avail = ep->ep.maxpacket;
462 else { 466 else {
463 avail = UDC_RXFSTAT_REG; 467 avail = omap_readw(UDC_RXFSTAT);
464 ep->fnf = ep->double_buf; 468 ep->fnf = ep->double_buf;
465 } 469 }
466 count = read_packet(buf, req, avail); 470 count = read_packet(buf, req, avail);
@@ -473,7 +477,7 @@ static int read_fifo(struct omap_ep *ep, struct omap_req *req)
473 req->req.status = -EOVERFLOW; 477 req->req.status = -EOVERFLOW;
474 avail -= count; 478 avail -= count;
475 while (avail--) 479 while (avail--)
476 (void) *(volatile u8 *)&UDC_DATA_REG; 480 omap_readw(UDC_DATA);
477 } 481 }
478 } else if (req->req.length == req->req.actual) 482 } else if (req->req.length == req->req.actual)
479 is_last = 1; 483 is_last = 1;
@@ -491,32 +495,6 @@ static int read_fifo(struct omap_ep *ep, struct omap_req *req)
491 495
492/*-------------------------------------------------------------------------*/ 496/*-------------------------------------------------------------------------*/
493 497
494static inline dma_addr_t dma_csac(unsigned lch)
495{
496 dma_addr_t csac;
497
498 /* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
499 * read before the DMA controller finished disabling the channel.
500 */
501 csac = OMAP_DMA_CSAC_REG(lch);
502 if (csac == 0)
503 csac = OMAP_DMA_CSAC_REG(lch);
504 return csac;
505}
506
507static inline dma_addr_t dma_cdac(unsigned lch)
508{
509 dma_addr_t cdac;
510
511 /* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
512 * read before the DMA controller finished disabling the channel.
513 */
514 cdac = OMAP_DMA_CDAC_REG(lch);
515 if (cdac == 0)
516 cdac = OMAP_DMA_CDAC_REG(lch);
517 return cdac;
518}
519
520static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start) 498static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
521{ 499{
522 dma_addr_t end; 500 dma_addr_t end;
@@ -527,7 +505,7 @@ static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
527 if (cpu_is_omap15xx()) 505 if (cpu_is_omap15xx())
528 return 0; 506 return 0;
529 507
530 end = dma_csac(ep->lch); 508 end = omap_get_dma_src_pos(ep->lch);
531 if (end == ep->dma_counter) 509 if (end == ep->dma_counter)
532 return 0; 510 return 0;
533 511
@@ -537,15 +515,11 @@ static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
537 return end - start; 515 return end - start;
538} 516}
539 517
540#define DMA_DEST_LAST(x) (cpu_is_omap15xx() \
541 ? OMAP_DMA_CSAC_REG(x) /* really: CPC */ \
542 : dma_cdac(x))
543
544static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start) 518static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start)
545{ 519{
546 dma_addr_t end; 520 dma_addr_t end;
547 521
548 end = DMA_DEST_LAST(ep->lch); 522 end = omap_get_dma_dst_pos(ep->lch);
549 if (end == ep->dma_counter) 523 if (end == ep->dma_counter)
550 return 0; 524 return 0;
551 525
@@ -565,7 +539,7 @@ static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start)
565 539
566static void next_in_dma(struct omap_ep *ep, struct omap_req *req) 540static void next_in_dma(struct omap_ep *ep, struct omap_req *req)
567{ 541{
568 u16 txdma_ctrl; 542 u16 txdma_ctrl, w;
569 unsigned length = req->req.length - req->req.actual; 543 unsigned length = req->req.length - req->req.actual;
570 const int sync_mode = cpu_is_omap15xx() 544 const int sync_mode = cpu_is_omap15xx()
571 ? OMAP_DMA_SYNC_FRAME 545 ? OMAP_DMA_SYNC_FRAME
@@ -596,14 +570,18 @@ static void next_in_dma(struct omap_ep *ep, struct omap_req *req)
596 0, 0); 570 0, 0);
597 571
598 omap_start_dma(ep->lch); 572 omap_start_dma(ep->lch);
599 ep->dma_counter = dma_csac(ep->lch); 573 ep->dma_counter = omap_get_dma_src_pos(ep->lch);
600 UDC_DMA_IRQ_EN_REG |= UDC_TX_DONE_IE(ep->dma_channel); 574 w = omap_readw(UDC_DMA_IRQ_EN);
601 UDC_TXDMA_REG(ep->dma_channel) = UDC_TXN_START | txdma_ctrl; 575 w |= UDC_TX_DONE_IE(ep->dma_channel);
576 omap_writew(w, UDC_DMA_IRQ_EN);
577 omap_writew(UDC_TXN_START | txdma_ctrl, UDC_TXDMA(ep->dma_channel));
602 req->dma_bytes = length; 578 req->dma_bytes = length;
603} 579}
604 580
605static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status) 581static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status)
606{ 582{
583 u16 w;
584
607 if (status == 0) { 585 if (status == 0) {
608 req->req.actual += req->dma_bytes; 586 req->req.actual += req->dma_bytes;
609 587
@@ -620,7 +598,9 @@ static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status)
620 598
621 /* tx completion */ 599 /* tx completion */
622 omap_stop_dma(ep->lch); 600 omap_stop_dma(ep->lch);
623 UDC_DMA_IRQ_EN_REG &= ~UDC_TX_DONE_IE(ep->dma_channel); 601 w = omap_readw(UDC_DMA_IRQ_EN);
602 w &= ~UDC_TX_DONE_IE(ep->dma_channel);
603 omap_writew(w, UDC_DMA_IRQ_EN);
624 done(ep, req, status); 604 done(ep, req, status);
625} 605}
626 606
@@ -628,6 +608,7 @@ static void next_out_dma(struct omap_ep *ep, struct omap_req *req)
628{ 608{
629 unsigned packets = req->req.length - req->req.actual; 609 unsigned packets = req->req.length - req->req.actual;
630 int dma_trigger = 0; 610 int dma_trigger = 0;
611 u16 w;
631 612
632 if (cpu_is_omap24xx()) 613 if (cpu_is_omap24xx())
633 dma_trigger = OMAP24XX_DMA(USB_W2FC_RX0, ep->dma_channel); 614 dma_trigger = OMAP24XX_DMA(USB_W2FC_RX0, ep->dma_channel);
@@ -654,12 +635,14 @@ static void next_out_dma(struct omap_ep *ep, struct omap_req *req)
654 omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF, 635 omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF,
655 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual, 636 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
656 0, 0); 637 0, 0);
657 ep->dma_counter = DMA_DEST_LAST(ep->lch); 638 ep->dma_counter = omap_get_dma_dst_pos(ep->lch);
658 639
659 UDC_RXDMA_REG(ep->dma_channel) = UDC_RXN_STOP | (packets - 1); 640 omap_writew(UDC_RXN_STOP | (packets - 1), UDC_RXDMA(ep->dma_channel));
660 UDC_DMA_IRQ_EN_REG |= UDC_RX_EOT_IE(ep->dma_channel); 641 w = omap_readw(UDC_DMA_IRQ_EN);
661 UDC_EP_NUM_REG = (ep->bEndpointAddress & 0xf); 642 w |= UDC_RX_EOT_IE(ep->dma_channel);
662 UDC_CTRL_REG = UDC_SET_FIFO_EN; 643 omap_writew(w, UDC_DMA_IRQ_EN);
644 omap_writew(ep->bEndpointAddress & 0xf, UDC_EP_NUM);
645 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
663 646
664 omap_start_dma(ep->lch); 647 omap_start_dma(ep->lch);
665} 648}
@@ -667,7 +650,7 @@ static void next_out_dma(struct omap_ep *ep, struct omap_req *req)
667static void 650static void
668finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one) 651finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one)
669{ 652{
670 u16 count; 653 u16 count, w;
671 654
672 if (status == 0) 655 if (status == 0)
673 ep->dma_counter = (u16) (req->req.dma + req->req.actual); 656 ep->dma_counter = (u16) (req->req.dma + req->req.actual);
@@ -686,13 +669,15 @@ finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one)
686 return; 669 return;
687 670
688 /* rx completion */ 671 /* rx completion */
689 UDC_DMA_IRQ_EN_REG &= ~UDC_RX_EOT_IE(ep->dma_channel); 672 w = omap_readw(UDC_DMA_IRQ_EN);
673 w &= ~UDC_RX_EOT_IE(ep->dma_channel);
674 omap_writew(w, UDC_DMA_IRQ_EN);
690 done(ep, req, status); 675 done(ep, req, status);
691} 676}
692 677
693static void dma_irq(struct omap_udc *udc, u16 irq_src) 678static void dma_irq(struct omap_udc *udc, u16 irq_src)
694{ 679{
695 u16 dman_stat = UDC_DMAN_STAT_REG; 680 u16 dman_stat = omap_readw(UDC_DMAN_STAT);
696 struct omap_ep *ep; 681 struct omap_ep *ep;
697 struct omap_req *req; 682 struct omap_req *req;
698 683
@@ -706,7 +691,7 @@ static void dma_irq(struct omap_udc *udc, u16 irq_src)
706 struct omap_req, queue); 691 struct omap_req, queue);
707 finish_in_dma(ep, req, 0); 692 finish_in_dma(ep, req, 0);
708 } 693 }
709 UDC_IRQ_SRC_REG = UDC_TXN_DONE; 694 omap_writew(UDC_TXN_DONE, UDC_IRQ_SRC);
710 695
711 if (!list_empty (&ep->queue)) { 696 if (!list_empty (&ep->queue)) {
712 req = container_of(ep->queue.next, 697 req = container_of(ep->queue.next,
@@ -725,7 +710,7 @@ static void dma_irq(struct omap_udc *udc, u16 irq_src)
725 struct omap_req, queue); 710 struct omap_req, queue);
726 finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB); 711 finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB);
727 } 712 }
728 UDC_IRQ_SRC_REG = UDC_RXN_EOT; 713 omap_writew(UDC_RXN_EOT, UDC_IRQ_SRC);
729 714
730 if (!list_empty (&ep->queue)) { 715 if (!list_empty (&ep->queue)) {
731 req = container_of(ep->queue.next, 716 req = container_of(ep->queue.next,
@@ -739,7 +724,7 @@ static void dma_irq(struct omap_udc *udc, u16 irq_src)
739 ep->irqs++; 724 ep->irqs++;
740 /* omap15xx does this unasked... */ 725 /* omap15xx does this unasked... */
741 VDBG("%s, RX_CNT irq?\n", ep->ep.name); 726 VDBG("%s, RX_CNT irq?\n", ep->ep.name);
742 UDC_IRQ_SRC_REG = UDC_RXN_CNT; 727 omap_writew(UDC_RXN_CNT, UDC_IRQ_SRC);
743 } 728 }
744} 729}
745 730
@@ -762,9 +747,9 @@ static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
762 747
763 is_in = ep->bEndpointAddress & USB_DIR_IN; 748 is_in = ep->bEndpointAddress & USB_DIR_IN;
764 if (is_in) 749 if (is_in)
765 reg = UDC_TXDMA_CFG_REG; 750 reg = omap_readw(UDC_TXDMA_CFG);
766 else 751 else
767 reg = UDC_RXDMA_CFG_REG; 752 reg = omap_readw(UDC_RXDMA_CFG);
768 reg |= UDC_DMA_REQ; /* "pulse" activated */ 753 reg |= UDC_DMA_REQ; /* "pulse" activated */
769 754
770 ep->dma_channel = 0; 755 ep->dma_channel = 0;
@@ -792,7 +777,7 @@ static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
792 status = omap_request_dma(dma_channel, 777 status = omap_request_dma(dma_channel,
793 ep->ep.name, dma_error, ep, &ep->lch); 778 ep->ep.name, dma_error, ep, &ep->lch);
794 if (status == 0) { 779 if (status == 0) {
795 UDC_TXDMA_CFG_REG = reg; 780 omap_writew(reg, UDC_TXDMA_CFG);
796 /* EMIFF or SDRC */ 781 /* EMIFF or SDRC */
797 omap_set_dma_src_burst_mode(ep->lch, 782 omap_set_dma_src_burst_mode(ep->lch,
798 OMAP_DMA_DATA_BURST_4); 783 OMAP_DMA_DATA_BURST_4);
@@ -801,7 +786,7 @@ static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
801 omap_set_dma_dest_params(ep->lch, 786 omap_set_dma_dest_params(ep->lch,
802 OMAP_DMA_PORT_TIPB, 787 OMAP_DMA_PORT_TIPB,
803 OMAP_DMA_AMODE_CONSTANT, 788 OMAP_DMA_AMODE_CONSTANT,
804 (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG), 789 (unsigned long) io_v2p(UDC_DATA_DMA),
805 0, 0); 790 0, 0);
806 } 791 }
807 } else { 792 } else {
@@ -813,12 +798,12 @@ static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
813 status = omap_request_dma(dma_channel, 798 status = omap_request_dma(dma_channel,
814 ep->ep.name, dma_error, ep, &ep->lch); 799 ep->ep.name, dma_error, ep, &ep->lch);
815 if (status == 0) { 800 if (status == 0) {
816 UDC_RXDMA_CFG_REG = reg; 801 omap_writew(reg, UDC_RXDMA_CFG);
817 /* TIPB */ 802 /* TIPB */
818 omap_set_dma_src_params(ep->lch, 803 omap_set_dma_src_params(ep->lch,
819 OMAP_DMA_PORT_TIPB, 804 OMAP_DMA_PORT_TIPB,
820 OMAP_DMA_AMODE_CONSTANT, 805 OMAP_DMA_AMODE_CONSTANT,
821 (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG), 806 (unsigned long) io_v2p(UDC_DATA_DMA),
822 0, 0); 807 0, 0);
823 /* EMIFF or SDRC */ 808 /* EMIFF or SDRC */
824 omap_set_dma_dest_burst_mode(ep->lch, 809 omap_set_dma_dest_burst_mode(ep->lch,
@@ -834,7 +819,7 @@ static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
834 819
835 /* channel type P: hw synch (fifo) */ 820 /* channel type P: hw synch (fifo) */
836 if (cpu_class_is_omap1() && !cpu_is_omap15xx()) 821 if (cpu_class_is_omap1() && !cpu_is_omap15xx())
837 OMAP1_DMA_LCH_CTRL_REG(ep->lch) = 2; 822 omap_set_dma_channel_mode(ep->lch, OMAP_DMA_LCH_P);
838 } 823 }
839 824
840just_restart: 825just_restart:
@@ -860,7 +845,7 @@ just_restart:
860 (is_in ? write_fifo : read_fifo)(ep, req); 845 (is_in ? write_fifo : read_fifo)(ep, req);
861 deselect_ep(); 846 deselect_ep();
862 if (!is_in) { 847 if (!is_in) {
863 UDC_CTRL_REG = UDC_SET_FIFO_EN; 848 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
864 ep->ackwait = 1 + ep->double_buf; 849 ep->ackwait = 1 + ep->double_buf;
865 } 850 }
866 /* IN: 6 wait states before it'll tx */ 851 /* IN: 6 wait states before it'll tx */
@@ -881,7 +866,7 @@ static void dma_channel_release(struct omap_ep *ep)
881 else 866 else
882 req = NULL; 867 req = NULL;
883 868
884 active = ((1 << 7) & OMAP_DMA_CCR_REG(ep->lch)) != 0; 869 active = omap_get_dma_active_status(ep->lch);
885 870
886 DBG("%s release %s %cxdma%d %p\n", ep->ep.name, 871 DBG("%s release %s %cxdma%d %p\n", ep->ep.name,
887 active ? "active" : "idle", 872 active ? "active" : "idle",
@@ -894,23 +879,25 @@ static void dma_channel_release(struct omap_ep *ep)
894 879
895 /* wait till current packet DMA finishes, and fifo empties */ 880 /* wait till current packet DMA finishes, and fifo empties */
896 if (ep->bEndpointAddress & USB_DIR_IN) { 881 if (ep->bEndpointAddress & USB_DIR_IN) {
897 UDC_TXDMA_CFG_REG = (UDC_TXDMA_CFG_REG & ~mask) | UDC_DMA_REQ; 882 omap_writew((omap_readw(UDC_TXDMA_CFG) & ~mask) | UDC_DMA_REQ,
883 UDC_TXDMA_CFG);
898 884
899 if (req) { 885 if (req) {
900 finish_in_dma(ep, req, -ECONNRESET); 886 finish_in_dma(ep, req, -ECONNRESET);
901 887
902 /* clear FIFO; hosts probably won't empty it */ 888 /* clear FIFO; hosts probably won't empty it */
903 use_ep(ep, UDC_EP_SEL); 889 use_ep(ep, UDC_EP_SEL);
904 UDC_CTRL_REG = UDC_CLR_EP; 890 omap_writew(UDC_CLR_EP, UDC_CTRL);
905 deselect_ep(); 891 deselect_ep();
906 } 892 }
907 while (UDC_TXDMA_CFG_REG & mask) 893 while (omap_readw(UDC_TXDMA_CFG) & mask)
908 udelay(10); 894 udelay(10);
909 } else { 895 } else {
910 UDC_RXDMA_CFG_REG = (UDC_RXDMA_CFG_REG & ~mask) | UDC_DMA_REQ; 896 omap_writew((omap_readw(UDC_RXDMA_CFG) & ~mask) | UDC_DMA_REQ,
897 UDC_RXDMA_CFG);
911 898
912 /* dma empties the fifo */ 899 /* dma empties the fifo */
913 while (UDC_RXDMA_CFG_REG & mask) 900 while (omap_readw(UDC_RXDMA_CFG) & mask)
914 udelay(10); 901 udelay(10);
915 if (req) 902 if (req)
916 finish_out_dma(ep, req, -ECONNRESET, 0); 903 finish_out_dma(ep, req, -ECONNRESET, 0);
@@ -997,9 +984,13 @@ omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
997 req->req.actual = 0; 984 req->req.actual = 0;
998 985
999 /* maybe kickstart non-iso i/o queues */ 986 /* maybe kickstart non-iso i/o queues */
1000 if (is_iso) 987 if (is_iso) {
1001 UDC_IRQ_EN_REG |= UDC_SOF_IE; 988 u16 w;
1002 else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) { 989
990 w = omap_readw(UDC_IRQ_EN);
991 w |= UDC_SOF_IE;
992 omap_writew(w, UDC_IRQ_EN);
993 } else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) {
1003 int is_in; 994 int is_in;
1004 995
1005 if (ep->bEndpointAddress == 0) { 996 if (ep->bEndpointAddress == 0) {
@@ -1017,23 +1008,23 @@ omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
1017 * requests to non-control endpoints 1008 * requests to non-control endpoints
1018 */ 1009 */
1019 if (udc->ep0_set_config) { 1010 if (udc->ep0_set_config) {
1020 u16 irq_en = UDC_IRQ_EN_REG; 1011 u16 irq_en = omap_readw(UDC_IRQ_EN);
1021 1012
1022 irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE; 1013 irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE;
1023 if (!udc->ep0_reset_config) 1014 if (!udc->ep0_reset_config)
1024 irq_en |= UDC_EPN_RX_IE 1015 irq_en |= UDC_EPN_RX_IE
1025 | UDC_EPN_TX_IE; 1016 | UDC_EPN_TX_IE;
1026 UDC_IRQ_EN_REG = irq_en; 1017 omap_writew(irq_en, UDC_IRQ_EN);
1027 } 1018 }
1028 1019
1029 /* STATUS for zero length DATA stages is 1020 /* STATUS for zero length DATA stages is
1030 * always an IN ... even for IN transfers, 1021 * always an IN ... even for IN transfers,
1031 * a weird case which seem to stall OMAP. 1022 * a weird case which seem to stall OMAP.
1032 */ 1023 */
1033 UDC_EP_NUM_REG = (UDC_EP_SEL|UDC_EP_DIR); 1024 omap_writew(UDC_EP_SEL | UDC_EP_DIR, UDC_EP_NUM);
1034 UDC_CTRL_REG = UDC_CLR_EP; 1025 omap_writew(UDC_CLR_EP, UDC_CTRL);
1035 UDC_CTRL_REG = UDC_SET_FIFO_EN; 1026 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1036 UDC_EP_NUM_REG = UDC_EP_DIR; 1027 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1037 1028
1038 /* cleanup */ 1029 /* cleanup */
1039 udc->ep0_pending = 0; 1030 udc->ep0_pending = 0;
@@ -1042,11 +1033,11 @@ omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
1042 1033
1043 /* non-empty DATA stage */ 1034 /* non-empty DATA stage */
1044 } else if (is_in) { 1035 } else if (is_in) {
1045 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR; 1036 omap_writew(UDC_EP_SEL | UDC_EP_DIR, UDC_EP_NUM);
1046 } else { 1037 } else {
1047 if (udc->ep0_setup) 1038 if (udc->ep0_setup)
1048 goto irq_wait; 1039 goto irq_wait;
1049 UDC_EP_NUM_REG = UDC_EP_SEL; 1040 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1050 } 1041 }
1051 } else { 1042 } else {
1052 is_in = ep->bEndpointAddress & USB_DIR_IN; 1043 is_in = ep->bEndpointAddress & USB_DIR_IN;
@@ -1062,7 +1053,7 @@ omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
1062 req = NULL; 1053 req = NULL;
1063 deselect_ep(); 1054 deselect_ep();
1064 if (!is_in) { 1055 if (!is_in) {
1065 UDC_CTRL_REG = UDC_SET_FIFO_EN; 1056 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1066 ep->ackwait = 1 + ep->double_buf; 1057 ep->ackwait = 1 + ep->double_buf;
1067 } 1058 }
1068 /* IN: 6 wait states before it'll tx */ 1059 /* IN: 6 wait states before it'll tx */
@@ -1130,9 +1121,9 @@ static int omap_ep_set_halt(struct usb_ep *_ep, int value)
1130 else if (value) { 1121 else if (value) {
1131 if (ep->udc->ep0_set_config) { 1122 if (ep->udc->ep0_set_config) {
1132 WARN("error changing config?\n"); 1123 WARN("error changing config?\n");
1133 UDC_SYSCON2_REG = UDC_CLR_CFG; 1124 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1134 } 1125 }
1135 UDC_SYSCON2_REG = UDC_STALL_CMD; 1126 omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1136 ep->udc->ep0_pending = 0; 1127 ep->udc->ep0_pending = 0;
1137 status = 0; 1128 status = 0;
1138 } else /* NOP */ 1129 } else /* NOP */
@@ -1159,8 +1150,8 @@ static int omap_ep_set_halt(struct usb_ep *_ep, int value)
1159 channel = 0; 1150 channel = 0;
1160 1151
1161 use_ep(ep, UDC_EP_SEL); 1152 use_ep(ep, UDC_EP_SEL);
1162 if (UDC_STAT_FLG_REG & UDC_NON_ISO_FIFO_EMPTY) { 1153 if (omap_readw(UDC_STAT_FLG) & UDC_NON_ISO_FIFO_EMPTY) {
1163 UDC_CTRL_REG = UDC_SET_HALT; 1154 omap_writew(UDC_SET_HALT, UDC_CTRL);
1164 status = 0; 1155 status = 0;
1165 } else 1156 } else
1166 status = -EAGAIN; 1157 status = -EAGAIN;
@@ -1170,10 +1161,10 @@ static int omap_ep_set_halt(struct usb_ep *_ep, int value)
1170 dma_channel_claim(ep, channel); 1161 dma_channel_claim(ep, channel);
1171 } else { 1162 } else {
1172 use_ep(ep, 0); 1163 use_ep(ep, 0);
1173 UDC_CTRL_REG = ep->udc->clr_halt; 1164 omap_writew(ep->udc->clr_halt, UDC_CTRL);
1174 ep->ackwait = 0; 1165 ep->ackwait = 0;
1175 if (!(ep->bEndpointAddress & USB_DIR_IN)) { 1166 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1176 UDC_CTRL_REG = UDC_SET_FIFO_EN; 1167 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1177 ep->ackwait = 1 + ep->double_buf; 1168 ep->ackwait = 1 + ep->double_buf;
1178 } 1169 }
1179 } 1170 }
@@ -1205,7 +1196,7 @@ static struct usb_ep_ops omap_ep_ops = {
1205 1196
1206static int omap_get_frame(struct usb_gadget *gadget) 1197static int omap_get_frame(struct usb_gadget *gadget)
1207{ 1198{
1208 u16 sof = UDC_SOF_REG; 1199 u16 sof = omap_readw(UDC_SOF);
1209 return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC; 1200 return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC;
1210} 1201}
1211 1202
@@ -1224,7 +1215,7 @@ static int omap_wakeup(struct usb_gadget *gadget)
1224 */ 1215 */
1225 if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) { 1216 if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) {
1226 DBG("remote wakeup...\n"); 1217 DBG("remote wakeup...\n");
1227 UDC_SYSCON2_REG = UDC_RMT_WKP; 1218 omap_writew(UDC_RMT_WKP, UDC_SYSCON2);
1228 retval = 0; 1219 retval = 0;
1229 } 1220 }
1230 1221
@@ -1247,12 +1238,12 @@ omap_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
1247 1238
1248 udc = container_of(gadget, struct omap_udc, gadget); 1239 udc = container_of(gadget, struct omap_udc, gadget);
1249 spin_lock_irqsave(&udc->lock, flags); 1240 spin_lock_irqsave(&udc->lock, flags);
1250 syscon1 = UDC_SYSCON1_REG; 1241 syscon1 = omap_readw(UDC_SYSCON1);
1251 if (is_selfpowered) 1242 if (is_selfpowered)
1252 syscon1 |= UDC_SELF_PWR; 1243 syscon1 |= UDC_SELF_PWR;
1253 else 1244 else
1254 syscon1 &= ~UDC_SELF_PWR; 1245 syscon1 &= ~UDC_SELF_PWR;
1255 UDC_SYSCON1_REG = syscon1; 1246 omap_writew(syscon1, UDC_SYSCON1);
1256 spin_unlock_irqrestore(&udc->lock, flags); 1247 spin_unlock_irqrestore(&udc->lock, flags);
1257 1248
1258 return 0; 1249 return 0;
@@ -1265,18 +1256,36 @@ static int can_pullup(struct omap_udc *udc)
1265 1256
1266static void pullup_enable(struct omap_udc *udc) 1257static void pullup_enable(struct omap_udc *udc)
1267{ 1258{
1268 UDC_SYSCON1_REG |= UDC_PULLUP_EN; 1259 u16 w;
1269 if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) 1260
1270 OTG_CTRL_REG |= OTG_BSESSVLD; 1261 w = omap_readw(UDC_SYSCON1);
1271 UDC_IRQ_EN_REG = UDC_DS_CHG_IE; 1262 w |= UDC_PULLUP_EN;
1263 omap_writew(w, UDC_SYSCON1);
1264 if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
1265 u32 l;
1266
1267 l = omap_readl(OTG_CTRL);
1268 l |= OTG_BSESSVLD;
1269 omap_writel(l, OTG_CTRL);
1270 }
1271 omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
1272} 1272}
1273 1273
1274static void pullup_disable(struct omap_udc *udc) 1274static void pullup_disable(struct omap_udc *udc)
1275{ 1275{
1276 if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) 1276 u16 w;
1277 OTG_CTRL_REG &= ~OTG_BSESSVLD; 1277
1278 UDC_IRQ_EN_REG = UDC_DS_CHG_IE; 1278 if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
1279 UDC_SYSCON1_REG &= ~UDC_PULLUP_EN; 1279 u32 l;
1280
1281 l = omap_readl(OTG_CTRL);
1282 l &= ~OTG_BSESSVLD;
1283 omap_writel(l, OTG_CTRL);
1284 }
1285 omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
1286 w = omap_readw(UDC_SYSCON1);
1287 w &= ~UDC_PULLUP_EN;
1288 omap_writew(w, UDC_SYSCON1);
1280} 1289}
1281 1290
1282static struct omap_udc *udc; 1291static struct omap_udc *udc;
@@ -1304,6 +1313,7 @@ static int omap_vbus_session(struct usb_gadget *gadget, int is_active)
1304{ 1313{
1305 struct omap_udc *udc; 1314 struct omap_udc *udc;
1306 unsigned long flags; 1315 unsigned long flags;
1316 u32 l;
1307 1317
1308 udc = container_of(gadget, struct omap_udc, gadget); 1318 udc = container_of(gadget, struct omap_udc, gadget);
1309 spin_lock_irqsave(&udc->lock, flags); 1319 spin_lock_irqsave(&udc->lock, flags);
@@ -1311,10 +1321,12 @@ static int omap_vbus_session(struct usb_gadget *gadget, int is_active)
1311 udc->vbus_active = (is_active != 0); 1321 udc->vbus_active = (is_active != 0);
1312 if (cpu_is_omap15xx()) { 1322 if (cpu_is_omap15xx()) {
1313 /* "software" detect, ignored if !VBUS_MODE_1510 */ 1323 /* "software" detect, ignored if !VBUS_MODE_1510 */
1324 l = omap_readl(FUNC_MUX_CTRL_0);
1314 if (is_active) 1325 if (is_active)
1315 FUNC_MUX_CTRL_0_REG |= VBUS_CTRL_1510; 1326 l |= VBUS_CTRL_1510;
1316 else 1327 else
1317 FUNC_MUX_CTRL_0_REG &= ~VBUS_CTRL_1510; 1328 l &= ~VBUS_CTRL_1510;
1329 omap_writel(l, FUNC_MUX_CTRL_0);
1318 } 1330 }
1319 if (udc->dc_clk != NULL && is_active) { 1331 if (udc->dc_clk != NULL && is_active) {
1320 if (!udc->clk_requested) { 1332 if (!udc->clk_requested) {
@@ -1384,9 +1396,9 @@ static void nuke(struct omap_ep *ep, int status)
1384 dma_channel_release(ep); 1396 dma_channel_release(ep);
1385 1397
1386 use_ep(ep, 0); 1398 use_ep(ep, 0);
1387 UDC_CTRL_REG = UDC_CLR_EP; 1399 omap_writew(UDC_CLR_EP, UDC_CTRL);
1388 if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC) 1400 if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
1389 UDC_CTRL_REG = UDC_SET_HALT; 1401 omap_writew(UDC_SET_HALT, UDC_CTRL);
1390 1402
1391 while (!list_empty(&ep->queue)) { 1403 while (!list_empty(&ep->queue)) {
1392 req = list_entry(ep->queue.next, struct omap_req, queue); 1404 req = list_entry(ep->queue.next, struct omap_req, queue);
@@ -1414,8 +1426,8 @@ static void update_otg(struct omap_udc *udc)
1414 if (!gadget_is_otg(&udc->gadget)) 1426 if (!gadget_is_otg(&udc->gadget))
1415 return; 1427 return;
1416 1428
1417 if (OTG_CTRL_REG & OTG_ID) 1429 if (omap_readl(OTG_CTRL) & OTG_ID)
1418 devstat = UDC_DEVSTAT_REG; 1430 devstat = omap_readw(UDC_DEVSTAT);
1419 else 1431 else
1420 devstat = 0; 1432 devstat = 0;
1421 1433
@@ -1426,9 +1438,14 @@ static void update_otg(struct omap_udc *udc)
1426 /* Enable HNP early, avoiding races on suspend irq path. 1438 /* Enable HNP early, avoiding races on suspend irq path.
1427 * ASSUMES OTG state machine B_BUS_REQ input is true. 1439 * ASSUMES OTG state machine B_BUS_REQ input is true.
1428 */ 1440 */
1429 if (udc->gadget.b_hnp_enable) 1441 if (udc->gadget.b_hnp_enable) {
1430 OTG_CTRL_REG = (OTG_CTRL_REG | OTG_B_HNPEN | OTG_B_BUSREQ) 1442 u32 l;
1431 & ~OTG_PULLUP; 1443
1444 l = omap_readl(OTG_CTRL);
1445 l |= OTG_B_HNPEN | OTG_B_BUSREQ;
1446 l &= ~OTG_PULLUP;
1447 omap_writel(l, OTG_CTRL);
1448 }
1432} 1449}
1433 1450
1434static void ep0_irq(struct omap_udc *udc, u16 irq_src) 1451static void ep0_irq(struct omap_udc *udc, u16 irq_src)
@@ -1446,7 +1463,7 @@ static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1446 1463
1447 nuke(ep0, 0); 1464 nuke(ep0, 0);
1448 if (ack) { 1465 if (ack) {
1449 UDC_IRQ_SRC_REG = ack; 1466 omap_writew(ack, UDC_IRQ_SRC);
1450 irq_src = UDC_SETUP; 1467 irq_src = UDC_SETUP;
1451 } 1468 }
1452 } 1469 }
@@ -1466,9 +1483,9 @@ static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1466 if (irq_src & UDC_EP0_TX) { 1483 if (irq_src & UDC_EP0_TX) {
1467 int stat; 1484 int stat;
1468 1485
1469 UDC_IRQ_SRC_REG = UDC_EP0_TX; 1486 omap_writew(UDC_EP0_TX, UDC_IRQ_SRC);
1470 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR; 1487 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1471 stat = UDC_STAT_FLG_REG; 1488 stat = omap_readw(UDC_STAT_FLG);
1472 if (stat & UDC_ACK) { 1489 if (stat & UDC_ACK) {
1473 if (udc->ep0_in) { 1490 if (udc->ep0_in) {
1474 /* write next IN packet from response, 1491 /* write next IN packet from response,
@@ -1476,26 +1493,26 @@ static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1476 */ 1493 */
1477 if (req) 1494 if (req)
1478 stat = write_fifo(ep0, req); 1495 stat = write_fifo(ep0, req);
1479 UDC_EP_NUM_REG = UDC_EP_DIR; 1496 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1480 if (!req && udc->ep0_pending) { 1497 if (!req && udc->ep0_pending) {
1481 UDC_EP_NUM_REG = UDC_EP_SEL; 1498 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1482 UDC_CTRL_REG = UDC_CLR_EP; 1499 omap_writew(UDC_CLR_EP, UDC_CTRL);
1483 UDC_CTRL_REG = UDC_SET_FIFO_EN; 1500 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1484 UDC_EP_NUM_REG = 0; 1501 omap_writew(0, UDC_EP_NUM);
1485 udc->ep0_pending = 0; 1502 udc->ep0_pending = 0;
1486 } /* else: 6 wait states before it'll tx */ 1503 } /* else: 6 wait states before it'll tx */
1487 } else { 1504 } else {
1488 /* ack status stage of OUT transfer */ 1505 /* ack status stage of OUT transfer */
1489 UDC_EP_NUM_REG = UDC_EP_DIR; 1506 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1490 if (req) 1507 if (req)
1491 done(ep0, req, 0); 1508 done(ep0, req, 0);
1492 } 1509 }
1493 req = NULL; 1510 req = NULL;
1494 } else if (stat & UDC_STALL) { 1511 } else if (stat & UDC_STALL) {
1495 UDC_CTRL_REG = UDC_CLR_HALT; 1512 omap_writew(UDC_CLR_HALT, UDC_CTRL);
1496 UDC_EP_NUM_REG = UDC_EP_DIR; 1513 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1497 } else { 1514 } else {
1498 UDC_EP_NUM_REG = UDC_EP_DIR; 1515 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1499 } 1516 }
1500 } 1517 }
1501 1518
@@ -1503,9 +1520,9 @@ static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1503 if (irq_src & UDC_EP0_RX) { 1520 if (irq_src & UDC_EP0_RX) {
1504 int stat; 1521 int stat;
1505 1522
1506 UDC_IRQ_SRC_REG = UDC_EP0_RX; 1523 omap_writew(UDC_EP0_RX, UDC_IRQ_SRC);
1507 UDC_EP_NUM_REG = UDC_EP_SEL; 1524 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1508 stat = UDC_STAT_FLG_REG; 1525 stat = omap_readw(UDC_STAT_FLG);
1509 if (stat & UDC_ACK) { 1526 if (stat & UDC_ACK) {
1510 if (!udc->ep0_in) { 1527 if (!udc->ep0_in) {
1511 stat = 0; 1528 stat = 0;
@@ -1513,34 +1530,35 @@ static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1513 * reactiviting the fifo; stall on errors. 1530 * reactiviting the fifo; stall on errors.
1514 */ 1531 */
1515 if (!req || (stat = read_fifo(ep0, req)) < 0) { 1532 if (!req || (stat = read_fifo(ep0, req)) < 0) {
1516 UDC_SYSCON2_REG = UDC_STALL_CMD; 1533 omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1517 udc->ep0_pending = 0; 1534 udc->ep0_pending = 0;
1518 stat = 0; 1535 stat = 0;
1519 } else if (stat == 0) 1536 } else if (stat == 0)
1520 UDC_CTRL_REG = UDC_SET_FIFO_EN; 1537 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1521 UDC_EP_NUM_REG = 0; 1538 omap_writew(0, UDC_EP_NUM);
1522 1539
1523 /* activate status stage */ 1540 /* activate status stage */
1524 if (stat == 1) { 1541 if (stat == 1) {
1525 done(ep0, req, 0); 1542 done(ep0, req, 0);
1526 /* that may have STALLed ep0... */ 1543 /* that may have STALLed ep0... */
1527 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR; 1544 omap_writew(UDC_EP_SEL | UDC_EP_DIR,
1528 UDC_CTRL_REG = UDC_CLR_EP; 1545 UDC_EP_NUM);
1529 UDC_CTRL_REG = UDC_SET_FIFO_EN; 1546 omap_writew(UDC_CLR_EP, UDC_CTRL);
1530 UDC_EP_NUM_REG = UDC_EP_DIR; 1547 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1548 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1531 udc->ep0_pending = 0; 1549 udc->ep0_pending = 0;
1532 } 1550 }
1533 } else { 1551 } else {
1534 /* ack status stage of IN transfer */ 1552 /* ack status stage of IN transfer */
1535 UDC_EP_NUM_REG = 0; 1553 omap_writew(0, UDC_EP_NUM);
1536 if (req) 1554 if (req)
1537 done(ep0, req, 0); 1555 done(ep0, req, 0);
1538 } 1556 }
1539 } else if (stat & UDC_STALL) { 1557 } else if (stat & UDC_STALL) {
1540 UDC_CTRL_REG = UDC_CLR_HALT; 1558 omap_writew(UDC_CLR_HALT, UDC_CTRL);
1541 UDC_EP_NUM_REG = 0; 1559 omap_writew(0, UDC_EP_NUM);
1542 } else { 1560 } else {
1543 UDC_EP_NUM_REG = 0; 1561 omap_writew(0, UDC_EP_NUM);
1544 } 1562 }
1545 } 1563 }
1546 1564
@@ -1555,14 +1573,14 @@ static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1555 1573
1556 /* read the (latest) SETUP message */ 1574 /* read the (latest) SETUP message */
1557 do { 1575 do {
1558 UDC_EP_NUM_REG = UDC_SETUP_SEL; 1576 omap_writew(UDC_SETUP_SEL, UDC_EP_NUM);
1559 /* two bytes at a time */ 1577 /* two bytes at a time */
1560 u.word[0] = UDC_DATA_REG; 1578 u.word[0] = omap_readw(UDC_DATA);
1561 u.word[1] = UDC_DATA_REG; 1579 u.word[1] = omap_readw(UDC_DATA);
1562 u.word[2] = UDC_DATA_REG; 1580 u.word[2] = omap_readw(UDC_DATA);
1563 u.word[3] = UDC_DATA_REG; 1581 u.word[3] = omap_readw(UDC_DATA);
1564 UDC_EP_NUM_REG = 0; 1582 omap_writew(0, UDC_EP_NUM);
1565 } while (UDC_IRQ_SRC_REG & UDC_SETUP); 1583 } while (omap_readw(UDC_IRQ_SRC) & UDC_SETUP);
1566 1584
1567#define w_value le16_to_cpu(u.r.wValue) 1585#define w_value le16_to_cpu(u.r.wValue)
1568#define w_index le16_to_cpu(u.r.wIndex) 1586#define w_index le16_to_cpu(u.r.wIndex)
@@ -1593,9 +1611,9 @@ static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1593 * later if it fails the request. 1611 * later if it fails the request.
1594 */ 1612 */
1595 if (udc->ep0_reset_config) 1613 if (udc->ep0_reset_config)
1596 UDC_SYSCON2_REG = UDC_CLR_CFG; 1614 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1597 else 1615 else
1598 UDC_SYSCON2_REG = UDC_DEV_CFG; 1616 omap_writew(UDC_DEV_CFG, UDC_SYSCON2);
1599 update_otg(udc); 1617 update_otg(udc);
1600 goto delegate; 1618 goto delegate;
1601 case USB_REQ_CLEAR_FEATURE: 1619 case USB_REQ_CLEAR_FEATURE:
@@ -1613,10 +1631,10 @@ static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1613 || !ep->desc) 1631 || !ep->desc)
1614 goto do_stall; 1632 goto do_stall;
1615 use_ep(ep, 0); 1633 use_ep(ep, 0);
1616 UDC_CTRL_REG = udc->clr_halt; 1634 omap_writew(udc->clr_halt, UDC_CTRL);
1617 ep->ackwait = 0; 1635 ep->ackwait = 0;
1618 if (!(ep->bEndpointAddress & USB_DIR_IN)) { 1636 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1619 UDC_CTRL_REG = UDC_SET_FIFO_EN; 1637 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1620 ep->ackwait = 1 + ep->double_buf; 1638 ep->ackwait = 1 + ep->double_buf;
1621 } 1639 }
1622 /* NOTE: assumes the host behaves sanely, 1640 /* NOTE: assumes the host behaves sanely,
@@ -1649,15 +1667,15 @@ static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1649 } 1667 }
1650 use_ep(ep, 0); 1668 use_ep(ep, 0);
1651 /* can't halt if fifo isn't empty... */ 1669 /* can't halt if fifo isn't empty... */
1652 UDC_CTRL_REG = UDC_CLR_EP; 1670 omap_writew(UDC_CLR_EP, UDC_CTRL);
1653 UDC_CTRL_REG = UDC_SET_HALT; 1671 omap_writew(UDC_SET_HALT, UDC_CTRL);
1654 VDBG("%s halted by host\n", ep->name); 1672 VDBG("%s halted by host\n", ep->name);
1655ep0out_status_stage: 1673ep0out_status_stage:
1656 status = 0; 1674 status = 0;
1657 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR; 1675 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1658 UDC_CTRL_REG = UDC_CLR_EP; 1676 omap_writew(UDC_CLR_EP, UDC_CTRL);
1659 UDC_CTRL_REG = UDC_SET_FIFO_EN; 1677 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1660 UDC_EP_NUM_REG = UDC_EP_DIR; 1678 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1661 udc->ep0_pending = 0; 1679 udc->ep0_pending = 0;
1662 break; 1680 break;
1663 case USB_REQ_GET_STATUS: 1681 case USB_REQ_GET_STATUS:
@@ -1694,10 +1712,10 @@ intf_status:
1694 1712
1695zero_status: 1713zero_status:
1696 /* return two zero bytes */ 1714 /* return two zero bytes */
1697 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR; 1715 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1698 UDC_DATA_REG = 0; 1716 omap_writew(0, UDC_DATA);
1699 UDC_CTRL_REG = UDC_SET_FIFO_EN; 1717 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1700 UDC_EP_NUM_REG = UDC_EP_DIR; 1718 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1701 status = 0; 1719 status = 0;
1702 VDBG("GET_STATUS, interface %d\n", w_index); 1720 VDBG("GET_STATUS, interface %d\n", w_index);
1703 /* next, status stage */ 1721 /* next, status stage */
@@ -1706,8 +1724,8 @@ zero_status:
1706delegate: 1724delegate:
1707 /* activate the ep0out fifo right away */ 1725 /* activate the ep0out fifo right away */
1708 if (!udc->ep0_in && w_length) { 1726 if (!udc->ep0_in && w_length) {
1709 UDC_EP_NUM_REG = 0; 1727 omap_writew(0, UDC_EP_NUM);
1710 UDC_CTRL_REG = UDC_SET_FIFO_EN; 1728 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1711 } 1729 }
1712 1730
1713 /* gadget drivers see class/vendor specific requests, 1731 /* gadget drivers see class/vendor specific requests,
@@ -1748,9 +1766,9 @@ do_stall:
1748 if (udc->ep0_reset_config) 1766 if (udc->ep0_reset_config)
1749 WARN("error resetting config?\n"); 1767 WARN("error resetting config?\n");
1750 else 1768 else
1751 UDC_SYSCON2_REG = UDC_CLR_CFG; 1769 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1752 } 1770 }
1753 UDC_SYSCON2_REG = UDC_STALL_CMD; 1771 omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1754 udc->ep0_pending = 0; 1772 udc->ep0_pending = 0;
1755 } 1773 }
1756 } 1774 }
@@ -1764,7 +1782,7 @@ static void devstate_irq(struct omap_udc *udc, u16 irq_src)
1764{ 1782{
1765 u16 devstat, change; 1783 u16 devstat, change;
1766 1784
1767 devstat = UDC_DEVSTAT_REG; 1785 devstat = omap_readw(UDC_DEVSTAT);
1768 change = devstat ^ udc->devstat; 1786 change = devstat ^ udc->devstat;
1769 udc->devstat = devstat; 1787 udc->devstat = devstat;
1770 1788
@@ -1804,7 +1822,8 @@ static void devstate_irq(struct omap_udc *udc, u16 irq_src)
1804 INFO("USB reset done, gadget %s\n", 1822 INFO("USB reset done, gadget %s\n",
1805 udc->driver->driver.name); 1823 udc->driver->driver.name);
1806 /* ep0 traffic is legal from now on */ 1824 /* ep0 traffic is legal from now on */
1807 UDC_IRQ_EN_REG = UDC_DS_CHG_IE | UDC_EP0_IE; 1825 omap_writew(UDC_DS_CHG_IE | UDC_EP0_IE,
1826 UDC_IRQ_EN);
1808 } 1827 }
1809 change &= ~UDC_USB_RESET; 1828 change &= ~UDC_USB_RESET;
1810 } 1829 }
@@ -1848,7 +1867,7 @@ static void devstate_irq(struct omap_udc *udc, u16 irq_src)
1848 VDBG("devstat %03x, ignore change %03x\n", 1867 VDBG("devstat %03x, ignore change %03x\n",
1849 devstat, change); 1868 devstat, change);
1850 1869
1851 UDC_IRQ_SRC_REG = UDC_DS_CHG; 1870 omap_writew(UDC_DS_CHG, UDC_IRQ_SRC);
1852} 1871}
1853 1872
1854static irqreturn_t omap_udc_irq(int irq, void *_udc) 1873static irqreturn_t omap_udc_irq(int irq, void *_udc)
@@ -1859,7 +1878,7 @@ static irqreturn_t omap_udc_irq(int irq, void *_udc)
1859 unsigned long flags; 1878 unsigned long flags;
1860 1879
1861 spin_lock_irqsave(&udc->lock, flags); 1880 spin_lock_irqsave(&udc->lock, flags);
1862 irq_src = UDC_IRQ_SRC_REG; 1881 irq_src = omap_readw(UDC_IRQ_SRC);
1863 1882
1864 /* Device state change (usb ch9 stuff) */ 1883 /* Device state change (usb ch9 stuff) */
1865 if (irq_src & UDC_DS_CHG) { 1884 if (irq_src & UDC_DS_CHG) {
@@ -1882,7 +1901,7 @@ static irqreturn_t omap_udc_irq(int irq, void *_udc)
1882 irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT); 1901 irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT);
1883 } 1902 }
1884 1903
1885 irq_src &= ~(UDC_SOF|UDC_EPN_TX|UDC_EPN_RX); 1904 irq_src &= ~(UDC_IRQ_SOF | UDC_EPN_TX|UDC_EPN_RX);
1886 if (irq_src) 1905 if (irq_src)
1887 DBG("udc_irq, unhandled %03x\n", irq_src); 1906 DBG("udc_irq, unhandled %03x\n", irq_src);
1888 spin_unlock_irqrestore(&udc->lock, flags); 1907 spin_unlock_irqrestore(&udc->lock, flags);
@@ -1903,7 +1922,7 @@ static void pio_out_timer(unsigned long _ep)
1903 spin_lock_irqsave(&ep->udc->lock, flags); 1922 spin_lock_irqsave(&ep->udc->lock, flags);
1904 if (!list_empty(&ep->queue) && ep->ackwait) { 1923 if (!list_empty(&ep->queue) && ep->ackwait) {
1905 use_ep(ep, UDC_EP_SEL); 1924 use_ep(ep, UDC_EP_SEL);
1906 stat_flg = UDC_STAT_FLG_REG; 1925 stat_flg = omap_readw(UDC_STAT_FLG);
1907 1926
1908 if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN) 1927 if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN)
1909 || (ep->double_buf && HALF_FULL(stat_flg)))) { 1928 || (ep->double_buf && HALF_FULL(stat_flg)))) {
@@ -1913,8 +1932,8 @@ static void pio_out_timer(unsigned long _ep)
1913 req = container_of(ep->queue.next, 1932 req = container_of(ep->queue.next,
1914 struct omap_req, queue); 1933 struct omap_req, queue);
1915 (void) read_fifo(ep, req); 1934 (void) read_fifo(ep, req);
1916 UDC_EP_NUM_REG = ep->bEndpointAddress; 1935 omap_writew(ep->bEndpointAddress, UDC_EP_NUM);
1917 UDC_CTRL_REG = UDC_SET_FIFO_EN; 1936 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1918 ep->ackwait = 1 + ep->double_buf; 1937 ep->ackwait = 1 + ep->double_buf;
1919 } else 1938 } else
1920 deselect_ep(); 1939 deselect_ep();
@@ -1934,20 +1953,20 @@ static irqreturn_t omap_udc_pio_irq(int irq, void *_dev)
1934 unsigned long flags; 1953 unsigned long flags;
1935 1954
1936 spin_lock_irqsave(&udc->lock, flags); 1955 spin_lock_irqsave(&udc->lock, flags);
1937 epn_stat = UDC_EPN_STAT_REG; 1956 epn_stat = omap_readw(UDC_EPN_STAT);
1938 irq_src = UDC_IRQ_SRC_REG; 1957 irq_src = omap_readw(UDC_IRQ_SRC);
1939 1958
1940 /* handle OUT first, to avoid some wasteful NAKs */ 1959 /* handle OUT first, to avoid some wasteful NAKs */
1941 if (irq_src & UDC_EPN_RX) { 1960 if (irq_src & UDC_EPN_RX) {
1942 epnum = (epn_stat >> 8) & 0x0f; 1961 epnum = (epn_stat >> 8) & 0x0f;
1943 UDC_IRQ_SRC_REG = UDC_EPN_RX; 1962 omap_writew(UDC_EPN_RX, UDC_IRQ_SRC);
1944 status = IRQ_HANDLED; 1963 status = IRQ_HANDLED;
1945 ep = &udc->ep[epnum]; 1964 ep = &udc->ep[epnum];
1946 ep->irqs++; 1965 ep->irqs++;
1947 1966
1948 UDC_EP_NUM_REG = epnum | UDC_EP_SEL; 1967 omap_writew(epnum | UDC_EP_SEL, UDC_EP_NUM);
1949 ep->fnf = 0; 1968 ep->fnf = 0;
1950 if ((UDC_STAT_FLG_REG & UDC_ACK)) { 1969 if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
1951 ep->ackwait--; 1970 ep->ackwait--;
1952 if (!list_empty(&ep->queue)) { 1971 if (!list_empty(&ep->queue)) {
1953 int stat; 1972 int stat;
@@ -1959,15 +1978,15 @@ static irqreturn_t omap_udc_pio_irq(int irq, void *_dev)
1959 } 1978 }
1960 } 1979 }
1961 /* min 6 clock delay before clearing EP_SEL ... */ 1980 /* min 6 clock delay before clearing EP_SEL ... */
1962 epn_stat = UDC_EPN_STAT_REG; 1981 epn_stat = omap_readw(UDC_EPN_STAT);
1963 epn_stat = UDC_EPN_STAT_REG; 1982 epn_stat = omap_readw(UDC_EPN_STAT);
1964 UDC_EP_NUM_REG = epnum; 1983 omap_writew(epnum, UDC_EP_NUM);
1965 1984
1966 /* enabling fifo _after_ clearing ACK, contrary to docs, 1985 /* enabling fifo _after_ clearing ACK, contrary to docs,
1967 * reduces lossage; timer still needed though (sigh). 1986 * reduces lossage; timer still needed though (sigh).
1968 */ 1987 */
1969 if (ep->fnf) { 1988 if (ep->fnf) {
1970 UDC_CTRL_REG = UDC_SET_FIFO_EN; 1989 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1971 ep->ackwait = 1 + ep->double_buf; 1990 ep->ackwait = 1 + ep->double_buf;
1972 } 1991 }
1973 mod_timer(&ep->timer, PIO_OUT_TIMEOUT); 1992 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
@@ -1976,13 +1995,13 @@ static irqreturn_t omap_udc_pio_irq(int irq, void *_dev)
1976 /* then IN transfers */ 1995 /* then IN transfers */
1977 else if (irq_src & UDC_EPN_TX) { 1996 else if (irq_src & UDC_EPN_TX) {
1978 epnum = epn_stat & 0x0f; 1997 epnum = epn_stat & 0x0f;
1979 UDC_IRQ_SRC_REG = UDC_EPN_TX; 1998 omap_writew(UDC_EPN_TX, UDC_IRQ_SRC);
1980 status = IRQ_HANDLED; 1999 status = IRQ_HANDLED;
1981 ep = &udc->ep[16 + epnum]; 2000 ep = &udc->ep[16 + epnum];
1982 ep->irqs++; 2001 ep->irqs++;
1983 2002
1984 UDC_EP_NUM_REG = epnum | UDC_EP_DIR | UDC_EP_SEL; 2003 omap_writew(epnum | UDC_EP_DIR | UDC_EP_SEL, UDC_EP_NUM);
1985 if ((UDC_STAT_FLG_REG & UDC_ACK)) { 2004 if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
1986 ep->ackwait = 0; 2005 ep->ackwait = 0;
1987 if (!list_empty(&ep->queue)) { 2006 if (!list_empty(&ep->queue)) {
1988 req = container_of(ep->queue.next, 2007 req = container_of(ep->queue.next,
@@ -1991,9 +2010,9 @@ static irqreturn_t omap_udc_pio_irq(int irq, void *_dev)
1991 } 2010 }
1992 } 2011 }
1993 /* min 6 clock delay before clearing EP_SEL ... */ 2012 /* min 6 clock delay before clearing EP_SEL ... */
1994 epn_stat = UDC_EPN_STAT_REG; 2013 epn_stat = omap_readw(UDC_EPN_STAT);
1995 epn_stat = UDC_EPN_STAT_REG; 2014 epn_stat = omap_readw(UDC_EPN_STAT);
1996 UDC_EP_NUM_REG = epnum | UDC_EP_DIR; 2015 omap_writew(epnum | UDC_EP_DIR, UDC_EP_NUM);
1997 /* then 6 clocks before it'd tx */ 2016 /* then 6 clocks before it'd tx */
1998 } 2017 }
1999 2018
@@ -2021,7 +2040,7 @@ static irqreturn_t omap_udc_iso_irq(int irq, void *_dev)
2021 req = list_entry(ep->queue.next, struct omap_req, queue); 2040 req = list_entry(ep->queue.next, struct omap_req, queue);
2022 2041
2023 use_ep(ep, UDC_EP_SEL); 2042 use_ep(ep, UDC_EP_SEL);
2024 stat = UDC_STAT_FLG_REG; 2043 stat = omap_readw(UDC_STAT_FLG);
2025 2044
2026 /* NOTE: like the other controller drivers, this isn't 2045 /* NOTE: like the other controller drivers, this isn't
2027 * currently reporting lost or damaged frames. 2046 * currently reporting lost or damaged frames.
@@ -2053,9 +2072,14 @@ static irqreturn_t omap_udc_iso_irq(int irq, void *_dev)
2053 if (!list_empty(&ep->queue)) 2072 if (!list_empty(&ep->queue))
2054 pending = 1; 2073 pending = 1;
2055 } 2074 }
2056 if (!pending) 2075 if (!pending) {
2057 UDC_IRQ_EN_REG &= ~UDC_SOF_IE; 2076 u16 w;
2058 UDC_IRQ_SRC_REG = UDC_SOF; 2077
2078 w = omap_readw(UDC_IRQ_EN);
2079 w &= ~UDC_SOF_IE;
2080 omap_writew(w, UDC_IRQ_EN);
2081 }
2082 omap_writew(UDC_IRQ_SOF, UDC_IRQ_SRC);
2059 2083
2060 spin_unlock_irqrestore(&udc->lock, flags); 2084 spin_unlock_irqrestore(&udc->lock, flags);
2061 return IRQ_HANDLED; 2085 return IRQ_HANDLED;
@@ -2104,7 +2128,7 @@ int usb_gadget_register_driver (struct usb_gadget_driver *driver)
2104 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) 2128 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
2105 continue; 2129 continue;
2106 use_ep(ep, 0); 2130 use_ep(ep, 0);
2107 UDC_CTRL_REG = UDC_SET_HALT; 2131 omap_writew(UDC_SET_HALT, UDC_CTRL);
2108 } 2132 }
2109 udc->ep0_pending = 0; 2133 udc->ep0_pending = 0;
2110 udc->ep[0].irqs = 0; 2134 udc->ep[0].irqs = 0;
@@ -2128,7 +2152,7 @@ int usb_gadget_register_driver (struct usb_gadget_driver *driver)
2128 } 2152 }
2129 DBG("bound to driver %s\n", driver->driver.name); 2153 DBG("bound to driver %s\n", driver->driver.name);
2130 2154
2131 UDC_IRQ_SRC_REG = UDC_IRQ_SRC_MASK; 2155 omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
2132 2156
2133 /* connect to bus through transceiver */ 2157 /* connect to bus through transceiver */
2134 if (udc->transceiver) { 2158 if (udc->transceiver) {
@@ -2225,7 +2249,7 @@ static void proc_ep_show(struct seq_file *s, struct omap_ep *ep)
2225 else 2249 else
2226 buf[0] = 0; 2250 buf[0] = 0;
2227 2251
2228 stat_flg = UDC_STAT_FLG_REG; 2252 stat_flg = omap_readw(UDC_STAT_FLG);
2229 seq_printf(s, 2253 seq_printf(s,
2230 "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n", 2254 "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n",
2231 ep->name, buf, 2255 ep->name, buf,
@@ -2292,11 +2316,11 @@ static int proc_otg_show(struct seq_file *s)
2292 trans = CONTROL_DEVCONF_REG; 2316 trans = CONTROL_DEVCONF_REG;
2293 } else { 2317 } else {
2294 ctrl_name = "tranceiver_ctrl"; 2318 ctrl_name = "tranceiver_ctrl";
2295 trans = USB_TRANSCEIVER_CTRL_REG; 2319 trans = omap_readw(USB_TRANSCEIVER_CTRL);
2296 } 2320 }
2297 seq_printf(s, "\nOTG rev %d.%d, %s %05x\n", 2321 seq_printf(s, "\nOTG rev %d.%d, %s %05x\n",
2298 tmp >> 4, tmp & 0xf, ctrl_name, trans); 2322 tmp >> 4, tmp & 0xf, ctrl_name, trans);
2299 tmp = OTG_SYSCON_1_REG; 2323 tmp = omap_readw(OTG_SYSCON_1);
2300 seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s," 2324 seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s,"
2301 FOURBITS "\n", tmp, 2325 FOURBITS "\n", tmp,
2302 trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R), 2326 trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R),
@@ -2308,7 +2332,7 @@ static int proc_otg_show(struct seq_file *s)
2308 (tmp & HST_IDLE_EN) ? " !host" : "", 2332 (tmp & HST_IDLE_EN) ? " !host" : "",
2309 (tmp & DEV_IDLE_EN) ? " !dev" : "", 2333 (tmp & DEV_IDLE_EN) ? " !dev" : "",
2310 (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active"); 2334 (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active");
2311 tmp = OTG_SYSCON_2_REG; 2335 tmp = omap_readl(OTG_SYSCON_2);
2312 seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS 2336 seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS
2313 " b_ase_brst=%d hmc=%d\n", tmp, 2337 " b_ase_brst=%d hmc=%d\n", tmp,
2314 (tmp & OTG_EN) ? " otg_en" : "", 2338 (tmp & OTG_EN) ? " otg_en" : "",
@@ -2323,7 +2347,7 @@ static int proc_otg_show(struct seq_file *s)
2323 (tmp & HMC_TLLATTACH) ? " tllattach" : "", 2347 (tmp & HMC_TLLATTACH) ? " tllattach" : "",
2324 B_ASE_BRST(tmp), 2348 B_ASE_BRST(tmp),
2325 OTG_HMC(tmp)); 2349 OTG_HMC(tmp));
2326 tmp = OTG_CTRL_REG; 2350 tmp = omap_readl(OTG_CTRL);
2327 seq_printf(s, "otg_ctrl %06x" EIGHTBITS EIGHTBITS "%s\n", tmp, 2351 seq_printf(s, "otg_ctrl %06x" EIGHTBITS EIGHTBITS "%s\n", tmp,
2328 (tmp & OTG_ASESSVLD) ? " asess" : "", 2352 (tmp & OTG_ASESSVLD) ? " asess" : "",
2329 (tmp & OTG_BSESSEND) ? " bsess_end" : "", 2353 (tmp & OTG_BSESSEND) ? " bsess_end" : "",
@@ -2343,13 +2367,13 @@ static int proc_otg_show(struct seq_file *s)
2343 (tmp & OTG_PU_VBUS) ? " pu_vb" : "", 2367 (tmp & OTG_PU_VBUS) ? " pu_vb" : "",
2344 (tmp & OTG_PU_ID) ? " pu_id" : "" 2368 (tmp & OTG_PU_ID) ? " pu_id" : ""
2345 ); 2369 );
2346 tmp = OTG_IRQ_EN_REG; 2370 tmp = omap_readw(OTG_IRQ_EN);
2347 seq_printf(s, "otg_irq_en %04x" "\n", tmp); 2371 seq_printf(s, "otg_irq_en %04x" "\n", tmp);
2348 tmp = OTG_IRQ_SRC_REG; 2372 tmp = omap_readw(OTG_IRQ_SRC);
2349 seq_printf(s, "otg_irq_src %04x" "\n", tmp); 2373 seq_printf(s, "otg_irq_src %04x" "\n", tmp);
2350 tmp = OTG_OUTCTRL_REG; 2374 tmp = omap_readw(OTG_OUTCTRL);
2351 seq_printf(s, "otg_outctrl %04x" "\n", tmp); 2375 seq_printf(s, "otg_outctrl %04x" "\n", tmp);
2352 tmp = OTG_TEST_REG; 2376 tmp = omap_readw(OTG_TEST);
2353 seq_printf(s, "otg_test %04x" "\n", tmp); 2377 seq_printf(s, "otg_test %04x" "\n", tmp);
2354 return 0; 2378 return 0;
2355} 2379}
@@ -2370,7 +2394,7 @@ static int proc_udc_show(struct seq_file *s, void *_)
2370 driver_desc, 2394 driver_desc,
2371 use_dma ? " (dma)" : ""); 2395 use_dma ? " (dma)" : "");
2372 2396
2373 tmp = UDC_REV_REG & 0xff; 2397 tmp = omap_readw(UDC_REV) & 0xff;
2374 seq_printf(s, 2398 seq_printf(s,
2375 "UDC rev %d.%d, fifo mode %d, gadget %s\n" 2399 "UDC rev %d.%d, fifo mode %d, gadget %s\n"
2376 "hmc %d, transceiver %s\n", 2400 "hmc %d, transceiver %s\n",
@@ -2384,16 +2408,16 @@ static int proc_udc_show(struct seq_file *s, void *_)
2384 ? "external" : "(none)")); 2408 ? "external" : "(none)"));
2385 if (cpu_class_is_omap1()) { 2409 if (cpu_class_is_omap1()) {
2386 seq_printf(s, "ULPD control %04x req %04x status %04x\n", 2410 seq_printf(s, "ULPD control %04x req %04x status %04x\n",
2387 __REG16(ULPD_CLOCK_CTRL), 2411 omap_readw(ULPD_CLOCK_CTRL),
2388 __REG16(ULPD_SOFT_REQ), 2412 omap_readw(ULPD_SOFT_REQ),
2389 __REG16(ULPD_STATUS_REQ)); 2413 omap_readw(ULPD_STATUS_REQ));
2390 } 2414 }
2391 2415
2392 /* OTG controller registers */ 2416 /* OTG controller registers */
2393 if (!cpu_is_omap15xx()) 2417 if (!cpu_is_omap15xx())
2394 proc_otg_show(s); 2418 proc_otg_show(s);
2395 2419
2396 tmp = UDC_SYSCON1_REG; 2420 tmp = omap_readw(UDC_SYSCON1);
2397 seq_printf(s, "\nsyscon1 %04x" EIGHTBITS "\n", tmp, 2421 seq_printf(s, "\nsyscon1 %04x" EIGHTBITS "\n", tmp,
2398 (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "", 2422 (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "",
2399 (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "", 2423 (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "",
@@ -2412,7 +2436,7 @@ static int proc_udc_show(struct seq_file *s, void *_)
2412 return 0; 2436 return 0;
2413 } 2437 }
2414 2438
2415 tmp = UDC_DEVSTAT_REG; 2439 tmp = omap_readw(UDC_DEVSTAT);
2416 seq_printf(s, "devstat %04x" EIGHTBITS "%s%s\n", tmp, 2440 seq_printf(s, "devstat %04x" EIGHTBITS "%s%s\n", tmp,
2417 (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "", 2441 (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "",
2418 (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "", 2442 (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "",
@@ -2424,20 +2448,20 @@ static int proc_udc_show(struct seq_file *s, void *_)
2424 (tmp & UDC_ADD) ? " ADD" : "", 2448 (tmp & UDC_ADD) ? " ADD" : "",
2425 (tmp & UDC_DEF) ? " DEF" : "", 2449 (tmp & UDC_DEF) ? " DEF" : "",
2426 (tmp & UDC_ATT) ? " ATT" : ""); 2450 (tmp & UDC_ATT) ? " ATT" : "");
2427 seq_printf(s, "sof %04x\n", UDC_SOF_REG); 2451 seq_printf(s, "sof %04x\n", omap_readw(UDC_SOF));
2428 tmp = UDC_IRQ_EN_REG; 2452 tmp = omap_readw(UDC_IRQ_EN);
2429 seq_printf(s, "irq_en %04x" FOURBITS "%s\n", tmp, 2453 seq_printf(s, "irq_en %04x" FOURBITS "%s\n", tmp,
2430 (tmp & UDC_SOF_IE) ? " sof" : "", 2454 (tmp & UDC_SOF_IE) ? " sof" : "",
2431 (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "", 2455 (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "",
2432 (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "", 2456 (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "",
2433 (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "", 2457 (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "",
2434 (tmp & UDC_EP0_IE) ? " ep0" : ""); 2458 (tmp & UDC_EP0_IE) ? " ep0" : "");
2435 tmp = UDC_IRQ_SRC_REG; 2459 tmp = omap_readw(UDC_IRQ_SRC);
2436 seq_printf(s, "irq_src %04x" EIGHTBITS "%s%s\n", tmp, 2460 seq_printf(s, "irq_src %04x" EIGHTBITS "%s%s\n", tmp,
2437 (tmp & UDC_TXN_DONE) ? " txn_done" : "", 2461 (tmp & UDC_TXN_DONE) ? " txn_done" : "",
2438 (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "", 2462 (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "",
2439 (tmp & UDC_RXN_EOT) ? " rxn_eot" : "", 2463 (tmp & UDC_RXN_EOT) ? " rxn_eot" : "",
2440 (tmp & UDC_SOF) ? " sof" : "", 2464 (tmp & UDC_IRQ_SOF) ? " sof" : "",
2441 (tmp & UDC_EPN_RX) ? " epn_rx" : "", 2465 (tmp & UDC_EPN_RX) ? " epn_rx" : "",
2442 (tmp & UDC_EPN_TX) ? " epn_tx" : "", 2466 (tmp & UDC_EPN_TX) ? " epn_tx" : "",
2443 (tmp & UDC_DS_CHG) ? " ds_chg" : "", 2467 (tmp & UDC_DS_CHG) ? " ds_chg" : "",
@@ -2447,7 +2471,7 @@ static int proc_udc_show(struct seq_file *s, void *_)
2447 if (use_dma) { 2471 if (use_dma) {
2448 unsigned i; 2472 unsigned i;
2449 2473
2450 tmp = UDC_DMA_IRQ_EN_REG; 2474 tmp = omap_readw(UDC_DMA_IRQ_EN);
2451 seq_printf(s, "dma_irq_en %04x%s" EIGHTBITS "\n", tmp, 2475 seq_printf(s, "dma_irq_en %04x%s" EIGHTBITS "\n", tmp,
2452 (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "", 2476 (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "",
2453 (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "", 2477 (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "",
@@ -2461,29 +2485,29 @@ static int proc_udc_show(struct seq_file *s, void *_)
2461 (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "", 2485 (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "",
2462 (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : ""); 2486 (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : "");
2463 2487
2464 tmp = UDC_RXDMA_CFG_REG; 2488 tmp = omap_readw(UDC_RXDMA_CFG);
2465 seq_printf(s, "rxdma_cfg %04x\n", tmp); 2489 seq_printf(s, "rxdma_cfg %04x\n", tmp);
2466 if (tmp) { 2490 if (tmp) {
2467 for (i = 0; i < 3; i++) { 2491 for (i = 0; i < 3; i++) {
2468 if ((tmp & (0x0f << (i * 4))) == 0) 2492 if ((tmp & (0x0f << (i * 4))) == 0)
2469 continue; 2493 continue;
2470 seq_printf(s, "rxdma[%d] %04x\n", i, 2494 seq_printf(s, "rxdma[%d] %04x\n", i,
2471 UDC_RXDMA_REG(i + 1)); 2495 omap_readw(UDC_RXDMA(i + 1)));
2472 } 2496 }
2473 } 2497 }
2474 tmp = UDC_TXDMA_CFG_REG; 2498 tmp = omap_readw(UDC_TXDMA_CFG);
2475 seq_printf(s, "txdma_cfg %04x\n", tmp); 2499 seq_printf(s, "txdma_cfg %04x\n", tmp);
2476 if (tmp) { 2500 if (tmp) {
2477 for (i = 0; i < 3; i++) { 2501 for (i = 0; i < 3; i++) {
2478 if (!(tmp & (0x0f << (i * 4)))) 2502 if (!(tmp & (0x0f << (i * 4))))
2479 continue; 2503 continue;
2480 seq_printf(s, "txdma[%d] %04x\n", i, 2504 seq_printf(s, "txdma[%d] %04x\n", i,
2481 UDC_TXDMA_REG(i + 1)); 2505 omap_readw(UDC_TXDMA(i + 1)));
2482 } 2506 }
2483 } 2507 }
2484 } 2508 }
2485 2509
2486 tmp = UDC_DEVSTAT_REG; 2510 tmp = omap_readw(UDC_DEVSTAT);
2487 if (tmp & UDC_ATT) { 2511 if (tmp & UDC_ATT) {
2488 proc_ep_show(s, &udc->ep[0]); 2512 proc_ep_show(s, &udc->ep[0]);
2489 if (tmp & UDC_ADD) { 2513 if (tmp & UDC_ADD) {
@@ -2535,7 +2559,7 @@ static inline void remove_proc_file(void) {}
2535 * buffer space among the endpoints we'll be operating. 2559 * buffer space among the endpoints we'll be operating.
2536 * 2560 *
2537 * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when 2561 * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when
2538 * UDC_SYSCON_1_REG.CFG_LOCK is set can now work. We won't use that 2562 * UDC_SYSCON_1.CFG_LOCK is set can now work. We won't use that
2539 * capability yet though. 2563 * capability yet though.
2540 */ 2564 */
2541static unsigned __init 2565static unsigned __init
@@ -2597,9 +2621,9 @@ omap_ep_setup(char *name, u8 addr, u8 type,
2597 name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf); 2621 name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf);
2598 2622
2599 if (addr & USB_DIR_IN) 2623 if (addr & USB_DIR_IN)
2600 UDC_EP_TX_REG(addr & 0xf) = epn_rxtx; 2624 omap_writew(epn_rxtx, UDC_EP_TX(addr & 0xf));
2601 else 2625 else
2602 UDC_EP_RX_REG(addr) = epn_rxtx; 2626 omap_writew(epn_rxtx, UDC_EP_RX(addr));
2603 2627
2604 /* next endpoint's buffer starts after this one's */ 2628 /* next endpoint's buffer starts after this one's */
2605 buf += maxp; 2629 buf += maxp;
@@ -2638,15 +2662,15 @@ omap_udc_setup(struct platform_device *odev, struct otg_transceiver *xceiv)
2638 unsigned tmp, buf; 2662 unsigned tmp, buf;
2639 2663
2640 /* abolish any previous hardware state */ 2664 /* abolish any previous hardware state */
2641 UDC_SYSCON1_REG = 0; 2665 omap_writew(0, UDC_SYSCON1);
2642 UDC_IRQ_EN_REG = 0; 2666 omap_writew(0, UDC_IRQ_EN);
2643 UDC_IRQ_SRC_REG = UDC_IRQ_SRC_MASK; 2667 omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
2644 UDC_DMA_IRQ_EN_REG = 0; 2668 omap_writew(0, UDC_DMA_IRQ_EN);
2645 UDC_RXDMA_CFG_REG = 0; 2669 omap_writew(0, UDC_RXDMA_CFG);
2646 UDC_TXDMA_CFG_REG = 0; 2670 omap_writew(0, UDC_TXDMA_CFG);
2647 2671
2648 /* UDC_PULLUP_EN gates the chip clock */ 2672 /* UDC_PULLUP_EN gates the chip clock */
2649 // OTG_SYSCON_1_REG |= DEV_IDLE_EN; 2673 // OTG_SYSCON_1 |= DEV_IDLE_EN;
2650 2674
2651 udc = kzalloc(sizeof(*udc), GFP_KERNEL); 2675 udc = kzalloc(sizeof(*udc), GFP_KERNEL);
2652 if (!udc) 2676 if (!udc)
@@ -2677,8 +2701,8 @@ omap_udc_setup(struct platform_device *odev, struct otg_transceiver *xceiv)
2677 2701
2678 /* initially disable all non-ep0 endpoints */ 2702 /* initially disable all non-ep0 endpoints */
2679 for (tmp = 1; tmp < 15; tmp++) { 2703 for (tmp = 1; tmp < 15; tmp++) {
2680 UDC_EP_RX_REG(tmp) = 0; 2704 omap_writew(0, UDC_EP_RX(tmp));
2681 UDC_EP_TX_REG(tmp) = 0; 2705 omap_writew(0, UDC_EP_TX(tmp));
2682 } 2706 }
2683 2707
2684#define OMAP_BULK_EP(name,addr) \ 2708#define OMAP_BULK_EP(name,addr) \
@@ -2763,7 +2787,7 @@ omap_udc_setup(struct platform_device *odev, struct otg_transceiver *xceiv)
2763 ERR("unsupported fifo_mode #%d\n", fifo_mode); 2787 ERR("unsupported fifo_mode #%d\n", fifo_mode);
2764 return -ENODEV; 2788 return -ENODEV;
2765 } 2789 }
2766 UDC_SYSCON1_REG = UDC_CFG_LOCK|UDC_SELF_PWR; 2790 omap_writew(UDC_CFG_LOCK|UDC_SELF_PWR, UDC_SYSCON1);
2767 INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf); 2791 INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf);
2768 return 0; 2792 return 0;
2769} 2793}
@@ -2807,7 +2831,7 @@ static int __init omap_udc_probe(struct platform_device *pdev)
2807 } 2831 }
2808 2832
2809 INFO("OMAP UDC rev %d.%d%s\n", 2833 INFO("OMAP UDC rev %d.%d%s\n",
2810 UDC_REV_REG >> 4, UDC_REV_REG & 0xf, 2834 omap_readw(UDC_REV) >> 4, omap_readw(UDC_REV) & 0xf,
2811 config->otg ? ", Mini-AB" : ""); 2835 config->otg ? ", Mini-AB" : "");
2812 2836
2813 /* use the mode given to us by board init code */ 2837 /* use the mode given to us by board init code */
@@ -2822,12 +2846,12 @@ static int __init omap_udc_probe(struct platform_device *pdev)
2822 * know when to turn PULLUP_EN on/off; and that 2846 * know when to turn PULLUP_EN on/off; and that
2823 * means we always "need" the 48MHz clock. 2847 * means we always "need" the 48MHz clock.
2824 */ 2848 */
2825 u32 tmp = FUNC_MUX_CTRL_0_REG; 2849 u32 tmp = omap_readl(FUNC_MUX_CTRL_0);
2826 2850 tmp &= ~VBUS_CTRL_1510;
2827 FUNC_MUX_CTRL_0_REG &= ~VBUS_CTRL_1510; 2851 omap_writel(tmp, FUNC_MUX_CTRL_0);
2828 tmp |= VBUS_MODE_1510; 2852 tmp |= VBUS_MODE_1510;
2829 tmp &= ~VBUS_CTRL_1510; 2853 tmp &= ~VBUS_CTRL_1510;
2830 FUNC_MUX_CTRL_0_REG = tmp; 2854 omap_writel(tmp, FUNC_MUX_CTRL_0);
2831 } 2855 }
2832 } else { 2856 } else {
2833 /* The transceiver may package some GPIO logic or handle 2857 /* The transceiver may package some GPIO logic or handle
@@ -2907,7 +2931,7 @@ known:
2907#endif 2931#endif
2908 2932
2909 /* starting with omap1710 es2.0, clear toggle is a separate bit */ 2933 /* starting with omap1710 es2.0, clear toggle is a separate bit */
2910 if (UDC_REV_REG >= 0x61) 2934 if (omap_readw(UDC_REV) >= 0x61)
2911 udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE; 2935 udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE;
2912 else 2936 else
2913 udc->clr_halt = UDC_RESET_EP; 2937 udc->clr_halt = UDC_RESET_EP;
@@ -3005,7 +3029,7 @@ static int __exit omap_udc_remove(struct platform_device *pdev)
3005 put_device(udc->transceiver->dev); 3029 put_device(udc->transceiver->dev);
3006 udc->transceiver = NULL; 3030 udc->transceiver = NULL;
3007 } 3031 }
3008 UDC_SYSCON1_REG = 0; 3032 omap_writew(0, UDC_SYSCON1);
3009 3033
3010 remove_proc_file(); 3034 remove_proc_file();
3011 3035
@@ -3036,7 +3060,7 @@ static int __exit omap_udc_remove(struct platform_device *pdev)
3036 * 3060 *
3037 * REVISIT we should probably reject suspend requests when there's a host 3061 * REVISIT we should probably reject suspend requests when there's a host
3038 * session active, rather than disconnecting, at least on boards that can 3062 * session active, rather than disconnecting, at least on boards that can
3039 * report VBUS irqs (UDC_DEVSTAT_REG.UDC_ATT). And in any case, we need to 3063 * report VBUS irqs (UDC_DEVSTAT.UDC_ATT). And in any case, we need to
3040 * make host resumes and VBUS detection trigger OMAP wakeup events; that 3064 * make host resumes and VBUS detection trigger OMAP wakeup events; that
3041 * may involve talking to an external transceiver (e.g. isp1301). 3065 * may involve talking to an external transceiver (e.g. isp1301).
3042 */ 3066 */
@@ -3045,7 +3069,7 @@ static int omap_udc_suspend(struct platform_device *dev, pm_message_t message)
3045{ 3069{
3046 u32 devstat; 3070 u32 devstat;
3047 3071
3048 devstat = UDC_DEVSTAT_REG; 3072 devstat = omap_readw(UDC_DEVSTAT);
3049 3073
3050 /* we're requesting 48 MHz clock if the pullup is enabled 3074 /* we're requesting 48 MHz clock if the pullup is enabled
3051 * (== we're attached to the host) and we're not suspended, 3075 * (== we're attached to the host) and we're not suspended,
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 01:07:55 -0500