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path: root/drivers/usb/gadget/omap_udc.c
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Diffstat (limited to 'drivers/usb/gadget/omap_udc.c')
-rw-r--r--drivers/usb/gadget/omap_udc.c301
1 files changed, 205 insertions, 96 deletions
diff --git a/drivers/usb/gadget/omap_udc.c b/drivers/usb/gadget/omap_udc.c
index 98cbcbc16cc1..a2b812af6e66 100644
--- a/drivers/usb/gadget/omap_udc.c
+++ b/drivers/usb/gadget/omap_udc.c
@@ -52,7 +52,6 @@
52#include <asm/mach-types.h> 52#include <asm/mach-types.h>
53 53
54#include <asm/arch/dma.h> 54#include <asm/arch/dma.h>
55#include <asm/arch/mux.h>
56#include <asm/arch/usb.h> 55#include <asm/arch/usb.h>
57 56
58#include "omap_udc.h" 57#include "omap_udc.h"
@@ -167,7 +166,7 @@ static int omap_ep_enable(struct usb_ep *_ep,
167 maxp = le16_to_cpu (desc->wMaxPacketSize); 166 maxp = le16_to_cpu (desc->wMaxPacketSize);
168 if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK 167 if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
169 && maxp != ep->maxpacket) 168 && maxp != ep->maxpacket)
170 || desc->wMaxPacketSize > ep->maxpacket 169 || le16_to_cpu(desc->wMaxPacketSize) > ep->maxpacket
171 || !desc->wMaxPacketSize) { 170 || !desc->wMaxPacketSize) {
172 DBG("%s, bad %s maxpacket\n", __FUNCTION__, _ep->name); 171 DBG("%s, bad %s maxpacket\n", __FUNCTION__, _ep->name);
173 return -ERANGE; 172 return -ERANGE;
@@ -214,7 +213,7 @@ static int omap_ep_enable(struct usb_ep *_ep,
214 ep->has_dma = 0; 213 ep->has_dma = 0;
215 ep->lch = -1; 214 ep->lch = -1;
216 use_ep(ep, UDC_EP_SEL); 215 use_ep(ep, UDC_EP_SEL);
217 UDC_CTRL_REG = UDC_RESET_EP; 216 UDC_CTRL_REG = udc->clr_halt;
218 ep->ackwait = 0; 217 ep->ackwait = 0;
219 deselect_ep(); 218 deselect_ep();
220 219
@@ -253,7 +252,7 @@ static int omap_ep_disable(struct usb_ep *_ep)
253 } 252 }
254 253
255 spin_lock_irqsave(&ep->udc->lock, flags); 254 spin_lock_irqsave(&ep->udc->lock, flags);
256 ep->desc = 0; 255 ep->desc = NULL;
257 nuke (ep, -ESHUTDOWN); 256 nuke (ep, -ESHUTDOWN);
258 ep->ep.maxpacket = ep->maxpacket; 257 ep->ep.maxpacket = ep->maxpacket;
259 ep->has_dma = 0; 258 ep->has_dma = 0;
@@ -388,8 +387,8 @@ done(struct omap_ep *ep, struct omap_req *req, int status)
388 387
389/*-------------------------------------------------------------------------*/ 388/*-------------------------------------------------------------------------*/
390 389
391#define FIFO_FULL (UDC_NON_ISO_FIFO_FULL | UDC_ISO_FIFO_FULL) 390#define UDC_FIFO_FULL (UDC_NON_ISO_FIFO_FULL | UDC_ISO_FIFO_FULL)
392#define FIFO_UNWRITABLE (UDC_EP_HALTED | FIFO_FULL) 391#define UDC_FIFO_UNWRITABLE (UDC_EP_HALTED | UDC_FIFO_FULL)
393 392
394#define FIFO_EMPTY (UDC_NON_ISO_FIFO_EMPTY | UDC_ISO_FIFO_EMPTY) 393#define FIFO_EMPTY (UDC_NON_ISO_FIFO_EMPTY | UDC_ISO_FIFO_EMPTY)
395#define FIFO_UNREADABLE (UDC_EP_HALTED | FIFO_EMPTY) 394#define FIFO_UNREADABLE (UDC_EP_HALTED | FIFO_EMPTY)
@@ -433,7 +432,7 @@ static int write_fifo(struct omap_ep *ep, struct omap_req *req)
433 432
434 /* PIO-IN isn't double buffered except for iso */ 433 /* PIO-IN isn't double buffered except for iso */
435 ep_stat = UDC_STAT_FLG_REG; 434 ep_stat = UDC_STAT_FLG_REG;
436 if (ep_stat & FIFO_UNWRITABLE) 435 if (ep_stat & UDC_FIFO_UNWRITABLE)
437 return 0; 436 return 0;
438 437
439 count = ep->ep.maxpacket; 438 count = ep->ep.maxpacket;
@@ -504,7 +503,7 @@ static int read_fifo(struct omap_ep *ep, struct omap_req *req)
504 if (ep_stat & UDC_EP_HALTED) 503 if (ep_stat & UDC_EP_HALTED)
505 break; 504 break;
506 505
507 if (ep_stat & FIFO_FULL) 506 if (ep_stat & UDC_FIFO_FULL)
508 avail = ep->ep.maxpacket; 507 avail = ep->ep.maxpacket;
509 else { 508 else {
510 avail = UDC_RXFSTAT_REG; 509 avail = UDC_RXFSTAT_REG;
@@ -538,6 +537,32 @@ static int read_fifo(struct omap_ep *ep, struct omap_req *req)
538 537
539/*-------------------------------------------------------------------------*/ 538/*-------------------------------------------------------------------------*/
540 539
540static inline dma_addr_t dma_csac(unsigned lch)
541{
542 dma_addr_t csac;
543
544 /* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
545 * read before the DMA controller finished disabling the channel.
546 */
547 csac = omap_readw(OMAP_DMA_CSAC(lch));
548 if (csac == 0)
549 csac = omap_readw(OMAP_DMA_CSAC(lch));
550 return csac;
551}
552
553static inline dma_addr_t dma_cdac(unsigned lch)
554{
555 dma_addr_t cdac;
556
557 /* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
558 * read before the DMA controller finished disabling the channel.
559 */
560 cdac = omap_readw(OMAP_DMA_CDAC(lch));
561 if (cdac == 0)
562 cdac = omap_readw(OMAP_DMA_CDAC(lch));
563 return cdac;
564}
565
541static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start) 566static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
542{ 567{
543 dma_addr_t end; 568 dma_addr_t end;
@@ -548,7 +573,7 @@ static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
548 if (cpu_is_omap15xx()) 573 if (cpu_is_omap15xx())
549 return 0; 574 return 0;
550 575
551 end = omap_readw(OMAP_DMA_CSAC(ep->lch)); 576 end = dma_csac(ep->lch);
552 if (end == ep->dma_counter) 577 if (end == ep->dma_counter)
553 return 0; 578 return 0;
554 579
@@ -559,14 +584,14 @@ static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
559} 584}
560 585
561#define DMA_DEST_LAST(x) (cpu_is_omap15xx() \ 586#define DMA_DEST_LAST(x) (cpu_is_omap15xx() \
562 ? OMAP_DMA_CSAC(x) /* really: CPC */ \ 587 ? omap_readw(OMAP_DMA_CSAC(x)) /* really: CPC */ \
563 : OMAP_DMA_CDAC(x)) 588 : dma_cdac(x))
564 589
565static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start) 590static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start)
566{ 591{
567 dma_addr_t end; 592 dma_addr_t end;
568 593
569 end = omap_readw(DMA_DEST_LAST(ep->lch)); 594 end = DMA_DEST_LAST(ep->lch);
570 if (end == ep->dma_counter) 595 if (end == ep->dma_counter)
571 return 0; 596 return 0;
572 597
@@ -593,7 +618,7 @@ static void next_in_dma(struct omap_ep *ep, struct omap_req *req)
593 : OMAP_DMA_SYNC_ELEMENT; 618 : OMAP_DMA_SYNC_ELEMENT;
594 619
595 /* measure length in either bytes or packets */ 620 /* measure length in either bytes or packets */
596 if ((cpu_is_omap16xx() && length <= (UDC_TXN_TSC + 1)) 621 if ((cpu_is_omap16xx() && length <= UDC_TXN_TSC)
597 || (cpu_is_omap15xx() && length < ep->maxpacket)) { 622 || (cpu_is_omap15xx() && length < ep->maxpacket)) {
598 txdma_ctrl = UDC_TXN_EOT | length; 623 txdma_ctrl = UDC_TXN_EOT | length;
599 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8, 624 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
@@ -602,15 +627,15 @@ static void next_in_dma(struct omap_ep *ep, struct omap_req *req)
602 length = min(length / ep->maxpacket, 627 length = min(length / ep->maxpacket,
603 (unsigned) UDC_TXN_TSC + 1); 628 (unsigned) UDC_TXN_TSC + 1);
604 txdma_ctrl = length; 629 txdma_ctrl = length;
605 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8, 630 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
606 ep->ep.maxpacket, length, sync_mode); 631 ep->ep.maxpacket >> 1, length, sync_mode);
607 length *= ep->maxpacket; 632 length *= ep->maxpacket;
608 } 633 }
609 omap_set_dma_src_params(ep->lch, OMAP_DMA_PORT_EMIFF, 634 omap_set_dma_src_params(ep->lch, OMAP_DMA_PORT_EMIFF,
610 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual); 635 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual);
611 636
612 omap_start_dma(ep->lch); 637 omap_start_dma(ep->lch);
613 ep->dma_counter = omap_readw(OMAP_DMA_CSAC(ep->lch)); 638 ep->dma_counter = dma_csac(ep->lch);
614 UDC_DMA_IRQ_EN_REG |= UDC_TX_DONE_IE(ep->dma_channel); 639 UDC_DMA_IRQ_EN_REG |= UDC_TX_DONE_IE(ep->dma_channel);
615 UDC_TXDMA_REG(ep->dma_channel) = UDC_TXN_START | txdma_ctrl; 640 UDC_TXDMA_REG(ep->dma_channel) = UDC_TXN_START | txdma_ctrl;
616 req->dma_bytes = length; 641 req->dma_bytes = length;
@@ -650,12 +675,12 @@ static void next_out_dma(struct omap_ep *ep, struct omap_req *req)
650 packets = (req->req.length - req->req.actual) / ep->ep.maxpacket; 675 packets = (req->req.length - req->req.actual) / ep->ep.maxpacket;
651 packets = min(packets, (unsigned)UDC_RXN_TC + 1); 676 packets = min(packets, (unsigned)UDC_RXN_TC + 1);
652 req->dma_bytes = packets * ep->ep.maxpacket; 677 req->dma_bytes = packets * ep->ep.maxpacket;
653 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8, 678 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
654 ep->ep.maxpacket, packets, 679 ep->ep.maxpacket >> 1, packets,
655 OMAP_DMA_SYNC_ELEMENT); 680 OMAP_DMA_SYNC_ELEMENT);
656 omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF, 681 omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF,
657 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual); 682 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual);
658 ep->dma_counter = omap_readw(DMA_DEST_LAST(ep->lch)); 683 ep->dma_counter = DMA_DEST_LAST(ep->lch);
659 684
660 UDC_RXDMA_REG(ep->dma_channel) = UDC_RXN_STOP | (packets - 1); 685 UDC_RXDMA_REG(ep->dma_channel) = UDC_RXN_STOP | (packets - 1);
661 UDC_DMA_IRQ_EN_REG |= UDC_RX_EOT_IE(ep->dma_channel); 686 UDC_DMA_IRQ_EN_REG |= UDC_RX_EOT_IE(ep->dma_channel);
@@ -763,7 +788,7 @@ static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
763 reg = UDC_TXDMA_CFG_REG; 788 reg = UDC_TXDMA_CFG_REG;
764 else 789 else
765 reg = UDC_RXDMA_CFG_REG; 790 reg = UDC_RXDMA_CFG_REG;
766 reg |= 1 << 12; /* "pulse" activated */ 791 reg |= UDC_DMA_REQ; /* "pulse" activated */
767 792
768 ep->dma_channel = 0; 793 ep->dma_channel = 0;
769 ep->lch = -1; 794 ep->lch = -1;
@@ -787,6 +812,11 @@ static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
787 ep->ep.name, dma_error, ep, &ep->lch); 812 ep->ep.name, dma_error, ep, &ep->lch);
788 if (status == 0) { 813 if (status == 0) {
789 UDC_TXDMA_CFG_REG = reg; 814 UDC_TXDMA_CFG_REG = reg;
815 /* EMIFF */
816 omap_set_dma_src_burst_mode(ep->lch,
817 OMAP_DMA_DATA_BURST_4);
818 omap_set_dma_src_data_pack(ep->lch, 1);
819 /* TIPB */
790 omap_set_dma_dest_params(ep->lch, 820 omap_set_dma_dest_params(ep->lch,
791 OMAP_DMA_PORT_TIPB, 821 OMAP_DMA_PORT_TIPB,
792 OMAP_DMA_AMODE_CONSTANT, 822 OMAP_DMA_AMODE_CONSTANT,
@@ -797,10 +827,15 @@ static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
797 ep->ep.name, dma_error, ep, &ep->lch); 827 ep->ep.name, dma_error, ep, &ep->lch);
798 if (status == 0) { 828 if (status == 0) {
799 UDC_RXDMA_CFG_REG = reg; 829 UDC_RXDMA_CFG_REG = reg;
830 /* TIPB */
800 omap_set_dma_src_params(ep->lch, 831 omap_set_dma_src_params(ep->lch,
801 OMAP_DMA_PORT_TIPB, 832 OMAP_DMA_PORT_TIPB,
802 OMAP_DMA_AMODE_CONSTANT, 833 OMAP_DMA_AMODE_CONSTANT,
803 (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG)); 834 (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG));
835 /* EMIFF */
836 omap_set_dma_dest_burst_mode(ep->lch,
837 OMAP_DMA_DATA_BURST_4);
838 omap_set_dma_dest_data_pack(ep->lch, 1);
804 } 839 }
805 } 840 }
806 if (status) 841 if (status)
@@ -856,7 +891,7 @@ static void dma_channel_release(struct omap_ep *ep)
856 if (!list_empty(&ep->queue)) 891 if (!list_empty(&ep->queue))
857 req = container_of(ep->queue.next, struct omap_req, queue); 892 req = container_of(ep->queue.next, struct omap_req, queue);
858 else 893 else
859 req = 0; 894 req = NULL;
860 895
861 active = ((1 << 7) & omap_readl(OMAP_DMA_CCR(ep->lch))) != 0; 896 active = ((1 << 7) & omap_readl(OMAP_DMA_CCR(ep->lch))) != 0;
862 897
@@ -865,9 +900,13 @@ static void dma_channel_release(struct omap_ep *ep)
865 (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r', 900 (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
866 ep->dma_channel - 1, req); 901 ep->dma_channel - 1, req);
867 902
903 /* NOTE: re-setting RX_REQ/TX_REQ because of a chip bug (before
904 * OMAP 1710 ES2.0) where reading the DMA_CFG can clear them.
905 */
906
868 /* wait till current packet DMA finishes, and fifo empties */ 907 /* wait till current packet DMA finishes, and fifo empties */
869 if (ep->bEndpointAddress & USB_DIR_IN) { 908 if (ep->bEndpointAddress & USB_DIR_IN) {
870 UDC_TXDMA_CFG_REG &= ~mask; 909 UDC_TXDMA_CFG_REG = (UDC_TXDMA_CFG_REG & ~mask) | UDC_DMA_REQ;
871 910
872 if (req) { 911 if (req) {
873 finish_in_dma(ep, req, -ECONNRESET); 912 finish_in_dma(ep, req, -ECONNRESET);
@@ -880,7 +919,7 @@ static void dma_channel_release(struct omap_ep *ep)
880 while (UDC_TXDMA_CFG_REG & mask) 919 while (UDC_TXDMA_CFG_REG & mask)
881 udelay(10); 920 udelay(10);
882 } else { 921 } else {
883 UDC_RXDMA_CFG_REG &= ~mask; 922 UDC_RXDMA_CFG_REG = (UDC_RXDMA_CFG_REG & ~mask) | UDC_DMA_REQ;
884 923
885 /* dma empties the fifo */ 924 /* dma empties the fifo */
886 while (UDC_RXDMA_CFG_REG & mask) 925 while (UDC_RXDMA_CFG_REG & mask)
@@ -997,18 +1036,19 @@ omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, int gfp_flags)
997 UDC_IRQ_EN_REG = irq_en; 1036 UDC_IRQ_EN_REG = irq_en;
998 } 1037 }
999 1038
1000 /* STATUS is reverse direction */ 1039 /* STATUS for zero length DATA stages is
1001 UDC_EP_NUM_REG = is_in 1040 * always an IN ... even for IN transfers,
1002 ? UDC_EP_SEL 1041 * a wierd case which seem to stall OMAP.
1003 : (UDC_EP_SEL|UDC_EP_DIR); 1042 */
1043 UDC_EP_NUM_REG = (UDC_EP_SEL|UDC_EP_DIR);
1004 UDC_CTRL_REG = UDC_CLR_EP; 1044 UDC_CTRL_REG = UDC_CLR_EP;
1005 UDC_CTRL_REG = UDC_SET_FIFO_EN; 1045 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1006 UDC_EP_NUM_REG = udc->ep0_in ? 0 : UDC_EP_DIR; 1046 UDC_EP_NUM_REG = UDC_EP_DIR;
1007 1047
1008 /* cleanup */ 1048 /* cleanup */
1009 udc->ep0_pending = 0; 1049 udc->ep0_pending = 0;
1010 done(ep, req, 0); 1050 done(ep, req, 0);
1011 req = 0; 1051 req = NULL;
1012 1052
1013 /* non-empty DATA stage */ 1053 /* non-empty DATA stage */
1014 } else if (is_in) { 1054 } else if (is_in) {
@@ -1029,7 +1069,7 @@ omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, int gfp_flags)
1029 (is_in ? next_in_dma : next_out_dma)(ep, req); 1069 (is_in ? next_in_dma : next_out_dma)(ep, req);
1030 else if (req) { 1070 else if (req) {
1031 if ((is_in ? write_fifo : read_fifo)(ep, req) == 1) 1071 if ((is_in ? write_fifo : read_fifo)(ep, req) == 1)
1032 req = 0; 1072 req = NULL;
1033 deselect_ep(); 1073 deselect_ep();
1034 if (!is_in) { 1074 if (!is_in) {
1035 UDC_CTRL_REG = UDC_SET_FIFO_EN; 1075 UDC_CTRL_REG = UDC_SET_FIFO_EN;
@@ -1041,7 +1081,7 @@ omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, int gfp_flags)
1041 1081
1042irq_wait: 1082irq_wait:
1043 /* irq handler advances the queue */ 1083 /* irq handler advances the queue */
1044 if (req != 0) 1084 if (req != NULL)
1045 list_add_tail(&req->queue, &ep->queue); 1085 list_add_tail(&req->queue, &ep->queue);
1046 spin_unlock_irqrestore(&udc->lock, flags); 1086 spin_unlock_irqrestore(&udc->lock, flags);
1047 1087
@@ -1140,7 +1180,7 @@ static int omap_ep_set_halt(struct usb_ep *_ep, int value)
1140 dma_channel_claim(ep, channel); 1180 dma_channel_claim(ep, channel);
1141 } else { 1181 } else {
1142 use_ep(ep, 0); 1182 use_ep(ep, 0);
1143 UDC_CTRL_REG = UDC_RESET_EP; 1183 UDC_CTRL_REG = ep->udc->clr_halt;
1144 ep->ackwait = 0; 1184 ep->ackwait = 0;
1145 if (!(ep->bEndpointAddress & USB_DIR_IN)) { 1185 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1146 UDC_CTRL_REG = UDC_SET_FIFO_EN; 1186 UDC_CTRL_REG = UDC_SET_FIFO_EN;
@@ -1238,6 +1278,8 @@ static int can_pullup(struct omap_udc *udc)
1238 1278
1239static void pullup_enable(struct omap_udc *udc) 1279static void pullup_enable(struct omap_udc *udc)
1240{ 1280{
1281 udc->gadget.dev.parent->power.power_state = PMSG_ON;
1282 udc->gadget.dev.power.power_state = PMSG_ON;
1241 UDC_SYSCON1_REG |= UDC_PULLUP_EN; 1283 UDC_SYSCON1_REG |= UDC_PULLUP_EN;
1242#ifndef CONFIG_USB_OTG 1284#ifndef CONFIG_USB_OTG
1243 if (!cpu_is_omap15xx()) 1285 if (!cpu_is_omap15xx())
@@ -1382,7 +1424,7 @@ static void update_otg(struct omap_udc *udc)
1382static void ep0_irq(struct omap_udc *udc, u16 irq_src) 1424static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1383{ 1425{
1384 struct omap_ep *ep0 = &udc->ep[0]; 1426 struct omap_ep *ep0 = &udc->ep[0];
1385 struct omap_req *req = 0; 1427 struct omap_req *req = NULL;
1386 1428
1387 ep0->irqs++; 1429 ep0->irqs++;
1388 1430
@@ -1438,7 +1480,7 @@ static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1438 if (req) 1480 if (req)
1439 done(ep0, req, 0); 1481 done(ep0, req, 0);
1440 } 1482 }
1441 req = 0; 1483 req = NULL;
1442 } else if (stat & UDC_STALL) { 1484 } else if (stat & UDC_STALL) {
1443 UDC_CTRL_REG = UDC_CLR_HALT; 1485 UDC_CTRL_REG = UDC_CLR_HALT;
1444 UDC_EP_NUM_REG = UDC_EP_DIR; 1486 UDC_EP_NUM_REG = UDC_EP_DIR;
@@ -1511,9 +1553,10 @@ static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1511 u.word[3] = UDC_DATA_REG; 1553 u.word[3] = UDC_DATA_REG;
1512 UDC_EP_NUM_REG = 0; 1554 UDC_EP_NUM_REG = 0;
1513 } while (UDC_IRQ_SRC_REG & UDC_SETUP); 1555 } while (UDC_IRQ_SRC_REG & UDC_SETUP);
1514 le16_to_cpus (&u.r.wValue); 1556
1515 le16_to_cpus (&u.r.wIndex); 1557#define w_value le16_to_cpup (&u.r.wValue)
1516 le16_to_cpus (&u.r.wLength); 1558#define w_index le16_to_cpup (&u.r.wIndex)
1559#define w_length le16_to_cpup (&u.r.wLength)
1517 1560
1518 /* Delegate almost all control requests to the gadget driver, 1561 /* Delegate almost all control requests to the gadget driver,
1519 * except for a handful of ch9 status/feature requests that 1562 * except for a handful of ch9 status/feature requests that
@@ -1529,11 +1572,11 @@ static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1529 /* udc needs to know when ep != 0 is valid */ 1572 /* udc needs to know when ep != 0 is valid */
1530 if (u.r.bRequestType != USB_RECIP_DEVICE) 1573 if (u.r.bRequestType != USB_RECIP_DEVICE)
1531 goto delegate; 1574 goto delegate;
1532 if (u.r.wLength != 0) 1575 if (w_length != 0)
1533 goto do_stall; 1576 goto do_stall;
1534 udc->ep0_set_config = 1; 1577 udc->ep0_set_config = 1;
1535 udc->ep0_reset_config = (u.r.wValue == 0); 1578 udc->ep0_reset_config = (w_value == 0);
1536 VDBG("set config %d\n", u.r.wValue); 1579 VDBG("set config %d\n", w_value);
1537 1580
1538 /* update udc NOW since gadget driver may start 1581 /* update udc NOW since gadget driver may start
1539 * queueing requests immediately; clear config 1582 * queueing requests immediately; clear config
@@ -1549,23 +1592,28 @@ static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1549 /* clear endpoint halt */ 1592 /* clear endpoint halt */
1550 if (u.r.bRequestType != USB_RECIP_ENDPOINT) 1593 if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1551 goto delegate; 1594 goto delegate;
1552 if (u.r.wValue != USB_ENDPOINT_HALT 1595 if (w_value != USB_ENDPOINT_HALT
1553 || u.r.wLength != 0) 1596 || w_length != 0)
1554 goto do_stall; 1597 goto do_stall;
1555 ep = &udc->ep[u.r.wIndex & 0xf]; 1598 ep = &udc->ep[w_index & 0xf];
1556 if (ep != ep0) { 1599 if (ep != ep0) {
1557 if (u.r.wIndex & USB_DIR_IN) 1600 if (w_index & USB_DIR_IN)
1558 ep += 16; 1601 ep += 16;
1559 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC 1602 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1560 || !ep->desc) 1603 || !ep->desc)
1561 goto do_stall; 1604 goto do_stall;
1562 use_ep(ep, 0); 1605 use_ep(ep, 0);
1563 UDC_CTRL_REG = UDC_RESET_EP; 1606 UDC_CTRL_REG = udc->clr_halt;
1564 ep->ackwait = 0; 1607 ep->ackwait = 0;
1565 if (!(ep->bEndpointAddress & USB_DIR_IN)) { 1608 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1566 UDC_CTRL_REG = UDC_SET_FIFO_EN; 1609 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1567 ep->ackwait = 1 + ep->double_buf; 1610 ep->ackwait = 1 + ep->double_buf;
1568 } 1611 }
1612 /* NOTE: assumes the host behaves sanely,
1613 * only clearing real halts. Else we may
1614 * need to kill pending transfers and then
1615 * restart the queue... very messy for DMA!
1616 */
1569 } 1617 }
1570 VDBG("%s halt cleared by host\n", ep->name); 1618 VDBG("%s halt cleared by host\n", ep->name);
1571 goto ep0out_status_stage; 1619 goto ep0out_status_stage;
@@ -1573,11 +1621,11 @@ static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1573 /* set endpoint halt */ 1621 /* set endpoint halt */
1574 if (u.r.bRequestType != USB_RECIP_ENDPOINT) 1622 if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1575 goto delegate; 1623 goto delegate;
1576 if (u.r.wValue != USB_ENDPOINT_HALT 1624 if (w_value != USB_ENDPOINT_HALT
1577 || u.r.wLength != 0) 1625 || w_length != 0)
1578 goto do_stall; 1626 goto do_stall;
1579 ep = &udc->ep[u.r.wIndex & 0xf]; 1627 ep = &udc->ep[w_index & 0xf];
1580 if (u.r.wIndex & USB_DIR_IN) 1628 if (w_index & USB_DIR_IN)
1581 ep += 16; 1629 ep += 16;
1582 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC 1630 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1583 || ep == ep0 || !ep->desc) 1631 || ep == ep0 || !ep->desc)
@@ -1615,13 +1663,13 @@ ep0out_status_stage:
1615 UDC_CTRL_REG = UDC_SET_FIFO_EN; 1663 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1616 UDC_EP_NUM_REG = UDC_EP_DIR; 1664 UDC_EP_NUM_REG = UDC_EP_DIR;
1617 status = 0; 1665 status = 0;
1618 VDBG("GET_STATUS, interface %d\n", u.r.wIndex); 1666 VDBG("GET_STATUS, interface %d\n", w_index);
1619 /* next, status stage */ 1667 /* next, status stage */
1620 break; 1668 break;
1621 default: 1669 default:
1622delegate: 1670delegate:
1623 /* activate the ep0out fifo right away */ 1671 /* activate the ep0out fifo right away */
1624 if (!udc->ep0_in && u.r.wLength) { 1672 if (!udc->ep0_in && w_length) {
1625 UDC_EP_NUM_REG = 0; 1673 UDC_EP_NUM_REG = 0;
1626 UDC_CTRL_REG = UDC_SET_FIFO_EN; 1674 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1627 } 1675 }
@@ -1632,7 +1680,11 @@ delegate:
1632 */ 1680 */
1633 VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n", 1681 VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n",
1634 u.r.bRequestType, u.r.bRequest, 1682 u.r.bRequestType, u.r.bRequest,
1635 u.r.wValue, u.r.wIndex, u.r.wLength); 1683 w_value, w_index, w_length);
1684
1685#undef w_value
1686#undef w_index
1687#undef w_length
1636 1688
1637 /* The gadget driver may return an error here, 1689 /* The gadget driver may return an error here,
1638 * causing an immediate protocol stall. 1690 * causing an immediate protocol stall.
@@ -2013,7 +2065,7 @@ int usb_gadget_register_driver (struct usb_gadget_driver *driver)
2013 udc->softconnect = 1; 2065 udc->softconnect = 1;
2014 2066
2015 /* hook up the driver */ 2067 /* hook up the driver */
2016 driver->driver.bus = 0; 2068 driver->driver.bus = NULL;
2017 udc->driver = driver; 2069 udc->driver = driver;
2018 udc->gadget.dev.driver = &driver->driver; 2070 udc->gadget.dev.driver = &driver->driver;
2019 spin_unlock_irqrestore(&udc->lock, flags); 2071 spin_unlock_irqrestore(&udc->lock, flags);
@@ -2021,8 +2073,8 @@ int usb_gadget_register_driver (struct usb_gadget_driver *driver)
2021 status = driver->bind (&udc->gadget); 2073 status = driver->bind (&udc->gadget);
2022 if (status) { 2074 if (status) {
2023 DBG("bind to %s --> %d\n", driver->driver.name, status); 2075 DBG("bind to %s --> %d\n", driver->driver.name, status);
2024 udc->gadget.dev.driver = 0; 2076 udc->gadget.dev.driver = NULL;
2025 udc->driver = 0; 2077 udc->driver = NULL;
2026 goto done; 2078 goto done;
2027 } 2079 }
2028 DBG("bound to driver %s\n", driver->driver.name); 2080 DBG("bound to driver %s\n", driver->driver.name);
@@ -2035,8 +2087,8 @@ int usb_gadget_register_driver (struct usb_gadget_driver *driver)
2035 if (status < 0) { 2087 if (status < 0) {
2036 ERR("can't bind to transceiver\n"); 2088 ERR("can't bind to transceiver\n");
2037 driver->unbind (&udc->gadget); 2089 driver->unbind (&udc->gadget);
2038 udc->gadget.dev.driver = 0; 2090 udc->gadget.dev.driver = NULL;
2039 udc->driver = 0; 2091 udc->driver = NULL;
2040 goto done; 2092 goto done;
2041 } 2093 }
2042 } else { 2094 } else {
@@ -2071,7 +2123,7 @@ int usb_gadget_unregister_driver (struct usb_gadget_driver *driver)
2071 omap_vbus_session(&udc->gadget, 0); 2123 omap_vbus_session(&udc->gadget, 0);
2072 2124
2073 if (udc->transceiver) 2125 if (udc->transceiver)
2074 (void) otg_set_peripheral(udc->transceiver, 0); 2126 (void) otg_set_peripheral(udc->transceiver, NULL);
2075 else 2127 else
2076 pullup_disable(udc); 2128 pullup_disable(udc);
2077 2129
@@ -2080,9 +2132,8 @@ int usb_gadget_unregister_driver (struct usb_gadget_driver *driver)
2080 spin_unlock_irqrestore(&udc->lock, flags); 2132 spin_unlock_irqrestore(&udc->lock, flags);
2081 2133
2082 driver->unbind(&udc->gadget); 2134 driver->unbind(&udc->gadget);
2083 udc->gadget.dev.driver = 0; 2135 udc->gadget.dev.driver = NULL;
2084 udc->driver = 0; 2136 udc->driver = NULL;
2085
2086 2137
2087 DBG("unregistered driver '%s'\n", driver->driver.name); 2138 DBG("unregistered driver '%s'\n", driver->driver.name);
2088 return status; 2139 return status;
@@ -2178,14 +2229,14 @@ static int proc_otg_show(struct seq_file *s)
2178 2229
2179 tmp = OTG_REV_REG; 2230 tmp = OTG_REV_REG;
2180 trans = USB_TRANSCEIVER_CTRL_REG; 2231 trans = USB_TRANSCEIVER_CTRL_REG;
2181 seq_printf(s, "OTG rev %d.%d, transceiver_ctrl %03x\n", 2232 seq_printf(s, "\nOTG rev %d.%d, transceiver_ctrl %05x\n",
2182 tmp >> 4, tmp & 0xf, trans); 2233 tmp >> 4, tmp & 0xf, trans);
2183 tmp = OTG_SYSCON_1_REG; 2234 tmp = OTG_SYSCON_1_REG;
2184 seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s," 2235 seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s,"
2185 FOURBITS "\n", tmp, 2236 FOURBITS "\n", tmp,
2186 trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R), 2237 trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R),
2187 trx_mode(USB1_TRX_MODE(tmp), trans & CONF_USB1_UNI_R), 2238 trx_mode(USB1_TRX_MODE(tmp), trans & CONF_USB1_UNI_R),
2188 (USB0_TRX_MODE(tmp) == 0) 2239 (USB0_TRX_MODE(tmp) == 0 && !cpu_is_omap1710())
2189 ? "internal" 2240 ? "internal"
2190 : trx_mode(USB0_TRX_MODE(tmp), 1), 2241 : trx_mode(USB0_TRX_MODE(tmp), 1),
2191 (tmp & OTG_IDLE_EN) ? " !otg" : "", 2242 (tmp & OTG_IDLE_EN) ? " !otg" : "",
@@ -2235,6 +2286,7 @@ static int proc_otg_show(struct seq_file *s)
2235 seq_printf(s, "otg_outctrl %04x" "\n", tmp); 2286 seq_printf(s, "otg_outctrl %04x" "\n", tmp);
2236 tmp = OTG_TEST_REG; 2287 tmp = OTG_TEST_REG;
2237 seq_printf(s, "otg_test %04x" "\n", tmp); 2288 seq_printf(s, "otg_test %04x" "\n", tmp);
2289 return 0;
2238} 2290}
2239 2291
2240static int proc_udc_show(struct seq_file *s, void *_) 2292static int proc_udc_show(struct seq_file *s, void *_)
@@ -2378,7 +2430,7 @@ static int proc_udc_show(struct seq_file *s, void *_)
2378 2430
2379static int proc_udc_open(struct inode *inode, struct file *file) 2431static int proc_udc_open(struct inode *inode, struct file *file)
2380{ 2432{
2381 return single_open(file, proc_udc_show, 0); 2433 return single_open(file, proc_udc_show, NULL);
2382} 2434}
2383 2435
2384static struct file_operations proc_ops = { 2436static struct file_operations proc_ops = {
@@ -2399,7 +2451,7 @@ static void create_proc_file(void)
2399 2451
2400static void remove_proc_file(void) 2452static void remove_proc_file(void)
2401{ 2453{
2402 remove_proc_entry(proc_filename, 0); 2454 remove_proc_entry(proc_filename, NULL);
2403} 2455}
2404 2456
2405#else 2457#else
@@ -2414,6 +2466,10 @@ static inline void remove_proc_file(void) {}
2414/* Before this controller can enumerate, we need to pick an endpoint 2466/* Before this controller can enumerate, we need to pick an endpoint
2415 * configuration, or "fifo_mode" That involves allocating 2KB of packet 2467 * configuration, or "fifo_mode" That involves allocating 2KB of packet
2416 * buffer space among the endpoints we'll be operating. 2468 * buffer space among the endpoints we'll be operating.
2469 *
2470 * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when
2471 * UDC_SYSCON_1_REG.CFG_LOCK is set can now work. We won't use that
2472 * capability yet though.
2417 */ 2473 */
2418static unsigned __init 2474static unsigned __init
2419omap_ep_setup(char *name, u8 addr, u8 type, 2475omap_ep_setup(char *name, u8 addr, u8 type,
@@ -2505,7 +2561,7 @@ static void omap_udc_release(struct device *dev)
2505{ 2561{
2506 complete(udc->done); 2562 complete(udc->done);
2507 kfree (udc); 2563 kfree (udc);
2508 udc = 0; 2564 udc = NULL;
2509} 2565}
2510 2566
2511static int __init 2567static int __init
@@ -2577,23 +2633,33 @@ omap_udc_setup(struct platform_device *odev, struct otg_transceiver *xceiv)
2577 case 1: 2633 case 1:
2578 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1); 2634 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
2579 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2); 2635 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2636 OMAP_INT_EP("ep9in", USB_DIR_IN | 9, 16);
2637
2580 OMAP_BULK_EP("ep3in", USB_DIR_IN | 3); 2638 OMAP_BULK_EP("ep3in", USB_DIR_IN | 3);
2581 OMAP_BULK_EP("ep4out", USB_DIR_OUT | 4); 2639 OMAP_BULK_EP("ep4out", USB_DIR_OUT | 4);
2640 OMAP_INT_EP("ep10in", USB_DIR_IN | 10, 16);
2582 2641
2583 OMAP_BULK_EP("ep5in", USB_DIR_IN | 5); 2642 OMAP_BULK_EP("ep5in", USB_DIR_IN | 5);
2584 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5); 2643 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2644 OMAP_INT_EP("ep11in", USB_DIR_IN | 11, 16);
2645
2585 OMAP_BULK_EP("ep6in", USB_DIR_IN | 6); 2646 OMAP_BULK_EP("ep6in", USB_DIR_IN | 6);
2586 OMAP_BULK_EP("ep6out", USB_DIR_OUT | 6); 2647 OMAP_BULK_EP("ep6out", USB_DIR_OUT | 6);
2648 OMAP_INT_EP("ep12in", USB_DIR_IN | 12, 16);
2587 2649
2588 OMAP_BULK_EP("ep7in", USB_DIR_IN | 7); 2650 OMAP_BULK_EP("ep7in", USB_DIR_IN | 7);
2589 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7); 2651 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2652 OMAP_INT_EP("ep13in", USB_DIR_IN | 13, 16);
2653 OMAP_INT_EP("ep13out", USB_DIR_OUT | 13, 16);
2654
2590 OMAP_BULK_EP("ep8in", USB_DIR_IN | 8); 2655 OMAP_BULK_EP("ep8in", USB_DIR_IN | 8);
2591 OMAP_BULK_EP("ep8out", USB_DIR_OUT | 8); 2656 OMAP_BULK_EP("ep8out", USB_DIR_OUT | 8);
2657 OMAP_INT_EP("ep14in", USB_DIR_IN | 14, 16);
2658 OMAP_INT_EP("ep14out", USB_DIR_OUT | 14, 16);
2659
2660 OMAP_BULK_EP("ep15in", USB_DIR_IN | 15);
2661 OMAP_BULK_EP("ep15out", USB_DIR_OUT | 15);
2592 2662
2593 OMAP_INT_EP("ep9in", USB_DIR_IN | 9, 16);
2594 OMAP_INT_EP("ep10out", USB_DIR_IN | 10, 16);
2595 OMAP_INT_EP("ep11in", USB_DIR_IN | 9, 16);
2596 OMAP_INT_EP("ep12out", USB_DIR_IN | 10, 16);
2597 break; 2663 break;
2598 2664
2599#ifdef USE_ISO 2665#ifdef USE_ISO
@@ -2640,8 +2706,8 @@ static int __init omap_udc_probe(struct device *dev)
2640 struct platform_device *odev = to_platform_device(dev); 2706 struct platform_device *odev = to_platform_device(dev);
2641 int status = -ENODEV; 2707 int status = -ENODEV;
2642 int hmc; 2708 int hmc;
2643 struct otg_transceiver *xceiv = 0; 2709 struct otg_transceiver *xceiv = NULL;
2644 const char *type = 0; 2710 const char *type = NULL;
2645 struct omap_usb_config *config = dev->platform_data; 2711 struct omap_usb_config *config = dev->platform_data;
2646 2712
2647 /* NOTE: "knows" the order of the resources! */ 2713 /* NOTE: "knows" the order of the resources! */
@@ -2676,54 +2742,78 @@ static int __init omap_udc_probe(struct device *dev)
2676 FUNC_MUX_CTRL_0_REG = tmp; 2742 FUNC_MUX_CTRL_0_REG = tmp;
2677 } 2743 }
2678 } else { 2744 } else {
2745 /* The transceiver may package some GPIO logic or handle
2746 * loopback and/or transceiverless setup; if we find one,
2747 * use it. Except for OTG, we don't _need_ to talk to one;
2748 * but not having one probably means no VBUS detection.
2749 */
2750 xceiv = otg_get_transceiver();
2751 if (xceiv)
2752 type = xceiv->label;
2753 else if (config->otg) {
2754 DBG("OTG requires external transceiver!\n");
2755 goto cleanup0;
2756 }
2757
2679 hmc = HMC_1610; 2758 hmc = HMC_1610;
2680 switch (hmc) { 2759 switch (hmc) {
2760 case 0: /* POWERUP DEFAULT == 0 */
2761 case 4:
2762 case 12:
2763 case 20:
2764 if (!cpu_is_omap1710()) {
2765 type = "integrated";
2766 break;
2767 }
2768 /* FALL THROUGH */
2681 case 3: 2769 case 3:
2682 case 11: 2770 case 11:
2683 case 16: 2771 case 16:
2684 case 19: 2772 case 19:
2685 case 25: 2773 case 25:
2686 xceiv = otg_get_transceiver();
2687 if (!xceiv) { 2774 if (!xceiv) {
2688 DBG("external transceiver not registered!\n"); 2775 DBG("external transceiver not registered!\n");
2689 if (config->otg) 2776 type = "unknown";
2690 goto cleanup0; 2777 }
2691 type = "(unknown external)";
2692 } else
2693 type = xceiv->label;
2694 break;
2695 case 0: /* POWERUP DEFAULT == 0 */
2696 case 4:
2697 case 12:
2698 case 20:
2699 type = "INTEGRATED";
2700 break; 2778 break;
2701 case 21: /* internal loopback */ 2779 case 21: /* internal loopback */
2702 type = "(loopback)"; 2780 type = "loopback";
2703 break; 2781 break;
2704 case 14: /* transceiverless */ 2782 case 14: /* transceiverless */
2705 type = "(none)"; 2783 if (cpu_is_omap1710())
2784 goto bad_on_1710;
2785 /* FALL THROUGH */
2786 case 13:
2787 case 15:
2788 type = "no";
2706 break; 2789 break;
2707 2790
2708 default: 2791 default:
2792bad_on_1710:
2709 ERR("unrecognized UDC HMC mode %d\n", hmc); 2793 ERR("unrecognized UDC HMC mode %d\n", hmc);
2710 return -ENODEV; 2794 goto cleanup0;
2711 } 2795 }
2712 } 2796 }
2713 INFO("hmc mode %d, transceiver %s\n", hmc, type); 2797 INFO("hmc mode %d, %s transceiver\n", hmc, type);
2714 2798
2715 /* a "gadget" abstracts/virtualizes the controller */ 2799 /* a "gadget" abstracts/virtualizes the controller */
2716 status = omap_udc_setup(odev, xceiv); 2800 status = omap_udc_setup(odev, xceiv);
2717 if (status) { 2801 if (status) {
2718 goto cleanup0; 2802 goto cleanup0;
2719 } 2803 }
2720 xceiv = 0; 2804 xceiv = NULL;
2721 // "udc" is now valid 2805 // "udc" is now valid
2722 pullup_disable(udc); 2806 pullup_disable(udc);
2723#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) 2807#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
2724 udc->gadget.is_otg = (config->otg != 0); 2808 udc->gadget.is_otg = (config->otg != 0);
2725#endif 2809#endif
2726 2810
2811 /* starting with omap1710 es2.0, clear toggle is a separate bit */
2812 if (UDC_REV_REG >= 0x61)
2813 udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE;
2814 else
2815 udc->clr_halt = UDC_RESET_EP;
2816
2727 /* USB general purpose IRQ: ep0, state changes, dma, etc */ 2817 /* USB general purpose IRQ: ep0, state changes, dma, etc */
2728 status = request_irq(odev->resource[1].start, omap_udc_irq, 2818 status = request_irq(odev->resource[1].start, omap_udc_irq,
2729 SA_SAMPLE_RANDOM, driver_name, udc); 2819 SA_SAMPLE_RANDOM, driver_name, udc);
@@ -2765,7 +2855,7 @@ cleanup2:
2765 2855
2766cleanup1: 2856cleanup1:
2767 kfree (udc); 2857 kfree (udc);
2768 udc = 0; 2858 udc = NULL;
2769 2859
2770cleanup0: 2860cleanup0:
2771 if (xceiv) 2861 if (xceiv)
@@ -2788,7 +2878,7 @@ static int __exit omap_udc_remove(struct device *dev)
2788 pullup_disable(udc); 2878 pullup_disable(udc);
2789 if (udc->transceiver) { 2879 if (udc->transceiver) {
2790 put_device(udc->transceiver->dev); 2880 put_device(udc->transceiver->dev);
2791 udc->transceiver = 0; 2881 udc->transceiver = NULL;
2792 } 2882 }
2793 UDC_SYSCON1_REG = 0; 2883 UDC_SYSCON1_REG = 0;
2794 2884
@@ -2809,13 +2899,32 @@ static int __exit omap_udc_remove(struct device *dev)
2809 return 0; 2899 return 0;
2810} 2900}
2811 2901
2812static int omap_udc_suspend(struct device *dev, pm_message_t state, u32 level) 2902/* suspend/resume/wakeup from sysfs (echo > power/state) or when the
2903 * system is forced into deep sleep
2904 *
2905 * REVISIT we should probably reject suspend requests when there's a host
2906 * session active, rather than disconnecting, at least on boards that can
2907 * report VBUS irqs (UDC_DEVSTAT_REG.UDC_ATT). And in any case, we need to
2908 * make host resumes and VBUS detection trigger OMAP wakeup events; that
2909 * may involve talking to an external transceiver (e.g. isp1301).
2910 */
2911static int omap_udc_suspend(struct device *dev, pm_message_t message, u32 level)
2813{ 2912{
2814 if (level != 0) 2913 u32 devstat;
2914
2915 if (level != SUSPEND_POWER_DOWN)
2815 return 0; 2916 return 0;
2917 devstat = UDC_DEVSTAT_REG;
2918
2919 /* we're requesting 48 MHz clock if the pullup is enabled
2920 * (== we're attached to the host) and we're not suspended,
2921 * which would prevent entry to deep sleep...
2922 */
2923 if ((devstat & UDC_ATT) != 0 && (devstat & UDC_SUS) == 0) {
2924 WARN("session active; suspend requires disconnect\n");
2925 omap_pullup(&udc->gadget, 0);
2926 }
2816 2927
2817 DBG("suspend, state %d\n", state);
2818 omap_pullup(&udc->gadget, 0);
2819 udc->gadget.dev.power.power_state = PMSG_SUSPEND; 2928 udc->gadget.dev.power.power_state = PMSG_SUSPEND;
2820 udc->gadget.dev.parent->power.power_state = PMSG_SUSPEND; 2929 udc->gadget.dev.parent->power.power_state = PMSG_SUSPEND;
2821 return 0; 2930 return 0;
@@ -2823,7 +2932,7 @@ static int omap_udc_suspend(struct device *dev, pm_message_t state, u32 level)
2823 2932
2824static int omap_udc_resume(struct device *dev, u32 level) 2933static int omap_udc_resume(struct device *dev, u32 level)
2825{ 2934{
2826 if (level != 0) 2935 if (level != RESUME_POWER_ON)
2827 return 0; 2936 return 0;
2828 2937
2829 DBG("resume + wakeup/SRP\n"); 2938 DBG("resume + wakeup/SRP\n");