diff options
Diffstat (limited to 'drivers/usb/gadget/m66592-udc.h')
-rw-r--r-- | drivers/usb/gadget/m66592-udc.h | 90 |
1 files changed, 45 insertions, 45 deletions
diff --git a/drivers/usb/gadget/m66592-udc.h b/drivers/usb/gadget/m66592-udc.h index 286ce07e7960..8b960deed680 100644 --- a/drivers/usb/gadget/m66592-udc.h +++ b/drivers/usb/gadget/m66592-udc.h | |||
@@ -23,10 +23,12 @@ | |||
23 | #ifndef __M66592_UDC_H__ | 23 | #ifndef __M66592_UDC_H__ |
24 | #define __M66592_UDC_H__ | 24 | #define __M66592_UDC_H__ |
25 | 25 | ||
26 | #if defined(CONFIG_SUPERH_BUILT_IN_M66592) && defined(CONFIG_HAVE_CLK) | 26 | #ifdef CONFIG_HAVE_CLK |
27 | #include <linux/clk.h> | 27 | #include <linux/clk.h> |
28 | #endif | 28 | #endif |
29 | 29 | ||
30 | #include <linux/usb/m66592.h> | ||
31 | |||
30 | #define M66592_SYSCFG 0x00 | 32 | #define M66592_SYSCFG 0x00 |
31 | #define M66592_XTAL 0xC000 /* b15-14: Crystal selection */ | 33 | #define M66592_XTAL 0xC000 /* b15-14: Crystal selection */ |
32 | #define M66592_XTAL48 0x8000 /* 48MHz */ | 34 | #define M66592_XTAL48 0x8000 /* 48MHz */ |
@@ -76,11 +78,11 @@ | |||
76 | #define M66592_P_TST_J 0x0001 /* PERI TEST J */ | 78 | #define M66592_P_TST_J 0x0001 /* PERI TEST J */ |
77 | #define M66592_P_TST_NORMAL 0x0000 /* PERI Normal Mode */ | 79 | #define M66592_P_TST_NORMAL 0x0000 /* PERI Normal Mode */ |
78 | 80 | ||
79 | #if defined(CONFIG_SUPERH_BUILT_IN_M66592) | 81 | /* built-in registers */ |
80 | #define M66592_CFBCFG 0x0A | 82 | #define M66592_CFBCFG 0x0A |
81 | #define M66592_D0FBCFG 0x0C | 83 | #define M66592_D0FBCFG 0x0C |
82 | #define M66592_LITTLE 0x0100 /* b8: Little endian mode */ | 84 | #define M66592_LITTLE 0x0100 /* b8: Little endian mode */ |
83 | #else | 85 | /* external chip case */ |
84 | #define M66592_PINCFG 0x0A | 86 | #define M66592_PINCFG 0x0A |
85 | #define M66592_LDRV 0x8000 /* b15: Drive Current Adjust */ | 87 | #define M66592_LDRV 0x8000 /* b15: Drive Current Adjust */ |
86 | #define M66592_BIGEND 0x0100 /* b8: Big endian mode */ | 88 | #define M66592_BIGEND 0x0100 /* b8: Big endian mode */ |
@@ -100,8 +102,8 @@ | |||
100 | #define M66592_PKTM 0x0020 /* b5: Packet mode */ | 102 | #define M66592_PKTM 0x0020 /* b5: Packet mode */ |
101 | #define M66592_DENDE 0x0010 /* b4: Dend enable */ | 103 | #define M66592_DENDE 0x0010 /* b4: Dend enable */ |
102 | #define M66592_OBUS 0x0004 /* b2: OUTbus mode */ | 104 | #define M66592_OBUS 0x0004 /* b2: OUTbus mode */ |
103 | #endif /* #if defined(CONFIG_SUPERH_BUILT_IN_M66592) */ | ||
104 | 105 | ||
106 | /* common case */ | ||
105 | #define M66592_CFIFO 0x10 | 107 | #define M66592_CFIFO 0x10 |
106 | #define M66592_D0FIFO 0x14 | 108 | #define M66592_D0FIFO 0x14 |
107 | #define M66592_D1FIFO 0x18 | 109 | #define M66592_D1FIFO 0x18 |
@@ -113,13 +115,9 @@ | |||
113 | #define M66592_REW 0x4000 /* b14: Buffer rewind */ | 115 | #define M66592_REW 0x4000 /* b14: Buffer rewind */ |
114 | #define M66592_DCLRM 0x2000 /* b13: DMA buffer clear mode */ | 116 | #define M66592_DCLRM 0x2000 /* b13: DMA buffer clear mode */ |
115 | #define M66592_DREQE 0x1000 /* b12: DREQ output enable */ | 117 | #define M66592_DREQE 0x1000 /* b12: DREQ output enable */ |
116 | #if defined(CONFIG_SUPERH_BUILT_IN_M66592) | 118 | #define M66592_MBW_8 0x0000 /* 8bit */ |
117 | #define M66592_MBW 0x0800 /* b11: Maximum bit width for FIFO */ | 119 | #define M66592_MBW_16 0x0400 /* 16bit */ |
118 | #else | 120 | #define M66592_MBW_32 0x0800 /* 32bit */ |
119 | #define M66592_MBW 0x0400 /* b10: Maximum bit width for FIFO */ | ||
120 | #define M66592_MBW_8 0x0000 /* 8bit */ | ||
121 | #define M66592_MBW_16 0x0400 /* 16bit */ | ||
122 | #endif /* #if defined(CONFIG_SUPERH_BUILT_IN_M66592) */ | ||
123 | #define M66592_TRENB 0x0200 /* b9: Transaction counter enable */ | 121 | #define M66592_TRENB 0x0200 /* b9: Transaction counter enable */ |
124 | #define M66592_TRCLR 0x0100 /* b8: Transaction counter clear */ | 122 | #define M66592_TRCLR 0x0100 /* b8: Transaction counter clear */ |
125 | #define M66592_DEZPM 0x0080 /* b7: Zero-length packet mode */ | 123 | #define M66592_DEZPM 0x0080 /* b7: Zero-length packet mode */ |
@@ -480,9 +478,11 @@ struct m66592_ep { | |||
480 | struct m66592 { | 478 | struct m66592 { |
481 | spinlock_t lock; | 479 | spinlock_t lock; |
482 | void __iomem *reg; | 480 | void __iomem *reg; |
483 | #if defined(CONFIG_SUPERH_BUILT_IN_M66592) && defined(CONFIG_HAVE_CLK) | 481 | #ifdef CONFIG_HAVE_CLK |
484 | struct clk *clk; | 482 | struct clk *clk; |
485 | #endif | 483 | #endif |
484 | struct m66592_platdata *pdata; | ||
485 | unsigned long irq_trigger; | ||
486 | 486 | ||
487 | struct usb_gadget gadget; | 487 | struct usb_gadget gadget; |
488 | struct usb_gadget_driver *driver; | 488 | struct usb_gadget_driver *driver; |
@@ -506,7 +506,6 @@ struct m66592 { | |||
506 | int interrupt; | 506 | int interrupt; |
507 | int isochronous; | 507 | int isochronous; |
508 | int num_dma; | 508 | int num_dma; |
509 | int bi_bufnum; /* bulk and isochronous's bufnum */ | ||
510 | }; | 509 | }; |
511 | 510 | ||
512 | #define gadget_to_m66592(_gadget) container_of(_gadget, struct m66592, gadget) | 511 | #define gadget_to_m66592(_gadget) container_of(_gadget, struct m66592, gadget) |
@@ -547,13 +546,13 @@ static inline void m66592_read_fifo(struct m66592 *m66592, | |||
547 | { | 546 | { |
548 | unsigned long fifoaddr = (unsigned long)m66592->reg + offset; | 547 | unsigned long fifoaddr = (unsigned long)m66592->reg + offset; |
549 | 548 | ||
550 | #if defined(CONFIG_SUPERH_BUILT_IN_M66592) | 549 | if (m66592->pdata->on_chip) { |
551 | len = (len + 3) / 4; | 550 | len = (len + 3) / 4; |
552 | insl(fifoaddr, buf, len); | 551 | insl(fifoaddr, buf, len); |
553 | #else | 552 | } else { |
554 | len = (len + 1) / 2; | 553 | len = (len + 1) / 2; |
555 | insw(fifoaddr, buf, len); | 554 | insw(fifoaddr, buf, len); |
556 | #endif | 555 | } |
557 | } | 556 | } |
558 | 557 | ||
559 | static inline void m66592_write(struct m66592 *m66592, u16 val, | 558 | static inline void m66592_write(struct m66592 *m66592, u16 val, |
@@ -567,33 +566,34 @@ static inline void m66592_write_fifo(struct m66592 *m66592, | |||
567 | void *buf, unsigned long len) | 566 | void *buf, unsigned long len) |
568 | { | 567 | { |
569 | unsigned long fifoaddr = (unsigned long)m66592->reg + offset; | 568 | unsigned long fifoaddr = (unsigned long)m66592->reg + offset; |
570 | #if defined(CONFIG_SUPERH_BUILT_IN_M66592) | 569 | |
571 | unsigned long count; | 570 | if (m66592->pdata->on_chip) { |
572 | unsigned char *pb; | 571 | unsigned long count; |
573 | int i; | 572 | unsigned char *pb; |
574 | 573 | int i; | |
575 | count = len / 4; | 574 | |
576 | outsl(fifoaddr, buf, count); | 575 | count = len / 4; |
577 | 576 | outsl(fifoaddr, buf, count); | |
578 | if (len & 0x00000003) { | 577 | |
579 | pb = buf + count * 4; | 578 | if (len & 0x00000003) { |
580 | for (i = 0; i < (len & 0x00000003); i++) { | 579 | pb = buf + count * 4; |
581 | if (m66592_read(m66592, M66592_CFBCFG)) /* little */ | 580 | for (i = 0; i < (len & 0x00000003); i++) { |
582 | outb(pb[i], fifoaddr + (3 - i)); | 581 | if (m66592_read(m66592, M66592_CFBCFG)) /* le */ |
583 | else | 582 | outb(pb[i], fifoaddr + (3 - i)); |
584 | outb(pb[i], fifoaddr + i); | 583 | else |
584 | outb(pb[i], fifoaddr + i); | ||
585 | } | ||
586 | } | ||
587 | } else { | ||
588 | unsigned long odd = len & 0x0001; | ||
589 | |||
590 | len = len / 2; | ||
591 | outsw(fifoaddr, buf, len); | ||
592 | if (odd) { | ||
593 | unsigned char *p = buf + len*2; | ||
594 | outb(*p, fifoaddr); | ||
585 | } | 595 | } |
586 | } | 596 | } |
587 | #else | ||
588 | unsigned long odd = len & 0x0001; | ||
589 | |||
590 | len = len / 2; | ||
591 | outsw(fifoaddr, buf, len); | ||
592 | if (odd) { | ||
593 | unsigned char *p = buf + len*2; | ||
594 | outb(*p, fifoaddr); | ||
595 | } | ||
596 | #endif /* #if defined(CONFIG_SUPERH_BUILT_IN_M66592) */ | ||
597 | } | 597 | } |
598 | 598 | ||
599 | static inline void m66592_mdfy(struct m66592 *m66592, u16 val, u16 pat, | 599 | static inline void m66592_mdfy(struct m66592 *m66592, u16 val, u16 pat, |