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-rw-r--r--drivers/usb/gadget/langwell_udc.h223
1 files changed, 0 insertions, 223 deletions
diff --git a/drivers/usb/gadget/langwell_udc.h b/drivers/usb/gadget/langwell_udc.h
deleted file mode 100644
index 38fa3c86d85c..000000000000
--- a/drivers/usb/gadget/langwell_udc.h
+++ /dev/null
@@ -1,223 +0,0 @@
1/*
2 * Intel Langwell USB Device Controller driver
3 * Copyright (C) 2008-2009, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 */
9
10#include <linux/usb/langwell_udc.h>
11
12/*-------------------------------------------------------------------------*/
13
14/* driver data structures and utilities */
15
16/*
17 * dTD: Device Endpoint Transfer Descriptor
18 * describe to the device controller the location and quantity of
19 * data to be send/received for given transfer
20 */
21struct langwell_dtd {
22 u32 dtd_next;
23/* bits 31:5, next transfer element pointer */
24#define DTD_NEXT(d) (((d)>>5)&0x7ffffff)
25#define DTD_NEXT_MASK (0x7ffffff << 5)
26/* terminate */
27#define DTD_TERM BIT(0)
28 /* bits 7:0, execution back states */
29 u32 dtd_status:8;
30#define DTD_STATUS(d) (((d)>>0)&0xff)
31#define DTD_STS_ACTIVE BIT(7) /* active */
32#define DTD_STS_HALTED BIT(6) /* halted */
33#define DTD_STS_DBE BIT(5) /* data buffer error */
34#define DTD_STS_TRE BIT(3) /* transaction error */
35 /* bits 9:8 */
36 u32 dtd_res0:2;
37 /* bits 11:10, multipier override */
38 u32 dtd_multo:2;
39#define DTD_MULTO (BIT(11) | BIT(10))
40 /* bits 14:12 */
41 u32 dtd_res1:3;
42 /* bit 15, interrupt on complete */
43 u32 dtd_ioc:1;
44#define DTD_IOC BIT(15)
45 /* bits 30:16, total bytes */
46 u32 dtd_total:15;
47#define DTD_TOTAL(d) (((d)>>16)&0x7fff)
48#define DTD_MAX_TRANSFER_LENGTH 0x4000
49 /* bit 31 */
50 u32 dtd_res2:1;
51 /* dTD buffer pointer page 0 to 4 */
52 u32 dtd_buf[5];
53#define DTD_OFFSET_MASK 0xfff
54/* bits 31:12, buffer pointer */
55#define DTD_BUFFER(d) (((d)>>12)&0x3ff)
56/* bits 11:0, current offset */
57#define DTD_C_OFFSET(d) (((d)>>0)&0xfff)
58/* bits 10:0, frame number */
59#define DTD_FRAME(d) (((d)>>0)&0x7ff)
60
61 /* driver-private parts */
62
63 /* dtd dma address */
64 dma_addr_t dtd_dma;
65 /* next dtd virtual address */
66 struct langwell_dtd *next_dtd_virt;
67};
68
69
70/*
71 * dQH: Device Endpoint Queue Head
72 * describe where all transfers are managed
73 * 48-byte data structure, aligned on 64-byte boundary
74 *
75 * These are associated with dTD structure
76 */
77struct langwell_dqh {
78 /* endpoint capabilities and characteristics */
79 u32 dqh_res0:15; /* bits 14:0 */
80 u32 dqh_ios:1; /* bit 15, interrupt on setup */
81#define DQH_IOS BIT(15)
82 u32 dqh_mpl:11; /* bits 26:16, maximum packet length */
83#define DQH_MPL (0x7ff << 16)
84 u32 dqh_res1:2; /* bits 28:27 */
85 u32 dqh_zlt:1; /* bit 29, zero length termination */
86#define DQH_ZLT BIT(29)
87 u32 dqh_mult:2; /* bits 31:30 */
88#define DQH_MULT (BIT(30) | BIT(31))
89
90 /* current dTD pointer */
91 u32 dqh_current; /* locate the transfer in progress */
92#define DQH_C_DTD(e) \
93 (((e)>>5)&0x7ffffff) /* bits 31:5, current dTD pointer */
94
95 /* transfer overlay, hardware parts of a struct langwell_dtd */
96 u32 dtd_next;
97 u32 dtd_status:8; /* bits 7:0, execution back states */
98 u32 dtd_res0:2; /* bits 9:8 */
99 u32 dtd_multo:2; /* bits 11:10, multipier override */
100 u32 dtd_res1:3; /* bits 14:12 */
101 u32 dtd_ioc:1; /* bit 15, interrupt on complete */
102 u32 dtd_total:15; /* bits 30:16, total bytes */
103 u32 dtd_res2:1; /* bit 31 */
104 u32 dtd_buf[5]; /* dTD buffer pointer page 0 to 4 */
105
106 u32 dqh_res2;
107 struct usb_ctrlrequest dqh_setup; /* setup packet buffer */
108} __attribute__ ((aligned(64)));
109
110
111/* endpoint data structure */
112struct langwell_ep {
113 struct usb_ep ep;
114 dma_addr_t dma;
115 struct langwell_udc *dev;
116 unsigned long irqs;
117 struct list_head queue;
118 struct langwell_dqh *dqh;
119 char name[14];
120 unsigned stopped:1,
121 ep_type:2,
122 ep_num:8;
123};
124
125
126/* request data structure */
127struct langwell_request {
128 struct usb_request req;
129 struct langwell_dtd *dtd, *head, *tail;
130 struct langwell_ep *ep;
131 dma_addr_t dtd_dma;
132 struct list_head queue;
133 unsigned dtd_count;
134 unsigned mapped:1;
135};
136
137
138/* ep0 transfer state */
139enum ep0_state {
140 WAIT_FOR_SETUP,
141 DATA_STATE_XMIT,
142 DATA_STATE_NEED_ZLP,
143 WAIT_FOR_OUT_STATUS,
144 DATA_STATE_RECV,
145};
146
147
148/* device suspend state */
149enum lpm_state {
150 LPM_L0, /* on */
151 LPM_L1, /* LPM L1 sleep */
152 LPM_L2, /* suspend */
153 LPM_L3, /* off */
154};
155
156
157/* device data structure */
158struct langwell_udc {
159 /* each pci device provides one gadget, several endpoints */
160 struct usb_gadget gadget;
161 spinlock_t lock; /* device lock */
162 struct langwell_ep *ep;
163 struct usb_gadget_driver *driver;
164 struct usb_phy *transceiver;
165 u8 dev_addr;
166 u32 usb_state;
167 u32 resume_state;
168 u32 bus_reset;
169 enum lpm_state lpm_state;
170 enum ep0_state ep0_state;
171 u32 ep0_dir;
172 u16 dciversion;
173 unsigned ep_max;
174 unsigned devcap:1,
175 enabled:1,
176 region:1,
177 got_irq:1,
178 powered:1,
179 remote_wakeup:1,
180 rate:1,
181 is_reset:1,
182 softconnected:1,
183 vbus_active:1,
184 suspended:1,
185 stopped:1,
186 lpm:1, /* LPM capability */
187 has_sram:1, /* SRAM caching */
188 got_sram:1;
189
190 /* pci state used to access those endpoints */
191 struct pci_dev *pdev;
192
193 /* Langwell otg transceiver */
194 struct langwell_otg *lotg;
195
196 /* control registers */
197 struct langwell_cap_regs __iomem *cap_regs;
198 struct langwell_op_regs __iomem *op_regs;
199
200 struct usb_ctrlrequest local_setup_buff;
201 struct langwell_dqh *ep_dqh;
202 size_t ep_dqh_size;
203 dma_addr_t ep_dqh_dma;
204
205 /* ep0 status request */
206 struct langwell_request *status_req;
207
208 /* dma pool */
209 struct dma_pool *dtd_pool;
210
211 /* make sure release() is done */
212 struct completion *done;
213
214 /* for private SRAM caching */
215 unsigned int sram_addr;
216 unsigned int sram_size;
217
218 /* device status data for get_status request */
219 u16 dev_status;
220};
221
222#define gadget_to_langwell(g) container_of((g), struct langwell_udc, gadget)
223
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-22 17:17:28 -0500