1 files changed, 228 insertions, 0 deletions
diff --git a/drivers/usb/gadget/langwell_udc.h b/drivers/usb/gadget/langwell_udc.h
new file mode 100644
index 000000000000..9719934e1c08
--- /dev/null
+++ b/drivers/usb/gadget/langwell_udc.h
@@ -0,0 +1,228 @@
+/*
+ * Intel Langwell USB Device Controller driver
+ * Copyright (C) 2008-2009, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+#include <linux/usb/langwell_udc.h>
+#if defined(CONFIG_USB_LANGWELL_OTG)
+#include <linux/usb/langwell_otg.h>
+#endif
+/*-------------------------------------------------------------------------*/
+/* driver data structures and utilities */
+/*
+ * dTD: Device Endpoint Transfer Descriptor
+ * describe to the device controller the location and quantity of
+ * data to be send/received for given transfer
+ */
+struct langwell_dtd {
+        u32     dtd_next;
+/* bits 31:5, next transfer element pointer */
+#define DTD_NEXT(d)     (((d)>>5)&0x7ffffff)
+#define DTD_NEXT_MASK   (0x7ffffff << 5)
+/* terminate */
+#define DTD_TERM        BIT(0)
+        /* bits 7:0, execution back states */
+        u32     dtd_status:8;
+#define DTD_STATUS(d)   (((d)>>0)&0xff)
+#define DTD_STS_ACTIVE  BIT(7)  /* active */
+#define DTD_STS_HALTED  BIT(6)  /* halted */
+#define DTD_STS_DBE     BIT(5)  /* data buffer error */
+#define DTD_STS_TRE     BIT(3)  /* transaction error  */
+        /* bits 9:8 */
+        u32     dtd_res0:2;
+        /* bits 11:10, multipier override */
+        u32     dtd_multo:2;
+#define DTD_MULTO       (BIT(11) | BIT(10))
+        /* bits 14:12 */
+        u32     dtd_res1:3;
+        /* bit 15, interrupt on complete */
+        u32     dtd_ioc:1;
+#define DTD_IOC         BIT(15)
+        /* bits 30:16, total bytes */
+        u32     dtd_total:15;
+#define DTD_TOTAL(d)    (((d)>>16)&0x7fff)
+#define DTD_MAX_TRANSFER_LENGTH 0x4000
+        /* bit 31 */
+        u32     dtd_res2:1;
+        /* dTD buffer pointer page 0 to 4 */
+        u32     dtd_buf[5];
+#define DTD_OFFSET_MASK 0xfff
+/* bits 31:12, buffer pointer */
+#define DTD_BUFFER(d)   (((d)>>12)&0x3ff)
+/* bits 11:0, current offset */
+#define DTD_C_OFFSET(d) (((d)>>0)&0xfff)
+/* bits 10:0, frame number */
+#define DTD_FRAME(d)    (((d)>>0)&0x7ff)
+        /* driver-private parts */
+        /* dtd dma address */
+        dma_addr_t              dtd_dma;
+        /* next dtd virtual address */
+        struct langwell_dtd     *next_dtd_virt;
+};
+/*
+ * dQH: Device Endpoint Queue Head
+ * describe where all transfers are managed
+ * 48-byte data structure, aligned on 64-byte boundary
+ *
+ * These are associated with dTD structure
+ */
+struct langwell_dqh {
+        /* endpoint capabilities and characteristics */
+        u32     dqh_res0:15;    /* bits 14:0 */
+        u32     dqh_ios:1;      /* bit 15, interrupt on setup */
+#define DQH_IOS         BIT(15)
+        u32     dqh_mpl:11;     /* bits 26:16, maximum packet length */
+#define DQH_MPL         (0x7ff << 16)
+        u32     dqh_res1:2;     /* bits 28:27 */
+        u32     dqh_zlt:1;      /* bit 29, zero length termination */
+#define DQH_ZLT         BIT(29)
+        u32     dqh_mult:2;     /* bits 31:30 */
+#define DQH_MULT        (BIT(30) | BIT(31))
+        /* current dTD pointer */
+        u32     dqh_current;    /* locate the transfer in progress */
+#define DQH_C_DTD(e)    \
+        (((e)>>5)&0x7ffffff)    /* bits 31:5, current dTD pointer */
+        /* transfer overlay, hardware parts of a struct langwell_dtd */
+        u32     dtd_next;
+        u32     dtd_status:8;   /* bits 7:0, execution back states */
+        u32     dtd_res0:2;     /* bits 9:8 */
+        u32     dtd_multo:2;    /* bits 11:10, multipier override */
+        u32     dtd_res1:3;     /* bits 14:12 */
+        u32     dtd_ioc:1;      /* bit 15, interrupt on complete */
+        u32     dtd_total:15;   /* bits 30:16, total bytes */
+        u32     dtd_res2:1;     /* bit 31 */
+        u32     dtd_buf[5];     /* dTD buffer pointer page 0 to 4 */
+        u32     dqh_res2;
+        struct usb_ctrlrequest  dqh_setup;      /* setup packet buffer */
+} __attribute__ ((aligned(64)));
+/* endpoint data structure */
+struct langwell_ep {
+        struct usb_ep           ep;
+        dma_addr_t              dma;
+        struct langwell_udc     *dev;
+        unsigned long           irqs;
+        struct list_head        queue;
+        struct langwell_dqh     *dqh;
+        const struct usb_endpoint_descriptor    *desc;
+        char                    name[14];
+        unsigned                stopped:1,
+                                ep_type:2,
+                                ep_num:8;
+};
+/* request data structure */
+struct langwell_request {
+        struct usb_request      req;
+        struct langwell_dtd     *dtd, *head, *tail;
+        struct langwell_ep      *ep;
+        dma_addr_t              dtd_dma;
+        struct list_head        queue;
+        unsigned                dtd_count;
+        unsigned                mapped:1;
+};
+/* ep0 transfer state */
+enum ep0_state {
+        WAIT_FOR_SETUP,
+        DATA_STATE_XMIT,
+        DATA_STATE_NEED_ZLP,
+        WAIT_FOR_OUT_STATUS,
+        DATA_STATE_RECV,
+};
+/* device suspend state */
+enum lpm_state {
+        LPM_L0, /* on */
+        LPM_L1, /* LPM L1 sleep */
+        LPM_L2, /* suspend */
+        LPM_L3, /* off */
+};
+/* device data structure */
+struct langwell_udc {
+        /* each pci device provides one gadget, several endpoints */
+        struct usb_gadget       gadget;
+        spinlock_t              lock;   /* device lock */
+        struct langwell_ep      *ep;
+        struct usb_gadget_driver        *driver;
+        struct otg_transceiver  *transceiver;
+        u8                      dev_addr;
+        u32                     usb_state;
+        u32                     resume_state;
+        u32                     bus_reset;
+        enum lpm_state          lpm_state;
+        enum ep0_state          ep0_state;
+        u32                     ep0_dir;
+        u16                     dciversion;
+        unsigned                ep_max;
+        unsigned                devcap:1,
+                                enabled:1,
+                                region:1,
+                                got_irq:1,
+                                powered:1,
+                                remote_wakeup:1,
+                                rate:1,
+                                is_reset:1,
+                                softconnected:1,
+                                vbus_active:1,
+                                suspended:1,
+                                stopped:1,
+                                lpm:1;  /* LPM capability */
+        /* pci state used to access those endpoints */
+        struct pci_dev          *pdev;
+        /* Langwell otg transceiver */
+        struct langwell_otg     *lotg;
+        /* control registers */
+        struct langwell_cap_regs        __iomem *cap_regs;
+        struct langwell_op_regs         __iomem *op_regs;
+        struct usb_ctrlrequest  local_setup_buff;
+        struct langwell_dqh     *ep_dqh;
+        size_t                  ep_dqh_size;
+        dma_addr_t              ep_dqh_dma;
+        /* ep0 status request */
+        struct langwell_request *status_req;
+        /* dma pool */
+        struct dma_pool         *dtd_pool;
+        /* make sure release() is done */
+        struct completion       *done;
+};

diff --git a/drivers/usb/gadget/langwell_udc.h b/drivers/usb/gadget/langwell_udc.h new file mode 100644 index 000000000000..9719934e1c08 --- /dev/null +++ b/drivers/usb/gadget/langwell_udc.h
@@ -0,0 +1,228 @@
	1	/*
	2	* Intel Langwell USB Device Controller driver
	3	* Copyright (C) 2008-2009, Intel Corporation.
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms and conditions of the GNU General Public License,
	7	* version 2, as published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	* You should have received a copy of the GNU General Public License along with
	15	* this program; if not, write to the Free Software Foundation, Inc.,
	16	* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	17	*
	18	*/
	19
	20	#include <linux/usb/langwell_udc.h>
	21
	22	#if defined(CONFIG_USB_LANGWELL_OTG)
	23	#include <linux/usb/langwell_otg.h>
	24	#endif
	25
	26
	27	/-------------------------------------------------------------------------/
	28
	29	/* driver data structures and utilities */
	30
	31	/*
	32	* dTD: Device Endpoint Transfer Descriptor
	33	* describe to the device controller the location and quantity of
	34	* data to be send/received for given transfer
	35	*/
	36	struct langwell_dtd {
	37	u32 dtd_next;
	38	/* bits 31:5, next transfer element pointer */
	39	#define DTD_NEXT(d) (((d)>>5)&0x7ffffff)
	40	#define DTD_NEXT_MASK (0x7ffffff << 5)
	41	/* terminate */
	42	#define DTD_TERM BIT(0)
	43	/* bits 7:0, execution back states */
	44	u32 dtd_status:8;
	45	#define DTD_STATUS(d) (((d)>>0)&0xff)
	46	#define DTD_STS_ACTIVE BIT(7) /* active */
	47	#define DTD_STS_HALTED BIT(6) /* halted */
	48	#define DTD_STS_DBE BIT(5) /* data buffer error */
	49	#define DTD_STS_TRE BIT(3) /* transaction error */
	50	/* bits 9:8 */
	51	u32 dtd_res0:2;
	52	/* bits 11:10, multipier override */
	53	u32 dtd_multo:2;
	54	#define DTD_MULTO (BIT(11) \| BIT(10))
	55	/* bits 14:12 */
	56	u32 dtd_res1:3;
	57	/* bit 15, interrupt on complete */
	58	u32 dtd_ioc:1;
	59	#define DTD_IOC BIT(15)
	60	/* bits 30:16, total bytes */
	61	u32 dtd_total:15;
	62	#define DTD_TOTAL(d) (((d)>>16)&0x7fff)
	63	#define DTD_MAX_TRANSFER_LENGTH 0x4000
	64	/* bit 31 */
	65	u32 dtd_res2:1;
	66	/* dTD buffer pointer page 0 to 4 */
	67	u32 dtd_buf[5];
	68	#define DTD_OFFSET_MASK 0xfff
	69	/* bits 31:12, buffer pointer */
	70	#define DTD_BUFFER(d) (((d)>>12)&0x3ff)
	71	/* bits 11:0, current offset */
	72	#define DTD_C_OFFSET(d) (((d)>>0)&0xfff)
	73	/* bits 10:0, frame number */
	74	#define DTD_FRAME(d) (((d)>>0)&0x7ff)
	75
	76	/* driver-private parts */
	77
	78	/* dtd dma address */
	79	dma_addr_t dtd_dma;
	80	/* next dtd virtual address */
	81	struct langwell_dtd *next_dtd_virt;
	82	};
	83
	84
	85	/*
	86	* dQH: Device Endpoint Queue Head
	87	* describe where all transfers are managed
	88	* 48-byte data structure, aligned on 64-byte boundary
	89	*
	90	* These are associated with dTD structure
	91	*/
	92	struct langwell_dqh {
	93	/* endpoint capabilities and characteristics */
	94	u32 dqh_res0:15; /* bits 14:0 */
	95	u32 dqh_ios:1; /* bit 15, interrupt on setup */
	96	#define DQH_IOS BIT(15)
	97	u32 dqh_mpl:11; /* bits 26:16, maximum packet length */
	98	#define DQH_MPL (0x7ff << 16)
	99	u32 dqh_res1:2; /* bits 28:27 */
	100	u32 dqh_zlt:1; /* bit 29, zero length termination */
	101	#define DQH_ZLT BIT(29)
	102	u32 dqh_mult:2; /* bits 31:30 */
	103	#define DQH_MULT (BIT(30) \| BIT(31))
	104
	105	/* current dTD pointer */
	106	u32 dqh_current; /* locate the transfer in progress */
	107	#define DQH_C_DTD(e) \
	108	(((e)>>5)&0x7ffffff) /* bits 31:5, current dTD pointer */
	109
	110	/* transfer overlay, hardware parts of a struct langwell_dtd */
	111	u32 dtd_next;
	112	u32 dtd_status:8; /* bits 7:0, execution back states */
	113	u32 dtd_res0:2; /* bits 9:8 */
	114	u32 dtd_multo:2; /* bits 11:10, multipier override */
	115	u32 dtd_res1:3; /* bits 14:12 */
	116	u32 dtd_ioc:1; /* bit 15, interrupt on complete */
	117	u32 dtd_total:15; /* bits 30:16, total bytes */
	118	u32 dtd_res2:1; /* bit 31 */
	119	u32 dtd_buf[5]; /* dTD buffer pointer page 0 to 4 */
	120
	121	u32 dqh_res2;
	122	struct usb_ctrlrequest dqh_setup; /* setup packet buffer */
	123	} __attribute__ ((aligned(64)));
	124
	125
	126	/* endpoint data structure */
	127	struct langwell_ep {
	128	struct usb_ep ep;
	129	dma_addr_t dma;
	130	struct langwell_udc *dev;
	131	unsigned long irqs;
	132	struct list_head queue;
	133	struct langwell_dqh *dqh;
	134	const struct usb_endpoint_descriptor *desc;
	135	char name[14];
	136	unsigned stopped:1,
	137	ep_type:2,
	138	ep_num:8;
	139	};
	140
	141
	142	/* request data structure */
	143	struct langwell_request {
	144	struct usb_request req;
	145	struct langwell_dtd dtd, head, *tail;
	146	struct langwell_ep *ep;
	147	dma_addr_t dtd_dma;
	148	struct list_head queue;
	149	unsigned dtd_count;
	150	unsigned mapped:1;
	151	};
	152
	153
	154	/* ep0 transfer state */
	155	enum ep0_state {
	156	WAIT_FOR_SETUP,
	157	DATA_STATE_XMIT,
	158	DATA_STATE_NEED_ZLP,
	159	WAIT_FOR_OUT_STATUS,
	160	DATA_STATE_RECV,
	161	};
	162
	163
	164	/* device suspend state */
	165	enum lpm_state {
	166	LPM_L0, /* on */
	167	LPM_L1, /* LPM L1 sleep */
	168	LPM_L2, /* suspend */
	169	LPM_L3, /* off */
	170	};
	171
	172
	173	/* device data structure */
	174	struct langwell_udc {
	175	/* each pci device provides one gadget, several endpoints */
	176	struct usb_gadget gadget;
	177	spinlock_t lock; /* device lock */
	178	struct langwell_ep *ep;
	179	struct usb_gadget_driver *driver;
	180	struct otg_transceiver *transceiver;
	181	u8 dev_addr;
	182	u32 usb_state;
	183	u32 resume_state;
	184	u32 bus_reset;
	185	enum lpm_state lpm_state;
	186	enum ep0_state ep0_state;
	187	u32 ep0_dir;
	188	u16 dciversion;
	189	unsigned ep_max;
	190	unsigned devcap:1,
	191	enabled:1,
	192	region:1,
	193	got_irq:1,
	194	powered:1,
	195	remote_wakeup:1,
	196	rate:1,
	197	is_reset:1,
	198	softconnected:1,
	199	vbus_active:1,
	200	suspended:1,
	201	stopped:1,
	202	lpm:1; /* LPM capability */
	203
	204	/* pci state used to access those endpoints */
	205	struct pci_dev *pdev;
	206
	207	/* Langwell otg transceiver */
	208	struct langwell_otg *lotg;
	209
	210	/* control registers */
	211	struct langwell_cap_regs __iomem *cap_regs;
	212	struct langwell_op_regs __iomem *op_regs;
	213
	214	struct usb_ctrlrequest local_setup_buff;
	215	struct langwell_dqh *ep_dqh;
	216	size_t ep_dqh_size;
	217	dma_addr_t ep_dqh_dma;
	218
	219	/* ep0 status request */
	220	struct langwell_request *status_req;
	221
	222	/* dma pool */
	223	struct dma_pool *dtd_pool;
	224
	225	/* make sure release() is done */
	226	struct completion *done;
	227	};
	228