diff options
Diffstat (limited to 'drivers/tty')
52 files changed, 1442 insertions, 4438 deletions
diff --git a/drivers/tty/hvc/hvc_opal.c b/drivers/tty/hvc/hvc_opal.c index 071551bf3e9a..543b234e70fc 100644 --- a/drivers/tty/hvc/hvc_opal.c +++ b/drivers/tty/hvc/hvc_opal.c | |||
@@ -41,7 +41,7 @@ | |||
41 | 41 | ||
42 | static const char hvc_opal_name[] = "hvc_opal"; | 42 | static const char hvc_opal_name[] = "hvc_opal"; |
43 | 43 | ||
44 | static struct of_device_id hvc_opal_match[] = { | 44 | static const struct of_device_id hvc_opal_match[] = { |
45 | { .name = "serial", .compatible = "ibm,opal-console-raw" }, | 45 | { .name = "serial", .compatible = "ibm,opal-console-raw" }, |
46 | { .name = "serial", .compatible = "ibm,opal-console-hvsi" }, | 46 | { .name = "serial", .compatible = "ibm,opal-console-hvsi" }, |
47 | { }, | 47 | { }, |
diff --git a/drivers/tty/n_gsm.c b/drivers/tty/n_gsm.c index c4343764cc5b..91abc00aa833 100644 --- a/drivers/tty/n_gsm.c +++ b/drivers/tty/n_gsm.c | |||
@@ -2669,7 +2669,7 @@ static inline void muxnet_put(struct gsm_mux_net *mux_net) | |||
2669 | static int gsm_mux_net_start_xmit(struct sk_buff *skb, | 2669 | static int gsm_mux_net_start_xmit(struct sk_buff *skb, |
2670 | struct net_device *net) | 2670 | struct net_device *net) |
2671 | { | 2671 | { |
2672 | struct gsm_mux_net *mux_net = (struct gsm_mux_net *)netdev_priv(net); | 2672 | struct gsm_mux_net *mux_net = netdev_priv(net); |
2673 | struct gsm_dlci *dlci = mux_net->dlci; | 2673 | struct gsm_dlci *dlci = mux_net->dlci; |
2674 | muxnet_get(mux_net); | 2674 | muxnet_get(mux_net); |
2675 | 2675 | ||
@@ -2698,7 +2698,7 @@ static void gsm_mux_rx_netchar(struct gsm_dlci *dlci, | |||
2698 | { | 2698 | { |
2699 | struct net_device *net = dlci->net; | 2699 | struct net_device *net = dlci->net; |
2700 | struct sk_buff *skb; | 2700 | struct sk_buff *skb; |
2701 | struct gsm_mux_net *mux_net = (struct gsm_mux_net *)netdev_priv(net); | 2701 | struct gsm_mux_net *mux_net = netdev_priv(net); |
2702 | muxnet_get(mux_net); | 2702 | muxnet_get(mux_net); |
2703 | 2703 | ||
2704 | /* Allocate an sk_buff */ | 2704 | /* Allocate an sk_buff */ |
@@ -2727,7 +2727,7 @@ static void gsm_mux_rx_netchar(struct gsm_dlci *dlci, | |||
2727 | 2727 | ||
2728 | static int gsm_change_mtu(struct net_device *net, int new_mtu) | 2728 | static int gsm_change_mtu(struct net_device *net, int new_mtu) |
2729 | { | 2729 | { |
2730 | struct gsm_mux_net *mux_net = (struct gsm_mux_net *)netdev_priv(net); | 2730 | struct gsm_mux_net *mux_net = netdev_priv(net); |
2731 | if ((new_mtu < 8) || (new_mtu > mux_net->dlci->gsm->mtu)) | 2731 | if ((new_mtu < 8) || (new_mtu > mux_net->dlci->gsm->mtu)) |
2732 | return -EINVAL; | 2732 | return -EINVAL; |
2733 | net->mtu = new_mtu; | 2733 | net->mtu = new_mtu; |
@@ -2763,7 +2763,7 @@ static void gsm_destroy_network(struct gsm_dlci *dlci) | |||
2763 | pr_debug("destroy network interface"); | 2763 | pr_debug("destroy network interface"); |
2764 | if (!dlci->net) | 2764 | if (!dlci->net) |
2765 | return; | 2765 | return; |
2766 | mux_net = (struct gsm_mux_net *)netdev_priv(dlci->net); | 2766 | mux_net = netdev_priv(dlci->net); |
2767 | muxnet_put(mux_net); | 2767 | muxnet_put(mux_net); |
2768 | } | 2768 | } |
2769 | 2769 | ||
@@ -2801,7 +2801,7 @@ static int gsm_create_network(struct gsm_dlci *dlci, struct gsm_netconfig *nc) | |||
2801 | return -ENOMEM; | 2801 | return -ENOMEM; |
2802 | } | 2802 | } |
2803 | net->mtu = dlci->gsm->mtu; | 2803 | net->mtu = dlci->gsm->mtu; |
2804 | mux_net = (struct gsm_mux_net *)netdev_priv(net); | 2804 | mux_net = netdev_priv(net); |
2805 | mux_net->dlci = dlci; | 2805 | mux_net->dlci = dlci; |
2806 | kref_init(&mux_net->ref); | 2806 | kref_init(&mux_net->ref); |
2807 | strncpy(nc->if_name, net->name, IFNAMSIZ); /* return net name */ | 2807 | strncpy(nc->if_name, net->name, IFNAMSIZ); /* return net name */ |
@@ -2824,7 +2824,7 @@ static int gsm_create_network(struct gsm_dlci *dlci, struct gsm_netconfig *nc) | |||
2824 | } | 2824 | } |
2825 | 2825 | ||
2826 | /* Line discipline for real tty */ | 2826 | /* Line discipline for real tty */ |
2827 | struct tty_ldisc_ops tty_ldisc_packet = { | 2827 | static struct tty_ldisc_ops tty_ldisc_packet = { |
2828 | .owner = THIS_MODULE, | 2828 | .owner = THIS_MODULE, |
2829 | .magic = TTY_LDISC_MAGIC, | 2829 | .magic = TTY_LDISC_MAGIC, |
2830 | .name = "n_gsm", | 2830 | .name = "n_gsm", |
diff --git a/drivers/tty/serial/8250/8250.h b/drivers/tty/serial/8250/8250.h index b00836851061..c43f74c53cd9 100644 --- a/drivers/tty/serial/8250/8250.h +++ b/drivers/tty/serial/8250/8250.h | |||
@@ -21,7 +21,6 @@ struct uart_8250_dma { | |||
21 | 21 | ||
22 | /* Filter function */ | 22 | /* Filter function */ |
23 | dma_filter_fn fn; | 23 | dma_filter_fn fn; |
24 | |||
25 | /* Parameter to the filter function */ | 24 | /* Parameter to the filter function */ |
26 | void *rx_param; | 25 | void *rx_param; |
27 | void *tx_param; | 26 | void *tx_param; |
@@ -53,7 +52,7 @@ struct old_serial_port { | |||
53 | unsigned int baud_base; | 52 | unsigned int baud_base; |
54 | unsigned int port; | 53 | unsigned int port; |
55 | unsigned int irq; | 54 | unsigned int irq; |
56 | unsigned int flags; | 55 | upf_t flags; |
57 | unsigned char hub6; | 56 | unsigned char hub6; |
58 | unsigned char io_type; | 57 | unsigned char io_type; |
59 | unsigned char __iomem *iomem_base; | 58 | unsigned char __iomem *iomem_base; |
@@ -85,9 +84,6 @@ struct serial8250_config { | |||
85 | #define UART_BUG_THRE (1 << 3) /* UART has buggy THRE reassertion */ | 84 | #define UART_BUG_THRE (1 << 3) /* UART has buggy THRE reassertion */ |
86 | #define UART_BUG_PARITY (1 << 4) /* UART mishandles parity if FIFO enabled */ | 85 | #define UART_BUG_PARITY (1 << 4) /* UART mishandles parity if FIFO enabled */ |
87 | 86 | ||
88 | #define PROBE_RSA (1 << 0) | ||
89 | #define PROBE_ANY (~0) | ||
90 | |||
91 | #define HIGH_BITS_OFFSET ((sizeof(long)-sizeof(int))*8) | 87 | #define HIGH_BITS_OFFSET ((sizeof(long)-sizeof(int))*8) |
92 | 88 | ||
93 | #ifdef CONFIG_SERIAL_8250_SHARE_IRQ | 89 | #ifdef CONFIG_SERIAL_8250_SHARE_IRQ |
@@ -198,3 +194,20 @@ static inline int serial8250_request_dma(struct uart_8250_port *p) | |||
198 | } | 194 | } |
199 | static inline void serial8250_release_dma(struct uart_8250_port *p) { } | 195 | static inline void serial8250_release_dma(struct uart_8250_port *p) { } |
200 | #endif | 196 | #endif |
197 | |||
198 | static inline int ns16550a_goto_highspeed(struct uart_8250_port *up) | ||
199 | { | ||
200 | unsigned char status; | ||
201 | |||
202 | status = serial_in(up, 0x04); /* EXCR2 */ | ||
203 | #define PRESL(x) ((x) & 0x30) | ||
204 | if (PRESL(status) == 0x10) { | ||
205 | /* already in high speed mode */ | ||
206 | return 0; | ||
207 | } else { | ||
208 | status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */ | ||
209 | status |= 0x10; /* 1.625 divisor for baud_base --> 921600 */ | ||
210 | serial_out(up, 0x04, status); | ||
211 | } | ||
212 | return 1; | ||
213 | } | ||
diff --git a/drivers/tty/serial/8250/8250_core.c b/drivers/tty/serial/8250/8250_core.c index deae122c9c4b..422ebea96a64 100644 --- a/drivers/tty/serial/8250/8250_core.c +++ b/drivers/tty/serial/8250/8250_core.c | |||
@@ -31,7 +31,6 @@ | |||
31 | #include <linux/tty.h> | 31 | #include <linux/tty.h> |
32 | #include <linux/ratelimit.h> | 32 | #include <linux/ratelimit.h> |
33 | #include <linux/tty_flip.h> | 33 | #include <linux/tty_flip.h> |
34 | #include <linux/serial_core.h> | ||
35 | #include <linux/serial.h> | 34 | #include <linux/serial.h> |
36 | #include <linux/serial_8250.h> | 35 | #include <linux/serial_8250.h> |
37 | #include <linux/nmi.h> | 36 | #include <linux/nmi.h> |
@@ -61,7 +60,7 @@ static struct uart_driver serial8250_reg; | |||
61 | 60 | ||
62 | static int serial_index(struct uart_port *port) | 61 | static int serial_index(struct uart_port *port) |
63 | { | 62 | { |
64 | return (serial8250_reg.minor - 64) + port->line; | 63 | return port->minor - 64; |
65 | } | 64 | } |
66 | 65 | ||
67 | static unsigned int skip_txen_test; /* force skip of txen test at init time */ | 66 | static unsigned int skip_txen_test; /* force skip of txen test at init time */ |
@@ -358,34 +357,46 @@ static void default_serial_dl_write(struct uart_8250_port *up, int value) | |||
358 | #if defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_SERIAL_8250_RT288X) | 357 | #if defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_SERIAL_8250_RT288X) |
359 | 358 | ||
360 | /* Au1x00/RT288x UART hardware has a weird register layout */ | 359 | /* Au1x00/RT288x UART hardware has a weird register layout */ |
361 | static const u8 au_io_in_map[] = { | 360 | static const s8 au_io_in_map[8] = { |
362 | [UART_RX] = 0, | 361 | 0, /* UART_RX */ |
363 | [UART_IER] = 2, | 362 | 2, /* UART_IER */ |
364 | [UART_IIR] = 3, | 363 | 3, /* UART_IIR */ |
365 | [UART_LCR] = 5, | 364 | 5, /* UART_LCR */ |
366 | [UART_MCR] = 6, | 365 | 6, /* UART_MCR */ |
367 | [UART_LSR] = 7, | 366 | 7, /* UART_LSR */ |
368 | [UART_MSR] = 8, | 367 | 8, /* UART_MSR */ |
368 | -1, /* UART_SCR (unmapped) */ | ||
369 | }; | 369 | }; |
370 | 370 | ||
371 | static const u8 au_io_out_map[] = { | 371 | static const s8 au_io_out_map[8] = { |
372 | [UART_TX] = 1, | 372 | 1, /* UART_TX */ |
373 | [UART_IER] = 2, | 373 | 2, /* UART_IER */ |
374 | [UART_FCR] = 4, | 374 | 4, /* UART_FCR */ |
375 | [UART_LCR] = 5, | 375 | 5, /* UART_LCR */ |
376 | [UART_MCR] = 6, | 376 | 6, /* UART_MCR */ |
377 | -1, /* UART_LSR (unmapped) */ | ||
378 | -1, /* UART_MSR (unmapped) */ | ||
379 | -1, /* UART_SCR (unmapped) */ | ||
377 | }; | 380 | }; |
378 | 381 | ||
379 | static unsigned int au_serial_in(struct uart_port *p, int offset) | 382 | static unsigned int au_serial_in(struct uart_port *p, int offset) |
380 | { | 383 | { |
381 | offset = au_io_in_map[offset] << p->regshift; | 384 | if (offset >= ARRAY_SIZE(au_io_in_map)) |
382 | return __raw_readl(p->membase + offset); | 385 | return UINT_MAX; |
386 | offset = au_io_in_map[offset]; | ||
387 | if (offset < 0) | ||
388 | return UINT_MAX; | ||
389 | return __raw_readl(p->membase + (offset << p->regshift)); | ||
383 | } | 390 | } |
384 | 391 | ||
385 | static void au_serial_out(struct uart_port *p, int offset, int value) | 392 | static void au_serial_out(struct uart_port *p, int offset, int value) |
386 | { | 393 | { |
387 | offset = au_io_out_map[offset] << p->regshift; | 394 | if (offset >= ARRAY_SIZE(au_io_out_map)) |
388 | __raw_writel(value, p->membase + offset); | 395 | return; |
396 | offset = au_io_out_map[offset]; | ||
397 | if (offset < 0) | ||
398 | return; | ||
399 | __raw_writel(value, p->membase + (offset << p->regshift)); | ||
389 | } | 400 | } |
390 | 401 | ||
391 | /* Au1x00 haven't got a standard divisor latch */ | 402 | /* Au1x00 haven't got a standard divisor latch */ |
@@ -895,7 +906,7 @@ static int broken_efr(struct uart_8250_port *up) | |||
895 | /* | 906 | /* |
896 | * Exar ST16C2550 "A2" devices incorrectly detect as | 907 | * Exar ST16C2550 "A2" devices incorrectly detect as |
897 | * having an EFR, and report an ID of 0x0201. See | 908 | * having an EFR, and report an ID of 0x0201. See |
898 | * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html | 909 | * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html |
899 | */ | 910 | */ |
900 | if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16) | 911 | if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16) |
901 | return 1; | 912 | return 1; |
@@ -903,23 +914,6 @@ static int broken_efr(struct uart_8250_port *up) | |||
903 | return 0; | 914 | return 0; |
904 | } | 915 | } |
905 | 916 | ||
906 | static inline int ns16550a_goto_highspeed(struct uart_8250_port *up) | ||
907 | { | ||
908 | unsigned char status; | ||
909 | |||
910 | status = serial_in(up, 0x04); /* EXCR2 */ | ||
911 | #define PRESL(x) ((x) & 0x30) | ||
912 | if (PRESL(status) == 0x10) { | ||
913 | /* already in high speed mode */ | ||
914 | return 0; | ||
915 | } else { | ||
916 | status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */ | ||
917 | status |= 0x10; /* 1.625 divisor for baud_base --> 921600 */ | ||
918 | serial_out(up, 0x04, status); | ||
919 | } | ||
920 | return 1; | ||
921 | } | ||
922 | |||
923 | /* | 917 | /* |
924 | * We know that the chip has FIFOs. Does it have an EFR? The | 918 | * We know that the chip has FIFOs. Does it have an EFR? The |
925 | * EFR is located in the same register position as the IIR and | 919 | * EFR is located in the same register position as the IIR and |
@@ -1122,7 +1116,7 @@ static void autoconfig_16550a(struct uart_8250_port *up) | |||
1122 | * whether or not this UART is a 16550A or not, since this will | 1116 | * whether or not this UART is a 16550A or not, since this will |
1123 | * determine whether or not we can use its FIFO features or not. | 1117 | * determine whether or not we can use its FIFO features or not. |
1124 | */ | 1118 | */ |
1125 | static void autoconfig(struct uart_8250_port *up, unsigned int probeflags) | 1119 | static void autoconfig(struct uart_8250_port *up) |
1126 | { | 1120 | { |
1127 | unsigned char status1, scratch, scratch2, scratch3; | 1121 | unsigned char status1, scratch, scratch2, scratch3; |
1128 | unsigned char save_lcr, save_mcr; | 1122 | unsigned char save_lcr, save_mcr; |
@@ -1245,22 +1239,15 @@ static void autoconfig(struct uart_8250_port *up, unsigned int probeflags) | |||
1245 | /* | 1239 | /* |
1246 | * Only probe for RSA ports if we got the region. | 1240 | * Only probe for RSA ports if we got the region. |
1247 | */ | 1241 | */ |
1248 | if (port->type == PORT_16550A && probeflags & PROBE_RSA) { | 1242 | if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA && |
1249 | int i; | 1243 | __enable_rsa(up)) |
1250 | 1244 | port->type = PORT_RSA; | |
1251 | for (i = 0 ; i < probe_rsa_count; ++i) { | ||
1252 | if (probe_rsa[i] == port->iobase && __enable_rsa(up)) { | ||
1253 | port->type = PORT_RSA; | ||
1254 | break; | ||
1255 | } | ||
1256 | } | ||
1257 | } | ||
1258 | #endif | 1245 | #endif |
1259 | 1246 | ||
1260 | serial_out(up, UART_LCR, save_lcr); | 1247 | serial_out(up, UART_LCR, save_lcr); |
1261 | 1248 | ||
1262 | port->fifosize = uart_config[up->port.type].fifo_size; | 1249 | port->fifosize = uart_config[up->port.type].fifo_size; |
1263 | old_capabilities = up->capabilities; | 1250 | old_capabilities = up->capabilities; |
1264 | up->capabilities = uart_config[port->type].flags; | 1251 | up->capabilities = uart_config[port->type].flags; |
1265 | up->tx_loadsz = uart_config[port->type].tx_loadsz; | 1252 | up->tx_loadsz = uart_config[port->type].tx_loadsz; |
1266 | 1253 | ||
@@ -1907,6 +1894,48 @@ static void serial8250_backup_timeout(unsigned long data) | |||
1907 | jiffies + uart_poll_timeout(&up->port) + HZ / 5); | 1894 | jiffies + uart_poll_timeout(&up->port) + HZ / 5); |
1908 | } | 1895 | } |
1909 | 1896 | ||
1897 | static int univ8250_setup_irq(struct uart_8250_port *up) | ||
1898 | { | ||
1899 | struct uart_port *port = &up->port; | ||
1900 | int retval = 0; | ||
1901 | |||
1902 | /* | ||
1903 | * The above check will only give an accurate result the first time | ||
1904 | * the port is opened so this value needs to be preserved. | ||
1905 | */ | ||
1906 | if (up->bugs & UART_BUG_THRE) { | ||
1907 | pr_debug("ttyS%d - using backup timer\n", serial_index(port)); | ||
1908 | |||
1909 | up->timer.function = serial8250_backup_timeout; | ||
1910 | up->timer.data = (unsigned long)up; | ||
1911 | mod_timer(&up->timer, jiffies + | ||
1912 | uart_poll_timeout(port) + HZ / 5); | ||
1913 | } | ||
1914 | |||
1915 | /* | ||
1916 | * If the "interrupt" for this port doesn't correspond with any | ||
1917 | * hardware interrupt, we use a timer-based system. The original | ||
1918 | * driver used to do this with IRQ0. | ||
1919 | */ | ||
1920 | if (!port->irq) { | ||
1921 | up->timer.data = (unsigned long)up; | ||
1922 | mod_timer(&up->timer, jiffies + uart_poll_timeout(port)); | ||
1923 | } else | ||
1924 | retval = serial_link_irq_chain(up); | ||
1925 | |||
1926 | return retval; | ||
1927 | } | ||
1928 | |||
1929 | static void univ8250_release_irq(struct uart_8250_port *up) | ||
1930 | { | ||
1931 | struct uart_port *port = &up->port; | ||
1932 | |||
1933 | del_timer_sync(&up->timer); | ||
1934 | up->timer.function = serial8250_timeout; | ||
1935 | if (port->irq) | ||
1936 | serial_unlink_irq_chain(up); | ||
1937 | } | ||
1938 | |||
1910 | static unsigned int serial8250_tx_empty(struct uart_port *port) | 1939 | static unsigned int serial8250_tx_empty(struct uart_port *port) |
1911 | { | 1940 | { |
1912 | struct uart_8250_port *up = up_to_u8250p(port); | 1941 | struct uart_8250_port *up = up_to_u8250p(port); |
@@ -2211,35 +2240,12 @@ int serial8250_do_startup(struct uart_port *port) | |||
2211 | if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) || | 2240 | if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) || |
2212 | up->port.flags & UPF_BUG_THRE) { | 2241 | up->port.flags & UPF_BUG_THRE) { |
2213 | up->bugs |= UART_BUG_THRE; | 2242 | up->bugs |= UART_BUG_THRE; |
2214 | pr_debug("ttyS%d - using backup timer\n", | ||
2215 | serial_index(port)); | ||
2216 | } | 2243 | } |
2217 | } | 2244 | } |
2218 | 2245 | ||
2219 | /* | 2246 | retval = up->ops->setup_irq(up); |
2220 | * The above check will only give an accurate result the first time | 2247 | if (retval) |
2221 | * the port is opened so this value needs to be preserved. | 2248 | goto out; |
2222 | */ | ||
2223 | if (up->bugs & UART_BUG_THRE) { | ||
2224 | up->timer.function = serial8250_backup_timeout; | ||
2225 | up->timer.data = (unsigned long)up; | ||
2226 | mod_timer(&up->timer, jiffies + | ||
2227 | uart_poll_timeout(port) + HZ / 5); | ||
2228 | } | ||
2229 | |||
2230 | /* | ||
2231 | * If the "interrupt" for this port doesn't correspond with any | ||
2232 | * hardware interrupt, we use a timer-based system. The original | ||
2233 | * driver used to do this with IRQ0. | ||
2234 | */ | ||
2235 | if (!port->irq) { | ||
2236 | up->timer.data = (unsigned long)up; | ||
2237 | mod_timer(&up->timer, jiffies + uart_poll_timeout(port)); | ||
2238 | } else { | ||
2239 | retval = serial_link_irq_chain(up); | ||
2240 | if (retval) | ||
2241 | goto out; | ||
2242 | } | ||
2243 | 2249 | ||
2244 | /* | 2250 | /* |
2245 | * Now, initialize the UART | 2251 | * Now, initialize the UART |
@@ -2270,7 +2276,7 @@ int serial8250_do_startup(struct uart_port *port) | |||
2270 | is variable. So, let's just don't test if we receive | 2276 | is variable. So, let's just don't test if we receive |
2271 | TX irq. This way, we'll never enable UART_BUG_TXEN. | 2277 | TX irq. This way, we'll never enable UART_BUG_TXEN. |
2272 | */ | 2278 | */ |
2273 | if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST) | 2279 | if (up->port.flags & UPF_NO_TXEN_TEST) |
2274 | goto dont_test_tx_en; | 2280 | goto dont_test_tx_en; |
2275 | 2281 | ||
2276 | /* | 2282 | /* |
@@ -2397,10 +2403,7 @@ void serial8250_do_shutdown(struct uart_port *port) | |||
2397 | serial_port_in(port, UART_RX); | 2403 | serial_port_in(port, UART_RX); |
2398 | serial8250_rpm_put(up); | 2404 | serial8250_rpm_put(up); |
2399 | 2405 | ||
2400 | del_timer_sync(&up->timer); | 2406 | up->ops->release_irq(up); |
2401 | up->timer.function = serial8250_timeout; | ||
2402 | if (port->irq) | ||
2403 | serial_unlink_irq_chain(up); | ||
2404 | } | 2407 | } |
2405 | EXPORT_SYMBOL_GPL(serial8250_do_shutdown); | 2408 | EXPORT_SYMBOL_GPL(serial8250_do_shutdown); |
2406 | 2409 | ||
@@ -2719,6 +2722,8 @@ serial8250_pm(struct uart_port *port, unsigned int state, | |||
2719 | 2722 | ||
2720 | static unsigned int serial8250_port_size(struct uart_8250_port *pt) | 2723 | static unsigned int serial8250_port_size(struct uart_8250_port *pt) |
2721 | { | 2724 | { |
2725 | if (pt->port.mapsize) | ||
2726 | return pt->port.mapsize; | ||
2722 | if (pt->port.iotype == UPIO_AU) { | 2727 | if (pt->port.iotype == UPIO_AU) { |
2723 | if (pt->port.type == PORT_RT2880) | 2728 | if (pt->port.type == PORT_RT2880) |
2724 | return 0x100; | 2729 | return 0x100; |
@@ -2798,6 +2803,7 @@ static void serial8250_release_std_resource(struct uart_8250_port *up) | |||
2798 | } | 2803 | } |
2799 | } | 2804 | } |
2800 | 2805 | ||
2806 | #ifdef CONFIG_SERIAL_8250_RSA | ||
2801 | static int serial8250_request_rsa_resource(struct uart_8250_port *up) | 2807 | static int serial8250_request_rsa_resource(struct uart_8250_port *up) |
2802 | { | 2808 | { |
2803 | unsigned long start = UART_RSA_BASE << up->port.regshift; | 2809 | unsigned long start = UART_RSA_BASE << up->port.regshift; |
@@ -2832,14 +2838,13 @@ static void serial8250_release_rsa_resource(struct uart_8250_port *up) | |||
2832 | break; | 2838 | break; |
2833 | } | 2839 | } |
2834 | } | 2840 | } |
2841 | #endif | ||
2835 | 2842 | ||
2836 | static void serial8250_release_port(struct uart_port *port) | 2843 | static void serial8250_release_port(struct uart_port *port) |
2837 | { | 2844 | { |
2838 | struct uart_8250_port *up = up_to_u8250p(port); | 2845 | struct uart_8250_port *up = up_to_u8250p(port); |
2839 | 2846 | ||
2840 | serial8250_release_std_resource(up); | 2847 | serial8250_release_std_resource(up); |
2841 | if (port->type == PORT_RSA) | ||
2842 | serial8250_release_rsa_resource(up); | ||
2843 | } | 2848 | } |
2844 | 2849 | ||
2845 | static int serial8250_request_port(struct uart_port *port) | 2850 | static int serial8250_request_port(struct uart_port *port) |
@@ -2851,11 +2856,6 @@ static int serial8250_request_port(struct uart_port *port) | |||
2851 | return -ENODEV; | 2856 | return -ENODEV; |
2852 | 2857 | ||
2853 | ret = serial8250_request_std_resource(up); | 2858 | ret = serial8250_request_std_resource(up); |
2854 | if (ret == 0 && port->type == PORT_RSA) { | ||
2855 | ret = serial8250_request_rsa_resource(up); | ||
2856 | if (ret < 0) | ||
2857 | serial8250_release_std_resource(up); | ||
2858 | } | ||
2859 | 2859 | ||
2860 | return ret; | 2860 | return ret; |
2861 | } | 2861 | } |
@@ -3003,7 +3003,6 @@ static void register_dev_spec_attr_grp(struct uart_8250_port *up) | |||
3003 | static void serial8250_config_port(struct uart_port *port, int flags) | 3003 | static void serial8250_config_port(struct uart_port *port, int flags) |
3004 | { | 3004 | { |
3005 | struct uart_8250_port *up = up_to_u8250p(port); | 3005 | struct uart_8250_port *up = up_to_u8250p(port); |
3006 | int probeflags = PROBE_ANY; | ||
3007 | int ret; | 3006 | int ret; |
3008 | 3007 | ||
3009 | if (port->type == PORT_8250_CIR) | 3008 | if (port->type == PORT_8250_CIR) |
@@ -3017,15 +3016,11 @@ static void serial8250_config_port(struct uart_port *port, int flags) | |||
3017 | if (ret < 0) | 3016 | if (ret < 0) |
3018 | return; | 3017 | return; |
3019 | 3018 | ||
3020 | ret = serial8250_request_rsa_resource(up); | ||
3021 | if (ret < 0) | ||
3022 | probeflags &= ~PROBE_RSA; | ||
3023 | |||
3024 | if (port->iotype != up->cur_iotype) | 3019 | if (port->iotype != up->cur_iotype) |
3025 | set_io_from_upio(port); | 3020 | set_io_from_upio(port); |
3026 | 3021 | ||
3027 | if (flags & UART_CONFIG_TYPE) | 3022 | if (flags & UART_CONFIG_TYPE) |
3028 | autoconfig(up, probeflags); | 3023 | autoconfig(up); |
3029 | 3024 | ||
3030 | /* if access method is AU, it is a 16550 with a quirk */ | 3025 | /* if access method is AU, it is a 16550 with a quirk */ |
3031 | if (port->type == PORT_16550A && port->iotype == UPIO_AU) | 3026 | if (port->type == PORT_16550A && port->iotype == UPIO_AU) |
@@ -3038,8 +3033,6 @@ static void serial8250_config_port(struct uart_port *port, int flags) | |||
3038 | if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ) | 3033 | if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ) |
3039 | autoconfig_irq(up); | 3034 | autoconfig_irq(up); |
3040 | 3035 | ||
3041 | if (port->type != PORT_RSA && probeflags & PROBE_RSA) | ||
3042 | serial8250_release_rsa_resource(up); | ||
3043 | if (port->type == PORT_UNKNOWN) | 3036 | if (port->type == PORT_UNKNOWN) |
3044 | serial8250_release_std_resource(up); | 3037 | serial8250_release_std_resource(up); |
3045 | 3038 | ||
@@ -3073,7 +3066,7 @@ serial8250_type(struct uart_port *port) | |||
3073 | return uart_config[type].name; | 3066 | return uart_config[type].name; |
3074 | } | 3067 | } |
3075 | 3068 | ||
3076 | static struct uart_ops serial8250_pops = { | 3069 | static const struct uart_ops serial8250_pops = { |
3077 | .tx_empty = serial8250_tx_empty, | 3070 | .tx_empty = serial8250_tx_empty, |
3078 | .set_mctrl = serial8250_set_mctrl, | 3071 | .set_mctrl = serial8250_set_mctrl, |
3079 | .get_mctrl = serial8250_get_mctrl, | 3072 | .get_mctrl = serial8250_get_mctrl, |
@@ -3100,6 +3093,14 @@ static struct uart_ops serial8250_pops = { | |||
3100 | #endif | 3093 | #endif |
3101 | }; | 3094 | }; |
3102 | 3095 | ||
3096 | static const struct uart_ops *base_ops; | ||
3097 | static struct uart_ops univ8250_port_ops; | ||
3098 | |||
3099 | static const struct uart_8250_ops univ8250_driver_ops = { | ||
3100 | .setup_irq = univ8250_setup_irq, | ||
3101 | .release_irq = univ8250_release_irq, | ||
3102 | }; | ||
3103 | |||
3103 | static struct uart_8250_port serial8250_ports[UART_NR]; | 3104 | static struct uart_8250_port serial8250_ports[UART_NR]; |
3104 | 3105 | ||
3105 | /** | 3106 | /** |
@@ -3130,6 +3131,105 @@ void serial8250_set_isa_configurator( | |||
3130 | } | 3131 | } |
3131 | EXPORT_SYMBOL(serial8250_set_isa_configurator); | 3132 | EXPORT_SYMBOL(serial8250_set_isa_configurator); |
3132 | 3133 | ||
3134 | static void serial8250_init_port(struct uart_8250_port *up) | ||
3135 | { | ||
3136 | struct uart_port *port = &up->port; | ||
3137 | |||
3138 | spin_lock_init(&port->lock); | ||
3139 | port->ops = &serial8250_pops; | ||
3140 | |||
3141 | up->cur_iotype = 0xFF; | ||
3142 | } | ||
3143 | |||
3144 | static void serial8250_set_defaults(struct uart_8250_port *up) | ||
3145 | { | ||
3146 | struct uart_port *port = &up->port; | ||
3147 | |||
3148 | if (up->port.flags & UPF_FIXED_TYPE) { | ||
3149 | unsigned int type = up->port.type; | ||
3150 | |||
3151 | if (!up->port.fifosize) | ||
3152 | up->port.fifosize = uart_config[type].fifo_size; | ||
3153 | if (!up->tx_loadsz) | ||
3154 | up->tx_loadsz = uart_config[type].tx_loadsz; | ||
3155 | if (!up->capabilities) | ||
3156 | up->capabilities = uart_config[type].flags; | ||
3157 | } | ||
3158 | |||
3159 | set_io_from_upio(port); | ||
3160 | |||
3161 | /* default dma handlers */ | ||
3162 | if (up->dma) { | ||
3163 | if (!up->dma->tx_dma) | ||
3164 | up->dma->tx_dma = serial8250_tx_dma; | ||
3165 | if (!up->dma->rx_dma) | ||
3166 | up->dma->rx_dma = serial8250_rx_dma; | ||
3167 | } | ||
3168 | } | ||
3169 | |||
3170 | #ifdef CONFIG_SERIAL_8250_RSA | ||
3171 | |||
3172 | static void univ8250_config_port(struct uart_port *port, int flags) | ||
3173 | { | ||
3174 | struct uart_8250_port *up = up_to_u8250p(port); | ||
3175 | |||
3176 | up->probe &= ~UART_PROBE_RSA; | ||
3177 | if (port->type == PORT_RSA) { | ||
3178 | if (serial8250_request_rsa_resource(up) == 0) | ||
3179 | up->probe |= UART_PROBE_RSA; | ||
3180 | } else if (flags & UART_CONFIG_TYPE) { | ||
3181 | int i; | ||
3182 | |||
3183 | for (i = 0; i < probe_rsa_count; i++) { | ||
3184 | if (probe_rsa[i] == up->port.iobase) { | ||
3185 | if (serial8250_request_rsa_resource(up) == 0) | ||
3186 | up->probe |= UART_PROBE_RSA; | ||
3187 | break; | ||
3188 | } | ||
3189 | } | ||
3190 | } | ||
3191 | |||
3192 | base_ops->config_port(port, flags); | ||
3193 | |||
3194 | if (port->type != PORT_RSA && up->probe & UART_PROBE_RSA) | ||
3195 | serial8250_release_rsa_resource(up); | ||
3196 | } | ||
3197 | |||
3198 | static int univ8250_request_port(struct uart_port *port) | ||
3199 | { | ||
3200 | struct uart_8250_port *up = up_to_u8250p(port); | ||
3201 | int ret; | ||
3202 | |||
3203 | ret = base_ops->request_port(port); | ||
3204 | if (ret == 0 && port->type == PORT_RSA) { | ||
3205 | ret = serial8250_request_rsa_resource(up); | ||
3206 | if (ret < 0) | ||
3207 | base_ops->release_port(port); | ||
3208 | } | ||
3209 | |||
3210 | return ret; | ||
3211 | } | ||
3212 | |||
3213 | static void univ8250_release_port(struct uart_port *port) | ||
3214 | { | ||
3215 | struct uart_8250_port *up = up_to_u8250p(port); | ||
3216 | |||
3217 | if (port->type == PORT_RSA) | ||
3218 | serial8250_release_rsa_resource(up); | ||
3219 | base_ops->release_port(port); | ||
3220 | } | ||
3221 | |||
3222 | static void univ8250_rsa_support(struct uart_ops *ops) | ||
3223 | { | ||
3224 | ops->config_port = univ8250_config_port; | ||
3225 | ops->request_port = univ8250_request_port; | ||
3226 | ops->release_port = univ8250_release_port; | ||
3227 | } | ||
3228 | |||
3229 | #else | ||
3230 | #define univ8250_rsa_support(x) do { } while (0) | ||
3231 | #endif /* CONFIG_SERIAL_8250_RSA */ | ||
3232 | |||
3133 | static void __init serial8250_isa_init_ports(void) | 3233 | static void __init serial8250_isa_init_ports(void) |
3134 | { | 3234 | { |
3135 | struct uart_8250_port *up; | 3235 | struct uart_8250_port *up; |
@@ -3148,21 +3248,27 @@ static void __init serial8250_isa_init_ports(void) | |||
3148 | struct uart_port *port = &up->port; | 3248 | struct uart_port *port = &up->port; |
3149 | 3249 | ||
3150 | port->line = i; | 3250 | port->line = i; |
3151 | spin_lock_init(&port->lock); | 3251 | serial8250_init_port(up); |
3252 | if (!base_ops) | ||
3253 | base_ops = port->ops; | ||
3254 | port->ops = &univ8250_port_ops; | ||
3152 | 3255 | ||
3153 | init_timer(&up->timer); | 3256 | init_timer(&up->timer); |
3154 | up->timer.function = serial8250_timeout; | 3257 | up->timer.function = serial8250_timeout; |
3155 | up->cur_iotype = 0xFF; | 3258 | |
3259 | up->ops = &univ8250_driver_ops; | ||
3156 | 3260 | ||
3157 | /* | 3261 | /* |
3158 | * ALPHA_KLUDGE_MCR needs to be killed. | 3262 | * ALPHA_KLUDGE_MCR needs to be killed. |
3159 | */ | 3263 | */ |
3160 | up->mcr_mask = ~ALPHA_KLUDGE_MCR; | 3264 | up->mcr_mask = ~ALPHA_KLUDGE_MCR; |
3161 | up->mcr_force = ALPHA_KLUDGE_MCR; | 3265 | up->mcr_force = ALPHA_KLUDGE_MCR; |
3162 | |||
3163 | port->ops = &serial8250_pops; | ||
3164 | } | 3266 | } |
3165 | 3267 | ||
3268 | /* chain base port ops to support Remote Supervisor Adapter */ | ||
3269 | univ8250_port_ops = *base_ops; | ||
3270 | univ8250_rsa_support(&univ8250_port_ops); | ||
3271 | |||
3166 | if (share_irqs) | 3272 | if (share_irqs) |
3167 | irqflag = IRQF_SHARED; | 3273 | irqflag = IRQF_SHARED; |
3168 | 3274 | ||
@@ -3180,26 +3286,14 @@ static void __init serial8250_isa_init_ports(void) | |||
3180 | port->membase = old_serial_port[i].iomem_base; | 3286 | port->membase = old_serial_port[i].iomem_base; |
3181 | port->iotype = old_serial_port[i].io_type; | 3287 | port->iotype = old_serial_port[i].io_type; |
3182 | port->regshift = old_serial_port[i].iomem_reg_shift; | 3288 | port->regshift = old_serial_port[i].iomem_reg_shift; |
3183 | set_io_from_upio(port); | 3289 | serial8250_set_defaults(up); |
3290 | |||
3184 | port->irqflags |= irqflag; | 3291 | port->irqflags |= irqflag; |
3185 | if (serial8250_isa_config != NULL) | 3292 | if (serial8250_isa_config != NULL) |
3186 | serial8250_isa_config(i, &up->port, &up->capabilities); | 3293 | serial8250_isa_config(i, &up->port, &up->capabilities); |
3187 | |||
3188 | } | 3294 | } |
3189 | } | 3295 | } |
3190 | 3296 | ||
3191 | static void | ||
3192 | serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type) | ||
3193 | { | ||
3194 | up->port.type = type; | ||
3195 | if (!up->port.fifosize) | ||
3196 | up->port.fifosize = uart_config[type].fifo_size; | ||
3197 | if (!up->tx_loadsz) | ||
3198 | up->tx_loadsz = uart_config[type].tx_loadsz; | ||
3199 | if (!up->capabilities) | ||
3200 | up->capabilities = uart_config[type].flags; | ||
3201 | } | ||
3202 | |||
3203 | static void __init | 3297 | static void __init |
3204 | serial8250_register_ports(struct uart_driver *drv, struct device *dev) | 3298 | serial8250_register_ports(struct uart_driver *drv, struct device *dev) |
3205 | { | 3299 | { |
@@ -3213,8 +3307,8 @@ serial8250_register_ports(struct uart_driver *drv, struct device *dev) | |||
3213 | 3307 | ||
3214 | up->port.dev = dev; | 3308 | up->port.dev = dev; |
3215 | 3309 | ||
3216 | if (up->port.flags & UPF_FIXED_TYPE) | 3310 | if (skip_txen_test) |
3217 | serial8250_init_fixed_type_port(up, up->port.type); | 3311 | up->port.flags |= UPF_NO_TXEN_TEST; |
3218 | 3312 | ||
3219 | uart_add_one_port(drv, &up->port); | 3313 | uart_add_one_port(drv, &up->port); |
3220 | } | 3314 | } |
@@ -3236,10 +3330,9 @@ static void serial8250_console_putchar(struct uart_port *port, int ch) | |||
3236 | * | 3330 | * |
3237 | * The console_lock must be held when we get here. | 3331 | * The console_lock must be held when we get here. |
3238 | */ | 3332 | */ |
3239 | static void | 3333 | static void serial8250_console_write(struct uart_8250_port *up, const char *s, |
3240 | serial8250_console_write(struct console *co, const char *s, unsigned int count) | 3334 | unsigned int count) |
3241 | { | 3335 | { |
3242 | struct uart_8250_port *up = &serial8250_ports[co->index]; | ||
3243 | struct uart_port *port = &up->port; | 3336 | struct uart_port *port = &up->port; |
3244 | unsigned long flags; | 3337 | unsigned long flags; |
3245 | unsigned int ier; | 3338 | unsigned int ier; |
@@ -3311,14 +3404,51 @@ serial8250_console_write(struct console *co, const char *s, unsigned int count) | |||
3311 | serial8250_rpm_put(up); | 3404 | serial8250_rpm_put(up); |
3312 | } | 3405 | } |
3313 | 3406 | ||
3314 | static int serial8250_console_setup(struct console *co, char *options) | 3407 | static void univ8250_console_write(struct console *co, const char *s, |
3408 | unsigned int count) | ||
3409 | { | ||
3410 | struct uart_8250_port *up = &serial8250_ports[co->index]; | ||
3411 | |||
3412 | serial8250_console_write(up, s, count); | ||
3413 | } | ||
3414 | |||
3415 | static unsigned int probe_baud(struct uart_port *port) | ||
3416 | { | ||
3417 | unsigned char lcr, dll, dlm; | ||
3418 | unsigned int quot; | ||
3419 | |||
3420 | lcr = serial_port_in(port, UART_LCR); | ||
3421 | serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB); | ||
3422 | dll = serial_port_in(port, UART_DLL); | ||
3423 | dlm = serial_port_in(port, UART_DLM); | ||
3424 | serial_port_out(port, UART_LCR, lcr); | ||
3425 | |||
3426 | quot = (dlm << 8) | dll; | ||
3427 | return (port->uartclk / 16) / quot; | ||
3428 | } | ||
3429 | |||
3430 | static int serial8250_console_setup(struct uart_port *port, char *options, bool probe) | ||
3315 | { | 3431 | { |
3316 | struct uart_port *port; | ||
3317 | int baud = 9600; | 3432 | int baud = 9600; |
3318 | int bits = 8; | 3433 | int bits = 8; |
3319 | int parity = 'n'; | 3434 | int parity = 'n'; |
3320 | int flow = 'n'; | 3435 | int flow = 'n'; |
3321 | 3436 | ||
3437 | if (!port->iobase && !port->membase) | ||
3438 | return -ENODEV; | ||
3439 | |||
3440 | if (options) | ||
3441 | uart_parse_options(options, &baud, &parity, &bits, &flow); | ||
3442 | else if (probe) | ||
3443 | baud = probe_baud(port); | ||
3444 | |||
3445 | return uart_set_options(port, port->cons, baud, parity, bits, flow); | ||
3446 | } | ||
3447 | |||
3448 | static int univ8250_console_setup(struct console *co, char *options) | ||
3449 | { | ||
3450 | struct uart_port *port; | ||
3451 | |||
3322 | /* | 3452 | /* |
3323 | * Check whether an invalid uart number has been specified, and | 3453 | * Check whether an invalid uart number has been specified, and |
3324 | * if so, search for the first available port that does have | 3454 | * if so, search for the first available port that does have |
@@ -3327,53 +3457,84 @@ static int serial8250_console_setup(struct console *co, char *options) | |||
3327 | if (co->index >= nr_uarts) | 3457 | if (co->index >= nr_uarts) |
3328 | co->index = 0; | 3458 | co->index = 0; |
3329 | port = &serial8250_ports[co->index].port; | 3459 | port = &serial8250_ports[co->index].port; |
3330 | if (!port->iobase && !port->membase) | 3460 | /* link port to console */ |
3331 | return -ENODEV; | 3461 | port->cons = co; |
3332 | 3462 | ||
3333 | if (options) | 3463 | return serial8250_console_setup(port, options, false); |
3334 | uart_parse_options(options, &baud, &parity, &bits, &flow); | ||
3335 | |||
3336 | return uart_set_options(port, co, baud, parity, bits, flow); | ||
3337 | } | 3464 | } |
3338 | 3465 | ||
3339 | static int serial8250_console_early_setup(void) | 3466 | /** |
3467 | * univ8250_console_match - non-standard console matching | ||
3468 | * @co: registering console | ||
3469 | * @name: name from console command line | ||
3470 | * @idx: index from console command line | ||
3471 | * @options: ptr to option string from console command line | ||
3472 | * | ||
3473 | * Only attempts to match console command lines of the form: | ||
3474 | * console=uart[8250],io|mmio|mmio32,<addr>[,<options>] | ||
3475 | * console=uart[8250],0x<addr>[,<options>] | ||
3476 | * This form is used to register an initial earlycon boot console and | ||
3477 | * replace it with the serial8250_console at 8250 driver init. | ||
3478 | * | ||
3479 | * Performs console setup for a match (as required by interface) | ||
3480 | * If no <options> are specified, then assume the h/w is already setup. | ||
3481 | * | ||
3482 | * Returns 0 if console matches; otherwise non-zero to use default matching | ||
3483 | */ | ||
3484 | static int univ8250_console_match(struct console *co, char *name, int idx, | ||
3485 | char *options) | ||
3340 | { | 3486 | { |
3341 | return serial8250_find_port_for_earlycon(); | 3487 | char match[] = "uart"; /* 8250-specific earlycon name */ |
3488 | unsigned char iotype; | ||
3489 | unsigned long addr; | ||
3490 | int i; | ||
3491 | |||
3492 | if (strncmp(name, match, 4) != 0) | ||
3493 | return -ENODEV; | ||
3494 | |||
3495 | if (uart_parse_earlycon(options, &iotype, &addr, &options)) | ||
3496 | return -ENODEV; | ||
3497 | |||
3498 | /* try to match the port specified on the command line */ | ||
3499 | for (i = 0; i < nr_uarts; i++) { | ||
3500 | struct uart_port *port = &serial8250_ports[i].port; | ||
3501 | |||
3502 | if (port->iotype != iotype) | ||
3503 | continue; | ||
3504 | if ((iotype == UPIO_MEM || iotype == UPIO_MEM32) && | ||
3505 | (port->mapbase != addr)) | ||
3506 | continue; | ||
3507 | if (iotype == UPIO_PORT && port->iobase != addr) | ||
3508 | continue; | ||
3509 | |||
3510 | co->index = i; | ||
3511 | port->cons = co; | ||
3512 | return serial8250_console_setup(port, options, true); | ||
3513 | } | ||
3514 | |||
3515 | return -ENODEV; | ||
3342 | } | 3516 | } |
3343 | 3517 | ||
3344 | static struct console serial8250_console = { | 3518 | static struct console univ8250_console = { |
3345 | .name = "ttyS", | 3519 | .name = "ttyS", |
3346 | .write = serial8250_console_write, | 3520 | .write = univ8250_console_write, |
3347 | .device = uart_console_device, | 3521 | .device = uart_console_device, |
3348 | .setup = serial8250_console_setup, | 3522 | .setup = univ8250_console_setup, |
3349 | .early_setup = serial8250_console_early_setup, | 3523 | .match = univ8250_console_match, |
3350 | .flags = CON_PRINTBUFFER | CON_ANYTIME, | 3524 | .flags = CON_PRINTBUFFER | CON_ANYTIME, |
3351 | .index = -1, | 3525 | .index = -1, |
3352 | .data = &serial8250_reg, | 3526 | .data = &serial8250_reg, |
3353 | }; | 3527 | }; |
3354 | 3528 | ||
3355 | static int __init serial8250_console_init(void) | 3529 | static int __init univ8250_console_init(void) |
3356 | { | 3530 | { |
3357 | serial8250_isa_init_ports(); | 3531 | serial8250_isa_init_ports(); |
3358 | register_console(&serial8250_console); | 3532 | register_console(&univ8250_console); |
3359 | return 0; | 3533 | return 0; |
3360 | } | 3534 | } |
3361 | console_initcall(serial8250_console_init); | 3535 | console_initcall(univ8250_console_init); |
3362 | |||
3363 | int serial8250_find_port(struct uart_port *p) | ||
3364 | { | ||
3365 | int line; | ||
3366 | struct uart_port *port; | ||
3367 | |||
3368 | for (line = 0; line < nr_uarts; line++) { | ||
3369 | port = &serial8250_ports[line].port; | ||
3370 | if (uart_match_port(p, port)) | ||
3371 | return line; | ||
3372 | } | ||
3373 | return -ENODEV; | ||
3374 | } | ||
3375 | 3536 | ||
3376 | #define SERIAL8250_CONSOLE &serial8250_console | 3537 | #define SERIAL8250_CONSOLE &univ8250_console |
3377 | #else | 3538 | #else |
3378 | #define SERIAL8250_CONSOLE NULL | 3539 | #define SERIAL8250_CONSOLE NULL |
3379 | #endif | 3540 | #endif |
@@ -3412,19 +3573,19 @@ int __init early_serial_setup(struct uart_port *port) | |||
3412 | p->iotype = port->iotype; | 3573 | p->iotype = port->iotype; |
3413 | p->flags = port->flags; | 3574 | p->flags = port->flags; |
3414 | p->mapbase = port->mapbase; | 3575 | p->mapbase = port->mapbase; |
3576 | p->mapsize = port->mapsize; | ||
3415 | p->private_data = port->private_data; | 3577 | p->private_data = port->private_data; |
3416 | p->type = port->type; | 3578 | p->type = port->type; |
3417 | p->line = port->line; | 3579 | p->line = port->line; |
3418 | 3580 | ||
3419 | set_io_from_upio(p); | 3581 | serial8250_set_defaults(up_to_u8250p(p)); |
3582 | |||
3420 | if (port->serial_in) | 3583 | if (port->serial_in) |
3421 | p->serial_in = port->serial_in; | 3584 | p->serial_in = port->serial_in; |
3422 | if (port->serial_out) | 3585 | if (port->serial_out) |
3423 | p->serial_out = port->serial_out; | 3586 | p->serial_out = port->serial_out; |
3424 | if (port->handle_irq) | 3587 | if (port->handle_irq) |
3425 | p->handle_irq = port->handle_irq; | 3588 | p->handle_irq = port->handle_irq; |
3426 | else | ||
3427 | p->handle_irq = serial8250_default_handle_irq; | ||
3428 | 3589 | ||
3429 | return 0; | 3590 | return 0; |
3430 | } | 3591 | } |
@@ -3444,7 +3605,8 @@ void serial8250_suspend_port(int line) | |||
3444 | port->type != PORT_8250) { | 3605 | port->type != PORT_8250) { |
3445 | unsigned char canary = 0xa5; | 3606 | unsigned char canary = 0xa5; |
3446 | serial_out(up, UART_SCR, canary); | 3607 | serial_out(up, UART_SCR, canary); |
3447 | up->canary = canary; | 3608 | if (serial_in(up, UART_SCR) == canary) |
3609 | up->canary = canary; | ||
3448 | } | 3610 | } |
3449 | 3611 | ||
3450 | uart_suspend_port(&serial8250_reg, port); | 3612 | uart_suspend_port(&serial8250_reg, port); |
@@ -3666,6 +3828,7 @@ int serial8250_register_8250_port(struct uart_8250_port *up) | |||
3666 | uart->port.flags = up->port.flags | UPF_BOOT_AUTOCONF; | 3828 | uart->port.flags = up->port.flags | UPF_BOOT_AUTOCONF; |
3667 | uart->bugs = up->bugs; | 3829 | uart->bugs = up->bugs; |
3668 | uart->port.mapbase = up->port.mapbase; | 3830 | uart->port.mapbase = up->port.mapbase; |
3831 | uart->port.mapsize = up->port.mapsize; | ||
3669 | uart->port.private_data = up->port.private_data; | 3832 | uart->port.private_data = up->port.private_data; |
3670 | uart->port.fifosize = up->port.fifosize; | 3833 | uart->port.fifosize = up->port.fifosize; |
3671 | uart->tx_loadsz = up->tx_loadsz; | 3834 | uart->tx_loadsz = up->tx_loadsz; |
@@ -3674,6 +3837,7 @@ int serial8250_register_8250_port(struct uart_8250_port *up) | |||
3674 | uart->port.unthrottle = up->port.unthrottle; | 3837 | uart->port.unthrottle = up->port.unthrottle; |
3675 | uart->port.rs485_config = up->port.rs485_config; | 3838 | uart->port.rs485_config = up->port.rs485_config; |
3676 | uart->port.rs485 = up->port.rs485; | 3839 | uart->port.rs485 = up->port.rs485; |
3840 | uart->dma = up->dma; | ||
3677 | 3841 | ||
3678 | /* Take tx_loadsz from fifosize if it wasn't set separately */ | 3842 | /* Take tx_loadsz from fifosize if it wasn't set separately */ |
3679 | if (uart->port.fifosize && !uart->tx_loadsz) | 3843 | if (uart->port.fifosize && !uart->tx_loadsz) |
@@ -3682,10 +3846,14 @@ int serial8250_register_8250_port(struct uart_8250_port *up) | |||
3682 | if (up->port.dev) | 3846 | if (up->port.dev) |
3683 | uart->port.dev = up->port.dev; | 3847 | uart->port.dev = up->port.dev; |
3684 | 3848 | ||
3849 | if (skip_txen_test) | ||
3850 | uart->port.flags |= UPF_NO_TXEN_TEST; | ||
3851 | |||
3685 | if (up->port.flags & UPF_FIXED_TYPE) | 3852 | if (up->port.flags & UPF_FIXED_TYPE) |
3686 | serial8250_init_fixed_type_port(uart, up->port.type); | 3853 | uart->port.type = up->port.type; |
3854 | |||
3855 | serial8250_set_defaults(uart); | ||
3687 | 3856 | ||
3688 | set_io_from_upio(&uart->port); | ||
3689 | /* Possibly override default I/O functions. */ | 3857 | /* Possibly override default I/O functions. */ |
3690 | if (up->port.serial_in) | 3858 | if (up->port.serial_in) |
3691 | uart->port.serial_in = up->port.serial_in; | 3859 | uart->port.serial_in = up->port.serial_in; |
@@ -3710,13 +3878,6 @@ int serial8250_register_8250_port(struct uart_8250_port *up) | |||
3710 | uart->dl_read = up->dl_read; | 3878 | uart->dl_read = up->dl_read; |
3711 | if (up->dl_write) | 3879 | if (up->dl_write) |
3712 | uart->dl_write = up->dl_write; | 3880 | uart->dl_write = up->dl_write; |
3713 | if (up->dma) { | ||
3714 | uart->dma = up->dma; | ||
3715 | if (!uart->dma->tx_dma) | ||
3716 | uart->dma->tx_dma = serial8250_tx_dma; | ||
3717 | if (!uart->dma->rx_dma) | ||
3718 | uart->dma->rx_dma = serial8250_rx_dma; | ||
3719 | } | ||
3720 | 3881 | ||
3721 | if (serial8250_isa_config != NULL) | 3882 | if (serial8250_isa_config != NULL) |
3722 | serial8250_isa_config(0, &uart->port, | 3883 | serial8250_isa_config(0, &uart->port, |
@@ -3747,9 +3908,11 @@ void serial8250_unregister_port(int line) | |||
3747 | uart_remove_one_port(&serial8250_reg, &uart->port); | 3908 | uart_remove_one_port(&serial8250_reg, &uart->port); |
3748 | if (serial8250_isa_devs) { | 3909 | if (serial8250_isa_devs) { |
3749 | uart->port.flags &= ~UPF_BOOT_AUTOCONF; | 3910 | uart->port.flags &= ~UPF_BOOT_AUTOCONF; |
3911 | if (skip_txen_test) | ||
3912 | uart->port.flags |= UPF_NO_TXEN_TEST; | ||
3750 | uart->port.type = PORT_UNKNOWN; | 3913 | uart->port.type = PORT_UNKNOWN; |
3751 | uart->port.dev = &serial8250_isa_devs->dev; | 3914 | uart->port.dev = &serial8250_isa_devs->dev; |
3752 | uart->capabilities = uart_config[uart->port.type].flags; | 3915 | uart->capabilities = 0; |
3753 | uart_add_one_port(&serial8250_reg, &uart->port); | 3916 | uart_add_one_port(&serial8250_reg, &uart->port); |
3754 | } else { | 3917 | } else { |
3755 | uart->port.dev = NULL; | 3918 | uart->port.dev = NULL; |
diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c index 6ae5b8560e4d..176f18f2e3ab 100644 --- a/drivers/tty/serial/8250/8250_dw.c +++ b/drivers/tty/serial/8250/8250_dw.c | |||
@@ -17,7 +17,6 @@ | |||
17 | #include <linux/io.h> | 17 | #include <linux/io.h> |
18 | #include <linux/module.h> | 18 | #include <linux/module.h> |
19 | #include <linux/serial_8250.h> | 19 | #include <linux/serial_8250.h> |
20 | #include <linux/serial_core.h> | ||
21 | #include <linux/serial_reg.h> | 20 | #include <linux/serial_reg.h> |
22 | #include <linux/of.h> | 21 | #include <linux/of.h> |
23 | #include <linux/of_irq.h> | 22 | #include <linux/of_irq.h> |
@@ -364,9 +363,9 @@ static int dw8250_probe_of(struct uart_port *p, | |||
364 | } | 363 | } |
365 | 364 | ||
366 | if (of_property_read_bool(np, "cts-override")) { | 365 | if (of_property_read_bool(np, "cts-override")) { |
367 | /* Always report DSR as active */ | 366 | /* Always report CTS as active */ |
368 | data->msr_mask_on |= UART_MSR_DSR; | 367 | data->msr_mask_on |= UART_MSR_CTS; |
369 | data->msr_mask_off |= UART_MSR_DDSR; | 368 | data->msr_mask_off |= UART_MSR_DCTS; |
370 | } | 369 | } |
371 | 370 | ||
372 | if (of_property_read_bool(np, "ri-override")) { | 371 | if (of_property_read_bool(np, "ri-override")) { |
@@ -375,37 +374,16 @@ static int dw8250_probe_of(struct uart_port *p, | |||
375 | data->msr_mask_off |= UART_MSR_TERI; | 374 | data->msr_mask_off |= UART_MSR_TERI; |
376 | } | 375 | } |
377 | 376 | ||
378 | /* clock got configured through clk api, all done */ | ||
379 | if (p->uartclk) | ||
380 | return 0; | ||
381 | |||
382 | /* try to find out clock frequency from DT as fallback */ | ||
383 | if (of_property_read_u32(np, "clock-frequency", &val)) { | ||
384 | dev_err(p->dev, "clk or clock-frequency not defined\n"); | ||
385 | return -EINVAL; | ||
386 | } | ||
387 | p->uartclk = val; | ||
388 | |||
389 | return 0; | 377 | return 0; |
390 | } | 378 | } |
391 | 379 | ||
392 | static int dw8250_probe_acpi(struct uart_8250_port *up, | 380 | static int dw8250_probe_acpi(struct uart_8250_port *up, |
393 | struct dw8250_data *data) | 381 | struct dw8250_data *data) |
394 | { | 382 | { |
395 | const struct acpi_device_id *id; | ||
396 | struct uart_port *p = &up->port; | 383 | struct uart_port *p = &up->port; |
397 | 384 | ||
398 | dw8250_setup_port(up); | 385 | dw8250_setup_port(up); |
399 | 386 | ||
400 | id = acpi_match_device(p->dev->driver->acpi_match_table, p->dev); | ||
401 | if (!id) | ||
402 | return -ENODEV; | ||
403 | |||
404 | if (!p->uartclk) | ||
405 | if (device_property_read_u32(p->dev, "clock-frequency", | ||
406 | &p->uartclk)) | ||
407 | return -EINVAL; | ||
408 | |||
409 | p->iotype = UPIO_MEM32; | 387 | p->iotype = UPIO_MEM32; |
410 | p->serial_in = dw8250_serial_in32; | 388 | p->serial_in = dw8250_serial_in32; |
411 | p->serial_out = dw8250_serial_out32; | 389 | p->serial_out = dw8250_serial_out32; |
@@ -425,18 +403,24 @@ static int dw8250_probe(struct platform_device *pdev) | |||
425 | { | 403 | { |
426 | struct uart_8250_port uart = {}; | 404 | struct uart_8250_port uart = {}; |
427 | struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 405 | struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
428 | struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | 406 | int irq = platform_get_irq(pdev, 0); |
429 | struct dw8250_data *data; | 407 | struct dw8250_data *data; |
430 | int err; | 408 | int err; |
431 | 409 | ||
432 | if (!regs || !irq) { | 410 | if (!regs) { |
433 | dev_err(&pdev->dev, "no registers/irq defined\n"); | 411 | dev_err(&pdev->dev, "no registers defined\n"); |
434 | return -EINVAL; | 412 | return -EINVAL; |
435 | } | 413 | } |
436 | 414 | ||
415 | if (irq < 0) { | ||
416 | if (irq != -EPROBE_DEFER) | ||
417 | dev_err(&pdev->dev, "cannot get irq\n"); | ||
418 | return irq; | ||
419 | } | ||
420 | |||
437 | spin_lock_init(&uart.port.lock); | 421 | spin_lock_init(&uart.port.lock); |
438 | uart.port.mapbase = regs->start; | 422 | uart.port.mapbase = regs->start; |
439 | uart.port.irq = irq->start; | 423 | uart.port.irq = irq; |
440 | uart.port.handle_irq = dw8250_handle_irq; | 424 | uart.port.handle_irq = dw8250_handle_irq; |
441 | uart.port.pm = dw8250_do_pm; | 425 | uart.port.pm = dw8250_do_pm; |
442 | uart.port.type = PORT_8250; | 426 | uart.port.type = PORT_8250; |
@@ -453,12 +437,18 @@ static int dw8250_probe(struct platform_device *pdev) | |||
453 | return -ENOMEM; | 437 | return -ENOMEM; |
454 | 438 | ||
455 | data->usr_reg = DW_UART_USR; | 439 | data->usr_reg = DW_UART_USR; |
440 | |||
441 | /* Always ask for fixed clock rate from a property. */ | ||
442 | device_property_read_u32(&pdev->dev, "clock-frequency", | ||
443 | &uart.port.uartclk); | ||
444 | |||
445 | /* If there is separate baudclk, get the rate from it. */ | ||
456 | data->clk = devm_clk_get(&pdev->dev, "baudclk"); | 446 | data->clk = devm_clk_get(&pdev->dev, "baudclk"); |
457 | if (IS_ERR(data->clk) && PTR_ERR(data->clk) != -EPROBE_DEFER) | 447 | if (IS_ERR(data->clk) && PTR_ERR(data->clk) != -EPROBE_DEFER) |
458 | data->clk = devm_clk_get(&pdev->dev, NULL); | 448 | data->clk = devm_clk_get(&pdev->dev, NULL); |
459 | if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER) | 449 | if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER) |
460 | return -EPROBE_DEFER; | 450 | return -EPROBE_DEFER; |
461 | if (!IS_ERR(data->clk)) { | 451 | if (!IS_ERR_OR_NULL(data->clk)) { |
462 | err = clk_prepare_enable(data->clk); | 452 | err = clk_prepare_enable(data->clk); |
463 | if (err) | 453 | if (err) |
464 | dev_warn(&pdev->dev, "could not enable optional baudclk: %d\n", | 454 | dev_warn(&pdev->dev, "could not enable optional baudclk: %d\n", |
@@ -467,6 +457,12 @@ static int dw8250_probe(struct platform_device *pdev) | |||
467 | uart.port.uartclk = clk_get_rate(data->clk); | 457 | uart.port.uartclk = clk_get_rate(data->clk); |
468 | } | 458 | } |
469 | 459 | ||
460 | /* If no clock rate is defined, fail. */ | ||
461 | if (!uart.port.uartclk) { | ||
462 | dev_err(&pdev->dev, "clock rate not defined\n"); | ||
463 | return -EINVAL; | ||
464 | } | ||
465 | |||
470 | data->pclk = devm_clk_get(&pdev->dev, "apb_pclk"); | 466 | data->pclk = devm_clk_get(&pdev->dev, "apb_pclk"); |
471 | if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER) { | 467 | if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER) { |
472 | err = -EPROBE_DEFER; | 468 | err = -EPROBE_DEFER; |
@@ -629,6 +625,7 @@ static const struct acpi_device_id dw8250_acpi_match[] = { | |||
629 | { "80860F0A", 0 }, | 625 | { "80860F0A", 0 }, |
630 | { "8086228A", 0 }, | 626 | { "8086228A", 0 }, |
631 | { "APMC0D08", 0}, | 627 | { "APMC0D08", 0}, |
628 | { "AMD0020", 0 }, | ||
632 | { }, | 629 | { }, |
633 | }; | 630 | }; |
634 | MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match); | 631 | MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match); |
@@ -649,3 +646,4 @@ module_platform_driver(dw8250_platform_driver); | |||
649 | MODULE_AUTHOR("Jamie Iles"); | 646 | MODULE_AUTHOR("Jamie Iles"); |
650 | MODULE_LICENSE("GPL"); | 647 | MODULE_LICENSE("GPL"); |
651 | MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver"); | 648 | MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver"); |
649 | MODULE_ALIAS("platform:dw-apb-uart"); | ||
diff --git a/drivers/tty/serial/8250/8250_early.c b/drivers/tty/serial/8250/8250_early.c index c31a22b4f845..8e119682266a 100644 --- a/drivers/tty/serial/8250/8250_early.c +++ b/drivers/tty/serial/8250/8250_early.c | |||
@@ -29,15 +29,12 @@ | |||
29 | #include <linux/tty.h> | 29 | #include <linux/tty.h> |
30 | #include <linux/init.h> | 30 | #include <linux/init.h> |
31 | #include <linux/console.h> | 31 | #include <linux/console.h> |
32 | #include <linux/serial_core.h> | ||
33 | #include <linux/serial_reg.h> | 32 | #include <linux/serial_reg.h> |
34 | #include <linux/serial.h> | 33 | #include <linux/serial.h> |
35 | #include <linux/serial_8250.h> | 34 | #include <linux/serial_8250.h> |
36 | #include <asm/io.h> | 35 | #include <asm/io.h> |
37 | #include <asm/serial.h> | 36 | #include <asm/serial.h> |
38 | 37 | ||
39 | static struct earlycon_device *early_device; | ||
40 | |||
41 | unsigned int __weak __init serial8250_early_in(struct uart_port *port, int offset) | 38 | unsigned int __weak __init serial8250_early_in(struct uart_port *port, int offset) |
42 | { | 39 | { |
43 | switch (port->iotype) { | 40 | switch (port->iotype) { |
@@ -90,7 +87,8 @@ static void __init serial_putc(struct uart_port *port, int c) | |||
90 | static void __init early_serial8250_write(struct console *console, | 87 | static void __init early_serial8250_write(struct console *console, |
91 | const char *s, unsigned int count) | 88 | const char *s, unsigned int count) |
92 | { | 89 | { |
93 | struct uart_port *port = &early_device->port; | 90 | struct earlycon_device *device = console->data; |
91 | struct uart_port *port = &device->port; | ||
94 | unsigned int ier; | 92 | unsigned int ier; |
95 | 93 | ||
96 | /* Save the IER and disable interrupts preserving the UUE bit */ | 94 | /* Save the IER and disable interrupts preserving the UUE bit */ |
@@ -107,21 +105,6 @@ static void __init early_serial8250_write(struct console *console, | |||
107 | serial8250_early_out(port, UART_IER, ier); | 105 | serial8250_early_out(port, UART_IER, ier); |
108 | } | 106 | } |
109 | 107 | ||
110 | static unsigned int __init probe_baud(struct uart_port *port) | ||
111 | { | ||
112 | unsigned char lcr, dll, dlm; | ||
113 | unsigned int quot; | ||
114 | |||
115 | lcr = serial8250_early_in(port, UART_LCR); | ||
116 | serial8250_early_out(port, UART_LCR, lcr | UART_LCR_DLAB); | ||
117 | dll = serial8250_early_in(port, UART_DLL); | ||
118 | dlm = serial8250_early_in(port, UART_DLM); | ||
119 | serial8250_early_out(port, UART_LCR, lcr); | ||
120 | |||
121 | quot = (dlm << 8) | dll; | ||
122 | return (port->uartclk / 16) / quot; | ||
123 | } | ||
124 | |||
125 | static void __init init_port(struct earlycon_device *device) | 108 | static void __init init_port(struct earlycon_device *device) |
126 | { | 109 | { |
127 | struct uart_port *port = &device->port; | 110 | struct uart_port *port = &device->port; |
@@ -147,52 +130,20 @@ static int __init early_serial8250_setup(struct earlycon_device *device, | |||
147 | const char *options) | 130 | const char *options) |
148 | { | 131 | { |
149 | if (!(device->port.membase || device->port.iobase)) | 132 | if (!(device->port.membase || device->port.iobase)) |
150 | return 0; | 133 | return -ENODEV; |
151 | 134 | ||
152 | if (!device->baud) { | 135 | if (!device->baud) { |
153 | device->baud = probe_baud(&device->port); | 136 | struct uart_port *port = &device->port; |
154 | snprintf(device->options, sizeof(device->options), "%u", | 137 | unsigned int ier; |
155 | device->baud); | ||
156 | } | ||
157 | 138 | ||
158 | init_port(device); | 139 | /* assume the device was initialized, only mask interrupts */ |
140 | ier = serial8250_early_in(port, UART_IER); | ||
141 | serial8250_early_out(port, UART_IER, ier & UART_IER_UUE); | ||
142 | } else | ||
143 | init_port(device); | ||
159 | 144 | ||
160 | early_device = device; | ||
161 | device->con->write = early_serial8250_write; | 145 | device->con->write = early_serial8250_write; |
162 | return 0; | 146 | return 0; |
163 | } | 147 | } |
164 | EARLYCON_DECLARE(uart8250, early_serial8250_setup); | 148 | EARLYCON_DECLARE(uart8250, early_serial8250_setup); |
165 | EARLYCON_DECLARE(uart, early_serial8250_setup); | 149 | EARLYCON_DECLARE(uart, early_serial8250_setup); |
166 | |||
167 | int __init setup_early_serial8250_console(char *cmdline) | ||
168 | { | ||
169 | char match[] = "uart8250"; | ||
170 | |||
171 | if (cmdline && cmdline[4] == ',') | ||
172 | match[4] = '\0'; | ||
173 | |||
174 | return setup_earlycon(cmdline, match, early_serial8250_setup); | ||
175 | } | ||
176 | |||
177 | int serial8250_find_port_for_earlycon(void) | ||
178 | { | ||
179 | struct earlycon_device *device = early_device; | ||
180 | struct uart_port *port = device ? &device->port : NULL; | ||
181 | int line; | ||
182 | int ret; | ||
183 | |||
184 | if (!port || (!port->membase && !port->iobase)) | ||
185 | return -ENODEV; | ||
186 | |||
187 | line = serial8250_find_port(port); | ||
188 | if (line < 0) | ||
189 | return -ENODEV; | ||
190 | |||
191 | ret = update_console_cmdline("uart", 8250, | ||
192 | "ttyS", line, device->options); | ||
193 | if (ret < 0) | ||
194 | ret = update_console_cmdline("uart", 0, | ||
195 | "ttyS", line, device->options); | ||
196 | |||
197 | return ret; | ||
198 | } | ||
diff --git a/drivers/tty/serial/8250/8250_em.c b/drivers/tty/serial/8250/8250_em.c index ae5eaed6aa85..0b6381214917 100644 --- a/drivers/tty/serial/8250/8250_em.c +++ b/drivers/tty/serial/8250/8250_em.c | |||
@@ -21,7 +21,6 @@ | |||
21 | #include <linux/io.h> | 21 | #include <linux/io.h> |
22 | #include <linux/module.h> | 22 | #include <linux/module.h> |
23 | #include <linux/serial_8250.h> | 23 | #include <linux/serial_8250.h> |
24 | #include <linux/serial_core.h> | ||
25 | #include <linux/serial_reg.h> | 24 | #include <linux/serial_reg.h> |
26 | #include <linux/platform_device.h> | 25 | #include <linux/platform_device.h> |
27 | #include <linux/clk.h> | 26 | #include <linux/clk.h> |
diff --git a/drivers/tty/serial/8250/8250_hp300.c b/drivers/tty/serial/8250/8250_hp300.c index b4882082b247..2891958cd842 100644 --- a/drivers/tty/serial/8250/8250_hp300.c +++ b/drivers/tty/serial/8250/8250_hp300.c | |||
@@ -10,7 +10,6 @@ | |||
10 | #include <linux/string.h> | 10 | #include <linux/string.h> |
11 | #include <linux/kernel.h> | 11 | #include <linux/kernel.h> |
12 | #include <linux/serial.h> | 12 | #include <linux/serial.h> |
13 | #include <linux/serial_core.h> | ||
14 | #include <linux/serial_8250.h> | 13 | #include <linux/serial_8250.h> |
15 | #include <linux/delay.h> | 14 | #include <linux/delay.h> |
16 | #include <linux/dio.h> | 15 | #include <linux/dio.h> |
diff --git a/drivers/tty/serial/8250/8250_omap.c b/drivers/tty/serial/8250/8250_omap.c index fe6d2e51da09..9289999cb7c6 100644 --- a/drivers/tty/serial/8250/8250_omap.c +++ b/drivers/tty/serial/8250/8250_omap.c | |||
@@ -11,7 +11,6 @@ | |||
11 | #include <linux/io.h> | 11 | #include <linux/io.h> |
12 | #include <linux/module.h> | 12 | #include <linux/module.h> |
13 | #include <linux/serial_8250.h> | 13 | #include <linux/serial_8250.h> |
14 | #include <linux/serial_core.h> | ||
15 | #include <linux/serial_reg.h> | 14 | #include <linux/serial_reg.h> |
16 | #include <linux/tty_flip.h> | 15 | #include <linux/tty_flip.h> |
17 | #include <linux/platform_device.h> | 16 | #include <linux/platform_device.h> |
diff --git a/drivers/tty/serial/8250/8250_pci.c b/drivers/tty/serial/8250/8250_pci.c index 892eb32cdef4..08da4d3e2162 100644 --- a/drivers/tty/serial/8250/8250_pci.c +++ b/drivers/tty/serial/8250/8250_pci.c | |||
@@ -21,12 +21,14 @@ | |||
21 | #include <linux/serial_core.h> | 21 | #include <linux/serial_core.h> |
22 | #include <linux/8250_pci.h> | 22 | #include <linux/8250_pci.h> |
23 | #include <linux/bitops.h> | 23 | #include <linux/bitops.h> |
24 | #include <linux/rational.h> | ||
24 | 25 | ||
25 | #include <asm/byteorder.h> | 26 | #include <asm/byteorder.h> |
26 | #include <asm/io.h> | 27 | #include <asm/io.h> |
27 | 28 | ||
28 | #include <linux/dmaengine.h> | 29 | #include <linux/dmaengine.h> |
29 | #include <linux/platform_data/dma-dw.h> | 30 | #include <linux/platform_data/dma-dw.h> |
31 | #include <linux/platform_data/dma-hsu.h> | ||
30 | 32 | ||
31 | #include "8250.h" | 33 | #include "8250.h" |
32 | 34 | ||
@@ -1392,45 +1394,22 @@ byt_set_termios(struct uart_port *p, struct ktermios *termios, | |||
1392 | struct ktermios *old) | 1394 | struct ktermios *old) |
1393 | { | 1395 | { |
1394 | unsigned int baud = tty_termios_baud_rate(termios); | 1396 | unsigned int baud = tty_termios_baud_rate(termios); |
1395 | unsigned int m, n; | 1397 | unsigned long fref = 100000000, fuart = baud * 16; |
1398 | unsigned long w = BIT(15) - 1; | ||
1399 | unsigned long m, n; | ||
1396 | u32 reg; | 1400 | u32 reg; |
1397 | 1401 | ||
1402 | /* Get Fuart closer to Fref */ | ||
1403 | fuart *= rounddown_pow_of_two(fref / fuart); | ||
1404 | |||
1398 | /* | 1405 | /* |
1399 | * For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the | 1406 | * For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the |
1400 | * dividers must be adjusted. | 1407 | * dividers must be adjusted. |
1401 | * | 1408 | * |
1402 | * uartclk = (m / n) * 100 MHz, where m <= n | 1409 | * uartclk = (m / n) * 100 MHz, where m <= n |
1403 | */ | 1410 | */ |
1404 | switch (baud) { | 1411 | rational_best_approximation(fuart, fref, w, w, &m, &n); |
1405 | case 500000: | 1412 | p->uartclk = fuart; |
1406 | case 1000000: | ||
1407 | case 2000000: | ||
1408 | case 4000000: | ||
1409 | m = 64; | ||
1410 | n = 100; | ||
1411 | p->uartclk = 64000000; | ||
1412 | break; | ||
1413 | case 3500000: | ||
1414 | m = 56; | ||
1415 | n = 100; | ||
1416 | p->uartclk = 56000000; | ||
1417 | break; | ||
1418 | case 1500000: | ||
1419 | case 3000000: | ||
1420 | m = 48; | ||
1421 | n = 100; | ||
1422 | p->uartclk = 48000000; | ||
1423 | break; | ||
1424 | case 2500000: | ||
1425 | m = 40; | ||
1426 | n = 100; | ||
1427 | p->uartclk = 40000000; | ||
1428 | break; | ||
1429 | default: | ||
1430 | m = 2304; | ||
1431 | n = 3125; | ||
1432 | p->uartclk = 73728000; | ||
1433 | } | ||
1434 | 1413 | ||
1435 | /* Reset the clock */ | 1414 | /* Reset the clock */ |
1436 | reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT); | 1415 | reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT); |
@@ -1525,6 +1504,167 @@ byt_serial_setup(struct serial_private *priv, | |||
1525 | return ret; | 1504 | return ret; |
1526 | } | 1505 | } |
1527 | 1506 | ||
1507 | #define INTEL_MID_UART_PS 0x30 | ||
1508 | #define INTEL_MID_UART_MUL 0x34 | ||
1509 | #define INTEL_MID_UART_DIV 0x38 | ||
1510 | |||
1511 | static void intel_mid_set_termios(struct uart_port *p, | ||
1512 | struct ktermios *termios, | ||
1513 | struct ktermios *old, | ||
1514 | unsigned long fref) | ||
1515 | { | ||
1516 | unsigned int baud = tty_termios_baud_rate(termios); | ||
1517 | unsigned short ps = 16; | ||
1518 | unsigned long fuart = baud * ps; | ||
1519 | unsigned long w = BIT(24) - 1; | ||
1520 | unsigned long mul, div; | ||
1521 | |||
1522 | if (fref < fuart) { | ||
1523 | /* Find prescaler value that satisfies Fuart < Fref */ | ||
1524 | if (fref > baud) | ||
1525 | ps = fref / baud; /* baud rate too high */ | ||
1526 | else | ||
1527 | ps = 1; /* PLL case */ | ||
1528 | fuart = baud * ps; | ||
1529 | } else { | ||
1530 | /* Get Fuart closer to Fref */ | ||
1531 | fuart *= rounddown_pow_of_two(fref / fuart); | ||
1532 | } | ||
1533 | |||
1534 | rational_best_approximation(fuart, fref, w, w, &mul, &div); | ||
1535 | p->uartclk = fuart * 16 / ps; /* core uses ps = 16 always */ | ||
1536 | |||
1537 | writel(ps, p->membase + INTEL_MID_UART_PS); /* set PS */ | ||
1538 | writel(mul, p->membase + INTEL_MID_UART_MUL); /* set MUL */ | ||
1539 | writel(div, p->membase + INTEL_MID_UART_DIV); | ||
1540 | |||
1541 | serial8250_do_set_termios(p, termios, old); | ||
1542 | } | ||
1543 | |||
1544 | static void intel_mid_set_termios_38_4M(struct uart_port *p, | ||
1545 | struct ktermios *termios, | ||
1546 | struct ktermios *old) | ||
1547 | { | ||
1548 | intel_mid_set_termios(p, termios, old, 38400000); | ||
1549 | } | ||
1550 | |||
1551 | static void intel_mid_set_termios_50M(struct uart_port *p, | ||
1552 | struct ktermios *termios, | ||
1553 | struct ktermios *old) | ||
1554 | { | ||
1555 | /* | ||
1556 | * The uart clk is 50Mhz, and the baud rate come from: | ||
1557 | * baud = 50M * MUL / (DIV * PS * DLAB) | ||
1558 | */ | ||
1559 | intel_mid_set_termios(p, termios, old, 50000000); | ||
1560 | } | ||
1561 | |||
1562 | static bool intel_mid_dma_filter(struct dma_chan *chan, void *param) | ||
1563 | { | ||
1564 | struct hsu_dma_slave *s = param; | ||
1565 | |||
1566 | if (s->dma_dev != chan->device->dev || s->chan_id != chan->chan_id) | ||
1567 | return false; | ||
1568 | |||
1569 | chan->private = s; | ||
1570 | return true; | ||
1571 | } | ||
1572 | |||
1573 | static int intel_mid_serial_setup(struct serial_private *priv, | ||
1574 | const struct pciserial_board *board, | ||
1575 | struct uart_8250_port *port, int idx, | ||
1576 | int index, struct pci_dev *dma_dev) | ||
1577 | { | ||
1578 | struct device *dev = port->port.dev; | ||
1579 | struct uart_8250_dma *dma; | ||
1580 | struct hsu_dma_slave *tx_param, *rx_param; | ||
1581 | |||
1582 | dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL); | ||
1583 | if (!dma) | ||
1584 | return -ENOMEM; | ||
1585 | |||
1586 | tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL); | ||
1587 | if (!tx_param) | ||
1588 | return -ENOMEM; | ||
1589 | |||
1590 | rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL); | ||
1591 | if (!rx_param) | ||
1592 | return -ENOMEM; | ||
1593 | |||
1594 | rx_param->chan_id = index * 2 + 1; | ||
1595 | tx_param->chan_id = index * 2; | ||
1596 | |||
1597 | dma->rxconf.src_maxburst = 64; | ||
1598 | dma->txconf.dst_maxburst = 64; | ||
1599 | |||
1600 | rx_param->dma_dev = &dma_dev->dev; | ||
1601 | tx_param->dma_dev = &dma_dev->dev; | ||
1602 | |||
1603 | dma->fn = intel_mid_dma_filter; | ||
1604 | dma->rx_param = rx_param; | ||
1605 | dma->tx_param = tx_param; | ||
1606 | |||
1607 | port->port.type = PORT_16750; | ||
1608 | port->port.flags |= UPF_FIXED_PORT | UPF_FIXED_TYPE; | ||
1609 | port->dma = dma; | ||
1610 | |||
1611 | return pci_default_setup(priv, board, port, idx); | ||
1612 | } | ||
1613 | |||
1614 | #define PCI_DEVICE_ID_INTEL_PNW_UART1 0x081b | ||
1615 | #define PCI_DEVICE_ID_INTEL_PNW_UART2 0x081c | ||
1616 | #define PCI_DEVICE_ID_INTEL_PNW_UART3 0x081d | ||
1617 | |||
1618 | static int pnw_serial_setup(struct serial_private *priv, | ||
1619 | const struct pciserial_board *board, | ||
1620 | struct uart_8250_port *port, int idx) | ||
1621 | { | ||
1622 | struct pci_dev *pdev = priv->dev; | ||
1623 | struct pci_dev *dma_dev; | ||
1624 | int index; | ||
1625 | |||
1626 | switch (pdev->device) { | ||
1627 | case PCI_DEVICE_ID_INTEL_PNW_UART1: | ||
1628 | index = 0; | ||
1629 | break; | ||
1630 | case PCI_DEVICE_ID_INTEL_PNW_UART2: | ||
1631 | index = 1; | ||
1632 | break; | ||
1633 | case PCI_DEVICE_ID_INTEL_PNW_UART3: | ||
1634 | index = 2; | ||
1635 | break; | ||
1636 | default: | ||
1637 | return -EINVAL; | ||
1638 | } | ||
1639 | |||
1640 | dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 3)); | ||
1641 | |||
1642 | port->port.set_termios = intel_mid_set_termios_50M; | ||
1643 | |||
1644 | return intel_mid_serial_setup(priv, board, port, idx, index, dma_dev); | ||
1645 | } | ||
1646 | |||
1647 | #define PCI_DEVICE_ID_INTEL_TNG_UART 0x1191 | ||
1648 | |||
1649 | static int tng_serial_setup(struct serial_private *priv, | ||
1650 | const struct pciserial_board *board, | ||
1651 | struct uart_8250_port *port, int idx) | ||
1652 | { | ||
1653 | struct pci_dev *pdev = priv->dev; | ||
1654 | struct pci_dev *dma_dev; | ||
1655 | int index = PCI_FUNC(pdev->devfn); | ||
1656 | |||
1657 | /* Currently no support for HSU port0 */ | ||
1658 | if (index-- == 0) | ||
1659 | return -ENODEV; | ||
1660 | |||
1661 | dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(5, 0)); | ||
1662 | |||
1663 | port->port.set_termios = intel_mid_set_termios_38_4M; | ||
1664 | |||
1665 | return intel_mid_serial_setup(priv, board, port, idx, index, dma_dev); | ||
1666 | } | ||
1667 | |||
1528 | static int | 1668 | static int |
1529 | pci_omegapci_setup(struct serial_private *priv, | 1669 | pci_omegapci_setup(struct serial_private *priv, |
1530 | const struct pciserial_board *board, | 1670 | const struct pciserial_board *board, |
@@ -1550,95 +1690,71 @@ static int pci_fintek_setup(struct serial_private *priv, | |||
1550 | struct uart_8250_port *port, int idx) | 1690 | struct uart_8250_port *port, int idx) |
1551 | { | 1691 | { |
1552 | struct pci_dev *pdev = priv->dev; | 1692 | struct pci_dev *pdev = priv->dev; |
1553 | unsigned long base; | ||
1554 | unsigned long iobase; | ||
1555 | unsigned long ciobase = 0; | ||
1556 | u8 config_base; | 1693 | u8 config_base; |
1694 | u16 iobase; | ||
1695 | |||
1696 | config_base = 0x40 + 0x08 * idx; | ||
1697 | |||
1698 | /* Get the io address from configuration space */ | ||
1699 | pci_read_config_word(pdev, config_base + 4, &iobase); | ||
1700 | |||
1701 | dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase); | ||
1702 | |||
1703 | port->port.iotype = UPIO_PORT; | ||
1704 | port->port.iobase = iobase; | ||
1705 | |||
1706 | return 0; | ||
1707 | } | ||
1708 | |||
1709 | static int pci_fintek_init(struct pci_dev *dev) | ||
1710 | { | ||
1711 | unsigned long iobase; | ||
1712 | u32 max_port, i; | ||
1557 | u32 bar_data[3]; | 1713 | u32 bar_data[3]; |
1714 | u8 config_base; | ||
1558 | 1715 | ||
1559 | /* | 1716 | switch (dev->device) { |
1560 | * Find each UARTs offset in PCI configuraion space | 1717 | case 0x1104: /* 4 ports */ |
1561 | */ | 1718 | case 0x1108: /* 8 ports */ |
1562 | switch (idx) { | 1719 | max_port = dev->device & 0xff; |
1563 | case 0: | ||
1564 | config_base = 0x40; | ||
1565 | break; | 1720 | break; |
1566 | case 1: | 1721 | case 0x1112: /* 12 ports */ |
1567 | config_base = 0x48; | 1722 | max_port = 12; |
1568 | break; | ||
1569 | case 2: | ||
1570 | config_base = 0x50; | ||
1571 | break; | ||
1572 | case 3: | ||
1573 | config_base = 0x58; | ||
1574 | break; | ||
1575 | case 4: | ||
1576 | config_base = 0x60; | ||
1577 | break; | ||
1578 | case 5: | ||
1579 | config_base = 0x68; | ||
1580 | break; | ||
1581 | case 6: | ||
1582 | config_base = 0x70; | ||
1583 | break; | ||
1584 | case 7: | ||
1585 | config_base = 0x78; | ||
1586 | break; | ||
1587 | case 8: | ||
1588 | config_base = 0x80; | ||
1589 | break; | ||
1590 | case 9: | ||
1591 | config_base = 0x88; | ||
1592 | break; | ||
1593 | case 10: | ||
1594 | config_base = 0x90; | ||
1595 | break; | ||
1596 | case 11: | ||
1597 | config_base = 0x98; | ||
1598 | break; | 1723 | break; |
1599 | default: | 1724 | default: |
1600 | /* Unknown number of ports, get out of here */ | ||
1601 | return -EINVAL; | 1725 | return -EINVAL; |
1602 | } | 1726 | } |
1603 | 1727 | ||
1604 | if (idx < 4) { | ||
1605 | base = pci_resource_start(priv->dev, 3); | ||
1606 | ciobase = (int)(base + (0x8 * idx)); | ||
1607 | } | ||
1608 | |||
1609 | /* Get the io address dispatch from the BIOS */ | 1728 | /* Get the io address dispatch from the BIOS */ |
1610 | pci_read_config_dword(pdev, 0x24, &bar_data[0]); | 1729 | pci_read_config_dword(dev, 0x24, &bar_data[0]); |
1611 | pci_read_config_dword(pdev, 0x20, &bar_data[1]); | 1730 | pci_read_config_dword(dev, 0x20, &bar_data[1]); |
1612 | pci_read_config_dword(pdev, 0x1c, &bar_data[2]); | 1731 | pci_read_config_dword(dev, 0x1c, &bar_data[2]); |
1613 | |||
1614 | /* Calculate Real IO Port */ | ||
1615 | iobase = (bar_data[idx/4] & 0xffffffe0) + (idx % 4) * 8; | ||
1616 | 1732 | ||
1617 | dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%lx ciobase=0x%lx config_base=0x%2x\n", | 1733 | for (i = 0; i < max_port; ++i) { |
1618 | __func__, idx, iobase, ciobase, config_base); | 1734 | /* UART0 configuration offset start from 0x40 */ |
1735 | config_base = 0x40 + 0x08 * i; | ||
1619 | 1736 | ||
1620 | /* Enable UART I/O port */ | 1737 | /* Calculate Real IO Port */ |
1621 | pci_write_config_byte(pdev, config_base + 0x00, 0x01); | 1738 | iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8; |
1622 | 1739 | ||
1623 | /* Select 128-byte FIFO and 8x FIFO threshold */ | 1740 | /* Enable UART I/O port */ |
1624 | pci_write_config_byte(pdev, config_base + 0x01, 0x33); | 1741 | pci_write_config_byte(dev, config_base + 0x00, 0x01); |
1625 | 1742 | ||
1626 | /* LSB UART */ | 1743 | /* Select 128-byte FIFO and 8x FIFO threshold */ |
1627 | pci_write_config_byte(pdev, config_base + 0x04, (u8)(iobase & 0xff)); | 1744 | pci_write_config_byte(dev, config_base + 0x01, 0x33); |
1628 | 1745 | ||
1629 | /* MSB UART */ | 1746 | /* LSB UART */ |
1630 | pci_write_config_byte(pdev, config_base + 0x05, (u8)((iobase & 0xff00) >> 8)); | 1747 | pci_write_config_byte(dev, config_base + 0x04, |
1748 | (u8)(iobase & 0xff)); | ||
1631 | 1749 | ||
1632 | /* irq number, this usually fails, but the spec says to do it anyway. */ | 1750 | /* MSB UART */ |
1633 | pci_write_config_byte(pdev, config_base + 0x06, pdev->irq); | 1751 | pci_write_config_byte(dev, config_base + 0x05, |
1752 | (u8)((iobase & 0xff00) >> 8)); | ||
1634 | 1753 | ||
1635 | port->port.iotype = UPIO_PORT; | 1754 | pci_write_config_byte(dev, config_base + 0x06, dev->irq); |
1636 | port->port.iobase = iobase; | 1755 | } |
1637 | port->port.mapbase = 0; | ||
1638 | port->port.membase = NULL; | ||
1639 | port->port.regshift = 0; | ||
1640 | 1756 | ||
1641 | return 0; | 1757 | return max_port; |
1642 | } | 1758 | } |
1643 | 1759 | ||
1644 | static int skip_tx_en_setup(struct serial_private *priv, | 1760 | static int skip_tx_en_setup(struct serial_private *priv, |
@@ -1989,6 +2105,34 @@ static struct pci_serial_quirk pci_serial_quirks[] __refdata = { | |||
1989 | }, | 2105 | }, |
1990 | { | 2106 | { |
1991 | .vendor = PCI_VENDOR_ID_INTEL, | 2107 | .vendor = PCI_VENDOR_ID_INTEL, |
2108 | .device = PCI_DEVICE_ID_INTEL_PNW_UART1, | ||
2109 | .subvendor = PCI_ANY_ID, | ||
2110 | .subdevice = PCI_ANY_ID, | ||
2111 | .setup = pnw_serial_setup, | ||
2112 | }, | ||
2113 | { | ||
2114 | .vendor = PCI_VENDOR_ID_INTEL, | ||
2115 | .device = PCI_DEVICE_ID_INTEL_PNW_UART2, | ||
2116 | .subvendor = PCI_ANY_ID, | ||
2117 | .subdevice = PCI_ANY_ID, | ||
2118 | .setup = pnw_serial_setup, | ||
2119 | }, | ||
2120 | { | ||
2121 | .vendor = PCI_VENDOR_ID_INTEL, | ||
2122 | .device = PCI_DEVICE_ID_INTEL_PNW_UART3, | ||
2123 | .subvendor = PCI_ANY_ID, | ||
2124 | .subdevice = PCI_ANY_ID, | ||
2125 | .setup = pnw_serial_setup, | ||
2126 | }, | ||
2127 | { | ||
2128 | .vendor = PCI_VENDOR_ID_INTEL, | ||
2129 | .device = PCI_DEVICE_ID_INTEL_TNG_UART, | ||
2130 | .subvendor = PCI_ANY_ID, | ||
2131 | .subdevice = PCI_ANY_ID, | ||
2132 | .setup = tng_serial_setup, | ||
2133 | }, | ||
2134 | { | ||
2135 | .vendor = PCI_VENDOR_ID_INTEL, | ||
1992 | .device = PCI_DEVICE_ID_INTEL_BSW_UART1, | 2136 | .device = PCI_DEVICE_ID_INTEL_BSW_UART1, |
1993 | .subvendor = PCI_ANY_ID, | 2137 | .subvendor = PCI_ANY_ID, |
1994 | .subdevice = PCI_ANY_ID, | 2138 | .subdevice = PCI_ANY_ID, |
@@ -2653,6 +2797,7 @@ static struct pci_serial_quirk pci_serial_quirks[] __refdata = { | |||
2653 | .subvendor = PCI_ANY_ID, | 2797 | .subvendor = PCI_ANY_ID, |
2654 | .subdevice = PCI_ANY_ID, | 2798 | .subdevice = PCI_ANY_ID, |
2655 | .setup = pci_fintek_setup, | 2799 | .setup = pci_fintek_setup, |
2800 | .init = pci_fintek_init, | ||
2656 | }, | 2801 | }, |
2657 | { | 2802 | { |
2658 | .vendor = 0x1c29, | 2803 | .vendor = 0x1c29, |
@@ -2660,6 +2805,7 @@ static struct pci_serial_quirk pci_serial_quirks[] __refdata = { | |||
2660 | .subvendor = PCI_ANY_ID, | 2805 | .subvendor = PCI_ANY_ID, |
2661 | .subdevice = PCI_ANY_ID, | 2806 | .subdevice = PCI_ANY_ID, |
2662 | .setup = pci_fintek_setup, | 2807 | .setup = pci_fintek_setup, |
2808 | .init = pci_fintek_init, | ||
2663 | }, | 2809 | }, |
2664 | { | 2810 | { |
2665 | .vendor = 0x1c29, | 2811 | .vendor = 0x1c29, |
@@ -2667,6 +2813,7 @@ static struct pci_serial_quirk pci_serial_quirks[] __refdata = { | |||
2667 | .subvendor = PCI_ANY_ID, | 2813 | .subvendor = PCI_ANY_ID, |
2668 | .subdevice = PCI_ANY_ID, | 2814 | .subdevice = PCI_ANY_ID, |
2669 | .setup = pci_fintek_setup, | 2815 | .setup = pci_fintek_setup, |
2816 | .init = pci_fintek_init, | ||
2670 | }, | 2817 | }, |
2671 | 2818 | ||
2672 | /* | 2819 | /* |
@@ -2864,6 +3011,8 @@ enum pci_board_num_t { | |||
2864 | pbn_ADDIDATA_PCIe_8_3906250, | 3011 | pbn_ADDIDATA_PCIe_8_3906250, |
2865 | pbn_ce4100_1_115200, | 3012 | pbn_ce4100_1_115200, |
2866 | pbn_byt, | 3013 | pbn_byt, |
3014 | pbn_pnw, | ||
3015 | pbn_tng, | ||
2867 | pbn_qrk, | 3016 | pbn_qrk, |
2868 | pbn_omegapci, | 3017 | pbn_omegapci, |
2869 | pbn_NETMOS9900_2s_115200, | 3018 | pbn_NETMOS9900_2s_115200, |
@@ -3630,6 +3779,16 @@ static struct pciserial_board pci_boards[] = { | |||
3630 | .uart_offset = 0x80, | 3779 | .uart_offset = 0x80, |
3631 | .reg_shift = 2, | 3780 | .reg_shift = 2, |
3632 | }, | 3781 | }, |
3782 | [pbn_pnw] = { | ||
3783 | .flags = FL_BASE0, | ||
3784 | .num_ports = 1, | ||
3785 | .base_baud = 115200, | ||
3786 | }, | ||
3787 | [pbn_tng] = { | ||
3788 | .flags = FL_BASE0, | ||
3789 | .num_ports = 1, | ||
3790 | .base_baud = 1843200, | ||
3791 | }, | ||
3633 | [pbn_qrk] = { | 3792 | [pbn_qrk] = { |
3634 | .flags = FL_BASE0, | 3793 | .flags = FL_BASE0, |
3635 | .num_ports = 1, | 3794 | .num_ports = 1, |
@@ -4006,41 +4165,41 @@ static void pciserial_remove_one(struct pci_dev *dev) | |||
4006 | pci_disable_device(dev); | 4165 | pci_disable_device(dev); |
4007 | } | 4166 | } |
4008 | 4167 | ||
4009 | #ifdef CONFIG_PM | 4168 | #ifdef CONFIG_PM_SLEEP |
4010 | static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state) | 4169 | static int pciserial_suspend_one(struct device *dev) |
4011 | { | 4170 | { |
4012 | struct serial_private *priv = pci_get_drvdata(dev); | 4171 | struct pci_dev *pdev = to_pci_dev(dev); |
4172 | struct serial_private *priv = pci_get_drvdata(pdev); | ||
4013 | 4173 | ||
4014 | if (priv) | 4174 | if (priv) |
4015 | pciserial_suspend_ports(priv); | 4175 | pciserial_suspend_ports(priv); |
4016 | 4176 | ||
4017 | pci_save_state(dev); | ||
4018 | pci_set_power_state(dev, pci_choose_state(dev, state)); | ||
4019 | return 0; | 4177 | return 0; |
4020 | } | 4178 | } |
4021 | 4179 | ||
4022 | static int pciserial_resume_one(struct pci_dev *dev) | 4180 | static int pciserial_resume_one(struct device *dev) |
4023 | { | 4181 | { |
4182 | struct pci_dev *pdev = to_pci_dev(dev); | ||
4183 | struct serial_private *priv = pci_get_drvdata(pdev); | ||
4024 | int err; | 4184 | int err; |
4025 | struct serial_private *priv = pci_get_drvdata(dev); | ||
4026 | |||
4027 | pci_set_power_state(dev, PCI_D0); | ||
4028 | pci_restore_state(dev); | ||
4029 | 4185 | ||
4030 | if (priv) { | 4186 | if (priv) { |
4031 | /* | 4187 | /* |
4032 | * The device may have been disabled. Re-enable it. | 4188 | * The device may have been disabled. Re-enable it. |
4033 | */ | 4189 | */ |
4034 | err = pci_enable_device(dev); | 4190 | err = pci_enable_device(pdev); |
4035 | /* FIXME: We cannot simply error out here */ | 4191 | /* FIXME: We cannot simply error out here */ |
4036 | if (err) | 4192 | if (err) |
4037 | dev_err(&dev->dev, "Unable to re-enable ports, trying to continue.\n"); | 4193 | dev_err(dev, "Unable to re-enable ports, trying to continue.\n"); |
4038 | pciserial_resume_ports(priv); | 4194 | pciserial_resume_ports(priv); |
4039 | } | 4195 | } |
4040 | return 0; | 4196 | return 0; |
4041 | } | 4197 | } |
4042 | #endif | 4198 | #endif |
4043 | 4199 | ||
4200 | static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one, | ||
4201 | pciserial_resume_one); | ||
4202 | |||
4044 | static struct pci_device_id serial_pci_tbl[] = { | 4203 | static struct pci_device_id serial_pci_tbl[] = { |
4045 | /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */ | 4204 | /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */ |
4046 | { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620, | 4205 | { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620, |
@@ -5363,6 +5522,26 @@ static struct pci_device_id serial_pci_tbl[] = { | |||
5363 | pbn_byt }, | 5522 | pbn_byt }, |
5364 | 5523 | ||
5365 | /* | 5524 | /* |
5525 | * Intel Penwell | ||
5526 | */ | ||
5527 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PNW_UART1, | ||
5528 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
5529 | pbn_pnw}, | ||
5530 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PNW_UART2, | ||
5531 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
5532 | pbn_pnw}, | ||
5533 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PNW_UART3, | ||
5534 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
5535 | pbn_pnw}, | ||
5536 | |||
5537 | /* | ||
5538 | * Intel Tangier | ||
5539 | */ | ||
5540 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TNG_UART, | ||
5541 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
5542 | pbn_tng}, | ||
5543 | |||
5544 | /* | ||
5366 | * Intel Quark x1000 | 5545 | * Intel Quark x1000 |
5367 | */ | 5546 | */ |
5368 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_UART, | 5547 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_UART, |
@@ -5510,10 +5689,9 @@ static struct pci_driver serial_pci_driver = { | |||
5510 | .name = "serial", | 5689 | .name = "serial", |
5511 | .probe = pciserial_init_one, | 5690 | .probe = pciserial_init_one, |
5512 | .remove = pciserial_remove_one, | 5691 | .remove = pciserial_remove_one, |
5513 | #ifdef CONFIG_PM | 5692 | .driver = { |
5514 | .suspend = pciserial_suspend_one, | 5693 | .pm = &pciserial_pm_ops, |
5515 | .resume = pciserial_resume_one, | 5694 | }, |
5516 | #endif | ||
5517 | .id_table = serial_pci_tbl, | 5695 | .id_table = serial_pci_tbl, |
5518 | .err_handler = &serial8250_err_handler, | 5696 | .err_handler = &serial8250_err_handler, |
5519 | }; | 5697 | }; |
diff --git a/drivers/tty/serial/8250/Kconfig b/drivers/tty/serial/8250/Kconfig index 6f7f2d753def..c35070356528 100644 --- a/drivers/tty/serial/8250/Kconfig +++ b/drivers/tty/serial/8250/Kconfig | |||
@@ -108,6 +108,7 @@ config SERIAL_8250_PCI | |||
108 | tristate "8250/16550 PCI device support" if EXPERT | 108 | tristate "8250/16550 PCI device support" if EXPERT |
109 | depends on SERIAL_8250 && PCI | 109 | depends on SERIAL_8250 && PCI |
110 | default SERIAL_8250 | 110 | default SERIAL_8250 |
111 | select RATIONAL | ||
111 | help | 112 | help |
112 | This builds standard PCI serial support. You may be able to | 113 | This builds standard PCI serial support. You may be able to |
113 | disable this feature if you only need legacy serial support. | 114 | disable this feature if you only need legacy serial support. |
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index d2501f01cd03..f8120c1bde14 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig | |||
@@ -20,7 +20,7 @@ comment "Non-8250 serial port support" | |||
20 | 20 | ||
21 | config SERIAL_AMBA_PL010 | 21 | config SERIAL_AMBA_PL010 |
22 | tristate "ARM AMBA PL010 serial port support" | 22 | tristate "ARM AMBA PL010 serial port support" |
23 | depends on ARM_AMBA && (BROKEN || !ARCH_VERSATILE) | 23 | depends on ARM_AMBA |
24 | select SERIAL_CORE | 24 | select SERIAL_CORE |
25 | help | 25 | help |
26 | This selects the ARM(R) AMBA(R) PrimeCell PL010 UART. If you have | 26 | This selects the ARM(R) AMBA(R) PrimeCell PL010 UART. If you have |
@@ -483,16 +483,6 @@ config SERIAL_SA1100_CONSOLE | |||
483 | your boot loader (lilo or loadlin) about how to pass options to the | 483 | your boot loader (lilo or loadlin) about how to pass options to the |
484 | kernel at boot time.) | 484 | kernel at boot time.) |
485 | 485 | ||
486 | config SERIAL_MFD_HSU | ||
487 | tristate "Medfield High Speed UART support" | ||
488 | depends on PCI | ||
489 | select SERIAL_CORE | ||
490 | |||
491 | config SERIAL_MFD_HSU_CONSOLE | ||
492 | bool "Medfile HSU serial console support" | ||
493 | depends on SERIAL_MFD_HSU=y | ||
494 | select SERIAL_CORE_CONSOLE | ||
495 | |||
496 | config SERIAL_BFIN | 486 | config SERIAL_BFIN |
497 | tristate "Blackfin serial port support" | 487 | tristate "Blackfin serial port support" |
498 | depends on BLACKFIN | 488 | depends on BLACKFIN |
@@ -835,7 +825,7 @@ config SERIAL_MCF_CONSOLE | |||
835 | 825 | ||
836 | config SERIAL_PMACZILOG | 826 | config SERIAL_PMACZILOG |
837 | tristate "Mac or PowerMac z85c30 ESCC support" | 827 | tristate "Mac or PowerMac z85c30 ESCC support" |
838 | depends on (M68K && MAC) || (PPC_OF && PPC_PMAC) | 828 | depends on (M68K && MAC) || PPC_PMAC |
839 | select SERIAL_CORE | 829 | select SERIAL_CORE |
840 | help | 830 | help |
841 | This driver supports the Zilog z85C30 serial ports found on | 831 | This driver supports the Zilog z85C30 serial ports found on |
@@ -878,7 +868,7 @@ config SERIAL_PMACZILOG_CONSOLE | |||
878 | 868 | ||
879 | config SERIAL_CPM | 869 | config SERIAL_CPM |
880 | tristate "CPM SCC/SMC serial port support" | 870 | tristate "CPM SCC/SMC serial port support" |
881 | depends on CPM2 || 8xx | 871 | depends on CPM2 || CPM1 |
882 | select SERIAL_CORE | 872 | select SERIAL_CORE |
883 | help | 873 | help |
884 | This driver supports the SCC and SMC serial ports on Motorola | 874 | This driver supports the SCC and SMC serial ports on Motorola |
@@ -1054,7 +1044,7 @@ config SERIAL_SGI_IOC3 | |||
1054 | 1044 | ||
1055 | config SERIAL_MSM | 1045 | config SERIAL_MSM |
1056 | bool "MSM on-chip serial port support" | 1046 | bool "MSM on-chip serial port support" |
1057 | depends on ARCH_MSM || ARCH_QCOM | 1047 | depends on ARCH_QCOM |
1058 | select SERIAL_CORE | 1048 | select SERIAL_CORE |
1059 | 1049 | ||
1060 | config SERIAL_MSM_CONSOLE | 1050 | config SERIAL_MSM_CONSOLE |
@@ -1063,18 +1053,6 @@ config SERIAL_MSM_CONSOLE | |||
1063 | select SERIAL_CORE_CONSOLE | 1053 | select SERIAL_CORE_CONSOLE |
1064 | select SERIAL_EARLYCON | 1054 | select SERIAL_EARLYCON |
1065 | 1055 | ||
1066 | config SERIAL_MSM_HS | ||
1067 | tristate "MSM UART High Speed: Serial Driver" | ||
1068 | depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50 | ||
1069 | select SERIAL_CORE | ||
1070 | help | ||
1071 | If you have a machine based on MSM family of SoCs, you | ||
1072 | can enable its onboard high speed serial port by enabling | ||
1073 | this option. | ||
1074 | |||
1075 | Choose M here to compile it as a module. The module will be | ||
1076 | called msm_serial_hs. | ||
1077 | |||
1078 | config SERIAL_VT8500 | 1056 | config SERIAL_VT8500 |
1079 | bool "VIA VT8500 on-chip serial port support" | 1057 | bool "VIA VT8500 on-chip serial port support" |
1080 | depends on ARCH_VT8500 | 1058 | depends on ARCH_VT8500 |
@@ -1153,7 +1131,7 @@ config SERIAL_OMAP_CONSOLE | |||
1153 | 1131 | ||
1154 | config SERIAL_OF_PLATFORM_NWPSERIAL | 1132 | config SERIAL_OF_PLATFORM_NWPSERIAL |
1155 | tristate "NWP serial port driver" | 1133 | tristate "NWP serial port driver" |
1156 | depends on PPC_OF && PPC_DCR | 1134 | depends on PPC_DCR |
1157 | select SERIAL_OF_PLATFORM | 1135 | select SERIAL_OF_PLATFORM |
1158 | select SERIAL_CORE_CONSOLE | 1136 | select SERIAL_CORE_CONSOLE |
1159 | select SERIAL_CORE | 1137 | select SERIAL_CORE |
diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile index 599be4b05a26..c3ac3d930b33 100644 --- a/drivers/tty/serial/Makefile +++ b/drivers/tty/serial/Makefile | |||
@@ -62,7 +62,6 @@ obj-$(CONFIG_SERIAL_SGI_IOC3) += ioc3_serial.o | |||
62 | obj-$(CONFIG_SERIAL_ATMEL) += atmel_serial.o | 62 | obj-$(CONFIG_SERIAL_ATMEL) += atmel_serial.o |
63 | obj-$(CONFIG_SERIAL_UARTLITE) += uartlite.o | 63 | obj-$(CONFIG_SERIAL_UARTLITE) += uartlite.o |
64 | obj-$(CONFIG_SERIAL_MSM) += msm_serial.o | 64 | obj-$(CONFIG_SERIAL_MSM) += msm_serial.o |
65 | obj-$(CONFIG_SERIAL_MSM_HS) += msm_serial_hs.o | ||
66 | obj-$(CONFIG_SERIAL_NETX) += netx-serial.o | 65 | obj-$(CONFIG_SERIAL_NETX) += netx-serial.o |
67 | obj-$(CONFIG_SERIAL_OF_PLATFORM) += of_serial.o | 66 | obj-$(CONFIG_SERIAL_OF_PLATFORM) += of_serial.o |
68 | obj-$(CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL) += nwpserial.o | 67 | obj-$(CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL) += nwpserial.o |
@@ -78,7 +77,6 @@ obj-$(CONFIG_SERIAL_TIMBERDALE) += timbuart.o | |||
78 | obj-$(CONFIG_SERIAL_GRLIB_GAISLER_APBUART) += apbuart.o | 77 | obj-$(CONFIG_SERIAL_GRLIB_GAISLER_APBUART) += apbuart.o |
79 | obj-$(CONFIG_SERIAL_ALTERA_JTAGUART) += altera_jtaguart.o | 78 | obj-$(CONFIG_SERIAL_ALTERA_JTAGUART) += altera_jtaguart.o |
80 | obj-$(CONFIG_SERIAL_VT8500) += vt8500_serial.o | 79 | obj-$(CONFIG_SERIAL_VT8500) += vt8500_serial.o |
81 | obj-$(CONFIG_SERIAL_MFD_HSU) += mfd.o | ||
82 | obj-$(CONFIG_SERIAL_IFX6X60) += ifx6x60.o | 80 | obj-$(CONFIG_SERIAL_IFX6X60) += ifx6x60.o |
83 | obj-$(CONFIG_SERIAL_PCH_UART) += pch_uart.o | 81 | obj-$(CONFIG_SERIAL_PCH_UART) += pch_uart.o |
84 | obj-$(CONFIG_SERIAL_MSM_SMD) += msm_smd_tty.o | 82 | obj-$(CONFIG_SERIAL_MSM_SMD) += msm_smd_tty.o |
diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c index 8d94c194f090..5a4e9d579585 100644 --- a/drivers/tty/serial/amba-pl011.c +++ b/drivers/tty/serial/amba-pl011.c | |||
@@ -58,6 +58,7 @@ | |||
58 | #include <linux/pinctrl/consumer.h> | 58 | #include <linux/pinctrl/consumer.h> |
59 | #include <linux/sizes.h> | 59 | #include <linux/sizes.h> |
60 | #include <linux/io.h> | 60 | #include <linux/io.h> |
61 | #include <linux/workqueue.h> | ||
61 | 62 | ||
62 | #define UART_NR 14 | 63 | #define UART_NR 14 |
63 | 64 | ||
@@ -156,7 +157,9 @@ struct uart_amba_port { | |||
156 | unsigned int lcrh_tx; /* vendor-specific */ | 157 | unsigned int lcrh_tx; /* vendor-specific */ |
157 | unsigned int lcrh_rx; /* vendor-specific */ | 158 | unsigned int lcrh_rx; /* vendor-specific */ |
158 | unsigned int old_cr; /* state during shutdown */ | 159 | unsigned int old_cr; /* state during shutdown */ |
160 | struct delayed_work tx_softirq_work; | ||
159 | bool autorts; | 161 | bool autorts; |
162 | unsigned int tx_irq_seen; /* 0=none, 1=1, 2=2 or more */ | ||
160 | char type[12]; | 163 | char type[12]; |
161 | #ifdef CONFIG_DMA_ENGINE | 164 | #ifdef CONFIG_DMA_ENGINE |
162 | /* DMA stuff */ | 165 | /* DMA stuff */ |
@@ -164,6 +167,7 @@ struct uart_amba_port { | |||
164 | bool using_rx_dma; | 167 | bool using_rx_dma; |
165 | struct pl011_dmarx_data dmarx; | 168 | struct pl011_dmarx_data dmarx; |
166 | struct pl011_dmatx_data dmatx; | 169 | struct pl011_dmatx_data dmatx; |
170 | bool dma_probed; | ||
167 | #endif | 171 | #endif |
168 | }; | 172 | }; |
169 | 173 | ||
@@ -261,10 +265,11 @@ static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg, | |||
261 | } | 265 | } |
262 | } | 266 | } |
263 | 267 | ||
264 | static void pl011_dma_probe_initcall(struct device *dev, struct uart_amba_port *uap) | 268 | static void pl011_dma_probe(struct uart_amba_port *uap) |
265 | { | 269 | { |
266 | /* DMA is the sole user of the platform data right now */ | 270 | /* DMA is the sole user of the platform data right now */ |
267 | struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev); | 271 | struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev); |
272 | struct device *dev = uap->port.dev; | ||
268 | struct dma_slave_config tx_conf = { | 273 | struct dma_slave_config tx_conf = { |
269 | .dst_addr = uap->port.mapbase + UART01x_DR, | 274 | .dst_addr = uap->port.mapbase + UART01x_DR, |
270 | .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, | 275 | .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, |
@@ -275,9 +280,14 @@ static void pl011_dma_probe_initcall(struct device *dev, struct uart_amba_port * | |||
275 | struct dma_chan *chan; | 280 | struct dma_chan *chan; |
276 | dma_cap_mask_t mask; | 281 | dma_cap_mask_t mask; |
277 | 282 | ||
278 | chan = dma_request_slave_channel(dev, "tx"); | 283 | uap->dma_probed = true; |
284 | chan = dma_request_slave_channel_reason(dev, "tx"); | ||
285 | if (IS_ERR(chan)) { | ||
286 | if (PTR_ERR(chan) == -EPROBE_DEFER) { | ||
287 | uap->dma_probed = false; | ||
288 | return; | ||
289 | } | ||
279 | 290 | ||
280 | if (!chan) { | ||
281 | /* We need platform data */ | 291 | /* We need platform data */ |
282 | if (!plat || !plat->dma_filter) { | 292 | if (!plat || !plat->dma_filter) { |
283 | dev_info(uap->port.dev, "no DMA platform data\n"); | 293 | dev_info(uap->port.dev, "no DMA platform data\n"); |
@@ -385,63 +395,17 @@ static void pl011_dma_probe_initcall(struct device *dev, struct uart_amba_port * | |||
385 | } | 395 | } |
386 | } | 396 | } |
387 | 397 | ||
388 | #ifndef MODULE | ||
389 | /* | ||
390 | * Stack up the UARTs and let the above initcall be done at device | ||
391 | * initcall time, because the serial driver is called as an arch | ||
392 | * initcall, and at this time the DMA subsystem is not yet registered. | ||
393 | * At this point the driver will switch over to using DMA where desired. | ||
394 | */ | ||
395 | struct dma_uap { | ||
396 | struct list_head node; | ||
397 | struct uart_amba_port *uap; | ||
398 | struct device *dev; | ||
399 | }; | ||
400 | |||
401 | static LIST_HEAD(pl011_dma_uarts); | ||
402 | |||
403 | static int __init pl011_dma_initcall(void) | ||
404 | { | ||
405 | struct list_head *node, *tmp; | ||
406 | |||
407 | list_for_each_safe(node, tmp, &pl011_dma_uarts) { | ||
408 | struct dma_uap *dmau = list_entry(node, struct dma_uap, node); | ||
409 | pl011_dma_probe_initcall(dmau->dev, dmau->uap); | ||
410 | list_del(node); | ||
411 | kfree(dmau); | ||
412 | } | ||
413 | return 0; | ||
414 | } | ||
415 | |||
416 | device_initcall(pl011_dma_initcall); | ||
417 | |||
418 | static void pl011_dma_probe(struct device *dev, struct uart_amba_port *uap) | ||
419 | { | ||
420 | struct dma_uap *dmau = kzalloc(sizeof(struct dma_uap), GFP_KERNEL); | ||
421 | if (dmau) { | ||
422 | dmau->uap = uap; | ||
423 | dmau->dev = dev; | ||
424 | list_add_tail(&dmau->node, &pl011_dma_uarts); | ||
425 | } | ||
426 | } | ||
427 | #else | ||
428 | static void pl011_dma_probe(struct device *dev, struct uart_amba_port *uap) | ||
429 | { | ||
430 | pl011_dma_probe_initcall(dev, uap); | ||
431 | } | ||
432 | #endif | ||
433 | |||
434 | static void pl011_dma_remove(struct uart_amba_port *uap) | 398 | static void pl011_dma_remove(struct uart_amba_port *uap) |
435 | { | 399 | { |
436 | /* TODO: remove the initcall if it has not yet executed */ | ||
437 | if (uap->dmatx.chan) | 400 | if (uap->dmatx.chan) |
438 | dma_release_channel(uap->dmatx.chan); | 401 | dma_release_channel(uap->dmatx.chan); |
439 | if (uap->dmarx.chan) | 402 | if (uap->dmarx.chan) |
440 | dma_release_channel(uap->dmarx.chan); | 403 | dma_release_channel(uap->dmarx.chan); |
441 | } | 404 | } |
442 | 405 | ||
443 | /* Forward declare this for the refill routine */ | 406 | /* Forward declare these for the refill routine */ |
444 | static int pl011_dma_tx_refill(struct uart_amba_port *uap); | 407 | static int pl011_dma_tx_refill(struct uart_amba_port *uap); |
408 | static void pl011_start_tx_pio(struct uart_amba_port *uap); | ||
445 | 409 | ||
446 | /* | 410 | /* |
447 | * The current DMA TX buffer has been sent. | 411 | * The current DMA TX buffer has been sent. |
@@ -479,14 +443,13 @@ static void pl011_dma_tx_callback(void *data) | |||
479 | return; | 443 | return; |
480 | } | 444 | } |
481 | 445 | ||
482 | if (pl011_dma_tx_refill(uap) <= 0) { | 446 | if (pl011_dma_tx_refill(uap) <= 0) |
483 | /* | 447 | /* |
484 | * We didn't queue a DMA buffer for some reason, but we | 448 | * We didn't queue a DMA buffer for some reason, but we |
485 | * have data pending to be sent. Re-enable the TX IRQ. | 449 | * have data pending to be sent. Re-enable the TX IRQ. |
486 | */ | 450 | */ |
487 | uap->im |= UART011_TXIM; | 451 | pl011_start_tx_pio(uap); |
488 | writew(uap->im, uap->port.membase + UART011_IMSC); | 452 | |
489 | } | ||
490 | spin_unlock_irqrestore(&uap->port.lock, flags); | 453 | spin_unlock_irqrestore(&uap->port.lock, flags); |
491 | } | 454 | } |
492 | 455 | ||
@@ -664,12 +627,10 @@ static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) | |||
664 | if (!uap->dmatx.queued) { | 627 | if (!uap->dmatx.queued) { |
665 | if (pl011_dma_tx_refill(uap) > 0) { | 628 | if (pl011_dma_tx_refill(uap) > 0) { |
666 | uap->im &= ~UART011_TXIM; | 629 | uap->im &= ~UART011_TXIM; |
667 | ret = true; | 630 | writew(uap->im, uap->port.membase + |
668 | } else { | 631 | UART011_IMSC); |
669 | uap->im |= UART011_TXIM; | 632 | } else |
670 | ret = false; | 633 | ret = false; |
671 | } | ||
672 | writew(uap->im, uap->port.membase + UART011_IMSC); | ||
673 | } else if (!(uap->dmacr & UART011_TXDMAE)) { | 634 | } else if (!(uap->dmacr & UART011_TXDMAE)) { |
674 | uap->dmacr |= UART011_TXDMAE; | 635 | uap->dmacr |= UART011_TXDMAE; |
675 | writew(uap->dmacr, | 636 | writew(uap->dmacr, |
@@ -1021,6 +982,9 @@ static void pl011_dma_startup(struct uart_amba_port *uap) | |||
1021 | { | 982 | { |
1022 | int ret; | 983 | int ret; |
1023 | 984 | ||
985 | if (!uap->dma_probed) | ||
986 | pl011_dma_probe(uap); | ||
987 | |||
1024 | if (!uap->dmatx.chan) | 988 | if (!uap->dmatx.chan) |
1025 | return; | 989 | return; |
1026 | 990 | ||
@@ -1142,7 +1106,7 @@ static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) | |||
1142 | 1106 | ||
1143 | #else | 1107 | #else |
1144 | /* Blank functions if the DMA engine is not available */ | 1108 | /* Blank functions if the DMA engine is not available */ |
1145 | static inline void pl011_dma_probe(struct device *dev, struct uart_amba_port *uap) | 1109 | static inline void pl011_dma_probe(struct uart_amba_port *uap) |
1146 | { | 1110 | { |
1147 | } | 1111 | } |
1148 | 1112 | ||
@@ -1208,15 +1172,24 @@ static void pl011_stop_tx(struct uart_port *port) | |||
1208 | pl011_dma_tx_stop(uap); | 1172 | pl011_dma_tx_stop(uap); |
1209 | } | 1173 | } |
1210 | 1174 | ||
1175 | static bool pl011_tx_chars(struct uart_amba_port *uap); | ||
1176 | |||
1177 | /* Start TX with programmed I/O only (no DMA) */ | ||
1178 | static void pl011_start_tx_pio(struct uart_amba_port *uap) | ||
1179 | { | ||
1180 | uap->im |= UART011_TXIM; | ||
1181 | writew(uap->im, uap->port.membase + UART011_IMSC); | ||
1182 | if (!uap->tx_irq_seen) | ||
1183 | pl011_tx_chars(uap); | ||
1184 | } | ||
1185 | |||
1211 | static void pl011_start_tx(struct uart_port *port) | 1186 | static void pl011_start_tx(struct uart_port *port) |
1212 | { | 1187 | { |
1213 | struct uart_amba_port *uap = | 1188 | struct uart_amba_port *uap = |
1214 | container_of(port, struct uart_amba_port, port); | 1189 | container_of(port, struct uart_amba_port, port); |
1215 | 1190 | ||
1216 | if (!pl011_dma_tx_start(uap)) { | 1191 | if (!pl011_dma_tx_start(uap)) |
1217 | uap->im |= UART011_TXIM; | 1192 | pl011_start_tx_pio(uap); |
1218 | writew(uap->im, uap->port.membase + UART011_IMSC); | ||
1219 | } | ||
1220 | } | 1193 | } |
1221 | 1194 | ||
1222 | static void pl011_stop_rx(struct uart_port *port) | 1195 | static void pl011_stop_rx(struct uart_port *port) |
@@ -1274,40 +1247,87 @@ __acquires(&uap->port.lock) | |||
1274 | spin_lock(&uap->port.lock); | 1247 | spin_lock(&uap->port.lock); |
1275 | } | 1248 | } |
1276 | 1249 | ||
1277 | static void pl011_tx_chars(struct uart_amba_port *uap) | 1250 | /* |
1251 | * Transmit a character | ||
1252 | * There must be at least one free entry in the TX FIFO to accept the char. | ||
1253 | * | ||
1254 | * Returns true if the FIFO might have space in it afterwards; | ||
1255 | * returns false if the FIFO definitely became full. | ||
1256 | */ | ||
1257 | static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c) | ||
1258 | { | ||
1259 | writew(c, uap->port.membase + UART01x_DR); | ||
1260 | uap->port.icount.tx++; | ||
1261 | |||
1262 | if (likely(uap->tx_irq_seen > 1)) | ||
1263 | return true; | ||
1264 | |||
1265 | return !(readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF); | ||
1266 | } | ||
1267 | |||
1268 | static bool pl011_tx_chars(struct uart_amba_port *uap) | ||
1278 | { | 1269 | { |
1279 | struct circ_buf *xmit = &uap->port.state->xmit; | 1270 | struct circ_buf *xmit = &uap->port.state->xmit; |
1280 | int count; | 1271 | int count; |
1281 | 1272 | ||
1273 | if (unlikely(uap->tx_irq_seen < 2)) | ||
1274 | /* | ||
1275 | * Initial FIFO fill level unknown: we must check TXFF | ||
1276 | * after each write, so just try to fill up the FIFO. | ||
1277 | */ | ||
1278 | count = uap->fifosize; | ||
1279 | else /* tx_irq_seen >= 2 */ | ||
1280 | /* | ||
1281 | * FIFO initially at least half-empty, so we can simply | ||
1282 | * write half the FIFO without polling TXFF. | ||
1283 | |||
1284 | * Note: the *first* TX IRQ can still race with | ||
1285 | * pl011_start_tx_pio(), which can result in the FIFO | ||
1286 | * being fuller than expected in that case. | ||
1287 | */ | ||
1288 | count = uap->fifosize >> 1; | ||
1289 | |||
1290 | /* | ||
1291 | * If the FIFO is full we're guaranteed a TX IRQ at some later point, | ||
1292 | * and can't transmit immediately in any case: | ||
1293 | */ | ||
1294 | if (unlikely(uap->tx_irq_seen < 2 && | ||
1295 | readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)) | ||
1296 | return false; | ||
1297 | |||
1282 | if (uap->port.x_char) { | 1298 | if (uap->port.x_char) { |
1283 | writew(uap->port.x_char, uap->port.membase + UART01x_DR); | 1299 | pl011_tx_char(uap, uap->port.x_char); |
1284 | uap->port.icount.tx++; | ||
1285 | uap->port.x_char = 0; | 1300 | uap->port.x_char = 0; |
1286 | return; | 1301 | --count; |
1287 | } | 1302 | } |
1288 | if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) { | 1303 | if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) { |
1289 | pl011_stop_tx(&uap->port); | 1304 | pl011_stop_tx(&uap->port); |
1290 | return; | 1305 | goto done; |
1291 | } | 1306 | } |
1292 | 1307 | ||
1293 | /* If we are using DMA mode, try to send some characters. */ | 1308 | /* If we are using DMA mode, try to send some characters. */ |
1294 | if (pl011_dma_tx_irq(uap)) | 1309 | if (pl011_dma_tx_irq(uap)) |
1295 | return; | 1310 | goto done; |
1296 | 1311 | ||
1297 | count = uap->fifosize >> 1; | 1312 | while (count-- > 0 && pl011_tx_char(uap, xmit->buf[xmit->tail])) { |
1298 | do { | ||
1299 | writew(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR); | ||
1300 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | 1313 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); |
1301 | uap->port.icount.tx++; | ||
1302 | if (uart_circ_empty(xmit)) | 1314 | if (uart_circ_empty(xmit)) |
1303 | break; | 1315 | break; |
1304 | } while (--count > 0); | 1316 | } |
1305 | 1317 | ||
1306 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | 1318 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
1307 | uart_write_wakeup(&uap->port); | 1319 | uart_write_wakeup(&uap->port); |
1308 | 1320 | ||
1309 | if (uart_circ_empty(xmit)) | 1321 | if (uart_circ_empty(xmit)) { |
1310 | pl011_stop_tx(&uap->port); | 1322 | pl011_stop_tx(&uap->port); |
1323 | goto done; | ||
1324 | } | ||
1325 | |||
1326 | if (unlikely(!uap->tx_irq_seen)) | ||
1327 | schedule_delayed_work(&uap->tx_softirq_work, uap->port.timeout); | ||
1328 | |||
1329 | done: | ||
1330 | return false; | ||
1311 | } | 1331 | } |
1312 | 1332 | ||
1313 | static void pl011_modem_status(struct uart_amba_port *uap) | 1333 | static void pl011_modem_status(struct uart_amba_port *uap) |
@@ -1334,6 +1354,28 @@ static void pl011_modem_status(struct uart_amba_port *uap) | |||
1334 | wake_up_interruptible(&uap->port.state->port.delta_msr_wait); | 1354 | wake_up_interruptible(&uap->port.state->port.delta_msr_wait); |
1335 | } | 1355 | } |
1336 | 1356 | ||
1357 | static void pl011_tx_softirq(struct work_struct *work) | ||
1358 | { | ||
1359 | struct delayed_work *dwork = to_delayed_work(work); | ||
1360 | struct uart_amba_port *uap = | ||
1361 | container_of(dwork, struct uart_amba_port, tx_softirq_work); | ||
1362 | |||
1363 | spin_lock(&uap->port.lock); | ||
1364 | while (pl011_tx_chars(uap)) ; | ||
1365 | spin_unlock(&uap->port.lock); | ||
1366 | } | ||
1367 | |||
1368 | static void pl011_tx_irq_seen(struct uart_amba_port *uap) | ||
1369 | { | ||
1370 | if (likely(uap->tx_irq_seen > 1)) | ||
1371 | return; | ||
1372 | |||
1373 | uap->tx_irq_seen++; | ||
1374 | if (uap->tx_irq_seen < 2) | ||
1375 | /* first TX IRQ */ | ||
1376 | cancel_delayed_work(&uap->tx_softirq_work); | ||
1377 | } | ||
1378 | |||
1337 | static irqreturn_t pl011_int(int irq, void *dev_id) | 1379 | static irqreturn_t pl011_int(int irq, void *dev_id) |
1338 | { | 1380 | { |
1339 | struct uart_amba_port *uap = dev_id; | 1381 | struct uart_amba_port *uap = dev_id; |
@@ -1372,8 +1414,10 @@ static irqreturn_t pl011_int(int irq, void *dev_id) | |||
1372 | if (status & (UART011_DSRMIS|UART011_DCDMIS| | 1414 | if (status & (UART011_DSRMIS|UART011_DCDMIS| |
1373 | UART011_CTSMIS|UART011_RIMIS)) | 1415 | UART011_CTSMIS|UART011_RIMIS)) |
1374 | pl011_modem_status(uap); | 1416 | pl011_modem_status(uap); |
1375 | if (status & UART011_TXIS) | 1417 | if (status & UART011_TXIS) { |
1418 | pl011_tx_irq_seen(uap); | ||
1376 | pl011_tx_chars(uap); | 1419 | pl011_tx_chars(uap); |
1420 | } | ||
1377 | 1421 | ||
1378 | if (pass_counter-- == 0) | 1422 | if (pass_counter-- == 0) |
1379 | break; | 1423 | break; |
@@ -1577,7 +1621,7 @@ static int pl011_startup(struct uart_port *port) | |||
1577 | { | 1621 | { |
1578 | struct uart_amba_port *uap = | 1622 | struct uart_amba_port *uap = |
1579 | container_of(port, struct uart_amba_port, port); | 1623 | container_of(port, struct uart_amba_port, port); |
1580 | unsigned int cr, lcr_h, fbrd, ibrd; | 1624 | unsigned int cr; |
1581 | int retval; | 1625 | int retval; |
1582 | 1626 | ||
1583 | retval = pl011_hwinit(port); | 1627 | retval = pl011_hwinit(port); |
@@ -1595,30 +1639,8 @@ static int pl011_startup(struct uart_port *port) | |||
1595 | 1639 | ||
1596 | writew(uap->vendor->ifls, uap->port.membase + UART011_IFLS); | 1640 | writew(uap->vendor->ifls, uap->port.membase + UART011_IFLS); |
1597 | 1641 | ||
1598 | /* | ||
1599 | * Provoke TX FIFO interrupt into asserting. Taking care to preserve | ||
1600 | * baud rate and data format specified by FBRD, IBRD and LCRH as the | ||
1601 | * UART may already be in use as a console. | ||
1602 | */ | ||
1603 | spin_lock_irq(&uap->port.lock); | 1642 | spin_lock_irq(&uap->port.lock); |
1604 | 1643 | ||
1605 | fbrd = readw(uap->port.membase + UART011_FBRD); | ||
1606 | ibrd = readw(uap->port.membase + UART011_IBRD); | ||
1607 | lcr_h = readw(uap->port.membase + uap->lcrh_rx); | ||
1608 | |||
1609 | cr = UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_LBE; | ||
1610 | writew(cr, uap->port.membase + UART011_CR); | ||
1611 | writew(0, uap->port.membase + UART011_FBRD); | ||
1612 | writew(1, uap->port.membase + UART011_IBRD); | ||
1613 | pl011_write_lcr_h(uap, 0); | ||
1614 | writew(0, uap->port.membase + UART01x_DR); | ||
1615 | while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY) | ||
1616 | barrier(); | ||
1617 | |||
1618 | writew(fbrd, uap->port.membase + UART011_FBRD); | ||
1619 | writew(ibrd, uap->port.membase + UART011_IBRD); | ||
1620 | pl011_write_lcr_h(uap, lcr_h); | ||
1621 | |||
1622 | /* restore RTS and DTR */ | 1644 | /* restore RTS and DTR */ |
1623 | cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR); | 1645 | cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR); |
1624 | cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE; | 1646 | cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE; |
@@ -1672,13 +1694,15 @@ static void pl011_shutdown(struct uart_port *port) | |||
1672 | container_of(port, struct uart_amba_port, port); | 1694 | container_of(port, struct uart_amba_port, port); |
1673 | unsigned int cr; | 1695 | unsigned int cr; |
1674 | 1696 | ||
1697 | cancel_delayed_work_sync(&uap->tx_softirq_work); | ||
1698 | |||
1675 | /* | 1699 | /* |
1676 | * disable all interrupts | 1700 | * disable all interrupts |
1677 | */ | 1701 | */ |
1678 | spin_lock_irq(&uap->port.lock); | 1702 | spin_lock_irq(&uap->port.lock); |
1679 | uap->im = 0; | 1703 | uap->im = 0; |
1680 | writew(uap->im, uap->port.membase + UART011_IMSC); | 1704 | writew(uap->im, uap->port.membase + UART011_IMSC); |
1681 | writew(0xffff, uap->port.membase + UART011_ICR); | 1705 | writew(0xffff & ~UART011_TXIS, uap->port.membase + UART011_ICR); |
1682 | spin_unlock_irq(&uap->port.lock); | 1706 | spin_unlock_irq(&uap->port.lock); |
1683 | 1707 | ||
1684 | pl011_dma_shutdown(uap); | 1708 | pl011_dma_shutdown(uap); |
@@ -2218,7 +2242,7 @@ static int pl011_probe(struct amba_device *dev, const struct amba_id *id) | |||
2218 | uap->port.ops = &amba_pl011_pops; | 2242 | uap->port.ops = &amba_pl011_pops; |
2219 | uap->port.flags = UPF_BOOT_AUTOCONF; | 2243 | uap->port.flags = UPF_BOOT_AUTOCONF; |
2220 | uap->port.line = i; | 2244 | uap->port.line = i; |
2221 | pl011_dma_probe(&dev->dev, uap); | 2245 | INIT_DELAYED_WORK(&uap->tx_softirq_work, pl011_tx_softirq); |
2222 | 2246 | ||
2223 | /* Ensure interrupts from this UART are masked and cleared */ | 2247 | /* Ensure interrupts from this UART are masked and cleared */ |
2224 | writew(0, uap->port.membase + UART011_IMSC); | 2248 | writew(0, uap->port.membase + UART011_IMSC); |
@@ -2233,7 +2257,8 @@ static int pl011_probe(struct amba_device *dev, const struct amba_id *id) | |||
2233 | if (!amba_reg.state) { | 2257 | if (!amba_reg.state) { |
2234 | ret = uart_register_driver(&amba_reg); | 2258 | ret = uart_register_driver(&amba_reg); |
2235 | if (ret < 0) { | 2259 | if (ret < 0) { |
2236 | pr_err("Failed to register AMBA-PL011 driver\n"); | 2260 | dev_err(&dev->dev, |
2261 | "Failed to register AMBA-PL011 driver\n"); | ||
2237 | return ret; | 2262 | return ret; |
2238 | } | 2263 | } |
2239 | } | 2264 | } |
@@ -2242,7 +2267,6 @@ static int pl011_probe(struct amba_device *dev, const struct amba_id *id) | |||
2242 | if (ret) { | 2267 | if (ret) { |
2243 | amba_ports[i] = NULL; | 2268 | amba_ports[i] = NULL; |
2244 | uart_unregister_driver(&amba_reg); | 2269 | uart_unregister_driver(&amba_reg); |
2245 | pl011_dma_remove(uap); | ||
2246 | } | 2270 | } |
2247 | 2271 | ||
2248 | return ret; | 2272 | return ret; |
diff --git a/drivers/tty/serial/apbuart.c b/drivers/tty/serial/apbuart.c index 4f0f95e358e8..f3af317131ac 100644 --- a/drivers/tty/serial/apbuart.c +++ b/drivers/tty/serial/apbuart.c | |||
@@ -572,7 +572,7 @@ static int apbuart_probe(struct platform_device *op) | |||
572 | return 0; | 572 | return 0; |
573 | } | 573 | } |
574 | 574 | ||
575 | static struct of_device_id apbuart_match[] = { | 575 | static const struct of_device_id apbuart_match[] = { |
576 | { | 576 | { |
577 | .name = "GAISLER_APBUART", | 577 | .name = "GAISLER_APBUART", |
578 | }, | 578 | }, |
diff --git a/drivers/tty/serial/ar933x_uart.c b/drivers/tty/serial/ar933x_uart.c index 77fc9faa74a4..1519d2ca7705 100644 --- a/drivers/tty/serial/ar933x_uart.c +++ b/drivers/tty/serial/ar933x_uart.c | |||
@@ -649,7 +649,7 @@ static int ar933x_uart_probe(struct platform_device *pdev) | |||
649 | id = 0; | 649 | id = 0; |
650 | } | 650 | } |
651 | 651 | ||
652 | if (id > CONFIG_SERIAL_AR933X_NR_UARTS) | 652 | if (id >= CONFIG_SERIAL_AR933X_NR_UARTS) |
653 | return -EINVAL; | 653 | return -EINVAL; |
654 | 654 | ||
655 | irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | 655 | irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c index 4e959c43f680..d58fe4763d9e 100644 --- a/drivers/tty/serial/atmel_serial.c +++ b/drivers/tty/serial/atmel_serial.c | |||
@@ -855,7 +855,7 @@ static int atmel_prepare_tx_dma(struct uart_port *port) | |||
855 | spin_lock_init(&atmel_port->lock_tx); | 855 | spin_lock_init(&atmel_port->lock_tx); |
856 | sg_init_table(&atmel_port->sg_tx, 1); | 856 | sg_init_table(&atmel_port->sg_tx, 1); |
857 | /* UART circular tx buffer is an aligned page. */ | 857 | /* UART circular tx buffer is an aligned page. */ |
858 | BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK); | 858 | BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf)); |
859 | sg_set_page(&atmel_port->sg_tx, | 859 | sg_set_page(&atmel_port->sg_tx, |
860 | virt_to_page(port->state->xmit.buf), | 860 | virt_to_page(port->state->xmit.buf), |
861 | UART_XMIT_SIZE, | 861 | UART_XMIT_SIZE, |
@@ -1034,10 +1034,10 @@ static int atmel_prepare_rx_dma(struct uart_port *port) | |||
1034 | spin_lock_init(&atmel_port->lock_rx); | 1034 | spin_lock_init(&atmel_port->lock_rx); |
1035 | sg_init_table(&atmel_port->sg_rx, 1); | 1035 | sg_init_table(&atmel_port->sg_rx, 1); |
1036 | /* UART circular rx buffer is an aligned page. */ | 1036 | /* UART circular rx buffer is an aligned page. */ |
1037 | BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK); | 1037 | BUG_ON(!PAGE_ALIGNED(ring->buf)); |
1038 | sg_set_page(&atmel_port->sg_rx, | 1038 | sg_set_page(&atmel_port->sg_rx, |
1039 | virt_to_page(ring->buf), | 1039 | virt_to_page(ring->buf), |
1040 | ATMEL_SERIAL_RINGSIZE, | 1040 | sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE, |
1041 | (int)ring->buf & ~PAGE_MASK); | 1041 | (int)ring->buf & ~PAGE_MASK); |
1042 | nent = dma_map_sg(port->dev, | 1042 | nent = dma_map_sg(port->dev, |
1043 | &atmel_port->sg_rx, | 1043 | &atmel_port->sg_rx, |
@@ -1554,7 +1554,7 @@ static void atmel_tasklet_func(unsigned long data) | |||
1554 | spin_unlock(&port->lock); | 1554 | spin_unlock(&port->lock); |
1555 | } | 1555 | } |
1556 | 1556 | ||
1557 | static int atmel_init_property(struct atmel_uart_port *atmel_port, | 1557 | static void atmel_init_property(struct atmel_uart_port *atmel_port, |
1558 | struct platform_device *pdev) | 1558 | struct platform_device *pdev) |
1559 | { | 1559 | { |
1560 | struct device_node *np = pdev->dev.of_node; | 1560 | struct device_node *np = pdev->dev.of_node; |
@@ -1595,7 +1595,6 @@ static int atmel_init_property(struct atmel_uart_port *atmel_port, | |||
1595 | atmel_port->use_dma_tx = false; | 1595 | atmel_port->use_dma_tx = false; |
1596 | } | 1596 | } |
1597 | 1597 | ||
1598 | return 0; | ||
1599 | } | 1598 | } |
1600 | 1599 | ||
1601 | static void atmel_init_rs485(struct uart_port *port, | 1600 | static void atmel_init_rs485(struct uart_port *port, |
@@ -1777,10 +1776,13 @@ static int atmel_startup(struct uart_port *port) | |||
1777 | if (retval) | 1776 | if (retval) |
1778 | goto free_irq; | 1777 | goto free_irq; |
1779 | 1778 | ||
1779 | tasklet_enable(&atmel_port->tasklet); | ||
1780 | |||
1780 | /* | 1781 | /* |
1781 | * Initialize DMA (if necessary) | 1782 | * Initialize DMA (if necessary) |
1782 | */ | 1783 | */ |
1783 | atmel_init_property(atmel_port, pdev); | 1784 | atmel_init_property(atmel_port, pdev); |
1785 | atmel_set_ops(port); | ||
1784 | 1786 | ||
1785 | if (atmel_port->prepare_rx) { | 1787 | if (atmel_port->prepare_rx) { |
1786 | retval = atmel_port->prepare_rx(port); | 1788 | retval = atmel_port->prepare_rx(port); |
@@ -1879,6 +1881,7 @@ static void atmel_shutdown(struct uart_port *port) | |||
1879 | * Clear out any scheduled tasklets before | 1881 | * Clear out any scheduled tasklets before |
1880 | * we destroy the buffers | 1882 | * we destroy the buffers |
1881 | */ | 1883 | */ |
1884 | tasklet_disable(&atmel_port->tasklet); | ||
1882 | tasklet_kill(&atmel_port->tasklet); | 1885 | tasklet_kill(&atmel_port->tasklet); |
1883 | 1886 | ||
1884 | /* | 1887 | /* |
@@ -2256,8 +2259,8 @@ static int atmel_init_port(struct atmel_uart_port *atmel_port, | |||
2256 | struct uart_port *port = &atmel_port->uart; | 2259 | struct uart_port *port = &atmel_port->uart; |
2257 | struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); | 2260 | struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); |
2258 | 2261 | ||
2259 | if (!atmel_init_property(atmel_port, pdev)) | 2262 | atmel_init_property(atmel_port, pdev); |
2260 | atmel_set_ops(port); | 2263 | atmel_set_ops(port); |
2261 | 2264 | ||
2262 | atmel_init_rs485(port, pdev); | 2265 | atmel_init_rs485(port, pdev); |
2263 | 2266 | ||
@@ -2272,6 +2275,7 @@ static int atmel_init_port(struct atmel_uart_port *atmel_port, | |||
2272 | 2275 | ||
2273 | tasklet_init(&atmel_port->tasklet, atmel_tasklet_func, | 2276 | tasklet_init(&atmel_port->tasklet, atmel_tasklet_func, |
2274 | (unsigned long)port); | 2277 | (unsigned long)port); |
2278 | tasklet_disable(&atmel_port->tasklet); | ||
2275 | 2279 | ||
2276 | memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring)); | 2280 | memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring)); |
2277 | 2281 | ||
@@ -2581,8 +2585,8 @@ static int atmel_init_gpios(struct atmel_uart_port *p, struct device *dev) | |||
2581 | struct gpio_desc *gpiod; | 2585 | struct gpio_desc *gpiod; |
2582 | 2586 | ||
2583 | p->gpios = mctrl_gpio_init(dev, 0); | 2587 | p->gpios = mctrl_gpio_init(dev, 0); |
2584 | if (IS_ERR_OR_NULL(p->gpios)) | 2588 | if (IS_ERR(p->gpios)) |
2585 | return -1; | 2589 | return PTR_ERR(p->gpios); |
2586 | 2590 | ||
2587 | for (i = 0; i < UART_GPIO_MAX; i++) { | 2591 | for (i = 0; i < UART_GPIO_MAX; i++) { |
2588 | gpiod = mctrl_gpio_to_gpiod(p->gpios, i); | 2592 | gpiod = mctrl_gpio_to_gpiod(p->gpios, i); |
@@ -2635,9 +2639,10 @@ static int atmel_serial_probe(struct platform_device *pdev) | |||
2635 | spin_lock_init(&port->lock_suspended); | 2639 | spin_lock_init(&port->lock_suspended); |
2636 | 2640 | ||
2637 | ret = atmel_init_gpios(port, &pdev->dev); | 2641 | ret = atmel_init_gpios(port, &pdev->dev); |
2638 | if (ret < 0) | 2642 | if (ret < 0) { |
2639 | dev_err(&pdev->dev, "%s", | 2643 | dev_err(&pdev->dev, "Failed to initialize GPIOs."); |
2640 | "Failed to initialize GPIOs. The serial port may not work as expected"); | 2644 | goto err; |
2645 | } | ||
2641 | 2646 | ||
2642 | ret = atmel_init_port(port, pdev); | 2647 | ret = atmel_init_port(port, pdev); |
2643 | if (ret) | 2648 | if (ret) |
diff --git a/drivers/tty/serial/bcm63xx_uart.c b/drivers/tty/serial/bcm63xx_uart.c index 01d83df08e3d..681e0f3d5e0e 100644 --- a/drivers/tty/serial/bcm63xx_uart.c +++ b/drivers/tty/serial/bcm63xx_uart.c | |||
@@ -854,7 +854,7 @@ static int bcm_uart_probe(struct platform_device *pdev) | |||
854 | 854 | ||
855 | ret = uart_add_one_port(&bcm_uart_driver, port); | 855 | ret = uart_add_one_port(&bcm_uart_driver, port); |
856 | if (ret) { | 856 | if (ret) { |
857 | ports[pdev->id].membase = 0; | 857 | ports[pdev->id].membase = NULL; |
858 | return ret; | 858 | return ret; |
859 | } | 859 | } |
860 | platform_set_drvdata(pdev, port); | 860 | platform_set_drvdata(pdev, port); |
@@ -868,7 +868,7 @@ static int bcm_uart_remove(struct platform_device *pdev) | |||
868 | port = platform_get_drvdata(pdev); | 868 | port = platform_get_drvdata(pdev); |
869 | uart_remove_one_port(&bcm_uart_driver, port); | 869 | uart_remove_one_port(&bcm_uart_driver, port); |
870 | /* mark port as free */ | 870 | /* mark port as free */ |
871 | ports[pdev->id].membase = 0; | 871 | ports[pdev->id].membase = NULL; |
872 | return 0; | 872 | return 0; |
873 | } | 873 | } |
874 | 874 | ||
diff --git a/drivers/tty/serial/bfin_uart.c b/drivers/tty/serial/bfin_uart.c index 43b3e2c233ff..155781ece050 100644 --- a/drivers/tty/serial/bfin_uart.c +++ b/drivers/tty/serial/bfin_uart.c | |||
@@ -464,6 +464,7 @@ void bfin_serial_rx_dma_timeout(struct bfin_serial_port *uart) | |||
464 | int x_pos, pos; | 464 | int x_pos, pos; |
465 | unsigned long flags; | 465 | unsigned long flags; |
466 | 466 | ||
467 | dma_disable_irq_nosync(uart->rx_dma_channel); | ||
467 | spin_lock_irqsave(&uart->rx_lock, flags); | 468 | spin_lock_irqsave(&uart->rx_lock, flags); |
468 | 469 | ||
469 | /* 2D DMA RX buffer ring is used. Because curr_y_count and | 470 | /* 2D DMA RX buffer ring is used. Because curr_y_count and |
@@ -496,6 +497,7 @@ void bfin_serial_rx_dma_timeout(struct bfin_serial_port *uart) | |||
496 | } | 497 | } |
497 | 498 | ||
498 | spin_unlock_irqrestore(&uart->rx_lock, flags); | 499 | spin_unlock_irqrestore(&uart->rx_lock, flags); |
500 | dma_enable_irq(uart->rx_dma_channel); | ||
499 | 501 | ||
500 | mod_timer(&(uart->rx_dma_timer), jiffies + DMA_RX_FLUSH_JIFFIES); | 502 | mod_timer(&(uart->rx_dma_timer), jiffies + DMA_RX_FLUSH_JIFFIES); |
501 | } | 503 | } |
diff --git a/drivers/tty/serial/clps711x.c b/drivers/tty/serial/clps711x.c index 6e11c275f2ab..d5d2dd7c7917 100644 --- a/drivers/tty/serial/clps711x.c +++ b/drivers/tty/serial/clps711x.c | |||
@@ -501,6 +501,8 @@ static int uart_clps711x_probe(struct platform_device *pdev) | |||
501 | platform_set_drvdata(pdev, s); | 501 | platform_set_drvdata(pdev, s); |
502 | 502 | ||
503 | s->gpios = mctrl_gpio_init(&pdev->dev, 0); | 503 | s->gpios = mctrl_gpio_init(&pdev->dev, 0); |
504 | if (IS_ERR(s->gpios)) | ||
505 | return PTR_ERR(s->gpios); | ||
504 | 506 | ||
505 | ret = uart_add_one_port(&clps711x_uart, &s->port); | 507 | ret = uart_add_one_port(&clps711x_uart, &s->port); |
506 | if (ret) | 508 | if (ret) |
diff --git a/drivers/tty/serial/cpm_uart/Makefile b/drivers/tty/serial/cpm_uart/Makefile index e072724ea754..896a5d57881c 100644 --- a/drivers/tty/serial/cpm_uart/Makefile +++ b/drivers/tty/serial/cpm_uart/Makefile | |||
@@ -6,6 +6,6 @@ obj-$(CONFIG_SERIAL_CPM) += cpm_uart.o | |||
6 | 6 | ||
7 | # Select the correct platform objects. | 7 | # Select the correct platform objects. |
8 | cpm_uart-objs-$(CONFIG_CPM2) += cpm_uart_cpm2.o | 8 | cpm_uart-objs-$(CONFIG_CPM2) += cpm_uart_cpm2.o |
9 | cpm_uart-objs-$(CONFIG_8xx) += cpm_uart_cpm1.o | 9 | cpm_uart-objs-$(CONFIG_CPM1) += cpm_uart_cpm1.o |
10 | 10 | ||
11 | cpm_uart-objs := cpm_uart_core.o $(cpm_uart-objs-y) | 11 | cpm_uart-objs := cpm_uart_core.o $(cpm_uart-objs-y) |
diff --git a/drivers/tty/serial/cpm_uart/cpm_uart.h b/drivers/tty/serial/cpm_uart/cpm_uart.h index cf34d26ff6cd..0ad027b95873 100644 --- a/drivers/tty/serial/cpm_uart/cpm_uart.h +++ b/drivers/tty/serial/cpm_uart/cpm_uart.h | |||
@@ -19,7 +19,7 @@ | |||
19 | 19 | ||
20 | #if defined(CONFIG_CPM2) | 20 | #if defined(CONFIG_CPM2) |
21 | #include "cpm_uart_cpm2.h" | 21 | #include "cpm_uart_cpm2.h" |
22 | #elif defined(CONFIG_8xx) | 22 | #elif defined(CONFIG_CPM1) |
23 | #include "cpm_uart_cpm1.h" | 23 | #include "cpm_uart_cpm1.h" |
24 | #endif | 24 | #endif |
25 | 25 | ||
diff --git a/drivers/tty/serial/cpm_uart/cpm_uart_core.c b/drivers/tty/serial/cpm_uart/cpm_uart_core.c index fddb1fd4d9d3..08431adeacd5 100644 --- a/drivers/tty/serial/cpm_uart/cpm_uart_core.c +++ b/drivers/tty/serial/cpm_uart/cpm_uart_core.c | |||
@@ -1435,7 +1435,7 @@ static int cpm_uart_remove(struct platform_device *ofdev) | |||
1435 | return uart_remove_one_port(&cpm_reg, &pinfo->port); | 1435 | return uart_remove_one_port(&cpm_reg, &pinfo->port); |
1436 | } | 1436 | } |
1437 | 1437 | ||
1438 | static struct of_device_id cpm_uart_match[] = { | 1438 | static const struct of_device_id cpm_uart_match[] = { |
1439 | { | 1439 | { |
1440 | .compatible = "fsl,cpm1-smc-uart", | 1440 | .compatible = "fsl,cpm1-smc-uart", |
1441 | }, | 1441 | }, |
diff --git a/drivers/tty/serial/earlycon.c b/drivers/tty/serial/earlycon.c index 64fe25a4285c..5fdc9f3ecd64 100644 --- a/drivers/tty/serial/earlycon.c +++ b/drivers/tty/serial/earlycon.c | |||
@@ -10,6 +10,9 @@ | |||
10 | * it under the terms of the GNU General Public License version 2 as | 10 | * it under the terms of the GNU General Public License version 2 as |
11 | * published by the Free Software Foundation. | 11 | * published by the Free Software Foundation. |
12 | */ | 12 | */ |
13 | |||
14 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | ||
15 | |||
13 | #include <linux/console.h> | 16 | #include <linux/console.h> |
14 | #include <linux/kernel.h> | 17 | #include <linux/kernel.h> |
15 | #include <linux/init.h> | 18 | #include <linux/init.h> |
@@ -34,6 +37,10 @@ static struct earlycon_device early_console_dev = { | |||
34 | .con = &early_con, | 37 | .con = &early_con, |
35 | }; | 38 | }; |
36 | 39 | ||
40 | extern struct earlycon_id __earlycon_table[]; | ||
41 | static const struct earlycon_id __earlycon_table_sentinel | ||
42 | __used __section(__earlycon_table_end); | ||
43 | |||
37 | static const struct of_device_id __earlycon_of_table_sentinel | 44 | static const struct of_device_id __earlycon_of_table_sentinel |
38 | __used __section(__earlycon_of_table_end); | 45 | __used __section(__earlycon_of_table_end); |
39 | 46 | ||
@@ -54,44 +61,29 @@ static void __iomem * __init earlycon_map(unsigned long paddr, size_t size) | |||
54 | return base; | 61 | return base; |
55 | } | 62 | } |
56 | 63 | ||
57 | static int __init parse_options(struct earlycon_device *device, | 64 | static int __init parse_options(struct earlycon_device *device, char *options) |
58 | char *options) | ||
59 | { | 65 | { |
60 | struct uart_port *port = &device->port; | 66 | struct uart_port *port = &device->port; |
61 | int mmio, mmio32, length; | 67 | int length; |
62 | unsigned long addr; | 68 | unsigned long addr; |
63 | 69 | ||
64 | if (!options) | 70 | if (uart_parse_earlycon(options, &port->iotype, &addr, &options)) |
65 | return -ENODEV; | 71 | return -EINVAL; |
66 | 72 | ||
67 | mmio = !strncmp(options, "mmio,", 5); | 73 | switch (port->iotype) { |
68 | mmio32 = !strncmp(options, "mmio32,", 7); | 74 | case UPIO_MEM32: |
69 | if (mmio || mmio32) { | 75 | port->regshift = 2; /* fall-through */ |
70 | port->iotype = (mmio ? UPIO_MEM : UPIO_MEM32); | 76 | case UPIO_MEM: |
71 | options += mmio ? 5 : 7; | ||
72 | addr = simple_strtoul(options, NULL, 0); | ||
73 | port->mapbase = addr; | 77 | port->mapbase = addr; |
74 | if (mmio32) | 78 | break; |
75 | port->regshift = 2; | 79 | case UPIO_PORT: |
76 | } else if (!strncmp(options, "io,", 3)) { | ||
77 | port->iotype = UPIO_PORT; | ||
78 | options += 3; | ||
79 | addr = simple_strtoul(options, NULL, 0); | ||
80 | port->iobase = addr; | 80 | port->iobase = addr; |
81 | mmio = 0; | 81 | break; |
82 | } else if (!strncmp(options, "0x", 2)) { | 82 | default: |
83 | port->iotype = UPIO_MEM; | ||
84 | addr = simple_strtoul(options, NULL, 0); | ||
85 | port->mapbase = addr; | ||
86 | } else { | ||
87 | return -EINVAL; | 83 | return -EINVAL; |
88 | } | 84 | } |
89 | 85 | ||
90 | port->uartclk = BASE_BAUD * 16; | ||
91 | |||
92 | options = strchr(options, ','); | ||
93 | if (options) { | 86 | if (options) { |
94 | options++; | ||
95 | device->baud = simple_strtoul(options, NULL, 0); | 87 | device->baud = simple_strtoul(options, NULL, 0); |
96 | length = min(strcspn(options, " ") + 1, | 88 | length = min(strcspn(options, " ") + 1, |
97 | (size_t)(sizeof(device->options))); | 89 | (size_t)(sizeof(device->options))); |
@@ -100,7 +92,7 @@ static int __init parse_options(struct earlycon_device *device, | |||
100 | 92 | ||
101 | if (port->iotype == UPIO_MEM || port->iotype == UPIO_MEM32) | 93 | if (port->iotype == UPIO_MEM || port->iotype == UPIO_MEM32) |
102 | pr_info("Early serial console at MMIO%s 0x%llx (options '%s')\n", | 94 | pr_info("Early serial console at MMIO%s 0x%llx (options '%s')\n", |
103 | mmio32 ? "32" : "", | 95 | (port->iotype == UPIO_MEM32) ? "32" : "", |
104 | (unsigned long long)port->mapbase, | 96 | (unsigned long long)port->mapbase, |
105 | device->options); | 97 | device->options); |
106 | else | 98 | else |
@@ -111,34 +103,21 @@ static int __init parse_options(struct earlycon_device *device, | |||
111 | return 0; | 103 | return 0; |
112 | } | 104 | } |
113 | 105 | ||
114 | int __init setup_earlycon(char *buf, const char *match, | 106 | static int __init register_earlycon(char *buf, const struct earlycon_id *match) |
115 | int (*setup)(struct earlycon_device *, const char *)) | ||
116 | { | 107 | { |
117 | int err; | 108 | int err; |
118 | size_t len; | ||
119 | struct uart_port *port = &early_console_dev.port; | 109 | struct uart_port *port = &early_console_dev.port; |
120 | 110 | ||
121 | if (!buf || !match || !setup) | ||
122 | return 0; | ||
123 | |||
124 | len = strlen(match); | ||
125 | if (strncmp(buf, match, len)) | ||
126 | return 0; | ||
127 | if (buf[len] && (buf[len] != ',')) | ||
128 | return 0; | ||
129 | |||
130 | buf += len + 1; | ||
131 | |||
132 | err = parse_options(&early_console_dev, buf); | ||
133 | /* On parsing error, pass the options buf to the setup function */ | 111 | /* On parsing error, pass the options buf to the setup function */ |
134 | if (!err) | 112 | if (buf && !parse_options(&early_console_dev, buf)) |
135 | buf = NULL; | 113 | buf = NULL; |
136 | 114 | ||
115 | port->uartclk = BASE_BAUD * 16; | ||
137 | if (port->mapbase) | 116 | if (port->mapbase) |
138 | port->membase = earlycon_map(port->mapbase, 64); | 117 | port->membase = earlycon_map(port->mapbase, 64); |
139 | 118 | ||
140 | early_console_dev.con->data = &early_console_dev; | 119 | early_console_dev.con->data = &early_console_dev; |
141 | err = setup(&early_console_dev, buf); | 120 | err = match->setup(&early_console_dev, buf); |
142 | if (err < 0) | 121 | if (err < 0) |
143 | return err; | 122 | return err; |
144 | if (!early_console_dev.con->write) | 123 | if (!early_console_dev.con->write) |
@@ -148,6 +127,77 @@ int __init setup_earlycon(char *buf, const char *match, | |||
148 | return 0; | 127 | return 0; |
149 | } | 128 | } |
150 | 129 | ||
130 | /** | ||
131 | * setup_earlycon - match and register earlycon console | ||
132 | * @buf: earlycon param string | ||
133 | * | ||
134 | * Registers the earlycon console matching the earlycon specified | ||
135 | * in the param string @buf. Acceptable param strings are of the form | ||
136 | * <name>,io|mmio|mmio32,<addr>,<options> | ||
137 | * <name>,0x<addr>,<options> | ||
138 | * <name>,<options> | ||
139 | * <name> | ||
140 | * | ||
141 | * Only for the third form does the earlycon setup() method receive the | ||
142 | * <options> string in the 'options' parameter; all other forms set | ||
143 | * the parameter to NULL. | ||
144 | * | ||
145 | * Returns 0 if an attempt to register the earlycon was made, | ||
146 | * otherwise negative error code | ||
147 | */ | ||
148 | int __init setup_earlycon(char *buf) | ||
149 | { | ||
150 | const struct earlycon_id *match; | ||
151 | |||
152 | if (!buf || !buf[0]) | ||
153 | return -EINVAL; | ||
154 | |||
155 | if (early_con.flags & CON_ENABLED) | ||
156 | return -EALREADY; | ||
157 | |||
158 | for (match = __earlycon_table; match->name[0]; match++) { | ||
159 | size_t len = strlen(match->name); | ||
160 | |||
161 | if (strncmp(buf, match->name, len)) | ||
162 | continue; | ||
163 | |||
164 | if (buf[len]) { | ||
165 | if (buf[len] != ',') | ||
166 | continue; | ||
167 | buf += len + 1; | ||
168 | } else | ||
169 | buf = NULL; | ||
170 | |||
171 | return register_earlycon(buf, match); | ||
172 | } | ||
173 | |||
174 | return -ENOENT; | ||
175 | } | ||
176 | |||
177 | /* early_param wrapper for setup_earlycon() */ | ||
178 | static int __init param_setup_earlycon(char *buf) | ||
179 | { | ||
180 | int err; | ||
181 | |||
182 | /* | ||
183 | * Just 'earlycon' is a valid param for devicetree earlycons; | ||
184 | * don't generate a warning from parse_early_params() in that case | ||
185 | */ | ||
186 | if (!buf || !buf[0]) | ||
187 | return 0; | ||
188 | |||
189 | err = setup_earlycon(buf); | ||
190 | if (err == -ENOENT) { | ||
191 | pr_warn("no match for %s\n", buf); | ||
192 | err = 0; | ||
193 | } else if (err == -EALREADY) { | ||
194 | pr_warn("already registered\n"); | ||
195 | err = 0; | ||
196 | } | ||
197 | return err; | ||
198 | } | ||
199 | early_param("earlycon", param_setup_earlycon); | ||
200 | |||
151 | int __init of_setup_earlycon(unsigned long addr, | 201 | int __init of_setup_earlycon(unsigned long addr, |
152 | int (*setup)(struct earlycon_device *, const char *)) | 202 | int (*setup)(struct earlycon_device *, const char *)) |
153 | { | 203 | { |
diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c index 3ad1458bfeb0..08ce76f4f261 100644 --- a/drivers/tty/serial/fsl_lpuart.c +++ b/drivers/tty/serial/fsl_lpuart.c | |||
@@ -257,7 +257,7 @@ struct lpuart_port { | |||
257 | struct timer_list lpuart_timer; | 257 | struct timer_list lpuart_timer; |
258 | }; | 258 | }; |
259 | 259 | ||
260 | static struct of_device_id lpuart_dt_ids[] = { | 260 | static const struct of_device_id lpuart_dt_ids[] = { |
261 | { | 261 | { |
262 | .compatible = "fsl,vf610-lpuart", | 262 | .compatible = "fsl,vf610-lpuart", |
263 | }, | 263 | }, |
diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c index 0eb29b1c47ac..c8cfa0637128 100644 --- a/drivers/tty/serial/imx.c +++ b/drivers/tty/serial/imx.c | |||
@@ -1,13 +1,10 @@ | |||
1 | /* | 1 | /* |
2 | * Driver for Motorola IMX serial ports | 2 | * Driver for Motorola/Freescale IMX serial ports |
3 | * | 3 | * |
4 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | 4 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. |
5 | * | 5 | * |
6 | * Author: Sascha Hauer <sascha@saschahauer.de> | 6 | * Author: Sascha Hauer <sascha@saschahauer.de> |
7 | * Copyright (C) 2004 Pengutronix | 7 | * Copyright (C) 2004 Pengutronix |
8 | * | ||
9 | * Copyright (C) 2009 emlix GmbH | ||
10 | * Author: Fabian Godehardt (added IrDA support for iMX) | ||
11 | * | 8 | * |
12 | * This program is free software; you can redistribute it and/or modify | 9 | * This program is free software; you can redistribute it and/or modify |
13 | * it under the terms of the GNU General Public License as published by | 10 | * it under the terms of the GNU General Public License as published by |
@@ -18,13 +15,6 @@ | |||
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
20 | * GNU General Public License for more details. | 17 | * GNU General Public License for more details. |
21 | * | ||
22 | * You should have received a copy of the GNU General Public License | ||
23 | * along with this program; if not, write to the Free Software | ||
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
25 | * | ||
26 | * [29-Mar-2005] Mike Lee | ||
27 | * Added hardware handshake | ||
28 | */ | 18 | */ |
29 | 19 | ||
30 | #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | 20 | #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
@@ -189,7 +179,7 @@ | |||
189 | 179 | ||
190 | #define UART_NR 8 | 180 | #define UART_NR 8 |
191 | 181 | ||
192 | /* i.mx21 type uart runs on all i.mx except i.mx1 */ | 182 | /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */ |
193 | enum imx_uart_type { | 183 | enum imx_uart_type { |
194 | IMX1_UART, | 184 | IMX1_UART, |
195 | IMX21_UART, | 185 | IMX21_UART, |
@@ -206,10 +196,8 @@ struct imx_port { | |||
206 | struct uart_port port; | 196 | struct uart_port port; |
207 | struct timer_list timer; | 197 | struct timer_list timer; |
208 | unsigned int old_status; | 198 | unsigned int old_status; |
209 | int txirq, rxirq, rtsirq; | ||
210 | unsigned int have_rtscts:1; | 199 | unsigned int have_rtscts:1; |
211 | unsigned int dte_mode:1; | 200 | unsigned int dte_mode:1; |
212 | unsigned int use_irda:1; | ||
213 | unsigned int irda_inv_rx:1; | 201 | unsigned int irda_inv_rx:1; |
214 | unsigned int irda_inv_tx:1; | 202 | unsigned int irda_inv_tx:1; |
215 | unsigned short trcv_delay; /* transceiver delay */ | 203 | unsigned short trcv_delay; /* transceiver delay */ |
@@ -236,12 +224,6 @@ struct imx_port_ucrs { | |||
236 | unsigned int ucr3; | 224 | unsigned int ucr3; |
237 | }; | 225 | }; |
238 | 226 | ||
239 | #ifdef CONFIG_IRDA | ||
240 | #define USE_IRDA(sport) ((sport)->use_irda) | ||
241 | #else | ||
242 | #define USE_IRDA(sport) (0) | ||
243 | #endif | ||
244 | |||
245 | static struct imx_uart_data imx_uart_devdata[] = { | 227 | static struct imx_uart_data imx_uart_devdata[] = { |
246 | [IMX1_UART] = { | 228 | [IMX1_UART] = { |
247 | .uts_reg = IMX1_UTS, | 229 | .uts_reg = IMX1_UTS, |
@@ -273,7 +255,7 @@ static struct platform_device_id imx_uart_devtype[] = { | |||
273 | }; | 255 | }; |
274 | MODULE_DEVICE_TABLE(platform, imx_uart_devtype); | 256 | MODULE_DEVICE_TABLE(platform, imx_uart_devtype); |
275 | 257 | ||
276 | static struct of_device_id imx_uart_dt_ids[] = { | 258 | static const struct of_device_id imx_uart_dt_ids[] = { |
277 | { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], }, | 259 | { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], }, |
278 | { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], }, | 260 | { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], }, |
279 | { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], }, | 261 | { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], }, |
@@ -376,48 +358,6 @@ static void imx_stop_tx(struct uart_port *port) | |||
376 | struct imx_port *sport = (struct imx_port *)port; | 358 | struct imx_port *sport = (struct imx_port *)port; |
377 | unsigned long temp; | 359 | unsigned long temp; |
378 | 360 | ||
379 | if (USE_IRDA(sport)) { | ||
380 | /* half duplex - wait for end of transmission */ | ||
381 | int n = 256; | ||
382 | while ((--n > 0) && | ||
383 | !(readl(sport->port.membase + USR2) & USR2_TXDC)) { | ||
384 | udelay(5); | ||
385 | barrier(); | ||
386 | } | ||
387 | /* | ||
388 | * irda transceiver - wait a bit more to avoid | ||
389 | * cutoff, hardware dependent | ||
390 | */ | ||
391 | udelay(sport->trcv_delay); | ||
392 | |||
393 | /* | ||
394 | * half duplex - reactivate receive mode, | ||
395 | * flush receive pipe echo crap | ||
396 | */ | ||
397 | if (readl(sport->port.membase + USR2) & USR2_TXDC) { | ||
398 | temp = readl(sport->port.membase + UCR1); | ||
399 | temp &= ~(UCR1_TXMPTYEN | UCR1_TRDYEN); | ||
400 | writel(temp, sport->port.membase + UCR1); | ||
401 | |||
402 | temp = readl(sport->port.membase + UCR4); | ||
403 | temp &= ~(UCR4_TCEN); | ||
404 | writel(temp, sport->port.membase + UCR4); | ||
405 | |||
406 | while (readl(sport->port.membase + URXD0) & | ||
407 | URXD_CHARRDY) | ||
408 | barrier(); | ||
409 | |||
410 | temp = readl(sport->port.membase + UCR1); | ||
411 | temp |= UCR1_RRDYEN; | ||
412 | writel(temp, sport->port.membase + UCR1); | ||
413 | |||
414 | temp = readl(sport->port.membase + UCR4); | ||
415 | temp |= UCR4_DREN; | ||
416 | writel(temp, sport->port.membase + UCR4); | ||
417 | } | ||
418 | return; | ||
419 | } | ||
420 | |||
421 | /* | 361 | /* |
422 | * We are maybe in the SMP context, so if the DMA TX thread is running | 362 | * We are maybe in the SMP context, so if the DMA TX thread is running |
423 | * on other cpu, we have to wait for it to finish. | 363 | * on other cpu, we have to wait for it to finish. |
@@ -425,8 +365,23 @@ static void imx_stop_tx(struct uart_port *port) | |||
425 | if (sport->dma_is_enabled && sport->dma_is_txing) | 365 | if (sport->dma_is_enabled && sport->dma_is_txing) |
426 | return; | 366 | return; |
427 | 367 | ||
428 | temp = readl(sport->port.membase + UCR1); | 368 | temp = readl(port->membase + UCR1); |
429 | writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1); | 369 | writel(temp & ~UCR1_TXMPTYEN, port->membase + UCR1); |
370 | |||
371 | /* in rs485 mode disable transmitter if shifter is empty */ | ||
372 | if (port->rs485.flags & SER_RS485_ENABLED && | ||
373 | readl(port->membase + USR2) & USR2_TXDC) { | ||
374 | temp = readl(port->membase + UCR2); | ||
375 | if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) | ||
376 | temp &= ~UCR2_CTS; | ||
377 | else | ||
378 | temp |= UCR2_CTS; | ||
379 | writel(temp, port->membase + UCR2); | ||
380 | |||
381 | temp = readl(port->membase + UCR4); | ||
382 | temp &= ~UCR4_TCEN; | ||
383 | writel(temp, port->membase + UCR4); | ||
384 | } | ||
430 | } | 385 | } |
431 | 386 | ||
432 | /* | 387 | /* |
@@ -620,15 +575,18 @@ static void imx_start_tx(struct uart_port *port) | |||
620 | struct imx_port *sport = (struct imx_port *)port; | 575 | struct imx_port *sport = (struct imx_port *)port; |
621 | unsigned long temp; | 576 | unsigned long temp; |
622 | 577 | ||
623 | if (USE_IRDA(sport)) { | 578 | if (port->rs485.flags & SER_RS485_ENABLED) { |
624 | /* half duplex in IrDA mode; have to disable receive mode */ | 579 | /* enable transmitter and shifter empty irq */ |
625 | temp = readl(sport->port.membase + UCR4); | 580 | temp = readl(port->membase + UCR2); |
626 | temp &= ~(UCR4_DREN); | 581 | if (port->rs485.flags & SER_RS485_RTS_ON_SEND) |
627 | writel(temp, sport->port.membase + UCR4); | 582 | temp &= ~UCR2_CTS; |
583 | else | ||
584 | temp |= UCR2_CTS; | ||
585 | writel(temp, port->membase + UCR2); | ||
628 | 586 | ||
629 | temp = readl(sport->port.membase + UCR1); | 587 | temp = readl(port->membase + UCR4); |
630 | temp &= ~(UCR1_RRDYEN); | 588 | temp |= UCR4_TCEN; |
631 | writel(temp, sport->port.membase + UCR1); | 589 | writel(temp, port->membase + UCR4); |
632 | } | 590 | } |
633 | 591 | ||
634 | if (!sport->dma_is_enabled) { | 592 | if (!sport->dma_is_enabled) { |
@@ -636,16 +594,6 @@ static void imx_start_tx(struct uart_port *port) | |||
636 | writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1); | 594 | writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1); |
637 | } | 595 | } |
638 | 596 | ||
639 | if (USE_IRDA(sport)) { | ||
640 | temp = readl(sport->port.membase + UCR1); | ||
641 | temp |= UCR1_TRDYEN; | ||
642 | writel(temp, sport->port.membase + UCR1); | ||
643 | |||
644 | temp = readl(sport->port.membase + UCR4); | ||
645 | temp |= UCR4_TCEN; | ||
646 | writel(temp, sport->port.membase + UCR4); | ||
647 | } | ||
648 | |||
649 | if (sport->dma_is_enabled) { | 597 | if (sport->dma_is_enabled) { |
650 | if (sport->port.x_char) { | 598 | if (sport->port.x_char) { |
651 | /* We have X-char to send, so enable TX IRQ and | 599 | /* We have X-char to send, so enable TX IRQ and |
@@ -796,6 +744,7 @@ static irqreturn_t imx_int(int irq, void *dev_id) | |||
796 | unsigned int sts2; | 744 | unsigned int sts2; |
797 | 745 | ||
798 | sts = readl(sport->port.membase + USR1); | 746 | sts = readl(sport->port.membase + USR1); |
747 | sts2 = readl(sport->port.membase + USR2); | ||
799 | 748 | ||
800 | if (sts & USR1_RRDY) { | 749 | if (sts & USR1_RRDY) { |
801 | if (sport->dma_is_enabled) | 750 | if (sport->dma_is_enabled) |
@@ -804,8 +753,10 @@ static irqreturn_t imx_int(int irq, void *dev_id) | |||
804 | imx_rxint(irq, dev_id); | 753 | imx_rxint(irq, dev_id); |
805 | } | 754 | } |
806 | 755 | ||
807 | if (sts & USR1_TRDY && | 756 | if ((sts & USR1_TRDY && |
808 | readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) | 757 | readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) || |
758 | (sts2 & USR2_TXDC && | ||
759 | readl(sport->port.membase + UCR4) & UCR4_TCEN)) | ||
809 | imx_txint(irq, dev_id); | 760 | imx_txint(irq, dev_id); |
810 | 761 | ||
811 | if (sts & USR1_RTSD) | 762 | if (sts & USR1_RTSD) |
@@ -814,11 +765,10 @@ static irqreturn_t imx_int(int irq, void *dev_id) | |||
814 | if (sts & USR1_AWAKE) | 765 | if (sts & USR1_AWAKE) |
815 | writel(USR1_AWAKE, sport->port.membase + USR1); | 766 | writel(USR1_AWAKE, sport->port.membase + USR1); |
816 | 767 | ||
817 | sts2 = readl(sport->port.membase + USR2); | ||
818 | if (sts2 & USR2_ORE) { | 768 | if (sts2 & USR2_ORE) { |
819 | dev_err(sport->port.dev, "Rx FIFO overrun\n"); | 769 | dev_err(sport->port.dev, "Rx FIFO overrun\n"); |
820 | sport->port.icount.overrun++; | 770 | sport->port.icount.overrun++; |
821 | writel(sts2 | USR2_ORE, sport->port.membase + USR2); | 771 | writel(USR2_ORE, sport->port.membase + USR2); |
822 | } | 772 | } |
823 | 773 | ||
824 | return IRQ_HANDLED; | 774 | return IRQ_HANDLED; |
@@ -866,11 +816,13 @@ static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl) | |||
866 | struct imx_port *sport = (struct imx_port *)port; | 816 | struct imx_port *sport = (struct imx_port *)port; |
867 | unsigned long temp; | 817 | unsigned long temp; |
868 | 818 | ||
869 | temp = readl(sport->port.membase + UCR2) & ~(UCR2_CTS | UCR2_CTSC); | 819 | if (!(port->rs485.flags & SER_RS485_ENABLED)) { |
870 | if (mctrl & TIOCM_RTS) | 820 | temp = readl(sport->port.membase + UCR2); |
871 | temp |= UCR2_CTS | UCR2_CTSC; | 821 | temp &= ~(UCR2_CTS | UCR2_CTSC); |
872 | 822 | if (mctrl & TIOCM_RTS) | |
873 | writel(temp, sport->port.membase + UCR2); | 823 | temp |= UCR2_CTS | UCR2_CTSC; |
824 | writel(temp, sport->port.membase + UCR2); | ||
825 | } | ||
874 | 826 | ||
875 | temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP; | 827 | temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP; |
876 | if (mctrl & TIOCM_LOOP) | 828 | if (mctrl & TIOCM_LOOP) |
@@ -1156,9 +1108,6 @@ static int imx_startup(struct uart_port *port) | |||
1156 | */ | 1108 | */ |
1157 | temp = readl(sport->port.membase + UCR4); | 1109 | temp = readl(sport->port.membase + UCR4); |
1158 | 1110 | ||
1159 | if (USE_IRDA(sport)) | ||
1160 | temp |= UCR4_IRSC; | ||
1161 | |||
1162 | /* set the trigger level for CTS */ | 1111 | /* set the trigger level for CTS */ |
1163 | temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF); | 1112 | temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF); |
1164 | temp |= CTSTL << UCR4_CTSTL_SHF; | 1113 | temp |= CTSTL << UCR4_CTSTL_SHF; |
@@ -1181,10 +1130,12 @@ static int imx_startup(struct uart_port *port) | |||
1181 | imx_uart_dma_init(sport); | 1130 | imx_uart_dma_init(sport); |
1182 | 1131 | ||
1183 | spin_lock_irqsave(&sport->port.lock, flags); | 1132 | spin_lock_irqsave(&sport->port.lock, flags); |
1133 | |||
1184 | /* | 1134 | /* |
1185 | * Finally, clear and enable interrupts | 1135 | * Finally, clear and enable interrupts |
1186 | */ | 1136 | */ |
1187 | writel(USR1_RTSD, sport->port.membase + USR1); | 1137 | writel(USR1_RTSD, sport->port.membase + USR1); |
1138 | writel(USR2_ORE, sport->port.membase + USR2); | ||
1188 | 1139 | ||
1189 | if (sport->dma_is_inited && !sport->dma_is_enabled) | 1140 | if (sport->dma_is_inited && !sport->dma_is_enabled) |
1190 | imx_enable_dma(sport); | 1141 | imx_enable_dma(sport); |
@@ -1192,17 +1143,8 @@ static int imx_startup(struct uart_port *port) | |||
1192 | temp = readl(sport->port.membase + UCR1); | 1143 | temp = readl(sport->port.membase + UCR1); |
1193 | temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN; | 1144 | temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN; |
1194 | 1145 | ||
1195 | if (USE_IRDA(sport)) { | ||
1196 | temp |= UCR1_IREN; | ||
1197 | temp &= ~(UCR1_RTSDEN); | ||
1198 | } | ||
1199 | |||
1200 | writel(temp, sport->port.membase + UCR1); | 1146 | writel(temp, sport->port.membase + UCR1); |
1201 | 1147 | ||
1202 | /* Clear any pending ORE flag before enabling interrupt */ | ||
1203 | temp = readl(sport->port.membase + USR2); | ||
1204 | writel(temp | USR2_ORE, sport->port.membase + USR2); | ||
1205 | |||
1206 | temp = readl(sport->port.membase + UCR4); | 1148 | temp = readl(sport->port.membase + UCR4); |
1207 | temp |= UCR4_OREN; | 1149 | temp |= UCR4_OREN; |
1208 | writel(temp, sport->port.membase + UCR4); | 1150 | writel(temp, sport->port.membase + UCR4); |
@@ -1219,38 +1161,12 @@ static int imx_startup(struct uart_port *port) | |||
1219 | writel(temp, sport->port.membase + UCR3); | 1161 | writel(temp, sport->port.membase + UCR3); |
1220 | } | 1162 | } |
1221 | 1163 | ||
1222 | if (USE_IRDA(sport)) { | ||
1223 | temp = readl(sport->port.membase + UCR4); | ||
1224 | if (sport->irda_inv_rx) | ||
1225 | temp |= UCR4_INVR; | ||
1226 | else | ||
1227 | temp &= ~(UCR4_INVR); | ||
1228 | writel(temp | UCR4_DREN, sport->port.membase + UCR4); | ||
1229 | |||
1230 | temp = readl(sport->port.membase + UCR3); | ||
1231 | if (sport->irda_inv_tx) | ||
1232 | temp |= UCR3_INVT; | ||
1233 | else | ||
1234 | temp &= ~(UCR3_INVT); | ||
1235 | writel(temp, sport->port.membase + UCR3); | ||
1236 | } | ||
1237 | |||
1238 | /* | 1164 | /* |
1239 | * Enable modem status interrupts | 1165 | * Enable modem status interrupts |
1240 | */ | 1166 | */ |
1241 | imx_enable_ms(&sport->port); | 1167 | imx_enable_ms(&sport->port); |
1242 | spin_unlock_irqrestore(&sport->port.lock, flags); | 1168 | spin_unlock_irqrestore(&sport->port.lock, flags); |
1243 | 1169 | ||
1244 | if (USE_IRDA(sport)) { | ||
1245 | struct imxuart_platform_data *pdata; | ||
1246 | pdata = dev_get_platdata(sport->port.dev); | ||
1247 | sport->irda_inv_rx = pdata->irda_inv_rx; | ||
1248 | sport->irda_inv_tx = pdata->irda_inv_tx; | ||
1249 | sport->trcv_delay = pdata->transceiver_delay; | ||
1250 | if (pdata->irda_enable) | ||
1251 | pdata->irda_enable(1); | ||
1252 | } | ||
1253 | |||
1254 | return 0; | 1170 | return 0; |
1255 | } | 1171 | } |
1256 | 1172 | ||
@@ -1286,13 +1202,6 @@ static void imx_shutdown(struct uart_port *port) | |||
1286 | writel(temp, sport->port.membase + UCR2); | 1202 | writel(temp, sport->port.membase + UCR2); |
1287 | spin_unlock_irqrestore(&sport->port.lock, flags); | 1203 | spin_unlock_irqrestore(&sport->port.lock, flags); |
1288 | 1204 | ||
1289 | if (USE_IRDA(sport)) { | ||
1290 | struct imxuart_platform_data *pdata; | ||
1291 | pdata = dev_get_platdata(sport->port.dev); | ||
1292 | if (pdata->irda_enable) | ||
1293 | pdata->irda_enable(0); | ||
1294 | } | ||
1295 | |||
1296 | /* | 1205 | /* |
1297 | * Stop our timer. | 1206 | * Stop our timer. |
1298 | */ | 1207 | */ |
@@ -1305,8 +1214,6 @@ static void imx_shutdown(struct uart_port *port) | |||
1305 | spin_lock_irqsave(&sport->port.lock, flags); | 1214 | spin_lock_irqsave(&sport->port.lock, flags); |
1306 | temp = readl(sport->port.membase + UCR1); | 1215 | temp = readl(sport->port.membase + UCR1); |
1307 | temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN); | 1216 | temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN); |
1308 | if (USE_IRDA(sport)) | ||
1309 | temp &= ~(UCR1_IREN); | ||
1310 | 1217 | ||
1311 | writel(temp, sport->port.membase + UCR1); | 1218 | writel(temp, sport->port.membase + UCR1); |
1312 | spin_unlock_irqrestore(&sport->port.lock, flags); | 1219 | spin_unlock_irqrestore(&sport->port.lock, flags); |
@@ -1320,7 +1227,7 @@ static void imx_flush_buffer(struct uart_port *port) | |||
1320 | struct imx_port *sport = (struct imx_port *)port; | 1227 | struct imx_port *sport = (struct imx_port *)port; |
1321 | struct scatterlist *sgl = &sport->tx_sgl[0]; | 1228 | struct scatterlist *sgl = &sport->tx_sgl[0]; |
1322 | unsigned long temp; | 1229 | unsigned long temp; |
1323 | int i = 100, ubir, ubmr, ubrc, uts; | 1230 | int i = 100, ubir, ubmr, uts; |
1324 | 1231 | ||
1325 | if (!sport->dma_chan_tx) | 1232 | if (!sport->dma_chan_tx) |
1326 | return; | 1233 | return; |
@@ -1345,7 +1252,6 @@ static void imx_flush_buffer(struct uart_port *port) | |||
1345 | */ | 1252 | */ |
1346 | ubir = readl(sport->port.membase + UBIR); | 1253 | ubir = readl(sport->port.membase + UBIR); |
1347 | ubmr = readl(sport->port.membase + UBMR); | 1254 | ubmr = readl(sport->port.membase + UBMR); |
1348 | ubrc = readl(sport->port.membase + UBRC); | ||
1349 | uts = readl(sport->port.membase + IMX21_UTS); | 1255 | uts = readl(sport->port.membase + IMX21_UTS); |
1350 | 1256 | ||
1351 | temp = readl(sport->port.membase + UCR2); | 1257 | temp = readl(sport->port.membase + UCR2); |
@@ -1358,7 +1264,6 @@ static void imx_flush_buffer(struct uart_port *port) | |||
1358 | /* Restore the registers */ | 1264 | /* Restore the registers */ |
1359 | writel(ubir, sport->port.membase + UBIR); | 1265 | writel(ubir, sport->port.membase + UBIR); |
1360 | writel(ubmr, sport->port.membase + UBMR); | 1266 | writel(ubmr, sport->port.membase + UBMR); |
1361 | writel(ubrc, sport->port.membase + UBRC); | ||
1362 | writel(uts, sport->port.membase + IMX21_UTS); | 1267 | writel(uts, sport->port.membase + IMX21_UTS); |
1363 | } | 1268 | } |
1364 | 1269 | ||
@@ -1375,15 +1280,6 @@ imx_set_termios(struct uart_port *port, struct ktermios *termios, | |||
1375 | uint64_t tdiv64; | 1280 | uint64_t tdiv64; |
1376 | 1281 | ||
1377 | /* | 1282 | /* |
1378 | * If we don't support modem control lines, don't allow | ||
1379 | * these to be set. | ||
1380 | */ | ||
1381 | if (0) { | ||
1382 | termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR); | ||
1383 | termios->c_cflag |= CLOCAL; | ||
1384 | } | ||
1385 | |||
1386 | /* | ||
1387 | * We only support CS7 and CS8. | 1283 | * We only support CS7 and CS8. |
1388 | */ | 1284 | */ |
1389 | while ((termios->c_cflag & CSIZE) != CS7 && | 1285 | while ((termios->c_cflag & CSIZE) != CS7 && |
@@ -1401,11 +1297,26 @@ imx_set_termios(struct uart_port *port, struct ktermios *termios, | |||
1401 | if (termios->c_cflag & CRTSCTS) { | 1297 | if (termios->c_cflag & CRTSCTS) { |
1402 | if (sport->have_rtscts) { | 1298 | if (sport->have_rtscts) { |
1403 | ucr2 &= ~UCR2_IRTS; | 1299 | ucr2 &= ~UCR2_IRTS; |
1404 | ucr2 |= UCR2_CTSC; | 1300 | |
1301 | if (port->rs485.flags & SER_RS485_ENABLED) { | ||
1302 | /* | ||
1303 | * RTS is mandatory for rs485 operation, so keep | ||
1304 | * it under manual control and keep transmitter | ||
1305 | * disabled. | ||
1306 | */ | ||
1307 | if (!(port->rs485.flags & | ||
1308 | SER_RS485_RTS_AFTER_SEND)) | ||
1309 | ucr2 |= UCR2_CTS; | ||
1310 | } else { | ||
1311 | ucr2 |= UCR2_CTSC; | ||
1312 | } | ||
1405 | } else { | 1313 | } else { |
1406 | termios->c_cflag &= ~CRTSCTS; | 1314 | termios->c_cflag &= ~CRTSCTS; |
1407 | } | 1315 | } |
1408 | } | 1316 | } else if (port->rs485.flags & SER_RS485_ENABLED) |
1317 | /* disable transmitter */ | ||
1318 | if (!(port->rs485.flags & SER_RS485_RTS_AFTER_SEND)) | ||
1319 | ucr2 |= UCR2_CTS; | ||
1409 | 1320 | ||
1410 | if (termios->c_cflag & CSTOPB) | 1321 | if (termios->c_cflag & CSTOPB) |
1411 | ucr2 |= UCR2_STPB; | 1322 | ucr2 |= UCR2_STPB; |
@@ -1471,24 +1382,16 @@ imx_set_termios(struct uart_port *port, struct ktermios *termios, | |||
1471 | sport->port.membase + UCR2); | 1382 | sport->port.membase + UCR2); |
1472 | old_txrxen &= (UCR2_TXEN | UCR2_RXEN); | 1383 | old_txrxen &= (UCR2_TXEN | UCR2_RXEN); |
1473 | 1384 | ||
1474 | if (USE_IRDA(sport)) { | 1385 | /* custom-baudrate handling */ |
1475 | /* | 1386 | div = sport->port.uartclk / (baud * 16); |
1476 | * use maximum available submodule frequency to | 1387 | if (baud == 38400 && quot != div) |
1477 | * avoid missing short pulses due to low sampling rate | 1388 | baud = sport->port.uartclk / (quot * 16); |
1478 | */ | 1389 | |
1390 | div = sport->port.uartclk / (baud * 16); | ||
1391 | if (div > 7) | ||
1392 | div = 7; | ||
1393 | if (!div) | ||
1479 | div = 1; | 1394 | div = 1; |
1480 | } else { | ||
1481 | /* custom-baudrate handling */ | ||
1482 | div = sport->port.uartclk / (baud * 16); | ||
1483 | if (baud == 38400 && quot != div) | ||
1484 | baud = sport->port.uartclk / (quot * 16); | ||
1485 | |||
1486 | div = sport->port.uartclk / (baud * 16); | ||
1487 | if (div > 7) | ||
1488 | div = 7; | ||
1489 | if (!div) | ||
1490 | div = 1; | ||
1491 | } | ||
1492 | 1395 | ||
1493 | rational_best_approximation(16 * div * baud, sport->port.uartclk, | 1396 | rational_best_approximation(16 * div * baud, sport->port.uartclk, |
1494 | 1 << 16, 1 << 16, &num, &denom); | 1397 | 1 << 16, 1 << 16, &num, &denom); |
@@ -1635,6 +1538,38 @@ static void imx_poll_put_char(struct uart_port *port, unsigned char c) | |||
1635 | } | 1538 | } |
1636 | #endif | 1539 | #endif |
1637 | 1540 | ||
1541 | static int imx_rs485_config(struct uart_port *port, | ||
1542 | struct serial_rs485 *rs485conf) | ||
1543 | { | ||
1544 | struct imx_port *sport = (struct imx_port *)port; | ||
1545 | |||
1546 | /* unimplemented */ | ||
1547 | rs485conf->delay_rts_before_send = 0; | ||
1548 | rs485conf->delay_rts_after_send = 0; | ||
1549 | rs485conf->flags |= SER_RS485_RX_DURING_TX; | ||
1550 | |||
1551 | /* RTS is required to control the transmitter */ | ||
1552 | if (!sport->have_rtscts) | ||
1553 | rs485conf->flags &= ~SER_RS485_ENABLED; | ||
1554 | |||
1555 | if (rs485conf->flags & SER_RS485_ENABLED) { | ||
1556 | unsigned long temp; | ||
1557 | |||
1558 | /* disable transmitter */ | ||
1559 | temp = readl(sport->port.membase + UCR2); | ||
1560 | temp &= ~UCR2_CTSC; | ||
1561 | if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND) | ||
1562 | temp &= ~UCR2_CTS; | ||
1563 | else | ||
1564 | temp |= UCR2_CTS; | ||
1565 | writel(temp, sport->port.membase + UCR2); | ||
1566 | } | ||
1567 | |||
1568 | port->rs485 = *rs485conf; | ||
1569 | |||
1570 | return 0; | ||
1571 | } | ||
1572 | |||
1638 | static struct uart_ops imx_pops = { | 1573 | static struct uart_ops imx_pops = { |
1639 | .tx_empty = imx_tx_empty, | 1574 | .tx_empty = imx_tx_empty, |
1640 | .set_mctrl = imx_set_mctrl, | 1575 | .set_mctrl = imx_set_mctrl, |
@@ -1927,9 +1862,6 @@ static int serial_imx_probe_dt(struct imx_port *sport, | |||
1927 | if (of_get_property(np, "fsl,uart-has-rtscts", NULL)) | 1862 | if (of_get_property(np, "fsl,uart-has-rtscts", NULL)) |
1928 | sport->have_rtscts = 1; | 1863 | sport->have_rtscts = 1; |
1929 | 1864 | ||
1930 | if (of_get_property(np, "fsl,irda-mode", NULL)) | ||
1931 | sport->use_irda = 1; | ||
1932 | |||
1933 | if (of_get_property(np, "fsl,dte-mode", NULL)) | 1865 | if (of_get_property(np, "fsl,dte-mode", NULL)) |
1934 | sport->dte_mode = 1; | 1866 | sport->dte_mode = 1; |
1935 | 1867 | ||
@@ -1958,9 +1890,6 @@ static void serial_imx_probe_pdata(struct imx_port *sport, | |||
1958 | 1890 | ||
1959 | if (pdata->flags & IMXUART_HAVE_RTSCTS) | 1891 | if (pdata->flags & IMXUART_HAVE_RTSCTS) |
1960 | sport->have_rtscts = 1; | 1892 | sport->have_rtscts = 1; |
1961 | |||
1962 | if (pdata->flags & IMXUART_IRDA) | ||
1963 | sport->use_irda = 1; | ||
1964 | } | 1893 | } |
1965 | 1894 | ||
1966 | static int serial_imx_probe(struct platform_device *pdev) | 1895 | static int serial_imx_probe(struct platform_device *pdev) |
@@ -1969,6 +1898,7 @@ static int serial_imx_probe(struct platform_device *pdev) | |||
1969 | void __iomem *base; | 1898 | void __iomem *base; |
1970 | int ret = 0; | 1899 | int ret = 0; |
1971 | struct resource *res; | 1900 | struct resource *res; |
1901 | int txirq, rxirq, rtsirq; | ||
1972 | 1902 | ||
1973 | sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); | 1903 | sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); |
1974 | if (!sport) | 1904 | if (!sport) |
@@ -1985,17 +1915,21 @@ static int serial_imx_probe(struct platform_device *pdev) | |||
1985 | if (IS_ERR(base)) | 1915 | if (IS_ERR(base)) |
1986 | return PTR_ERR(base); | 1916 | return PTR_ERR(base); |
1987 | 1917 | ||
1918 | rxirq = platform_get_irq(pdev, 0); | ||
1919 | txirq = platform_get_irq(pdev, 1); | ||
1920 | rtsirq = platform_get_irq(pdev, 2); | ||
1921 | |||
1988 | sport->port.dev = &pdev->dev; | 1922 | sport->port.dev = &pdev->dev; |
1989 | sport->port.mapbase = res->start; | 1923 | sport->port.mapbase = res->start; |
1990 | sport->port.membase = base; | 1924 | sport->port.membase = base; |
1991 | sport->port.type = PORT_IMX, | 1925 | sport->port.type = PORT_IMX, |
1992 | sport->port.iotype = UPIO_MEM; | 1926 | sport->port.iotype = UPIO_MEM; |
1993 | sport->port.irq = platform_get_irq(pdev, 0); | 1927 | sport->port.irq = rxirq; |
1994 | sport->rxirq = platform_get_irq(pdev, 0); | ||
1995 | sport->txirq = platform_get_irq(pdev, 1); | ||
1996 | sport->rtsirq = platform_get_irq(pdev, 2); | ||
1997 | sport->port.fifosize = 32; | 1928 | sport->port.fifosize = 32; |
1998 | sport->port.ops = &imx_pops; | 1929 | sport->port.ops = &imx_pops; |
1930 | sport->port.rs485_config = imx_rs485_config; | ||
1931 | sport->port.rs485.flags = | ||
1932 | SER_RS485_RTS_ON_SEND | SER_RS485_RX_DURING_TX; | ||
1999 | sport->port.flags = UPF_BOOT_AUTOCONF; | 1933 | sport->port.flags = UPF_BOOT_AUTOCONF; |
2000 | init_timer(&sport->timer); | 1934 | init_timer(&sport->timer); |
2001 | sport->timer.function = imx_timeout; | 1935 | sport->timer.function = imx_timeout; |
@@ -2021,27 +1955,18 @@ static int serial_imx_probe(struct platform_device *pdev) | |||
2021 | * Allocate the IRQ(s) i.MX1 has three interrupts whereas later | 1955 | * Allocate the IRQ(s) i.MX1 has three interrupts whereas later |
2022 | * chips only have one interrupt. | 1956 | * chips only have one interrupt. |
2023 | */ | 1957 | */ |
2024 | if (sport->txirq > 0) { | 1958 | if (txirq > 0) { |
2025 | ret = devm_request_irq(&pdev->dev, sport->rxirq, imx_rxint, 0, | 1959 | ret = devm_request_irq(&pdev->dev, rxirq, imx_rxint, 0, |
2026 | dev_name(&pdev->dev), sport); | 1960 | dev_name(&pdev->dev), sport); |
2027 | if (ret) | 1961 | if (ret) |
2028 | return ret; | 1962 | return ret; |
2029 | 1963 | ||
2030 | ret = devm_request_irq(&pdev->dev, sport->txirq, imx_txint, 0, | 1964 | ret = devm_request_irq(&pdev->dev, txirq, imx_txint, 0, |
2031 | dev_name(&pdev->dev), sport); | 1965 | dev_name(&pdev->dev), sport); |
2032 | if (ret) | 1966 | if (ret) |
2033 | return ret; | 1967 | return ret; |
2034 | |||
2035 | /* do not use RTS IRQ on IrDA */ | ||
2036 | if (!USE_IRDA(sport)) { | ||
2037 | ret = devm_request_irq(&pdev->dev, sport->rtsirq, | ||
2038 | imx_rtsint, 0, | ||
2039 | dev_name(&pdev->dev), sport); | ||
2040 | if (ret) | ||
2041 | return ret; | ||
2042 | } | ||
2043 | } else { | 1968 | } else { |
2044 | ret = devm_request_irq(&pdev->dev, sport->port.irq, imx_int, 0, | 1969 | ret = devm_request_irq(&pdev->dev, rxirq, imx_int, 0, |
2045 | dev_name(&pdev->dev), sport); | 1970 | dev_name(&pdev->dev), sport); |
2046 | if (ret) | 1971 | if (ret) |
2047 | return ret; | 1972 | return ret; |
diff --git a/drivers/tty/serial/jsm/jsm_cls.c b/drivers/tty/serial/jsm/jsm_cls.c index bfb0681195b6..4eb12a9cae76 100644 --- a/drivers/tty/serial/jsm/jsm_cls.c +++ b/drivers/tty/serial/jsm/jsm_cls.c | |||
@@ -570,7 +570,7 @@ static inline void cls_parse_isr(struct jsm_board *brd, uint port) | |||
570 | * verified in the interrupt routine. | 570 | * verified in the interrupt routine. |
571 | */ | 571 | */ |
572 | 572 | ||
573 | if (port > brd->nasync) | 573 | if (port >= brd->nasync) |
574 | return; | 574 | return; |
575 | 575 | ||
576 | ch = brd->channels[port]; | 576 | ch = brd->channels[port]; |
diff --git a/drivers/tty/serial/jsm/jsm_neo.c b/drivers/tty/serial/jsm/jsm_neo.c index 7291c2117daa..932b2accd06f 100644 --- a/drivers/tty/serial/jsm/jsm_neo.c +++ b/drivers/tty/serial/jsm/jsm_neo.c | |||
@@ -724,7 +724,7 @@ static inline void neo_parse_isr(struct jsm_board *brd, u32 port) | |||
724 | if (!brd) | 724 | if (!brd) |
725 | return; | 725 | return; |
726 | 726 | ||
727 | if (port > brd->maxports) | 727 | if (port >= brd->maxports) |
728 | return; | 728 | return; |
729 | 729 | ||
730 | ch = brd->channels[port]; | 730 | ch = brd->channels[port]; |
@@ -840,7 +840,7 @@ static inline void neo_parse_lsr(struct jsm_board *brd, u32 port) | |||
840 | if (!brd) | 840 | if (!brd) |
841 | return; | 841 | return; |
842 | 842 | ||
843 | if (port > brd->maxports) | 843 | if (port >= brd->maxports) |
844 | return; | 844 | return; |
845 | 845 | ||
846 | ch = brd->channels[port]; | 846 | ch = brd->channels[port]; |
@@ -1180,7 +1180,7 @@ static irqreturn_t neo_intr(int irq, void *voidbrd) | |||
1180 | */ | 1180 | */ |
1181 | 1181 | ||
1182 | /* Verify the port is in range. */ | 1182 | /* Verify the port is in range. */ |
1183 | if (port > brd->nasync) | 1183 | if (port >= brd->nasync) |
1184 | continue; | 1184 | continue; |
1185 | 1185 | ||
1186 | ch = brd->channels[port]; | 1186 | ch = brd->channels[port]; |
diff --git a/drivers/tty/serial/max3100.c b/drivers/tty/serial/max3100.c index 79f9a9eff545..077377259a2c 100644 --- a/drivers/tty/serial/max3100.c +++ b/drivers/tty/serial/max3100.c | |||
@@ -782,7 +782,7 @@ static int max3100_probe(struct spi_device *spi) | |||
782 | pdata = dev_get_platdata(&spi->dev); | 782 | pdata = dev_get_platdata(&spi->dev); |
783 | max3100s[i]->crystal = pdata->crystal; | 783 | max3100s[i]->crystal = pdata->crystal; |
784 | max3100s[i]->loopback = pdata->loopback; | 784 | max3100s[i]->loopback = pdata->loopback; |
785 | max3100s[i]->poll_time = pdata->poll_time * HZ / 1000; | 785 | max3100s[i]->poll_time = msecs_to_jiffies(pdata->poll_time); |
786 | if (pdata->poll_time > 0 && max3100s[i]->poll_time == 0) | 786 | if (pdata->poll_time > 0 && max3100s[i]->poll_time == 0) |
787 | max3100s[i]->poll_time = 1; | 787 | max3100s[i]->poll_time = 1; |
788 | max3100s[i]->max3100_hw_suspend = pdata->max3100_hw_suspend; | 788 | max3100s[i]->max3100_hw_suspend = pdata->max3100_hw_suspend; |
diff --git a/drivers/tty/serial/mfd.c b/drivers/tty/serial/mfd.c deleted file mode 100644 index 8fe4501d7565..000000000000 --- a/drivers/tty/serial/mfd.c +++ /dev/null | |||
@@ -1,1505 +0,0 @@ | |||
1 | /* | ||
2 | * mfd.c: driver for High Speed UART device of Intel Medfield platform | ||
3 | * | ||
4 | * Refer pxa.c, 8250.c and some other drivers in drivers/serial/ | ||
5 | * | ||
6 | * (C) Copyright 2010 Intel Corporation | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or | ||
9 | * modify it under the terms of the GNU General Public License | ||
10 | * as published by the Free Software Foundation; version 2 | ||
11 | * of the License. | ||
12 | */ | ||
13 | |||
14 | /* Notes: | ||
15 | * 1. DMA channel allocation: 0/1 channel are assigned to port 0, | ||
16 | * 2/3 chan to port 1, 4/5 chan to port 3. Even number chans | ||
17 | * are used for RX, odd chans for TX | ||
18 | * | ||
19 | * 2. The RI/DSR/DCD/DTR are not pinned out, DCD & DSR are always | ||
20 | * asserted, only when the HW is reset the DDCD and DDSR will | ||
21 | * be triggered | ||
22 | */ | ||
23 | |||
24 | #if defined(CONFIG_SERIAL_MFD_HSU_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | ||
25 | #define SUPPORT_SYSRQ | ||
26 | #endif | ||
27 | |||
28 | #include <linux/module.h> | ||
29 | #include <linux/init.h> | ||
30 | #include <linux/console.h> | ||
31 | #include <linux/sysrq.h> | ||
32 | #include <linux/slab.h> | ||
33 | #include <linux/serial_reg.h> | ||
34 | #include <linux/circ_buf.h> | ||
35 | #include <linux/delay.h> | ||
36 | #include <linux/interrupt.h> | ||
37 | #include <linux/tty.h> | ||
38 | #include <linux/tty_flip.h> | ||
39 | #include <linux/serial_core.h> | ||
40 | #include <linux/serial_mfd.h> | ||
41 | #include <linux/dma-mapping.h> | ||
42 | #include <linux/pci.h> | ||
43 | #include <linux/nmi.h> | ||
44 | #include <linux/io.h> | ||
45 | #include <linux/debugfs.h> | ||
46 | #include <linux/pm_runtime.h> | ||
47 | |||
48 | #define HSU_DMA_BUF_SIZE 2048 | ||
49 | |||
50 | #define chan_readl(chan, offset) readl(chan->reg + offset) | ||
51 | #define chan_writel(chan, offset, val) writel(val, chan->reg + offset) | ||
52 | |||
53 | #define mfd_readl(obj, offset) readl(obj->reg + offset) | ||
54 | #define mfd_writel(obj, offset, val) writel(val, obj->reg + offset) | ||
55 | |||
56 | static int hsu_dma_enable; | ||
57 | module_param(hsu_dma_enable, int, 0); | ||
58 | MODULE_PARM_DESC(hsu_dma_enable, | ||
59 | "It is a bitmap to set working mode, if bit[x] is 1, then port[x] will work in DMA mode, otherwise in PIO mode."); | ||
60 | |||
61 | struct hsu_dma_buffer { | ||
62 | u8 *buf; | ||
63 | dma_addr_t dma_addr; | ||
64 | u32 dma_size; | ||
65 | u32 ofs; | ||
66 | }; | ||
67 | |||
68 | struct hsu_dma_chan { | ||
69 | u32 id; | ||
70 | enum dma_data_direction dirt; | ||
71 | struct uart_hsu_port *uport; | ||
72 | void __iomem *reg; | ||
73 | }; | ||
74 | |||
75 | struct uart_hsu_port { | ||
76 | struct uart_port port; | ||
77 | unsigned char ier; | ||
78 | unsigned char lcr; | ||
79 | unsigned char mcr; | ||
80 | unsigned int lsr_break_flag; | ||
81 | char name[12]; | ||
82 | int index; | ||
83 | struct device *dev; | ||
84 | |||
85 | struct hsu_dma_chan *txc; | ||
86 | struct hsu_dma_chan *rxc; | ||
87 | struct hsu_dma_buffer txbuf; | ||
88 | struct hsu_dma_buffer rxbuf; | ||
89 | int use_dma; /* flag for DMA/PIO */ | ||
90 | int running; | ||
91 | int dma_tx_on; | ||
92 | }; | ||
93 | |||
94 | /* Top level data structure of HSU */ | ||
95 | struct hsu_port { | ||
96 | void __iomem *reg; | ||
97 | unsigned long paddr; | ||
98 | unsigned long iolen; | ||
99 | u32 irq; | ||
100 | |||
101 | struct uart_hsu_port port[3]; | ||
102 | struct hsu_dma_chan chans[10]; | ||
103 | |||
104 | struct dentry *debugfs; | ||
105 | }; | ||
106 | |||
107 | static inline unsigned int serial_in(struct uart_hsu_port *up, int offset) | ||
108 | { | ||
109 | unsigned int val; | ||
110 | |||
111 | if (offset > UART_MSR) { | ||
112 | offset <<= 2; | ||
113 | val = readl(up->port.membase + offset); | ||
114 | } else | ||
115 | val = (unsigned int)readb(up->port.membase + offset); | ||
116 | |||
117 | return val; | ||
118 | } | ||
119 | |||
120 | static inline void serial_out(struct uart_hsu_port *up, int offset, int value) | ||
121 | { | ||
122 | if (offset > UART_MSR) { | ||
123 | offset <<= 2; | ||
124 | writel(value, up->port.membase + offset); | ||
125 | } else { | ||
126 | unsigned char val = value & 0xff; | ||
127 | writeb(val, up->port.membase + offset); | ||
128 | } | ||
129 | } | ||
130 | |||
131 | #ifdef CONFIG_DEBUG_FS | ||
132 | |||
133 | #define HSU_REGS_BUFSIZE 1024 | ||
134 | |||
135 | |||
136 | static ssize_t port_show_regs(struct file *file, char __user *user_buf, | ||
137 | size_t count, loff_t *ppos) | ||
138 | { | ||
139 | struct uart_hsu_port *up = file->private_data; | ||
140 | char *buf; | ||
141 | u32 len = 0; | ||
142 | ssize_t ret; | ||
143 | |||
144 | buf = kzalloc(HSU_REGS_BUFSIZE, GFP_KERNEL); | ||
145 | if (!buf) | ||
146 | return 0; | ||
147 | |||
148 | len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, | ||
149 | "MFD HSU port[%d] regs:\n", up->index); | ||
150 | |||
151 | len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, | ||
152 | "=================================\n"); | ||
153 | len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, | ||
154 | "IER: \t\t0x%08x\n", serial_in(up, UART_IER)); | ||
155 | len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, | ||
156 | "IIR: \t\t0x%08x\n", serial_in(up, UART_IIR)); | ||
157 | len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, | ||
158 | "LCR: \t\t0x%08x\n", serial_in(up, UART_LCR)); | ||
159 | len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, | ||
160 | "MCR: \t\t0x%08x\n", serial_in(up, UART_MCR)); | ||
161 | len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, | ||
162 | "LSR: \t\t0x%08x\n", serial_in(up, UART_LSR)); | ||
163 | len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, | ||
164 | "MSR: \t\t0x%08x\n", serial_in(up, UART_MSR)); | ||
165 | len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, | ||
166 | "FOR: \t\t0x%08x\n", serial_in(up, UART_FOR)); | ||
167 | len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, | ||
168 | "PS: \t\t0x%08x\n", serial_in(up, UART_PS)); | ||
169 | len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, | ||
170 | "MUL: \t\t0x%08x\n", serial_in(up, UART_MUL)); | ||
171 | len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, | ||
172 | "DIV: \t\t0x%08x\n", serial_in(up, UART_DIV)); | ||
173 | |||
174 | if (len > HSU_REGS_BUFSIZE) | ||
175 | len = HSU_REGS_BUFSIZE; | ||
176 | |||
177 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); | ||
178 | kfree(buf); | ||
179 | return ret; | ||
180 | } | ||
181 | |||
182 | static ssize_t dma_show_regs(struct file *file, char __user *user_buf, | ||
183 | size_t count, loff_t *ppos) | ||
184 | { | ||
185 | struct hsu_dma_chan *chan = file->private_data; | ||
186 | char *buf; | ||
187 | u32 len = 0; | ||
188 | ssize_t ret; | ||
189 | |||
190 | buf = kzalloc(HSU_REGS_BUFSIZE, GFP_KERNEL); | ||
191 | if (!buf) | ||
192 | return 0; | ||
193 | |||
194 | len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, | ||
195 | "MFD HSU DMA channel [%d] regs:\n", chan->id); | ||
196 | |||
197 | len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, | ||
198 | "=================================\n"); | ||
199 | len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, | ||
200 | "CR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_CR)); | ||
201 | len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, | ||
202 | "DCR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_DCR)); | ||
203 | len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, | ||
204 | "BSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_BSR)); | ||
205 | len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, | ||
206 | "MOTSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_MOTSR)); | ||
207 | len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, | ||
208 | "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D0SAR)); | ||
209 | len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, | ||
210 | "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D0TSR)); | ||
211 | len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, | ||
212 | "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D1SAR)); | ||
213 | len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, | ||
214 | "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D1TSR)); | ||
215 | len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, | ||
216 | "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D2SAR)); | ||
217 | len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, | ||
218 | "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D2TSR)); | ||
219 | len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, | ||
220 | "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D3SAR)); | ||
221 | len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, | ||
222 | "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D3TSR)); | ||
223 | |||
224 | if (len > HSU_REGS_BUFSIZE) | ||
225 | len = HSU_REGS_BUFSIZE; | ||
226 | |||
227 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); | ||
228 | kfree(buf); | ||
229 | return ret; | ||
230 | } | ||
231 | |||
232 | static const struct file_operations port_regs_ops = { | ||
233 | .owner = THIS_MODULE, | ||
234 | .open = simple_open, | ||
235 | .read = port_show_regs, | ||
236 | .llseek = default_llseek, | ||
237 | }; | ||
238 | |||
239 | static const struct file_operations dma_regs_ops = { | ||
240 | .owner = THIS_MODULE, | ||
241 | .open = simple_open, | ||
242 | .read = dma_show_regs, | ||
243 | .llseek = default_llseek, | ||
244 | }; | ||
245 | |||
246 | static int hsu_debugfs_init(struct hsu_port *hsu) | ||
247 | { | ||
248 | int i; | ||
249 | char name[32]; | ||
250 | |||
251 | hsu->debugfs = debugfs_create_dir("hsu", NULL); | ||
252 | if (!hsu->debugfs) | ||
253 | return -ENOMEM; | ||
254 | |||
255 | for (i = 0; i < 3; i++) { | ||
256 | snprintf(name, sizeof(name), "port_%d_regs", i); | ||
257 | debugfs_create_file(name, S_IFREG | S_IRUGO, | ||
258 | hsu->debugfs, (void *)(&hsu->port[i]), &port_regs_ops); | ||
259 | } | ||
260 | |||
261 | for (i = 0; i < 6; i++) { | ||
262 | snprintf(name, sizeof(name), "dma_chan_%d_regs", i); | ||
263 | debugfs_create_file(name, S_IFREG | S_IRUGO, | ||
264 | hsu->debugfs, (void *)&hsu->chans[i], &dma_regs_ops); | ||
265 | } | ||
266 | |||
267 | return 0; | ||
268 | } | ||
269 | |||
270 | static void hsu_debugfs_remove(struct hsu_port *hsu) | ||
271 | { | ||
272 | if (hsu->debugfs) | ||
273 | debugfs_remove_recursive(hsu->debugfs); | ||
274 | } | ||
275 | |||
276 | #else | ||
277 | static inline int hsu_debugfs_init(struct hsu_port *hsu) | ||
278 | { | ||
279 | return 0; | ||
280 | } | ||
281 | |||
282 | static inline void hsu_debugfs_remove(struct hsu_port *hsu) | ||
283 | { | ||
284 | } | ||
285 | #endif /* CONFIG_DEBUG_FS */ | ||
286 | |||
287 | static void serial_hsu_enable_ms(struct uart_port *port) | ||
288 | { | ||
289 | struct uart_hsu_port *up = | ||
290 | container_of(port, struct uart_hsu_port, port); | ||
291 | |||
292 | up->ier |= UART_IER_MSI; | ||
293 | serial_out(up, UART_IER, up->ier); | ||
294 | } | ||
295 | |||
296 | static void hsu_dma_tx(struct uart_hsu_port *up) | ||
297 | { | ||
298 | struct circ_buf *xmit = &up->port.state->xmit; | ||
299 | struct hsu_dma_buffer *dbuf = &up->txbuf; | ||
300 | int count; | ||
301 | |||
302 | /* test_and_set_bit may be better, but anyway it's in lock protected mode */ | ||
303 | if (up->dma_tx_on) | ||
304 | return; | ||
305 | |||
306 | /* Update the circ buf info */ | ||
307 | xmit->tail += dbuf->ofs; | ||
308 | xmit->tail &= UART_XMIT_SIZE - 1; | ||
309 | |||
310 | up->port.icount.tx += dbuf->ofs; | ||
311 | dbuf->ofs = 0; | ||
312 | |||
313 | /* Disable the channel */ | ||
314 | chan_writel(up->txc, HSU_CH_CR, 0x0); | ||
315 | |||
316 | if (!uart_circ_empty(xmit) && !uart_tx_stopped(&up->port)) { | ||
317 | dma_sync_single_for_device(up->port.dev, | ||
318 | dbuf->dma_addr, | ||
319 | dbuf->dma_size, | ||
320 | DMA_TO_DEVICE); | ||
321 | |||
322 | count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); | ||
323 | dbuf->ofs = count; | ||
324 | |||
325 | /* Reprogram the channel */ | ||
326 | chan_writel(up->txc, HSU_CH_D0SAR, dbuf->dma_addr + xmit->tail); | ||
327 | chan_writel(up->txc, HSU_CH_D0TSR, count); | ||
328 | |||
329 | /* Reenable the channel */ | ||
330 | chan_writel(up->txc, HSU_CH_DCR, 0x1 | ||
331 | | (0x1 << 8) | ||
332 | | (0x1 << 16) | ||
333 | | (0x1 << 24)); | ||
334 | up->dma_tx_on = 1; | ||
335 | chan_writel(up->txc, HSU_CH_CR, 0x1); | ||
336 | } | ||
337 | |||
338 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | ||
339 | uart_write_wakeup(&up->port); | ||
340 | } | ||
341 | |||
342 | /* The buffer is already cache coherent */ | ||
343 | static void hsu_dma_start_rx_chan(struct hsu_dma_chan *rxc, | ||
344 | struct hsu_dma_buffer *dbuf) | ||
345 | { | ||
346 | dbuf->ofs = 0; | ||
347 | |||
348 | chan_writel(rxc, HSU_CH_BSR, 32); | ||
349 | chan_writel(rxc, HSU_CH_MOTSR, 4); | ||
350 | |||
351 | chan_writel(rxc, HSU_CH_D0SAR, dbuf->dma_addr); | ||
352 | chan_writel(rxc, HSU_CH_D0TSR, dbuf->dma_size); | ||
353 | chan_writel(rxc, HSU_CH_DCR, 0x1 | (0x1 << 8) | ||
354 | | (0x1 << 16) | ||
355 | | (0x1 << 24) /* timeout bit, see HSU Errata 1 */ | ||
356 | ); | ||
357 | chan_writel(rxc, HSU_CH_CR, 0x3); | ||
358 | } | ||
359 | |||
360 | /* Protected by spin_lock_irqsave(port->lock) */ | ||
361 | static void serial_hsu_start_tx(struct uart_port *port) | ||
362 | { | ||
363 | struct uart_hsu_port *up = | ||
364 | container_of(port, struct uart_hsu_port, port); | ||
365 | |||
366 | if (up->use_dma) { | ||
367 | hsu_dma_tx(up); | ||
368 | } else if (!(up->ier & UART_IER_THRI)) { | ||
369 | up->ier |= UART_IER_THRI; | ||
370 | serial_out(up, UART_IER, up->ier); | ||
371 | } | ||
372 | } | ||
373 | |||
374 | static void serial_hsu_stop_tx(struct uart_port *port) | ||
375 | { | ||
376 | struct uart_hsu_port *up = | ||
377 | container_of(port, struct uart_hsu_port, port); | ||
378 | struct hsu_dma_chan *txc = up->txc; | ||
379 | |||
380 | if (up->use_dma) | ||
381 | chan_writel(txc, HSU_CH_CR, 0x0); | ||
382 | else if (up->ier & UART_IER_THRI) { | ||
383 | up->ier &= ~UART_IER_THRI; | ||
384 | serial_out(up, UART_IER, up->ier); | ||
385 | } | ||
386 | } | ||
387 | |||
388 | /* This is always called in spinlock protected mode, so | ||
389 | * modify timeout timer is safe here */ | ||
390 | static void hsu_dma_rx(struct uart_hsu_port *up, u32 int_sts, | ||
391 | unsigned long *flags) | ||
392 | { | ||
393 | struct hsu_dma_buffer *dbuf = &up->rxbuf; | ||
394 | struct hsu_dma_chan *chan = up->rxc; | ||
395 | struct uart_port *port = &up->port; | ||
396 | struct tty_port *tport = &port->state->port; | ||
397 | int count; | ||
398 | |||
399 | /* | ||
400 | * First need to know how many is already transferred, | ||
401 | * then check if its a timeout DMA irq, and return | ||
402 | * the trail bytes out, push them up and reenable the | ||
403 | * channel | ||
404 | */ | ||
405 | |||
406 | /* Timeout IRQ, need wait some time, see Errata 2 */ | ||
407 | if (int_sts & 0xf00) | ||
408 | udelay(2); | ||
409 | |||
410 | /* Stop the channel */ | ||
411 | chan_writel(chan, HSU_CH_CR, 0x0); | ||
412 | |||
413 | count = chan_readl(chan, HSU_CH_D0SAR) - dbuf->dma_addr; | ||
414 | if (!count) { | ||
415 | /* Restart the channel before we leave */ | ||
416 | chan_writel(chan, HSU_CH_CR, 0x3); | ||
417 | return; | ||
418 | } | ||
419 | |||
420 | dma_sync_single_for_cpu(port->dev, dbuf->dma_addr, | ||
421 | dbuf->dma_size, DMA_FROM_DEVICE); | ||
422 | |||
423 | /* | ||
424 | * Head will only wrap around when we recycle | ||
425 | * the DMA buffer, and when that happens, we | ||
426 | * explicitly set tail to 0. So head will | ||
427 | * always be greater than tail. | ||
428 | */ | ||
429 | tty_insert_flip_string(tport, dbuf->buf, count); | ||
430 | port->icount.rx += count; | ||
431 | |||
432 | dma_sync_single_for_device(up->port.dev, dbuf->dma_addr, | ||
433 | dbuf->dma_size, DMA_FROM_DEVICE); | ||
434 | |||
435 | /* Reprogram the channel */ | ||
436 | chan_writel(chan, HSU_CH_D0SAR, dbuf->dma_addr); | ||
437 | chan_writel(chan, HSU_CH_D0TSR, dbuf->dma_size); | ||
438 | chan_writel(chan, HSU_CH_DCR, 0x1 | ||
439 | | (0x1 << 8) | ||
440 | | (0x1 << 16) | ||
441 | | (0x1 << 24) /* timeout bit, see HSU Errata 1 */ | ||
442 | ); | ||
443 | spin_unlock_irqrestore(&up->port.lock, *flags); | ||
444 | tty_flip_buffer_push(tport); | ||
445 | spin_lock_irqsave(&up->port.lock, *flags); | ||
446 | |||
447 | chan_writel(chan, HSU_CH_CR, 0x3); | ||
448 | |||
449 | } | ||
450 | |||
451 | static void serial_hsu_stop_rx(struct uart_port *port) | ||
452 | { | ||
453 | struct uart_hsu_port *up = | ||
454 | container_of(port, struct uart_hsu_port, port); | ||
455 | struct hsu_dma_chan *chan = up->rxc; | ||
456 | |||
457 | if (up->use_dma) | ||
458 | chan_writel(chan, HSU_CH_CR, 0x2); | ||
459 | else { | ||
460 | up->ier &= ~UART_IER_RLSI; | ||
461 | up->port.read_status_mask &= ~UART_LSR_DR; | ||
462 | serial_out(up, UART_IER, up->ier); | ||
463 | } | ||
464 | } | ||
465 | |||
466 | static inline void receive_chars(struct uart_hsu_port *up, int *status, | ||
467 | unsigned long *flags) | ||
468 | { | ||
469 | unsigned int ch, flag; | ||
470 | unsigned int max_count = 256; | ||
471 | |||
472 | do { | ||
473 | ch = serial_in(up, UART_RX); | ||
474 | flag = TTY_NORMAL; | ||
475 | up->port.icount.rx++; | ||
476 | |||
477 | if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE | | ||
478 | UART_LSR_FE | UART_LSR_OE))) { | ||
479 | |||
480 | dev_warn(up->dev, "We really rush into ERR/BI case" | ||
481 | "status = 0x%02x", *status); | ||
482 | /* For statistics only */ | ||
483 | if (*status & UART_LSR_BI) { | ||
484 | *status &= ~(UART_LSR_FE | UART_LSR_PE); | ||
485 | up->port.icount.brk++; | ||
486 | /* | ||
487 | * We do the SysRQ and SAK checking | ||
488 | * here because otherwise the break | ||
489 | * may get masked by ignore_status_mask | ||
490 | * or read_status_mask. | ||
491 | */ | ||
492 | if (uart_handle_break(&up->port)) | ||
493 | goto ignore_char; | ||
494 | } else if (*status & UART_LSR_PE) | ||
495 | up->port.icount.parity++; | ||
496 | else if (*status & UART_LSR_FE) | ||
497 | up->port.icount.frame++; | ||
498 | if (*status & UART_LSR_OE) | ||
499 | up->port.icount.overrun++; | ||
500 | |||
501 | /* Mask off conditions which should be ignored. */ | ||
502 | *status &= up->port.read_status_mask; | ||
503 | |||
504 | #ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE | ||
505 | if (up->port.cons && | ||
506 | up->port.cons->index == up->port.line) { | ||
507 | /* Recover the break flag from console xmit */ | ||
508 | *status |= up->lsr_break_flag; | ||
509 | up->lsr_break_flag = 0; | ||
510 | } | ||
511 | #endif | ||
512 | if (*status & UART_LSR_BI) { | ||
513 | flag = TTY_BREAK; | ||
514 | } else if (*status & UART_LSR_PE) | ||
515 | flag = TTY_PARITY; | ||
516 | else if (*status & UART_LSR_FE) | ||
517 | flag = TTY_FRAME; | ||
518 | } | ||
519 | |||
520 | if (uart_handle_sysrq_char(&up->port, ch)) | ||
521 | goto ignore_char; | ||
522 | |||
523 | uart_insert_char(&up->port, *status, UART_LSR_OE, ch, flag); | ||
524 | ignore_char: | ||
525 | *status = serial_in(up, UART_LSR); | ||
526 | } while ((*status & UART_LSR_DR) && max_count--); | ||
527 | |||
528 | spin_unlock_irqrestore(&up->port.lock, *flags); | ||
529 | tty_flip_buffer_push(&up->port.state->port); | ||
530 | spin_lock_irqsave(&up->port.lock, *flags); | ||
531 | } | ||
532 | |||
533 | static void transmit_chars(struct uart_hsu_port *up) | ||
534 | { | ||
535 | struct circ_buf *xmit = &up->port.state->xmit; | ||
536 | int count; | ||
537 | |||
538 | if (up->port.x_char) { | ||
539 | serial_out(up, UART_TX, up->port.x_char); | ||
540 | up->port.icount.tx++; | ||
541 | up->port.x_char = 0; | ||
542 | return; | ||
543 | } | ||
544 | if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { | ||
545 | serial_hsu_stop_tx(&up->port); | ||
546 | return; | ||
547 | } | ||
548 | |||
549 | /* The IRQ is for TX FIFO half-empty */ | ||
550 | count = up->port.fifosize / 2; | ||
551 | |||
552 | do { | ||
553 | serial_out(up, UART_TX, xmit->buf[xmit->tail]); | ||
554 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | ||
555 | |||
556 | up->port.icount.tx++; | ||
557 | if (uart_circ_empty(xmit)) | ||
558 | break; | ||
559 | } while (--count > 0); | ||
560 | |||
561 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | ||
562 | uart_write_wakeup(&up->port); | ||
563 | |||
564 | if (uart_circ_empty(xmit)) | ||
565 | serial_hsu_stop_tx(&up->port); | ||
566 | } | ||
567 | |||
568 | static inline void check_modem_status(struct uart_hsu_port *up) | ||
569 | { | ||
570 | int status; | ||
571 | |||
572 | status = serial_in(up, UART_MSR); | ||
573 | |||
574 | if ((status & UART_MSR_ANY_DELTA) == 0) | ||
575 | return; | ||
576 | |||
577 | if (status & UART_MSR_TERI) | ||
578 | up->port.icount.rng++; | ||
579 | if (status & UART_MSR_DDSR) | ||
580 | up->port.icount.dsr++; | ||
581 | /* We may only get DDCD when HW init and reset */ | ||
582 | if (status & UART_MSR_DDCD) | ||
583 | uart_handle_dcd_change(&up->port, status & UART_MSR_DCD); | ||
584 | /* Will start/stop_tx accordingly */ | ||
585 | if (status & UART_MSR_DCTS) | ||
586 | uart_handle_cts_change(&up->port, status & UART_MSR_CTS); | ||
587 | |||
588 | wake_up_interruptible(&up->port.state->port.delta_msr_wait); | ||
589 | } | ||
590 | |||
591 | /* | ||
592 | * This handles the interrupt from one port. | ||
593 | */ | ||
594 | static irqreturn_t port_irq(int irq, void *dev_id) | ||
595 | { | ||
596 | struct uart_hsu_port *up = dev_id; | ||
597 | unsigned int iir, lsr; | ||
598 | unsigned long flags; | ||
599 | |||
600 | if (unlikely(!up->running)) | ||
601 | return IRQ_NONE; | ||
602 | |||
603 | spin_lock_irqsave(&up->port.lock, flags); | ||
604 | if (up->use_dma) { | ||
605 | lsr = serial_in(up, UART_LSR); | ||
606 | if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE | | ||
607 | UART_LSR_FE | UART_LSR_OE))) | ||
608 | dev_warn(up->dev, | ||
609 | "Got lsr irq while using DMA, lsr = 0x%2x\n", | ||
610 | lsr); | ||
611 | check_modem_status(up); | ||
612 | spin_unlock_irqrestore(&up->port.lock, flags); | ||
613 | return IRQ_HANDLED; | ||
614 | } | ||
615 | |||
616 | iir = serial_in(up, UART_IIR); | ||
617 | if (iir & UART_IIR_NO_INT) { | ||
618 | spin_unlock_irqrestore(&up->port.lock, flags); | ||
619 | return IRQ_NONE; | ||
620 | } | ||
621 | |||
622 | lsr = serial_in(up, UART_LSR); | ||
623 | if (lsr & UART_LSR_DR) | ||
624 | receive_chars(up, &lsr, &flags); | ||
625 | check_modem_status(up); | ||
626 | |||
627 | /* lsr will be renewed during the receive_chars */ | ||
628 | if (lsr & UART_LSR_THRE) | ||
629 | transmit_chars(up); | ||
630 | |||
631 | spin_unlock_irqrestore(&up->port.lock, flags); | ||
632 | return IRQ_HANDLED; | ||
633 | } | ||
634 | |||
635 | static inline void dma_chan_irq(struct hsu_dma_chan *chan) | ||
636 | { | ||
637 | struct uart_hsu_port *up = chan->uport; | ||
638 | unsigned long flags; | ||
639 | u32 int_sts; | ||
640 | |||
641 | spin_lock_irqsave(&up->port.lock, flags); | ||
642 | |||
643 | if (!up->use_dma || !up->running) | ||
644 | goto exit; | ||
645 | |||
646 | /* | ||
647 | * No matter what situation, need read clear the IRQ status | ||
648 | * There is a bug, see Errata 5, HSD 2900918 | ||
649 | */ | ||
650 | int_sts = chan_readl(chan, HSU_CH_SR); | ||
651 | |||
652 | /* Rx channel */ | ||
653 | if (chan->dirt == DMA_FROM_DEVICE) | ||
654 | hsu_dma_rx(up, int_sts, &flags); | ||
655 | |||
656 | /* Tx channel */ | ||
657 | if (chan->dirt == DMA_TO_DEVICE) { | ||
658 | chan_writel(chan, HSU_CH_CR, 0x0); | ||
659 | up->dma_tx_on = 0; | ||
660 | hsu_dma_tx(up); | ||
661 | } | ||
662 | |||
663 | exit: | ||
664 | spin_unlock_irqrestore(&up->port.lock, flags); | ||
665 | return; | ||
666 | } | ||
667 | |||
668 | static irqreturn_t dma_irq(int irq, void *dev_id) | ||
669 | { | ||
670 | struct hsu_port *hsu = dev_id; | ||
671 | u32 int_sts, i; | ||
672 | |||
673 | int_sts = mfd_readl(hsu, HSU_GBL_DMAISR); | ||
674 | |||
675 | /* Currently we only have 6 channels may be used */ | ||
676 | for (i = 0; i < 6; i++) { | ||
677 | if (int_sts & 0x1) | ||
678 | dma_chan_irq(&hsu->chans[i]); | ||
679 | int_sts >>= 1; | ||
680 | } | ||
681 | |||
682 | return IRQ_HANDLED; | ||
683 | } | ||
684 | |||
685 | static unsigned int serial_hsu_tx_empty(struct uart_port *port) | ||
686 | { | ||
687 | struct uart_hsu_port *up = | ||
688 | container_of(port, struct uart_hsu_port, port); | ||
689 | unsigned long flags; | ||
690 | unsigned int ret; | ||
691 | |||
692 | spin_lock_irqsave(&up->port.lock, flags); | ||
693 | ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; | ||
694 | spin_unlock_irqrestore(&up->port.lock, flags); | ||
695 | |||
696 | return ret; | ||
697 | } | ||
698 | |||
699 | static unsigned int serial_hsu_get_mctrl(struct uart_port *port) | ||
700 | { | ||
701 | struct uart_hsu_port *up = | ||
702 | container_of(port, struct uart_hsu_port, port); | ||
703 | unsigned char status; | ||
704 | unsigned int ret; | ||
705 | |||
706 | status = serial_in(up, UART_MSR); | ||
707 | |||
708 | ret = 0; | ||
709 | if (status & UART_MSR_DCD) | ||
710 | ret |= TIOCM_CAR; | ||
711 | if (status & UART_MSR_RI) | ||
712 | ret |= TIOCM_RNG; | ||
713 | if (status & UART_MSR_DSR) | ||
714 | ret |= TIOCM_DSR; | ||
715 | if (status & UART_MSR_CTS) | ||
716 | ret |= TIOCM_CTS; | ||
717 | return ret; | ||
718 | } | ||
719 | |||
720 | static void serial_hsu_set_mctrl(struct uart_port *port, unsigned int mctrl) | ||
721 | { | ||
722 | struct uart_hsu_port *up = | ||
723 | container_of(port, struct uart_hsu_port, port); | ||
724 | unsigned char mcr = 0; | ||
725 | |||
726 | if (mctrl & TIOCM_RTS) | ||
727 | mcr |= UART_MCR_RTS; | ||
728 | if (mctrl & TIOCM_DTR) | ||
729 | mcr |= UART_MCR_DTR; | ||
730 | if (mctrl & TIOCM_OUT1) | ||
731 | mcr |= UART_MCR_OUT1; | ||
732 | if (mctrl & TIOCM_OUT2) | ||
733 | mcr |= UART_MCR_OUT2; | ||
734 | if (mctrl & TIOCM_LOOP) | ||
735 | mcr |= UART_MCR_LOOP; | ||
736 | |||
737 | mcr |= up->mcr; | ||
738 | |||
739 | serial_out(up, UART_MCR, mcr); | ||
740 | } | ||
741 | |||
742 | static void serial_hsu_break_ctl(struct uart_port *port, int break_state) | ||
743 | { | ||
744 | struct uart_hsu_port *up = | ||
745 | container_of(port, struct uart_hsu_port, port); | ||
746 | unsigned long flags; | ||
747 | |||
748 | spin_lock_irqsave(&up->port.lock, flags); | ||
749 | if (break_state == -1) | ||
750 | up->lcr |= UART_LCR_SBC; | ||
751 | else | ||
752 | up->lcr &= ~UART_LCR_SBC; | ||
753 | serial_out(up, UART_LCR, up->lcr); | ||
754 | spin_unlock_irqrestore(&up->port.lock, flags); | ||
755 | } | ||
756 | |||
757 | /* | ||
758 | * What special to do: | ||
759 | * 1. chose the 64B fifo mode | ||
760 | * 2. start dma or pio depends on configuration | ||
761 | * 3. we only allocate dma memory when needed | ||
762 | */ | ||
763 | static int serial_hsu_startup(struct uart_port *port) | ||
764 | { | ||
765 | struct uart_hsu_port *up = | ||
766 | container_of(port, struct uart_hsu_port, port); | ||
767 | unsigned long flags; | ||
768 | |||
769 | pm_runtime_get_sync(up->dev); | ||
770 | |||
771 | /* | ||
772 | * Clear the FIFO buffers and disable them. | ||
773 | * (they will be reenabled in set_termios()) | ||
774 | */ | ||
775 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); | ||
776 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | | ||
777 | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); | ||
778 | serial_out(up, UART_FCR, 0); | ||
779 | |||
780 | /* Clear the interrupt registers. */ | ||
781 | (void) serial_in(up, UART_LSR); | ||
782 | (void) serial_in(up, UART_RX); | ||
783 | (void) serial_in(up, UART_IIR); | ||
784 | (void) serial_in(up, UART_MSR); | ||
785 | |||
786 | /* Now, initialize the UART, default is 8n1 */ | ||
787 | serial_out(up, UART_LCR, UART_LCR_WLEN8); | ||
788 | |||
789 | spin_lock_irqsave(&up->port.lock, flags); | ||
790 | |||
791 | up->port.mctrl |= TIOCM_OUT2; | ||
792 | serial_hsu_set_mctrl(&up->port, up->port.mctrl); | ||
793 | |||
794 | /* | ||
795 | * Finally, enable interrupts. Note: Modem status interrupts | ||
796 | * are set via set_termios(), which will be occurring imminently | ||
797 | * anyway, so we don't enable them here. | ||
798 | */ | ||
799 | if (!up->use_dma) | ||
800 | up->ier = UART_IER_RLSI | UART_IER_RDI | UART_IER_RTOIE; | ||
801 | else | ||
802 | up->ier = 0; | ||
803 | serial_out(up, UART_IER, up->ier); | ||
804 | |||
805 | spin_unlock_irqrestore(&up->port.lock, flags); | ||
806 | |||
807 | /* DMA init */ | ||
808 | if (up->use_dma) { | ||
809 | struct hsu_dma_buffer *dbuf; | ||
810 | struct circ_buf *xmit = &port->state->xmit; | ||
811 | |||
812 | up->dma_tx_on = 0; | ||
813 | |||
814 | /* First allocate the RX buffer */ | ||
815 | dbuf = &up->rxbuf; | ||
816 | dbuf->buf = kzalloc(HSU_DMA_BUF_SIZE, GFP_KERNEL); | ||
817 | if (!dbuf->buf) { | ||
818 | up->use_dma = 0; | ||
819 | goto exit; | ||
820 | } | ||
821 | dbuf->dma_addr = dma_map_single(port->dev, | ||
822 | dbuf->buf, | ||
823 | HSU_DMA_BUF_SIZE, | ||
824 | DMA_FROM_DEVICE); | ||
825 | dbuf->dma_size = HSU_DMA_BUF_SIZE; | ||
826 | |||
827 | /* Start the RX channel right now */ | ||
828 | hsu_dma_start_rx_chan(up->rxc, dbuf); | ||
829 | |||
830 | /* Next init the TX DMA */ | ||
831 | dbuf = &up->txbuf; | ||
832 | dbuf->buf = xmit->buf; | ||
833 | dbuf->dma_addr = dma_map_single(port->dev, | ||
834 | dbuf->buf, | ||
835 | UART_XMIT_SIZE, | ||
836 | DMA_TO_DEVICE); | ||
837 | dbuf->dma_size = UART_XMIT_SIZE; | ||
838 | |||
839 | /* This should not be changed all around */ | ||
840 | chan_writel(up->txc, HSU_CH_BSR, 32); | ||
841 | chan_writel(up->txc, HSU_CH_MOTSR, 4); | ||
842 | dbuf->ofs = 0; | ||
843 | } | ||
844 | |||
845 | exit: | ||
846 | /* And clear the interrupt registers again for luck. */ | ||
847 | (void) serial_in(up, UART_LSR); | ||
848 | (void) serial_in(up, UART_RX); | ||
849 | (void) serial_in(up, UART_IIR); | ||
850 | (void) serial_in(up, UART_MSR); | ||
851 | |||
852 | up->running = 1; | ||
853 | return 0; | ||
854 | } | ||
855 | |||
856 | static void serial_hsu_shutdown(struct uart_port *port) | ||
857 | { | ||
858 | struct uart_hsu_port *up = | ||
859 | container_of(port, struct uart_hsu_port, port); | ||
860 | unsigned long flags; | ||
861 | |||
862 | /* Disable interrupts from this port */ | ||
863 | up->ier = 0; | ||
864 | serial_out(up, UART_IER, 0); | ||
865 | up->running = 0; | ||
866 | |||
867 | spin_lock_irqsave(&up->port.lock, flags); | ||
868 | up->port.mctrl &= ~TIOCM_OUT2; | ||
869 | serial_hsu_set_mctrl(&up->port, up->port.mctrl); | ||
870 | spin_unlock_irqrestore(&up->port.lock, flags); | ||
871 | |||
872 | /* Disable break condition and FIFOs */ | ||
873 | serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC); | ||
874 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | | ||
875 | UART_FCR_CLEAR_RCVR | | ||
876 | UART_FCR_CLEAR_XMIT); | ||
877 | serial_out(up, UART_FCR, 0); | ||
878 | |||
879 | pm_runtime_put(up->dev); | ||
880 | } | ||
881 | |||
882 | static void | ||
883 | serial_hsu_set_termios(struct uart_port *port, struct ktermios *termios, | ||
884 | struct ktermios *old) | ||
885 | { | ||
886 | struct uart_hsu_port *up = | ||
887 | container_of(port, struct uart_hsu_port, port); | ||
888 | unsigned char cval, fcr = 0; | ||
889 | unsigned long flags; | ||
890 | unsigned int baud, quot; | ||
891 | u32 ps, mul; | ||
892 | |||
893 | switch (termios->c_cflag & CSIZE) { | ||
894 | case CS5: | ||
895 | cval = UART_LCR_WLEN5; | ||
896 | break; | ||
897 | case CS6: | ||
898 | cval = UART_LCR_WLEN6; | ||
899 | break; | ||
900 | case CS7: | ||
901 | cval = UART_LCR_WLEN7; | ||
902 | break; | ||
903 | default: | ||
904 | case CS8: | ||
905 | cval = UART_LCR_WLEN8; | ||
906 | break; | ||
907 | } | ||
908 | |||
909 | /* CMSPAR isn't supported by this driver */ | ||
910 | termios->c_cflag &= ~CMSPAR; | ||
911 | |||
912 | if (termios->c_cflag & CSTOPB) | ||
913 | cval |= UART_LCR_STOP; | ||
914 | if (termios->c_cflag & PARENB) | ||
915 | cval |= UART_LCR_PARITY; | ||
916 | if (!(termios->c_cflag & PARODD)) | ||
917 | cval |= UART_LCR_EPAR; | ||
918 | |||
919 | /* | ||
920 | * The base clk is 50Mhz, and the baud rate come from: | ||
921 | * baud = 50M * MUL / (DIV * PS * DLAB) | ||
922 | * | ||
923 | * For those basic low baud rate we can get the direct | ||
924 | * scalar from 2746800, like 115200 = 2746800/24. For those | ||
925 | * higher baud rate, we handle them case by case, mainly by | ||
926 | * adjusting the MUL/PS registers, and DIV register is kept | ||
927 | * as default value 0x3d09 to make things simple | ||
928 | */ | ||
929 | baud = uart_get_baud_rate(port, termios, old, 0, 4000000); | ||
930 | |||
931 | quot = 1; | ||
932 | ps = 0x10; | ||
933 | mul = 0x3600; | ||
934 | switch (baud) { | ||
935 | case 3500000: | ||
936 | mul = 0x3345; | ||
937 | ps = 0xC; | ||
938 | break; | ||
939 | case 1843200: | ||
940 | mul = 0x2400; | ||
941 | break; | ||
942 | case 3000000: | ||
943 | case 2500000: | ||
944 | case 2000000: | ||
945 | case 1500000: | ||
946 | case 1000000: | ||
947 | case 500000: | ||
948 | /* mul/ps/quot = 0x9C4/0x10/0x1 will make a 500000 bps */ | ||
949 | mul = baud / 500000 * 0x9C4; | ||
950 | break; | ||
951 | default: | ||
952 | /* Use uart_get_divisor to get quot for other baud rates */ | ||
953 | quot = 0; | ||
954 | } | ||
955 | |||
956 | if (!quot) | ||
957 | quot = uart_get_divisor(port, baud); | ||
958 | |||
959 | if ((up->port.uartclk / quot) < (2400 * 16)) | ||
960 | fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_1B; | ||
961 | else if ((up->port.uartclk / quot) < (230400 * 16)) | ||
962 | fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_16B; | ||
963 | else | ||
964 | fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_32B; | ||
965 | |||
966 | fcr |= UART_FCR_HSU_64B_FIFO; | ||
967 | |||
968 | /* | ||
969 | * Ok, we're now changing the port state. Do it with | ||
970 | * interrupts disabled. | ||
971 | */ | ||
972 | spin_lock_irqsave(&up->port.lock, flags); | ||
973 | |||
974 | /* Update the per-port timeout */ | ||
975 | uart_update_timeout(port, termios->c_cflag, baud); | ||
976 | |||
977 | up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; | ||
978 | if (termios->c_iflag & INPCK) | ||
979 | up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; | ||
980 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) | ||
981 | up->port.read_status_mask |= UART_LSR_BI; | ||
982 | |||
983 | /* Characters to ignore */ | ||
984 | up->port.ignore_status_mask = 0; | ||
985 | if (termios->c_iflag & IGNPAR) | ||
986 | up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; | ||
987 | if (termios->c_iflag & IGNBRK) { | ||
988 | up->port.ignore_status_mask |= UART_LSR_BI; | ||
989 | /* | ||
990 | * If we're ignoring parity and break indicators, | ||
991 | * ignore overruns too (for real raw support). | ||
992 | */ | ||
993 | if (termios->c_iflag & IGNPAR) | ||
994 | up->port.ignore_status_mask |= UART_LSR_OE; | ||
995 | } | ||
996 | |||
997 | /* Ignore all characters if CREAD is not set */ | ||
998 | if ((termios->c_cflag & CREAD) == 0) | ||
999 | up->port.ignore_status_mask |= UART_LSR_DR; | ||
1000 | |||
1001 | /* | ||
1002 | * CTS flow control flag and modem status interrupts, disable | ||
1003 | * MSI by default | ||
1004 | */ | ||
1005 | up->ier &= ~UART_IER_MSI; | ||
1006 | if (UART_ENABLE_MS(&up->port, termios->c_cflag)) | ||
1007 | up->ier |= UART_IER_MSI; | ||
1008 | |||
1009 | serial_out(up, UART_IER, up->ier); | ||
1010 | |||
1011 | if (termios->c_cflag & CRTSCTS) | ||
1012 | up->mcr |= UART_MCR_AFE | UART_MCR_RTS; | ||
1013 | else | ||
1014 | up->mcr &= ~UART_MCR_AFE; | ||
1015 | |||
1016 | serial_out(up, UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */ | ||
1017 | serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */ | ||
1018 | serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */ | ||
1019 | serial_out(up, UART_LCR, cval); /* reset DLAB */ | ||
1020 | serial_out(up, UART_MUL, mul); /* set MUL */ | ||
1021 | serial_out(up, UART_PS, ps); /* set PS */ | ||
1022 | up->lcr = cval; /* Save LCR */ | ||
1023 | serial_hsu_set_mctrl(&up->port, up->port.mctrl); | ||
1024 | serial_out(up, UART_FCR, fcr); | ||
1025 | spin_unlock_irqrestore(&up->port.lock, flags); | ||
1026 | } | ||
1027 | |||
1028 | static void | ||
1029 | serial_hsu_pm(struct uart_port *port, unsigned int state, | ||
1030 | unsigned int oldstate) | ||
1031 | { | ||
1032 | } | ||
1033 | |||
1034 | static void serial_hsu_release_port(struct uart_port *port) | ||
1035 | { | ||
1036 | } | ||
1037 | |||
1038 | static int serial_hsu_request_port(struct uart_port *port) | ||
1039 | { | ||
1040 | return 0; | ||
1041 | } | ||
1042 | |||
1043 | static void serial_hsu_config_port(struct uart_port *port, int flags) | ||
1044 | { | ||
1045 | struct uart_hsu_port *up = | ||
1046 | container_of(port, struct uart_hsu_port, port); | ||
1047 | up->port.type = PORT_MFD; | ||
1048 | } | ||
1049 | |||
1050 | static int | ||
1051 | serial_hsu_verify_port(struct uart_port *port, struct serial_struct *ser) | ||
1052 | { | ||
1053 | /* We don't want the core code to modify any port params */ | ||
1054 | return -EINVAL; | ||
1055 | } | ||
1056 | |||
1057 | static const char * | ||
1058 | serial_hsu_type(struct uart_port *port) | ||
1059 | { | ||
1060 | struct uart_hsu_port *up = | ||
1061 | container_of(port, struct uart_hsu_port, port); | ||
1062 | return up->name; | ||
1063 | } | ||
1064 | |||
1065 | /* Mainly for uart console use */ | ||
1066 | static struct uart_hsu_port *serial_hsu_ports[3]; | ||
1067 | static struct uart_driver serial_hsu_reg; | ||
1068 | |||
1069 | #ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE | ||
1070 | |||
1071 | #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) | ||
1072 | |||
1073 | /* Wait for transmitter & holding register to empty */ | ||
1074 | static inline void wait_for_xmitr(struct uart_hsu_port *up) | ||
1075 | { | ||
1076 | unsigned int status, tmout = 1000; | ||
1077 | |||
1078 | /* Wait up to 1ms for the character to be sent. */ | ||
1079 | do { | ||
1080 | status = serial_in(up, UART_LSR); | ||
1081 | |||
1082 | if (status & UART_LSR_BI) | ||
1083 | up->lsr_break_flag = UART_LSR_BI; | ||
1084 | |||
1085 | if (--tmout == 0) | ||
1086 | break; | ||
1087 | udelay(1); | ||
1088 | } while (!(status & BOTH_EMPTY)); | ||
1089 | |||
1090 | /* Wait up to 1s for flow control if necessary */ | ||
1091 | if (up->port.flags & UPF_CONS_FLOW) { | ||
1092 | tmout = 1000000; | ||
1093 | while (--tmout && | ||
1094 | ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0)) | ||
1095 | udelay(1); | ||
1096 | } | ||
1097 | } | ||
1098 | |||
1099 | static void serial_hsu_console_putchar(struct uart_port *port, int ch) | ||
1100 | { | ||
1101 | struct uart_hsu_port *up = | ||
1102 | container_of(port, struct uart_hsu_port, port); | ||
1103 | |||
1104 | wait_for_xmitr(up); | ||
1105 | serial_out(up, UART_TX, ch); | ||
1106 | } | ||
1107 | |||
1108 | /* | ||
1109 | * Print a string to the serial port trying not to disturb | ||
1110 | * any possible real use of the port... | ||
1111 | * | ||
1112 | * The console_lock must be held when we get here. | ||
1113 | */ | ||
1114 | static void | ||
1115 | serial_hsu_console_write(struct console *co, const char *s, unsigned int count) | ||
1116 | { | ||
1117 | struct uart_hsu_port *up = serial_hsu_ports[co->index]; | ||
1118 | unsigned long flags; | ||
1119 | unsigned int ier; | ||
1120 | int locked = 1; | ||
1121 | |||
1122 | touch_nmi_watchdog(); | ||
1123 | |||
1124 | local_irq_save(flags); | ||
1125 | if (up->port.sysrq) | ||
1126 | locked = 0; | ||
1127 | else if (oops_in_progress) { | ||
1128 | locked = spin_trylock(&up->port.lock); | ||
1129 | } else | ||
1130 | spin_lock(&up->port.lock); | ||
1131 | |||
1132 | /* First save the IER then disable the interrupts */ | ||
1133 | ier = serial_in(up, UART_IER); | ||
1134 | serial_out(up, UART_IER, 0); | ||
1135 | |||
1136 | uart_console_write(&up->port, s, count, serial_hsu_console_putchar); | ||
1137 | |||
1138 | /* | ||
1139 | * Finally, wait for transmitter to become empty | ||
1140 | * and restore the IER | ||
1141 | */ | ||
1142 | wait_for_xmitr(up); | ||
1143 | serial_out(up, UART_IER, ier); | ||
1144 | |||
1145 | if (locked) | ||
1146 | spin_unlock(&up->port.lock); | ||
1147 | local_irq_restore(flags); | ||
1148 | } | ||
1149 | |||
1150 | static struct console serial_hsu_console; | ||
1151 | |||
1152 | static int __init | ||
1153 | serial_hsu_console_setup(struct console *co, char *options) | ||
1154 | { | ||
1155 | struct uart_hsu_port *up; | ||
1156 | int baud = 115200; | ||
1157 | int bits = 8; | ||
1158 | int parity = 'n'; | ||
1159 | int flow = 'n'; | ||
1160 | |||
1161 | if (co->index == -1 || co->index >= serial_hsu_reg.nr) | ||
1162 | co->index = 0; | ||
1163 | up = serial_hsu_ports[co->index]; | ||
1164 | if (!up) | ||
1165 | return -ENODEV; | ||
1166 | |||
1167 | if (options) | ||
1168 | uart_parse_options(options, &baud, &parity, &bits, &flow); | ||
1169 | |||
1170 | return uart_set_options(&up->port, co, baud, parity, bits, flow); | ||
1171 | } | ||
1172 | |||
1173 | static struct console serial_hsu_console = { | ||
1174 | .name = "ttyMFD", | ||
1175 | .write = serial_hsu_console_write, | ||
1176 | .device = uart_console_device, | ||
1177 | .setup = serial_hsu_console_setup, | ||
1178 | .flags = CON_PRINTBUFFER, | ||
1179 | .index = -1, | ||
1180 | .data = &serial_hsu_reg, | ||
1181 | }; | ||
1182 | |||
1183 | #define SERIAL_HSU_CONSOLE (&serial_hsu_console) | ||
1184 | #else | ||
1185 | #define SERIAL_HSU_CONSOLE NULL | ||
1186 | #endif | ||
1187 | |||
1188 | static struct uart_ops serial_hsu_pops = { | ||
1189 | .tx_empty = serial_hsu_tx_empty, | ||
1190 | .set_mctrl = serial_hsu_set_mctrl, | ||
1191 | .get_mctrl = serial_hsu_get_mctrl, | ||
1192 | .stop_tx = serial_hsu_stop_tx, | ||
1193 | .start_tx = serial_hsu_start_tx, | ||
1194 | .stop_rx = serial_hsu_stop_rx, | ||
1195 | .enable_ms = serial_hsu_enable_ms, | ||
1196 | .break_ctl = serial_hsu_break_ctl, | ||
1197 | .startup = serial_hsu_startup, | ||
1198 | .shutdown = serial_hsu_shutdown, | ||
1199 | .set_termios = serial_hsu_set_termios, | ||
1200 | .pm = serial_hsu_pm, | ||
1201 | .type = serial_hsu_type, | ||
1202 | .release_port = serial_hsu_release_port, | ||
1203 | .request_port = serial_hsu_request_port, | ||
1204 | .config_port = serial_hsu_config_port, | ||
1205 | .verify_port = serial_hsu_verify_port, | ||
1206 | }; | ||
1207 | |||
1208 | static struct uart_driver serial_hsu_reg = { | ||
1209 | .owner = THIS_MODULE, | ||
1210 | .driver_name = "MFD serial", | ||
1211 | .dev_name = "ttyMFD", | ||
1212 | .major = TTY_MAJOR, | ||
1213 | .minor = 128, | ||
1214 | .nr = 3, | ||
1215 | .cons = SERIAL_HSU_CONSOLE, | ||
1216 | }; | ||
1217 | |||
1218 | #ifdef CONFIG_PM | ||
1219 | static int serial_hsu_suspend(struct pci_dev *pdev, pm_message_t state) | ||
1220 | { | ||
1221 | void *priv = pci_get_drvdata(pdev); | ||
1222 | struct uart_hsu_port *up; | ||
1223 | |||
1224 | /* Make sure this is not the internal dma controller */ | ||
1225 | if (priv && (pdev->device != 0x081E)) { | ||
1226 | up = priv; | ||
1227 | uart_suspend_port(&serial_hsu_reg, &up->port); | ||
1228 | } | ||
1229 | |||
1230 | pci_save_state(pdev); | ||
1231 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | ||
1232 | return 0; | ||
1233 | } | ||
1234 | |||
1235 | static int serial_hsu_resume(struct pci_dev *pdev) | ||
1236 | { | ||
1237 | void *priv = pci_get_drvdata(pdev); | ||
1238 | struct uart_hsu_port *up; | ||
1239 | int ret; | ||
1240 | |||
1241 | pci_set_power_state(pdev, PCI_D0); | ||
1242 | pci_restore_state(pdev); | ||
1243 | |||
1244 | ret = pci_enable_device(pdev); | ||
1245 | if (ret) | ||
1246 | dev_warn(&pdev->dev, | ||
1247 | "HSU: can't re-enable device, try to continue\n"); | ||
1248 | |||
1249 | if (priv && (pdev->device != 0x081E)) { | ||
1250 | up = priv; | ||
1251 | uart_resume_port(&serial_hsu_reg, &up->port); | ||
1252 | } | ||
1253 | return 0; | ||
1254 | } | ||
1255 | |||
1256 | static int serial_hsu_runtime_idle(struct device *dev) | ||
1257 | { | ||
1258 | pm_schedule_suspend(dev, 500); | ||
1259 | return -EBUSY; | ||
1260 | } | ||
1261 | |||
1262 | static int serial_hsu_runtime_suspend(struct device *dev) | ||
1263 | { | ||
1264 | return 0; | ||
1265 | } | ||
1266 | |||
1267 | static int serial_hsu_runtime_resume(struct device *dev) | ||
1268 | { | ||
1269 | return 0; | ||
1270 | } | ||
1271 | #else | ||
1272 | #define serial_hsu_suspend NULL | ||
1273 | #define serial_hsu_resume NULL | ||
1274 | #define serial_hsu_runtime_idle NULL | ||
1275 | #define serial_hsu_runtime_suspend NULL | ||
1276 | #define serial_hsu_runtime_resume NULL | ||
1277 | #endif | ||
1278 | |||
1279 | static const struct dev_pm_ops serial_hsu_pm_ops = { | ||
1280 | .runtime_suspend = serial_hsu_runtime_suspend, | ||
1281 | .runtime_resume = serial_hsu_runtime_resume, | ||
1282 | .runtime_idle = serial_hsu_runtime_idle, | ||
1283 | }; | ||
1284 | |||
1285 | /* temp global pointer before we settle down on using one or four PCI dev */ | ||
1286 | static struct hsu_port *phsu; | ||
1287 | |||
1288 | static int serial_hsu_probe(struct pci_dev *pdev, | ||
1289 | const struct pci_device_id *ent) | ||
1290 | { | ||
1291 | struct uart_hsu_port *uport; | ||
1292 | int index, ret; | ||
1293 | |||
1294 | printk(KERN_INFO "HSU: found PCI Serial controller(ID: %04x:%04x)\n", | ||
1295 | pdev->vendor, pdev->device); | ||
1296 | |||
1297 | switch (pdev->device) { | ||
1298 | case 0x081B: | ||
1299 | index = 0; | ||
1300 | break; | ||
1301 | case 0x081C: | ||
1302 | index = 1; | ||
1303 | break; | ||
1304 | case 0x081D: | ||
1305 | index = 2; | ||
1306 | break; | ||
1307 | case 0x081E: | ||
1308 | /* internal DMA controller */ | ||
1309 | index = 3; | ||
1310 | break; | ||
1311 | default: | ||
1312 | dev_err(&pdev->dev, "HSU: out of index!"); | ||
1313 | return -ENODEV; | ||
1314 | } | ||
1315 | |||
1316 | ret = pci_enable_device(pdev); | ||
1317 | if (ret) | ||
1318 | return ret; | ||
1319 | |||
1320 | if (index == 3) { | ||
1321 | /* DMA controller */ | ||
1322 | ret = request_irq(pdev->irq, dma_irq, 0, "hsu_dma", phsu); | ||
1323 | if (ret) { | ||
1324 | dev_err(&pdev->dev, "can not get IRQ\n"); | ||
1325 | goto err_disable; | ||
1326 | } | ||
1327 | pci_set_drvdata(pdev, phsu); | ||
1328 | } else { | ||
1329 | /* UART port 0~2 */ | ||
1330 | uport = &phsu->port[index]; | ||
1331 | uport->port.irq = pdev->irq; | ||
1332 | uport->port.dev = &pdev->dev; | ||
1333 | uport->dev = &pdev->dev; | ||
1334 | |||
1335 | ret = request_irq(pdev->irq, port_irq, 0, uport->name, uport); | ||
1336 | if (ret) { | ||
1337 | dev_err(&pdev->dev, "can not get IRQ\n"); | ||
1338 | goto err_disable; | ||
1339 | } | ||
1340 | uart_add_one_port(&serial_hsu_reg, &uport->port); | ||
1341 | |||
1342 | pci_set_drvdata(pdev, uport); | ||
1343 | } | ||
1344 | |||
1345 | pm_runtime_put_noidle(&pdev->dev); | ||
1346 | pm_runtime_allow(&pdev->dev); | ||
1347 | |||
1348 | return 0; | ||
1349 | |||
1350 | err_disable: | ||
1351 | pci_disable_device(pdev); | ||
1352 | return ret; | ||
1353 | } | ||
1354 | |||
1355 | static void hsu_global_init(void) | ||
1356 | { | ||
1357 | struct hsu_port *hsu; | ||
1358 | struct uart_hsu_port *uport; | ||
1359 | struct hsu_dma_chan *dchan; | ||
1360 | int i, ret; | ||
1361 | |||
1362 | hsu = kzalloc(sizeof(struct hsu_port), GFP_KERNEL); | ||
1363 | if (!hsu) | ||
1364 | return; | ||
1365 | |||
1366 | /* Get basic io resource and map it */ | ||
1367 | hsu->paddr = 0xffa28000; | ||
1368 | hsu->iolen = 0x1000; | ||
1369 | |||
1370 | if (!(request_mem_region(hsu->paddr, hsu->iolen, "HSU global"))) | ||
1371 | pr_warn("HSU: error in request mem region\n"); | ||
1372 | |||
1373 | hsu->reg = ioremap_nocache((unsigned long)hsu->paddr, hsu->iolen); | ||
1374 | if (!hsu->reg) { | ||
1375 | pr_err("HSU: error in ioremap\n"); | ||
1376 | ret = -ENOMEM; | ||
1377 | goto err_free_region; | ||
1378 | } | ||
1379 | |||
1380 | /* Initialise the 3 UART ports */ | ||
1381 | uport = hsu->port; | ||
1382 | for (i = 0; i < 3; i++) { | ||
1383 | uport->port.type = PORT_MFD; | ||
1384 | uport->port.iotype = UPIO_MEM; | ||
1385 | uport->port.mapbase = (resource_size_t)hsu->paddr | ||
1386 | + HSU_PORT_REG_OFFSET | ||
1387 | + i * HSU_PORT_REG_LENGTH; | ||
1388 | uport->port.membase = hsu->reg + HSU_PORT_REG_OFFSET | ||
1389 | + i * HSU_PORT_REG_LENGTH; | ||
1390 | |||
1391 | sprintf(uport->name, "hsu_port%d", i); | ||
1392 | uport->port.fifosize = 64; | ||
1393 | uport->port.ops = &serial_hsu_pops; | ||
1394 | uport->port.line = i; | ||
1395 | uport->port.flags = UPF_IOREMAP; | ||
1396 | /* set the scalable maxim support rate to 2746800 bps */ | ||
1397 | uport->port.uartclk = 115200 * 24 * 16; | ||
1398 | |||
1399 | uport->running = 0; | ||
1400 | uport->txc = &hsu->chans[i * 2]; | ||
1401 | uport->rxc = &hsu->chans[i * 2 + 1]; | ||
1402 | |||
1403 | serial_hsu_ports[i] = uport; | ||
1404 | uport->index = i; | ||
1405 | |||
1406 | if (hsu_dma_enable & (1<<i)) | ||
1407 | uport->use_dma = 1; | ||
1408 | else | ||
1409 | uport->use_dma = 0; | ||
1410 | |||
1411 | uport++; | ||
1412 | } | ||
1413 | |||
1414 | /* Initialise 6 dma channels */ | ||
1415 | dchan = hsu->chans; | ||
1416 | for (i = 0; i < 6; i++) { | ||
1417 | dchan->id = i; | ||
1418 | dchan->dirt = (i & 0x1) ? DMA_FROM_DEVICE : DMA_TO_DEVICE; | ||
1419 | dchan->uport = &hsu->port[i/2]; | ||
1420 | dchan->reg = hsu->reg + HSU_DMA_CHANS_REG_OFFSET + | ||
1421 | i * HSU_DMA_CHANS_REG_LENGTH; | ||
1422 | |||
1423 | dchan++; | ||
1424 | } | ||
1425 | |||
1426 | phsu = hsu; | ||
1427 | hsu_debugfs_init(hsu); | ||
1428 | return; | ||
1429 | |||
1430 | err_free_region: | ||
1431 | release_mem_region(hsu->paddr, hsu->iolen); | ||
1432 | kfree(hsu); | ||
1433 | return; | ||
1434 | } | ||
1435 | |||
1436 | static void serial_hsu_remove(struct pci_dev *pdev) | ||
1437 | { | ||
1438 | void *priv = pci_get_drvdata(pdev); | ||
1439 | struct uart_hsu_port *up; | ||
1440 | |||
1441 | if (!priv) | ||
1442 | return; | ||
1443 | |||
1444 | pm_runtime_forbid(&pdev->dev); | ||
1445 | pm_runtime_get_noresume(&pdev->dev); | ||
1446 | |||
1447 | /* For port 0/1/2, priv is the address of uart_hsu_port */ | ||
1448 | if (pdev->device != 0x081E) { | ||
1449 | up = priv; | ||
1450 | uart_remove_one_port(&serial_hsu_reg, &up->port); | ||
1451 | } | ||
1452 | |||
1453 | free_irq(pdev->irq, priv); | ||
1454 | pci_disable_device(pdev); | ||
1455 | } | ||
1456 | |||
1457 | /* First 3 are UART ports, and the 4th is the DMA */ | ||
1458 | static const struct pci_device_id pci_ids[] = { | ||
1459 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081B) }, | ||
1460 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081C) }, | ||
1461 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081D) }, | ||
1462 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081E) }, | ||
1463 | {}, | ||
1464 | }; | ||
1465 | |||
1466 | static struct pci_driver hsu_pci_driver = { | ||
1467 | .name = "HSU serial", | ||
1468 | .id_table = pci_ids, | ||
1469 | .probe = serial_hsu_probe, | ||
1470 | .remove = serial_hsu_remove, | ||
1471 | .suspend = serial_hsu_suspend, | ||
1472 | .resume = serial_hsu_resume, | ||
1473 | .driver = { | ||
1474 | .pm = &serial_hsu_pm_ops, | ||
1475 | }, | ||
1476 | }; | ||
1477 | |||
1478 | static int __init hsu_pci_init(void) | ||
1479 | { | ||
1480 | int ret; | ||
1481 | |||
1482 | hsu_global_init(); | ||
1483 | |||
1484 | ret = uart_register_driver(&serial_hsu_reg); | ||
1485 | if (ret) | ||
1486 | return ret; | ||
1487 | |||
1488 | return pci_register_driver(&hsu_pci_driver); | ||
1489 | } | ||
1490 | |||
1491 | static void __exit hsu_pci_exit(void) | ||
1492 | { | ||
1493 | pci_unregister_driver(&hsu_pci_driver); | ||
1494 | uart_unregister_driver(&serial_hsu_reg); | ||
1495 | |||
1496 | hsu_debugfs_remove(phsu); | ||
1497 | |||
1498 | kfree(phsu); | ||
1499 | } | ||
1500 | |||
1501 | module_init(hsu_pci_init); | ||
1502 | module_exit(hsu_pci_exit); | ||
1503 | |||
1504 | MODULE_LICENSE("GPL v2"); | ||
1505 | MODULE_DEVICE_TABLE(pci, pci_ids); | ||
diff --git a/drivers/tty/serial/mpc52xx_uart.c b/drivers/tty/serial/mpc52xx_uart.c index 3308ef243dc3..1589f17c1fca 100644 --- a/drivers/tty/serial/mpc52xx_uart.c +++ b/drivers/tty/serial/mpc52xx_uart.c | |||
@@ -1717,7 +1717,7 @@ static struct uart_driver mpc52xx_uart_driver = { | |||
1717 | /* OF Platform Driver */ | 1717 | /* OF Platform Driver */ |
1718 | /* ======================================================================== */ | 1718 | /* ======================================================================== */ |
1719 | 1719 | ||
1720 | static struct of_device_id mpc52xx_uart_of_match[] = { | 1720 | static const struct of_device_id mpc52xx_uart_of_match[] = { |
1721 | #ifdef CONFIG_PPC_MPC52xx | 1721 | #ifdef CONFIG_PPC_MPC52xx |
1722 | { .compatible = "fsl,mpc5200b-psc-uart", .data = &mpc5200b_psc_ops, }, | 1722 | { .compatible = "fsl,mpc5200b-psc-uart", .data = &mpc5200b_psc_ops, }, |
1723 | { .compatible = "fsl,mpc5200-psc-uart", .data = &mpc52xx_psc_ops, }, | 1723 | { .compatible = "fsl,mpc5200-psc-uart", .data = &mpc52xx_psc_ops, }, |
diff --git a/drivers/tty/serial/msm_serial.h b/drivers/tty/serial/msm_serial.h index 3e1c7138d8cd..737f69fe7113 100644 --- a/drivers/tty/serial/msm_serial.h +++ b/drivers/tty/serial/msm_serial.h | |||
@@ -170,15 +170,6 @@ void msm_serial_set_mnd_regs_from_uartclk(struct uart_port *port) | |||
170 | msm_serial_set_mnd_regs_tcxoby4(port); | 170 | msm_serial_set_mnd_regs_tcxoby4(port); |
171 | } | 171 | } |
172 | 172 | ||
173 | /* | ||
174 | * TROUT has a specific defect that makes it report it's uartclk | ||
175 | * as 19.2Mhz (TCXO) when it's actually 4.8Mhz (TCXO/4). This special | ||
176 | * cases TROUT to use the right clock. | ||
177 | */ | ||
178 | #ifdef CONFIG_MACH_TROUT | ||
179 | #define msm_serial_set_mnd_regs msm_serial_set_mnd_regs_tcxoby4 | ||
180 | #else | ||
181 | #define msm_serial_set_mnd_regs msm_serial_set_mnd_regs_from_uartclk | 173 | #define msm_serial_set_mnd_regs msm_serial_set_mnd_regs_from_uartclk |
182 | #endif | ||
183 | 174 | ||
184 | #endif /* __DRIVERS_SERIAL_MSM_SERIAL_H */ | 175 | #endif /* __DRIVERS_SERIAL_MSM_SERIAL_H */ |
diff --git a/drivers/tty/serial/msm_serial_hs.c b/drivers/tty/serial/msm_serial_hs.c deleted file mode 100644 index 62da8534ba75..000000000000 --- a/drivers/tty/serial/msm_serial_hs.c +++ /dev/null | |||
@@ -1,1874 +0,0 @@ | |||
1 | /* | ||
2 | * MSM 7k/8k High speed uart driver | ||
3 | * | ||
4 | * Copyright (c) 2007-2011, Code Aurora Forum. All rights reserved. | ||
5 | * Copyright (c) 2008 Google Inc. | ||
6 | * Modified: Nick Pelly <npelly@google.com> | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or | ||
9 | * modify it under the terms of the GNU General Public License | ||
10 | * version 2 as published by the Free Software Foundation. | ||
11 | * | ||
12 | * This program is distributed in the hope that it will be useful, | ||
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | ||
15 | * See the GNU General Public License for more details. | ||
16 | * | ||
17 | * Has optional support for uart power management independent of linux | ||
18 | * suspend/resume: | ||
19 | * | ||
20 | * RX wakeup. | ||
21 | * UART wakeup can be triggered by RX activity (using a wakeup GPIO on the | ||
22 | * UART RX pin). This should only be used if there is not a wakeup | ||
23 | * GPIO on the UART CTS, and the first RX byte is known (for example, with the | ||
24 | * Bluetooth Texas Instruments HCILL protocol), since the first RX byte will | ||
25 | * always be lost. RTS will be asserted even while the UART is off in this mode | ||
26 | * of operation. See msm_serial_hs_platform_data.rx_wakeup_irq. | ||
27 | */ | ||
28 | |||
29 | #include <linux/module.h> | ||
30 | |||
31 | #include <linux/serial.h> | ||
32 | #include <linux/serial_core.h> | ||
33 | #include <linux/tty.h> | ||
34 | #include <linux/tty_flip.h> | ||
35 | #include <linux/slab.h> | ||
36 | #include <linux/init.h> | ||
37 | #include <linux/interrupt.h> | ||
38 | #include <linux/irq.h> | ||
39 | #include <linux/io.h> | ||
40 | #include <linux/ioport.h> | ||
41 | #include <linux/kernel.h> | ||
42 | #include <linux/timer.h> | ||
43 | #include <linux/clk.h> | ||
44 | #include <linux/platform_device.h> | ||
45 | #include <linux/pm_runtime.h> | ||
46 | #include <linux/dma-mapping.h> | ||
47 | #include <linux/dmapool.h> | ||
48 | #include <linux/wait.h> | ||
49 | #include <linux/workqueue.h> | ||
50 | |||
51 | #include <linux/atomic.h> | ||
52 | #include <asm/irq.h> | ||
53 | |||
54 | #include <mach/hardware.h> | ||
55 | #include <mach/dma.h> | ||
56 | #include <linux/platform_data/msm_serial_hs.h> | ||
57 | |||
58 | /* HSUART Registers */ | ||
59 | #define UARTDM_MR1_ADDR 0x0 | ||
60 | #define UARTDM_MR2_ADDR 0x4 | ||
61 | |||
62 | /* Data Mover result codes */ | ||
63 | #define RSLT_FIFO_CNTR_BMSK (0xE << 28) | ||
64 | #define RSLT_VLD BIT(1) | ||
65 | |||
66 | /* write only register */ | ||
67 | #define UARTDM_CSR_ADDR 0x8 | ||
68 | #define UARTDM_CSR_115200 0xFF | ||
69 | #define UARTDM_CSR_57600 0xEE | ||
70 | #define UARTDM_CSR_38400 0xDD | ||
71 | #define UARTDM_CSR_28800 0xCC | ||
72 | #define UARTDM_CSR_19200 0xBB | ||
73 | #define UARTDM_CSR_14400 0xAA | ||
74 | #define UARTDM_CSR_9600 0x99 | ||
75 | #define UARTDM_CSR_7200 0x88 | ||
76 | #define UARTDM_CSR_4800 0x77 | ||
77 | #define UARTDM_CSR_3600 0x66 | ||
78 | #define UARTDM_CSR_2400 0x55 | ||
79 | #define UARTDM_CSR_1200 0x44 | ||
80 | #define UARTDM_CSR_600 0x33 | ||
81 | #define UARTDM_CSR_300 0x22 | ||
82 | #define UARTDM_CSR_150 0x11 | ||
83 | #define UARTDM_CSR_75 0x00 | ||
84 | |||
85 | /* write only register */ | ||
86 | #define UARTDM_TF_ADDR 0x70 | ||
87 | #define UARTDM_TF2_ADDR 0x74 | ||
88 | #define UARTDM_TF3_ADDR 0x78 | ||
89 | #define UARTDM_TF4_ADDR 0x7C | ||
90 | |||
91 | /* write only register */ | ||
92 | #define UARTDM_CR_ADDR 0x10 | ||
93 | #define UARTDM_IMR_ADDR 0x14 | ||
94 | |||
95 | #define UARTDM_IPR_ADDR 0x18 | ||
96 | #define UARTDM_TFWR_ADDR 0x1c | ||
97 | #define UARTDM_RFWR_ADDR 0x20 | ||
98 | #define UARTDM_HCR_ADDR 0x24 | ||
99 | #define UARTDM_DMRX_ADDR 0x34 | ||
100 | #define UARTDM_IRDA_ADDR 0x38 | ||
101 | #define UARTDM_DMEN_ADDR 0x3c | ||
102 | |||
103 | /* UART_DM_NO_CHARS_FOR_TX */ | ||
104 | #define UARTDM_NCF_TX_ADDR 0x40 | ||
105 | |||
106 | #define UARTDM_BADR_ADDR 0x44 | ||
107 | |||
108 | #define UARTDM_SIM_CFG_ADDR 0x80 | ||
109 | /* Read Only register */ | ||
110 | #define UARTDM_SR_ADDR 0x8 | ||
111 | |||
112 | /* Read Only register */ | ||
113 | #define UARTDM_RF_ADDR 0x70 | ||
114 | #define UARTDM_RF2_ADDR 0x74 | ||
115 | #define UARTDM_RF3_ADDR 0x78 | ||
116 | #define UARTDM_RF4_ADDR 0x7C | ||
117 | |||
118 | /* Read Only register */ | ||
119 | #define UARTDM_MISR_ADDR 0x10 | ||
120 | |||
121 | /* Read Only register */ | ||
122 | #define UARTDM_ISR_ADDR 0x14 | ||
123 | #define UARTDM_RX_TOTAL_SNAP_ADDR 0x38 | ||
124 | |||
125 | #define UARTDM_RXFS_ADDR 0x50 | ||
126 | |||
127 | /* Register field Mask Mapping */ | ||
128 | #define UARTDM_SR_PAR_FRAME_BMSK BIT(5) | ||
129 | #define UARTDM_SR_OVERRUN_BMSK BIT(4) | ||
130 | #define UARTDM_SR_TXEMT_BMSK BIT(3) | ||
131 | #define UARTDM_SR_TXRDY_BMSK BIT(2) | ||
132 | #define UARTDM_SR_RXRDY_BMSK BIT(0) | ||
133 | |||
134 | #define UARTDM_CR_TX_DISABLE_BMSK BIT(3) | ||
135 | #define UARTDM_CR_RX_DISABLE_BMSK BIT(1) | ||
136 | #define UARTDM_CR_TX_EN_BMSK BIT(2) | ||
137 | #define UARTDM_CR_RX_EN_BMSK BIT(0) | ||
138 | |||
139 | /* UARTDM_CR channel_comman bit value (register field is bits 8:4) */ | ||
140 | #define RESET_RX 0x10 | ||
141 | #define RESET_TX 0x20 | ||
142 | #define RESET_ERROR_STATUS 0x30 | ||
143 | #define RESET_BREAK_INT 0x40 | ||
144 | #define START_BREAK 0x50 | ||
145 | #define STOP_BREAK 0x60 | ||
146 | #define RESET_CTS 0x70 | ||
147 | #define RESET_STALE_INT 0x80 | ||
148 | #define RFR_LOW 0xD0 | ||
149 | #define RFR_HIGH 0xE0 | ||
150 | #define CR_PROTECTION_EN 0x100 | ||
151 | #define STALE_EVENT_ENABLE 0x500 | ||
152 | #define STALE_EVENT_DISABLE 0x600 | ||
153 | #define FORCE_STALE_EVENT 0x400 | ||
154 | #define CLEAR_TX_READY 0x300 | ||
155 | #define RESET_TX_ERROR 0x800 | ||
156 | #define RESET_TX_DONE 0x810 | ||
157 | |||
158 | #define UARTDM_MR1_AUTO_RFR_LEVEL1_BMSK 0xffffff00 | ||
159 | #define UARTDM_MR1_AUTO_RFR_LEVEL0_BMSK 0x3f | ||
160 | #define UARTDM_MR1_CTS_CTL_BMSK 0x40 | ||
161 | #define UARTDM_MR1_RX_RDY_CTL_BMSK 0x80 | ||
162 | |||
163 | #define UARTDM_MR2_ERROR_MODE_BMSK 0x40 | ||
164 | #define UARTDM_MR2_BITS_PER_CHAR_BMSK 0x30 | ||
165 | |||
166 | /* bits per character configuration */ | ||
167 | #define FIVE_BPC (0 << 4) | ||
168 | #define SIX_BPC (1 << 4) | ||
169 | #define SEVEN_BPC (2 << 4) | ||
170 | #define EIGHT_BPC (3 << 4) | ||
171 | |||
172 | #define UARTDM_MR2_STOP_BIT_LEN_BMSK 0xc | ||
173 | #define STOP_BIT_ONE (1 << 2) | ||
174 | #define STOP_BIT_TWO (3 << 2) | ||
175 | |||
176 | #define UARTDM_MR2_PARITY_MODE_BMSK 0x3 | ||
177 | |||
178 | /* Parity configuration */ | ||
179 | #define NO_PARITY 0x0 | ||
180 | #define EVEN_PARITY 0x1 | ||
181 | #define ODD_PARITY 0x2 | ||
182 | #define SPACE_PARITY 0x3 | ||
183 | |||
184 | #define UARTDM_IPR_STALE_TIMEOUT_MSB_BMSK 0xffffff80 | ||
185 | #define UARTDM_IPR_STALE_LSB_BMSK 0x1f | ||
186 | |||
187 | /* These can be used for both ISR and IMR register */ | ||
188 | #define UARTDM_ISR_TX_READY_BMSK BIT(7) | ||
189 | #define UARTDM_ISR_CURRENT_CTS_BMSK BIT(6) | ||
190 | #define UARTDM_ISR_DELTA_CTS_BMSK BIT(5) | ||
191 | #define UARTDM_ISR_RXLEV_BMSK BIT(4) | ||
192 | #define UARTDM_ISR_RXSTALE_BMSK BIT(3) | ||
193 | #define UARTDM_ISR_RXBREAK_BMSK BIT(2) | ||
194 | #define UARTDM_ISR_RXHUNT_BMSK BIT(1) | ||
195 | #define UARTDM_ISR_TXLEV_BMSK BIT(0) | ||
196 | |||
197 | /* Field definitions for UART_DM_DMEN*/ | ||
198 | #define UARTDM_TX_DM_EN_BMSK 0x1 | ||
199 | #define UARTDM_RX_DM_EN_BMSK 0x2 | ||
200 | |||
201 | #define UART_FIFOSIZE 64 | ||
202 | #define UARTCLK 7372800 | ||
203 | |||
204 | /* Rx DMA request states */ | ||
205 | enum flush_reason { | ||
206 | FLUSH_NONE, | ||
207 | FLUSH_DATA_READY, | ||
208 | FLUSH_DATA_INVALID, /* values after this indicate invalid data */ | ||
209 | FLUSH_IGNORE = FLUSH_DATA_INVALID, | ||
210 | FLUSH_STOP, | ||
211 | FLUSH_SHUTDOWN, | ||
212 | }; | ||
213 | |||
214 | /* UART clock states */ | ||
215 | enum msm_hs_clk_states_e { | ||
216 | MSM_HS_CLK_PORT_OFF, /* port not in use */ | ||
217 | MSM_HS_CLK_OFF, /* clock disabled */ | ||
218 | MSM_HS_CLK_REQUEST_OFF, /* disable after TX and RX flushed */ | ||
219 | MSM_HS_CLK_ON, /* clock enabled */ | ||
220 | }; | ||
221 | |||
222 | /* Track the forced RXSTALE flush during clock off sequence. | ||
223 | * These states are only valid during MSM_HS_CLK_REQUEST_OFF */ | ||
224 | enum msm_hs_clk_req_off_state_e { | ||
225 | CLK_REQ_OFF_START, | ||
226 | CLK_REQ_OFF_RXSTALE_ISSUED, | ||
227 | CLK_REQ_OFF_FLUSH_ISSUED, | ||
228 | CLK_REQ_OFF_RXSTALE_FLUSHED, | ||
229 | }; | ||
230 | |||
231 | /** | ||
232 | * struct msm_hs_tx | ||
233 | * @tx_ready_int_en: ok to dma more tx? | ||
234 | * @dma_in_flight: tx dma in progress | ||
235 | * @xfer: top level DMA command pointer structure | ||
236 | * @command_ptr: third level command struct pointer | ||
237 | * @command_ptr_ptr: second level command list struct pointer | ||
238 | * @mapped_cmd_ptr: DMA view of third level command struct | ||
239 | * @mapped_cmd_ptr_ptr: DMA view of second level command list struct | ||
240 | * @tx_count: number of bytes to transfer in DMA transfer | ||
241 | * @dma_base: DMA view of UART xmit buffer | ||
242 | * | ||
243 | * This structure describes a single Tx DMA transaction. MSM DMA | ||
244 | * commands have two levels of indirection. The top level command | ||
245 | * ptr points to a list of command ptr which in turn points to a | ||
246 | * single DMA 'command'. In our case each Tx transaction consists | ||
247 | * of a single second level pointer pointing to a 'box type' command. | ||
248 | */ | ||
249 | struct msm_hs_tx { | ||
250 | unsigned int tx_ready_int_en; | ||
251 | unsigned int dma_in_flight; | ||
252 | struct msm_dmov_cmd xfer; | ||
253 | dmov_box *command_ptr; | ||
254 | u32 *command_ptr_ptr; | ||
255 | dma_addr_t mapped_cmd_ptr; | ||
256 | dma_addr_t mapped_cmd_ptr_ptr; | ||
257 | int tx_count; | ||
258 | dma_addr_t dma_base; | ||
259 | }; | ||
260 | |||
261 | /** | ||
262 | * struct msm_hs_rx | ||
263 | * @flush: Rx DMA request state | ||
264 | * @xfer: top level DMA command pointer structure | ||
265 | * @cmdptr_dmaaddr: DMA view of second level command structure | ||
266 | * @command_ptr: third level DMA command pointer structure | ||
267 | * @command_ptr_ptr: second level DMA command list pointer | ||
268 | * @mapped_cmd_ptr: DMA view of the third level command structure | ||
269 | * @wait: wait for DMA completion before shutdown | ||
270 | * @buffer: destination buffer for RX DMA | ||
271 | * @rbuffer: DMA view of buffer | ||
272 | * @pool: dma pool out of which coherent rx buffer is allocated | ||
273 | * @tty_work: private work-queue for tty flip buffer push task | ||
274 | * | ||
275 | * This structure describes a single Rx DMA transaction. Rx DMA | ||
276 | * transactions use box mode DMA commands. | ||
277 | */ | ||
278 | struct msm_hs_rx { | ||
279 | enum flush_reason flush; | ||
280 | struct msm_dmov_cmd xfer; | ||
281 | dma_addr_t cmdptr_dmaaddr; | ||
282 | dmov_box *command_ptr; | ||
283 | u32 *command_ptr_ptr; | ||
284 | dma_addr_t mapped_cmd_ptr; | ||
285 | wait_queue_head_t wait; | ||
286 | dma_addr_t rbuffer; | ||
287 | unsigned char *buffer; | ||
288 | struct dma_pool *pool; | ||
289 | struct work_struct tty_work; | ||
290 | }; | ||
291 | |||
292 | /** | ||
293 | * struct msm_hs_rx_wakeup | ||
294 | * @irq: IRQ line to be configured as interrupt source on Rx activity | ||
295 | * @ignore: boolean value. 1 = ignore the wakeup interrupt | ||
296 | * @rx_to_inject: extra character to be inserted to Rx tty on wakeup | ||
297 | * @inject_rx: 1 = insert rx_to_inject. 0 = do not insert extra character | ||
298 | * | ||
299 | * This is an optional structure required for UART Rx GPIO IRQ based | ||
300 | * wakeup from low power state. UART wakeup can be triggered by RX activity | ||
301 | * (using a wakeup GPIO on the UART RX pin). This should only be used if | ||
302 | * there is not a wakeup GPIO on the UART CTS, and the first RX byte is | ||
303 | * known (eg., with the Bluetooth Texas Instruments HCILL protocol), | ||
304 | * since the first RX byte will always be lost. RTS will be asserted even | ||
305 | * while the UART is clocked off in this mode of operation. | ||
306 | */ | ||
307 | struct msm_hs_rx_wakeup { | ||
308 | int irq; /* < 0 indicates low power wakeup disabled */ | ||
309 | unsigned char ignore; | ||
310 | unsigned char inject_rx; | ||
311 | char rx_to_inject; | ||
312 | }; | ||
313 | |||
314 | /** | ||
315 | * struct msm_hs_port | ||
316 | * @uport: embedded uart port structure | ||
317 | * @imr_reg: shadow value of UARTDM_IMR | ||
318 | * @clk: uart input clock handle | ||
319 | * @tx: Tx transaction related data structure | ||
320 | * @rx: Rx transaction related data structure | ||
321 | * @dma_tx_channel: Tx DMA command channel | ||
322 | * @dma_rx_channel Rx DMA command channel | ||
323 | * @dma_tx_crci: Tx channel rate control interface number | ||
324 | * @dma_rx_crci: Rx channel rate control interface number | ||
325 | * @clk_off_timer: Timer to poll DMA event completion before clock off | ||
326 | * @clk_off_delay: clk_off_timer poll interval | ||
327 | * @clk_state: overall clock state | ||
328 | * @clk_req_off_state: post flush clock states | ||
329 | * @rx_wakeup: optional rx_wakeup feature related data | ||
330 | * @exit_lpm_cb: optional callback to exit low power mode | ||
331 | * | ||
332 | * Low level serial port structure. | ||
333 | */ | ||
334 | struct msm_hs_port { | ||
335 | struct uart_port uport; | ||
336 | unsigned long imr_reg; | ||
337 | struct clk *clk; | ||
338 | struct msm_hs_tx tx; | ||
339 | struct msm_hs_rx rx; | ||
340 | |||
341 | int dma_tx_channel; | ||
342 | int dma_rx_channel; | ||
343 | int dma_tx_crci; | ||
344 | int dma_rx_crci; | ||
345 | |||
346 | struct hrtimer clk_off_timer; | ||
347 | ktime_t clk_off_delay; | ||
348 | enum msm_hs_clk_states_e clk_state; | ||
349 | enum msm_hs_clk_req_off_state_e clk_req_off_state; | ||
350 | |||
351 | struct msm_hs_rx_wakeup rx_wakeup; | ||
352 | void (*exit_lpm_cb)(struct uart_port *); | ||
353 | }; | ||
354 | |||
355 | #define MSM_UARTDM_BURST_SIZE 16 /* DM burst size (in bytes) */ | ||
356 | #define UARTDM_TX_BUF_SIZE UART_XMIT_SIZE | ||
357 | #define UARTDM_RX_BUF_SIZE 512 | ||
358 | |||
359 | #define UARTDM_NR 2 | ||
360 | |||
361 | static struct msm_hs_port q_uart_port[UARTDM_NR]; | ||
362 | static struct platform_driver msm_serial_hs_platform_driver; | ||
363 | static struct uart_driver msm_hs_driver; | ||
364 | static struct uart_ops msm_hs_ops; | ||
365 | static struct workqueue_struct *msm_hs_workqueue; | ||
366 | |||
367 | #define UARTDM_TO_MSM(uart_port) \ | ||
368 | container_of((uart_port), struct msm_hs_port, uport) | ||
369 | |||
370 | static unsigned int use_low_power_rx_wakeup(struct msm_hs_port | ||
371 | *msm_uport) | ||
372 | { | ||
373 | return (msm_uport->rx_wakeup.irq >= 0); | ||
374 | } | ||
375 | |||
376 | static unsigned int msm_hs_read(struct uart_port *uport, | ||
377 | unsigned int offset) | ||
378 | { | ||
379 | return ioread32(uport->membase + offset); | ||
380 | } | ||
381 | |||
382 | static void msm_hs_write(struct uart_port *uport, unsigned int offset, | ||
383 | unsigned int value) | ||
384 | { | ||
385 | iowrite32(value, uport->membase + offset); | ||
386 | } | ||
387 | |||
388 | static void msm_hs_release_port(struct uart_port *port) | ||
389 | { | ||
390 | iounmap(port->membase); | ||
391 | } | ||
392 | |||
393 | static int msm_hs_request_port(struct uart_port *port) | ||
394 | { | ||
395 | port->membase = ioremap(port->mapbase, PAGE_SIZE); | ||
396 | if (unlikely(!port->membase)) | ||
397 | return -ENOMEM; | ||
398 | |||
399 | /* configure the CR Protection to Enable */ | ||
400 | msm_hs_write(port, UARTDM_CR_ADDR, CR_PROTECTION_EN); | ||
401 | return 0; | ||
402 | } | ||
403 | |||
404 | static int msm_hs_remove(struct platform_device *pdev) | ||
405 | { | ||
406 | |||
407 | struct msm_hs_port *msm_uport; | ||
408 | struct device *dev; | ||
409 | |||
410 | if (pdev->id < 0 || pdev->id >= UARTDM_NR) { | ||
411 | printk(KERN_ERR "Invalid plaform device ID = %d\n", pdev->id); | ||
412 | return -EINVAL; | ||
413 | } | ||
414 | |||
415 | msm_uport = &q_uart_port[pdev->id]; | ||
416 | dev = msm_uport->uport.dev; | ||
417 | |||
418 | dma_unmap_single(dev, msm_uport->rx.mapped_cmd_ptr, sizeof(dmov_box), | ||
419 | DMA_TO_DEVICE); | ||
420 | dma_pool_free(msm_uport->rx.pool, msm_uport->rx.buffer, | ||
421 | msm_uport->rx.rbuffer); | ||
422 | dma_pool_destroy(msm_uport->rx.pool); | ||
423 | |||
424 | dma_unmap_single(dev, msm_uport->rx.cmdptr_dmaaddr, sizeof(u32), | ||
425 | DMA_TO_DEVICE); | ||
426 | dma_unmap_single(dev, msm_uport->tx.mapped_cmd_ptr_ptr, sizeof(u32), | ||
427 | DMA_TO_DEVICE); | ||
428 | dma_unmap_single(dev, msm_uport->tx.mapped_cmd_ptr, sizeof(dmov_box), | ||
429 | DMA_TO_DEVICE); | ||
430 | |||
431 | uart_remove_one_port(&msm_hs_driver, &msm_uport->uport); | ||
432 | clk_put(msm_uport->clk); | ||
433 | |||
434 | /* Free the tx resources */ | ||
435 | kfree(msm_uport->tx.command_ptr); | ||
436 | kfree(msm_uport->tx.command_ptr_ptr); | ||
437 | |||
438 | /* Free the rx resources */ | ||
439 | kfree(msm_uport->rx.command_ptr); | ||
440 | kfree(msm_uport->rx.command_ptr_ptr); | ||
441 | |||
442 | iounmap(msm_uport->uport.membase); | ||
443 | |||
444 | return 0; | ||
445 | } | ||
446 | |||
447 | static int msm_hs_init_clk_locked(struct uart_port *uport) | ||
448 | { | ||
449 | int ret; | ||
450 | struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); | ||
451 | |||
452 | ret = clk_enable(msm_uport->clk); | ||
453 | if (ret) { | ||
454 | printk(KERN_ERR "Error could not turn on UART clk\n"); | ||
455 | return ret; | ||
456 | } | ||
457 | |||
458 | /* Set up the MREG/NREG/DREG/MNDREG */ | ||
459 | ret = clk_set_rate(msm_uport->clk, uport->uartclk); | ||
460 | if (ret) { | ||
461 | printk(KERN_WARNING "Error setting clock rate on UART\n"); | ||
462 | clk_disable(msm_uport->clk); | ||
463 | return ret; | ||
464 | } | ||
465 | |||
466 | msm_uport->clk_state = MSM_HS_CLK_ON; | ||
467 | return 0; | ||
468 | } | ||
469 | |||
470 | /* Enable and Disable clocks (Used for power management) */ | ||
471 | static void msm_hs_pm(struct uart_port *uport, unsigned int state, | ||
472 | unsigned int oldstate) | ||
473 | { | ||
474 | struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); | ||
475 | |||
476 | if (use_low_power_rx_wakeup(msm_uport) || | ||
477 | msm_uport->exit_lpm_cb) | ||
478 | return; /* ignore linux PM states, | ||
479 | use msm_hs_request_clock API */ | ||
480 | |||
481 | switch (state) { | ||
482 | case 0: | ||
483 | clk_enable(msm_uport->clk); | ||
484 | break; | ||
485 | case 3: | ||
486 | clk_disable(msm_uport->clk); | ||
487 | break; | ||
488 | default: | ||
489 | dev_err(uport->dev, "msm_serial: Unknown PM state %d\n", | ||
490 | state); | ||
491 | } | ||
492 | } | ||
493 | |||
494 | /* | ||
495 | * programs the UARTDM_CSR register with correct bit rates | ||
496 | * | ||
497 | * Interrupts should be disabled before we are called, as | ||
498 | * we modify Set Baud rate | ||
499 | * Set receive stale interrupt level, dependent on Bit Rate | ||
500 | * Goal is to have around 8 ms before indicate stale. | ||
501 | * roundup (((Bit Rate * .008) / 10) + 1 | ||
502 | */ | ||
503 | static void msm_hs_set_bps_locked(struct uart_port *uport, | ||
504 | unsigned int bps) | ||
505 | { | ||
506 | unsigned long rxstale; | ||
507 | unsigned long data; | ||
508 | struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); | ||
509 | |||
510 | switch (bps) { | ||
511 | case 300: | ||
512 | msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_75); | ||
513 | rxstale = 1; | ||
514 | break; | ||
515 | case 600: | ||
516 | msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_150); | ||
517 | rxstale = 1; | ||
518 | break; | ||
519 | case 1200: | ||
520 | msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_300); | ||
521 | rxstale = 1; | ||
522 | break; | ||
523 | case 2400: | ||
524 | msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_600); | ||
525 | rxstale = 1; | ||
526 | break; | ||
527 | case 4800: | ||
528 | msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_1200); | ||
529 | rxstale = 1; | ||
530 | break; | ||
531 | case 9600: | ||
532 | msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_2400); | ||
533 | rxstale = 2; | ||
534 | break; | ||
535 | case 14400: | ||
536 | msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_3600); | ||
537 | rxstale = 3; | ||
538 | break; | ||
539 | case 19200: | ||
540 | msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_4800); | ||
541 | rxstale = 4; | ||
542 | break; | ||
543 | case 28800: | ||
544 | msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_7200); | ||
545 | rxstale = 6; | ||
546 | break; | ||
547 | case 38400: | ||
548 | msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_9600); | ||
549 | rxstale = 8; | ||
550 | break; | ||
551 | case 57600: | ||
552 | msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_14400); | ||
553 | rxstale = 16; | ||
554 | break; | ||
555 | case 76800: | ||
556 | msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_19200); | ||
557 | rxstale = 16; | ||
558 | break; | ||
559 | case 115200: | ||
560 | msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_28800); | ||
561 | rxstale = 31; | ||
562 | break; | ||
563 | case 230400: | ||
564 | msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_57600); | ||
565 | rxstale = 31; | ||
566 | break; | ||
567 | case 460800: | ||
568 | msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_115200); | ||
569 | rxstale = 31; | ||
570 | break; | ||
571 | case 4000000: | ||
572 | case 3686400: | ||
573 | case 3200000: | ||
574 | case 3500000: | ||
575 | case 3000000: | ||
576 | case 2500000: | ||
577 | case 1500000: | ||
578 | case 1152000: | ||
579 | case 1000000: | ||
580 | case 921600: | ||
581 | msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_115200); | ||
582 | rxstale = 31; | ||
583 | break; | ||
584 | default: | ||
585 | msm_hs_write(uport, UARTDM_CSR_ADDR, UARTDM_CSR_2400); | ||
586 | /* default to 9600 */ | ||
587 | bps = 9600; | ||
588 | rxstale = 2; | ||
589 | break; | ||
590 | } | ||
591 | if (bps > 460800) | ||
592 | uport->uartclk = bps * 16; | ||
593 | else | ||
594 | uport->uartclk = UARTCLK; | ||
595 | |||
596 | if (clk_set_rate(msm_uport->clk, uport->uartclk)) { | ||
597 | printk(KERN_WARNING "Error setting clock rate on UART\n"); | ||
598 | return; | ||
599 | } | ||
600 | |||
601 | data = rxstale & UARTDM_IPR_STALE_LSB_BMSK; | ||
602 | data |= UARTDM_IPR_STALE_TIMEOUT_MSB_BMSK & (rxstale << 2); | ||
603 | |||
604 | msm_hs_write(uport, UARTDM_IPR_ADDR, data); | ||
605 | } | ||
606 | |||
607 | /* | ||
608 | * termios : new ktermios | ||
609 | * oldtermios: old ktermios previous setting | ||
610 | * | ||
611 | * Configure the serial port | ||
612 | */ | ||
613 | static void msm_hs_set_termios(struct uart_port *uport, | ||
614 | struct ktermios *termios, | ||
615 | struct ktermios *oldtermios) | ||
616 | { | ||
617 | unsigned int bps; | ||
618 | unsigned long data; | ||
619 | unsigned long flags; | ||
620 | unsigned int c_cflag = termios->c_cflag; | ||
621 | struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); | ||
622 | |||
623 | spin_lock_irqsave(&uport->lock, flags); | ||
624 | clk_enable(msm_uport->clk); | ||
625 | |||
626 | /* 300 is the minimum baud support by the driver */ | ||
627 | bps = uart_get_baud_rate(uport, termios, oldtermios, 200, 4000000); | ||
628 | |||
629 | /* Temporary remapping 200 BAUD to 3.2 mbps */ | ||
630 | if (bps == 200) | ||
631 | bps = 3200000; | ||
632 | |||
633 | msm_hs_set_bps_locked(uport, bps); | ||
634 | |||
635 | data = msm_hs_read(uport, UARTDM_MR2_ADDR); | ||
636 | data &= ~UARTDM_MR2_PARITY_MODE_BMSK; | ||
637 | /* set parity */ | ||
638 | if (PARENB == (c_cflag & PARENB)) { | ||
639 | if (PARODD == (c_cflag & PARODD)) | ||
640 | data |= ODD_PARITY; | ||
641 | else if (CMSPAR == (c_cflag & CMSPAR)) | ||
642 | data |= SPACE_PARITY; | ||
643 | else | ||
644 | data |= EVEN_PARITY; | ||
645 | } | ||
646 | |||
647 | /* Set bits per char */ | ||
648 | data &= ~UARTDM_MR2_BITS_PER_CHAR_BMSK; | ||
649 | |||
650 | switch (c_cflag & CSIZE) { | ||
651 | case CS5: | ||
652 | data |= FIVE_BPC; | ||
653 | break; | ||
654 | case CS6: | ||
655 | data |= SIX_BPC; | ||
656 | break; | ||
657 | case CS7: | ||
658 | data |= SEVEN_BPC; | ||
659 | break; | ||
660 | default: | ||
661 | data |= EIGHT_BPC; | ||
662 | break; | ||
663 | } | ||
664 | /* stop bits */ | ||
665 | if (c_cflag & CSTOPB) { | ||
666 | data |= STOP_BIT_TWO; | ||
667 | } else { | ||
668 | /* otherwise 1 stop bit */ | ||
669 | data |= STOP_BIT_ONE; | ||
670 | } | ||
671 | data |= UARTDM_MR2_ERROR_MODE_BMSK; | ||
672 | /* write parity/bits per char/stop bit configuration */ | ||
673 | msm_hs_write(uport, UARTDM_MR2_ADDR, data); | ||
674 | |||
675 | /* Configure HW flow control */ | ||
676 | data = msm_hs_read(uport, UARTDM_MR1_ADDR); | ||
677 | |||
678 | data &= ~(UARTDM_MR1_CTS_CTL_BMSK | UARTDM_MR1_RX_RDY_CTL_BMSK); | ||
679 | |||
680 | if (c_cflag & CRTSCTS) { | ||
681 | data |= UARTDM_MR1_CTS_CTL_BMSK; | ||
682 | data |= UARTDM_MR1_RX_RDY_CTL_BMSK; | ||
683 | } | ||
684 | |||
685 | msm_hs_write(uport, UARTDM_MR1_ADDR, data); | ||
686 | |||
687 | uport->ignore_status_mask = termios->c_iflag & INPCK; | ||
688 | uport->ignore_status_mask |= termios->c_iflag & IGNPAR; | ||
689 | uport->read_status_mask = (termios->c_cflag & CREAD); | ||
690 | |||
691 | msm_hs_write(uport, UARTDM_IMR_ADDR, 0); | ||
692 | |||
693 | /* Set Transmit software time out */ | ||
694 | uart_update_timeout(uport, c_cflag, bps); | ||
695 | |||
696 | msm_hs_write(uport, UARTDM_CR_ADDR, RESET_RX); | ||
697 | msm_hs_write(uport, UARTDM_CR_ADDR, RESET_TX); | ||
698 | |||
699 | if (msm_uport->rx.flush == FLUSH_NONE) { | ||
700 | msm_uport->rx.flush = FLUSH_IGNORE; | ||
701 | msm_dmov_stop_cmd(msm_uport->dma_rx_channel, NULL, 1); | ||
702 | } | ||
703 | |||
704 | msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg); | ||
705 | |||
706 | clk_disable(msm_uport->clk); | ||
707 | spin_unlock_irqrestore(&uport->lock, flags); | ||
708 | } | ||
709 | |||
710 | /* | ||
711 | * Standard API, Transmitter | ||
712 | * Any character in the transmit shift register is sent | ||
713 | */ | ||
714 | static unsigned int msm_hs_tx_empty(struct uart_port *uport) | ||
715 | { | ||
716 | unsigned int data; | ||
717 | unsigned int ret = 0; | ||
718 | struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); | ||
719 | |||
720 | clk_enable(msm_uport->clk); | ||
721 | |||
722 | data = msm_hs_read(uport, UARTDM_SR_ADDR); | ||
723 | if (data & UARTDM_SR_TXEMT_BMSK) | ||
724 | ret = TIOCSER_TEMT; | ||
725 | |||
726 | clk_disable(msm_uport->clk); | ||
727 | |||
728 | return ret; | ||
729 | } | ||
730 | |||
731 | /* | ||
732 | * Standard API, Stop transmitter. | ||
733 | * Any character in the transmit shift register is sent as | ||
734 | * well as the current data mover transfer . | ||
735 | */ | ||
736 | static void msm_hs_stop_tx_locked(struct uart_port *uport) | ||
737 | { | ||
738 | struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); | ||
739 | |||
740 | msm_uport->tx.tx_ready_int_en = 0; | ||
741 | } | ||
742 | |||
743 | /* | ||
744 | * Standard API, Stop receiver as soon as possible. | ||
745 | * | ||
746 | * Function immediately terminates the operation of the | ||
747 | * channel receiver and any incoming characters are lost. None | ||
748 | * of the receiver status bits are affected by this command and | ||
749 | * characters that are already in the receive FIFO there. | ||
750 | */ | ||
751 | static void msm_hs_stop_rx_locked(struct uart_port *uport) | ||
752 | { | ||
753 | struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); | ||
754 | unsigned int data; | ||
755 | |||
756 | clk_enable(msm_uport->clk); | ||
757 | |||
758 | /* disable dlink */ | ||
759 | data = msm_hs_read(uport, UARTDM_DMEN_ADDR); | ||
760 | data &= ~UARTDM_RX_DM_EN_BMSK; | ||
761 | msm_hs_write(uport, UARTDM_DMEN_ADDR, data); | ||
762 | |||
763 | /* Disable the receiver */ | ||
764 | if (msm_uport->rx.flush == FLUSH_NONE) | ||
765 | msm_dmov_stop_cmd(msm_uport->dma_rx_channel, NULL, 1); | ||
766 | |||
767 | if (msm_uport->rx.flush != FLUSH_SHUTDOWN) | ||
768 | msm_uport->rx.flush = FLUSH_STOP; | ||
769 | |||
770 | clk_disable(msm_uport->clk); | ||
771 | } | ||
772 | |||
773 | /* Transmit the next chunk of data */ | ||
774 | static void msm_hs_submit_tx_locked(struct uart_port *uport) | ||
775 | { | ||
776 | int left; | ||
777 | int tx_count; | ||
778 | dma_addr_t src_addr; | ||
779 | struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); | ||
780 | struct msm_hs_tx *tx = &msm_uport->tx; | ||
781 | struct circ_buf *tx_buf = &msm_uport->uport.state->xmit; | ||
782 | |||
783 | if (uart_circ_empty(tx_buf) || uport->state->port.tty->stopped) { | ||
784 | msm_hs_stop_tx_locked(uport); | ||
785 | return; | ||
786 | } | ||
787 | |||
788 | tx->dma_in_flight = 1; | ||
789 | |||
790 | tx_count = uart_circ_chars_pending(tx_buf); | ||
791 | |||
792 | if (UARTDM_TX_BUF_SIZE < tx_count) | ||
793 | tx_count = UARTDM_TX_BUF_SIZE; | ||
794 | |||
795 | left = UART_XMIT_SIZE - tx_buf->tail; | ||
796 | |||
797 | if (tx_count > left) | ||
798 | tx_count = left; | ||
799 | |||
800 | src_addr = tx->dma_base + tx_buf->tail; | ||
801 | dma_sync_single_for_device(uport->dev, src_addr, tx_count, | ||
802 | DMA_TO_DEVICE); | ||
803 | |||
804 | tx->command_ptr->num_rows = (((tx_count + 15) >> 4) << 16) | | ||
805 | ((tx_count + 15) >> 4); | ||
806 | tx->command_ptr->src_row_addr = src_addr; | ||
807 | |||
808 | dma_sync_single_for_device(uport->dev, tx->mapped_cmd_ptr, | ||
809 | sizeof(dmov_box), DMA_TO_DEVICE); | ||
810 | |||
811 | *tx->command_ptr_ptr = CMD_PTR_LP | DMOV_CMD_ADDR(tx->mapped_cmd_ptr); | ||
812 | |||
813 | dma_sync_single_for_device(uport->dev, tx->mapped_cmd_ptr_ptr, | ||
814 | sizeof(u32), DMA_TO_DEVICE); | ||
815 | |||
816 | /* Save tx_count to use in Callback */ | ||
817 | tx->tx_count = tx_count; | ||
818 | msm_hs_write(uport, UARTDM_NCF_TX_ADDR, tx_count); | ||
819 | |||
820 | /* Disable the tx_ready interrupt */ | ||
821 | msm_uport->imr_reg &= ~UARTDM_ISR_TX_READY_BMSK; | ||
822 | msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg); | ||
823 | msm_dmov_enqueue_cmd(msm_uport->dma_tx_channel, &tx->xfer); | ||
824 | } | ||
825 | |||
826 | /* Start to receive the next chunk of data */ | ||
827 | static void msm_hs_start_rx_locked(struct uart_port *uport) | ||
828 | { | ||
829 | struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); | ||
830 | |||
831 | msm_hs_write(uport, UARTDM_CR_ADDR, RESET_STALE_INT); | ||
832 | msm_hs_write(uport, UARTDM_DMRX_ADDR, UARTDM_RX_BUF_SIZE); | ||
833 | msm_hs_write(uport, UARTDM_CR_ADDR, STALE_EVENT_ENABLE); | ||
834 | msm_uport->imr_reg |= UARTDM_ISR_RXLEV_BMSK; | ||
835 | msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg); | ||
836 | |||
837 | msm_uport->rx.flush = FLUSH_NONE; | ||
838 | msm_dmov_enqueue_cmd(msm_uport->dma_rx_channel, &msm_uport->rx.xfer); | ||
839 | |||
840 | /* might have finished RX and be ready to clock off */ | ||
841 | hrtimer_start(&msm_uport->clk_off_timer, msm_uport->clk_off_delay, | ||
842 | HRTIMER_MODE_REL); | ||
843 | } | ||
844 | |||
845 | /* Enable the transmitter Interrupt */ | ||
846 | static void msm_hs_start_tx_locked(struct uart_port *uport) | ||
847 | { | ||
848 | struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); | ||
849 | |||
850 | clk_enable(msm_uport->clk); | ||
851 | |||
852 | if (msm_uport->exit_lpm_cb) | ||
853 | msm_uport->exit_lpm_cb(uport); | ||
854 | |||
855 | if (msm_uport->tx.tx_ready_int_en == 0) { | ||
856 | msm_uport->tx.tx_ready_int_en = 1; | ||
857 | msm_hs_submit_tx_locked(uport); | ||
858 | } | ||
859 | |||
860 | clk_disable(msm_uport->clk); | ||
861 | } | ||
862 | |||
863 | /* | ||
864 | * This routine is called when we are done with a DMA transfer | ||
865 | * | ||
866 | * This routine is registered with Data mover when we set | ||
867 | * up a Data Mover transfer. It is called from Data mover ISR | ||
868 | * when the DMA transfer is done. | ||
869 | */ | ||
870 | static void msm_hs_dmov_tx_callback(struct msm_dmov_cmd *cmd_ptr, | ||
871 | unsigned int result, | ||
872 | struct msm_dmov_errdata *err) | ||
873 | { | ||
874 | unsigned long flags; | ||
875 | struct msm_hs_port *msm_uport; | ||
876 | |||
877 | /* DMA did not finish properly */ | ||
878 | WARN_ON((((result & RSLT_FIFO_CNTR_BMSK) >> 28) == 1) && | ||
879 | !(result & RSLT_VLD)); | ||
880 | |||
881 | msm_uport = container_of(cmd_ptr, struct msm_hs_port, tx.xfer); | ||
882 | |||
883 | spin_lock_irqsave(&msm_uport->uport.lock, flags); | ||
884 | clk_enable(msm_uport->clk); | ||
885 | |||
886 | msm_uport->imr_reg |= UARTDM_ISR_TX_READY_BMSK; | ||
887 | msm_hs_write(&msm_uport->uport, UARTDM_IMR_ADDR, msm_uport->imr_reg); | ||
888 | |||
889 | clk_disable(msm_uport->clk); | ||
890 | spin_unlock_irqrestore(&msm_uport->uport.lock, flags); | ||
891 | } | ||
892 | |||
893 | /* | ||
894 | * This routine is called when we are done with a DMA transfer or the | ||
895 | * a flush has been sent to the data mover driver. | ||
896 | * | ||
897 | * This routine is registered with Data mover when we set up a Data Mover | ||
898 | * transfer. It is called from Data mover ISR when the DMA transfer is done. | ||
899 | */ | ||
900 | static void msm_hs_dmov_rx_callback(struct msm_dmov_cmd *cmd_ptr, | ||
901 | unsigned int result, | ||
902 | struct msm_dmov_errdata *err) | ||
903 | { | ||
904 | int retval; | ||
905 | int rx_count; | ||
906 | unsigned long status; | ||
907 | unsigned int error_f = 0; | ||
908 | unsigned long flags; | ||
909 | unsigned int flush; | ||
910 | struct tty_port *port; | ||
911 | struct uart_port *uport; | ||
912 | struct msm_hs_port *msm_uport; | ||
913 | |||
914 | msm_uport = container_of(cmd_ptr, struct msm_hs_port, rx.xfer); | ||
915 | uport = &msm_uport->uport; | ||
916 | |||
917 | spin_lock_irqsave(&uport->lock, flags); | ||
918 | clk_enable(msm_uport->clk); | ||
919 | |||
920 | port = &uport->state->port; | ||
921 | |||
922 | msm_hs_write(uport, UARTDM_CR_ADDR, STALE_EVENT_DISABLE); | ||
923 | |||
924 | status = msm_hs_read(uport, UARTDM_SR_ADDR); | ||
925 | |||
926 | /* overflow is not connect to data in a FIFO */ | ||
927 | if (unlikely((status & UARTDM_SR_OVERRUN_BMSK) && | ||
928 | (uport->read_status_mask & CREAD))) { | ||
929 | tty_insert_flip_char(port, 0, TTY_OVERRUN); | ||
930 | uport->icount.buf_overrun++; | ||
931 | error_f = 1; | ||
932 | } | ||
933 | |||
934 | if (!(uport->ignore_status_mask & INPCK)) | ||
935 | status = status & ~(UARTDM_SR_PAR_FRAME_BMSK); | ||
936 | |||
937 | if (unlikely(status & UARTDM_SR_PAR_FRAME_BMSK)) { | ||
938 | /* Can not tell difference between parity & frame error */ | ||
939 | uport->icount.parity++; | ||
940 | error_f = 1; | ||
941 | if (uport->ignore_status_mask & IGNPAR) | ||
942 | tty_insert_flip_char(port, 0, TTY_PARITY); | ||
943 | } | ||
944 | |||
945 | if (error_f) | ||
946 | msm_hs_write(uport, UARTDM_CR_ADDR, RESET_ERROR_STATUS); | ||
947 | |||
948 | if (msm_uport->clk_req_off_state == CLK_REQ_OFF_FLUSH_ISSUED) | ||
949 | msm_uport->clk_req_off_state = CLK_REQ_OFF_RXSTALE_FLUSHED; | ||
950 | |||
951 | flush = msm_uport->rx.flush; | ||
952 | if (flush == FLUSH_IGNORE) | ||
953 | msm_hs_start_rx_locked(uport); | ||
954 | if (flush == FLUSH_STOP) | ||
955 | msm_uport->rx.flush = FLUSH_SHUTDOWN; | ||
956 | if (flush >= FLUSH_DATA_INVALID) | ||
957 | goto out; | ||
958 | |||
959 | rx_count = msm_hs_read(uport, UARTDM_RX_TOTAL_SNAP_ADDR); | ||
960 | |||
961 | if (0 != (uport->read_status_mask & CREAD)) { | ||
962 | retval = tty_insert_flip_string(port, msm_uport->rx.buffer, | ||
963 | rx_count); | ||
964 | BUG_ON(retval != rx_count); | ||
965 | } | ||
966 | |||
967 | msm_hs_start_rx_locked(uport); | ||
968 | |||
969 | out: | ||
970 | clk_disable(msm_uport->clk); | ||
971 | |||
972 | spin_unlock_irqrestore(&uport->lock, flags); | ||
973 | |||
974 | if (flush < FLUSH_DATA_INVALID) | ||
975 | queue_work(msm_hs_workqueue, &msm_uport->rx.tty_work); | ||
976 | } | ||
977 | |||
978 | static void msm_hs_tty_flip_buffer_work(struct work_struct *work) | ||
979 | { | ||
980 | struct msm_hs_port *msm_uport = | ||
981 | container_of(work, struct msm_hs_port, rx.tty_work); | ||
982 | |||
983 | tty_flip_buffer_push(&msm_uport->uport.state->port); | ||
984 | } | ||
985 | |||
986 | /* | ||
987 | * Standard API, Current states of modem control inputs | ||
988 | * | ||
989 | * Since CTS can be handled entirely by HARDWARE we always | ||
990 | * indicate clear to send and count on the TX FIFO to block when | ||
991 | * it fills up. | ||
992 | * | ||
993 | * - TIOCM_DCD | ||
994 | * - TIOCM_CTS | ||
995 | * - TIOCM_DSR | ||
996 | * - TIOCM_RI | ||
997 | * (Unsupported) DCD and DSR will return them high. RI will return low. | ||
998 | */ | ||
999 | static unsigned int msm_hs_get_mctrl_locked(struct uart_port *uport) | ||
1000 | { | ||
1001 | return TIOCM_DSR | TIOCM_CAR | TIOCM_CTS; | ||
1002 | } | ||
1003 | |||
1004 | /* | ||
1005 | * True enables UART auto RFR, which indicates we are ready for data if the RX | ||
1006 | * buffer is not full. False disables auto RFR, and deasserts RFR to indicate | ||
1007 | * we are not ready for data. Must be called with UART clock on. | ||
1008 | */ | ||
1009 | static void set_rfr_locked(struct uart_port *uport, int auto_rfr) | ||
1010 | { | ||
1011 | unsigned int data; | ||
1012 | |||
1013 | data = msm_hs_read(uport, UARTDM_MR1_ADDR); | ||
1014 | |||
1015 | if (auto_rfr) { | ||
1016 | /* enable auto ready-for-receiving */ | ||
1017 | data |= UARTDM_MR1_RX_RDY_CTL_BMSK; | ||
1018 | msm_hs_write(uport, UARTDM_MR1_ADDR, data); | ||
1019 | } else { | ||
1020 | /* disable auto ready-for-receiving */ | ||
1021 | data &= ~UARTDM_MR1_RX_RDY_CTL_BMSK; | ||
1022 | msm_hs_write(uport, UARTDM_MR1_ADDR, data); | ||
1023 | /* RFR is active low, set high */ | ||
1024 | msm_hs_write(uport, UARTDM_CR_ADDR, RFR_HIGH); | ||
1025 | } | ||
1026 | } | ||
1027 | |||
1028 | /* | ||
1029 | * Standard API, used to set or clear RFR | ||
1030 | */ | ||
1031 | static void msm_hs_set_mctrl_locked(struct uart_port *uport, | ||
1032 | unsigned int mctrl) | ||
1033 | { | ||
1034 | unsigned int auto_rfr; | ||
1035 | struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); | ||
1036 | |||
1037 | clk_enable(msm_uport->clk); | ||
1038 | |||
1039 | auto_rfr = TIOCM_RTS & mctrl ? 1 : 0; | ||
1040 | set_rfr_locked(uport, auto_rfr); | ||
1041 | |||
1042 | clk_disable(msm_uport->clk); | ||
1043 | } | ||
1044 | |||
1045 | /* Standard API, Enable modem status (CTS) interrupt */ | ||
1046 | static void msm_hs_enable_ms_locked(struct uart_port *uport) | ||
1047 | { | ||
1048 | struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); | ||
1049 | |||
1050 | clk_enable(msm_uport->clk); | ||
1051 | |||
1052 | /* Enable DELTA_CTS Interrupt */ | ||
1053 | msm_uport->imr_reg |= UARTDM_ISR_DELTA_CTS_BMSK; | ||
1054 | msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg); | ||
1055 | |||
1056 | clk_disable(msm_uport->clk); | ||
1057 | |||
1058 | } | ||
1059 | |||
1060 | /* | ||
1061 | * Standard API, Break Signal | ||
1062 | * | ||
1063 | * Control the transmission of a break signal. ctl eq 0 => break | ||
1064 | * signal terminate ctl ne 0 => start break signal | ||
1065 | */ | ||
1066 | static void msm_hs_break_ctl(struct uart_port *uport, int ctl) | ||
1067 | { | ||
1068 | struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); | ||
1069 | |||
1070 | clk_enable(msm_uport->clk); | ||
1071 | msm_hs_write(uport, UARTDM_CR_ADDR, ctl ? START_BREAK : STOP_BREAK); | ||
1072 | clk_disable(msm_uport->clk); | ||
1073 | } | ||
1074 | |||
1075 | static void msm_hs_config_port(struct uart_port *uport, int cfg_flags) | ||
1076 | { | ||
1077 | unsigned long flags; | ||
1078 | |||
1079 | spin_lock_irqsave(&uport->lock, flags); | ||
1080 | if (cfg_flags & UART_CONFIG_TYPE) { | ||
1081 | uport->type = PORT_MSM; | ||
1082 | msm_hs_request_port(uport); | ||
1083 | } | ||
1084 | spin_unlock_irqrestore(&uport->lock, flags); | ||
1085 | } | ||
1086 | |||
1087 | /* Handle CTS changes (Called from interrupt handler) */ | ||
1088 | static void msm_hs_handle_delta_cts_locked(struct uart_port *uport) | ||
1089 | { | ||
1090 | struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); | ||
1091 | |||
1092 | clk_enable(msm_uport->clk); | ||
1093 | |||
1094 | /* clear interrupt */ | ||
1095 | msm_hs_write(uport, UARTDM_CR_ADDR, RESET_CTS); | ||
1096 | uport->icount.cts++; | ||
1097 | |||
1098 | clk_disable(msm_uport->clk); | ||
1099 | |||
1100 | /* clear the IOCTL TIOCMIWAIT if called */ | ||
1101 | wake_up_interruptible(&uport->state->port.delta_msr_wait); | ||
1102 | } | ||
1103 | |||
1104 | /* check if the TX path is flushed, and if so clock off | ||
1105 | * returns 0 did not clock off, need to retry (still sending final byte) | ||
1106 | * -1 did not clock off, do not retry | ||
1107 | * 1 if we clocked off | ||
1108 | */ | ||
1109 | static int msm_hs_check_clock_off_locked(struct uart_port *uport) | ||
1110 | { | ||
1111 | unsigned long sr_status; | ||
1112 | struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); | ||
1113 | struct circ_buf *tx_buf = &uport->state->xmit; | ||
1114 | |||
1115 | /* Cancel if tx tty buffer is not empty, dma is in flight, | ||
1116 | * or tx fifo is not empty, or rx fifo is not empty */ | ||
1117 | if (msm_uport->clk_state != MSM_HS_CLK_REQUEST_OFF || | ||
1118 | !uart_circ_empty(tx_buf) || msm_uport->tx.dma_in_flight || | ||
1119 | (msm_uport->imr_reg & UARTDM_ISR_TXLEV_BMSK) || | ||
1120 | !(msm_uport->imr_reg & UARTDM_ISR_RXLEV_BMSK)) { | ||
1121 | return -1; | ||
1122 | } | ||
1123 | |||
1124 | /* Make sure the uart is finished with the last byte */ | ||
1125 | sr_status = msm_hs_read(uport, UARTDM_SR_ADDR); | ||
1126 | if (!(sr_status & UARTDM_SR_TXEMT_BMSK)) | ||
1127 | return 0; /* retry */ | ||
1128 | |||
1129 | /* Make sure forced RXSTALE flush complete */ | ||
1130 | switch (msm_uport->clk_req_off_state) { | ||
1131 | case CLK_REQ_OFF_START: | ||
1132 | msm_uport->clk_req_off_state = CLK_REQ_OFF_RXSTALE_ISSUED; | ||
1133 | msm_hs_write(uport, UARTDM_CR_ADDR, FORCE_STALE_EVENT); | ||
1134 | return 0; /* RXSTALE flush not complete - retry */ | ||
1135 | case CLK_REQ_OFF_RXSTALE_ISSUED: | ||
1136 | case CLK_REQ_OFF_FLUSH_ISSUED: | ||
1137 | return 0; /* RXSTALE flush not complete - retry */ | ||
1138 | case CLK_REQ_OFF_RXSTALE_FLUSHED: | ||
1139 | break; /* continue */ | ||
1140 | } | ||
1141 | |||
1142 | if (msm_uport->rx.flush != FLUSH_SHUTDOWN) { | ||
1143 | if (msm_uport->rx.flush == FLUSH_NONE) | ||
1144 | msm_hs_stop_rx_locked(uport); | ||
1145 | return 0; /* come back later to really clock off */ | ||
1146 | } | ||
1147 | |||
1148 | /* we really want to clock off */ | ||
1149 | clk_disable(msm_uport->clk); | ||
1150 | msm_uport->clk_state = MSM_HS_CLK_OFF; | ||
1151 | |||
1152 | if (use_low_power_rx_wakeup(msm_uport)) { | ||
1153 | msm_uport->rx_wakeup.ignore = 1; | ||
1154 | enable_irq(msm_uport->rx_wakeup.irq); | ||
1155 | } | ||
1156 | return 1; | ||
1157 | } | ||
1158 | |||
1159 | static enum hrtimer_restart msm_hs_clk_off_retry(struct hrtimer *timer) | ||
1160 | { | ||
1161 | unsigned long flags; | ||
1162 | int ret = HRTIMER_NORESTART; | ||
1163 | struct msm_hs_port *msm_uport = container_of(timer, struct msm_hs_port, | ||
1164 | clk_off_timer); | ||
1165 | struct uart_port *uport = &msm_uport->uport; | ||
1166 | |||
1167 | spin_lock_irqsave(&uport->lock, flags); | ||
1168 | |||
1169 | if (!msm_hs_check_clock_off_locked(uport)) { | ||
1170 | hrtimer_forward_now(timer, msm_uport->clk_off_delay); | ||
1171 | ret = HRTIMER_RESTART; | ||
1172 | } | ||
1173 | |||
1174 | spin_unlock_irqrestore(&uport->lock, flags); | ||
1175 | |||
1176 | return ret; | ||
1177 | } | ||
1178 | |||
1179 | static irqreturn_t msm_hs_isr(int irq, void *dev) | ||
1180 | { | ||
1181 | unsigned long flags; | ||
1182 | unsigned long isr_status; | ||
1183 | struct msm_hs_port *msm_uport = dev; | ||
1184 | struct uart_port *uport = &msm_uport->uport; | ||
1185 | struct circ_buf *tx_buf = &uport->state->xmit; | ||
1186 | struct msm_hs_tx *tx = &msm_uport->tx; | ||
1187 | struct msm_hs_rx *rx = &msm_uport->rx; | ||
1188 | |||
1189 | spin_lock_irqsave(&uport->lock, flags); | ||
1190 | |||
1191 | isr_status = msm_hs_read(uport, UARTDM_MISR_ADDR); | ||
1192 | |||
1193 | /* Uart RX starting */ | ||
1194 | if (isr_status & UARTDM_ISR_RXLEV_BMSK) { | ||
1195 | msm_uport->imr_reg &= ~UARTDM_ISR_RXLEV_BMSK; | ||
1196 | msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg); | ||
1197 | } | ||
1198 | /* Stale rx interrupt */ | ||
1199 | if (isr_status & UARTDM_ISR_RXSTALE_BMSK) { | ||
1200 | msm_hs_write(uport, UARTDM_CR_ADDR, STALE_EVENT_DISABLE); | ||
1201 | msm_hs_write(uport, UARTDM_CR_ADDR, RESET_STALE_INT); | ||
1202 | |||
1203 | if (msm_uport->clk_req_off_state == CLK_REQ_OFF_RXSTALE_ISSUED) | ||
1204 | msm_uport->clk_req_off_state = | ||
1205 | CLK_REQ_OFF_FLUSH_ISSUED; | ||
1206 | if (rx->flush == FLUSH_NONE) { | ||
1207 | rx->flush = FLUSH_DATA_READY; | ||
1208 | msm_dmov_stop_cmd(msm_uport->dma_rx_channel, NULL, 1); | ||
1209 | } | ||
1210 | } | ||
1211 | /* tx ready interrupt */ | ||
1212 | if (isr_status & UARTDM_ISR_TX_READY_BMSK) { | ||
1213 | /* Clear TX Ready */ | ||
1214 | msm_hs_write(uport, UARTDM_CR_ADDR, CLEAR_TX_READY); | ||
1215 | |||
1216 | if (msm_uport->clk_state == MSM_HS_CLK_REQUEST_OFF) { | ||
1217 | msm_uport->imr_reg |= UARTDM_ISR_TXLEV_BMSK; | ||
1218 | msm_hs_write(uport, UARTDM_IMR_ADDR, | ||
1219 | msm_uport->imr_reg); | ||
1220 | } | ||
1221 | |||
1222 | /* Complete DMA TX transactions and submit new transactions */ | ||
1223 | tx_buf->tail = (tx_buf->tail + tx->tx_count) & ~UART_XMIT_SIZE; | ||
1224 | |||
1225 | tx->dma_in_flight = 0; | ||
1226 | |||
1227 | uport->icount.tx += tx->tx_count; | ||
1228 | if (tx->tx_ready_int_en) | ||
1229 | msm_hs_submit_tx_locked(uport); | ||
1230 | |||
1231 | if (uart_circ_chars_pending(tx_buf) < WAKEUP_CHARS) | ||
1232 | uart_write_wakeup(uport); | ||
1233 | } | ||
1234 | if (isr_status & UARTDM_ISR_TXLEV_BMSK) { | ||
1235 | /* TX FIFO is empty */ | ||
1236 | msm_uport->imr_reg &= ~UARTDM_ISR_TXLEV_BMSK; | ||
1237 | msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg); | ||
1238 | if (!msm_hs_check_clock_off_locked(uport)) | ||
1239 | hrtimer_start(&msm_uport->clk_off_timer, | ||
1240 | msm_uport->clk_off_delay, | ||
1241 | HRTIMER_MODE_REL); | ||
1242 | } | ||
1243 | |||
1244 | /* Change in CTS interrupt */ | ||
1245 | if (isr_status & UARTDM_ISR_DELTA_CTS_BMSK) | ||
1246 | msm_hs_handle_delta_cts_locked(uport); | ||
1247 | |||
1248 | spin_unlock_irqrestore(&uport->lock, flags); | ||
1249 | |||
1250 | return IRQ_HANDLED; | ||
1251 | } | ||
1252 | |||
1253 | void msm_hs_request_clock_off_locked(struct uart_port *uport) | ||
1254 | { | ||
1255 | struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); | ||
1256 | |||
1257 | if (msm_uport->clk_state == MSM_HS_CLK_ON) { | ||
1258 | msm_uport->clk_state = MSM_HS_CLK_REQUEST_OFF; | ||
1259 | msm_uport->clk_req_off_state = CLK_REQ_OFF_START; | ||
1260 | if (!use_low_power_rx_wakeup(msm_uport)) | ||
1261 | set_rfr_locked(uport, 0); | ||
1262 | msm_uport->imr_reg |= UARTDM_ISR_TXLEV_BMSK; | ||
1263 | msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg); | ||
1264 | } | ||
1265 | } | ||
1266 | |||
1267 | /** | ||
1268 | * msm_hs_request_clock_off - request to (i.e. asynchronously) turn off uart | ||
1269 | * clock once pending TX is flushed and Rx DMA command is terminated. | ||
1270 | * @uport: uart_port structure for the device instance. | ||
1271 | * | ||
1272 | * This functions puts the device into a partially active low power mode. It | ||
1273 | * waits to complete all pending tx transactions, flushes ongoing Rx DMA | ||
1274 | * command and terminates UART side Rx transaction, puts UART HW in non DMA | ||
1275 | * mode and then clocks off the device. A client calls this when no UART | ||
1276 | * data is expected. msm_request_clock_on() must be called before any further | ||
1277 | * UART can be sent or received. | ||
1278 | */ | ||
1279 | void msm_hs_request_clock_off(struct uart_port *uport) | ||
1280 | { | ||
1281 | unsigned long flags; | ||
1282 | |||
1283 | spin_lock_irqsave(&uport->lock, flags); | ||
1284 | msm_hs_request_clock_off_locked(uport); | ||
1285 | spin_unlock_irqrestore(&uport->lock, flags); | ||
1286 | } | ||
1287 | |||
1288 | void msm_hs_request_clock_on_locked(struct uart_port *uport) | ||
1289 | { | ||
1290 | struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); | ||
1291 | unsigned int data; | ||
1292 | |||
1293 | switch (msm_uport->clk_state) { | ||
1294 | case MSM_HS_CLK_OFF: | ||
1295 | clk_enable(msm_uport->clk); | ||
1296 | disable_irq_nosync(msm_uport->rx_wakeup.irq); | ||
1297 | /* fall-through */ | ||
1298 | case MSM_HS_CLK_REQUEST_OFF: | ||
1299 | if (msm_uport->rx.flush == FLUSH_STOP || | ||
1300 | msm_uport->rx.flush == FLUSH_SHUTDOWN) { | ||
1301 | msm_hs_write(uport, UARTDM_CR_ADDR, RESET_RX); | ||
1302 | data = msm_hs_read(uport, UARTDM_DMEN_ADDR); | ||
1303 | data |= UARTDM_RX_DM_EN_BMSK; | ||
1304 | msm_hs_write(uport, UARTDM_DMEN_ADDR, data); | ||
1305 | } | ||
1306 | hrtimer_try_to_cancel(&msm_uport->clk_off_timer); | ||
1307 | if (msm_uport->rx.flush == FLUSH_SHUTDOWN) | ||
1308 | msm_hs_start_rx_locked(uport); | ||
1309 | if (!use_low_power_rx_wakeup(msm_uport)) | ||
1310 | set_rfr_locked(uport, 1); | ||
1311 | if (msm_uport->rx.flush == FLUSH_STOP) | ||
1312 | msm_uport->rx.flush = FLUSH_IGNORE; | ||
1313 | msm_uport->clk_state = MSM_HS_CLK_ON; | ||
1314 | break; | ||
1315 | case MSM_HS_CLK_ON: | ||
1316 | break; | ||
1317 | case MSM_HS_CLK_PORT_OFF: | ||
1318 | break; | ||
1319 | } | ||
1320 | } | ||
1321 | |||
1322 | /** | ||
1323 | * msm_hs_request_clock_on - Switch the device from partially active low | ||
1324 | * power mode to fully active (i.e. clock on) mode. | ||
1325 | * @uport: uart_port structure for the device. | ||
1326 | * | ||
1327 | * This function switches on the input clock, puts UART HW into DMA mode | ||
1328 | * and enqueues an Rx DMA command if the device was in partially active | ||
1329 | * mode. It has no effect if called with the device in inactive state. | ||
1330 | */ | ||
1331 | void msm_hs_request_clock_on(struct uart_port *uport) | ||
1332 | { | ||
1333 | unsigned long flags; | ||
1334 | |||
1335 | spin_lock_irqsave(&uport->lock, flags); | ||
1336 | msm_hs_request_clock_on_locked(uport); | ||
1337 | spin_unlock_irqrestore(&uport->lock, flags); | ||
1338 | } | ||
1339 | |||
1340 | static irqreturn_t msm_hs_rx_wakeup_isr(int irq, void *dev) | ||
1341 | { | ||
1342 | unsigned int wakeup = 0; | ||
1343 | unsigned long flags; | ||
1344 | struct msm_hs_port *msm_uport = dev; | ||
1345 | struct uart_port *uport = &msm_uport->uport; | ||
1346 | |||
1347 | spin_lock_irqsave(&uport->lock, flags); | ||
1348 | if (msm_uport->clk_state == MSM_HS_CLK_OFF) { | ||
1349 | /* ignore the first irq - it is a pending irq that occurred | ||
1350 | * before enable_irq() */ | ||
1351 | if (msm_uport->rx_wakeup.ignore) | ||
1352 | msm_uport->rx_wakeup.ignore = 0; | ||
1353 | else | ||
1354 | wakeup = 1; | ||
1355 | } | ||
1356 | |||
1357 | if (wakeup) { | ||
1358 | /* the uart was clocked off during an rx, wake up and | ||
1359 | * optionally inject char into tty rx */ | ||
1360 | msm_hs_request_clock_on_locked(uport); | ||
1361 | if (msm_uport->rx_wakeup.inject_rx) { | ||
1362 | tty_insert_flip_char(&uport->state->port, | ||
1363 | msm_uport->rx_wakeup.rx_to_inject, | ||
1364 | TTY_NORMAL); | ||
1365 | queue_work(msm_hs_workqueue, &msm_uport->rx.tty_work); | ||
1366 | } | ||
1367 | } | ||
1368 | |||
1369 | spin_unlock_irqrestore(&uport->lock, flags); | ||
1370 | |||
1371 | return IRQ_HANDLED; | ||
1372 | } | ||
1373 | |||
1374 | static const char *msm_hs_type(struct uart_port *port) | ||
1375 | { | ||
1376 | return (port->type == PORT_MSM) ? "MSM_HS_UART" : NULL; | ||
1377 | } | ||
1378 | |||
1379 | /* Called when port is opened */ | ||
1380 | static int msm_hs_startup(struct uart_port *uport) | ||
1381 | { | ||
1382 | int ret; | ||
1383 | int rfr_level; | ||
1384 | unsigned long flags; | ||
1385 | unsigned int data; | ||
1386 | struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); | ||
1387 | struct circ_buf *tx_buf = &uport->state->xmit; | ||
1388 | struct msm_hs_tx *tx = &msm_uport->tx; | ||
1389 | struct msm_hs_rx *rx = &msm_uport->rx; | ||
1390 | |||
1391 | rfr_level = uport->fifosize; | ||
1392 | if (rfr_level > 16) | ||
1393 | rfr_level -= 16; | ||
1394 | |||
1395 | tx->dma_base = dma_map_single(uport->dev, tx_buf->buf, UART_XMIT_SIZE, | ||
1396 | DMA_TO_DEVICE); | ||
1397 | |||
1398 | /* do not let tty layer execute RX in global workqueue, use a | ||
1399 | * dedicated workqueue managed by this driver */ | ||
1400 | uport->state->port.low_latency = 1; | ||
1401 | |||
1402 | /* turn on uart clk */ | ||
1403 | ret = msm_hs_init_clk_locked(uport); | ||
1404 | if (unlikely(ret)) { | ||
1405 | printk(KERN_ERR "Turning uartclk failed!\n"); | ||
1406 | goto err_msm_hs_init_clk; | ||
1407 | } | ||
1408 | |||
1409 | /* Set auto RFR Level */ | ||
1410 | data = msm_hs_read(uport, UARTDM_MR1_ADDR); | ||
1411 | data &= ~UARTDM_MR1_AUTO_RFR_LEVEL1_BMSK; | ||
1412 | data &= ~UARTDM_MR1_AUTO_RFR_LEVEL0_BMSK; | ||
1413 | data |= (UARTDM_MR1_AUTO_RFR_LEVEL1_BMSK & (rfr_level << 2)); | ||
1414 | data |= (UARTDM_MR1_AUTO_RFR_LEVEL0_BMSK & rfr_level); | ||
1415 | msm_hs_write(uport, UARTDM_MR1_ADDR, data); | ||
1416 | |||
1417 | /* Make sure RXSTALE count is non-zero */ | ||
1418 | data = msm_hs_read(uport, UARTDM_IPR_ADDR); | ||
1419 | if (!data) { | ||
1420 | data |= 0x1f & UARTDM_IPR_STALE_LSB_BMSK; | ||
1421 | msm_hs_write(uport, UARTDM_IPR_ADDR, data); | ||
1422 | } | ||
1423 | |||
1424 | /* Enable Data Mover Mode */ | ||
1425 | data = UARTDM_TX_DM_EN_BMSK | UARTDM_RX_DM_EN_BMSK; | ||
1426 | msm_hs_write(uport, UARTDM_DMEN_ADDR, data); | ||
1427 | |||
1428 | /* Reset TX */ | ||
1429 | msm_hs_write(uport, UARTDM_CR_ADDR, RESET_TX); | ||
1430 | msm_hs_write(uport, UARTDM_CR_ADDR, RESET_RX); | ||
1431 | msm_hs_write(uport, UARTDM_CR_ADDR, RESET_ERROR_STATUS); | ||
1432 | msm_hs_write(uport, UARTDM_CR_ADDR, RESET_BREAK_INT); | ||
1433 | msm_hs_write(uport, UARTDM_CR_ADDR, RESET_STALE_INT); | ||
1434 | msm_hs_write(uport, UARTDM_CR_ADDR, RESET_CTS); | ||
1435 | msm_hs_write(uport, UARTDM_CR_ADDR, RFR_LOW); | ||
1436 | /* Turn on Uart Receiver */ | ||
1437 | msm_hs_write(uport, UARTDM_CR_ADDR, UARTDM_CR_RX_EN_BMSK); | ||
1438 | |||
1439 | /* Turn on Uart Transmitter */ | ||
1440 | msm_hs_write(uport, UARTDM_CR_ADDR, UARTDM_CR_TX_EN_BMSK); | ||
1441 | |||
1442 | /* Initialize the tx */ | ||
1443 | tx->tx_ready_int_en = 0; | ||
1444 | tx->dma_in_flight = 0; | ||
1445 | |||
1446 | tx->xfer.complete_func = msm_hs_dmov_tx_callback; | ||
1447 | tx->xfer.execute_func = NULL; | ||
1448 | |||
1449 | tx->command_ptr->cmd = CMD_LC | | ||
1450 | CMD_DST_CRCI(msm_uport->dma_tx_crci) | CMD_MODE_BOX; | ||
1451 | |||
1452 | tx->command_ptr->src_dst_len = (MSM_UARTDM_BURST_SIZE << 16) | ||
1453 | | (MSM_UARTDM_BURST_SIZE); | ||
1454 | |||
1455 | tx->command_ptr->row_offset = (MSM_UARTDM_BURST_SIZE << 16); | ||
1456 | |||
1457 | tx->command_ptr->dst_row_addr = | ||
1458 | msm_uport->uport.mapbase + UARTDM_TF_ADDR; | ||
1459 | |||
1460 | |||
1461 | /* Turn on Uart Receive */ | ||
1462 | rx->xfer.complete_func = msm_hs_dmov_rx_callback; | ||
1463 | rx->xfer.execute_func = NULL; | ||
1464 | |||
1465 | rx->command_ptr->cmd = CMD_LC | | ||
1466 | CMD_SRC_CRCI(msm_uport->dma_rx_crci) | CMD_MODE_BOX; | ||
1467 | |||
1468 | rx->command_ptr->src_dst_len = (MSM_UARTDM_BURST_SIZE << 16) | ||
1469 | | (MSM_UARTDM_BURST_SIZE); | ||
1470 | rx->command_ptr->row_offset = MSM_UARTDM_BURST_SIZE; | ||
1471 | rx->command_ptr->src_row_addr = uport->mapbase + UARTDM_RF_ADDR; | ||
1472 | |||
1473 | |||
1474 | msm_uport->imr_reg |= UARTDM_ISR_RXSTALE_BMSK; | ||
1475 | /* Enable reading the current CTS, no harm even if CTS is ignored */ | ||
1476 | msm_uport->imr_reg |= UARTDM_ISR_CURRENT_CTS_BMSK; | ||
1477 | |||
1478 | msm_hs_write(uport, UARTDM_TFWR_ADDR, 0); /* TXLEV on empty TX fifo */ | ||
1479 | |||
1480 | |||
1481 | ret = request_irq(uport->irq, msm_hs_isr, IRQF_TRIGGER_HIGH, | ||
1482 | "msm_hs_uart", msm_uport); | ||
1483 | if (unlikely(ret)) { | ||
1484 | printk(KERN_ERR "Request msm_hs_uart IRQ failed!\n"); | ||
1485 | goto err_request_irq; | ||
1486 | } | ||
1487 | if (use_low_power_rx_wakeup(msm_uport)) { | ||
1488 | ret = request_irq(msm_uport->rx_wakeup.irq, | ||
1489 | msm_hs_rx_wakeup_isr, | ||
1490 | IRQF_TRIGGER_FALLING, | ||
1491 | "msm_hs_rx_wakeup", msm_uport); | ||
1492 | if (unlikely(ret)) { | ||
1493 | printk(KERN_ERR "Request msm_hs_rx_wakeup IRQ failed!\n"); | ||
1494 | free_irq(uport->irq, msm_uport); | ||
1495 | goto err_request_irq; | ||
1496 | } | ||
1497 | disable_irq(msm_uport->rx_wakeup.irq); | ||
1498 | } | ||
1499 | |||
1500 | spin_lock_irqsave(&uport->lock, flags); | ||
1501 | |||
1502 | msm_hs_write(uport, UARTDM_RFWR_ADDR, 0); | ||
1503 | msm_hs_start_rx_locked(uport); | ||
1504 | |||
1505 | spin_unlock_irqrestore(&uport->lock, flags); | ||
1506 | ret = pm_runtime_set_active(uport->dev); | ||
1507 | if (ret) | ||
1508 | dev_err(uport->dev, "set active error:%d\n", ret); | ||
1509 | pm_runtime_enable(uport->dev); | ||
1510 | |||
1511 | return 0; | ||
1512 | |||
1513 | err_request_irq: | ||
1514 | err_msm_hs_init_clk: | ||
1515 | dma_unmap_single(uport->dev, tx->dma_base, | ||
1516 | UART_XMIT_SIZE, DMA_TO_DEVICE); | ||
1517 | return ret; | ||
1518 | } | ||
1519 | |||
1520 | /* Initialize tx and rx data structures */ | ||
1521 | static int uartdm_init_port(struct uart_port *uport) | ||
1522 | { | ||
1523 | int ret = 0; | ||
1524 | struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); | ||
1525 | struct msm_hs_tx *tx = &msm_uport->tx; | ||
1526 | struct msm_hs_rx *rx = &msm_uport->rx; | ||
1527 | |||
1528 | /* Allocate the command pointer. Needs to be 64 bit aligned */ | ||
1529 | tx->command_ptr = kmalloc(sizeof(dmov_box), GFP_KERNEL | __GFP_DMA); | ||
1530 | if (!tx->command_ptr) | ||
1531 | return -ENOMEM; | ||
1532 | |||
1533 | tx->command_ptr_ptr = kmalloc(sizeof(u32), GFP_KERNEL | __GFP_DMA); | ||
1534 | if (!tx->command_ptr_ptr) { | ||
1535 | ret = -ENOMEM; | ||
1536 | goto err_tx_command_ptr_ptr; | ||
1537 | } | ||
1538 | |||
1539 | tx->mapped_cmd_ptr = dma_map_single(uport->dev, tx->command_ptr, | ||
1540 | sizeof(dmov_box), DMA_TO_DEVICE); | ||
1541 | tx->mapped_cmd_ptr_ptr = dma_map_single(uport->dev, | ||
1542 | tx->command_ptr_ptr, | ||
1543 | sizeof(u32), DMA_TO_DEVICE); | ||
1544 | tx->xfer.cmdptr = DMOV_CMD_ADDR(tx->mapped_cmd_ptr_ptr); | ||
1545 | |||
1546 | init_waitqueue_head(&rx->wait); | ||
1547 | |||
1548 | rx->pool = dma_pool_create("rx_buffer_pool", uport->dev, | ||
1549 | UARTDM_RX_BUF_SIZE, 16, 0); | ||
1550 | if (!rx->pool) { | ||
1551 | pr_err("%s(): cannot allocate rx_buffer_pool", __func__); | ||
1552 | ret = -ENOMEM; | ||
1553 | goto err_dma_pool_create; | ||
1554 | } | ||
1555 | |||
1556 | rx->buffer = dma_pool_alloc(rx->pool, GFP_KERNEL, &rx->rbuffer); | ||
1557 | if (!rx->buffer) { | ||
1558 | pr_err("%s(): cannot allocate rx->buffer", __func__); | ||
1559 | ret = -ENOMEM; | ||
1560 | goto err_dma_pool_alloc; | ||
1561 | } | ||
1562 | |||
1563 | /* Allocate the command pointer. Needs to be 64 bit aligned */ | ||
1564 | rx->command_ptr = kmalloc(sizeof(dmov_box), GFP_KERNEL | __GFP_DMA); | ||
1565 | if (!rx->command_ptr) { | ||
1566 | pr_err("%s(): cannot allocate rx->command_ptr", __func__); | ||
1567 | ret = -ENOMEM; | ||
1568 | goto err_rx_command_ptr; | ||
1569 | } | ||
1570 | |||
1571 | rx->command_ptr_ptr = kmalloc(sizeof(u32), GFP_KERNEL | __GFP_DMA); | ||
1572 | if (!rx->command_ptr_ptr) { | ||
1573 | pr_err("%s(): cannot allocate rx->command_ptr_ptr", __func__); | ||
1574 | ret = -ENOMEM; | ||
1575 | goto err_rx_command_ptr_ptr; | ||
1576 | } | ||
1577 | |||
1578 | rx->command_ptr->num_rows = ((UARTDM_RX_BUF_SIZE >> 4) << 16) | | ||
1579 | (UARTDM_RX_BUF_SIZE >> 4); | ||
1580 | |||
1581 | rx->command_ptr->dst_row_addr = rx->rbuffer; | ||
1582 | |||
1583 | rx->mapped_cmd_ptr = dma_map_single(uport->dev, rx->command_ptr, | ||
1584 | sizeof(dmov_box), DMA_TO_DEVICE); | ||
1585 | |||
1586 | *rx->command_ptr_ptr = CMD_PTR_LP | DMOV_CMD_ADDR(rx->mapped_cmd_ptr); | ||
1587 | |||
1588 | rx->cmdptr_dmaaddr = dma_map_single(uport->dev, rx->command_ptr_ptr, | ||
1589 | sizeof(u32), DMA_TO_DEVICE); | ||
1590 | rx->xfer.cmdptr = DMOV_CMD_ADDR(rx->cmdptr_dmaaddr); | ||
1591 | |||
1592 | INIT_WORK(&rx->tty_work, msm_hs_tty_flip_buffer_work); | ||
1593 | |||
1594 | return ret; | ||
1595 | |||
1596 | err_rx_command_ptr_ptr: | ||
1597 | kfree(rx->command_ptr); | ||
1598 | err_rx_command_ptr: | ||
1599 | dma_pool_free(msm_uport->rx.pool, msm_uport->rx.buffer, | ||
1600 | msm_uport->rx.rbuffer); | ||
1601 | err_dma_pool_alloc: | ||
1602 | dma_pool_destroy(msm_uport->rx.pool); | ||
1603 | err_dma_pool_create: | ||
1604 | dma_unmap_single(uport->dev, msm_uport->tx.mapped_cmd_ptr_ptr, | ||
1605 | sizeof(u32), DMA_TO_DEVICE); | ||
1606 | dma_unmap_single(uport->dev, msm_uport->tx.mapped_cmd_ptr, | ||
1607 | sizeof(dmov_box), DMA_TO_DEVICE); | ||
1608 | kfree(msm_uport->tx.command_ptr_ptr); | ||
1609 | err_tx_command_ptr_ptr: | ||
1610 | kfree(msm_uport->tx.command_ptr); | ||
1611 | return ret; | ||
1612 | } | ||
1613 | |||
1614 | static int msm_hs_probe(struct platform_device *pdev) | ||
1615 | { | ||
1616 | int ret; | ||
1617 | struct uart_port *uport; | ||
1618 | struct msm_hs_port *msm_uport; | ||
1619 | struct resource *resource; | ||
1620 | const struct msm_serial_hs_platform_data *pdata = | ||
1621 | dev_get_platdata(&pdev->dev); | ||
1622 | |||
1623 | if (pdev->id < 0 || pdev->id >= UARTDM_NR) { | ||
1624 | printk(KERN_ERR "Invalid plaform device ID = %d\n", pdev->id); | ||
1625 | return -EINVAL; | ||
1626 | } | ||
1627 | |||
1628 | msm_uport = &q_uart_port[pdev->id]; | ||
1629 | uport = &msm_uport->uport; | ||
1630 | |||
1631 | uport->dev = &pdev->dev; | ||
1632 | |||
1633 | resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
1634 | if (unlikely(!resource)) | ||
1635 | return -ENXIO; | ||
1636 | |||
1637 | uport->mapbase = resource->start; | ||
1638 | uport->irq = platform_get_irq(pdev, 0); | ||
1639 | if (unlikely(uport->irq < 0)) | ||
1640 | return -ENXIO; | ||
1641 | |||
1642 | if (unlikely(irq_set_irq_wake(uport->irq, 1))) | ||
1643 | return -ENXIO; | ||
1644 | |||
1645 | if (pdata == NULL || pdata->rx_wakeup_irq < 0) | ||
1646 | msm_uport->rx_wakeup.irq = -1; | ||
1647 | else { | ||
1648 | msm_uport->rx_wakeup.irq = pdata->rx_wakeup_irq; | ||
1649 | msm_uport->rx_wakeup.ignore = 1; | ||
1650 | msm_uport->rx_wakeup.inject_rx = pdata->inject_rx_on_wakeup; | ||
1651 | msm_uport->rx_wakeup.rx_to_inject = pdata->rx_to_inject; | ||
1652 | |||
1653 | if (unlikely(msm_uport->rx_wakeup.irq < 0)) | ||
1654 | return -ENXIO; | ||
1655 | |||
1656 | if (unlikely(irq_set_irq_wake(msm_uport->rx_wakeup.irq, 1))) | ||
1657 | return -ENXIO; | ||
1658 | } | ||
1659 | |||
1660 | if (pdata == NULL) | ||
1661 | msm_uport->exit_lpm_cb = NULL; | ||
1662 | else | ||
1663 | msm_uport->exit_lpm_cb = pdata->exit_lpm_cb; | ||
1664 | |||
1665 | resource = platform_get_resource_byname(pdev, IORESOURCE_DMA, | ||
1666 | "uartdm_channels"); | ||
1667 | if (unlikely(!resource)) | ||
1668 | return -ENXIO; | ||
1669 | |||
1670 | msm_uport->dma_tx_channel = resource->start; | ||
1671 | msm_uport->dma_rx_channel = resource->end; | ||
1672 | |||
1673 | resource = platform_get_resource_byname(pdev, IORESOURCE_DMA, | ||
1674 | "uartdm_crci"); | ||
1675 | if (unlikely(!resource)) | ||
1676 | return -ENXIO; | ||
1677 | |||
1678 | msm_uport->dma_tx_crci = resource->start; | ||
1679 | msm_uport->dma_rx_crci = resource->end; | ||
1680 | |||
1681 | uport->iotype = UPIO_MEM; | ||
1682 | uport->fifosize = UART_FIFOSIZE; | ||
1683 | uport->ops = &msm_hs_ops; | ||
1684 | uport->flags = UPF_BOOT_AUTOCONF; | ||
1685 | uport->uartclk = UARTCLK; | ||
1686 | msm_uport->imr_reg = 0x0; | ||
1687 | msm_uport->clk = clk_get(&pdev->dev, "uartdm_clk"); | ||
1688 | if (IS_ERR(msm_uport->clk)) | ||
1689 | return PTR_ERR(msm_uport->clk); | ||
1690 | |||
1691 | ret = uartdm_init_port(uport); | ||
1692 | if (unlikely(ret)) | ||
1693 | return ret; | ||
1694 | |||
1695 | msm_uport->clk_state = MSM_HS_CLK_PORT_OFF; | ||
1696 | hrtimer_init(&msm_uport->clk_off_timer, CLOCK_MONOTONIC, | ||
1697 | HRTIMER_MODE_REL); | ||
1698 | msm_uport->clk_off_timer.function = msm_hs_clk_off_retry; | ||
1699 | msm_uport->clk_off_delay = ktime_set(0, 1000000); /* 1ms */ | ||
1700 | |||
1701 | uport->line = pdev->id; | ||
1702 | return uart_add_one_port(&msm_hs_driver, uport); | ||
1703 | } | ||
1704 | |||
1705 | static int __init msm_serial_hs_init(void) | ||
1706 | { | ||
1707 | int ret, i; | ||
1708 | |||
1709 | /* Init all UARTS as non-configured */ | ||
1710 | for (i = 0; i < UARTDM_NR; i++) | ||
1711 | q_uart_port[i].uport.type = PORT_UNKNOWN; | ||
1712 | |||
1713 | msm_hs_workqueue = create_singlethread_workqueue("msm_serial_hs"); | ||
1714 | if (unlikely(!msm_hs_workqueue)) | ||
1715 | return -ENOMEM; | ||
1716 | |||
1717 | ret = uart_register_driver(&msm_hs_driver); | ||
1718 | if (unlikely(ret)) { | ||
1719 | printk(KERN_ERR "%s failed to load\n", __func__); | ||
1720 | goto err_uart_register_driver; | ||
1721 | } | ||
1722 | |||
1723 | ret = platform_driver_register(&msm_serial_hs_platform_driver); | ||
1724 | if (ret) { | ||
1725 | printk(KERN_ERR "%s failed to load\n", __func__); | ||
1726 | goto err_platform_driver_register; | ||
1727 | } | ||
1728 | |||
1729 | return ret; | ||
1730 | |||
1731 | err_platform_driver_register: | ||
1732 | uart_unregister_driver(&msm_hs_driver); | ||
1733 | err_uart_register_driver: | ||
1734 | destroy_workqueue(msm_hs_workqueue); | ||
1735 | return ret; | ||
1736 | } | ||
1737 | module_init(msm_serial_hs_init); | ||
1738 | |||
1739 | /* | ||
1740 | * Called by the upper layer when port is closed. | ||
1741 | * - Disables the port | ||
1742 | * - Unhook the ISR | ||
1743 | */ | ||
1744 | static void msm_hs_shutdown(struct uart_port *uport) | ||
1745 | { | ||
1746 | unsigned long flags; | ||
1747 | struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); | ||
1748 | |||
1749 | BUG_ON(msm_uport->rx.flush < FLUSH_STOP); | ||
1750 | |||
1751 | spin_lock_irqsave(&uport->lock, flags); | ||
1752 | clk_enable(msm_uport->clk); | ||
1753 | |||
1754 | /* Disable the transmitter */ | ||
1755 | msm_hs_write(uport, UARTDM_CR_ADDR, UARTDM_CR_TX_DISABLE_BMSK); | ||
1756 | /* Disable the receiver */ | ||
1757 | msm_hs_write(uport, UARTDM_CR_ADDR, UARTDM_CR_RX_DISABLE_BMSK); | ||
1758 | |||
1759 | pm_runtime_disable(uport->dev); | ||
1760 | pm_runtime_set_suspended(uport->dev); | ||
1761 | |||
1762 | /* Free the interrupt */ | ||
1763 | free_irq(uport->irq, msm_uport); | ||
1764 | if (use_low_power_rx_wakeup(msm_uport)) | ||
1765 | free_irq(msm_uport->rx_wakeup.irq, msm_uport); | ||
1766 | |||
1767 | msm_uport->imr_reg = 0; | ||
1768 | msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg); | ||
1769 | |||
1770 | wait_event(msm_uport->rx.wait, msm_uport->rx.flush == FLUSH_SHUTDOWN); | ||
1771 | |||
1772 | clk_disable(msm_uport->clk); /* to balance local clk_enable() */ | ||
1773 | if (msm_uport->clk_state != MSM_HS_CLK_OFF) | ||
1774 | clk_disable(msm_uport->clk); /* to balance clk_state */ | ||
1775 | msm_uport->clk_state = MSM_HS_CLK_PORT_OFF; | ||
1776 | |||
1777 | dma_unmap_single(uport->dev, msm_uport->tx.dma_base, | ||
1778 | UART_XMIT_SIZE, DMA_TO_DEVICE); | ||
1779 | |||
1780 | spin_unlock_irqrestore(&uport->lock, flags); | ||
1781 | |||
1782 | if (cancel_work_sync(&msm_uport->rx.tty_work)) | ||
1783 | msm_hs_tty_flip_buffer_work(&msm_uport->rx.tty_work); | ||
1784 | } | ||
1785 | |||
1786 | static void __exit msm_serial_hs_exit(void) | ||
1787 | { | ||
1788 | flush_workqueue(msm_hs_workqueue); | ||
1789 | destroy_workqueue(msm_hs_workqueue); | ||
1790 | platform_driver_unregister(&msm_serial_hs_platform_driver); | ||
1791 | uart_unregister_driver(&msm_hs_driver); | ||
1792 | } | ||
1793 | module_exit(msm_serial_hs_exit); | ||
1794 | |||
1795 | #ifdef CONFIG_PM | ||
1796 | static int msm_hs_runtime_idle(struct device *dev) | ||
1797 | { | ||
1798 | /* | ||
1799 | * returning success from idle results in runtime suspend to be | ||
1800 | * called | ||
1801 | */ | ||
1802 | return 0; | ||
1803 | } | ||
1804 | |||
1805 | static int msm_hs_runtime_resume(struct device *dev) | ||
1806 | { | ||
1807 | struct platform_device *pdev = container_of(dev, struct | ||
1808 | platform_device, dev); | ||
1809 | struct msm_hs_port *msm_uport = &q_uart_port[pdev->id]; | ||
1810 | |||
1811 | msm_hs_request_clock_on(&msm_uport->uport); | ||
1812 | return 0; | ||
1813 | } | ||
1814 | |||
1815 | static int msm_hs_runtime_suspend(struct device *dev) | ||
1816 | { | ||
1817 | struct platform_device *pdev = container_of(dev, struct | ||
1818 | platform_device, dev); | ||
1819 | struct msm_hs_port *msm_uport = &q_uart_port[pdev->id]; | ||
1820 | |||
1821 | msm_hs_request_clock_off(&msm_uport->uport); | ||
1822 | return 0; | ||
1823 | } | ||
1824 | #else | ||
1825 | #define msm_hs_runtime_idle NULL | ||
1826 | #define msm_hs_runtime_resume NULL | ||
1827 | #define msm_hs_runtime_suspend NULL | ||
1828 | #endif | ||
1829 | |||
1830 | static const struct dev_pm_ops msm_hs_dev_pm_ops = { | ||
1831 | .runtime_suspend = msm_hs_runtime_suspend, | ||
1832 | .runtime_resume = msm_hs_runtime_resume, | ||
1833 | .runtime_idle = msm_hs_runtime_idle, | ||
1834 | }; | ||
1835 | |||
1836 | static struct platform_driver msm_serial_hs_platform_driver = { | ||
1837 | .probe = msm_hs_probe, | ||
1838 | .remove = msm_hs_remove, | ||
1839 | .driver = { | ||
1840 | .name = "msm_serial_hs", | ||
1841 | .pm = &msm_hs_dev_pm_ops, | ||
1842 | }, | ||
1843 | }; | ||
1844 | |||
1845 | static struct uart_driver msm_hs_driver = { | ||
1846 | .owner = THIS_MODULE, | ||
1847 | .driver_name = "msm_serial_hs", | ||
1848 | .dev_name = "ttyHS", | ||
1849 | .nr = UARTDM_NR, | ||
1850 | .cons = 0, | ||
1851 | }; | ||
1852 | |||
1853 | static struct uart_ops msm_hs_ops = { | ||
1854 | .tx_empty = msm_hs_tx_empty, | ||
1855 | .set_mctrl = msm_hs_set_mctrl_locked, | ||
1856 | .get_mctrl = msm_hs_get_mctrl_locked, | ||
1857 | .stop_tx = msm_hs_stop_tx_locked, | ||
1858 | .start_tx = msm_hs_start_tx_locked, | ||
1859 | .stop_rx = msm_hs_stop_rx_locked, | ||
1860 | .enable_ms = msm_hs_enable_ms_locked, | ||
1861 | .break_ctl = msm_hs_break_ctl, | ||
1862 | .startup = msm_hs_startup, | ||
1863 | .shutdown = msm_hs_shutdown, | ||
1864 | .set_termios = msm_hs_set_termios, | ||
1865 | .pm = msm_hs_pm, | ||
1866 | .type = msm_hs_type, | ||
1867 | .config_port = msm_hs_config_port, | ||
1868 | .release_port = msm_hs_release_port, | ||
1869 | .request_port = msm_hs_request_port, | ||
1870 | }; | ||
1871 | |||
1872 | MODULE_DESCRIPTION("High Speed UART Driver for the MSM chipset"); | ||
1873 | MODULE_VERSION("1.2"); | ||
1874 | MODULE_LICENSE("GPL v2"); | ||
diff --git a/drivers/tty/serial/mxs-auart.c b/drivers/tty/serial/mxs-auart.c index d1298b6cc68e..f7e5825b55ab 100644 --- a/drivers/tty/serial/mxs-auart.c +++ b/drivers/tty/serial/mxs-auart.c | |||
@@ -176,7 +176,7 @@ static struct platform_device_id mxs_auart_devtype[] = { | |||
176 | }; | 176 | }; |
177 | MODULE_DEVICE_TABLE(platform, mxs_auart_devtype); | 177 | MODULE_DEVICE_TABLE(platform, mxs_auart_devtype); |
178 | 178 | ||
179 | static struct of_device_id mxs_auart_dt_ids[] = { | 179 | static const struct of_device_id mxs_auart_dt_ids[] = { |
180 | { | 180 | { |
181 | .compatible = "fsl,imx28-auart", | 181 | .compatible = "fsl,imx28-auart", |
182 | .data = &mxs_auart_devtype[IMX28_AUART] | 182 | .data = &mxs_auart_devtype[IMX28_AUART] |
@@ -1155,14 +1155,14 @@ static int serial_mxs_probe_dt(struct mxs_auart_port *s, | |||
1155 | return 0; | 1155 | return 0; |
1156 | } | 1156 | } |
1157 | 1157 | ||
1158 | static bool mxs_auart_init_gpios(struct mxs_auart_port *s, struct device *dev) | 1158 | static int mxs_auart_init_gpios(struct mxs_auart_port *s, struct device *dev) |
1159 | { | 1159 | { |
1160 | enum mctrl_gpio_idx i; | 1160 | enum mctrl_gpio_idx i; |
1161 | struct gpio_desc *gpiod; | 1161 | struct gpio_desc *gpiod; |
1162 | 1162 | ||
1163 | s->gpios = mctrl_gpio_init(dev, 0); | 1163 | s->gpios = mctrl_gpio_init(dev, 0); |
1164 | if (IS_ERR_OR_NULL(s->gpios)) | 1164 | if (IS_ERR(s->gpios)) |
1165 | return false; | 1165 | return PTR_ERR(s->gpios); |
1166 | 1166 | ||
1167 | /* Block (enabled before) DMA option if RTS or CTS is GPIO line */ | 1167 | /* Block (enabled before) DMA option if RTS or CTS is GPIO line */ |
1168 | if (!RTS_AT_AUART() || !CTS_AT_AUART()) { | 1168 | if (!RTS_AT_AUART() || !CTS_AT_AUART()) { |
@@ -1180,7 +1180,7 @@ static bool mxs_auart_init_gpios(struct mxs_auart_port *s, struct device *dev) | |||
1180 | s->gpio_irq[i] = -EINVAL; | 1180 | s->gpio_irq[i] = -EINVAL; |
1181 | } | 1181 | } |
1182 | 1182 | ||
1183 | return true; | 1183 | return 0; |
1184 | } | 1184 | } |
1185 | 1185 | ||
1186 | static void mxs_auart_free_gpio_irq(struct mxs_auart_port *s) | 1186 | static void mxs_auart_free_gpio_irq(struct mxs_auart_port *s) |
@@ -1276,9 +1276,11 @@ static int mxs_auart_probe(struct platform_device *pdev) | |||
1276 | 1276 | ||
1277 | platform_set_drvdata(pdev, s); | 1277 | platform_set_drvdata(pdev, s); |
1278 | 1278 | ||
1279 | if (!mxs_auart_init_gpios(s, &pdev->dev)) | 1279 | ret = mxs_auart_init_gpios(s, &pdev->dev); |
1280 | dev_err(&pdev->dev, | 1280 | if (ret) { |
1281 | "Failed to initialize GPIOs. The serial port may not work as expected\n"); | 1281 | dev_err(&pdev->dev, "Failed to initialize GPIOs.\n"); |
1282 | return ret; | ||
1283 | } | ||
1282 | 1284 | ||
1283 | /* | 1285 | /* |
1284 | * Get the GPIO lines IRQ | 1286 | * Get the GPIO lines IRQ |
diff --git a/drivers/tty/serial/of_serial.c b/drivers/tty/serial/of_serial.c index 33fb94f78967..aa00154c4a6d 100644 --- a/drivers/tty/serial/of_serial.c +++ b/drivers/tty/serial/of_serial.c | |||
@@ -89,6 +89,7 @@ static int of_platform_serial_setup(struct platform_device *ofdev, | |||
89 | 89 | ||
90 | spin_lock_init(&port->lock); | 90 | spin_lock_init(&port->lock); |
91 | port->mapbase = resource.start; | 91 | port->mapbase = resource.start; |
92 | port->mapsize = resource_size(&resource); | ||
92 | 93 | ||
93 | /* Check for shifted address mapping */ | 94 | /* Check for shifted address mapping */ |
94 | if (of_property_read_u32(np, "reg-offset", &prop) == 0) | 95 | if (of_property_read_u32(np, "reg-offset", &prop) == 0) |
@@ -155,7 +156,7 @@ out: | |||
155 | /* | 156 | /* |
156 | * Try to register a serial port | 157 | * Try to register a serial port |
157 | */ | 158 | */ |
158 | static struct of_device_id of_platform_serial_table[]; | 159 | static const struct of_device_id of_platform_serial_table[]; |
159 | static int of_platform_serial_probe(struct platform_device *ofdev) | 160 | static int of_platform_serial_probe(struct platform_device *ofdev) |
160 | { | 161 | { |
161 | const struct of_device_id *match; | 162 | const struct of_device_id *match; |
@@ -320,7 +321,7 @@ static SIMPLE_DEV_PM_OPS(of_serial_pm_ops, of_serial_suspend, of_serial_resume); | |||
320 | /* | 321 | /* |
321 | * A few common types, add more as needed. | 322 | * A few common types, add more as needed. |
322 | */ | 323 | */ |
323 | static struct of_device_id of_platform_serial_table[] = { | 324 | static const struct of_device_id of_platform_serial_table[] = { |
324 | { .compatible = "ns8250", .data = (void *)PORT_8250, }, | 325 | { .compatible = "ns8250", .data = (void *)PORT_8250, }, |
325 | { .compatible = "ns16450", .data = (void *)PORT_16450, }, | 326 | { .compatible = "ns16450", .data = (void *)PORT_16450, }, |
326 | { .compatible = "ns16550a", .data = (void *)PORT_16550A, }, | 327 | { .compatible = "ns16550a", .data = (void *)PORT_16550A, }, |
diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c index 10256fa04b40..211479aa34bb 100644 --- a/drivers/tty/serial/omap-serial.c +++ b/drivers/tty/serial/omap-serial.c | |||
@@ -1654,11 +1654,6 @@ static int serial_omap_probe(struct platform_device *pdev) | |||
1654 | up->port.type = PORT_OMAP; | 1654 | up->port.type = PORT_OMAP; |
1655 | up->port.iotype = UPIO_MEM; | 1655 | up->port.iotype = UPIO_MEM; |
1656 | up->port.irq = uartirq; | 1656 | up->port.irq = uartirq; |
1657 | up->wakeirq = wakeirq; | ||
1658 | if (!up->wakeirq) | ||
1659 | dev_info(up->port.dev, "no wakeirq for uart%d\n", | ||
1660 | up->port.line); | ||
1661 | |||
1662 | up->port.regshift = 2; | 1657 | up->port.regshift = 2; |
1663 | up->port.fifosize = 64; | 1658 | up->port.fifosize = 64; |
1664 | up->port.ops = &serial_omap_pops; | 1659 | up->port.ops = &serial_omap_pops; |
@@ -1682,6 +1677,11 @@ static int serial_omap_probe(struct platform_device *pdev) | |||
1682 | goto err_port_line; | 1677 | goto err_port_line; |
1683 | } | 1678 | } |
1684 | 1679 | ||
1680 | up->wakeirq = wakeirq; | ||
1681 | if (!up->wakeirq) | ||
1682 | dev_info(up->port.dev, "no wakeirq for uart%d\n", | ||
1683 | up->port.line); | ||
1684 | |||
1685 | ret = serial_omap_probe_rs485(up, pdev->dev.of_node); | 1685 | ret = serial_omap_probe_rs485(up, pdev->dev.of_node); |
1686 | if (ret < 0) | 1686 | if (ret < 0) |
1687 | goto err_rs485; | 1687 | goto err_rs485; |
diff --git a/drivers/tty/serial/pmac_zilog.c b/drivers/tty/serial/pmac_zilog.c index 8f515799c9c1..e156e39d620c 100644 --- a/drivers/tty/serial/pmac_zilog.c +++ b/drivers/tty/serial/pmac_zilog.c | |||
@@ -1846,7 +1846,7 @@ static int __init pmz_register(void) | |||
1846 | 1846 | ||
1847 | #ifdef CONFIG_PPC_PMAC | 1847 | #ifdef CONFIG_PPC_PMAC |
1848 | 1848 | ||
1849 | static struct of_device_id pmz_match[] = | 1849 | static const struct of_device_id pmz_match[] = |
1850 | { | 1850 | { |
1851 | { | 1851 | { |
1852 | .name = "ch-a", | 1852 | .name = "ch-a", |
diff --git a/drivers/tty/serial/pxa.c b/drivers/tty/serial/pxa.c index d5d062694bd3..9becba654892 100644 --- a/drivers/tty/serial/pxa.c +++ b/drivers/tty/serial/pxa.c | |||
@@ -824,7 +824,7 @@ static const struct dev_pm_ops serial_pxa_pm_ops = { | |||
824 | }; | 824 | }; |
825 | #endif | 825 | #endif |
826 | 826 | ||
827 | static struct of_device_id serial_pxa_dt_ids[] = { | 827 | static const struct of_device_id serial_pxa_dt_ids[] = { |
828 | { .compatible = "mrvl,pxa-uart", }, | 828 | { .compatible = "mrvl,pxa-uart", }, |
829 | { .compatible = "mrvl,mmp-uart", }, | 829 | { .compatible = "mrvl,mmp-uart", }, |
830 | {} | 830 | {} |
diff --git a/drivers/tty/serial/sc16is7xx.c b/drivers/tty/serial/sc16is7xx.c index df9a384dfbda..468354ef7baa 100644 --- a/drivers/tty/serial/sc16is7xx.c +++ b/drivers/tty/serial/sc16is7xx.c | |||
@@ -829,16 +829,32 @@ static void sc16is7xx_set_termios(struct uart_port *port, | |||
829 | } | 829 | } |
830 | 830 | ||
831 | static int sc16is7xx_config_rs485(struct uart_port *port, | 831 | static int sc16is7xx_config_rs485(struct uart_port *port, |
832 | struct serial_rs485 *rs485) | 832 | struct serial_rs485 *rs485) |
833 | { | 833 | { |
834 | if (port->rs485.flags & SER_RS485_ENABLED) | 834 | const u32 mask = SC16IS7XX_EFCR_AUTO_RS485_BIT | |
835 | sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, | 835 | SC16IS7XX_EFCR_RTS_INVERT_BIT; |
836 | SC16IS7XX_EFCR_AUTO_RS485_BIT, | 836 | u32 efcr = 0; |
837 | SC16IS7XX_EFCR_AUTO_RS485_BIT); | 837 | |
838 | else | 838 | if (rs485->flags & SER_RS485_ENABLED) { |
839 | sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, | 839 | bool rts_during_rx, rts_during_tx; |
840 | SC16IS7XX_EFCR_AUTO_RS485_BIT, | 840 | |
841 | 0); | 841 | rts_during_rx = rs485->flags & SER_RS485_RTS_AFTER_SEND; |
842 | rts_during_tx = rs485->flags & SER_RS485_RTS_ON_SEND; | ||
843 | |||
844 | efcr |= SC16IS7XX_EFCR_AUTO_RS485_BIT; | ||
845 | |||
846 | if (!rts_during_rx && rts_during_tx) | ||
847 | /* default */; | ||
848 | else if (rts_during_rx && !rts_during_tx) | ||
849 | efcr |= SC16IS7XX_EFCR_RTS_INVERT_BIT; | ||
850 | else | ||
851 | dev_err(port->dev, | ||
852 | "unsupported RTS signalling on_send:%d after_send:%d - exactly one of RS485 RTS flags should be set\n", | ||
853 | rts_during_tx, rts_during_rx); | ||
854 | } | ||
855 | |||
856 | sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, mask, efcr); | ||
857 | |||
842 | port->rs485 = *rs485; | 858 | port->rs485 = *rs485; |
843 | 859 | ||
844 | return 0; | 860 | return 0; |
@@ -903,9 +919,11 @@ static void sc16is7xx_shutdown(struct uart_port *port) | |||
903 | /* Disable all interrupts */ | 919 | /* Disable all interrupts */ |
904 | sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0); | 920 | sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0); |
905 | /* Disable TX/RX */ | 921 | /* Disable TX/RX */ |
906 | sc16is7xx_port_write(port, SC16IS7XX_EFCR_REG, | 922 | sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, |
907 | SC16IS7XX_EFCR_RXDISABLE_BIT | | 923 | SC16IS7XX_EFCR_RXDISABLE_BIT | |
908 | SC16IS7XX_EFCR_TXDISABLE_BIT); | 924 | SC16IS7XX_EFCR_TXDISABLE_BIT, |
925 | SC16IS7XX_EFCR_RXDISABLE_BIT | | ||
926 | SC16IS7XX_EFCR_TXDISABLE_BIT); | ||
909 | 927 | ||
910 | sc16is7xx_power(port, 0); | 928 | sc16is7xx_power(port, 0); |
911 | } | 929 | } |
@@ -1048,6 +1066,7 @@ static int sc16is7xx_probe(struct device *dev, | |||
1048 | else | 1066 | else |
1049 | return PTR_ERR(s->clk); | 1067 | return PTR_ERR(s->clk); |
1050 | } else { | 1068 | } else { |
1069 | clk_prepare_enable(s->clk); | ||
1051 | freq = clk_get_rate(s->clk); | 1070 | freq = clk_get_rate(s->clk); |
1052 | } | 1071 | } |
1053 | 1072 | ||
@@ -1120,6 +1139,9 @@ static int sc16is7xx_probe(struct device *dev, | |||
1120 | if (!ret) | 1139 | if (!ret) |
1121 | return 0; | 1140 | return 0; |
1122 | 1141 | ||
1142 | for (i = 0; i < s->uart.nr; i++) | ||
1143 | uart_remove_one_port(&s->uart, &s->p[i].port); | ||
1144 | |||
1123 | mutex_destroy(&s->mutex); | 1145 | mutex_destroy(&s->mutex); |
1124 | 1146 | ||
1125 | #ifdef CONFIG_GPIOLIB | 1147 | #ifdef CONFIG_GPIOLIB |
diff --git a/drivers/tty/serial/serial-tegra.c b/drivers/tty/serial/serial-tegra.c index 48e6e41636b2..1d5ea3964ee5 100644 --- a/drivers/tty/serial/serial-tegra.c +++ b/drivers/tty/serial/serial-tegra.c | |||
@@ -1251,7 +1251,7 @@ static struct tegra_uart_chip_data tegra30_uart_chip_data = { | |||
1251 | .support_clk_src_div = true, | 1251 | .support_clk_src_div = true, |
1252 | }; | 1252 | }; |
1253 | 1253 | ||
1254 | static struct of_device_id tegra_uart_of_match[] = { | 1254 | static const struct of_device_id tegra_uart_of_match[] = { |
1255 | { | 1255 | { |
1256 | .compatible = "nvidia,tegra30-hsuart", | 1256 | .compatible = "nvidia,tegra30-hsuart", |
1257 | .data = &tegra30_uart_chip_data, | 1257 | .data = &tegra30_uart_chip_data, |
diff --git a/drivers/tty/serial/serial_core.c b/drivers/tty/serial/serial_core.c index 6a1055ae3437..eb5b03be9dfd 100644 --- a/drivers/tty/serial/serial_core.c +++ b/drivers/tty/serial/serial_core.c | |||
@@ -1118,8 +1118,7 @@ uart_wait_modem_status(struct uart_state *state, unsigned long arg) | |||
1118 | 1118 | ||
1119 | cprev = cnow; | 1119 | cprev = cnow; |
1120 | } | 1120 | } |
1121 | 1121 | __set_current_state(TASK_RUNNING); | |
1122 | current->state = TASK_RUNNING; | ||
1123 | remove_wait_queue(&port->delta_msr_wait, &wait); | 1122 | remove_wait_queue(&port->delta_msr_wait, &wait); |
1124 | 1123 | ||
1125 | return ret; | 1124 | return ret; |
@@ -1766,7 +1765,7 @@ static const struct file_operations uart_proc_fops = { | |||
1766 | #endif | 1765 | #endif |
1767 | 1766 | ||
1768 | #if defined(CONFIG_SERIAL_CORE_CONSOLE) || defined(CONFIG_CONSOLE_POLL) | 1767 | #if defined(CONFIG_SERIAL_CORE_CONSOLE) || defined(CONFIG_CONSOLE_POLL) |
1769 | /* | 1768 | /** |
1770 | * uart_console_write - write a console message to a serial port | 1769 | * uart_console_write - write a console message to a serial port |
1771 | * @port: the port to write the message | 1770 | * @port: the port to write the message |
1772 | * @s: array of characters | 1771 | * @s: array of characters |
@@ -1810,6 +1809,52 @@ uart_get_console(struct uart_port *ports, int nr, struct console *co) | |||
1810 | } | 1809 | } |
1811 | 1810 | ||
1812 | /** | 1811 | /** |
1812 | * uart_parse_earlycon - Parse earlycon options | ||
1813 | * @p: ptr to 2nd field (ie., just beyond '<name>,') | ||
1814 | * @iotype: ptr for decoded iotype (out) | ||
1815 | * @addr: ptr for decoded mapbase/iobase (out) | ||
1816 | * @options: ptr for <options> field; NULL if not present (out) | ||
1817 | * | ||
1818 | * Decodes earlycon kernel command line parameters of the form | ||
1819 | * earlycon=<name>,io|mmio|mmio32,<addr>,<options> | ||
1820 | * console=<name>,io|mmio|mmio32,<addr>,<options> | ||
1821 | * | ||
1822 | * The optional form | ||
1823 | * earlycon=<name>,0x<addr>,<options> | ||
1824 | * console=<name>,0x<addr>,<options> | ||
1825 | * is also accepted; the returned @iotype will be UPIO_MEM. | ||
1826 | * | ||
1827 | * Returns 0 on success or -EINVAL on failure | ||
1828 | */ | ||
1829 | int uart_parse_earlycon(char *p, unsigned char *iotype, unsigned long *addr, | ||
1830 | char **options) | ||
1831 | { | ||
1832 | if (strncmp(p, "mmio,", 5) == 0) { | ||
1833 | *iotype = UPIO_MEM; | ||
1834 | p += 5; | ||
1835 | } else if (strncmp(p, "mmio32,", 7) == 0) { | ||
1836 | *iotype = UPIO_MEM32; | ||
1837 | p += 7; | ||
1838 | } else if (strncmp(p, "io,", 3) == 0) { | ||
1839 | *iotype = UPIO_PORT; | ||
1840 | p += 3; | ||
1841 | } else if (strncmp(p, "0x", 2) == 0) { | ||
1842 | *iotype = UPIO_MEM; | ||
1843 | } else { | ||
1844 | return -EINVAL; | ||
1845 | } | ||
1846 | |||
1847 | *addr = simple_strtoul(p, NULL, 0); | ||
1848 | p = strchr(p, ','); | ||
1849 | if (p) | ||
1850 | p++; | ||
1851 | |||
1852 | *options = p; | ||
1853 | return 0; | ||
1854 | } | ||
1855 | EXPORT_SYMBOL_GPL(uart_parse_earlycon); | ||
1856 | |||
1857 | /** | ||
1813 | * uart_parse_options - Parse serial port baud/parity/bits/flow control. | 1858 | * uart_parse_options - Parse serial port baud/parity/bits/flow control. |
1814 | * @options: pointer to option string | 1859 | * @options: pointer to option string |
1815 | * @baud: pointer to an 'int' variable for the baud rate. | 1860 | * @baud: pointer to an 'int' variable for the baud rate. |
@@ -2637,6 +2682,7 @@ int uart_add_one_port(struct uart_driver *drv, struct uart_port *uport) | |||
2637 | 2682 | ||
2638 | state->pm_state = UART_PM_STATE_UNDEFINED; | 2683 | state->pm_state = UART_PM_STATE_UNDEFINED; |
2639 | uport->cons = drv->cons; | 2684 | uport->cons = drv->cons; |
2685 | uport->minor = drv->tty_driver->minor_start + uport->line; | ||
2640 | 2686 | ||
2641 | /* | 2687 | /* |
2642 | * If this port is a console, then the spinlock is already | 2688 | * If this port is a console, then the spinlock is already |
diff --git a/drivers/tty/serial/serial_mctrl_gpio.c b/drivers/tty/serial/serial_mctrl_gpio.c index a38596c5194e..0ec756c62bcf 100644 --- a/drivers/tty/serial/serial_mctrl_gpio.c +++ b/drivers/tty/serial/serial_mctrl_gpio.c | |||
@@ -48,9 +48,6 @@ void mctrl_gpio_set(struct mctrl_gpios *gpios, unsigned int mctrl) | |||
48 | int value_array[UART_GPIO_MAX]; | 48 | int value_array[UART_GPIO_MAX]; |
49 | unsigned int count = 0; | 49 | unsigned int count = 0; |
50 | 50 | ||
51 | if (IS_ERR_OR_NULL(gpios)) | ||
52 | return; | ||
53 | |||
54 | for (i = 0; i < UART_GPIO_MAX; i++) | 51 | for (i = 0; i < UART_GPIO_MAX; i++) |
55 | if (!IS_ERR_OR_NULL(gpios->gpio[i]) && | 52 | if (!IS_ERR_OR_NULL(gpios->gpio[i]) && |
56 | mctrl_gpios_desc[i].dir_out) { | 53 | mctrl_gpios_desc[i].dir_out) { |
@@ -65,10 +62,7 @@ EXPORT_SYMBOL_GPL(mctrl_gpio_set); | |||
65 | struct gpio_desc *mctrl_gpio_to_gpiod(struct mctrl_gpios *gpios, | 62 | struct gpio_desc *mctrl_gpio_to_gpiod(struct mctrl_gpios *gpios, |
66 | enum mctrl_gpio_idx gidx) | 63 | enum mctrl_gpio_idx gidx) |
67 | { | 64 | { |
68 | if (!IS_ERR_OR_NULL(gpios) && !IS_ERR_OR_NULL(gpios->gpio[gidx])) | 65 | return gpios->gpio[gidx]; |
69 | return gpios->gpio[gidx]; | ||
70 | else | ||
71 | return NULL; | ||
72 | } | 66 | } |
73 | EXPORT_SYMBOL_GPL(mctrl_gpio_to_gpiod); | 67 | EXPORT_SYMBOL_GPL(mctrl_gpio_to_gpiod); |
74 | 68 | ||
@@ -76,15 +70,8 @@ unsigned int mctrl_gpio_get(struct mctrl_gpios *gpios, unsigned int *mctrl) | |||
76 | { | 70 | { |
77 | enum mctrl_gpio_idx i; | 71 | enum mctrl_gpio_idx i; |
78 | 72 | ||
79 | /* | ||
80 | * return it unchanged if the structure is not allocated | ||
81 | */ | ||
82 | if (IS_ERR_OR_NULL(gpios)) | ||
83 | return *mctrl; | ||
84 | |||
85 | for (i = 0; i < UART_GPIO_MAX; i++) { | 73 | for (i = 0; i < UART_GPIO_MAX; i++) { |
86 | if (!IS_ERR_OR_NULL(gpios->gpio[i]) && | 74 | if (gpios->gpio[i] && !mctrl_gpios_desc[i].dir_out) { |
87 | !mctrl_gpios_desc[i].dir_out) { | ||
88 | if (gpiod_get_value(gpios->gpio[i])) | 75 | if (gpiod_get_value(gpios->gpio[i])) |
89 | *mctrl |= mctrl_gpios_desc[i].mctrl; | 76 | *mctrl |= mctrl_gpios_desc[i].mctrl; |
90 | else | 77 | else |
@@ -100,34 +87,26 @@ struct mctrl_gpios *mctrl_gpio_init(struct device *dev, unsigned int idx) | |||
100 | { | 87 | { |
101 | struct mctrl_gpios *gpios; | 88 | struct mctrl_gpios *gpios; |
102 | enum mctrl_gpio_idx i; | 89 | enum mctrl_gpio_idx i; |
103 | int err; | ||
104 | 90 | ||
105 | gpios = devm_kzalloc(dev, sizeof(*gpios), GFP_KERNEL); | 91 | gpios = devm_kzalloc(dev, sizeof(*gpios), GFP_KERNEL); |
106 | if (!gpios) | 92 | if (!gpios) |
107 | return ERR_PTR(-ENOMEM); | 93 | return ERR_PTR(-ENOMEM); |
108 | 94 | ||
109 | for (i = 0; i < UART_GPIO_MAX; i++) { | 95 | for (i = 0; i < UART_GPIO_MAX; i++) { |
110 | gpios->gpio[i] = devm_gpiod_get_index(dev, | 96 | enum gpiod_flags flags; |
111 | mctrl_gpios_desc[i].name, | ||
112 | idx); | ||
113 | |||
114 | /* | ||
115 | * The GPIOs are maybe not all filled, | ||
116 | * this is not an error. | ||
117 | */ | ||
118 | if (IS_ERR_OR_NULL(gpios->gpio[i])) | ||
119 | continue; | ||
120 | 97 | ||
121 | if (mctrl_gpios_desc[i].dir_out) | 98 | if (mctrl_gpios_desc[i].dir_out) |
122 | err = gpiod_direction_output(gpios->gpio[i], 0); | 99 | flags = GPIOD_OUT_LOW; |
123 | else | 100 | else |
124 | err = gpiod_direction_input(gpios->gpio[i]); | 101 | flags = GPIOD_IN; |
125 | if (err) { | 102 | |
126 | dev_dbg(dev, "Unable to set direction for %s GPIO", | 103 | gpios->gpio[i] = |
127 | mctrl_gpios_desc[i].name); | 104 | devm_gpiod_get_index_optional(dev, |
128 | devm_gpiod_put(dev, gpios->gpio[i]); | 105 | mctrl_gpios_desc[i].name, |
129 | gpios->gpio[i] = NULL; | 106 | idx, flags); |
130 | } | 107 | |
108 | if (IS_ERR(gpios->gpio[i])) | ||
109 | return ERR_CAST(gpios->gpio[i]); | ||
131 | } | 110 | } |
132 | 111 | ||
133 | return gpios; | 112 | return gpios; |
@@ -138,9 +117,6 @@ void mctrl_gpio_free(struct device *dev, struct mctrl_gpios *gpios) | |||
138 | { | 117 | { |
139 | enum mctrl_gpio_idx i; | 118 | enum mctrl_gpio_idx i; |
140 | 119 | ||
141 | if (IS_ERR_OR_NULL(gpios)) | ||
142 | return; | ||
143 | |||
144 | for (i = 0; i < UART_GPIO_MAX; i++) | 120 | for (i = 0; i < UART_GPIO_MAX; i++) |
145 | if (!IS_ERR_OR_NULL(gpios->gpio[i])) | 121 | if (!IS_ERR_OR_NULL(gpios->gpio[i])) |
146 | devm_gpiod_put(dev, gpios->gpio[i]); | 122 | devm_gpiod_put(dev, gpios->gpio[i]); |
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index 5b50c792ad5f..e7d6566fafaf 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c | |||
@@ -844,14 +844,32 @@ static int sci_handle_fifo_overrun(struct uart_port *port) | |||
844 | struct tty_port *tport = &port->state->port; | 844 | struct tty_port *tport = &port->state->port; |
845 | struct sci_port *s = to_sci_port(port); | 845 | struct sci_port *s = to_sci_port(port); |
846 | struct plat_sci_reg *reg; | 846 | struct plat_sci_reg *reg; |
847 | int copied = 0; | 847 | int copied = 0, offset; |
848 | u16 status, bit; | ||
849 | |||
850 | switch (port->type) { | ||
851 | case PORT_SCIF: | ||
852 | case PORT_HSCIF: | ||
853 | offset = SCLSR; | ||
854 | break; | ||
855 | case PORT_SCIFA: | ||
856 | case PORT_SCIFB: | ||
857 | offset = SCxSR; | ||
858 | break; | ||
859 | default: | ||
860 | return 0; | ||
861 | } | ||
848 | 862 | ||
849 | reg = sci_getreg(port, SCLSR); | 863 | reg = sci_getreg(port, offset); |
850 | if (!reg->size) | 864 | if (!reg->size) |
851 | return 0; | 865 | return 0; |
852 | 866 | ||
853 | if ((serial_port_in(port, SCLSR) & (1 << s->overrun_bit))) { | 867 | status = serial_port_in(port, offset); |
854 | serial_port_out(port, SCLSR, 0); | 868 | bit = 1 << s->overrun_bit; |
869 | |||
870 | if (status & bit) { | ||
871 | status &= ~bit; | ||
872 | serial_port_out(port, offset, status); | ||
855 | 873 | ||
856 | port->icount.overrun++; | 874 | port->icount.overrun++; |
857 | 875 | ||
@@ -996,16 +1014,24 @@ static inline unsigned long port_rx_irq_mask(struct uart_port *port) | |||
996 | 1014 | ||
997 | static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) | 1015 | static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) |
998 | { | 1016 | { |
999 | unsigned short ssr_status, scr_status, err_enabled; | 1017 | unsigned short ssr_status, scr_status, err_enabled, orer_status = 0; |
1000 | unsigned short slr_status = 0; | ||
1001 | struct uart_port *port = ptr; | 1018 | struct uart_port *port = ptr; |
1002 | struct sci_port *s = to_sci_port(port); | 1019 | struct sci_port *s = to_sci_port(port); |
1003 | irqreturn_t ret = IRQ_NONE; | 1020 | irqreturn_t ret = IRQ_NONE; |
1004 | 1021 | ||
1005 | ssr_status = serial_port_in(port, SCxSR); | 1022 | ssr_status = serial_port_in(port, SCxSR); |
1006 | scr_status = serial_port_in(port, SCSCR); | 1023 | scr_status = serial_port_in(port, SCSCR); |
1007 | if (port->type == PORT_SCIF || port->type == PORT_HSCIF) | 1024 | switch (port->type) { |
1008 | slr_status = serial_port_in(port, SCLSR); | 1025 | case PORT_SCIF: |
1026 | case PORT_HSCIF: | ||
1027 | orer_status = serial_port_in(port, SCLSR); | ||
1028 | break; | ||
1029 | case PORT_SCIFA: | ||
1030 | case PORT_SCIFB: | ||
1031 | orer_status = ssr_status; | ||
1032 | break; | ||
1033 | } | ||
1034 | |||
1009 | err_enabled = scr_status & port_rx_irq_mask(port); | 1035 | err_enabled = scr_status & port_rx_irq_mask(port); |
1010 | 1036 | ||
1011 | /* Tx Interrupt */ | 1037 | /* Tx Interrupt */ |
@@ -1033,10 +1059,8 @@ static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) | |||
1033 | ret = sci_br_interrupt(irq, ptr); | 1059 | ret = sci_br_interrupt(irq, ptr); |
1034 | 1060 | ||
1035 | /* Overrun Interrupt */ | 1061 | /* Overrun Interrupt */ |
1036 | if (port->type == PORT_SCIF || port->type == PORT_HSCIF) { | 1062 | if (orer_status & (1 << s->overrun_bit)) |
1037 | if (slr_status & 0x01) | 1063 | sci_handle_fifo_overrun(port); |
1038 | sci_handle_fifo_overrun(port); | ||
1039 | } | ||
1040 | 1064 | ||
1041 | return ret; | 1065 | return ret; |
1042 | } | 1066 | } |
@@ -1967,18 +1991,40 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios, | |||
1967 | 1991 | ||
1968 | #ifdef CONFIG_SERIAL_SH_SCI_DMA | 1992 | #ifdef CONFIG_SERIAL_SH_SCI_DMA |
1969 | /* | 1993 | /* |
1970 | * Calculate delay for 1.5 DMA buffers: see | 1994 | * Calculate delay for 2 DMA buffers (4 FIFO). |
1971 | * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits | 1995 | * See drivers/serial/serial_core.c::uart_update_timeout(). With 10 |
1972 | * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function | 1996 | * bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function |
1973 | * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)." | 1997 | * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)." |
1974 | * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO | 1998 | * Then below we calculate 5 jiffies (20ms) for 2 DMA buffers (4 FIFO |
1975 | * sizes), but it has been found out experimentally, that this is not | 1999 | * sizes), but when performing a faster transfer, value obtained by |
1976 | * enough: the driver too often needlessly runs on a DMA timeout. 20ms | 2000 | * this formula is may not enough. Therefore, if value is smaller than |
1977 | * as a minimum seem to work perfectly. | 2001 | * 20msec, this sets 20msec as timeout of DMA. |
1978 | */ | 2002 | */ |
1979 | if (s->chan_rx) { | 2003 | if (s->chan_rx) { |
1980 | s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 / | 2004 | unsigned int bits; |
1981 | port->fifosize / 2; | 2005 | |
2006 | /* byte size and parity */ | ||
2007 | switch (termios->c_cflag & CSIZE) { | ||
2008 | case CS5: | ||
2009 | bits = 7; | ||
2010 | break; | ||
2011 | case CS6: | ||
2012 | bits = 8; | ||
2013 | break; | ||
2014 | case CS7: | ||
2015 | bits = 9; | ||
2016 | break; | ||
2017 | default: | ||
2018 | bits = 10; | ||
2019 | break; | ||
2020 | } | ||
2021 | |||
2022 | if (termios->c_cflag & CSTOPB) | ||
2023 | bits++; | ||
2024 | if (termios->c_cflag & PARENB) | ||
2025 | bits++; | ||
2026 | s->rx_timeout = DIV_ROUND_UP((s->buf_len_rx * 2 * bits * HZ) / | ||
2027 | (baud / 10), 10); | ||
1982 | dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n", | 2028 | dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n", |
1983 | s->rx_timeout * 1000 / HZ, port->timeout); | 2029 | s->rx_timeout * 1000 / HZ, port->timeout); |
1984 | if (s->rx_timeout < msecs_to_jiffies(20)) | 2030 | if (s->rx_timeout < msecs_to_jiffies(20)) |
diff --git a/drivers/tty/serial/sirfsoc_uart.c b/drivers/tty/serial/sirfsoc_uart.c index 27ed0e960880..9de3eabe5737 100644 --- a/drivers/tty/serial/sirfsoc_uart.c +++ b/drivers/tty/serial/sirfsoc_uart.c | |||
@@ -1269,7 +1269,7 @@ static struct uart_driver sirfsoc_uart_drv = { | |||
1269 | #endif | 1269 | #endif |
1270 | }; | 1270 | }; |
1271 | 1271 | ||
1272 | static struct of_device_id sirfsoc_uart_ids[] = { | 1272 | static const struct of_device_id sirfsoc_uart_ids[] = { |
1273 | { .compatible = "sirf,prima2-uart", .data = &sirfsoc_uart,}, | 1273 | { .compatible = "sirf,prima2-uart", .data = &sirfsoc_uart,}, |
1274 | { .compatible = "sirf,atlas7-uart", .data = &sirfsoc_uart}, | 1274 | { .compatible = "sirf,atlas7-uart", .data = &sirfsoc_uart}, |
1275 | { .compatible = "sirf,prima2-usp-uart", .data = &sirfsoc_usp}, | 1275 | { .compatible = "sirf,prima2-usp-uart", .data = &sirfsoc_usp}, |
diff --git a/drivers/tty/serial/sprd_serial.c b/drivers/tty/serial/sprd_serial.c index bca975f5093b..582d2729f700 100644 --- a/drivers/tty/serial/sprd_serial.c +++ b/drivers/tty/serial/sprd_serial.c | |||
@@ -493,6 +493,8 @@ static int sprd_verify_port(struct uart_port *port, | |||
493 | return -EINVAL; | 493 | return -EINVAL; |
494 | if (port->irq != ser->irq) | 494 | if (port->irq != ser->irq) |
495 | return -EINVAL; | 495 | return -EINVAL; |
496 | if (port->iotype != ser->io_type) | ||
497 | return -EINVAL; | ||
496 | return 0; | 498 | return 0; |
497 | } | 499 | } |
498 | 500 | ||
@@ -707,7 +709,7 @@ static int sprd_probe(struct platform_device *pdev) | |||
707 | up->dev = &pdev->dev; | 709 | up->dev = &pdev->dev; |
708 | up->line = index; | 710 | up->line = index; |
709 | up->type = PORT_SPRD; | 711 | up->type = PORT_SPRD; |
710 | up->iotype = SERIAL_IO_PORT; | 712 | up->iotype = UPIO_MEM; |
711 | up->uartclk = SPRD_DEF_RATE; | 713 | up->uartclk = SPRD_DEF_RATE; |
712 | up->fifosize = SPRD_FIFO_SIZE; | 714 | up->fifosize = SPRD_FIFO_SIZE; |
713 | up->ops = &serial_sprd_ops; | 715 | up->ops = &serial_sprd_ops; |
@@ -754,6 +756,7 @@ static int sprd_probe(struct platform_device *pdev) | |||
754 | return ret; | 756 | return ret; |
755 | } | 757 | } |
756 | 758 | ||
759 | #ifdef CONFIG_PM_SLEEP | ||
757 | static int sprd_suspend(struct device *dev) | 760 | static int sprd_suspend(struct device *dev) |
758 | { | 761 | { |
759 | struct sprd_uart_port *sup = dev_get_drvdata(dev); | 762 | struct sprd_uart_port *sup = dev_get_drvdata(dev); |
@@ -771,6 +774,7 @@ static int sprd_resume(struct device *dev) | |||
771 | 774 | ||
772 | return 0; | 775 | return 0; |
773 | } | 776 | } |
777 | #endif | ||
774 | 778 | ||
775 | static SIMPLE_DEV_PM_OPS(sprd_pm_ops, sprd_suspend, sprd_resume); | 779 | static SIMPLE_DEV_PM_OPS(sprd_pm_ops, sprd_suspend, sprd_resume); |
776 | 780 | ||
diff --git a/drivers/tty/serial/st-asc.c b/drivers/tty/serial/st-asc.c index 712b03a076b8..d625664ce1b5 100644 --- a/drivers/tty/serial/st-asc.c +++ b/drivers/tty/serial/st-asc.c | |||
@@ -720,7 +720,7 @@ static struct asc_port *asc_of_get_asc_port(struct platform_device *pdev) | |||
720 | } | 720 | } |
721 | 721 | ||
722 | #ifdef CONFIG_OF | 722 | #ifdef CONFIG_OF |
723 | static struct of_device_id asc_match[] = { | 723 | static const struct of_device_id asc_match[] = { |
724 | { .compatible = "st,asc", }, | 724 | { .compatible = "st,asc", }, |
725 | {}, | 725 | {}, |
726 | }; | 726 | }; |
diff --git a/drivers/tty/serial/uartlite.c b/drivers/tty/serial/uartlite.c index 189f52e3111f..708eead850b0 100644 --- a/drivers/tty/serial/uartlite.c +++ b/drivers/tty/serial/uartlite.c | |||
@@ -622,7 +622,7 @@ static int ulite_release(struct device *dev) | |||
622 | 622 | ||
623 | #if defined(CONFIG_OF) | 623 | #if defined(CONFIG_OF) |
624 | /* Match table for of_platform binding */ | 624 | /* Match table for of_platform binding */ |
625 | static struct of_device_id ulite_of_match[] = { | 625 | static const struct of_device_id ulite_of_match[] = { |
626 | { .compatible = "xlnx,opb-uartlite-1.00.b", }, | 626 | { .compatible = "xlnx,opb-uartlite-1.00.b", }, |
627 | { .compatible = "xlnx,xps-uartlite-1.00.a", }, | 627 | { .compatible = "xlnx,xps-uartlite-1.00.a", }, |
628 | {} | 628 | {} |
diff --git a/drivers/tty/serial/ucc_uart.c b/drivers/tty/serial/ucc_uart.c index 14d10fcfd210..7d2532b23969 100644 --- a/drivers/tty/serial/ucc_uart.c +++ b/drivers/tty/serial/ucc_uart.c | |||
@@ -1473,7 +1473,7 @@ static int ucc_uart_remove(struct platform_device *ofdev) | |||
1473 | return 0; | 1473 | return 0; |
1474 | } | 1474 | } |
1475 | 1475 | ||
1476 | static struct of_device_id ucc_uart_match[] = { | 1476 | static const struct of_device_id ucc_uart_match[] = { |
1477 | { | 1477 | { |
1478 | .type = "serial", | 1478 | .type = "serial", |
1479 | .compatible = "ucc_uart", | 1479 | .compatible = "ucc_uart", |
diff --git a/drivers/tty/serial/xilinx_uartps.c b/drivers/tty/serial/xilinx_uartps.c index cff531a51a78..f218ec658f5d 100644 --- a/drivers/tty/serial/xilinx_uartps.c +++ b/drivers/tty/serial/xilinx_uartps.c | |||
@@ -37,10 +37,7 @@ | |||
37 | #define CDNS_UART_MINOR 0 /* works best with devtmpfs */ | 37 | #define CDNS_UART_MINOR 0 /* works best with devtmpfs */ |
38 | #define CDNS_UART_NR_PORTS 2 | 38 | #define CDNS_UART_NR_PORTS 2 |
39 | #define CDNS_UART_FIFO_SIZE 64 /* FIFO size */ | 39 | #define CDNS_UART_FIFO_SIZE 64 /* FIFO size */ |
40 | #define CDNS_UART_REGISTER_SPACE 0xFFF | 40 | #define CDNS_UART_REGISTER_SPACE 0x1000 |
41 | |||
42 | #define cdns_uart_readl(offset) ioread32(port->membase + offset) | ||
43 | #define cdns_uart_writel(val, offset) iowrite32(val, port->membase + offset) | ||
44 | 41 | ||
45 | /* Rx Trigger level */ | 42 | /* Rx Trigger level */ |
46 | static int rx_trigger_level = 56; | 43 | static int rx_trigger_level = 56; |
@@ -195,7 +192,7 @@ static irqreturn_t cdns_uart_isr(int irq, void *dev_id) | |||
195 | /* Read the interrupt status register to determine which | 192 | /* Read the interrupt status register to determine which |
196 | * interrupt(s) is/are active. | 193 | * interrupt(s) is/are active. |
197 | */ | 194 | */ |
198 | isrstatus = cdns_uart_readl(CDNS_UART_ISR_OFFSET); | 195 | isrstatus = readl(port->membase + CDNS_UART_ISR_OFFSET); |
199 | 196 | ||
200 | /* | 197 | /* |
201 | * There is no hardware break detection, so we interpret framing | 198 | * There is no hardware break detection, so we interpret framing |
@@ -203,14 +200,15 @@ static irqreturn_t cdns_uart_isr(int irq, void *dev_id) | |||
203 | * there's another non-zero byte at the end of the sequence. | 200 | * there's another non-zero byte at the end of the sequence. |
204 | */ | 201 | */ |
205 | if (isrstatus & CDNS_UART_IXR_FRAMING) { | 202 | if (isrstatus & CDNS_UART_IXR_FRAMING) { |
206 | while (!(cdns_uart_readl(CDNS_UART_SR_OFFSET) & | 203 | while (!(readl(port->membase + CDNS_UART_SR_OFFSET) & |
207 | CDNS_UART_SR_RXEMPTY)) { | 204 | CDNS_UART_SR_RXEMPTY)) { |
208 | if (!cdns_uart_readl(CDNS_UART_FIFO_OFFSET)) { | 205 | if (!readl(port->membase + CDNS_UART_FIFO_OFFSET)) { |
209 | port->read_status_mask |= CDNS_UART_IXR_BRK; | 206 | port->read_status_mask |= CDNS_UART_IXR_BRK; |
210 | isrstatus &= ~CDNS_UART_IXR_FRAMING; | 207 | isrstatus &= ~CDNS_UART_IXR_FRAMING; |
211 | } | 208 | } |
212 | } | 209 | } |
213 | cdns_uart_writel(CDNS_UART_IXR_FRAMING, CDNS_UART_ISR_OFFSET); | 210 | writel(CDNS_UART_IXR_FRAMING, |
211 | port->membase + CDNS_UART_ISR_OFFSET); | ||
214 | } | 212 | } |
215 | 213 | ||
216 | /* drop byte with parity error if IGNPAR specified */ | 214 | /* drop byte with parity error if IGNPAR specified */ |
@@ -223,9 +221,9 @@ static irqreturn_t cdns_uart_isr(int irq, void *dev_id) | |||
223 | if ((isrstatus & CDNS_UART_IXR_TOUT) || | 221 | if ((isrstatus & CDNS_UART_IXR_TOUT) || |
224 | (isrstatus & CDNS_UART_IXR_RXTRIG)) { | 222 | (isrstatus & CDNS_UART_IXR_RXTRIG)) { |
225 | /* Receive Timeout Interrupt */ | 223 | /* Receive Timeout Interrupt */ |
226 | while ((cdns_uart_readl(CDNS_UART_SR_OFFSET) & | 224 | while (!(readl(port->membase + CDNS_UART_SR_OFFSET) & |
227 | CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) { | 225 | CDNS_UART_SR_RXEMPTY)) { |
228 | data = cdns_uart_readl(CDNS_UART_FIFO_OFFSET); | 226 | data = readl(port->membase + CDNS_UART_FIFO_OFFSET); |
229 | 227 | ||
230 | /* Non-NULL byte after BREAK is garbage (99%) */ | 228 | /* Non-NULL byte after BREAK is garbage (99%) */ |
231 | if (data && (port->read_status_mask & | 229 | if (data && (port->read_status_mask & |
@@ -275,8 +273,8 @@ static irqreturn_t cdns_uart_isr(int irq, void *dev_id) | |||
275 | /* Dispatch an appropriate handler */ | 273 | /* Dispatch an appropriate handler */ |
276 | if ((isrstatus & CDNS_UART_IXR_TXEMPTY) == CDNS_UART_IXR_TXEMPTY) { | 274 | if ((isrstatus & CDNS_UART_IXR_TXEMPTY) == CDNS_UART_IXR_TXEMPTY) { |
277 | if (uart_circ_empty(&port->state->xmit)) { | 275 | if (uart_circ_empty(&port->state->xmit)) { |
278 | cdns_uart_writel(CDNS_UART_IXR_TXEMPTY, | 276 | writel(CDNS_UART_IXR_TXEMPTY, |
279 | CDNS_UART_IDR_OFFSET); | 277 | port->membase + CDNS_UART_IDR_OFFSET); |
280 | } else { | 278 | } else { |
281 | numbytes = port->fifosize; | 279 | numbytes = port->fifosize; |
282 | /* Break if no more data available in the UART buffer */ | 280 | /* Break if no more data available in the UART buffer */ |
@@ -287,9 +285,9 @@ static irqreturn_t cdns_uart_isr(int irq, void *dev_id) | |||
287 | * and write it to the cdns_uart's TX_FIFO | 285 | * and write it to the cdns_uart's TX_FIFO |
288 | * register. | 286 | * register. |
289 | */ | 287 | */ |
290 | cdns_uart_writel( | 288 | writel(port->state->xmit.buf[ |
291 | port->state->xmit.buf[port->state->xmit. | 289 | port->state->xmit.tail], |
292 | tail], CDNS_UART_FIFO_OFFSET); | 290 | port->membase + CDNS_UART_FIFO_OFFSET); |
293 | 291 | ||
294 | port->icount.tx++; | 292 | port->icount.tx++; |
295 | 293 | ||
@@ -307,7 +305,7 @@ static irqreturn_t cdns_uart_isr(int irq, void *dev_id) | |||
307 | } | 305 | } |
308 | } | 306 | } |
309 | 307 | ||
310 | cdns_uart_writel(isrstatus, CDNS_UART_ISR_OFFSET); | 308 | writel(isrstatus, port->membase + CDNS_UART_ISR_OFFSET); |
311 | 309 | ||
312 | /* be sure to release the lock and tty before leaving */ | 310 | /* be sure to release the lock and tty before leaving */ |
313 | spin_unlock_irqrestore(&port->lock, flags); | 311 | spin_unlock_irqrestore(&port->lock, flags); |
@@ -397,14 +395,14 @@ static unsigned int cdns_uart_set_baud_rate(struct uart_port *port, | |||
397 | &div8); | 395 | &div8); |
398 | 396 | ||
399 | /* Write new divisors to hardware */ | 397 | /* Write new divisors to hardware */ |
400 | mreg = cdns_uart_readl(CDNS_UART_MR_OFFSET); | 398 | mreg = readl(port->membase + CDNS_UART_MR_OFFSET); |
401 | if (div8) | 399 | if (div8) |
402 | mreg |= CDNS_UART_MR_CLKSEL; | 400 | mreg |= CDNS_UART_MR_CLKSEL; |
403 | else | 401 | else |
404 | mreg &= ~CDNS_UART_MR_CLKSEL; | 402 | mreg &= ~CDNS_UART_MR_CLKSEL; |
405 | cdns_uart_writel(mreg, CDNS_UART_MR_OFFSET); | 403 | writel(mreg, port->membase + CDNS_UART_MR_OFFSET); |
406 | cdns_uart_writel(cd, CDNS_UART_BAUDGEN_OFFSET); | 404 | writel(cd, port->membase + CDNS_UART_BAUDGEN_OFFSET); |
407 | cdns_uart_writel(bdiv, CDNS_UART_BAUDDIV_OFFSET); | 405 | writel(bdiv, port->membase + CDNS_UART_BAUDDIV_OFFSET); |
408 | cdns_uart->baud = baud; | 406 | cdns_uart->baud = baud; |
409 | 407 | ||
410 | return calc_baud; | 408 | return calc_baud; |
@@ -451,9 +449,9 @@ static int cdns_uart_clk_notifier_cb(struct notifier_block *nb, | |||
451 | spin_lock_irqsave(&cdns_uart->port->lock, flags); | 449 | spin_lock_irqsave(&cdns_uart->port->lock, flags); |
452 | 450 | ||
453 | /* Disable the TX and RX to set baud rate */ | 451 | /* Disable the TX and RX to set baud rate */ |
454 | ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET); | 452 | ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET); |
455 | ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS; | 453 | ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS; |
456 | cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET); | 454 | writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET); |
457 | 455 | ||
458 | spin_unlock_irqrestore(&cdns_uart->port->lock, flags); | 456 | spin_unlock_irqrestore(&cdns_uart->port->lock, flags); |
459 | 457 | ||
@@ -478,11 +476,11 @@ static int cdns_uart_clk_notifier_cb(struct notifier_block *nb, | |||
478 | spin_lock_irqsave(&cdns_uart->port->lock, flags); | 476 | spin_lock_irqsave(&cdns_uart->port->lock, flags); |
479 | 477 | ||
480 | /* Set TX/RX Reset */ | 478 | /* Set TX/RX Reset */ |
481 | ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET); | 479 | ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET); |
482 | ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST; | 480 | ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST; |
483 | cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET); | 481 | writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET); |
484 | 482 | ||
485 | while (cdns_uart_readl(CDNS_UART_CR_OFFSET) & | 483 | while (readl(port->membase + CDNS_UART_CR_OFFSET) & |
486 | (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST)) | 484 | (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST)) |
487 | cpu_relax(); | 485 | cpu_relax(); |
488 | 486 | ||
@@ -491,11 +489,11 @@ static int cdns_uart_clk_notifier_cb(struct notifier_block *nb, | |||
491 | * enable bit and RX enable bit to enable the transmitter and | 489 | * enable bit and RX enable bit to enable the transmitter and |
492 | * receiver. | 490 | * receiver. |
493 | */ | 491 | */ |
494 | cdns_uart_writel(rx_timeout, CDNS_UART_RXTOUT_OFFSET); | 492 | writel(rx_timeout, port->membase + CDNS_UART_RXTOUT_OFFSET); |
495 | ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET); | 493 | ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET); |
496 | ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS); | 494 | ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS); |
497 | ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; | 495 | ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; |
498 | cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET); | 496 | writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET); |
499 | 497 | ||
500 | spin_unlock_irqrestore(&cdns_uart->port->lock, flags); | 498 | spin_unlock_irqrestore(&cdns_uart->port->lock, flags); |
501 | 499 | ||
@@ -517,14 +515,14 @@ static void cdns_uart_start_tx(struct uart_port *port) | |||
517 | if (uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port)) | 515 | if (uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port)) |
518 | return; | 516 | return; |
519 | 517 | ||
520 | status = cdns_uart_readl(CDNS_UART_CR_OFFSET); | 518 | status = readl(port->membase + CDNS_UART_CR_OFFSET); |
521 | /* Set the TX enable bit and clear the TX disable bit to enable the | 519 | /* Set the TX enable bit and clear the TX disable bit to enable the |
522 | * transmitter. | 520 | * transmitter. |
523 | */ | 521 | */ |
524 | cdns_uart_writel((status & ~CDNS_UART_CR_TX_DIS) | CDNS_UART_CR_TX_EN, | 522 | writel((status & ~CDNS_UART_CR_TX_DIS) | CDNS_UART_CR_TX_EN, |
525 | CDNS_UART_CR_OFFSET); | 523 | port->membase + CDNS_UART_CR_OFFSET); |
526 | 524 | ||
527 | while (numbytes-- && ((cdns_uart_readl(CDNS_UART_SR_OFFSET) & | 525 | while (numbytes-- && ((readl(port->membase + CDNS_UART_SR_OFFSET) & |
528 | CDNS_UART_SR_TXFULL)) != CDNS_UART_SR_TXFULL) { | 526 | CDNS_UART_SR_TXFULL)) != CDNS_UART_SR_TXFULL) { |
529 | /* Break if no more data available in the UART buffer */ | 527 | /* Break if no more data available in the UART buffer */ |
530 | if (uart_circ_empty(&port->state->xmit)) | 528 | if (uart_circ_empty(&port->state->xmit)) |
@@ -533,9 +531,8 @@ static void cdns_uart_start_tx(struct uart_port *port) | |||
533 | /* Get the data from the UART circular buffer and | 531 | /* Get the data from the UART circular buffer and |
534 | * write it to the cdns_uart's TX_FIFO register. | 532 | * write it to the cdns_uart's TX_FIFO register. |
535 | */ | 533 | */ |
536 | cdns_uart_writel( | 534 | writel(port->state->xmit.buf[port->state->xmit.tail], |
537 | port->state->xmit.buf[port->state->xmit.tail], | 535 | port->membase + CDNS_UART_FIFO_OFFSET); |
538 | CDNS_UART_FIFO_OFFSET); | ||
539 | port->icount.tx++; | 536 | port->icount.tx++; |
540 | 537 | ||
541 | /* Adjust the tail of the UART buffer and wrap | 538 | /* Adjust the tail of the UART buffer and wrap |
@@ -544,9 +541,9 @@ static void cdns_uart_start_tx(struct uart_port *port) | |||
544 | port->state->xmit.tail = (port->state->xmit.tail + 1) & | 541 | port->state->xmit.tail = (port->state->xmit.tail + 1) & |
545 | (UART_XMIT_SIZE - 1); | 542 | (UART_XMIT_SIZE - 1); |
546 | } | 543 | } |
547 | cdns_uart_writel(CDNS_UART_IXR_TXEMPTY, CDNS_UART_ISR_OFFSET); | 544 | writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR_OFFSET); |
548 | /* Enable the TX Empty interrupt */ | 545 | /* Enable the TX Empty interrupt */ |
549 | cdns_uart_writel(CDNS_UART_IXR_TXEMPTY, CDNS_UART_IER_OFFSET); | 546 | writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IER_OFFSET); |
550 | 547 | ||
551 | if (uart_circ_chars_pending(&port->state->xmit) < WAKEUP_CHARS) | 548 | if (uart_circ_chars_pending(&port->state->xmit) < WAKEUP_CHARS) |
552 | uart_write_wakeup(port); | 549 | uart_write_wakeup(port); |
@@ -560,10 +557,10 @@ static void cdns_uart_stop_tx(struct uart_port *port) | |||
560 | { | 557 | { |
561 | unsigned int regval; | 558 | unsigned int regval; |
562 | 559 | ||
563 | regval = cdns_uart_readl(CDNS_UART_CR_OFFSET); | 560 | regval = readl(port->membase + CDNS_UART_CR_OFFSET); |
564 | regval |= CDNS_UART_CR_TX_DIS; | 561 | regval |= CDNS_UART_CR_TX_DIS; |
565 | /* Disable the transmitter */ | 562 | /* Disable the transmitter */ |
566 | cdns_uart_writel(regval, CDNS_UART_CR_OFFSET); | 563 | writel(regval, port->membase + CDNS_UART_CR_OFFSET); |
567 | } | 564 | } |
568 | 565 | ||
569 | /** | 566 | /** |
@@ -574,10 +571,10 @@ static void cdns_uart_stop_rx(struct uart_port *port) | |||
574 | { | 571 | { |
575 | unsigned int regval; | 572 | unsigned int regval; |
576 | 573 | ||
577 | regval = cdns_uart_readl(CDNS_UART_CR_OFFSET); | 574 | regval = readl(port->membase + CDNS_UART_CR_OFFSET); |
578 | regval |= CDNS_UART_CR_RX_DIS; | 575 | regval |= CDNS_UART_CR_RX_DIS; |
579 | /* Disable the receiver */ | 576 | /* Disable the receiver */ |
580 | cdns_uart_writel(regval, CDNS_UART_CR_OFFSET); | 577 | writel(regval, port->membase + CDNS_UART_CR_OFFSET); |
581 | } | 578 | } |
582 | 579 | ||
583 | /** | 580 | /** |
@@ -590,7 +587,8 @@ static unsigned int cdns_uart_tx_empty(struct uart_port *port) | |||
590 | { | 587 | { |
591 | unsigned int status; | 588 | unsigned int status; |
592 | 589 | ||
593 | status = cdns_uart_readl(CDNS_UART_SR_OFFSET) & CDNS_UART_SR_TXEMPTY; | 590 | status = readl(port->membase + CDNS_UART_SR_OFFSET) & |
591 | CDNS_UART_SR_TXEMPTY; | ||
594 | return status ? TIOCSER_TEMT : 0; | 592 | return status ? TIOCSER_TEMT : 0; |
595 | } | 593 | } |
596 | 594 | ||
@@ -607,15 +605,15 @@ static void cdns_uart_break_ctl(struct uart_port *port, int ctl) | |||
607 | 605 | ||
608 | spin_lock_irqsave(&port->lock, flags); | 606 | spin_lock_irqsave(&port->lock, flags); |
609 | 607 | ||
610 | status = cdns_uart_readl(CDNS_UART_CR_OFFSET); | 608 | status = readl(port->membase + CDNS_UART_CR_OFFSET); |
611 | 609 | ||
612 | if (ctl == -1) | 610 | if (ctl == -1) |
613 | cdns_uart_writel(CDNS_UART_CR_STARTBRK | status, | 611 | writel(CDNS_UART_CR_STARTBRK | status, |
614 | CDNS_UART_CR_OFFSET); | 612 | port->membase + CDNS_UART_CR_OFFSET); |
615 | else { | 613 | else { |
616 | if ((status & CDNS_UART_CR_STOPBRK) == 0) | 614 | if ((status & CDNS_UART_CR_STOPBRK) == 0) |
617 | cdns_uart_writel(CDNS_UART_CR_STOPBRK | status, | 615 | writel(CDNS_UART_CR_STOPBRK | status, |
618 | CDNS_UART_CR_OFFSET); | 616 | port->membase + CDNS_UART_CR_OFFSET); |
619 | } | 617 | } |
620 | spin_unlock_irqrestore(&port->lock, flags); | 618 | spin_unlock_irqrestore(&port->lock, flags); |
621 | } | 619 | } |
@@ -638,17 +636,18 @@ static void cdns_uart_set_termios(struct uart_port *port, | |||
638 | spin_lock_irqsave(&port->lock, flags); | 636 | spin_lock_irqsave(&port->lock, flags); |
639 | 637 | ||
640 | /* Wait for the transmit FIFO to empty before making changes */ | 638 | /* Wait for the transmit FIFO to empty before making changes */ |
641 | if (!(cdns_uart_readl(CDNS_UART_CR_OFFSET) & CDNS_UART_CR_TX_DIS)) { | 639 | if (!(readl(port->membase + CDNS_UART_CR_OFFSET) & |
642 | while (!(cdns_uart_readl(CDNS_UART_SR_OFFSET) & | 640 | CDNS_UART_CR_TX_DIS)) { |
641 | while (!(readl(port->membase + CDNS_UART_SR_OFFSET) & | ||
643 | CDNS_UART_SR_TXEMPTY)) { | 642 | CDNS_UART_SR_TXEMPTY)) { |
644 | cpu_relax(); | 643 | cpu_relax(); |
645 | } | 644 | } |
646 | } | 645 | } |
647 | 646 | ||
648 | /* Disable the TX and RX to set baud rate */ | 647 | /* Disable the TX and RX to set baud rate */ |
649 | ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET); | 648 | ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET); |
650 | ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS; | 649 | ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS; |
651 | cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET); | 650 | writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET); |
652 | 651 | ||
653 | /* | 652 | /* |
654 | * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk | 653 | * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk |
@@ -667,20 +666,20 @@ static void cdns_uart_set_termios(struct uart_port *port, | |||
667 | uart_update_timeout(port, termios->c_cflag, baud); | 666 | uart_update_timeout(port, termios->c_cflag, baud); |
668 | 667 | ||
669 | /* Set TX/RX Reset */ | 668 | /* Set TX/RX Reset */ |
670 | ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET); | 669 | ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET); |
671 | ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST; | 670 | ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST; |
672 | cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET); | 671 | writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET); |
673 | 672 | ||
674 | /* | 673 | /* |
675 | * Clear the RX disable and TX disable bits and then set the TX enable | 674 | * Clear the RX disable and TX disable bits and then set the TX enable |
676 | * bit and RX enable bit to enable the transmitter and receiver. | 675 | * bit and RX enable bit to enable the transmitter and receiver. |
677 | */ | 676 | */ |
678 | ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET); | 677 | ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET); |
679 | ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS); | 678 | ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS); |
680 | ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; | 679 | ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; |
681 | cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET); | 680 | writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET); |
682 | 681 | ||
683 | cdns_uart_writel(rx_timeout, CDNS_UART_RXTOUT_OFFSET); | 682 | writel(rx_timeout, port->membase + CDNS_UART_RXTOUT_OFFSET); |
684 | 683 | ||
685 | port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG | | 684 | port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG | |
686 | CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT; | 685 | CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT; |
@@ -700,7 +699,7 @@ static void cdns_uart_set_termios(struct uart_port *port, | |||
700 | CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY | | 699 | CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY | |
701 | CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN; | 700 | CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN; |
702 | 701 | ||
703 | mode_reg = cdns_uart_readl(CDNS_UART_MR_OFFSET); | 702 | mode_reg = readl(port->membase + CDNS_UART_MR_OFFSET); |
704 | 703 | ||
705 | /* Handling Data Size */ | 704 | /* Handling Data Size */ |
706 | switch (termios->c_cflag & CSIZE) { | 705 | switch (termios->c_cflag & CSIZE) { |
@@ -741,7 +740,7 @@ static void cdns_uart_set_termios(struct uart_port *port, | |||
741 | cval |= CDNS_UART_MR_PARITY_NONE; | 740 | cval |= CDNS_UART_MR_PARITY_NONE; |
742 | } | 741 | } |
743 | cval |= mode_reg & 1; | 742 | cval |= mode_reg & 1; |
744 | cdns_uart_writel(cval, CDNS_UART_MR_OFFSET); | 743 | writel(cval, port->membase + CDNS_UART_MR_OFFSET); |
745 | 744 | ||
746 | spin_unlock_irqrestore(&port->lock, flags); | 745 | spin_unlock_irqrestore(&port->lock, flags); |
747 | } | 746 | } |
@@ -762,52 +761,53 @@ static int cdns_uart_startup(struct uart_port *port) | |||
762 | return retval; | 761 | return retval; |
763 | 762 | ||
764 | /* Disable the TX and RX */ | 763 | /* Disable the TX and RX */ |
765 | cdns_uart_writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS, | 764 | writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS, |
766 | CDNS_UART_CR_OFFSET); | 765 | port->membase + CDNS_UART_CR_OFFSET); |
767 | 766 | ||
768 | /* Set the Control Register with TX/RX Enable, TX/RX Reset, | 767 | /* Set the Control Register with TX/RX Enable, TX/RX Reset, |
769 | * no break chars. | 768 | * no break chars. |
770 | */ | 769 | */ |
771 | cdns_uart_writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST, | 770 | writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST, |
772 | CDNS_UART_CR_OFFSET); | 771 | port->membase + CDNS_UART_CR_OFFSET); |
773 | 772 | ||
774 | status = cdns_uart_readl(CDNS_UART_CR_OFFSET); | 773 | status = readl(port->membase + CDNS_UART_CR_OFFSET); |
775 | 774 | ||
776 | /* Clear the RX disable and TX disable bits and then set the TX enable | 775 | /* Clear the RX disable and TX disable bits and then set the TX enable |
777 | * bit and RX enable bit to enable the transmitter and receiver. | 776 | * bit and RX enable bit to enable the transmitter and receiver. |
778 | */ | 777 | */ |
779 | cdns_uart_writel((status & ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS)) | 778 | writel((status & ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS)) |
780 | | (CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN | | 779 | | (CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN | |
781 | CDNS_UART_CR_STOPBRK), CDNS_UART_CR_OFFSET); | 780 | CDNS_UART_CR_STOPBRK), |
781 | port->membase + CDNS_UART_CR_OFFSET); | ||
782 | 782 | ||
783 | /* Set the Mode Register with normal mode,8 data bits,1 stop bit, | 783 | /* Set the Mode Register with normal mode,8 data bits,1 stop bit, |
784 | * no parity. | 784 | * no parity. |
785 | */ | 785 | */ |
786 | cdns_uart_writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT | 786 | writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT |
787 | | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT, | 787 | | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT, |
788 | CDNS_UART_MR_OFFSET); | 788 | port->membase + CDNS_UART_MR_OFFSET); |
789 | 789 | ||
790 | /* | 790 | /* |
791 | * Set the RX FIFO Trigger level to use most of the FIFO, but it | 791 | * Set the RX FIFO Trigger level to use most of the FIFO, but it |
792 | * can be tuned with a module parameter | 792 | * can be tuned with a module parameter |
793 | */ | 793 | */ |
794 | cdns_uart_writel(rx_trigger_level, CDNS_UART_RXWM_OFFSET); | 794 | writel(rx_trigger_level, port->membase + CDNS_UART_RXWM_OFFSET); |
795 | 795 | ||
796 | /* | 796 | /* |
797 | * Receive Timeout register is enabled but it | 797 | * Receive Timeout register is enabled but it |
798 | * can be tuned with a module parameter | 798 | * can be tuned with a module parameter |
799 | */ | 799 | */ |
800 | cdns_uart_writel(rx_timeout, CDNS_UART_RXTOUT_OFFSET); | 800 | writel(rx_timeout, port->membase + CDNS_UART_RXTOUT_OFFSET); |
801 | 801 | ||
802 | /* Clear out any pending interrupts before enabling them */ | 802 | /* Clear out any pending interrupts before enabling them */ |
803 | cdns_uart_writel(cdns_uart_readl(CDNS_UART_ISR_OFFSET), | 803 | writel(readl(port->membase + CDNS_UART_ISR_OFFSET), |
804 | CDNS_UART_ISR_OFFSET); | 804 | port->membase + CDNS_UART_ISR_OFFSET); |
805 | 805 | ||
806 | /* Set the Interrupt Registers with desired interrupts */ | 806 | /* Set the Interrupt Registers with desired interrupts */ |
807 | cdns_uart_writel(CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_PARITY | | 807 | writel(CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_PARITY | |
808 | CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN | | 808 | CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN | |
809 | CDNS_UART_IXR_RXTRIG | CDNS_UART_IXR_TOUT, | 809 | CDNS_UART_IXR_RXTRIG | CDNS_UART_IXR_TOUT, |
810 | CDNS_UART_IER_OFFSET); | 810 | port->membase + CDNS_UART_IER_OFFSET); |
811 | 811 | ||
812 | return retval; | 812 | return retval; |
813 | } | 813 | } |
@@ -821,12 +821,12 @@ static void cdns_uart_shutdown(struct uart_port *port) | |||
821 | int status; | 821 | int status; |
822 | 822 | ||
823 | /* Disable interrupts */ | 823 | /* Disable interrupts */ |
824 | status = cdns_uart_readl(CDNS_UART_IMR_OFFSET); | 824 | status = readl(port->membase + CDNS_UART_IMR_OFFSET); |
825 | cdns_uart_writel(status, CDNS_UART_IDR_OFFSET); | 825 | writel(status, port->membase + CDNS_UART_IDR_OFFSET); |
826 | 826 | ||
827 | /* Disable the TX and RX */ | 827 | /* Disable the TX and RX */ |
828 | cdns_uart_writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS, | 828 | writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS, |
829 | CDNS_UART_CR_OFFSET); | 829 | port->membase + CDNS_UART_CR_OFFSET); |
830 | free_irq(port->irq, port); | 830 | free_irq(port->irq, port); |
831 | } | 831 | } |
832 | 832 | ||
@@ -928,7 +928,7 @@ static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) | |||
928 | { | 928 | { |
929 | u32 val; | 929 | u32 val; |
930 | 930 | ||
931 | val = cdns_uart_readl(CDNS_UART_MODEMCR_OFFSET); | 931 | val = readl(port->membase + CDNS_UART_MODEMCR_OFFSET); |
932 | 932 | ||
933 | val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR); | 933 | val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR); |
934 | 934 | ||
@@ -937,7 +937,7 @@ static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) | |||
937 | if (mctrl & TIOCM_DTR) | 937 | if (mctrl & TIOCM_DTR) |
938 | val |= CDNS_UART_MODEMCR_DTR; | 938 | val |= CDNS_UART_MODEMCR_DTR; |
939 | 939 | ||
940 | cdns_uart_writel(val, CDNS_UART_MODEMCR_OFFSET); | 940 | writel(val, port->membase + CDNS_UART_MODEMCR_OFFSET); |
941 | } | 941 | } |
942 | 942 | ||
943 | #ifdef CONFIG_CONSOLE_POLL | 943 | #ifdef CONFIG_CONSOLE_POLL |
@@ -947,17 +947,18 @@ static int cdns_uart_poll_get_char(struct uart_port *port) | |||
947 | int c; | 947 | int c; |
948 | 948 | ||
949 | /* Disable all interrupts */ | 949 | /* Disable all interrupts */ |
950 | imr = cdns_uart_readl(CDNS_UART_IMR_OFFSET); | 950 | imr = readl(port->membase + CDNS_UART_IMR_OFFSET); |
951 | cdns_uart_writel(imr, CDNS_UART_IDR_OFFSET); | 951 | writel(imr, port->membase + CDNS_UART_IDR_OFFSET); |
952 | 952 | ||
953 | /* Check if FIFO is empty */ | 953 | /* Check if FIFO is empty */ |
954 | if (cdns_uart_readl(CDNS_UART_SR_OFFSET) & CDNS_UART_SR_RXEMPTY) | 954 | if (readl(port->membase + CDNS_UART_SR_OFFSET) & CDNS_UART_SR_RXEMPTY) |
955 | c = NO_POLL_CHAR; | 955 | c = NO_POLL_CHAR; |
956 | else /* Read a character */ | 956 | else /* Read a character */ |
957 | c = (unsigned char) cdns_uart_readl(CDNS_UART_FIFO_OFFSET); | 957 | c = (unsigned char) readl( |
958 | port->membase + CDNS_UART_FIFO_OFFSET); | ||
958 | 959 | ||
959 | /* Enable interrupts */ | 960 | /* Enable interrupts */ |
960 | cdns_uart_writel(imr, CDNS_UART_IER_OFFSET); | 961 | writel(imr, port->membase + CDNS_UART_IER_OFFSET); |
961 | 962 | ||
962 | return c; | 963 | return c; |
963 | } | 964 | } |
@@ -967,22 +968,24 @@ static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c) | |||
967 | u32 imr; | 968 | u32 imr; |
968 | 969 | ||
969 | /* Disable all interrupts */ | 970 | /* Disable all interrupts */ |
970 | imr = cdns_uart_readl(CDNS_UART_IMR_OFFSET); | 971 | imr = readl(port->membase + CDNS_UART_IMR_OFFSET); |
971 | cdns_uart_writel(imr, CDNS_UART_IDR_OFFSET); | 972 | writel(imr, port->membase + CDNS_UART_IDR_OFFSET); |
972 | 973 | ||
973 | /* Wait until FIFO is empty */ | 974 | /* Wait until FIFO is empty */ |
974 | while (!(cdns_uart_readl(CDNS_UART_SR_OFFSET) & CDNS_UART_SR_TXEMPTY)) | 975 | while (!(readl(port->membase + CDNS_UART_SR_OFFSET) & |
976 | CDNS_UART_SR_TXEMPTY)) | ||
975 | cpu_relax(); | 977 | cpu_relax(); |
976 | 978 | ||
977 | /* Write a character */ | 979 | /* Write a character */ |
978 | cdns_uart_writel(c, CDNS_UART_FIFO_OFFSET); | 980 | writel(c, port->membase + CDNS_UART_FIFO_OFFSET); |
979 | 981 | ||
980 | /* Wait until FIFO is empty */ | 982 | /* Wait until FIFO is empty */ |
981 | while (!(cdns_uart_readl(CDNS_UART_SR_OFFSET) & CDNS_UART_SR_TXEMPTY)) | 983 | while (!(readl(port->membase + CDNS_UART_SR_OFFSET) & |
984 | CDNS_UART_SR_TXEMPTY)) | ||
982 | cpu_relax(); | 985 | cpu_relax(); |
983 | 986 | ||
984 | /* Enable interrupts */ | 987 | /* Enable interrupts */ |
985 | cdns_uart_writel(imr, CDNS_UART_IER_OFFSET); | 988 | writel(imr, port->membase + CDNS_UART_IER_OFFSET); |
986 | 989 | ||
987 | return; | 990 | return; |
988 | } | 991 | } |
@@ -1010,7 +1013,7 @@ static struct uart_ops cdns_uart_ops = { | |||
1010 | #endif | 1013 | #endif |
1011 | }; | 1014 | }; |
1012 | 1015 | ||
1013 | static struct uart_port cdns_uart_port[2]; | 1016 | static struct uart_port cdns_uart_port[CDNS_UART_NR_PORTS]; |
1014 | 1017 | ||
1015 | /** | 1018 | /** |
1016 | * cdns_uart_get_port - Configure the port from platform device resource info | 1019 | * cdns_uart_get_port - Configure the port from platform device resource info |
@@ -1038,7 +1041,6 @@ static struct uart_port *cdns_uart_get_port(int id) | |||
1038 | /* At this point, we've got an empty uart_port struct, initialize it */ | 1041 | /* At this point, we've got an empty uart_port struct, initialize it */ |
1039 | spin_lock_init(&port->lock); | 1042 | spin_lock_init(&port->lock); |
1040 | port->membase = NULL; | 1043 | port->membase = NULL; |
1041 | port->iobase = 1; /* mark port in use */ | ||
1042 | port->irq = 0; | 1044 | port->irq = 0; |
1043 | port->type = PORT_UNKNOWN; | 1045 | port->type = PORT_UNKNOWN; |
1044 | port->iotype = UPIO_MEM32; | 1046 | port->iotype = UPIO_MEM32; |
@@ -1057,8 +1059,8 @@ static struct uart_port *cdns_uart_get_port(int id) | |||
1057 | */ | 1059 | */ |
1058 | static void cdns_uart_console_wait_tx(struct uart_port *port) | 1060 | static void cdns_uart_console_wait_tx(struct uart_port *port) |
1059 | { | 1061 | { |
1060 | while ((cdns_uart_readl(CDNS_UART_SR_OFFSET) & CDNS_UART_SR_TXEMPTY) | 1062 | while (!(readl(port->membase + CDNS_UART_SR_OFFSET) & |
1061 | != CDNS_UART_SR_TXEMPTY) | 1063 | CDNS_UART_SR_TXEMPTY)) |
1062 | barrier(); | 1064 | barrier(); |
1063 | } | 1065 | } |
1064 | 1066 | ||
@@ -1070,7 +1072,7 @@ static void cdns_uart_console_wait_tx(struct uart_port *port) | |||
1070 | static void cdns_uart_console_putchar(struct uart_port *port, int ch) | 1072 | static void cdns_uart_console_putchar(struct uart_port *port, int ch) |
1071 | { | 1073 | { |
1072 | cdns_uart_console_wait_tx(port); | 1074 | cdns_uart_console_wait_tx(port); |
1073 | cdns_uart_writel(ch, CDNS_UART_FIFO_OFFSET); | 1075 | writel(ch, port->membase + CDNS_UART_FIFO_OFFSET); |
1074 | } | 1076 | } |
1075 | 1077 | ||
1076 | static void cdns_early_write(struct console *con, const char *s, unsigned n) | 1078 | static void cdns_early_write(struct console *con, const char *s, unsigned n) |
@@ -1112,24 +1114,24 @@ static void cdns_uart_console_write(struct console *co, const char *s, | |||
1112 | spin_lock_irqsave(&port->lock, flags); | 1114 | spin_lock_irqsave(&port->lock, flags); |
1113 | 1115 | ||
1114 | /* save and disable interrupt */ | 1116 | /* save and disable interrupt */ |
1115 | imr = cdns_uart_readl(CDNS_UART_IMR_OFFSET); | 1117 | imr = readl(port->membase + CDNS_UART_IMR_OFFSET); |
1116 | cdns_uart_writel(imr, CDNS_UART_IDR_OFFSET); | 1118 | writel(imr, port->membase + CDNS_UART_IDR_OFFSET); |
1117 | 1119 | ||
1118 | /* | 1120 | /* |
1119 | * Make sure that the tx part is enabled. Set the TX enable bit and | 1121 | * Make sure that the tx part is enabled. Set the TX enable bit and |
1120 | * clear the TX disable bit to enable the transmitter. | 1122 | * clear the TX disable bit to enable the transmitter. |
1121 | */ | 1123 | */ |
1122 | ctrl = cdns_uart_readl(CDNS_UART_CR_OFFSET); | 1124 | ctrl = readl(port->membase + CDNS_UART_CR_OFFSET); |
1123 | cdns_uart_writel((ctrl & ~CDNS_UART_CR_TX_DIS) | CDNS_UART_CR_TX_EN, | 1125 | writel((ctrl & ~CDNS_UART_CR_TX_DIS) | CDNS_UART_CR_TX_EN, |
1124 | CDNS_UART_CR_OFFSET); | 1126 | port->membase + CDNS_UART_CR_OFFSET); |
1125 | 1127 | ||
1126 | uart_console_write(port, s, count, cdns_uart_console_putchar); | 1128 | uart_console_write(port, s, count, cdns_uart_console_putchar); |
1127 | cdns_uart_console_wait_tx(port); | 1129 | cdns_uart_console_wait_tx(port); |
1128 | 1130 | ||
1129 | cdns_uart_writel(ctrl, CDNS_UART_CR_OFFSET); | 1131 | writel(ctrl, port->membase + CDNS_UART_CR_OFFSET); |
1130 | 1132 | ||
1131 | /* restore interrupt state */ | 1133 | /* restore interrupt state */ |
1132 | cdns_uart_writel(imr, CDNS_UART_IER_OFFSET); | 1134 | writel(imr, port->membase + CDNS_UART_IER_OFFSET); |
1133 | 1135 | ||
1134 | if (locked) | 1136 | if (locked) |
1135 | spin_unlock_irqrestore(&port->lock, flags); | 1137 | spin_unlock_irqrestore(&port->lock, flags); |
@@ -1153,8 +1155,9 @@ static int __init cdns_uart_console_setup(struct console *co, char *options) | |||
1153 | if (co->index < 0 || co->index >= CDNS_UART_NR_PORTS) | 1155 | if (co->index < 0 || co->index >= CDNS_UART_NR_PORTS) |
1154 | return -EINVAL; | 1156 | return -EINVAL; |
1155 | 1157 | ||
1156 | if (!port->mapbase) { | 1158 | if (!port->membase) { |
1157 | pr_debug("console on ttyPS%i not present\n", co->index); | 1159 | pr_debug("console on " CDNS_UART_TTY_NAME "%i not present\n", |
1160 | co->index); | ||
1158 | return -ENODEV; | 1161 | return -ENODEV; |
1159 | } | 1162 | } |
1160 | 1163 | ||
@@ -1240,13 +1243,14 @@ static int cdns_uart_suspend(struct device *device) | |||
1240 | 1243 | ||
1241 | spin_lock_irqsave(&port->lock, flags); | 1244 | spin_lock_irqsave(&port->lock, flags); |
1242 | /* Empty the receive FIFO 1st before making changes */ | 1245 | /* Empty the receive FIFO 1st before making changes */ |
1243 | while (!(cdns_uart_readl(CDNS_UART_SR_OFFSET) & | 1246 | while (!(readl(port->membase + CDNS_UART_SR_OFFSET) & |
1244 | CDNS_UART_SR_RXEMPTY)) | 1247 | CDNS_UART_SR_RXEMPTY)) |
1245 | cdns_uart_readl(CDNS_UART_FIFO_OFFSET); | 1248 | readl(port->membase + CDNS_UART_FIFO_OFFSET); |
1246 | /* set RX trigger level to 1 */ | 1249 | /* set RX trigger level to 1 */ |
1247 | cdns_uart_writel(1, CDNS_UART_RXWM_OFFSET); | 1250 | writel(1, port->membase + CDNS_UART_RXWM_OFFSET); |
1248 | /* disable RX timeout interrups */ | 1251 | /* disable RX timeout interrups */ |
1249 | cdns_uart_writel(CDNS_UART_IXR_TOUT, CDNS_UART_IDR_OFFSET); | 1252 | writel(CDNS_UART_IXR_TOUT, |
1253 | port->membase + CDNS_UART_IDR_OFFSET); | ||
1250 | spin_unlock_irqrestore(&port->lock, flags); | 1254 | spin_unlock_irqrestore(&port->lock, flags); |
1251 | } | 1255 | } |
1252 | 1256 | ||
@@ -1285,28 +1289,30 @@ static int cdns_uart_resume(struct device *device) | |||
1285 | spin_lock_irqsave(&port->lock, flags); | 1289 | spin_lock_irqsave(&port->lock, flags); |
1286 | 1290 | ||
1287 | /* Set TX/RX Reset */ | 1291 | /* Set TX/RX Reset */ |
1288 | ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET); | 1292 | ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET); |
1289 | ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST; | 1293 | ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST; |
1290 | cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET); | 1294 | writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET); |
1291 | while (cdns_uart_readl(CDNS_UART_CR_OFFSET) & | 1295 | while (readl(port->membase + CDNS_UART_CR_OFFSET) & |
1292 | (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST)) | 1296 | (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST)) |
1293 | cpu_relax(); | 1297 | cpu_relax(); |
1294 | 1298 | ||
1295 | /* restore rx timeout value */ | 1299 | /* restore rx timeout value */ |
1296 | cdns_uart_writel(rx_timeout, CDNS_UART_RXTOUT_OFFSET); | 1300 | writel(rx_timeout, port->membase + CDNS_UART_RXTOUT_OFFSET); |
1297 | /* Enable Tx/Rx */ | 1301 | /* Enable Tx/Rx */ |
1298 | ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET); | 1302 | ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET); |
1299 | ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS); | 1303 | ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS); |
1300 | ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; | 1304 | ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; |
1301 | cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET); | 1305 | writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET); |
1302 | 1306 | ||
1303 | spin_unlock_irqrestore(&port->lock, flags); | 1307 | spin_unlock_irqrestore(&port->lock, flags); |
1304 | } else { | 1308 | } else { |
1305 | spin_lock_irqsave(&port->lock, flags); | 1309 | spin_lock_irqsave(&port->lock, flags); |
1306 | /* restore original rx trigger level */ | 1310 | /* restore original rx trigger level */ |
1307 | cdns_uart_writel(rx_trigger_level, CDNS_UART_RXWM_OFFSET); | 1311 | writel(rx_trigger_level, |
1312 | port->membase + CDNS_UART_RXWM_OFFSET); | ||
1308 | /* enable RX timeout interrupt */ | 1313 | /* enable RX timeout interrupt */ |
1309 | cdns_uart_writel(CDNS_UART_IXR_TOUT, CDNS_UART_IER_OFFSET); | 1314 | writel(CDNS_UART_IXR_TOUT, |
1315 | port->membase + CDNS_UART_IER_OFFSET); | ||
1310 | spin_unlock_irqrestore(&port->lock, flags); | 1316 | spin_unlock_irqrestore(&port->lock, flags); |
1311 | } | 1317 | } |
1312 | 1318 | ||
@@ -1458,7 +1464,7 @@ static int cdns_uart_remove(struct platform_device *pdev) | |||
1458 | } | 1464 | } |
1459 | 1465 | ||
1460 | /* Match table for of_platform binding */ | 1466 | /* Match table for of_platform binding */ |
1461 | static struct of_device_id cdns_uart_of_match[] = { | 1467 | static const struct of_device_id cdns_uart_of_match[] = { |
1462 | { .compatible = "xlnx,xuartps", }, | 1468 | { .compatible = "xlnx,xuartps", }, |
1463 | { .compatible = "cdns,uart-r1p8", }, | 1469 | { .compatible = "cdns,uart-r1p8", }, |
1464 | {} | 1470 | {} |
diff --git a/drivers/tty/tty_io.c b/drivers/tty/tty_io.c index 2bb4dfc02873..e5695467598f 100644 --- a/drivers/tty/tty_io.c +++ b/drivers/tty/tty_io.c | |||
@@ -1025,11 +1025,17 @@ void start_tty(struct tty_struct *tty) | |||
1025 | } | 1025 | } |
1026 | EXPORT_SYMBOL(start_tty); | 1026 | EXPORT_SYMBOL(start_tty); |
1027 | 1027 | ||
1028 | /* We limit tty time update visibility to every 8 seconds or so. */ | ||
1029 | static void tty_update_time(struct timespec *time) | 1028 | static void tty_update_time(struct timespec *time) |
1030 | { | 1029 | { |
1031 | unsigned long sec = get_seconds(); | 1030 | unsigned long sec = get_seconds(); |
1032 | if (abs(sec - time->tv_sec) & ~7) | 1031 | |
1032 | /* | ||
1033 | * We only care if the two values differ in anything other than the | ||
1034 | * lower three bits (i.e every 8 seconds). If so, then we can update | ||
1035 | * the time of the tty device, otherwise it could be construded as a | ||
1036 | * security leak to let userspace know the exact timing of the tty. | ||
1037 | */ | ||
1038 | if ((sec ^ time->tv_sec) & ~7) | ||
1033 | time->tv_sec = sec; | 1039 | time->tv_sec = sec; |
1034 | } | 1040 | } |
1035 | 1041 | ||
@@ -3593,6 +3599,13 @@ static ssize_t show_cons_active(struct device *dev, | |||
3593 | } | 3599 | } |
3594 | static DEVICE_ATTR(active, S_IRUGO, show_cons_active, NULL); | 3600 | static DEVICE_ATTR(active, S_IRUGO, show_cons_active, NULL); |
3595 | 3601 | ||
3602 | static struct attribute *cons_dev_attrs[] = { | ||
3603 | &dev_attr_active.attr, | ||
3604 | NULL | ||
3605 | }; | ||
3606 | |||
3607 | ATTRIBUTE_GROUPS(cons_dev); | ||
3608 | |||
3596 | static struct device *consdev; | 3609 | static struct device *consdev; |
3597 | 3610 | ||
3598 | void console_sysfs_notify(void) | 3611 | void console_sysfs_notify(void) |
@@ -3617,12 +3630,11 @@ int __init tty_init(void) | |||
3617 | if (cdev_add(&console_cdev, MKDEV(TTYAUX_MAJOR, 1), 1) || | 3630 | if (cdev_add(&console_cdev, MKDEV(TTYAUX_MAJOR, 1), 1) || |
3618 | register_chrdev_region(MKDEV(TTYAUX_MAJOR, 1), 1, "/dev/console") < 0) | 3631 | register_chrdev_region(MKDEV(TTYAUX_MAJOR, 1), 1, "/dev/console") < 0) |
3619 | panic("Couldn't register /dev/console driver\n"); | 3632 | panic("Couldn't register /dev/console driver\n"); |
3620 | consdev = device_create(tty_class, NULL, MKDEV(TTYAUX_MAJOR, 1), NULL, | 3633 | consdev = device_create_with_groups(tty_class, NULL, |
3621 | "console"); | 3634 | MKDEV(TTYAUX_MAJOR, 1), NULL, |
3635 | cons_dev_groups, "console"); | ||
3622 | if (IS_ERR(consdev)) | 3636 | if (IS_ERR(consdev)) |
3623 | consdev = NULL; | 3637 | consdev = NULL; |
3624 | else | ||
3625 | WARN_ON(device_create_file(consdev, &dev_attr_active) < 0); | ||
3626 | 3638 | ||
3627 | #ifdef CONFIG_VT | 3639 | #ifdef CONFIG_VT |
3628 | vty_init(&console_fops); | 3640 | vty_init(&console_fops); |
diff --git a/drivers/tty/vt/vt.c b/drivers/tty/vt/vt.c index 6e00572cbeb9..4a24eb2b0ede 100644 --- a/drivers/tty/vt/vt.c +++ b/drivers/tty/vt/vt.c | |||
@@ -1237,7 +1237,7 @@ static void default_attr(struct vc_data *vc) | |||
1237 | 1237 | ||
1238 | struct rgb { u8 r; u8 g; u8 b; }; | 1238 | struct rgb { u8 r; u8 g; u8 b; }; |
1239 | 1239 | ||
1240 | struct rgb rgb_from_256(int i) | 1240 | static struct rgb rgb_from_256(int i) |
1241 | { | 1241 | { |
1242 | struct rgb c; | 1242 | struct rgb c; |
1243 | if (i < 8) { /* Standard colours. */ | 1243 | if (i < 8) { /* Standard colours. */ |
@@ -1573,7 +1573,7 @@ static void setterm_command(struct vc_data *vc) | |||
1573 | case 11: /* set bell duration in msec */ | 1573 | case 11: /* set bell duration in msec */ |
1574 | if (vc->vc_npar >= 1) | 1574 | if (vc->vc_npar >= 1) |
1575 | vc->vc_bell_duration = (vc->vc_par[1] < 2000) ? | 1575 | vc->vc_bell_duration = (vc->vc_par[1] < 2000) ? |
1576 | vc->vc_par[1] * HZ / 1000 : 0; | 1576 | msecs_to_jiffies(vc->vc_par[1]) : 0; |
1577 | else | 1577 | else |
1578 | vc->vc_bell_duration = DEFAULT_BELL_DURATION; | 1578 | vc->vc_bell_duration = DEFAULT_BELL_DURATION; |
1579 | break; | 1579 | break; |
@@ -3041,17 +3041,24 @@ static ssize_t show_tty_active(struct device *dev, | |||
3041 | } | 3041 | } |
3042 | static DEVICE_ATTR(active, S_IRUGO, show_tty_active, NULL); | 3042 | static DEVICE_ATTR(active, S_IRUGO, show_tty_active, NULL); |
3043 | 3043 | ||
3044 | static struct attribute *vt_dev_attrs[] = { | ||
3045 | &dev_attr_active.attr, | ||
3046 | NULL | ||
3047 | }; | ||
3048 | |||
3049 | ATTRIBUTE_GROUPS(vt_dev); | ||
3050 | |||
3044 | int __init vty_init(const struct file_operations *console_fops) | 3051 | int __init vty_init(const struct file_operations *console_fops) |
3045 | { | 3052 | { |
3046 | cdev_init(&vc0_cdev, console_fops); | 3053 | cdev_init(&vc0_cdev, console_fops); |
3047 | if (cdev_add(&vc0_cdev, MKDEV(TTY_MAJOR, 0), 1) || | 3054 | if (cdev_add(&vc0_cdev, MKDEV(TTY_MAJOR, 0), 1) || |
3048 | register_chrdev_region(MKDEV(TTY_MAJOR, 0), 1, "/dev/vc/0") < 0) | 3055 | register_chrdev_region(MKDEV(TTY_MAJOR, 0), 1, "/dev/vc/0") < 0) |
3049 | panic("Couldn't register /dev/tty0 driver\n"); | 3056 | panic("Couldn't register /dev/tty0 driver\n"); |
3050 | tty0dev = device_create(tty_class, NULL, MKDEV(TTY_MAJOR, 0), NULL, "tty0"); | 3057 | tty0dev = device_create_with_groups(tty_class, NULL, |
3058 | MKDEV(TTY_MAJOR, 0), NULL, | ||
3059 | vt_dev_groups, "tty0"); | ||
3051 | if (IS_ERR(tty0dev)) | 3060 | if (IS_ERR(tty0dev)) |
3052 | tty0dev = NULL; | 3061 | tty0dev = NULL; |
3053 | else | ||
3054 | WARN_ON(device_create_file(tty0dev, &dev_attr_active) < 0); | ||
3055 | 3062 | ||
3056 | vcs_init(); | 3063 | vcs_init(); |
3057 | 3064 | ||
@@ -3423,42 +3430,26 @@ static ssize_t show_name(struct device *dev, struct device_attribute *attr, | |||
3423 | 3430 | ||
3424 | } | 3431 | } |
3425 | 3432 | ||
3426 | static struct device_attribute device_attrs[] = { | 3433 | static DEVICE_ATTR(bind, S_IRUGO|S_IWUSR, show_bind, store_bind); |
3427 | __ATTR(bind, S_IRUGO|S_IWUSR, show_bind, store_bind), | 3434 | static DEVICE_ATTR(name, S_IRUGO, show_name, NULL); |
3428 | __ATTR(name, S_IRUGO, show_name, NULL), | 3435 | |
3436 | static struct attribute *con_dev_attrs[] = { | ||
3437 | &dev_attr_bind.attr, | ||
3438 | &dev_attr_name.attr, | ||
3439 | NULL | ||
3429 | }; | 3440 | }; |
3430 | 3441 | ||
3442 | ATTRIBUTE_GROUPS(con_dev); | ||
3443 | |||
3431 | static int vtconsole_init_device(struct con_driver *con) | 3444 | static int vtconsole_init_device(struct con_driver *con) |
3432 | { | 3445 | { |
3433 | int i; | ||
3434 | int error = 0; | ||
3435 | |||
3436 | con->flag |= CON_DRIVER_FLAG_ATTR; | 3446 | con->flag |= CON_DRIVER_FLAG_ATTR; |
3437 | dev_set_drvdata(con->dev, con); | 3447 | return 0; |
3438 | for (i = 0; i < ARRAY_SIZE(device_attrs); i++) { | ||
3439 | error = device_create_file(con->dev, &device_attrs[i]); | ||
3440 | if (error) | ||
3441 | break; | ||
3442 | } | ||
3443 | |||
3444 | if (error) { | ||
3445 | while (--i >= 0) | ||
3446 | device_remove_file(con->dev, &device_attrs[i]); | ||
3447 | con->flag &= ~CON_DRIVER_FLAG_ATTR; | ||
3448 | } | ||
3449 | |||
3450 | return error; | ||
3451 | } | 3448 | } |
3452 | 3449 | ||
3453 | static void vtconsole_deinit_device(struct con_driver *con) | 3450 | static void vtconsole_deinit_device(struct con_driver *con) |
3454 | { | 3451 | { |
3455 | int i; | 3452 | con->flag &= ~CON_DRIVER_FLAG_ATTR; |
3456 | |||
3457 | if (con->flag & CON_DRIVER_FLAG_ATTR) { | ||
3458 | for (i = 0; i < ARRAY_SIZE(device_attrs); i++) | ||
3459 | device_remove_file(con->dev, &device_attrs[i]); | ||
3460 | con->flag &= ~CON_DRIVER_FLAG_ATTR; | ||
3461 | } | ||
3462 | } | 3453 | } |
3463 | 3454 | ||
3464 | /** | 3455 | /** |
@@ -3621,11 +3612,11 @@ static int do_register_con_driver(const struct consw *csw, int first, int last) | |||
3621 | if (retval) | 3612 | if (retval) |
3622 | goto err; | 3613 | goto err; |
3623 | 3614 | ||
3624 | con_driver->dev = device_create(vtconsole_class, NULL, | 3615 | con_driver->dev = |
3625 | MKDEV(0, con_driver->node), | 3616 | device_create_with_groups(vtconsole_class, NULL, |
3626 | NULL, "vtcon%i", | 3617 | MKDEV(0, con_driver->node), |
3627 | con_driver->node); | 3618 | con_driver, con_dev_groups, |
3628 | 3619 | "vtcon%i", con_driver->node); | |
3629 | if (IS_ERR(con_driver->dev)) { | 3620 | if (IS_ERR(con_driver->dev)) { |
3630 | printk(KERN_WARNING "Unable to create device for %s; " | 3621 | printk(KERN_WARNING "Unable to create device for %s; " |
3631 | "errno = %ld\n", con_driver->desc, | 3622 | "errno = %ld\n", con_driver->desc, |
@@ -3739,10 +3730,11 @@ static int __init vtconsole_class_init(void) | |||
3739 | struct con_driver *con = ®istered_con_driver[i]; | 3730 | struct con_driver *con = ®istered_con_driver[i]; |
3740 | 3731 | ||
3741 | if (con->con && !con->dev) { | 3732 | if (con->con && !con->dev) { |
3742 | con->dev = device_create(vtconsole_class, NULL, | 3733 | con->dev = |
3743 | MKDEV(0, con->node), | 3734 | device_create_with_groups(vtconsole_class, NULL, |
3744 | NULL, "vtcon%i", | 3735 | MKDEV(0, con->node), |
3745 | con->node); | 3736 | con, con_dev_groups, |
3737 | "vtcon%i", con->node); | ||
3746 | 3738 | ||
3747 | if (IS_ERR(con->dev)) { | 3739 | if (IS_ERR(con->dev)) { |
3748 | printk(KERN_WARNING "Unable to create " | 3740 | printk(KERN_WARNING "Unable to create " |
diff --git a/drivers/tty/vt/vt_ioctl.c b/drivers/tty/vt/vt_ioctl.c index 2bd78e2ac8ec..97d5a74558a3 100644 --- a/drivers/tty/vt/vt_ioctl.c +++ b/drivers/tty/vt/vt_ioctl.c | |||
@@ -388,7 +388,7 @@ int vt_ioctl(struct tty_struct *tty, | |||
388 | * Generate the tone for the appropriate number of ticks. | 388 | * Generate the tone for the appropriate number of ticks. |
389 | * If the time is zero, turn off sound ourselves. | 389 | * If the time is zero, turn off sound ourselves. |
390 | */ | 390 | */ |
391 | ticks = HZ * ((arg >> 16) & 0xffff) / 1000; | 391 | ticks = msecs_to_jiffies((arg >> 16) & 0xffff); |
392 | count = ticks ? (arg & 0xffff) : 0; | 392 | count = ticks ? (arg & 0xffff) : 0; |
393 | if (count) | 393 | if (count) |
394 | count = PIT_TICK_RATE / count; | 394 | count = PIT_TICK_RATE / count; |