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-rw-r--r--drivers/tty/serial/68328serial.c23
-rw-r--r--drivers/tty/serial/8250/8250.c84
-rw-r--r--drivers/tty/serial/8250/8250.h34
-rw-r--r--drivers/tty/serial/8250/8250_acorn.c22
-rw-r--r--drivers/tty/serial/8250/8250_dw.c38
-rw-r--r--drivers/tty/serial/8250/8250_gsc.c26
-rw-r--r--drivers/tty/serial/8250/8250_hp300.c26
-rw-r--r--drivers/tty/serial/8250/8250_pci.c205
-rw-r--r--drivers/tty/serial/8250/8250_pnp.c28
-rw-r--r--drivers/tty/serial/8250/serial_cs.c30
-rw-r--r--drivers/tty/serial/Kconfig50
-rw-r--r--drivers/tty/serial/Makefile4
-rw-r--r--drivers/tty/serial/altera_uart.c6
-rw-r--r--drivers/tty/serial/amba-pl010.c15
-rw-r--r--drivers/tty/serial/amba-pl011.c89
-rw-r--r--drivers/tty/serial/bfin_uart.c2
-rw-r--r--drivers/tty/serial/crisv10.c45
-rw-r--r--drivers/tty/serial/ifx6x60.c4
-rw-r--r--drivers/tty/serial/imx.c5
-rw-r--r--drivers/tty/serial/ioc3_serial.c3
-rw-r--r--drivers/tty/serial/ioc4_serial.c5
-rw-r--r--drivers/tty/serial/jsm/jsm_tty.c8
-rw-r--r--drivers/tty/serial/lpc32xx_hs.c823
-rw-r--r--drivers/tty/serial/m32r_sio.c36
-rw-r--r--drivers/tty/serial/max3100.c12
-rw-r--r--drivers/tty/serial/max3107.c1215
-rw-r--r--drivers/tty/serial/max3107.h441
-rw-r--r--drivers/tty/serial/max310x.c1260
-rw-r--r--drivers/tty/serial/mpc52xx_uart.c8
-rw-r--r--drivers/tty/serial/msm_serial.c2
-rw-r--r--drivers/tty/serial/msm_smd_tty.c8
-rw-r--r--drivers/tty/serial/mxs-auart.c7
-rw-r--r--drivers/tty/serial/of_serial.c13
-rw-r--r--drivers/tty/serial/omap-serial.c860
-rw-r--r--drivers/tty/serial/pch_uart.c4
-rw-r--r--drivers/tty/serial/pxa.c14
-rw-r--r--drivers/tty/serial/samsung.c46
-rw-r--r--drivers/tty/serial/sc26xx.c4
-rw-r--r--drivers/tty/serial/sccnxp.c985
-rw-r--r--drivers/tty/serial/serial_core.c223
-rw-r--r--drivers/tty/serial/sirfsoc_uart.c8
-rw-r--r--drivers/tty/serial/sunsu.c8
42 files changed, 4078 insertions, 2651 deletions
diff --git a/drivers/tty/serial/68328serial.c b/drivers/tty/serial/68328serial.c
index 3ed20e435e59..66c38a3f74ce 100644
--- a/drivers/tty/serial/68328serial.c
+++ b/drivers/tty/serial/68328serial.c
@@ -515,7 +515,7 @@ static void change_speed(struct m68k_serial *info, struct tty_struct *tty)
515 unsigned cflag; 515 unsigned cflag;
516 int i; 516 int i;
517 517
518 cflag = tty->termios->c_cflag; 518 cflag = tty->termios.c_cflag;
519 if (!(port = info->port)) 519 if (!(port = info->port))
520 return; 520 return;
521 521
@@ -617,7 +617,7 @@ static void rs_set_ldisc(struct tty_struct *tty)
617 if (serial_paranoia_check(info, tty->name, "rs_set_ldisc")) 617 if (serial_paranoia_check(info, tty->name, "rs_set_ldisc"))
618 return; 618 return;
619 619
620 info->is_cons = (tty->termios->c_line == N_TTY); 620 info->is_cons = (tty->termios.c_line == N_TTY);
621 621
622 printk("ttyS%d console mode %s\n", info->line, info->is_cons ? "on" : "off"); 622 printk("ttyS%d console mode %s\n", info->line, info->is_cons ? "on" : "off");
623} 623}
@@ -985,7 +985,7 @@ static void rs_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
985 change_speed(info, tty); 985 change_speed(info, tty);
986 986
987 if ((old_termios->c_cflag & CRTSCTS) && 987 if ((old_termios->c_cflag & CRTSCTS) &&
988 !(tty->termios->c_cflag & CRTSCTS)) { 988 !(tty->termios.c_cflag & CRTSCTS)) {
989 tty->hw_stopped = 0; 989 tty->hw_stopped = 0;
990 rs_start(tty); 990 rs_start(tty);
991 } 991 }
@@ -1070,7 +1070,7 @@ static void rs_close(struct tty_struct *tty, struct file * filp)
1070 if (tty->ldisc.close) 1070 if (tty->ldisc.close)
1071 (tty->ldisc.close)(tty); 1071 (tty->ldisc.close)(tty);
1072 tty->ldisc = ldiscs[N_TTY]; 1072 tty->ldisc = ldiscs[N_TTY];
1073 tty->termios->c_line = N_TTY; 1073 tty->termios.c_line = N_TTY;
1074 if (tty->ldisc.open) 1074 if (tty->ldisc.open)
1075 (tty->ldisc.open)(tty); 1075 (tty->ldisc.open)(tty);
1076 } 1076 }
@@ -1189,12 +1189,6 @@ rs68328_init(void)
1189 serial_driver->flags = TTY_DRIVER_REAL_RAW; 1189 serial_driver->flags = TTY_DRIVER_REAL_RAW;
1190 tty_set_operations(serial_driver, &rs_ops); 1190 tty_set_operations(serial_driver, &rs_ops);
1191 1191
1192 if (tty_register_driver(serial_driver)) {
1193 put_tty_driver(serial_driver);
1194 printk(KERN_ERR "Couldn't register serial driver\n");
1195 return -ENOMEM;
1196 }
1197
1198 local_irq_save(flags); 1192 local_irq_save(flags);
1199 1193
1200 for(i=0;i<NR_PORTS;i++) { 1194 for(i=0;i<NR_PORTS;i++) {
@@ -1224,8 +1218,17 @@ rs68328_init(void)
1224 0, 1218 0,
1225 "M68328_UART", info)) 1219 "M68328_UART", info))
1226 panic("Unable to attach 68328 serial interrupt\n"); 1220 panic("Unable to attach 68328 serial interrupt\n");
1221
1222 tty_port_link_device(&info->tport, serial_driver, i);
1227 } 1223 }
1228 local_irq_restore(flags); 1224 local_irq_restore(flags);
1225
1226 if (tty_register_driver(serial_driver)) {
1227 put_tty_driver(serial_driver);
1228 printk(KERN_ERR "Couldn't register serial driver\n");
1229 return -ENOMEM;
1230 }
1231
1229 return 0; 1232 return 0;
1230} 1233}
1231 1234
diff --git a/drivers/tty/serial/8250/8250.c b/drivers/tty/serial/8250/8250.c
index 8123f784bcda..d4e0b07cb130 100644
--- a/drivers/tty/serial/8250/8250.c
+++ b/drivers/tty/serial/8250/8250.c
@@ -2202,6 +2202,7 @@ serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2202 unsigned char cval, fcr = 0; 2202 unsigned char cval, fcr = 0;
2203 unsigned long flags; 2203 unsigned long flags;
2204 unsigned int baud, quot; 2204 unsigned int baud, quot;
2205 int fifo_bug = 0;
2205 2206
2206 switch (termios->c_cflag & CSIZE) { 2207 switch (termios->c_cflag & CSIZE) {
2207 case CS5: 2208 case CS5:
@@ -2221,8 +2222,11 @@ serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2221 2222
2222 if (termios->c_cflag & CSTOPB) 2223 if (termios->c_cflag & CSTOPB)
2223 cval |= UART_LCR_STOP; 2224 cval |= UART_LCR_STOP;
2224 if (termios->c_cflag & PARENB) 2225 if (termios->c_cflag & PARENB) {
2225 cval |= UART_LCR_PARITY; 2226 cval |= UART_LCR_PARITY;
2227 if (up->bugs & UART_BUG_PARITY)
2228 fifo_bug = 1;
2229 }
2226 if (!(termios->c_cflag & PARODD)) 2230 if (!(termios->c_cflag & PARODD))
2227 cval |= UART_LCR_EPAR; 2231 cval |= UART_LCR_EPAR;
2228#ifdef CMSPAR 2232#ifdef CMSPAR
@@ -2246,7 +2250,7 @@ serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2246 2250
2247 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) { 2251 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2248 fcr = uart_config[port->type].fcr; 2252 fcr = uart_config[port->type].fcr;
2249 if (baud < 2400) { 2253 if (baud < 2400 || fifo_bug) {
2250 fcr &= ~UART_FCR_TRIGGER_MASK; 2254 fcr &= ~UART_FCR_TRIGGER_MASK;
2251 fcr |= UART_FCR_TRIGGER_1; 2255 fcr |= UART_FCR_TRIGGER_1;
2252 } 2256 }
@@ -2336,7 +2340,7 @@ serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2336 serial_port_out(port, UART_EFR, efr); 2340 serial_port_out(port, UART_EFR, efr);
2337 } 2341 }
2338 2342
2339#ifdef CONFIG_ARCH_OMAP 2343#ifdef CONFIG_ARCH_OMAP1
2340 /* Workaround to enable 115200 baud on OMAP1510 internal ports */ 2344 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2341 if (cpu_is_omap1510() && is_omap_port(up)) { 2345 if (cpu_is_omap1510() && is_omap_port(up)) {
2342 if (baud == 115200) { 2346 if (baud == 115200) {
@@ -2426,7 +2430,7 @@ static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2426{ 2430{
2427 if (pt->port.iotype == UPIO_AU) 2431 if (pt->port.iotype == UPIO_AU)
2428 return 0x1000; 2432 return 0x1000;
2429#ifdef CONFIG_ARCH_OMAP 2433#ifdef CONFIG_ARCH_OMAP1
2430 if (is_omap_port(pt)) 2434 if (is_omap_port(pt))
2431 return 0x16 << pt->port.regshift; 2435 return 0x16 << pt->port.regshift;
2432#endif 2436#endif
@@ -2979,36 +2983,36 @@ void serial8250_resume_port(int line)
2979static int __devinit serial8250_probe(struct platform_device *dev) 2983static int __devinit serial8250_probe(struct platform_device *dev)
2980{ 2984{
2981 struct plat_serial8250_port *p = dev->dev.platform_data; 2985 struct plat_serial8250_port *p = dev->dev.platform_data;
2982 struct uart_port port; 2986 struct uart_8250_port uart;
2983 int ret, i, irqflag = 0; 2987 int ret, i, irqflag = 0;
2984 2988
2985 memset(&port, 0, sizeof(struct uart_port)); 2989 memset(&uart, 0, sizeof(uart));
2986 2990
2987 if (share_irqs) 2991 if (share_irqs)
2988 irqflag = IRQF_SHARED; 2992 irqflag = IRQF_SHARED;
2989 2993
2990 for (i = 0; p && p->flags != 0; p++, i++) { 2994 for (i = 0; p && p->flags != 0; p++, i++) {
2991 port.iobase = p->iobase; 2995 uart.port.iobase = p->iobase;
2992 port.membase = p->membase; 2996 uart.port.membase = p->membase;
2993 port.irq = p->irq; 2997 uart.port.irq = p->irq;
2994 port.irqflags = p->irqflags; 2998 uart.port.irqflags = p->irqflags;
2995 port.uartclk = p->uartclk; 2999 uart.port.uartclk = p->uartclk;
2996 port.regshift = p->regshift; 3000 uart.port.regshift = p->regshift;
2997 port.iotype = p->iotype; 3001 uart.port.iotype = p->iotype;
2998 port.flags = p->flags; 3002 uart.port.flags = p->flags;
2999 port.mapbase = p->mapbase; 3003 uart.port.mapbase = p->mapbase;
3000 port.hub6 = p->hub6; 3004 uart.port.hub6 = p->hub6;
3001 port.private_data = p->private_data; 3005 uart.port.private_data = p->private_data;
3002 port.type = p->type; 3006 uart.port.type = p->type;
3003 port.serial_in = p->serial_in; 3007 uart.port.serial_in = p->serial_in;
3004 port.serial_out = p->serial_out; 3008 uart.port.serial_out = p->serial_out;
3005 port.handle_irq = p->handle_irq; 3009 uart.port.handle_irq = p->handle_irq;
3006 port.handle_break = p->handle_break; 3010 uart.port.handle_break = p->handle_break;
3007 port.set_termios = p->set_termios; 3011 uart.port.set_termios = p->set_termios;
3008 port.pm = p->pm; 3012 uart.port.pm = p->pm;
3009 port.dev = &dev->dev; 3013 uart.port.dev = &dev->dev;
3010 port.irqflags |= irqflag; 3014 uart.port.irqflags |= irqflag;
3011 ret = serial8250_register_port(&port); 3015 ret = serial8250_register_8250_port(&uart);
3012 if (ret < 0) { 3016 if (ret < 0) {
3013 dev_err(&dev->dev, "unable to register port at index %d " 3017 dev_err(&dev->dev, "unable to register port at index %d "
3014 "(IO%lx MEM%llx IRQ%d): %d\n", i, 3018 "(IO%lx MEM%llx IRQ%d): %d\n", i,
@@ -3081,7 +3085,7 @@ static struct platform_driver serial8250_isa_driver = {
3081static struct platform_device *serial8250_isa_devs; 3085static struct platform_device *serial8250_isa_devs;
3082 3086
3083/* 3087/*
3084 * serial8250_register_port and serial8250_unregister_port allows for 3088 * serial8250_register_8250_port and serial8250_unregister_port allows for
3085 * 16x50 serial ports to be configured at run-time, to support PCMCIA 3089 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3086 * modems and PCI multiport cards. 3090 * modems and PCI multiport cards.
3087 */ 3091 */
@@ -3155,6 +3159,7 @@ int serial8250_register_8250_port(struct uart_8250_port *up)
3155 uart->port.regshift = up->port.regshift; 3159 uart->port.regshift = up->port.regshift;
3156 uart->port.iotype = up->port.iotype; 3160 uart->port.iotype = up->port.iotype;
3157 uart->port.flags = up->port.flags | UPF_BOOT_AUTOCONF; 3161 uart->port.flags = up->port.flags | UPF_BOOT_AUTOCONF;
3162 uart->bugs = up->bugs;
3158 uart->port.mapbase = up->port.mapbase; 3163 uart->port.mapbase = up->port.mapbase;
3159 uart->port.private_data = up->port.private_data; 3164 uart->port.private_data = up->port.private_data;
3160 if (up->port.dev) 3165 if (up->port.dev)
@@ -3198,29 +3203,6 @@ int serial8250_register_8250_port(struct uart_8250_port *up)
3198EXPORT_SYMBOL(serial8250_register_8250_port); 3203EXPORT_SYMBOL(serial8250_register_8250_port);
3199 3204
3200/** 3205/**
3201 * serial8250_register_port - register a serial port
3202 * @port: serial port template
3203 *
3204 * Configure the serial port specified by the request. If the
3205 * port exists and is in use, it is hung up and unregistered
3206 * first.
3207 *
3208 * The port is then probed and if necessary the IRQ is autodetected
3209 * If this fails an error is returned.
3210 *
3211 * On success the port is ready to use and the line number is returned.
3212 */
3213int serial8250_register_port(struct uart_port *port)
3214{
3215 struct uart_8250_port up;
3216
3217 memset(&up, 0, sizeof(up));
3218 memcpy(&up.port, port, sizeof(*port));
3219 return serial8250_register_8250_port(&up);
3220}
3221EXPORT_SYMBOL(serial8250_register_port);
3222
3223/**
3224 * serial8250_unregister_port - remove a 16x50 serial port at runtime 3206 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3225 * @line: serial line number 3207 * @line: serial line number
3226 * 3208 *
diff --git a/drivers/tty/serial/8250/8250.h b/drivers/tty/serial/8250/8250.h
index f9719d167c8d..0c5e908df0b5 100644
--- a/drivers/tty/serial/8250/8250.h
+++ b/drivers/tty/serial/8250/8250.h
@@ -13,36 +13,6 @@
13 13
14#include <linux/serial_8250.h> 14#include <linux/serial_8250.h>
15 15
16struct uart_8250_port {
17 struct uart_port port;
18 struct timer_list timer; /* "no irq" timer */
19 struct list_head list; /* ports on this IRQ */
20 unsigned short capabilities; /* port capabilities */
21 unsigned short bugs; /* port bugs */
22 unsigned int tx_loadsz; /* transmit fifo load size */
23 unsigned char acr;
24 unsigned char ier;
25 unsigned char lcr;
26 unsigned char mcr;
27 unsigned char mcr_mask; /* mask of user bits */
28 unsigned char mcr_force; /* mask of forced bits */
29 unsigned char cur_iotype; /* Running I/O type */
30
31 /*
32 * Some bits in registers are cleared on a read, so they must
33 * be saved whenever the register is read but the bits will not
34 * be immediately processed.
35 */
36#define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS
37 unsigned char lsr_saved_flags;
38#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
39 unsigned char msr_saved_flags;
40
41 /* 8250 specific callbacks */
42 int (*dl_read)(struct uart_8250_port *);
43 void (*dl_write)(struct uart_8250_port *, int);
44};
45
46struct old_serial_port { 16struct old_serial_port {
47 unsigned int uart; 17 unsigned int uart;
48 unsigned int baud_base; 18 unsigned int baud_base;
@@ -56,9 +26,6 @@ struct old_serial_port {
56 unsigned long irqflags; 26 unsigned long irqflags;
57}; 27};
58 28
59/*
60 * This replaces serial_uart_config in include/linux/serial.h
61 */
62struct serial8250_config { 29struct serial8250_config {
63 const char *name; 30 const char *name;
64 unsigned short fifo_size; 31 unsigned short fifo_size;
@@ -78,6 +45,7 @@ struct serial8250_config {
78#define UART_BUG_TXEN (1 << 1) /* UART has buggy TX IIR status */ 45#define UART_BUG_TXEN (1 << 1) /* UART has buggy TX IIR status */
79#define UART_BUG_NOMSR (1 << 2) /* UART has buggy MSR status bits (Au1x00) */ 46#define UART_BUG_NOMSR (1 << 2) /* UART has buggy MSR status bits (Au1x00) */
80#define UART_BUG_THRE (1 << 3) /* UART has buggy THRE reassertion */ 47#define UART_BUG_THRE (1 << 3) /* UART has buggy THRE reassertion */
48#define UART_BUG_PARITY (1 << 4) /* UART mishandles parity if FIFO enabled */
81 49
82#define PROBE_RSA (1 << 0) 50#define PROBE_RSA (1 << 0)
83#define PROBE_ANY (~0) 51#define PROBE_ANY (~0)
diff --git a/drivers/tty/serial/8250/8250_acorn.c b/drivers/tty/serial/8250/8250_acorn.c
index b0ce8c56f1a4..857498312a9a 100644
--- a/drivers/tty/serial/8250/8250_acorn.c
+++ b/drivers/tty/serial/8250/8250_acorn.c
@@ -43,7 +43,7 @@ serial_card_probe(struct expansion_card *ec, const struct ecard_id *id)
43{ 43{
44 struct serial_card_info *info; 44 struct serial_card_info *info;
45 struct serial_card_type *type = id->data; 45 struct serial_card_type *type = id->data;
46 struct uart_port port; 46 struct uart_8250_port uart;
47 unsigned long bus_addr; 47 unsigned long bus_addr;
48 unsigned int i; 48 unsigned int i;
49 49
@@ -62,19 +62,19 @@ serial_card_probe(struct expansion_card *ec, const struct ecard_id *id)
62 62
63 ecard_set_drvdata(ec, info); 63 ecard_set_drvdata(ec, info);
64 64
65 memset(&port, 0, sizeof(struct uart_port)); 65 memset(&uart, 0, sizeof(struct uart_8250_port));
66 port.irq = ec->irq; 66 uart.port.irq = ec->irq;
67 port.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; 67 uart.port.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
68 port.uartclk = type->uartclk; 68 uart.port.uartclk = type->uartclk;
69 port.iotype = UPIO_MEM; 69 uart.port.iotype = UPIO_MEM;
70 port.regshift = 2; 70 uart.port.regshift = 2;
71 port.dev = &ec->dev; 71 uart.port.dev = &ec->dev;
72 72
73 for (i = 0; i < info->num_ports; i ++) { 73 for (i = 0; i < info->num_ports; i ++) {
74 port.membase = info->vaddr + type->offset[i]; 74 uart.port.membase = info->vaddr + type->offset[i];
75 port.mapbase = bus_addr + type->offset[i]; 75 uart.port.mapbase = bus_addr + type->offset[i];
76 76
77 info->ports[i] = serial8250_register_port(&port); 77 info->ports[i] = serial8250_register_8250_port(&uart);
78 } 78 }
79 79
80 return 0; 80 return 0;
diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
index f574eef3075f..c3b2ec0c8c0b 100644
--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty/serial/8250/8250_dw.c
@@ -89,7 +89,7 @@ static int dw8250_handle_irq(struct uart_port *p)
89 89
90static int __devinit dw8250_probe(struct platform_device *pdev) 90static int __devinit dw8250_probe(struct platform_device *pdev)
91{ 91{
92 struct uart_port port = {}; 92 struct uart_8250_port uart = {};
93 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 93 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
94 struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 94 struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
95 struct device_node *np = pdev->dev.of_node; 95 struct device_node *np = pdev->dev.of_node;
@@ -104,28 +104,28 @@ static int __devinit dw8250_probe(struct platform_device *pdev)
104 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); 104 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
105 if (!data) 105 if (!data)
106 return -ENOMEM; 106 return -ENOMEM;
107 port.private_data = data; 107 uart.port.private_data = data;
108 108
109 spin_lock_init(&port.lock); 109 spin_lock_init(&uart.port.lock);
110 port.mapbase = regs->start; 110 uart.port.mapbase = regs->start;
111 port.irq = irq->start; 111 uart.port.irq = irq->start;
112 port.handle_irq = dw8250_handle_irq; 112 uart.port.handle_irq = dw8250_handle_irq;
113 port.type = PORT_8250; 113 uart.port.type = PORT_8250;
114 port.flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_IOREMAP | 114 uart.port.flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_IOREMAP |
115 UPF_FIXED_PORT | UPF_FIXED_TYPE; 115 UPF_FIXED_PORT | UPF_FIXED_TYPE;
116 port.dev = &pdev->dev; 116 uart.port.dev = &pdev->dev;
117 117
118 port.iotype = UPIO_MEM; 118 uart.port.iotype = UPIO_MEM;
119 port.serial_in = dw8250_serial_in; 119 uart.port.serial_in = dw8250_serial_in;
120 port.serial_out = dw8250_serial_out; 120 uart.port.serial_out = dw8250_serial_out;
121 if (!of_property_read_u32(np, "reg-io-width", &val)) { 121 if (!of_property_read_u32(np, "reg-io-width", &val)) {
122 switch (val) { 122 switch (val) {
123 case 1: 123 case 1:
124 break; 124 break;
125 case 4: 125 case 4:
126 port.iotype = UPIO_MEM32; 126 uart.port.iotype = UPIO_MEM32;
127 port.serial_in = dw8250_serial_in32; 127 uart.port.serial_in = dw8250_serial_in32;
128 port.serial_out = dw8250_serial_out32; 128 uart.port.serial_out = dw8250_serial_out32;
129 break; 129 break;
130 default: 130 default:
131 dev_err(&pdev->dev, "unsupported reg-io-width (%u)\n", 131 dev_err(&pdev->dev, "unsupported reg-io-width (%u)\n",
@@ -135,15 +135,15 @@ static int __devinit dw8250_probe(struct platform_device *pdev)
135 } 135 }
136 136
137 if (!of_property_read_u32(np, "reg-shift", &val)) 137 if (!of_property_read_u32(np, "reg-shift", &val))
138 port.regshift = val; 138 uart.port.regshift = val;
139 139
140 if (of_property_read_u32(np, "clock-frequency", &val)) { 140 if (of_property_read_u32(np, "clock-frequency", &val)) {
141 dev_err(&pdev->dev, "no clock-frequency property set\n"); 141 dev_err(&pdev->dev, "no clock-frequency property set\n");
142 return -EINVAL; 142 return -EINVAL;
143 } 143 }
144 port.uartclk = val; 144 uart.port.uartclk = val;
145 145
146 data->line = serial8250_register_port(&port); 146 data->line = serial8250_register_8250_port(&uart);
147 if (data->line < 0) 147 if (data->line < 0)
148 return data->line; 148 return data->line;
149 149
diff --git a/drivers/tty/serial/8250/8250_gsc.c b/drivers/tty/serial/8250/8250_gsc.c
index d8c0ffbfa6e3..097dff9c08ad 100644
--- a/drivers/tty/serial/8250/8250_gsc.c
+++ b/drivers/tty/serial/8250/8250_gsc.c
@@ -26,7 +26,7 @@
26 26
27static int __init serial_init_chip(struct parisc_device *dev) 27static int __init serial_init_chip(struct parisc_device *dev)
28{ 28{
29 struct uart_port port; 29 struct uart_8250_port uart;
30 unsigned long address; 30 unsigned long address;
31 int err; 31 int err;
32 32
@@ -48,21 +48,21 @@ static int __init serial_init_chip(struct parisc_device *dev)
48 if (dev->id.sversion != 0x8d) 48 if (dev->id.sversion != 0x8d)
49 address += 0x800; 49 address += 0x800;
50 50
51 memset(&port, 0, sizeof(port)); 51 memset(&uart, 0, sizeof(uart));
52 port.iotype = UPIO_MEM; 52 uart.port.iotype = UPIO_MEM;
53 /* 7.272727MHz on Lasi. Assumed the same for Dino, Wax and Timi. */ 53 /* 7.272727MHz on Lasi. Assumed the same for Dino, Wax and Timi. */
54 port.uartclk = 7272727; 54 uart.port.uartclk = 7272727;
55 port.mapbase = address; 55 uart.port.mapbase = address;
56 port.membase = ioremap_nocache(address, 16); 56 uart.port.membase = ioremap_nocache(address, 16);
57 port.irq = dev->irq; 57 uart.port.irq = dev->irq;
58 port.flags = UPF_BOOT_AUTOCONF; 58 uart.port.flags = UPF_BOOT_AUTOCONF;
59 port.dev = &dev->dev; 59 uart.port.dev = &dev->dev;
60 60
61 err = serial8250_register_port(&port); 61 err = serial8250_register_8250_port(&uart);
62 if (err < 0) { 62 if (err < 0) {
63 printk(KERN_WARNING 63 printk(KERN_WARNING
64 "serial8250_register_port returned error %d\n", err); 64 "serial8250_register_8250_port returned error %d\n", err);
65 iounmap(port.membase); 65 iounmap(uart.port.membase);
66 return err; 66 return err;
67 } 67 }
68 68
diff --git a/drivers/tty/serial/8250/8250_hp300.c b/drivers/tty/serial/8250/8250_hp300.c
index c13438c93012..8f1dd2cc00a8 100644
--- a/drivers/tty/serial/8250/8250_hp300.c
+++ b/drivers/tty/serial/8250/8250_hp300.c
@@ -171,7 +171,7 @@ static int __devinit hpdca_init_one(struct dio_dev *d,
171 return 0; 171 return 0;
172 } 172 }
173#endif 173#endif
174 memset(&port, 0, sizeof(struct uart_port)); 174 memset(&uart, 0, sizeof(uart));
175 175
176 /* Memory mapped I/O */ 176 /* Memory mapped I/O */
177 port.iotype = UPIO_MEM; 177 port.iotype = UPIO_MEM;
@@ -182,7 +182,7 @@ static int __devinit hpdca_init_one(struct dio_dev *d,
182 port.membase = (char *)(port.mapbase + DIO_VIRADDRBASE); 182 port.membase = (char *)(port.mapbase + DIO_VIRADDRBASE);
183 port.regshift = 1; 183 port.regshift = 1;
184 port.dev = &d->dev; 184 port.dev = &d->dev;
185 line = serial8250_register_port(&port); 185 line = serial8250_register_8250_port(&uart);
186 186
187 if (line < 0) { 187 if (line < 0) {
188 printk(KERN_NOTICE "8250_hp300: register_serial() DCA scode %d" 188 printk(KERN_NOTICE "8250_hp300: register_serial() DCA scode %d"
@@ -210,7 +210,7 @@ static int __init hp300_8250_init(void)
210#ifdef CONFIG_HPAPCI 210#ifdef CONFIG_HPAPCI
211 int line; 211 int line;
212 unsigned long base; 212 unsigned long base;
213 struct uart_port uport; 213 struct uart_8250_port uart;
214 struct hp300_port *port; 214 struct hp300_port *port;
215 int i; 215 int i;
216#endif 216#endif
@@ -248,26 +248,26 @@ static int __init hp300_8250_init(void)
248 if (!port) 248 if (!port)
249 return -ENOMEM; 249 return -ENOMEM;
250 250
251 memset(&uport, 0, sizeof(struct uart_port)); 251 memset(&uart, 0, sizeof(uart));
252 252
253 base = (FRODO_BASE + FRODO_APCI_OFFSET(i)); 253 base = (FRODO_BASE + FRODO_APCI_OFFSET(i));
254 254
255 /* Memory mapped I/O */ 255 /* Memory mapped I/O */
256 uport.iotype = UPIO_MEM; 256 uart.port.iotype = UPIO_MEM;
257 uport.flags = UPF_SKIP_TEST | UPF_SHARE_IRQ \ 257 uart.port.flags = UPF_SKIP_TEST | UPF_SHARE_IRQ \
258 | UPF_BOOT_AUTOCONF; 258 | UPF_BOOT_AUTOCONF;
259 /* XXX - no interrupt support yet */ 259 /* XXX - no interrupt support yet */
260 uport.irq = 0; 260 uart.port.irq = 0;
261 uport.uartclk = HPAPCI_BAUD_BASE * 16; 261 uart.port.uartclk = HPAPCI_BAUD_BASE * 16;
262 uport.mapbase = base; 262 uart.port.mapbase = base;
263 uport.membase = (char *)(base + DIO_VIRADDRBASE); 263 uart.port.membase = (char *)(base + DIO_VIRADDRBASE);
264 uport.regshift = 2; 264 uart.port.regshift = 2;
265 265
266 line = serial8250_register_port(&uport); 266 line = serial8250_register_8250_port(&uart);
267 267
268 if (line < 0) { 268 if (line < 0) {
269 printk(KERN_NOTICE "8250_hp300: register_serial() APCI" 269 printk(KERN_NOTICE "8250_hp300: register_serial() APCI"
270 " %d irq %d failed\n", i, uport.irq); 270 " %d irq %d failed\n", i, uart.port.irq);
271 kfree(port); 271 kfree(port);
272 continue; 272 continue;
273 } 273 }
diff --git a/drivers/tty/serial/8250/8250_pci.c b/drivers/tty/serial/8250/8250_pci.c
index 28e7c7cce893..fdab80a4e063 100644
--- a/drivers/tty/serial/8250/8250_pci.c
+++ b/drivers/tty/serial/8250/8250_pci.c
@@ -44,7 +44,7 @@ struct pci_serial_quirk {
44 int (*init)(struct pci_dev *dev); 44 int (*init)(struct pci_dev *dev);
45 int (*setup)(struct serial_private *, 45 int (*setup)(struct serial_private *,
46 const struct pciserial_board *, 46 const struct pciserial_board *,
47 struct uart_port *, int); 47 struct uart_8250_port *, int);
48 void (*exit)(struct pci_dev *dev); 48 void (*exit)(struct pci_dev *dev);
49}; 49};
50 50
@@ -59,7 +59,7 @@ struct serial_private {
59}; 59};
60 60
61static int pci_default_setup(struct serial_private*, 61static int pci_default_setup(struct serial_private*,
62 const struct pciserial_board*, struct uart_port*, int); 62 const struct pciserial_board*, struct uart_8250_port *, int);
63 63
64static void moan_device(const char *str, struct pci_dev *dev) 64static void moan_device(const char *str, struct pci_dev *dev)
65{ 65{
@@ -74,7 +74,7 @@ static void moan_device(const char *str, struct pci_dev *dev)
74} 74}
75 75
76static int 76static int
77setup_port(struct serial_private *priv, struct uart_port *port, 77setup_port(struct serial_private *priv, struct uart_8250_port *port,
78 int bar, int offset, int regshift) 78 int bar, int offset, int regshift)
79{ 79{
80 struct pci_dev *dev = priv->dev; 80 struct pci_dev *dev = priv->dev;
@@ -93,17 +93,17 @@ setup_port(struct serial_private *priv, struct uart_port *port,
93 if (!priv->remapped_bar[bar]) 93 if (!priv->remapped_bar[bar])
94 return -ENOMEM; 94 return -ENOMEM;
95 95
96 port->iotype = UPIO_MEM; 96 port->port.iotype = UPIO_MEM;
97 port->iobase = 0; 97 port->port.iobase = 0;
98 port->mapbase = base + offset; 98 port->port.mapbase = base + offset;
99 port->membase = priv->remapped_bar[bar] + offset; 99 port->port.membase = priv->remapped_bar[bar] + offset;
100 port->regshift = regshift; 100 port->port.regshift = regshift;
101 } else { 101 } else {
102 port->iotype = UPIO_PORT; 102 port->port.iotype = UPIO_PORT;
103 port->iobase = base + offset; 103 port->port.iobase = base + offset;
104 port->mapbase = 0; 104 port->port.mapbase = 0;
105 port->membase = NULL; 105 port->port.membase = NULL;
106 port->regshift = 0; 106 port->port.regshift = 0;
107 } 107 }
108 return 0; 108 return 0;
109} 109}
@@ -113,7 +113,7 @@ setup_port(struct serial_private *priv, struct uart_port *port,
113 */ 113 */
114static int addidata_apci7800_setup(struct serial_private *priv, 114static int addidata_apci7800_setup(struct serial_private *priv,
115 const struct pciserial_board *board, 115 const struct pciserial_board *board,
116 struct uart_port *port, int idx) 116 struct uart_8250_port *port, int idx)
117{ 117{
118 unsigned int bar = 0, offset = board->first_offset; 118 unsigned int bar = 0, offset = board->first_offset;
119 bar = FL_GET_BASE(board->flags); 119 bar = FL_GET_BASE(board->flags);
@@ -140,7 +140,7 @@ static int addidata_apci7800_setup(struct serial_private *priv,
140 */ 140 */
141static int 141static int
142afavlab_setup(struct serial_private *priv, const struct pciserial_board *board, 142afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
143 struct uart_port *port, int idx) 143 struct uart_8250_port *port, int idx)
144{ 144{
145 unsigned int bar, offset = board->first_offset; 145 unsigned int bar, offset = board->first_offset;
146 146
@@ -195,7 +195,7 @@ static int pci_hp_diva_init(struct pci_dev *dev)
195static int 195static int
196pci_hp_diva_setup(struct serial_private *priv, 196pci_hp_diva_setup(struct serial_private *priv,
197 const struct pciserial_board *board, 197 const struct pciserial_board *board,
198 struct uart_port *port, int idx) 198 struct uart_8250_port *port, int idx)
199{ 199{
200 unsigned int offset = board->first_offset; 200 unsigned int offset = board->first_offset;
201 unsigned int bar = FL_GET_BASE(board->flags); 201 unsigned int bar = FL_GET_BASE(board->flags);
@@ -370,7 +370,7 @@ static void __devexit pci_ni8430_exit(struct pci_dev *dev)
370/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */ 370/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
371static int 371static int
372sbs_setup(struct serial_private *priv, const struct pciserial_board *board, 372sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
373 struct uart_port *port, int idx) 373 struct uart_8250_port *port, int idx)
374{ 374{
375 unsigned int bar, offset = board->first_offset; 375 unsigned int bar, offset = board->first_offset;
376 376
@@ -525,7 +525,7 @@ static int pci_siig_init(struct pci_dev *dev)
525 525
526static int pci_siig_setup(struct serial_private *priv, 526static int pci_siig_setup(struct serial_private *priv,
527 const struct pciserial_board *board, 527 const struct pciserial_board *board,
528 struct uart_port *port, int idx) 528 struct uart_8250_port *port, int idx)
529{ 529{
530 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0; 530 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
531 531
@@ -619,7 +619,7 @@ static int pci_timedia_init(struct pci_dev *dev)
619static int 619static int
620pci_timedia_setup(struct serial_private *priv, 620pci_timedia_setup(struct serial_private *priv,
621 const struct pciserial_board *board, 621 const struct pciserial_board *board,
622 struct uart_port *port, int idx) 622 struct uart_8250_port *port, int idx)
623{ 623{
624 unsigned int bar = 0, offset = board->first_offset; 624 unsigned int bar = 0, offset = board->first_offset;
625 625
@@ -653,7 +653,7 @@ pci_timedia_setup(struct serial_private *priv,
653static int 653static int
654titan_400l_800l_setup(struct serial_private *priv, 654titan_400l_800l_setup(struct serial_private *priv,
655 const struct pciserial_board *board, 655 const struct pciserial_board *board,
656 struct uart_port *port, int idx) 656 struct uart_8250_port *port, int idx)
657{ 657{
658 unsigned int bar, offset = board->first_offset; 658 unsigned int bar, offset = board->first_offset;
659 659
@@ -754,7 +754,7 @@ static int pci_ni8430_init(struct pci_dev *dev)
754static int 754static int
755pci_ni8430_setup(struct serial_private *priv, 755pci_ni8430_setup(struct serial_private *priv,
756 const struct pciserial_board *board, 756 const struct pciserial_board *board,
757 struct uart_port *port, int idx) 757 struct uart_8250_port *port, int idx)
758{ 758{
759 void __iomem *p; 759 void __iomem *p;
760 unsigned long base, len; 760 unsigned long base, len;
@@ -781,7 +781,7 @@ pci_ni8430_setup(struct serial_private *priv,
781 781
782static int pci_netmos_9900_setup(struct serial_private *priv, 782static int pci_netmos_9900_setup(struct serial_private *priv,
783 const struct pciserial_board *board, 783 const struct pciserial_board *board,
784 struct uart_port *port, int idx) 784 struct uart_8250_port *port, int idx)
785{ 785{
786 unsigned int bar; 786 unsigned int bar;
787 787
@@ -1032,10 +1032,17 @@ static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1032 return number_uarts; 1032 return number_uarts;
1033} 1033}
1034 1034
1035static int 1035static int pci_asix_setup(struct serial_private *priv,
1036pci_default_setup(struct serial_private *priv,
1037 const struct pciserial_board *board, 1036 const struct pciserial_board *board,
1038 struct uart_port *port, int idx) 1037 struct uart_8250_port *port, int idx)
1038{
1039 port->bugs |= UART_BUG_PARITY;
1040 return pci_default_setup(priv, board, port, idx);
1041}
1042
1043static int pci_default_setup(struct serial_private *priv,
1044 const struct pciserial_board *board,
1045 struct uart_8250_port *port, int idx)
1039{ 1046{
1040 unsigned int bar, offset = board->first_offset, maxnr; 1047 unsigned int bar, offset = board->first_offset, maxnr;
1041 1048
@@ -1057,15 +1064,15 @@ pci_default_setup(struct serial_private *priv,
1057static int 1064static int
1058ce4100_serial_setup(struct serial_private *priv, 1065ce4100_serial_setup(struct serial_private *priv,
1059 const struct pciserial_board *board, 1066 const struct pciserial_board *board,
1060 struct uart_port *port, int idx) 1067 struct uart_8250_port *port, int idx)
1061{ 1068{
1062 int ret; 1069 int ret;
1063 1070
1064 ret = setup_port(priv, port, 0, 0, board->reg_shift); 1071 ret = setup_port(priv, port, 0, 0, board->reg_shift);
1065 port->iotype = UPIO_MEM32; 1072 port->port.iotype = UPIO_MEM32;
1066 port->type = PORT_XSCALE; 1073 port->port.type = PORT_XSCALE;
1067 port->flags = (port->flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1074 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1068 port->regshift = 2; 1075 port->port.regshift = 2;
1069 1076
1070 return ret; 1077 return ret;
1071} 1078}
@@ -1073,16 +1080,16 @@ ce4100_serial_setup(struct serial_private *priv,
1073static int 1080static int
1074pci_omegapci_setup(struct serial_private *priv, 1081pci_omegapci_setup(struct serial_private *priv,
1075 const struct pciserial_board *board, 1082 const struct pciserial_board *board,
1076 struct uart_port *port, int idx) 1083 struct uart_8250_port *port, int idx)
1077{ 1084{
1078 return setup_port(priv, port, 2, idx * 8, 0); 1085 return setup_port(priv, port, 2, idx * 8, 0);
1079} 1086}
1080 1087
1081static int skip_tx_en_setup(struct serial_private *priv, 1088static int skip_tx_en_setup(struct serial_private *priv,
1082 const struct pciserial_board *board, 1089 const struct pciserial_board *board,
1083 struct uart_port *port, int idx) 1090 struct uart_8250_port *port, int idx)
1084{ 1091{
1085 port->flags |= UPF_NO_TXEN_TEST; 1092 port->port.flags |= UPF_NO_TXEN_TEST;
1086 printk(KERN_DEBUG "serial8250: skipping TxEn test for device " 1093 printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
1087 "[%04x:%04x] subsystem [%04x:%04x]\n", 1094 "[%04x:%04x] subsystem [%04x:%04x]\n",
1088 priv->dev->vendor, 1095 priv->dev->vendor,
@@ -1131,11 +1138,11 @@ static unsigned int kt_serial_in(struct uart_port *p, int offset)
1131 1138
1132static int kt_serial_setup(struct serial_private *priv, 1139static int kt_serial_setup(struct serial_private *priv,
1133 const struct pciserial_board *board, 1140 const struct pciserial_board *board,
1134 struct uart_port *port, int idx) 1141 struct uart_8250_port *port, int idx)
1135{ 1142{
1136 port->flags |= UPF_BUG_THRE; 1143 port->port.flags |= UPF_BUG_THRE;
1137 port->serial_in = kt_serial_in; 1144 port->port.serial_in = kt_serial_in;
1138 port->handle_break = kt_handle_break; 1145 port->port.handle_break = kt_handle_break;
1139 return skip_tx_en_setup(priv, board, port, idx); 1146 return skip_tx_en_setup(priv, board, port, idx);
1140} 1147}
1141 1148
@@ -1151,9 +1158,19 @@ static int pci_eg20t_init(struct pci_dev *dev)
1151static int 1158static int
1152pci_xr17c154_setup(struct serial_private *priv, 1159pci_xr17c154_setup(struct serial_private *priv,
1153 const struct pciserial_board *board, 1160 const struct pciserial_board *board,
1154 struct uart_port *port, int idx) 1161 struct uart_8250_port *port, int idx)
1162{
1163 port->port.flags |= UPF_EXAR_EFR;
1164 return pci_default_setup(priv, board, port, idx);
1165}
1166
1167static int
1168pci_wch_ch353_setup(struct serial_private *priv,
1169 const struct pciserial_board *board,
1170 struct uart_8250_port *port, int idx)
1155{ 1171{
1156 port->flags |= UPF_EXAR_EFR; 1172 port->port.flags |= UPF_FIXED_TYPE;
1173 port->port.type = PORT_16550A;
1157 return pci_default_setup(priv, board, port, idx); 1174 return pci_default_setup(priv, board, port, idx);
1158} 1175}
1159 1176
@@ -1187,6 +1204,13 @@ pci_xr17c154_setup(struct serial_private *priv,
1187#define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6 1204#define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
1188#define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001 1205#define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
1189#define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d 1206#define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1207#define PCI_VENDOR_ID_WCH 0x4348
1208#define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
1209#define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
1210#define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
1211#define PCI_VENDOR_ID_AGESTAR 0x5372
1212#define PCI_DEVICE_ID_AGESTAR_9375 0x6872
1213#define PCI_VENDOR_ID_ASIX 0x9710
1190 1214
1191/* Unknown vendors/cards - this should not be in linux/pci_ids.h */ 1215/* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1192#define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584 1216#define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
@@ -1726,7 +1750,41 @@ static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1726 .subvendor = PCI_ANY_ID, 1750 .subvendor = PCI_ANY_ID,
1727 .subdevice = PCI_ANY_ID, 1751 .subdevice = PCI_ANY_ID,
1728 .setup = pci_omegapci_setup, 1752 .setup = pci_omegapci_setup,
1729 }, 1753 },
1754 /* WCH CH353 2S1P card (16550 clone) */
1755 {
1756 .vendor = PCI_VENDOR_ID_WCH,
1757 .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
1758 .subvendor = PCI_ANY_ID,
1759 .subdevice = PCI_ANY_ID,
1760 .setup = pci_wch_ch353_setup,
1761 },
1762 /* WCH CH353 4S card (16550 clone) */
1763 {
1764 .vendor = PCI_VENDOR_ID_WCH,
1765 .device = PCI_DEVICE_ID_WCH_CH353_4S,
1766 .subvendor = PCI_ANY_ID,
1767 .subdevice = PCI_ANY_ID,
1768 .setup = pci_wch_ch353_setup,
1769 },
1770 /* WCH CH353 2S1PF card (16550 clone) */
1771 {
1772 .vendor = PCI_VENDOR_ID_WCH,
1773 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
1774 .subvendor = PCI_ANY_ID,
1775 .subdevice = PCI_ANY_ID,
1776 .setup = pci_wch_ch353_setup,
1777 },
1778 /*
1779 * ASIX devices with FIFO bug
1780 */
1781 {
1782 .vendor = PCI_VENDOR_ID_ASIX,
1783 .device = PCI_ANY_ID,
1784 .subvendor = PCI_ANY_ID,
1785 .subdevice = PCI_ANY_ID,
1786 .setup = pci_asix_setup,
1787 },
1730 /* 1788 /*
1731 * Default "match everything" terminator entry 1789 * Default "match everything" terminator entry
1732 */ 1790 */
@@ -1887,7 +1945,6 @@ enum pci_board_num_t {
1887 pbn_panacom, 1945 pbn_panacom,
1888 pbn_panacom2, 1946 pbn_panacom2,
1889 pbn_panacom4, 1947 pbn_panacom4,
1890 pbn_exsys_4055,
1891 pbn_plx_romulus, 1948 pbn_plx_romulus,
1892 pbn_oxsemi, 1949 pbn_oxsemi,
1893 pbn_oxsemi_1_4000000, 1950 pbn_oxsemi_1_4000000,
@@ -2393,13 +2450,6 @@ static struct pciserial_board pci_boards[] __devinitdata = {
2393 .reg_shift = 7, 2450 .reg_shift = 7,
2394 }, 2451 },
2395 2452
2396 [pbn_exsys_4055] = {
2397 .flags = FL_BASE2,
2398 .num_ports = 4,
2399 .base_baud = 115200,
2400 .uart_offset = 8,
2401 },
2402
2403 /* I think this entry is broken - the first_offset looks wrong --rmk */ 2453 /* I think this entry is broken - the first_offset looks wrong --rmk */
2404 [pbn_plx_romulus] = { 2454 [pbn_plx_romulus] = {
2405 .flags = FL_BASE2, 2455 .flags = FL_BASE2,
@@ -2624,10 +2674,14 @@ static struct pciserial_board pci_boards[] __devinitdata = {
2624 }, 2674 },
2625}; 2675};
2626 2676
2627static const struct pci_device_id softmodem_blacklist[] = { 2677static const struct pci_device_id blacklist[] = {
2678 /* softmodems */
2628 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */ 2679 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
2629 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */ 2680 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
2630 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */ 2681 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
2682
2683 /* multi-io cards handled by parport_serial */
2684 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
2631}; 2685};
2632 2686
2633/* 2687/*
@@ -2638,7 +2692,7 @@ static const struct pci_device_id softmodem_blacklist[] = {
2638static int __devinit 2692static int __devinit
2639serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board) 2693serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
2640{ 2694{
2641 const struct pci_device_id *blacklist; 2695 const struct pci_device_id *bldev;
2642 int num_iomem, num_port, first_port = -1, i; 2696 int num_iomem, num_port, first_port = -1, i;
2643 2697
2644 /* 2698 /*
@@ -2655,13 +2709,13 @@ serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
2655 2709
2656 /* 2710 /*
2657 * Do not access blacklisted devices that are known not to 2711 * Do not access blacklisted devices that are known not to
2658 * feature serial ports. 2712 * feature serial ports or are handled by other modules.
2659 */ 2713 */
2660 for (blacklist = softmodem_blacklist; 2714 for (bldev = blacklist;
2661 blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist); 2715 bldev < blacklist + ARRAY_SIZE(blacklist);
2662 blacklist++) { 2716 bldev++) {
2663 if (dev->vendor == blacklist->vendor && 2717 if (dev->vendor == bldev->vendor &&
2664 dev->device == blacklist->device) 2718 dev->device == bldev->device)
2665 return -ENODEV; 2719 return -ENODEV;
2666 } 2720 }
2667 2721
@@ -2728,7 +2782,7 @@ serial_pci_matches(const struct pciserial_board *board,
2728struct serial_private * 2782struct serial_private *
2729pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board) 2783pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
2730{ 2784{
2731 struct uart_port serial_port; 2785 struct uart_8250_port uart;
2732 struct serial_private *priv; 2786 struct serial_private *priv;
2733 struct pci_serial_quirk *quirk; 2787 struct pci_serial_quirk *quirk;
2734 int rc, nr_ports, i; 2788 int rc, nr_ports, i;
@@ -2768,22 +2822,22 @@ pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
2768 priv->dev = dev; 2822 priv->dev = dev;
2769 priv->quirk = quirk; 2823 priv->quirk = quirk;
2770 2824
2771 memset(&serial_port, 0, sizeof(struct uart_port)); 2825 memset(&uart, 0, sizeof(uart));
2772 serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; 2826 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
2773 serial_port.uartclk = board->base_baud * 16; 2827 uart.port.uartclk = board->base_baud * 16;
2774 serial_port.irq = get_pci_irq(dev, board); 2828 uart.port.irq = get_pci_irq(dev, board);
2775 serial_port.dev = &dev->dev; 2829 uart.port.dev = &dev->dev;
2776 2830
2777 for (i = 0; i < nr_ports; i++) { 2831 for (i = 0; i < nr_ports; i++) {
2778 if (quirk->setup(priv, board, &serial_port, i)) 2832 if (quirk->setup(priv, board, &uart, i))
2779 break; 2833 break;
2780 2834
2781#ifdef SERIAL_DEBUG_PCI 2835#ifdef SERIAL_DEBUG_PCI
2782 printk(KERN_DEBUG "Setup PCI port: port %lx, irq %d, type %d\n", 2836 printk(KERN_DEBUG "Setup PCI port: port %lx, irq %d, type %d\n",
2783 serial_port.iobase, serial_port.irq, serial_port.iotype); 2837 uart.port.iobase, uart.port.irq, uart.port.iotype);
2784#endif 2838#endif
2785 2839
2786 priv->line[i] = serial8250_register_port(&serial_port); 2840 priv->line[i] = serial8250_register_8250_port(&uart);
2787 if (priv->line[i] < 0) { 2841 if (priv->line[i] < 0) {
2788 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]); 2842 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
2789 break; 2843 break;
@@ -3193,7 +3247,7 @@ static struct pci_device_id serial_pci_tbl[] = {
3193 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 3247 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3194 PCI_SUBVENDOR_ID_EXSYS, 3248 PCI_SUBVENDOR_ID_EXSYS,
3195 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0, 3249 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
3196 pbn_exsys_4055 }, 3250 pbn_b2_4_115200 },
3197 /* 3251 /*
3198 * Megawolf Romulus PCI Serial Card, from Mike Hudson 3252 * Megawolf Romulus PCI Serial Card, from Mike Hudson
3199 * (Exoray@isys.ca) 3253 * (Exoray@isys.ca)
@@ -4179,6 +4233,25 @@ static struct pci_device_id serial_pci_tbl[] = {
4179 pbn_omegapci }, 4233 pbn_omegapci },
4180 4234
4181 /* 4235 /*
4236 * AgeStar as-prs2-009
4237 */
4238 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
4239 PCI_ANY_ID, PCI_ANY_ID,
4240 0, 0, pbn_b0_bt_2_115200 },
4241
4242 /*
4243 * WCH CH353 series devices: The 2S1P is handled by parport_serial
4244 * so not listed here.
4245 */
4246 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
4247 PCI_ANY_ID, PCI_ANY_ID,
4248 0, 0, pbn_b0_bt_4_115200 },
4249
4250 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
4251 PCI_ANY_ID, PCI_ANY_ID,
4252 0, 0, pbn_b0_bt_2_115200 },
4253
4254 /*
4182 * These entries match devices with class COMMUNICATION_SERIAL, 4255 * These entries match devices with class COMMUNICATION_SERIAL,
4183 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL 4256 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
4184 */ 4257 */
diff --git a/drivers/tty/serial/8250/8250_pnp.c b/drivers/tty/serial/8250/8250_pnp.c
index a2f236510ff1..fde5aa60d51e 100644
--- a/drivers/tty/serial/8250/8250_pnp.c
+++ b/drivers/tty/serial/8250/8250_pnp.c
@@ -424,7 +424,7 @@ static int __devinit serial_pnp_guess_board(struct pnp_dev *dev, int *flags)
424static int __devinit 424static int __devinit
425serial_pnp_probe(struct pnp_dev *dev, const struct pnp_device_id *dev_id) 425serial_pnp_probe(struct pnp_dev *dev, const struct pnp_device_id *dev_id)
426{ 426{
427 struct uart_port port; 427 struct uart_8250_port uart;
428 int ret, line, flags = dev_id->driver_data; 428 int ret, line, flags = dev_id->driver_data;
429 429
430 if (flags & UNKNOWN_DEV) { 430 if (flags & UNKNOWN_DEV) {
@@ -433,32 +433,32 @@ serial_pnp_probe(struct pnp_dev *dev, const struct pnp_device_id *dev_id)
433 return ret; 433 return ret;
434 } 434 }
435 435
436 memset(&port, 0, sizeof(struct uart_port)); 436 memset(&uart, 0, sizeof(uart));
437 if (pnp_irq_valid(dev, 0)) 437 if (pnp_irq_valid(dev, 0))
438 port.irq = pnp_irq(dev, 0); 438 uart.port.irq = pnp_irq(dev, 0);
439 if (pnp_port_valid(dev, 0)) { 439 if (pnp_port_valid(dev, 0)) {
440 port.iobase = pnp_port_start(dev, 0); 440 uart.port.iobase = pnp_port_start(dev, 0);
441 port.iotype = UPIO_PORT; 441 uart.port.iotype = UPIO_PORT;
442 } else if (pnp_mem_valid(dev, 0)) { 442 } else if (pnp_mem_valid(dev, 0)) {
443 port.mapbase = pnp_mem_start(dev, 0); 443 uart.port.mapbase = pnp_mem_start(dev, 0);
444 port.iotype = UPIO_MEM; 444 uart.port.iotype = UPIO_MEM;
445 port.flags = UPF_IOREMAP; 445 uart.port.flags = UPF_IOREMAP;
446 } else 446 } else
447 return -ENODEV; 447 return -ENODEV;
448 448
449#ifdef SERIAL_DEBUG_PNP 449#ifdef SERIAL_DEBUG_PNP
450 printk(KERN_DEBUG 450 printk(KERN_DEBUG
451 "Setup PNP port: port %x, mem 0x%lx, irq %d, type %d\n", 451 "Setup PNP port: port %x, mem 0x%lx, irq %d, type %d\n",
452 port.iobase, port.mapbase, port.irq, port.iotype); 452 uart.port.iobase, uart.port.mapbase, uart.port.irq, uart.port.iotype);
453#endif 453#endif
454 454
455 port.flags |= UPF_SKIP_TEST | UPF_BOOT_AUTOCONF; 455 uart.port.flags |= UPF_SKIP_TEST | UPF_BOOT_AUTOCONF;
456 if (pnp_irq_flags(dev, 0) & IORESOURCE_IRQ_SHAREABLE) 456 if (pnp_irq_flags(dev, 0) & IORESOURCE_IRQ_SHAREABLE)
457 port.flags |= UPF_SHARE_IRQ; 457 uart.port.flags |= UPF_SHARE_IRQ;
458 port.uartclk = 1843200; 458 uart.port.uartclk = 1843200;
459 port.dev = &dev->dev; 459 uart.port.dev = &dev->dev;
460 460
461 line = serial8250_register_port(&port); 461 line = serial8250_register_8250_port(&uart);
462 if (line < 0) 462 if (line < 0)
463 return -ENODEV; 463 return -ENODEV;
464 464
diff --git a/drivers/tty/serial/8250/serial_cs.c b/drivers/tty/serial/8250/serial_cs.c
index 29b695d041ec..b7d48b346393 100644
--- a/drivers/tty/serial/8250/serial_cs.c
+++ b/drivers/tty/serial/8250/serial_cs.c
@@ -73,7 +73,7 @@ struct serial_quirk {
73 unsigned int prodid; 73 unsigned int prodid;
74 int multi; /* 1 = multifunction, > 1 = # ports */ 74 int multi; /* 1 = multifunction, > 1 = # ports */
75 void (*config)(struct pcmcia_device *); 75 void (*config)(struct pcmcia_device *);
76 void (*setup)(struct pcmcia_device *, struct uart_port *); 76 void (*setup)(struct pcmcia_device *, struct uart_8250_port *);
77 void (*wakeup)(struct pcmcia_device *); 77 void (*wakeup)(struct pcmcia_device *);
78 int (*post)(struct pcmcia_device *); 78 int (*post)(struct pcmcia_device *);
79}; 79};
@@ -105,9 +105,9 @@ struct serial_cfg_mem {
105 * Elan VPU16551 UART with 14.7456MHz oscillator 105 * Elan VPU16551 UART with 14.7456MHz oscillator
106 * manfid 0x015D, 0x4C45 106 * manfid 0x015D, 0x4C45
107 */ 107 */
108static void quirk_setup_brainboxes_0104(struct pcmcia_device *link, struct uart_port *port) 108static void quirk_setup_brainboxes_0104(struct pcmcia_device *link, struct uart_8250_port *uart)
109{ 109{
110 port->uartclk = 14745600; 110 uart->port.uartclk = 14745600;
111} 111}
112 112
113static int quirk_post_ibm(struct pcmcia_device *link) 113static int quirk_post_ibm(struct pcmcia_device *link)
@@ -343,25 +343,25 @@ static void serial_detach(struct pcmcia_device *link)
343static int setup_serial(struct pcmcia_device *handle, struct serial_info * info, 343static int setup_serial(struct pcmcia_device *handle, struct serial_info * info,
344 unsigned int iobase, int irq) 344 unsigned int iobase, int irq)
345{ 345{
346 struct uart_port port; 346 struct uart_8250_port uart;
347 int line; 347 int line;
348 348
349 memset(&port, 0, sizeof (struct uart_port)); 349 memset(&uart, 0, sizeof(uart));
350 port.iobase = iobase; 350 uart.port.iobase = iobase;
351 port.irq = irq; 351 uart.port.irq = irq;
352 port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ; 352 uart.port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ;
353 port.uartclk = 1843200; 353 uart.port.uartclk = 1843200;
354 port.dev = &handle->dev; 354 uart.port.dev = &handle->dev;
355 if (buggy_uart) 355 if (buggy_uart)
356 port.flags |= UPF_BUGGY_UART; 356 uart.port.flags |= UPF_BUGGY_UART;
357 357
358 if (info->quirk && info->quirk->setup) 358 if (info->quirk && info->quirk->setup)
359 info->quirk->setup(handle, &port); 359 info->quirk->setup(handle, &uart);
360 360
361 line = serial8250_register_port(&port); 361 line = serial8250_register_8250_port(&uart);
362 if (line < 0) { 362 if (line < 0) {
363 printk(KERN_NOTICE "serial_cs: serial8250_register_port() at " 363 pr_err("serial_cs: serial8250_register_8250_port() at 0x%04lx, irq %d failed\n",
364 "0x%04lx, irq %d failed\n", (u_long)iobase, irq); 364 (unsigned long)iobase, irq);
365 return -EINVAL; 365 return -EINVAL;
366 } 366 }
367 367
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 4720b4ba096a..26907cf25744 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -257,12 +257,19 @@ config SERIAL_MAX3100
257 help 257 help
258 MAX3100 chip support 258 MAX3100 chip support
259 259
260config SERIAL_MAX3107 260config SERIAL_MAX310X
261 tristate "MAX3107 support" 261 bool "MAX310X support"
262 depends on SPI 262 depends on SPI
263 select SERIAL_CORE 263 select SERIAL_CORE
264 select REGMAP_SPI if SPI
265 default n
264 help 266 help
265 MAX3107 chip support 267 This selects support for an advanced UART from Maxim (Dallas).
268 Supported ICs are MAX3107, MAX3108.
269 Each IC contains 128 words each of receive and transmit FIFO
270 that can be controlled through I2C or high-speed SPI.
271
272 Say Y here if you want to support this ICs.
266 273
267config SERIAL_DZ 274config SERIAL_DZ
268 bool "DECstation DZ serial driver" 275 bool "DECstation DZ serial driver"
@@ -704,6 +711,25 @@ config SERIAL_PNX8XXX_CONSOLE
704 If you have a MIPS-based Philips SoC such as PNX8550 or PNX8330 711 If you have a MIPS-based Philips SoC such as PNX8550 or PNX8330
705 and you want to use serial console, say Y. Otherwise, say N. 712 and you want to use serial console, say Y. Otherwise, say N.
706 713
714config SERIAL_HS_LPC32XX
715 tristate "LPC32XX high speed serial port support"
716 depends on ARCH_LPC32XX && OF
717 select SERIAL_CORE
718 help
719 Support for the LPC32XX high speed serial ports (up to 900kbps).
720 Those are UARTs completely different from the Standard UARTs on the
721 LPC32XX SoC.
722 Choose M or Y here to build this driver.
723
724config SERIAL_HS_LPC32XX_CONSOLE
725 bool "Enable LPC32XX high speed UART serial console"
726 depends on SERIAL_HS_LPC32XX
727 select SERIAL_CORE_CONSOLE
728 help
729 If you would like to be able to use one of the high speed serial
730 ports on the LPC32XX as the console, you can do so by answering
731 Y to this option.
732
707config SERIAL_CORE 733config SERIAL_CORE
708 tristate 734 tristate
709 735
@@ -1104,6 +1130,24 @@ config SERIAL_SC26XX_CONSOLE
1104 help 1130 help
1105 Support for Console on SC2681/SC2692 serial ports. 1131 Support for Console on SC2681/SC2692 serial ports.
1106 1132
1133config SERIAL_SCCNXP
1134 bool "SCCNXP serial port support"
1135 depends on !SERIAL_SC26XX
1136 select SERIAL_CORE
1137 default n
1138 help
1139 This selects support for an advanced UART from NXP (Philips).
1140 Supported ICs are SCC2681, SCC2691, SCC2692, SC28L91, SC28L92,
1141 SC28L202, SCC68681 and SCC68692.
1142 Positioned as a replacement for the driver SC26XX.
1143
1144config SERIAL_SCCNXP_CONSOLE
1145 bool "Console on SCCNXP serial port"
1146 depends on SERIAL_SCCNXP
1147 select SERIAL_CORE_CONSOLE
1148 help
1149 Support for console on SCCNXP serial ports.
1150
1107config SERIAL_BFIN_SPORT 1151config SERIAL_BFIN_SPORT
1108 tristate "Blackfin SPORT emulate UART" 1152 tristate "Blackfin SPORT emulate UART"
1109 depends on BLACKFIN 1153 depends on BLACKFIN
diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
index 7257c5d898ae..ce88667cfd17 100644
--- a/drivers/tty/serial/Makefile
+++ b/drivers/tty/serial/Makefile
@@ -28,12 +28,13 @@ obj-$(CONFIG_SERIAL_BFIN) += bfin_uart.o
28obj-$(CONFIG_SERIAL_BFIN_SPORT) += bfin_sport_uart.o 28obj-$(CONFIG_SERIAL_BFIN_SPORT) += bfin_sport_uart.o
29obj-$(CONFIG_SERIAL_SAMSUNG) += samsung.o 29obj-$(CONFIG_SERIAL_SAMSUNG) += samsung.o
30obj-$(CONFIG_SERIAL_MAX3100) += max3100.o 30obj-$(CONFIG_SERIAL_MAX3100) += max3100.o
31obj-$(CONFIG_SERIAL_MAX3107) += max3107.o 31obj-$(CONFIG_SERIAL_MAX310X) += max310x.o
32obj-$(CONFIG_SERIAL_IP22_ZILOG) += ip22zilog.o 32obj-$(CONFIG_SERIAL_IP22_ZILOG) += ip22zilog.o
33obj-$(CONFIG_SERIAL_MUX) += mux.o 33obj-$(CONFIG_SERIAL_MUX) += mux.o
34obj-$(CONFIG_SERIAL_68328) += 68328serial.o 34obj-$(CONFIG_SERIAL_68328) += 68328serial.o
35obj-$(CONFIG_SERIAL_MCF) += mcf.o 35obj-$(CONFIG_SERIAL_MCF) += mcf.o
36obj-$(CONFIG_SERIAL_PMACZILOG) += pmac_zilog.o 36obj-$(CONFIG_SERIAL_PMACZILOG) += pmac_zilog.o
37obj-$(CONFIG_SERIAL_HS_LPC32XX) += lpc32xx_hs.o
37obj-$(CONFIG_SERIAL_DZ) += dz.o 38obj-$(CONFIG_SERIAL_DZ) += dz.o
38obj-$(CONFIG_SERIAL_ZS) += zs.o 39obj-$(CONFIG_SERIAL_ZS) += zs.o
39obj-$(CONFIG_SERIAL_SH_SCI) += sh-sci.o 40obj-$(CONFIG_SERIAL_SH_SCI) += sh-sci.o
@@ -47,6 +48,7 @@ obj-$(CONFIG_SERIAL_MPSC) += mpsc.o
47obj-$(CONFIG_SERIAL_SB1250_DUART) += sb1250-duart.o 48obj-$(CONFIG_SERIAL_SB1250_DUART) += sb1250-duart.o
48obj-$(CONFIG_ETRAX_SERIAL) += crisv10.o 49obj-$(CONFIG_ETRAX_SERIAL) += crisv10.o
49obj-$(CONFIG_SERIAL_SC26XX) += sc26xx.o 50obj-$(CONFIG_SERIAL_SC26XX) += sc26xx.o
51obj-$(CONFIG_SERIAL_SCCNXP) += sccnxp.o
50obj-$(CONFIG_SERIAL_JSM) += jsm/ 52obj-$(CONFIG_SERIAL_JSM) += jsm/
51obj-$(CONFIG_SERIAL_TXX9) += serial_txx9.o 53obj-$(CONFIG_SERIAL_TXX9) += serial_txx9.o
52obj-$(CONFIG_SERIAL_VR41XX) += vr41xx_siu.o 54obj-$(CONFIG_SERIAL_VR41XX) += vr41xx_siu.o
diff --git a/drivers/tty/serial/altera_uart.c b/drivers/tty/serial/altera_uart.c
index 1f0330915d5a..15d80b9fb303 100644
--- a/drivers/tty/serial/altera_uart.c
+++ b/drivers/tty/serial/altera_uart.c
@@ -591,7 +591,7 @@ static int __devinit altera_uart_probe(struct platform_device *pdev)
591 port->ops = &altera_uart_ops; 591 port->ops = &altera_uart_ops;
592 port->flags = UPF_BOOT_AUTOCONF; 592 port->flags = UPF_BOOT_AUTOCONF;
593 593
594 dev_set_drvdata(&pdev->dev, port); 594 platform_set_drvdata(pdev, port);
595 595
596 uart_add_one_port(&altera_uart_driver, port); 596 uart_add_one_port(&altera_uart_driver, port);
597 597
@@ -600,11 +600,11 @@ static int __devinit altera_uart_probe(struct platform_device *pdev)
600 600
601static int __devexit altera_uart_remove(struct platform_device *pdev) 601static int __devexit altera_uart_remove(struct platform_device *pdev)
602{ 602{
603 struct uart_port *port = dev_get_drvdata(&pdev->dev); 603 struct uart_port *port = platform_get_drvdata(pdev);
604 604
605 if (port) { 605 if (port) {
606 uart_remove_one_port(&altera_uart_driver, port); 606 uart_remove_one_port(&altera_uart_driver, port);
607 dev_set_drvdata(&pdev->dev, NULL); 607 platform_set_drvdata(pdev, NULL);
608 port->mapbase = 0; 608 port->mapbase = 0;
609 } 609 }
610 610
diff --git a/drivers/tty/serial/amba-pl010.c b/drivers/tty/serial/amba-pl010.c
index 0d91a540bf11..22317dd16474 100644
--- a/drivers/tty/serial/amba-pl010.c
+++ b/drivers/tty/serial/amba-pl010.c
@@ -312,16 +312,12 @@ static int pl010_startup(struct uart_port *port)
312 struct uart_amba_port *uap = (struct uart_amba_port *)port; 312 struct uart_amba_port *uap = (struct uart_amba_port *)port;
313 int retval; 313 int retval;
314 314
315 retval = clk_prepare(uap->clk);
316 if (retval)
317 goto out;
318
319 /* 315 /*
320 * Try to enable the clock producer. 316 * Try to enable the clock producer.
321 */ 317 */
322 retval = clk_enable(uap->clk); 318 retval = clk_prepare_enable(uap->clk);
323 if (retval) 319 if (retval)
324 goto clk_unprep; 320 goto out;
325 321
326 uap->port.uartclk = clk_get_rate(uap->clk); 322 uap->port.uartclk = clk_get_rate(uap->clk);
327 323
@@ -346,9 +342,7 @@ static int pl010_startup(struct uart_port *port)
346 return 0; 342 return 0;
347 343
348 clk_dis: 344 clk_dis:
349 clk_disable(uap->clk); 345 clk_disable_unprepare(uap->clk);
350 clk_unprep:
351 clk_unprepare(uap->clk);
352 out: 346 out:
353 return retval; 347 return retval;
354} 348}
@@ -375,8 +369,7 @@ static void pl010_shutdown(struct uart_port *port)
375 /* 369 /*
376 * Shut down the clock producer 370 * Shut down the clock producer
377 */ 371 */
378 clk_disable(uap->clk); 372 clk_disable_unprepare(uap->clk);
379 clk_unprepare(uap->clk);
380} 373}
381 374
382static void 375static void
diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
index d3553b5d3fca..cede93876649 100644
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -52,6 +52,8 @@
52#include <linux/scatterlist.h> 52#include <linux/scatterlist.h>
53#include <linux/delay.h> 53#include <linux/delay.h>
54#include <linux/types.h> 54#include <linux/types.h>
55#include <linux/of.h>
56#include <linux/of_device.h>
55#include <linux/pinctrl/consumer.h> 57#include <linux/pinctrl/consumer.h>
56#include <linux/sizes.h> 58#include <linux/sizes.h>
57 59
@@ -75,7 +77,6 @@ struct vendor_data {
75 unsigned int lcrh_tx; 77 unsigned int lcrh_tx;
76 unsigned int lcrh_rx; 78 unsigned int lcrh_rx;
77 bool oversampling; 79 bool oversampling;
78 bool interrupt_may_hang; /* vendor-specific */
79 bool dma_threshold; 80 bool dma_threshold;
80 bool cts_event_workaround; 81 bool cts_event_workaround;
81}; 82};
@@ -96,7 +97,6 @@ static struct vendor_data vendor_st = {
96 .lcrh_tx = ST_UART011_LCRH_TX, 97 .lcrh_tx = ST_UART011_LCRH_TX,
97 .lcrh_rx = ST_UART011_LCRH_RX, 98 .lcrh_rx = ST_UART011_LCRH_RX,
98 .oversampling = true, 99 .oversampling = true,
99 .interrupt_may_hang = true,
100 .dma_threshold = true, 100 .dma_threshold = true,
101 .cts_event_workaround = true, 101 .cts_event_workaround = true,
102}; 102};
@@ -147,7 +147,6 @@ struct uart_amba_port {
147 unsigned int old_cr; /* state during shutdown */ 147 unsigned int old_cr; /* state during shutdown */
148 bool autorts; 148 bool autorts;
149 char type[12]; 149 char type[12];
150 bool interrupt_may_hang; /* vendor-specific */
151#ifdef CONFIG_DMA_ENGINE 150#ifdef CONFIG_DMA_ENGINE
152 /* DMA stuff */ 151 /* DMA stuff */
153 bool using_tx_dma; 152 bool using_tx_dma;
@@ -1215,14 +1214,14 @@ static irqreturn_t pl011_int(int irq, void *dev_id)
1215 return IRQ_RETVAL(handled); 1214 return IRQ_RETVAL(handled);
1216} 1215}
1217 1216
1218static unsigned int pl01x_tx_empty(struct uart_port *port) 1217static unsigned int pl011_tx_empty(struct uart_port *port)
1219{ 1218{
1220 struct uart_amba_port *uap = (struct uart_amba_port *)port; 1219 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1221 unsigned int status = readw(uap->port.membase + UART01x_FR); 1220 unsigned int status = readw(uap->port.membase + UART01x_FR);
1222 return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT; 1221 return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT;
1223} 1222}
1224 1223
1225static unsigned int pl01x_get_mctrl(struct uart_port *port) 1224static unsigned int pl011_get_mctrl(struct uart_port *port)
1226{ 1225{
1227 struct uart_amba_port *uap = (struct uart_amba_port *)port; 1226 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1228 unsigned int result = 0; 1227 unsigned int result = 0;
@@ -1285,7 +1284,7 @@ static void pl011_break_ctl(struct uart_port *port, int break_state)
1285} 1284}
1286 1285
1287#ifdef CONFIG_CONSOLE_POLL 1286#ifdef CONFIG_CONSOLE_POLL
1288static int pl010_get_poll_char(struct uart_port *port) 1287static int pl011_get_poll_char(struct uart_port *port)
1289{ 1288{
1290 struct uart_amba_port *uap = (struct uart_amba_port *)port; 1289 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1291 unsigned int status; 1290 unsigned int status;
@@ -1297,7 +1296,7 @@ static int pl010_get_poll_char(struct uart_port *port)
1297 return readw(uap->port.membase + UART01x_DR); 1296 return readw(uap->port.membase + UART01x_DR);
1298} 1297}
1299 1298
1300static void pl010_put_poll_char(struct uart_port *port, 1299static void pl011_put_poll_char(struct uart_port *port,
1301 unsigned char ch) 1300 unsigned char ch)
1302{ 1301{
1303 struct uart_amba_port *uap = (struct uart_amba_port *)port; 1302 struct uart_amba_port *uap = (struct uart_amba_port *)port;
@@ -1324,16 +1323,12 @@ static int pl011_startup(struct uart_port *port)
1324 "could not set default pins\n"); 1323 "could not set default pins\n");
1325 } 1324 }
1326 1325
1327 retval = clk_prepare(uap->clk);
1328 if (retval)
1329 goto out;
1330
1331 /* 1326 /*
1332 * Try to enable the clock producer. 1327 * Try to enable the clock producer.
1333 */ 1328 */
1334 retval = clk_enable(uap->clk); 1329 retval = clk_prepare_enable(uap->clk);
1335 if (retval) 1330 if (retval)
1336 goto clk_unprep; 1331 goto out;
1337 1332
1338 uap->port.uartclk = clk_get_rate(uap->clk); 1333 uap->port.uartclk = clk_get_rate(uap->clk);
1339 1334
@@ -1411,9 +1406,7 @@ static int pl011_startup(struct uart_port *port)
1411 return 0; 1406 return 0;
1412 1407
1413 clk_dis: 1408 clk_dis:
1414 clk_disable(uap->clk); 1409 clk_disable_unprepare(uap->clk);
1415 clk_unprep:
1416 clk_unprepare(uap->clk);
1417 out: 1410 out:
1418 return retval; 1411 return retval;
1419} 1412}
@@ -1473,8 +1466,7 @@ static void pl011_shutdown(struct uart_port *port)
1473 /* 1466 /*
1474 * Shut down the clock producer 1467 * Shut down the clock producer
1475 */ 1468 */
1476 clk_disable(uap->clk); 1469 clk_disable_unprepare(uap->clk);
1477 clk_unprepare(uap->clk);
1478 /* Optionally let pins go into sleep states */ 1470 /* Optionally let pins go into sleep states */
1479 if (!IS_ERR(uap->pins_sleep)) { 1471 if (!IS_ERR(uap->pins_sleep)) {
1480 retval = pinctrl_select_state(uap->pinctrl, uap->pins_sleep); 1472 retval = pinctrl_select_state(uap->pinctrl, uap->pins_sleep);
@@ -1637,7 +1629,7 @@ static const char *pl011_type(struct uart_port *port)
1637/* 1629/*
1638 * Release the memory region(s) being used by 'port' 1630 * Release the memory region(s) being used by 'port'
1639 */ 1631 */
1640static void pl010_release_port(struct uart_port *port) 1632static void pl011_release_port(struct uart_port *port)
1641{ 1633{
1642 release_mem_region(port->mapbase, SZ_4K); 1634 release_mem_region(port->mapbase, SZ_4K);
1643} 1635}
@@ -1645,7 +1637,7 @@ static void pl010_release_port(struct uart_port *port)
1645/* 1637/*
1646 * Request the memory region(s) being used by 'port' 1638 * Request the memory region(s) being used by 'port'
1647 */ 1639 */
1648static int pl010_request_port(struct uart_port *port) 1640static int pl011_request_port(struct uart_port *port)
1649{ 1641{
1650 return request_mem_region(port->mapbase, SZ_4K, "uart-pl011") 1642 return request_mem_region(port->mapbase, SZ_4K, "uart-pl011")
1651 != NULL ? 0 : -EBUSY; 1643 != NULL ? 0 : -EBUSY;
@@ -1654,18 +1646,18 @@ static int pl010_request_port(struct uart_port *port)
1654/* 1646/*
1655 * Configure/autoconfigure the port. 1647 * Configure/autoconfigure the port.
1656 */ 1648 */
1657static void pl010_config_port(struct uart_port *port, int flags) 1649static void pl011_config_port(struct uart_port *port, int flags)
1658{ 1650{
1659 if (flags & UART_CONFIG_TYPE) { 1651 if (flags & UART_CONFIG_TYPE) {
1660 port->type = PORT_AMBA; 1652 port->type = PORT_AMBA;
1661 pl010_request_port(port); 1653 pl011_request_port(port);
1662 } 1654 }
1663} 1655}
1664 1656
1665/* 1657/*
1666 * verify the new serial_struct (for TIOCSSERIAL). 1658 * verify the new serial_struct (for TIOCSSERIAL).
1667 */ 1659 */
1668static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser) 1660static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser)
1669{ 1661{
1670 int ret = 0; 1662 int ret = 0;
1671 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA) 1663 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
@@ -1678,9 +1670,9 @@ static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser)
1678} 1670}
1679 1671
1680static struct uart_ops amba_pl011_pops = { 1672static struct uart_ops amba_pl011_pops = {
1681 .tx_empty = pl01x_tx_empty, 1673 .tx_empty = pl011_tx_empty,
1682 .set_mctrl = pl011_set_mctrl, 1674 .set_mctrl = pl011_set_mctrl,
1683 .get_mctrl = pl01x_get_mctrl, 1675 .get_mctrl = pl011_get_mctrl,
1684 .stop_tx = pl011_stop_tx, 1676 .stop_tx = pl011_stop_tx,
1685 .start_tx = pl011_start_tx, 1677 .start_tx = pl011_start_tx,
1686 .stop_rx = pl011_stop_rx, 1678 .stop_rx = pl011_stop_rx,
@@ -1691,13 +1683,13 @@ static struct uart_ops amba_pl011_pops = {
1691 .flush_buffer = pl011_dma_flush_buffer, 1683 .flush_buffer = pl011_dma_flush_buffer,
1692 .set_termios = pl011_set_termios, 1684 .set_termios = pl011_set_termios,
1693 .type = pl011_type, 1685 .type = pl011_type,
1694 .release_port = pl010_release_port, 1686 .release_port = pl011_release_port,
1695 .request_port = pl010_request_port, 1687 .request_port = pl011_request_port,
1696 .config_port = pl010_config_port, 1688 .config_port = pl011_config_port,
1697 .verify_port = pl010_verify_port, 1689 .verify_port = pl011_verify_port,
1698#ifdef CONFIG_CONSOLE_POLL 1690#ifdef CONFIG_CONSOLE_POLL
1699 .poll_get_char = pl010_get_poll_char, 1691 .poll_get_char = pl011_get_poll_char,
1700 .poll_put_char = pl010_put_poll_char, 1692 .poll_put_char = pl011_put_poll_char,
1701#endif 1693#endif
1702}; 1694};
1703 1695
@@ -1869,6 +1861,38 @@ static struct uart_driver amba_reg = {
1869 .cons = AMBA_CONSOLE, 1861 .cons = AMBA_CONSOLE,
1870}; 1862};
1871 1863
1864static int pl011_probe_dt_alias(int index, struct device *dev)
1865{
1866 struct device_node *np;
1867 static bool seen_dev_with_alias = false;
1868 static bool seen_dev_without_alias = false;
1869 int ret = index;
1870
1871 if (!IS_ENABLED(CONFIG_OF))
1872 return ret;
1873
1874 np = dev->of_node;
1875 if (!np)
1876 return ret;
1877
1878 ret = of_alias_get_id(np, "serial");
1879 if (IS_ERR_VALUE(ret)) {
1880 seen_dev_without_alias = true;
1881 ret = index;
1882 } else {
1883 seen_dev_with_alias = true;
1884 if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) {
1885 dev_warn(dev, "requested serial port %d not available.\n", ret);
1886 ret = index;
1887 }
1888 }
1889
1890 if (seen_dev_with_alias && seen_dev_without_alias)
1891 dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n");
1892
1893 return ret;
1894}
1895
1872static int pl011_probe(struct amba_device *dev, const struct amba_id *id) 1896static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
1873{ 1897{
1874 struct uart_amba_port *uap; 1898 struct uart_amba_port *uap;
@@ -1891,6 +1915,8 @@ static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
1891 goto out; 1915 goto out;
1892 } 1916 }
1893 1917
1918 i = pl011_probe_dt_alias(i, &dev->dev);
1919
1894 base = ioremap(dev->res.start, resource_size(&dev->res)); 1920 base = ioremap(dev->res.start, resource_size(&dev->res));
1895 if (!base) { 1921 if (!base) {
1896 ret = -ENOMEM; 1922 ret = -ENOMEM;
@@ -1923,7 +1949,6 @@ static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
1923 uap->lcrh_tx = vendor->lcrh_tx; 1949 uap->lcrh_tx = vendor->lcrh_tx;
1924 uap->old_cr = 0; 1950 uap->old_cr = 0;
1925 uap->fifosize = vendor->fifosize; 1951 uap->fifosize = vendor->fifosize;
1926 uap->interrupt_may_hang = vendor->interrupt_may_hang;
1927 uap->port.dev = &dev->dev; 1952 uap->port.dev = &dev->dev;
1928 uap->port.mapbase = dev->res.start; 1953 uap->port.mapbase = dev->res.start;
1929 uap->port.membase = base; 1954 uap->port.membase = base;
diff --git a/drivers/tty/serial/bfin_uart.c b/drivers/tty/serial/bfin_uart.c
index bd97db23985b..9242d56ba267 100644
--- a/drivers/tty/serial/bfin_uart.c
+++ b/drivers/tty/serial/bfin_uart.c
@@ -182,7 +182,7 @@ static void bfin_serial_start_tx(struct uart_port *port)
182 * To avoid losting RX interrupt, we reset IR function 182 * To avoid losting RX interrupt, we reset IR function
183 * before sending data. 183 * before sending data.
184 */ 184 */
185 if (tty->termios->c_line == N_IRDA) 185 if (tty->termios.c_line == N_IRDA)
186 bfin_serial_reset_irda(port); 186 bfin_serial_reset_irda(port);
187 187
188#ifdef CONFIG_SERIAL_BFIN_DMA 188#ifdef CONFIG_SERIAL_BFIN_DMA
diff --git a/drivers/tty/serial/crisv10.c b/drivers/tty/serial/crisv10.c
index 80b6b1b1f725..35ee6a2c6877 100644
--- a/drivers/tty/serial/crisv10.c
+++ b/drivers/tty/serial/crisv10.c
@@ -955,7 +955,7 @@ static const struct control_pins e100_modem_pins[NR_PORTS] =
955/* Calculate the chartime depending on baudrate, numbor of bits etc. */ 955/* Calculate the chartime depending on baudrate, numbor of bits etc. */
956static void update_char_time(struct e100_serial * info) 956static void update_char_time(struct e100_serial * info)
957{ 957{
958 tcflag_t cflags = info->port.tty->termios->c_cflag; 958 tcflag_t cflags = info->port.tty->termios.c_cflag;
959 int bits; 959 int bits;
960 960
961 /* calc. number of bits / data byte */ 961 /* calc. number of bits / data byte */
@@ -1473,7 +1473,7 @@ rs_stop(struct tty_struct *tty)
1473 xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char, 1473 xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char,
1474 STOP_CHAR(info->port.tty)); 1474 STOP_CHAR(info->port.tty));
1475 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, stop); 1475 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, stop);
1476 if (tty->termios->c_iflag & IXON ) { 1476 if (tty->termios.c_iflag & IXON ) {
1477 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable); 1477 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable);
1478 } 1478 }
1479 1479
@@ -1496,7 +1496,7 @@ rs_start(struct tty_struct *tty)
1496 info->xmit.tail,SERIAL_XMIT_SIZE))); 1496 info->xmit.tail,SERIAL_XMIT_SIZE)));
1497 xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char, STOP_CHAR(tty)); 1497 xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char, STOP_CHAR(tty));
1498 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, enable); 1498 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, enable);
1499 if (tty->termios->c_iflag & IXON ) { 1499 if (tty->termios.c_iflag & IXON ) {
1500 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable); 1500 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable);
1501 } 1501 }
1502 1502
@@ -2929,7 +2929,7 @@ shutdown(struct e100_serial * info)
2929 descr[i].buf = 0; 2929 descr[i].buf = 0;
2930 } 2930 }
2931 2931
2932 if (!info->port.tty || (info->port.tty->termios->c_cflag & HUPCL)) { 2932 if (!info->port.tty || (info->port.tty->termios.c_cflag & HUPCL)) {
2933 /* hang up DTR and RTS if HUPCL is enabled */ 2933 /* hang up DTR and RTS if HUPCL is enabled */
2934 e100_dtr(info, 0); 2934 e100_dtr(info, 0);
2935 e100_rts(info, 0); /* could check CRTSCTS before doing this */ 2935 e100_rts(info, 0); /* could check CRTSCTS before doing this */
@@ -2953,12 +2953,12 @@ change_speed(struct e100_serial *info)
2953 unsigned long flags; 2953 unsigned long flags;
2954 /* first some safety checks */ 2954 /* first some safety checks */
2955 2955
2956 if (!info->port.tty || !info->port.tty->termios) 2956 if (!info->port.tty)
2957 return; 2957 return;
2958 if (!info->ioport) 2958 if (!info->ioport)
2959 return; 2959 return;
2960 2960
2961 cflag = info->port.tty->termios->c_cflag; 2961 cflag = info->port.tty->termios.c_cflag;
2962 2962
2963 /* possibly, the tx/rx should be disabled first to do this safely */ 2963 /* possibly, the tx/rx should be disabled first to do this safely */
2964 2964
@@ -3088,7 +3088,7 @@ change_speed(struct e100_serial *info)
3088 info->ioport[REG_REC_CTRL] = info->rx_ctrl; 3088 info->ioport[REG_REC_CTRL] = info->rx_ctrl;
3089 xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char, STOP_CHAR(info->port.tty)); 3089 xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char, STOP_CHAR(info->port.tty));
3090 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, enable); 3090 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, enable);
3091 if (info->port.tty->termios->c_iflag & IXON ) { 3091 if (info->port.tty->termios.c_iflag & IXON ) {
3092 DFLOW(DEBUG_LOG(info->line, "FLOW XOFF enabled 0x%02X\n", 3092 DFLOW(DEBUG_LOG(info->line, "FLOW XOFF enabled 0x%02X\n",
3093 STOP_CHAR(info->port.tty))); 3093 STOP_CHAR(info->port.tty)));
3094 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable); 3094 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable);
@@ -3355,7 +3355,7 @@ rs_throttle(struct tty_struct * tty)
3355 DFLOW(DEBUG_LOG(info->line,"rs_throttle %lu\n", tty->ldisc.chars_in_buffer(tty))); 3355 DFLOW(DEBUG_LOG(info->line,"rs_throttle %lu\n", tty->ldisc.chars_in_buffer(tty)));
3356 3356
3357 /* Do RTS before XOFF since XOFF might take some time */ 3357 /* Do RTS before XOFF since XOFF might take some time */
3358 if (tty->termios->c_cflag & CRTSCTS) { 3358 if (tty->termios.c_cflag & CRTSCTS) {
3359 /* Turn off RTS line */ 3359 /* Turn off RTS line */
3360 e100_rts(info, 0); 3360 e100_rts(info, 0);
3361 } 3361 }
@@ -3377,7 +3377,7 @@ rs_unthrottle(struct tty_struct * tty)
3377 DFLOW(DEBUG_LOG(info->line,"rs_unthrottle ldisc %d\n", tty->ldisc.chars_in_buffer(tty))); 3377 DFLOW(DEBUG_LOG(info->line,"rs_unthrottle ldisc %d\n", tty->ldisc.chars_in_buffer(tty)));
3378 DFLOW(DEBUG_LOG(info->line,"rs_unthrottle flip.count: %i\n", tty->flip.count)); 3378 DFLOW(DEBUG_LOG(info->line,"rs_unthrottle flip.count: %i\n", tty->flip.count));
3379 /* Do RTS before XOFF since XOFF might take some time */ 3379 /* Do RTS before XOFF since XOFF might take some time */
3380 if (tty->termios->c_cflag & CRTSCTS) { 3380 if (tty->termios.c_cflag & CRTSCTS) {
3381 /* Assert RTS line */ 3381 /* Assert RTS line */
3382 e100_rts(info, 1); 3382 e100_rts(info, 1);
3383 } 3383 }
@@ -3748,7 +3748,7 @@ rs_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
3748 3748
3749 /* Handle turning off CRTSCTS */ 3749 /* Handle turning off CRTSCTS */
3750 if ((old_termios->c_cflag & CRTSCTS) && 3750 if ((old_termios->c_cflag & CRTSCTS) &&
3751 !(tty->termios->c_cflag & CRTSCTS)) { 3751 !(tty->termios.c_cflag & CRTSCTS)) {
3752 tty->hw_stopped = 0; 3752 tty->hw_stopped = 0;
3753 rs_start(tty); 3753 rs_start(tty);
3754 } 3754 }
@@ -3815,7 +3815,7 @@ rs_close(struct tty_struct *tty, struct file * filp)
3815 * separate termios for callout and dialin. 3815 * separate termios for callout and dialin.
3816 */ 3816 */
3817 if (info->flags & ASYNC_NORMAL_ACTIVE) 3817 if (info->flags & ASYNC_NORMAL_ACTIVE)
3818 info->normal_termios = *tty->termios; 3818 info->normal_termios = tty->termios;
3819 /* 3819 /*
3820 * Now we wait for the transmit buffer to clear; and we notify 3820 * Now we wait for the transmit buffer to clear; and we notify
3821 * the line discipline to only process XON/XOFF characters. 3821 * the line discipline to only process XON/XOFF characters.
@@ -3976,7 +3976,7 @@ block_til_ready(struct tty_struct *tty, struct file * filp,
3976 */ 3976 */
3977 if (tty_hung_up_p(filp) || 3977 if (tty_hung_up_p(filp) ||
3978 (info->flags & ASYNC_CLOSING)) { 3978 (info->flags & ASYNC_CLOSING)) {
3979 wait_event_interruptible_tty(info->close_wait, 3979 wait_event_interruptible_tty(tty, info->close_wait,
3980 !(info->flags & ASYNC_CLOSING)); 3980 !(info->flags & ASYNC_CLOSING));
3981#ifdef SERIAL_DO_RESTART 3981#ifdef SERIAL_DO_RESTART
3982 if (info->flags & ASYNC_HUP_NOTIFY) 3982 if (info->flags & ASYNC_HUP_NOTIFY)
@@ -3998,7 +3998,7 @@ block_til_ready(struct tty_struct *tty, struct file * filp,
3998 return 0; 3998 return 0;
3999 } 3999 }
4000 4000
4001 if (tty->termios->c_cflag & CLOCAL) { 4001 if (tty->termios.c_cflag & CLOCAL) {
4002 do_clocal = 1; 4002 do_clocal = 1;
4003 } 4003 }
4004 4004
@@ -4052,9 +4052,9 @@ block_til_ready(struct tty_struct *tty, struct file * filp,
4052 printk("block_til_ready blocking: ttyS%d, count = %d\n", 4052 printk("block_til_ready blocking: ttyS%d, count = %d\n",
4053 info->line, info->count); 4053 info->line, info->count);
4054#endif 4054#endif
4055 tty_unlock(); 4055 tty_unlock(tty);
4056 schedule(); 4056 schedule();
4057 tty_lock(); 4057 tty_lock(tty);
4058 } 4058 }
4059 set_current_state(TASK_RUNNING); 4059 set_current_state(TASK_RUNNING);
4060 remove_wait_queue(&info->open_wait, &wait); 4060 remove_wait_queue(&info->open_wait, &wait);
@@ -4115,7 +4115,7 @@ rs_open(struct tty_struct *tty, struct file * filp)
4115 */ 4115 */
4116 if (tty_hung_up_p(filp) || 4116 if (tty_hung_up_p(filp) ||
4117 (info->flags & ASYNC_CLOSING)) { 4117 (info->flags & ASYNC_CLOSING)) {
4118 wait_event_interruptible_tty(info->close_wait, 4118 wait_event_interruptible_tty(tty, info->close_wait,
4119 !(info->flags & ASYNC_CLOSING)); 4119 !(info->flags & ASYNC_CLOSING));
4120#ifdef SERIAL_DO_RESTART 4120#ifdef SERIAL_DO_RESTART
4121 return ((info->flags & ASYNC_HUP_NOTIFY) ? 4121 return ((info->flags & ASYNC_HUP_NOTIFY) ?
@@ -4219,7 +4219,7 @@ rs_open(struct tty_struct *tty, struct file * filp)
4219 } 4219 }
4220 4220
4221 if ((info->count == 1) && (info->flags & ASYNC_SPLIT_TERMIOS)) { 4221 if ((info->count == 1) && (info->flags & ASYNC_SPLIT_TERMIOS)) {
4222 *tty->termios = info->normal_termios; 4222 tty->termios = info->normal_termios;
4223 change_speed(info); 4223 change_speed(info);
4224 } 4224 }
4225 4225
@@ -4443,14 +4443,12 @@ static int __init rs_init(void)
4443 B115200 | CS8 | CREAD | HUPCL | CLOCAL; /* is normally B9600 default... */ 4443 B115200 | CS8 | CREAD | HUPCL | CLOCAL; /* is normally B9600 default... */
4444 driver->init_termios.c_ispeed = 115200; 4444 driver->init_termios.c_ispeed = 115200;
4445 driver->init_termios.c_ospeed = 115200; 4445 driver->init_termios.c_ospeed = 115200;
4446 driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV; 4446 driver->flags = TTY_DRIVER_REAL_RAW;
4447 4447
4448 tty_set_operations(driver, &rs_ops); 4448 tty_set_operations(driver, &rs_ops);
4449 serial_driver = driver; 4449 serial_driver = driver;
4450 if (tty_register_driver(driver))
4451 panic("Couldn't register serial driver\n");
4452 /* do some initializing for the separate ports */
4453 4450
4451 /* do some initializing for the separate ports */
4454 for (i = 0, info = rs_table; i < NR_PORTS; i++,info++) { 4452 for (i = 0, info = rs_table; i < NR_PORTS; i++,info++) {
4455 if (info->enabled) { 4453 if (info->enabled) {
4456 if (cris_request_io_interface(info->io_if, 4454 if (cris_request_io_interface(info->io_if,
@@ -4502,7 +4500,12 @@ static int __init rs_init(void)
4502 printk(KERN_INFO "%s%d at %p is a builtin UART with DMA\n", 4500 printk(KERN_INFO "%s%d at %p is a builtin UART with DMA\n",
4503 serial_driver->name, info->line, info->ioport); 4501 serial_driver->name, info->line, info->ioport);
4504 } 4502 }
4503 tty_port_link_device(&info->port, driver, i);
4505 } 4504 }
4505
4506 if (tty_register_driver(driver))
4507 panic("Couldn't register serial driver\n");
4508
4506#ifdef CONFIG_ETRAX_FAST_TIMER 4509#ifdef CONFIG_ETRAX_FAST_TIMER
4507#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER 4510#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
4508 memset(fast_timers, 0, sizeof(fast_timers)); 4511 memset(fast_timers, 0, sizeof(fast_timers));
diff --git a/drivers/tty/serial/ifx6x60.c b/drivers/tty/serial/ifx6x60.c
index 3ad079ffd049..5b9bc19ed134 100644
--- a/drivers/tty/serial/ifx6x60.c
+++ b/drivers/tty/serial/ifx6x60.c
@@ -800,8 +800,8 @@ static int ifx_spi_create_port(struct ifx_spi_device *ifx_dev)
800 tty_port_init(pport); 800 tty_port_init(pport);
801 pport->ops = &ifx_tty_port_ops; 801 pport->ops = &ifx_tty_port_ops;
802 ifx_dev->minor = IFX_SPI_TTY_ID; 802 ifx_dev->minor = IFX_SPI_TTY_ID;
803 ifx_dev->tty_dev = tty_register_device(tty_drv, ifx_dev->minor, 803 ifx_dev->tty_dev = tty_port_register_device(pport, tty_drv,
804 &ifx_dev->spi_dev->dev); 804 ifx_dev->minor, &ifx_dev->spi_dev->dev);
805 if (IS_ERR(ifx_dev->tty_dev)) { 805 if (IS_ERR(ifx_dev->tty_dev)) {
806 dev_dbg(&ifx_dev->spi_dev->dev, 806 dev_dbg(&ifx_dev->spi_dev->dev,
807 "%s: registering tty device failed", __func__); 807 "%s: registering tty device failed", __func__);
diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
index e309e8b0aaba..5952b25c288e 100644
--- a/drivers/tty/serial/imx.c
+++ b/drivers/tty/serial/imx.c
@@ -207,7 +207,7 @@ struct imx_port {
207 unsigned short trcv_delay; /* transceiver delay */ 207 unsigned short trcv_delay; /* transceiver delay */
208 struct clk *clk_ipg; 208 struct clk *clk_ipg;
209 struct clk *clk_per; 209 struct clk *clk_per;
210 struct imx_uart_data *devdata; 210 const struct imx_uart_data *devdata;
211}; 211};
212 212
213struct imx_port_ucrs { 213struct imx_port_ucrs {
@@ -1505,18 +1505,21 @@ static int serial_imx_probe(struct platform_device *pdev)
1505 pinctrl = devm_pinctrl_get_select_default(&pdev->dev); 1505 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1506 if (IS_ERR(pinctrl)) { 1506 if (IS_ERR(pinctrl)) {
1507 ret = PTR_ERR(pinctrl); 1507 ret = PTR_ERR(pinctrl);
1508 dev_err(&pdev->dev, "failed to get default pinctrl: %d\n", ret);
1508 goto unmap; 1509 goto unmap;
1509 } 1510 }
1510 1511
1511 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 1512 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1512 if (IS_ERR(sport->clk_ipg)) { 1513 if (IS_ERR(sport->clk_ipg)) {
1513 ret = PTR_ERR(sport->clk_ipg); 1514 ret = PTR_ERR(sport->clk_ipg);
1515 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
1514 goto unmap; 1516 goto unmap;
1515 } 1517 }
1516 1518
1517 sport->clk_per = devm_clk_get(&pdev->dev, "per"); 1519 sport->clk_per = devm_clk_get(&pdev->dev, "per");
1518 if (IS_ERR(sport->clk_per)) { 1520 if (IS_ERR(sport->clk_per)) {
1519 ret = PTR_ERR(sport->clk_per); 1521 ret = PTR_ERR(sport->clk_per);
1522 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
1520 goto unmap; 1523 goto unmap;
1521 } 1524 }
1522 1525
diff --git a/drivers/tty/serial/ioc3_serial.c b/drivers/tty/serial/ioc3_serial.c
index 758ff310f7f8..5ac52898a0bb 100644
--- a/drivers/tty/serial/ioc3_serial.c
+++ b/drivers/tty/serial/ioc3_serial.c
@@ -1120,13 +1120,14 @@ static inline int do_read(struct uart_port *the_port, char *buf, int len)
1120 struct ioc3_port *port = get_ioc3_port(the_port); 1120 struct ioc3_port *port = get_ioc3_port(the_port);
1121 struct ring *inring; 1121 struct ring *inring;
1122 struct ring_entry *entry; 1122 struct ring_entry *entry;
1123 struct port_hooks *hooks = port->ip_hooks; 1123 struct port_hooks *hooks;
1124 int byte_num; 1124 int byte_num;
1125 char *sc; 1125 char *sc;
1126 int loop_counter; 1126 int loop_counter;
1127 1127
1128 BUG_ON(!(len >= 0)); 1128 BUG_ON(!(len >= 0));
1129 BUG_ON(!port); 1129 BUG_ON(!port);
1130 hooks = port->ip_hooks;
1130 1131
1131 /* There is a nasty timing issue in the IOC3. When the rx_timer 1132 /* There is a nasty timing issue in the IOC3. When the rx_timer
1132 * expires or the rx_high condition arises, we take an interrupt. 1133 * expires or the rx_high condition arises, we take an interrupt.
diff --git a/drivers/tty/serial/ioc4_serial.c b/drivers/tty/serial/ioc4_serial.c
index e16894fb2ca3..3e7da10cebba 100644
--- a/drivers/tty/serial/ioc4_serial.c
+++ b/drivers/tty/serial/ioc4_serial.c
@@ -1803,7 +1803,7 @@ static inline int ic4_startup_local(struct uart_port *the_port)
1803 ioc4_set_proto(port, the_port->mapbase); 1803 ioc4_set_proto(port, the_port->mapbase);
1804 1804
1805 /* set the speed of the serial port */ 1805 /* set the speed of the serial port */
1806 ioc4_change_speed(the_port, state->port.tty->termios, 1806 ioc4_change_speed(the_port, &state->port.tty->termios,
1807 (struct ktermios *)0); 1807 (struct ktermios *)0);
1808 1808
1809 return 0; 1809 return 0;
@@ -2069,13 +2069,14 @@ static inline int do_read(struct uart_port *the_port, unsigned char *buf,
2069 struct ioc4_port *port = get_ioc4_port(the_port, 0); 2069 struct ioc4_port *port = get_ioc4_port(the_port, 0);
2070 struct ring *inring; 2070 struct ring *inring;
2071 struct ring_entry *entry; 2071 struct ring_entry *entry;
2072 struct hooks *hooks = port->ip_hooks; 2072 struct hooks *hooks;
2073 int byte_num; 2073 int byte_num;
2074 char *sc; 2074 char *sc;
2075 int loop_counter; 2075 int loop_counter;
2076 2076
2077 BUG_ON(!(len >= 0)); 2077 BUG_ON(!(len >= 0));
2078 BUG_ON(!port); 2078 BUG_ON(!port);
2079 hooks = port->ip_hooks;
2079 2080
2080 /* There is a nasty timing issue in the IOC4. When the rx_timer 2081 /* There is a nasty timing issue in the IOC4. When the rx_timer
2081 * expires or the rx_high condition arises, we take an interrupt. 2082 * expires or the rx_high condition arises, we take an interrupt.
diff --git a/drivers/tty/serial/jsm/jsm_tty.c b/drivers/tty/serial/jsm/jsm_tty.c
index 434bd881fcae..71397961773c 100644
--- a/drivers/tty/serial/jsm/jsm_tty.c
+++ b/drivers/tty/serial/jsm/jsm_tty.c
@@ -161,7 +161,7 @@ static void jsm_tty_send_xchar(struct uart_port *port, char ch)
161 struct ktermios *termios; 161 struct ktermios *termios;
162 162
163 spin_lock_irqsave(&port->lock, lock_flags); 163 spin_lock_irqsave(&port->lock, lock_flags);
164 termios = port->state->port.tty->termios; 164 termios = &port->state->port.tty->termios;
165 if (ch == termios->c_cc[VSTART]) 165 if (ch == termios->c_cc[VSTART])
166 channel->ch_bd->bd_ops->send_start_character(channel); 166 channel->ch_bd->bd_ops->send_start_character(channel);
167 167
@@ -250,7 +250,7 @@ static int jsm_tty_open(struct uart_port *port)
250 channel->ch_cached_lsr = 0; 250 channel->ch_cached_lsr = 0;
251 channel->ch_stops_sent = 0; 251 channel->ch_stops_sent = 0;
252 252
253 termios = port->state->port.tty->termios; 253 termios = &port->state->port.tty->termios;
254 channel->ch_c_cflag = termios->c_cflag; 254 channel->ch_c_cflag = termios->c_cflag;
255 channel->ch_c_iflag = termios->c_iflag; 255 channel->ch_c_iflag = termios->c_iflag;
256 channel->ch_c_oflag = termios->c_oflag; 256 channel->ch_c_oflag = termios->c_oflag;
@@ -283,7 +283,7 @@ static void jsm_tty_close(struct uart_port *port)
283 jsm_printk(CLOSE, INFO, &channel->ch_bd->pci_dev, "start\n"); 283 jsm_printk(CLOSE, INFO, &channel->ch_bd->pci_dev, "start\n");
284 284
285 bd = channel->ch_bd; 285 bd = channel->ch_bd;
286 ts = port->state->port.tty->termios; 286 ts = &port->state->port.tty->termios;
287 287
288 channel->ch_flags &= ~(CH_STOPI); 288 channel->ch_flags &= ~(CH_STOPI);
289 289
@@ -567,7 +567,7 @@ void jsm_input(struct jsm_channel *ch)
567 *input data and return immediately. 567 *input data and return immediately.
568 */ 568 */
569 if (!tp || 569 if (!tp ||
570 !(tp->termios->c_cflag & CREAD) ) { 570 !(tp->termios.c_cflag & CREAD) ) {
571 571
572 jsm_printk(READ, INFO, &ch->ch_bd->pci_dev, 572 jsm_printk(READ, INFO, &ch->ch_bd->pci_dev,
573 "input. dropping %d bytes on port %d...\n", data_len, ch->ch_portnum); 573 "input. dropping %d bytes on port %d...\n", data_len, ch->ch_portnum);
diff --git a/drivers/tty/serial/lpc32xx_hs.c b/drivers/tty/serial/lpc32xx_hs.c
new file mode 100644
index 000000000000..ba3af3bf6d43
--- /dev/null
+++ b/drivers/tty/serial/lpc32xx_hs.c
@@ -0,0 +1,823 @@
1/*
2 * High Speed Serial Ports on NXP LPC32xx SoC
3 *
4 * Authors: Kevin Wells <kevin.wells@nxp.com>
5 * Roland Stigge <stigge@antcom.de>
6 *
7 * Copyright (C) 2010 NXP Semiconductors
8 * Copyright (C) 2012 Roland Stigge
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 */
20
21#include <linux/module.h>
22#include <linux/ioport.h>
23#include <linux/init.h>
24#include <linux/console.h>
25#include <linux/sysrq.h>
26#include <linux/tty.h>
27#include <linux/tty_flip.h>
28#include <linux/serial_core.h>
29#include <linux/serial.h>
30#include <linux/platform_device.h>
31#include <linux/delay.h>
32#include <linux/nmi.h>
33#include <linux/io.h>
34#include <linux/irq.h>
35#include <linux/gpio.h>
36#include <linux/of.h>
37#include <mach/platform.h>
38#include <mach/hardware.h>
39
40/*
41 * High Speed UART register offsets
42 */
43#define LPC32XX_HSUART_FIFO(x) ((x) + 0x00)
44#define LPC32XX_HSUART_LEVEL(x) ((x) + 0x04)
45#define LPC32XX_HSUART_IIR(x) ((x) + 0x08)
46#define LPC32XX_HSUART_CTRL(x) ((x) + 0x0C)
47#define LPC32XX_HSUART_RATE(x) ((x) + 0x10)
48
49#define LPC32XX_HSU_BREAK_DATA (1 << 10)
50#define LPC32XX_HSU_ERROR_DATA (1 << 9)
51#define LPC32XX_HSU_RX_EMPTY (1 << 8)
52
53#define LPC32XX_HSU_TX_LEV(n) (((n) >> 8) & 0xFF)
54#define LPC32XX_HSU_RX_LEV(n) ((n) & 0xFF)
55
56#define LPC32XX_HSU_TX_INT_SET (1 << 6)
57#define LPC32XX_HSU_RX_OE_INT (1 << 5)
58#define LPC32XX_HSU_BRK_INT (1 << 4)
59#define LPC32XX_HSU_FE_INT (1 << 3)
60#define LPC32XX_HSU_RX_TIMEOUT_INT (1 << 2)
61#define LPC32XX_HSU_RX_TRIG_INT (1 << 1)
62#define LPC32XX_HSU_TX_INT (1 << 0)
63
64#define LPC32XX_HSU_HRTS_INV (1 << 21)
65#define LPC32XX_HSU_HRTS_TRIG_8B (0x0 << 19)
66#define LPC32XX_HSU_HRTS_TRIG_16B (0x1 << 19)
67#define LPC32XX_HSU_HRTS_TRIG_32B (0x2 << 19)
68#define LPC32XX_HSU_HRTS_TRIG_48B (0x3 << 19)
69#define LPC32XX_HSU_HRTS_EN (1 << 18)
70#define LPC32XX_HSU_TMO_DISABLED (0x0 << 16)
71#define LPC32XX_HSU_TMO_INACT_4B (0x1 << 16)
72#define LPC32XX_HSU_TMO_INACT_8B (0x2 << 16)
73#define LPC32XX_HSU_TMO_INACT_16B (0x3 << 16)
74#define LPC32XX_HSU_HCTS_INV (1 << 15)
75#define LPC32XX_HSU_HCTS_EN (1 << 14)
76#define LPC32XX_HSU_OFFSET(n) ((n) << 9)
77#define LPC32XX_HSU_BREAK (1 << 8)
78#define LPC32XX_HSU_ERR_INT_EN (1 << 7)
79#define LPC32XX_HSU_RX_INT_EN (1 << 6)
80#define LPC32XX_HSU_TX_INT_EN (1 << 5)
81#define LPC32XX_HSU_RX_TL1B (0x0 << 2)
82#define LPC32XX_HSU_RX_TL4B (0x1 << 2)
83#define LPC32XX_HSU_RX_TL8B (0x2 << 2)
84#define LPC32XX_HSU_RX_TL16B (0x3 << 2)
85#define LPC32XX_HSU_RX_TL32B (0x4 << 2)
86#define LPC32XX_HSU_RX_TL48B (0x5 << 2)
87#define LPC32XX_HSU_TX_TLEMPTY (0x0 << 0)
88#define LPC32XX_HSU_TX_TL0B (0x0 << 0)
89#define LPC32XX_HSU_TX_TL4B (0x1 << 0)
90#define LPC32XX_HSU_TX_TL8B (0x2 << 0)
91#define LPC32XX_HSU_TX_TL16B (0x3 << 0)
92
93#define MODNAME "lpc32xx_hsuart"
94
95struct lpc32xx_hsuart_port {
96 struct uart_port port;
97};
98
99#define FIFO_READ_LIMIT 128
100#define MAX_PORTS 3
101#define LPC32XX_TTY_NAME "ttyTX"
102static struct lpc32xx_hsuart_port lpc32xx_hs_ports[MAX_PORTS];
103
104#ifdef CONFIG_SERIAL_HS_LPC32XX_CONSOLE
105static void wait_for_xmit_empty(struct uart_port *port)
106{
107 unsigned int timeout = 10000;
108
109 do {
110 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(
111 port->membase))) == 0)
112 break;
113 if (--timeout == 0)
114 break;
115 udelay(1);
116 } while (1);
117}
118
119static void wait_for_xmit_ready(struct uart_port *port)
120{
121 unsigned int timeout = 10000;
122
123 while (1) {
124 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(
125 port->membase))) < 32)
126 break;
127 if (--timeout == 0)
128 break;
129 udelay(1);
130 }
131}
132
133static void lpc32xx_hsuart_console_putchar(struct uart_port *port, int ch)
134{
135 wait_for_xmit_ready(port);
136 writel((u32)ch, LPC32XX_HSUART_FIFO(port->membase));
137}
138
139static void lpc32xx_hsuart_console_write(struct console *co, const char *s,
140 unsigned int count)
141{
142 struct lpc32xx_hsuart_port *up = &lpc32xx_hs_ports[co->index];
143 unsigned long flags;
144 int locked = 1;
145
146 touch_nmi_watchdog();
147 local_irq_save(flags);
148 if (up->port.sysrq)
149 locked = 0;
150 else if (oops_in_progress)
151 locked = spin_trylock(&up->port.lock);
152 else
153 spin_lock(&up->port.lock);
154
155 uart_console_write(&up->port, s, count, lpc32xx_hsuart_console_putchar);
156 wait_for_xmit_empty(&up->port);
157
158 if (locked)
159 spin_unlock(&up->port.lock);
160 local_irq_restore(flags);
161}
162
163static int __init lpc32xx_hsuart_console_setup(struct console *co,
164 char *options)
165{
166 struct uart_port *port;
167 int baud = 115200;
168 int bits = 8;
169 int parity = 'n';
170 int flow = 'n';
171
172 if (co->index >= MAX_PORTS)
173 co->index = 0;
174
175 port = &lpc32xx_hs_ports[co->index].port;
176 if (!port->membase)
177 return -ENODEV;
178
179 if (options)
180 uart_parse_options(options, &baud, &parity, &bits, &flow);
181
182 return uart_set_options(port, co, baud, parity, bits, flow);
183}
184
185static struct uart_driver lpc32xx_hsuart_reg;
186static struct console lpc32xx_hsuart_console = {
187 .name = LPC32XX_TTY_NAME,
188 .write = lpc32xx_hsuart_console_write,
189 .device = uart_console_device,
190 .setup = lpc32xx_hsuart_console_setup,
191 .flags = CON_PRINTBUFFER,
192 .index = -1,
193 .data = &lpc32xx_hsuart_reg,
194};
195
196static int __init lpc32xx_hsuart_console_init(void)
197{
198 register_console(&lpc32xx_hsuart_console);
199 return 0;
200}
201console_initcall(lpc32xx_hsuart_console_init);
202
203#define LPC32XX_HSUART_CONSOLE (&lpc32xx_hsuart_console)
204#else
205#define LPC32XX_HSUART_CONSOLE NULL
206#endif
207
208static struct uart_driver lpc32xx_hs_reg = {
209 .owner = THIS_MODULE,
210 .driver_name = MODNAME,
211 .dev_name = LPC32XX_TTY_NAME,
212 .nr = MAX_PORTS,
213 .cons = LPC32XX_HSUART_CONSOLE,
214};
215static int uarts_registered;
216
217static unsigned int __serial_get_clock_div(unsigned long uartclk,
218 unsigned long rate)
219{
220 u32 div, goodrate, hsu_rate, l_hsu_rate, comprate;
221 u32 rate_diff;
222
223 /* Find the closest divider to get the desired clock rate */
224 div = uartclk / rate;
225 goodrate = hsu_rate = (div / 14) - 1;
226 if (hsu_rate != 0)
227 hsu_rate--;
228
229 /* Tweak divider */
230 l_hsu_rate = hsu_rate + 3;
231 rate_diff = 0xFFFFFFFF;
232
233 while (hsu_rate < l_hsu_rate) {
234 comprate = uartclk / ((hsu_rate + 1) * 14);
235 if (abs(comprate - rate) < rate_diff) {
236 goodrate = hsu_rate;
237 rate_diff = abs(comprate - rate);
238 }
239
240 hsu_rate++;
241 }
242 if (hsu_rate > 0xFF)
243 hsu_rate = 0xFF;
244
245 return goodrate;
246}
247
248static void __serial_uart_flush(struct uart_port *port)
249{
250 u32 tmp;
251 int cnt = 0;
252
253 while ((readl(LPC32XX_HSUART_LEVEL(port->membase)) > 0) &&
254 (cnt++ < FIFO_READ_LIMIT))
255 tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
256}
257
258static void __serial_lpc32xx_rx(struct uart_port *port)
259{
260 unsigned int tmp, flag;
261 struct tty_struct *tty = tty_port_tty_get(&port->state->port);
262
263 if (!tty) {
264 /* Discard data: no tty available */
265 while (!(readl(LPC32XX_HSUART_FIFO(port->membase)) &
266 LPC32XX_HSU_RX_EMPTY))
267 ;
268
269 return;
270 }
271
272 /* Read data from FIFO and push into terminal */
273 tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
274 while (!(tmp & LPC32XX_HSU_RX_EMPTY)) {
275 flag = TTY_NORMAL;
276 port->icount.rx++;
277
278 if (tmp & LPC32XX_HSU_ERROR_DATA) {
279 /* Framing error */
280 writel(LPC32XX_HSU_FE_INT,
281 LPC32XX_HSUART_IIR(port->membase));
282 port->icount.frame++;
283 flag = TTY_FRAME;
284 tty_insert_flip_char(tty, 0, TTY_FRAME);
285 }
286
287 tty_insert_flip_char(tty, (tmp & 0xFF), flag);
288
289 tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
290 }
291 tty_flip_buffer_push(tty);
292 tty_kref_put(tty);
293}
294
295static void __serial_lpc32xx_tx(struct uart_port *port)
296{
297 struct circ_buf *xmit = &port->state->xmit;
298 unsigned int tmp;
299
300 if (port->x_char) {
301 writel((u32)port->x_char, LPC32XX_HSUART_FIFO(port->membase));
302 port->icount.tx++;
303 port->x_char = 0;
304 return;
305 }
306
307 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
308 goto exit_tx;
309
310 /* Transfer data */
311 while (LPC32XX_HSU_TX_LEV(readl(
312 LPC32XX_HSUART_LEVEL(port->membase))) < 64) {
313 writel((u32) xmit->buf[xmit->tail],
314 LPC32XX_HSUART_FIFO(port->membase));
315 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
316 port->icount.tx++;
317 if (uart_circ_empty(xmit))
318 break;
319 }
320
321 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
322 uart_write_wakeup(port);
323
324exit_tx:
325 if (uart_circ_empty(xmit)) {
326 tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
327 tmp &= ~LPC32XX_HSU_TX_INT_EN;
328 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
329 }
330}
331
332static irqreturn_t serial_lpc32xx_interrupt(int irq, void *dev_id)
333{
334 struct uart_port *port = dev_id;
335 struct tty_struct *tty = tty_port_tty_get(&port->state->port);
336 u32 status;
337
338 spin_lock(&port->lock);
339
340 /* Read UART status and clear latched interrupts */
341 status = readl(LPC32XX_HSUART_IIR(port->membase));
342
343 if (status & LPC32XX_HSU_BRK_INT) {
344 /* Break received */
345 writel(LPC32XX_HSU_BRK_INT, LPC32XX_HSUART_IIR(port->membase));
346 port->icount.brk++;
347 uart_handle_break(port);
348 }
349
350 /* Framing error */
351 if (status & LPC32XX_HSU_FE_INT)
352 writel(LPC32XX_HSU_FE_INT, LPC32XX_HSUART_IIR(port->membase));
353
354 if (status & LPC32XX_HSU_RX_OE_INT) {
355 /* Receive FIFO overrun */
356 writel(LPC32XX_HSU_RX_OE_INT,
357 LPC32XX_HSUART_IIR(port->membase));
358 port->icount.overrun++;
359 if (tty) {
360 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
361 tty_schedule_flip(tty);
362 }
363 }
364
365 /* Data received? */
366 if (status & (LPC32XX_HSU_RX_TIMEOUT_INT | LPC32XX_HSU_RX_TRIG_INT)) {
367 __serial_lpc32xx_rx(port);
368 if (tty)
369 tty_flip_buffer_push(tty);
370 }
371
372 /* Transmit data request? */
373 if ((status & LPC32XX_HSU_TX_INT) && (!uart_tx_stopped(port))) {
374 writel(LPC32XX_HSU_TX_INT, LPC32XX_HSUART_IIR(port->membase));
375 __serial_lpc32xx_tx(port);
376 }
377
378 spin_unlock(&port->lock);
379 tty_kref_put(tty);
380
381 return IRQ_HANDLED;
382}
383
384/* port->lock is not held. */
385static unsigned int serial_lpc32xx_tx_empty(struct uart_port *port)
386{
387 unsigned int ret = 0;
388
389 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(port->membase))) == 0)
390 ret = TIOCSER_TEMT;
391
392 return ret;
393}
394
395/* port->lock held by caller. */
396static void serial_lpc32xx_set_mctrl(struct uart_port *port,
397 unsigned int mctrl)
398{
399 /* No signals are supported on HS UARTs */
400}
401
402/* port->lock is held by caller and interrupts are disabled. */
403static unsigned int serial_lpc32xx_get_mctrl(struct uart_port *port)
404{
405 /* No signals are supported on HS UARTs */
406 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
407}
408
409/* port->lock held by caller. */
410static void serial_lpc32xx_stop_tx(struct uart_port *port)
411{
412 u32 tmp;
413
414 tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
415 tmp &= ~LPC32XX_HSU_TX_INT_EN;
416 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
417}
418
419/* port->lock held by caller. */
420static void serial_lpc32xx_start_tx(struct uart_port *port)
421{
422 u32 tmp;
423
424 __serial_lpc32xx_tx(port);
425 tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
426 tmp |= LPC32XX_HSU_TX_INT_EN;
427 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
428}
429
430/* port->lock held by caller. */
431static void serial_lpc32xx_stop_rx(struct uart_port *port)
432{
433 u32 tmp;
434
435 tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
436 tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN);
437 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
438
439 writel((LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT |
440 LPC32XX_HSU_FE_INT), LPC32XX_HSUART_IIR(port->membase));
441}
442
443/* port->lock held by caller. */
444static void serial_lpc32xx_enable_ms(struct uart_port *port)
445{
446 /* Modem status is not supported */
447}
448
449/* port->lock is not held. */
450static void serial_lpc32xx_break_ctl(struct uart_port *port,
451 int break_state)
452{
453 unsigned long flags;
454 u32 tmp;
455
456 spin_lock_irqsave(&port->lock, flags);
457 tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
458 if (break_state != 0)
459 tmp |= LPC32XX_HSU_BREAK;
460 else
461 tmp &= ~LPC32XX_HSU_BREAK;
462 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
463 spin_unlock_irqrestore(&port->lock, flags);
464}
465
466/* LPC3250 Errata HSUART.1: Hang workaround via loopback mode on inactivity */
467static void lpc32xx_loopback_set(resource_size_t mapbase, int state)
468{
469 int bit;
470 u32 tmp;
471
472 switch (mapbase) {
473 case LPC32XX_HS_UART1_BASE:
474 bit = 0;
475 break;
476 case LPC32XX_HS_UART2_BASE:
477 bit = 1;
478 break;
479 case LPC32XX_HS_UART7_BASE:
480 bit = 6;
481 break;
482 default:
483 WARN(1, "lpc32xx_hs: Warning: Unknown port at %08x\n", mapbase);
484 return;
485 }
486
487 tmp = readl(LPC32XX_UARTCTL_CLOOP);
488 if (state)
489 tmp |= (1 << bit);
490 else
491 tmp &= ~(1 << bit);
492 writel(tmp, LPC32XX_UARTCTL_CLOOP);
493}
494
495/* port->lock is not held. */
496static int serial_lpc32xx_startup(struct uart_port *port)
497{
498 int retval;
499 unsigned long flags;
500 u32 tmp;
501
502 spin_lock_irqsave(&port->lock, flags);
503
504 __serial_uart_flush(port);
505
506 writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT |
507 LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT),
508 LPC32XX_HSUART_IIR(port->membase));
509
510 writel(0xFF, LPC32XX_HSUART_RATE(port->membase));
511
512 /*
513 * Set receiver timeout, HSU offset of 20, no break, no interrupts,
514 * and default FIFO trigger levels
515 */
516 tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
517 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B;
518 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
519
520 lpc32xx_loopback_set(port->mapbase, 0); /* get out of loopback mode */
521
522 spin_unlock_irqrestore(&port->lock, flags);
523
524 retval = request_irq(port->irq, serial_lpc32xx_interrupt,
525 0, MODNAME, port);
526 if (!retval)
527 writel((tmp | LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN),
528 LPC32XX_HSUART_CTRL(port->membase));
529
530 return retval;
531}
532
533/* port->lock is not held. */
534static void serial_lpc32xx_shutdown(struct uart_port *port)
535{
536 u32 tmp;
537 unsigned long flags;
538
539 spin_lock_irqsave(&port->lock, flags);
540
541 tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
542 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B;
543 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
544
545 lpc32xx_loopback_set(port->mapbase, 1); /* go to loopback mode */
546
547 spin_unlock_irqrestore(&port->lock, flags);
548
549 free_irq(port->irq, port);
550}
551
552/* port->lock is not held. */
553static void serial_lpc32xx_set_termios(struct uart_port *port,
554 struct ktermios *termios,
555 struct ktermios *old)
556{
557 unsigned long flags;
558 unsigned int baud, quot;
559 u32 tmp;
560
561 /* Always 8-bit, no parity, 1 stop bit */
562 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD);
563 termios->c_cflag |= CS8;
564
565 termios->c_cflag &= ~(HUPCL | CMSPAR | CLOCAL | CRTSCTS);
566
567 baud = uart_get_baud_rate(port, termios, old, 0,
568 port->uartclk / 14);
569
570 quot = __serial_get_clock_div(port->uartclk, baud);
571
572 spin_lock_irqsave(&port->lock, flags);
573
574 /* Ignore characters? */
575 tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
576 if ((termios->c_cflag & CREAD) == 0)
577 tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN);
578 else
579 tmp |= LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN;
580 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
581
582 writel(quot, LPC32XX_HSUART_RATE(port->membase));
583
584 uart_update_timeout(port, termios->c_cflag, baud);
585
586 spin_unlock_irqrestore(&port->lock, flags);
587
588 /* Don't rewrite B0 */
589 if (tty_termios_baud_rate(termios))
590 tty_termios_encode_baud_rate(termios, baud, baud);
591}
592
593static const char *serial_lpc32xx_type(struct uart_port *port)
594{
595 return MODNAME;
596}
597
598static void serial_lpc32xx_release_port(struct uart_port *port)
599{
600 if ((port->iotype == UPIO_MEM32) && (port->mapbase)) {
601 if (port->flags & UPF_IOREMAP) {
602 iounmap(port->membase);
603 port->membase = NULL;
604 }
605
606 release_mem_region(port->mapbase, SZ_4K);
607 }
608}
609
610static int serial_lpc32xx_request_port(struct uart_port *port)
611{
612 int ret = -ENODEV;
613
614 if ((port->iotype == UPIO_MEM32) && (port->mapbase)) {
615 ret = 0;
616
617 if (!request_mem_region(port->mapbase, SZ_4K, MODNAME))
618 ret = -EBUSY;
619 else if (port->flags & UPF_IOREMAP) {
620 port->membase = ioremap(port->mapbase, SZ_4K);
621 if (!port->membase) {
622 release_mem_region(port->mapbase, SZ_4K);
623 ret = -ENOMEM;
624 }
625 }
626 }
627
628 return ret;
629}
630
631static void serial_lpc32xx_config_port(struct uart_port *port, int uflags)
632{
633 int ret;
634
635 ret = serial_lpc32xx_request_port(port);
636 if (ret < 0)
637 return;
638 port->type = PORT_UART00;
639 port->fifosize = 64;
640
641 __serial_uart_flush(port);
642
643 writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT |
644 LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT),
645 LPC32XX_HSUART_IIR(port->membase));
646
647 writel(0xFF, LPC32XX_HSUART_RATE(port->membase));
648
649 /* Set receiver timeout, HSU offset of 20, no break, no interrupts,
650 and default FIFO trigger levels */
651 writel(LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
652 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B,
653 LPC32XX_HSUART_CTRL(port->membase));
654}
655
656static int serial_lpc32xx_verify_port(struct uart_port *port,
657 struct serial_struct *ser)
658{
659 int ret = 0;
660
661 if (ser->type != PORT_UART00)
662 ret = -EINVAL;
663
664 return ret;
665}
666
667static struct uart_ops serial_lpc32xx_pops = {
668 .tx_empty = serial_lpc32xx_tx_empty,
669 .set_mctrl = serial_lpc32xx_set_mctrl,
670 .get_mctrl = serial_lpc32xx_get_mctrl,
671 .stop_tx = serial_lpc32xx_stop_tx,
672 .start_tx = serial_lpc32xx_start_tx,
673 .stop_rx = serial_lpc32xx_stop_rx,
674 .enable_ms = serial_lpc32xx_enable_ms,
675 .break_ctl = serial_lpc32xx_break_ctl,
676 .startup = serial_lpc32xx_startup,
677 .shutdown = serial_lpc32xx_shutdown,
678 .set_termios = serial_lpc32xx_set_termios,
679 .type = serial_lpc32xx_type,
680 .release_port = serial_lpc32xx_release_port,
681 .request_port = serial_lpc32xx_request_port,
682 .config_port = serial_lpc32xx_config_port,
683 .verify_port = serial_lpc32xx_verify_port,
684};
685
686/*
687 * Register a set of serial devices attached to a platform device
688 */
689static int __devinit serial_hs_lpc32xx_probe(struct platform_device *pdev)
690{
691 struct lpc32xx_hsuart_port *p = &lpc32xx_hs_ports[uarts_registered];
692 int ret = 0;
693 struct resource *res;
694
695 if (uarts_registered >= MAX_PORTS) {
696 dev_err(&pdev->dev,
697 "Error: Number of possible ports exceeded (%d)!\n",
698 uarts_registered + 1);
699 return -ENXIO;
700 }
701
702 memset(p, 0, sizeof(*p));
703
704 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
705 if (!res) {
706 dev_err(&pdev->dev,
707 "Error getting mem resource for HS UART port %d\n",
708 uarts_registered);
709 return -ENXIO;
710 }
711 p->port.mapbase = res->start;
712 p->port.membase = NULL;
713
714 p->port.irq = platform_get_irq(pdev, 0);
715 if (p->port.irq < 0) {
716 dev_err(&pdev->dev, "Error getting irq for HS UART port %d\n",
717 uarts_registered);
718 return p->port.irq;
719 }
720
721 p->port.iotype = UPIO_MEM32;
722 p->port.uartclk = LPC32XX_MAIN_OSC_FREQ;
723 p->port.regshift = 2;
724 p->port.flags = UPF_BOOT_AUTOCONF | UPF_FIXED_PORT | UPF_IOREMAP;
725 p->port.dev = &pdev->dev;
726 p->port.ops = &serial_lpc32xx_pops;
727 p->port.line = uarts_registered++;
728 spin_lock_init(&p->port.lock);
729
730 /* send port to loopback mode by default */
731 lpc32xx_loopback_set(p->port.mapbase, 1);
732
733 ret = uart_add_one_port(&lpc32xx_hs_reg, &p->port);
734
735 platform_set_drvdata(pdev, p);
736
737 return ret;
738}
739
740/*
741 * Remove serial ports registered against a platform device.
742 */
743static int __devexit serial_hs_lpc32xx_remove(struct platform_device *pdev)
744{
745 struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
746
747 uart_remove_one_port(&lpc32xx_hs_reg, &p->port);
748
749 return 0;
750}
751
752
753#ifdef CONFIG_PM
754static int serial_hs_lpc32xx_suspend(struct platform_device *pdev,
755 pm_message_t state)
756{
757 struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
758
759 uart_suspend_port(&lpc32xx_hs_reg, &p->port);
760
761 return 0;
762}
763
764static int serial_hs_lpc32xx_resume(struct platform_device *pdev)
765{
766 struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
767
768 uart_resume_port(&lpc32xx_hs_reg, &p->port);
769
770 return 0;
771}
772#else
773#define serial_hs_lpc32xx_suspend NULL
774#define serial_hs_lpc32xx_resume NULL
775#endif
776
777static const struct of_device_id serial_hs_lpc32xx_dt_ids[] = {
778 { .compatible = "nxp,lpc3220-hsuart" },
779 { /* sentinel */ }
780};
781
782MODULE_DEVICE_TABLE(of, serial_hs_lpc32xx_dt_ids);
783
784static struct platform_driver serial_hs_lpc32xx_driver = {
785 .probe = serial_hs_lpc32xx_probe,
786 .remove = __devexit_p(serial_hs_lpc32xx_remove),
787 .suspend = serial_hs_lpc32xx_suspend,
788 .resume = serial_hs_lpc32xx_resume,
789 .driver = {
790 .name = MODNAME,
791 .owner = THIS_MODULE,
792 .of_match_table = serial_hs_lpc32xx_dt_ids,
793 },
794};
795
796static int __init lpc32xx_hsuart_init(void)
797{
798 int ret;
799
800 ret = uart_register_driver(&lpc32xx_hs_reg);
801 if (ret)
802 return ret;
803
804 ret = platform_driver_register(&serial_hs_lpc32xx_driver);
805 if (ret)
806 uart_unregister_driver(&lpc32xx_hs_reg);
807
808 return ret;
809}
810
811static void __exit lpc32xx_hsuart_exit(void)
812{
813 platform_driver_unregister(&serial_hs_lpc32xx_driver);
814 uart_unregister_driver(&lpc32xx_hs_reg);
815}
816
817module_init(lpc32xx_hsuart_init);
818module_exit(lpc32xx_hsuart_exit);
819
820MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
821MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
822MODULE_DESCRIPTION("NXP LPC32XX High Speed UART driver");
823MODULE_LICENSE("GPL");
diff --git a/drivers/tty/serial/m32r_sio.c b/drivers/tty/serial/m32r_sio.c
index a0703624d5e5..b13949ad3408 100644
--- a/drivers/tty/serial/m32r_sio.c
+++ b/drivers/tty/serial/m32r_sio.c
@@ -44,8 +44,6 @@
44#include <asm/io.h> 44#include <asm/io.h>
45#include <asm/irq.h> 45#include <asm/irq.h>
46 46
47#define PORT_M32R_BASE PORT_M32R_SIO
48#define PORT_INDEX(x) (x - PORT_M32R_BASE + 1)
49#define BAUD_RATE 115200 47#define BAUD_RATE 115200
50 48
51#include <linux/serial_core.h> 49#include <linux/serial_core.h>
@@ -132,22 +130,6 @@ struct irq_info {
132 130
133static struct irq_info irq_lists[NR_IRQS]; 131static struct irq_info irq_lists[NR_IRQS];
134 132
135/*
136 * Here we define the default xmit fifo size used for each type of UART.
137 */
138static const struct serial_uart_config uart_config[] = {
139 [PORT_UNKNOWN] = {
140 .name = "unknown",
141 .dfl_xmit_fifo_size = 1,
142 .flags = 0,
143 },
144 [PORT_INDEX(PORT_M32R_SIO)] = {
145 .name = "M32RSIO",
146 .dfl_xmit_fifo_size = 1,
147 .flags = 0,
148 },
149};
150
151#ifdef CONFIG_SERIAL_M32R_PLDSIO 133#ifdef CONFIG_SERIAL_M32R_PLDSIO
152 134
153#define __sio_in(x) inw((unsigned long)(x)) 135#define __sio_in(x) inw((unsigned long)(x))
@@ -907,8 +889,7 @@ static void m32r_sio_config_port(struct uart_port *port, int unused)
907 889
908 spin_lock_irqsave(&up->port.lock, flags); 890 spin_lock_irqsave(&up->port.lock, flags);
909 891
910 up->port.type = (PORT_M32R_SIO - PORT_M32R_BASE + 1); 892 up->port.fifosize = 1;
911 up->port.fifosize = uart_config[up->port.type].dfl_xmit_fifo_size;
912 893
913 spin_unlock_irqrestore(&up->port.lock, flags); 894 spin_unlock_irqrestore(&up->port.lock, flags);
914} 895}
@@ -916,23 +897,11 @@ static void m32r_sio_config_port(struct uart_port *port, int unused)
916static int 897static int
917m32r_sio_verify_port(struct uart_port *port, struct serial_struct *ser) 898m32r_sio_verify_port(struct uart_port *port, struct serial_struct *ser)
918{ 899{
919 if (ser->irq >= nr_irqs || ser->irq < 0 || 900 if (ser->irq >= nr_irqs || ser->irq < 0 || ser->baud_base < 9600)
920 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
921 ser->type >= ARRAY_SIZE(uart_config))
922 return -EINVAL; 901 return -EINVAL;
923 return 0; 902 return 0;
924} 903}
925 904
926static const char *
927m32r_sio_type(struct uart_port *port)
928{
929 int type = port->type;
930
931 if (type >= ARRAY_SIZE(uart_config))
932 type = 0;
933 return uart_config[type].name;
934}
935
936static struct uart_ops m32r_sio_pops = { 905static struct uart_ops m32r_sio_pops = {
937 .tx_empty = m32r_sio_tx_empty, 906 .tx_empty = m32r_sio_tx_empty,
938 .set_mctrl = m32r_sio_set_mctrl, 907 .set_mctrl = m32r_sio_set_mctrl,
@@ -946,7 +915,6 @@ static struct uart_ops m32r_sio_pops = {
946 .shutdown = m32r_sio_shutdown, 915 .shutdown = m32r_sio_shutdown,
947 .set_termios = m32r_sio_set_termios, 916 .set_termios = m32r_sio_set_termios,
948 .pm = m32r_sio_pm, 917 .pm = m32r_sio_pm,
949 .type = m32r_sio_type,
950 .release_port = m32r_sio_release_port, 918 .release_port = m32r_sio_release_port,
951 .request_port = m32r_sio_request_port, 919 .request_port = m32r_sio_request_port,
952 .config_port = m32r_sio_config_port, 920 .config_port = m32r_sio_config_port,
diff --git a/drivers/tty/serial/max3100.c b/drivers/tty/serial/max3100.c
index b4902b99cfd2..46043c2521ce 100644
--- a/drivers/tty/serial/max3100.c
+++ b/drivers/tty/serial/max3100.c
@@ -910,17 +910,7 @@ static struct spi_driver max3100_driver = {
910 .resume = max3100_resume, 910 .resume = max3100_resume,
911}; 911};
912 912
913static int __init max3100_init(void) 913module_spi_driver(max3100_driver);
914{
915 return spi_register_driver(&max3100_driver);
916}
917module_init(max3100_init);
918
919static void __exit max3100_exit(void)
920{
921 spi_unregister_driver(&max3100_driver);
922}
923module_exit(max3100_exit);
924 914
925MODULE_DESCRIPTION("MAX3100 driver"); 915MODULE_DESCRIPTION("MAX3100 driver");
926MODULE_AUTHOR("Christian Pellegrin <chripell@evolware.org>"); 916MODULE_AUTHOR("Christian Pellegrin <chripell@evolware.org>");
diff --git a/drivers/tty/serial/max3107.c b/drivers/tty/serial/max3107.c
deleted file mode 100644
index 17c7ba805d98..000000000000
--- a/drivers/tty/serial/max3107.c
+++ /dev/null
@@ -1,1215 +0,0 @@
1/*
2 * max3107.c - spi uart protocol driver for Maxim 3107
3 * Based on max3100.c
4 * by Christian Pellegrin <chripell@evolware.org>
5 * and max3110.c
6 * by Feng Tang <feng.tang@intel.com>
7 *
8 * Copyright (C) Aavamobile 2009
9 *
10 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
27 *
28 */
29
30#include <linux/delay.h>
31#include <linux/device.h>
32#include <linux/serial_core.h>
33#include <linux/serial.h>
34#include <linux/tty.h>
35#include <linux/tty_flip.h>
36#include <linux/gpio.h>
37#include <linux/spi/spi.h>
38#include <linux/freezer.h>
39#include <linux/module.h>
40#include "max3107.h"
41
42static const struct baud_table brg26_ext[] = {
43 { 300, MAX3107_BRG26_B300 },
44 { 600, MAX3107_BRG26_B600 },
45 { 1200, MAX3107_BRG26_B1200 },
46 { 2400, MAX3107_BRG26_B2400 },
47 { 4800, MAX3107_BRG26_B4800 },
48 { 9600, MAX3107_BRG26_B9600 },
49 { 19200, MAX3107_BRG26_B19200 },
50 { 57600, MAX3107_BRG26_B57600 },
51 { 115200, MAX3107_BRG26_B115200 },
52 { 230400, MAX3107_BRG26_B230400 },
53 { 460800, MAX3107_BRG26_B460800 },
54 { 921600, MAX3107_BRG26_B921600 },
55 { 0, 0 }
56};
57
58static const struct baud_table brg13_int[] = {
59 { 300, MAX3107_BRG13_IB300 },
60 { 600, MAX3107_BRG13_IB600 },
61 { 1200, MAX3107_BRG13_IB1200 },
62 { 2400, MAX3107_BRG13_IB2400 },
63 { 4800, MAX3107_BRG13_IB4800 },
64 { 9600, MAX3107_BRG13_IB9600 },
65 { 19200, MAX3107_BRG13_IB19200 },
66 { 57600, MAX3107_BRG13_IB57600 },
67 { 115200, MAX3107_BRG13_IB115200 },
68 { 230400, MAX3107_BRG13_IB230400 },
69 { 460800, MAX3107_BRG13_IB460800 },
70 { 921600, MAX3107_BRG13_IB921600 },
71 { 0, 0 }
72};
73
74static u32 get_new_brg(int baud, struct max3107_port *s)
75{
76 int i;
77 const struct baud_table *baud_tbl = s->baud_tbl;
78
79 for (i = 0; i < 13; i++) {
80 if (baud == baud_tbl[i].baud)
81 return baud_tbl[i].new_brg;
82 }
83
84 return 0;
85}
86
87/* Perform SPI transfer for write/read of device register(s) */
88int max3107_rw(struct max3107_port *s, u8 *tx, u8 *rx, int len)
89{
90 struct spi_message spi_msg;
91 struct spi_transfer spi_xfer;
92
93 /* Initialize SPI ,message */
94 spi_message_init(&spi_msg);
95
96 /* Initialize SPI transfer */
97 memset(&spi_xfer, 0, sizeof spi_xfer);
98 spi_xfer.len = len;
99 spi_xfer.tx_buf = tx;
100 spi_xfer.rx_buf = rx;
101 spi_xfer.speed_hz = MAX3107_SPI_SPEED;
102
103 /* Add SPI transfer to SPI message */
104 spi_message_add_tail(&spi_xfer, &spi_msg);
105
106#ifdef DBG_TRACE_SPI_DATA
107 {
108 int i;
109 pr_info("tx len %d:\n", spi_xfer.len);
110 for (i = 0 ; i < spi_xfer.len && i < 32 ; i++)
111 pr_info(" %x", ((u8 *)spi_xfer.tx_buf)[i]);
112 pr_info("\n");
113 }
114#endif
115
116 /* Perform synchronous SPI transfer */
117 if (spi_sync(s->spi, &spi_msg)) {
118 dev_err(&s->spi->dev, "spi_sync failure\n");
119 return -EIO;
120 }
121
122#ifdef DBG_TRACE_SPI_DATA
123 if (spi_xfer.rx_buf) {
124 int i;
125 pr_info("rx len %d:\n", spi_xfer.len);
126 for (i = 0 ; i < spi_xfer.len && i < 32 ; i++)
127 pr_info(" %x", ((u8 *)spi_xfer.rx_buf)[i]);
128 pr_info("\n");
129 }
130#endif
131 return 0;
132}
133EXPORT_SYMBOL_GPL(max3107_rw);
134
135/* Puts received data to circular buffer */
136static void put_data_to_circ_buf(struct max3107_port *s, unsigned char *data,
137 int len)
138{
139 struct uart_port *port = &s->port;
140 struct tty_struct *tty;
141
142 if (!port->state)
143 return;
144
145 tty = port->state->port.tty;
146 if (!tty)
147 return;
148
149 /* Insert received data */
150 tty_insert_flip_string(tty, data, len);
151 /* Update RX counter */
152 port->icount.rx += len;
153}
154
155/* Handle data receiving */
156static void max3107_handlerx(struct max3107_port *s, u16 rxlvl)
157{
158 int i;
159 int j;
160 int len; /* SPI transfer buffer length */
161 u16 *buf;
162 u8 *valid_str;
163
164 if (!s->rx_enabled)
165 /* RX is disabled */
166 return;
167
168 if (rxlvl == 0) {
169 /* RX fifo is empty */
170 return;
171 } else if (rxlvl >= MAX3107_RX_FIFO_SIZE) {
172 dev_warn(&s->spi->dev, "Possible RX FIFO overrun %d\n", rxlvl);
173 /* Ensure sanity of RX level */
174 rxlvl = MAX3107_RX_FIFO_SIZE;
175 }
176 if ((s->rxbuf == 0) || (s->rxstr == 0)) {
177 dev_warn(&s->spi->dev, "Rx buffer/str isn't ready\n");
178 return;
179 }
180 buf = s->rxbuf;
181 valid_str = s->rxstr;
182 while (rxlvl) {
183 pr_debug("rxlvl %d\n", rxlvl);
184 /* Clear buffer */
185 memset(buf, 0, sizeof(u16) * (MAX3107_RX_FIFO_SIZE + 2));
186 len = 0;
187 if (s->irqen_reg & MAX3107_IRQ_RXFIFO_BIT) {
188 /* First disable RX FIFO interrupt */
189 pr_debug("Disabling RX INT\n");
190 buf[0] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
191 s->irqen_reg &= ~MAX3107_IRQ_RXFIFO_BIT;
192 buf[0] |= s->irqen_reg;
193 len++;
194 }
195 /* Just increase the length by amount of words in FIFO since
196 * buffer was zeroed and SPI transfer of 0x0000 means reading
197 * from RX FIFO
198 */
199 len += rxlvl;
200 /* Append RX level query */
201 buf[len] = MAX3107_RXFIFOLVL_REG;
202 len++;
203
204 /* Perform the SPI transfer */
205 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, len * 2)) {
206 dev_err(&s->spi->dev, "SPI transfer for RX h failed\n");
207 return;
208 }
209
210 /* Skip RX FIFO interrupt disabling word if it was added */
211 j = ((len - 1) - rxlvl);
212 /* Read received words */
213 for (i = 0; i < rxlvl; i++, j++)
214 valid_str[i] = (u8)buf[j];
215 put_data_to_circ_buf(s, valid_str, rxlvl);
216 /* Get new RX level */
217 rxlvl = (buf[len - 1] & MAX3107_SPI_RX_DATA_MASK);
218 }
219
220 if (s->rx_enabled) {
221 /* RX still enabled, re-enable RX FIFO interrupt */
222 pr_debug("Enabling RX INT\n");
223 buf[0] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
224 s->irqen_reg |= MAX3107_IRQ_RXFIFO_BIT;
225 buf[0] |= s->irqen_reg;
226 if (max3107_rw(s, (u8 *)buf, NULL, 2))
227 dev_err(&s->spi->dev, "RX FIFO INT enabling failed\n");
228 }
229
230 /* Push the received data to receivers */
231 if (s->port.state->port.tty)
232 tty_flip_buffer_push(s->port.state->port.tty);
233}
234
235
236/* Handle data sending */
237static void max3107_handletx(struct max3107_port *s)
238{
239 struct circ_buf *xmit = &s->port.state->xmit;
240 int i;
241 unsigned long flags;
242 int len; /* SPI transfer buffer length */
243 u16 *buf;
244
245 if (!s->tx_fifo_empty)
246 /* Don't send more data before previous data is sent */
247 return;
248
249 if (uart_circ_empty(xmit) || uart_tx_stopped(&s->port))
250 /* No data to send or TX is stopped */
251 return;
252
253 if (!s->txbuf) {
254 dev_warn(&s->spi->dev, "Txbuf isn't ready\n");
255 return;
256 }
257 buf = s->txbuf;
258 /* Get length of data pending in circular buffer */
259 len = uart_circ_chars_pending(xmit);
260 if (len) {
261 /* Limit to size of TX FIFO */
262 if (len > MAX3107_TX_FIFO_SIZE)
263 len = MAX3107_TX_FIFO_SIZE;
264
265 pr_debug("txlen %d\n", len);
266
267 /* Update TX counter */
268 s->port.icount.tx += len;
269
270 /* TX FIFO will no longer be empty */
271 s->tx_fifo_empty = 0;
272
273 i = 0;
274 if (s->irqen_reg & MAX3107_IRQ_TXEMPTY_BIT) {
275 /* First disable TX empty interrupt */
276 pr_debug("Disabling TE INT\n");
277 buf[i] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
278 s->irqen_reg &= ~MAX3107_IRQ_TXEMPTY_BIT;
279 buf[i] |= s->irqen_reg;
280 i++;
281 len++;
282 }
283 /* Add data to send */
284 spin_lock_irqsave(&s->port.lock, flags);
285 for ( ; i < len ; i++) {
286 buf[i] = (MAX3107_WRITE_BIT | MAX3107_THR_REG);
287 buf[i] |= ((u16)xmit->buf[xmit->tail] &
288 MAX3107_SPI_TX_DATA_MASK);
289 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
290 }
291 spin_unlock_irqrestore(&s->port.lock, flags);
292 if (!(s->irqen_reg & MAX3107_IRQ_TXEMPTY_BIT)) {
293 /* Enable TX empty interrupt */
294 pr_debug("Enabling TE INT\n");
295 buf[i] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
296 s->irqen_reg |= MAX3107_IRQ_TXEMPTY_BIT;
297 buf[i] |= s->irqen_reg;
298 i++;
299 len++;
300 }
301 if (!s->tx_enabled) {
302 /* Enable TX */
303 pr_debug("Enable TX\n");
304 buf[i] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
305 spin_lock_irqsave(&s->data_lock, flags);
306 s->mode1_reg &= ~MAX3107_MODE1_TXDIS_BIT;
307 buf[i] |= s->mode1_reg;
308 spin_unlock_irqrestore(&s->data_lock, flags);
309 s->tx_enabled = 1;
310 i++;
311 len++;
312 }
313
314 /* Perform the SPI transfer */
315 if (max3107_rw(s, (u8 *)buf, NULL, len*2)) {
316 dev_err(&s->spi->dev,
317 "SPI transfer TX handling failed\n");
318 return;
319 }
320 }
321
322 /* Indicate wake up if circular buffer is getting low on data */
323 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
324 uart_write_wakeup(&s->port);
325
326}
327
328/* Handle interrupts
329 * Also reads and returns current RX FIFO level
330 */
331static u16 handle_interrupt(struct max3107_port *s)
332{
333 u16 buf[4]; /* Buffer for SPI transfers */
334 u8 irq_status;
335 u16 rx_level;
336 unsigned long flags;
337
338 /* Read IRQ status register */
339 buf[0] = MAX3107_IRQSTS_REG;
340 /* Read status IRQ status register */
341 buf[1] = MAX3107_STS_IRQSTS_REG;
342 /* Read LSR IRQ status register */
343 buf[2] = MAX3107_LSR_IRQSTS_REG;
344 /* Query RX level */
345 buf[3] = MAX3107_RXFIFOLVL_REG;
346
347 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 8)) {
348 dev_err(&s->spi->dev,
349 "SPI transfer for INTR handling failed\n");
350 return 0;
351 }
352
353 irq_status = (u8)buf[0];
354 pr_debug("IRQSTS %x\n", irq_status);
355 rx_level = (buf[3] & MAX3107_SPI_RX_DATA_MASK);
356
357 if (irq_status & MAX3107_IRQ_LSR_BIT) {
358 /* LSR interrupt */
359 if (buf[2] & MAX3107_LSR_RXTO_BIT)
360 /* RX timeout interrupt,
361 * handled by normal RX handling
362 */
363 pr_debug("RX TO INT\n");
364 }
365
366 if (irq_status & MAX3107_IRQ_TXEMPTY_BIT) {
367 /* Tx empty interrupt,
368 * disable TX and set tx_fifo_empty flag
369 */
370 pr_debug("TE INT, disabling TX\n");
371 buf[0] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
372 spin_lock_irqsave(&s->data_lock, flags);
373 s->mode1_reg |= MAX3107_MODE1_TXDIS_BIT;
374 buf[0] |= s->mode1_reg;
375 spin_unlock_irqrestore(&s->data_lock, flags);
376 if (max3107_rw(s, (u8 *)buf, NULL, 2))
377 dev_err(&s->spi->dev, "SPI transfer TX dis failed\n");
378 s->tx_enabled = 0;
379 s->tx_fifo_empty = 1;
380 }
381
382 if (irq_status & MAX3107_IRQ_RXFIFO_BIT)
383 /* RX FIFO interrupt,
384 * handled by normal RX handling
385 */
386 pr_debug("RFIFO INT\n");
387
388 /* Return RX level */
389 return rx_level;
390}
391
392/* Trigger work thread*/
393static void max3107_dowork(struct max3107_port *s)
394{
395 if (!work_pending(&s->work) && !freezing(current) && !s->suspended)
396 queue_work(s->workqueue, &s->work);
397 else
398 dev_warn(&s->spi->dev, "interrup isn't serviced normally!\n");
399}
400
401/* Work thread */
402static void max3107_work(struct work_struct *w)
403{
404 struct max3107_port *s = container_of(w, struct max3107_port, work);
405 u16 rxlvl = 0;
406 int len; /* SPI transfer buffer length */
407 u16 buf[5]; /* Buffer for SPI transfers */
408 unsigned long flags;
409
410 /* Start by reading current RX FIFO level */
411 buf[0] = MAX3107_RXFIFOLVL_REG;
412 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 2)) {
413 dev_err(&s->spi->dev, "SPI transfer RX lev failed\n");
414 rxlvl = 0;
415 } else {
416 rxlvl = (buf[0] & MAX3107_SPI_RX_DATA_MASK);
417 }
418
419 do {
420 pr_debug("rxlvl %d\n", rxlvl);
421
422 /* Handle RX */
423 max3107_handlerx(s, rxlvl);
424 rxlvl = 0;
425
426 if (s->handle_irq) {
427 /* Handle pending interrupts
428 * We also get new RX FIFO level since new data may
429 * have been received while pushing received data to
430 * receivers
431 */
432 s->handle_irq = 0;
433 rxlvl = handle_interrupt(s);
434 }
435
436 /* Handle TX */
437 max3107_handletx(s);
438
439 /* Handle configuration changes */
440 len = 0;
441 spin_lock_irqsave(&s->data_lock, flags);
442 if (s->mode1_commit) {
443 pr_debug("mode1_commit\n");
444 buf[len] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
445 buf[len++] |= s->mode1_reg;
446 s->mode1_commit = 0;
447 }
448 if (s->lcr_commit) {
449 pr_debug("lcr_commit\n");
450 buf[len] = (MAX3107_WRITE_BIT | MAX3107_LCR_REG);
451 buf[len++] |= s->lcr_reg;
452 s->lcr_commit = 0;
453 }
454 if (s->brg_commit) {
455 pr_debug("brg_commit\n");
456 buf[len] = (MAX3107_WRITE_BIT | MAX3107_BRGDIVMSB_REG);
457 buf[len++] |= ((s->brg_cfg >> 16) &
458 MAX3107_SPI_TX_DATA_MASK);
459 buf[len] = (MAX3107_WRITE_BIT | MAX3107_BRGDIVLSB_REG);
460 buf[len++] |= ((s->brg_cfg >> 8) &
461 MAX3107_SPI_TX_DATA_MASK);
462 buf[len] = (MAX3107_WRITE_BIT | MAX3107_BRGCFG_REG);
463 buf[len++] |= ((s->brg_cfg) & 0xff);
464 s->brg_commit = 0;
465 }
466 spin_unlock_irqrestore(&s->data_lock, flags);
467
468 if (len > 0) {
469 if (max3107_rw(s, (u8 *)buf, NULL, len * 2))
470 dev_err(&s->spi->dev,
471 "SPI transfer config failed\n");
472 }
473
474 /* Reloop if interrupt handling indicated data in RX FIFO */
475 } while (rxlvl);
476
477}
478
479/* Set sleep mode */
480static void max3107_set_sleep(struct max3107_port *s, int mode)
481{
482 u16 buf[1]; /* Buffer for SPI transfer */
483 unsigned long flags;
484 pr_debug("enter, mode %d\n", mode);
485
486 buf[0] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
487 spin_lock_irqsave(&s->data_lock, flags);
488 switch (mode) {
489 case MAX3107_DISABLE_FORCED_SLEEP:
490 s->mode1_reg &= ~MAX3107_MODE1_FORCESLEEP_BIT;
491 break;
492 case MAX3107_ENABLE_FORCED_SLEEP:
493 s->mode1_reg |= MAX3107_MODE1_FORCESLEEP_BIT;
494 break;
495 case MAX3107_DISABLE_AUTOSLEEP:
496 s->mode1_reg &= ~MAX3107_MODE1_AUTOSLEEP_BIT;
497 break;
498 case MAX3107_ENABLE_AUTOSLEEP:
499 s->mode1_reg |= MAX3107_MODE1_AUTOSLEEP_BIT;
500 break;
501 default:
502 spin_unlock_irqrestore(&s->data_lock, flags);
503 dev_warn(&s->spi->dev, "invalid sleep mode\n");
504 return;
505 }
506 buf[0] |= s->mode1_reg;
507 spin_unlock_irqrestore(&s->data_lock, flags);
508
509 if (max3107_rw(s, (u8 *)buf, NULL, 2))
510 dev_err(&s->spi->dev, "SPI transfer sleep mode failed\n");
511
512 if (mode == MAX3107_DISABLE_AUTOSLEEP ||
513 mode == MAX3107_DISABLE_FORCED_SLEEP)
514 msleep(MAX3107_WAKEUP_DELAY);
515}
516
517/* Perform full register initialization */
518static void max3107_register_init(struct max3107_port *s)
519{
520 u16 buf[11]; /* Buffer for SPI transfers */
521
522 /* 1. Configure baud rate, 9600 as default */
523 s->baud = 9600;
524 /* the below is default*/
525 if (s->ext_clk) {
526 s->brg_cfg = MAX3107_BRG26_B9600;
527 s->baud_tbl = (struct baud_table *)brg26_ext;
528 } else {
529 s->brg_cfg = MAX3107_BRG13_IB9600;
530 s->baud_tbl = (struct baud_table *)brg13_int;
531 }
532
533 if (s->pdata->init)
534 s->pdata->init(s);
535
536 buf[0] = (MAX3107_WRITE_BIT | MAX3107_BRGDIVMSB_REG)
537 | ((s->brg_cfg >> 16) & MAX3107_SPI_TX_DATA_MASK);
538 buf[1] = (MAX3107_WRITE_BIT | MAX3107_BRGDIVLSB_REG)
539 | ((s->brg_cfg >> 8) & MAX3107_SPI_TX_DATA_MASK);
540 buf[2] = (MAX3107_WRITE_BIT | MAX3107_BRGCFG_REG)
541 | ((s->brg_cfg) & 0xff);
542
543 /* 2. Configure LCR register, 8N1 mode by default */
544 s->lcr_reg = MAX3107_LCR_WORD_LEN_8;
545 buf[3] = (MAX3107_WRITE_BIT | MAX3107_LCR_REG)
546 | s->lcr_reg;
547
548 /* 3. Configure MODE 1 register */
549 s->mode1_reg = 0;
550 /* Enable IRQ pin */
551 s->mode1_reg |= MAX3107_MODE1_IRQSEL_BIT;
552 /* Disable TX */
553 s->mode1_reg |= MAX3107_MODE1_TXDIS_BIT;
554 s->tx_enabled = 0;
555 /* RX is enabled */
556 s->rx_enabled = 1;
557 buf[4] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG)
558 | s->mode1_reg;
559
560 /* 4. Configure MODE 2 register */
561 buf[5] = (MAX3107_WRITE_BIT | MAX3107_MODE2_REG);
562 if (s->loopback) {
563 /* Enable loopback */
564 buf[5] |= MAX3107_MODE2_LOOPBACK_BIT;
565 }
566 /* Reset FIFOs */
567 buf[5] |= MAX3107_MODE2_FIFORST_BIT;
568 s->tx_fifo_empty = 1;
569
570 /* 5. Configure FIFO trigger level register */
571 buf[6] = (MAX3107_WRITE_BIT | MAX3107_FIFOTRIGLVL_REG);
572 /* RX FIFO trigger for 16 words, TX FIFO trigger not used */
573 buf[6] |= (MAX3107_FIFOTRIGLVL_RX(16) | MAX3107_FIFOTRIGLVL_TX(0));
574
575 /* 6. Configure flow control levels */
576 buf[7] = (MAX3107_WRITE_BIT | MAX3107_FLOWLVL_REG);
577 /* Flow control halt level 96, resume level 48 */
578 buf[7] |= (MAX3107_FLOWLVL_RES(48) | MAX3107_FLOWLVL_HALT(96));
579
580 /* 7. Configure flow control */
581 buf[8] = (MAX3107_WRITE_BIT | MAX3107_FLOWCTRL_REG);
582 /* Enable auto CTS and auto RTS flow control */
583 buf[8] |= (MAX3107_FLOWCTRL_AUTOCTS_BIT | MAX3107_FLOWCTRL_AUTORTS_BIT);
584
585 /* 8. Configure RX timeout register */
586 buf[9] = (MAX3107_WRITE_BIT | MAX3107_RXTO_REG);
587 /* Timeout after 48 character intervals */
588 buf[9] |= 0x0030;
589
590 /* 9. Configure LSR interrupt enable register */
591 buf[10] = (MAX3107_WRITE_BIT | MAX3107_LSR_IRQEN_REG);
592 /* Enable RX timeout interrupt */
593 buf[10] |= MAX3107_LSR_RXTO_BIT;
594
595 /* Perform SPI transfer */
596 if (max3107_rw(s, (u8 *)buf, NULL, 22))
597 dev_err(&s->spi->dev, "SPI transfer for init failed\n");
598
599 /* 10. Clear IRQ status register by reading it */
600 buf[0] = MAX3107_IRQSTS_REG;
601
602 /* 11. Configure interrupt enable register */
603 /* Enable LSR interrupt */
604 s->irqen_reg = MAX3107_IRQ_LSR_BIT;
605 /* Enable RX FIFO interrupt */
606 s->irqen_reg |= MAX3107_IRQ_RXFIFO_BIT;
607 buf[1] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG)
608 | s->irqen_reg;
609
610 /* 12. Clear FIFO reset that was set in step 6 */
611 buf[2] = (MAX3107_WRITE_BIT | MAX3107_MODE2_REG);
612 if (s->loopback) {
613 /* Keep loopback enabled */
614 buf[2] |= MAX3107_MODE2_LOOPBACK_BIT;
615 }
616
617 /* Perform SPI transfer */
618 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 6))
619 dev_err(&s->spi->dev, "SPI transfer for init failed\n");
620
621}
622
623/* IRQ handler */
624static irqreturn_t max3107_irq(int irqno, void *dev_id)
625{
626 struct max3107_port *s = dev_id;
627
628 if (irqno != s->spi->irq) {
629 /* Unexpected IRQ */
630 return IRQ_NONE;
631 }
632
633 /* Indicate irq */
634 s->handle_irq = 1;
635
636 /* Trigger work thread */
637 max3107_dowork(s);
638
639 return IRQ_HANDLED;
640}
641
642/* HW suspension function
643 *
644 * Currently autosleep is used to decrease current consumption, alternative
645 * approach would be to set the chip to reset mode if UART is not being
646 * used but that would mess the GPIOs
647 *
648 */
649void max3107_hw_susp(struct max3107_port *s, int suspend)
650{
651 pr_debug("enter, suspend %d\n", suspend);
652
653 if (suspend) {
654 /* Suspend requested,
655 * enable autosleep to decrease current consumption
656 */
657 s->suspended = 1;
658 max3107_set_sleep(s, MAX3107_ENABLE_AUTOSLEEP);
659 } else {
660 /* Resume requested,
661 * disable autosleep
662 */
663 s->suspended = 0;
664 max3107_set_sleep(s, MAX3107_DISABLE_AUTOSLEEP);
665 }
666}
667EXPORT_SYMBOL_GPL(max3107_hw_susp);
668
669/* Modem status IRQ enabling */
670static void max3107_enable_ms(struct uart_port *port)
671{
672 /* Modem status not supported */
673}
674
675/* Data send function */
676static void max3107_start_tx(struct uart_port *port)
677{
678 struct max3107_port *s = container_of(port, struct max3107_port, port);
679
680 /* Trigger work thread for sending data */
681 max3107_dowork(s);
682}
683
684/* Function for checking that there is no pending transfers */
685static unsigned int max3107_tx_empty(struct uart_port *port)
686{
687 struct max3107_port *s = container_of(port, struct max3107_port, port);
688
689 pr_debug("returning %d\n",
690 (s->tx_fifo_empty && uart_circ_empty(&s->port.state->xmit)));
691 return s->tx_fifo_empty && uart_circ_empty(&s->port.state->xmit);
692}
693
694/* Function for stopping RX */
695static void max3107_stop_rx(struct uart_port *port)
696{
697 struct max3107_port *s = container_of(port, struct max3107_port, port);
698 unsigned long flags;
699
700 /* Set RX disabled in MODE 1 register */
701 spin_lock_irqsave(&s->data_lock, flags);
702 s->mode1_reg |= MAX3107_MODE1_RXDIS_BIT;
703 s->mode1_commit = 1;
704 spin_unlock_irqrestore(&s->data_lock, flags);
705 /* Set RX disabled */
706 s->rx_enabled = 0;
707 /* Trigger work thread for doing the actual configuration change */
708 max3107_dowork(s);
709}
710
711/* Function for returning control pin states */
712static unsigned int max3107_get_mctrl(struct uart_port *port)
713{
714 /* DCD and DSR are not wired and CTS/RTS is handled automatically
715 * so just indicate DSR and CAR asserted
716 */
717 return TIOCM_DSR | TIOCM_CAR;
718}
719
720/* Function for setting control pin states */
721static void max3107_set_mctrl(struct uart_port *port, unsigned int mctrl)
722{
723 /* DCD and DSR are not wired and CTS/RTS is hadnled automatically
724 * so do nothing
725 */
726}
727
728/* Function for configuring UART parameters */
729static void max3107_set_termios(struct uart_port *port,
730 struct ktermios *termios,
731 struct ktermios *old)
732{
733 struct max3107_port *s = container_of(port, struct max3107_port, port);
734 struct tty_struct *tty;
735 int baud;
736 u16 new_lcr = 0;
737 u32 new_brg = 0;
738 unsigned long flags;
739
740 if (!port->state)
741 return;
742
743 tty = port->state->port.tty;
744 if (!tty)
745 return;
746
747 /* Get new LCR register values */
748 /* Word size */
749 if ((termios->c_cflag & CSIZE) == CS7)
750 new_lcr |= MAX3107_LCR_WORD_LEN_7;
751 else
752 new_lcr |= MAX3107_LCR_WORD_LEN_8;
753
754 /* Parity */
755 if (termios->c_cflag & PARENB) {
756 new_lcr |= MAX3107_LCR_PARITY_BIT;
757 if (!(termios->c_cflag & PARODD))
758 new_lcr |= MAX3107_LCR_EVENPARITY_BIT;
759 }
760
761 /* Stop bits */
762 if (termios->c_cflag & CSTOPB) {
763 /* 2 stop bits */
764 new_lcr |= MAX3107_LCR_STOPLEN_BIT;
765 }
766
767 /* Mask termios capabilities we don't support */
768 termios->c_cflag &= ~CMSPAR;
769
770 /* Set status ignore mask */
771 s->port.ignore_status_mask = 0;
772 if (termios->c_iflag & IGNPAR)
773 s->port.ignore_status_mask |= MAX3107_ALL_ERRORS;
774
775 /* Set low latency to immediately handle pushed data */
776 s->port.state->port.tty->low_latency = 1;
777
778 /* Get new baud rate generator configuration */
779 baud = tty_get_baud_rate(tty);
780
781 spin_lock_irqsave(&s->data_lock, flags);
782 new_brg = get_new_brg(baud, s);
783 /* if can't find the corrent config, use previous */
784 if (!new_brg) {
785 baud = s->baud;
786 new_brg = s->brg_cfg;
787 }
788 spin_unlock_irqrestore(&s->data_lock, flags);
789 tty_termios_encode_baud_rate(termios, baud, baud);
790 s->baud = baud;
791
792 /* Update timeout according to new baud rate */
793 uart_update_timeout(port, termios->c_cflag, baud);
794
795 spin_lock_irqsave(&s->data_lock, flags);
796 if (s->lcr_reg != new_lcr) {
797 s->lcr_reg = new_lcr;
798 s->lcr_commit = 1;
799 }
800 if (s->brg_cfg != new_brg) {
801 s->brg_cfg = new_brg;
802 s->brg_commit = 1;
803 }
804 spin_unlock_irqrestore(&s->data_lock, flags);
805
806 /* Trigger work thread for doing the actual configuration change */
807 max3107_dowork(s);
808}
809
810/* Port shutdown function */
811static void max3107_shutdown(struct uart_port *port)
812{
813 struct max3107_port *s = container_of(port, struct max3107_port, port);
814
815 if (s->suspended && s->pdata->hw_suspend)
816 s->pdata->hw_suspend(s, 0);
817
818 /* Free the interrupt */
819 free_irq(s->spi->irq, s);
820
821 if (s->workqueue) {
822 /* Flush and destroy work queue */
823 flush_workqueue(s->workqueue);
824 destroy_workqueue(s->workqueue);
825 s->workqueue = NULL;
826 }
827
828 /* Suspend HW */
829 if (s->pdata->hw_suspend)
830 s->pdata->hw_suspend(s, 1);
831}
832
833/* Port startup function */
834static int max3107_startup(struct uart_port *port)
835{
836 struct max3107_port *s = container_of(port, struct max3107_port, port);
837
838 /* Initialize work queue */
839 s->workqueue = create_freezable_workqueue("max3107");
840 if (!s->workqueue) {
841 dev_err(&s->spi->dev, "Workqueue creation failed\n");
842 return -EBUSY;
843 }
844 INIT_WORK(&s->work, max3107_work);
845
846 /* Setup IRQ */
847 if (request_irq(s->spi->irq, max3107_irq, IRQF_TRIGGER_FALLING,
848 "max3107", s)) {
849 dev_err(&s->spi->dev, "IRQ reguest failed\n");
850 destroy_workqueue(s->workqueue);
851 s->workqueue = NULL;
852 return -EBUSY;
853 }
854
855 /* Resume HW */
856 if (s->pdata->hw_suspend)
857 s->pdata->hw_suspend(s, 0);
858
859 /* Init registers */
860 max3107_register_init(s);
861
862 return 0;
863}
864
865/* Port type function */
866static const char *max3107_type(struct uart_port *port)
867{
868 struct max3107_port *s = container_of(port, struct max3107_port, port);
869 return s->spi->modalias;
870}
871
872/* Port release function */
873static void max3107_release_port(struct uart_port *port)
874{
875 /* Do nothing */
876}
877
878/* Port request function */
879static int max3107_request_port(struct uart_port *port)
880{
881 /* Do nothing */
882 return 0;
883}
884
885/* Port config function */
886static void max3107_config_port(struct uart_port *port, int flags)
887{
888 struct max3107_port *s = container_of(port, struct max3107_port, port);
889 s->port.type = PORT_MAX3107;
890}
891
892/* Port verify function */
893static int max3107_verify_port(struct uart_port *port,
894 struct serial_struct *ser)
895{
896 if (ser->type == PORT_UNKNOWN || ser->type == PORT_MAX3107)
897 return 0;
898
899 return -EINVAL;
900}
901
902/* Port stop TX function */
903static void max3107_stop_tx(struct uart_port *port)
904{
905 /* Do nothing */
906}
907
908/* Port break control function */
909static void max3107_break_ctl(struct uart_port *port, int break_state)
910{
911 /* We don't support break control, do nothing */
912}
913
914
915/* Port functions */
916static struct uart_ops max3107_ops = {
917 .tx_empty = max3107_tx_empty,
918 .set_mctrl = max3107_set_mctrl,
919 .get_mctrl = max3107_get_mctrl,
920 .stop_tx = max3107_stop_tx,
921 .start_tx = max3107_start_tx,
922 .stop_rx = max3107_stop_rx,
923 .enable_ms = max3107_enable_ms,
924 .break_ctl = max3107_break_ctl,
925 .startup = max3107_startup,
926 .shutdown = max3107_shutdown,
927 .set_termios = max3107_set_termios,
928 .type = max3107_type,
929 .release_port = max3107_release_port,
930 .request_port = max3107_request_port,
931 .config_port = max3107_config_port,
932 .verify_port = max3107_verify_port,
933};
934
935/* UART driver data */
936static struct uart_driver max3107_uart_driver = {
937 .owner = THIS_MODULE,
938 .driver_name = "ttyMAX",
939 .dev_name = "ttyMAX",
940 .nr = 1,
941};
942
943static int driver_registered = 0;
944
945
946
947/* 'Generic' platform data */
948static struct max3107_plat generic_plat_data = {
949 .loopback = 0,
950 .ext_clk = 1,
951 .hw_suspend = max3107_hw_susp,
952 .polled_mode = 0,
953 .poll_time = 0,
954};
955
956
957/*******************************************************************/
958
959/**
960 * max3107_probe - SPI bus probe entry point
961 * @spi: the spi device
962 *
963 * SPI wants us to probe this device and if appropriate claim it.
964 * Perform any platform specific requirements and then initialise
965 * the device.
966 */
967
968int max3107_probe(struct spi_device *spi, struct max3107_plat *pdata)
969{
970 struct max3107_port *s;
971 u16 buf[2]; /* Buffer for SPI transfers */
972 int retval;
973
974 pr_info("enter max3107 probe\n");
975
976 /* Allocate port structure */
977 s = kzalloc(sizeof(*s), GFP_KERNEL);
978 if (!s) {
979 pr_err("Allocating port structure failed\n");
980 return -ENOMEM;
981 }
982
983 s->pdata = pdata;
984
985 /* SPI Rx buffer
986 * +2 for RX FIFO interrupt
987 * disabling and RX level query
988 */
989 s->rxbuf = kzalloc(sizeof(u16) * (MAX3107_RX_FIFO_SIZE+2), GFP_KERNEL);
990 if (!s->rxbuf) {
991 pr_err("Allocating RX buffer failed\n");
992 retval = -ENOMEM;
993 goto err_free4;
994 }
995 s->rxstr = kzalloc(sizeof(u8) * MAX3107_RX_FIFO_SIZE, GFP_KERNEL);
996 if (!s->rxstr) {
997 pr_err("Allocating RX buffer failed\n");
998 retval = -ENOMEM;
999 goto err_free3;
1000 }
1001 /* SPI Tx buffer
1002 * SPI transfer buffer
1003 * +3 for TX FIFO empty
1004 * interrupt disabling and
1005 * enabling and TX enabling
1006 */
1007 s->txbuf = kzalloc(sizeof(u16) * MAX3107_TX_FIFO_SIZE + 3, GFP_KERNEL);
1008 if (!s->txbuf) {
1009 pr_err("Allocating TX buffer failed\n");
1010 retval = -ENOMEM;
1011 goto err_free2;
1012 }
1013 /* Initialize shared data lock */
1014 spin_lock_init(&s->data_lock);
1015
1016 /* SPI intializations */
1017 dev_set_drvdata(&spi->dev, s);
1018 spi->mode = SPI_MODE_0;
1019 spi->dev.platform_data = pdata;
1020 spi->bits_per_word = 16;
1021 s->ext_clk = pdata->ext_clk;
1022 s->loopback = pdata->loopback;
1023 spi_setup(spi);
1024 s->spi = spi;
1025
1026 /* Check REV ID to ensure we are talking to what we expect */
1027 buf[0] = MAX3107_REVID_REG;
1028 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 2)) {
1029 dev_err(&s->spi->dev, "SPI transfer for REVID read failed\n");
1030 retval = -EIO;
1031 goto err_free1;
1032 }
1033 if ((buf[0] & MAX3107_SPI_RX_DATA_MASK) != MAX3107_REVID1 &&
1034 (buf[0] & MAX3107_SPI_RX_DATA_MASK) != MAX3107_REVID2) {
1035 dev_err(&s->spi->dev, "REVID %x does not match\n",
1036 (buf[0] & MAX3107_SPI_RX_DATA_MASK));
1037 retval = -ENODEV;
1038 goto err_free1;
1039 }
1040
1041 /* Disable all interrupts */
1042 buf[0] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG | 0x0000);
1043 buf[0] |= 0x0000;
1044
1045 /* Configure clock source */
1046 buf[1] = (MAX3107_WRITE_BIT | MAX3107_CLKSRC_REG);
1047 if (s->ext_clk) {
1048 /* External clock */
1049 buf[1] |= MAX3107_CLKSRC_EXTCLK_BIT;
1050 }
1051
1052 /* PLL bypass ON */
1053 buf[1] |= MAX3107_CLKSRC_PLLBYP_BIT;
1054
1055 /* Perform SPI transfer */
1056 if (max3107_rw(s, (u8 *)buf, NULL, 4)) {
1057 dev_err(&s->spi->dev, "SPI transfer for init failed\n");
1058 retval = -EIO;
1059 goto err_free1;
1060 }
1061
1062 /* Register UART driver */
1063 if (!driver_registered) {
1064 retval = uart_register_driver(&max3107_uart_driver);
1065 if (retval) {
1066 dev_err(&s->spi->dev, "Registering UART driver failed\n");
1067 goto err_free1;
1068 }
1069 driver_registered = 1;
1070 }
1071
1072 /* Initialize UART port data */
1073 s->port.fifosize = 128;
1074 s->port.ops = &max3107_ops;
1075 s->port.line = 0;
1076 s->port.dev = &spi->dev;
1077 s->port.uartclk = 9600;
1078 s->port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF;
1079 s->port.irq = s->spi->irq;
1080 s->port.type = PORT_MAX3107;
1081
1082 /* Add UART port */
1083 retval = uart_add_one_port(&max3107_uart_driver, &s->port);
1084 if (retval < 0) {
1085 dev_err(&s->spi->dev, "Adding UART port failed\n");
1086 goto err_free1;
1087 }
1088
1089 if (pdata->configure) {
1090 retval = pdata->configure(s);
1091 if (retval < 0)
1092 goto err_free1;
1093 }
1094
1095 /* Go to suspend mode */
1096 if (pdata->hw_suspend)
1097 pdata->hw_suspend(s, 1);
1098
1099 return 0;
1100
1101err_free1:
1102 kfree(s->txbuf);
1103err_free2:
1104 kfree(s->rxstr);
1105err_free3:
1106 kfree(s->rxbuf);
1107err_free4:
1108 kfree(s);
1109 return retval;
1110}
1111EXPORT_SYMBOL_GPL(max3107_probe);
1112
1113/* Driver remove function */
1114int max3107_remove(struct spi_device *spi)
1115{
1116 struct max3107_port *s = dev_get_drvdata(&spi->dev);
1117
1118 pr_info("enter max3107 remove\n");
1119
1120 /* Remove port */
1121 if (uart_remove_one_port(&max3107_uart_driver, &s->port))
1122 dev_warn(&s->spi->dev, "Removing UART port failed\n");
1123
1124
1125 /* Free TxRx buffer */
1126 kfree(s->rxbuf);
1127 kfree(s->rxstr);
1128 kfree(s->txbuf);
1129
1130 /* Free port structure */
1131 kfree(s);
1132
1133 return 0;
1134}
1135EXPORT_SYMBOL_GPL(max3107_remove);
1136
1137/* Driver suspend function */
1138int max3107_suspend(struct spi_device *spi, pm_message_t state)
1139{
1140#ifdef CONFIG_PM
1141 struct max3107_port *s = dev_get_drvdata(&spi->dev);
1142
1143 pr_debug("enter suspend\n");
1144
1145 /* Suspend UART port */
1146 uart_suspend_port(&max3107_uart_driver, &s->port);
1147
1148 /* Go to suspend mode */
1149 if (s->pdata->hw_suspend)
1150 s->pdata->hw_suspend(s, 1);
1151#endif /* CONFIG_PM */
1152 return 0;
1153}
1154EXPORT_SYMBOL_GPL(max3107_suspend);
1155
1156/* Driver resume function */
1157int max3107_resume(struct spi_device *spi)
1158{
1159#ifdef CONFIG_PM
1160 struct max3107_port *s = dev_get_drvdata(&spi->dev);
1161
1162 pr_debug("enter resume\n");
1163
1164 /* Resume from suspend */
1165 if (s->pdata->hw_suspend)
1166 s->pdata->hw_suspend(s, 0);
1167
1168 /* Resume UART port */
1169 uart_resume_port(&max3107_uart_driver, &s->port);
1170#endif /* CONFIG_PM */
1171 return 0;
1172}
1173EXPORT_SYMBOL_GPL(max3107_resume);
1174
1175static int max3107_probe_generic(struct spi_device *spi)
1176{
1177 return max3107_probe(spi, &generic_plat_data);
1178}
1179
1180/* Spi driver data */
1181static struct spi_driver max3107_driver = {
1182 .driver = {
1183 .name = "max3107",
1184 .owner = THIS_MODULE,
1185 },
1186 .probe = max3107_probe_generic,
1187 .remove = __devexit_p(max3107_remove),
1188 .suspend = max3107_suspend,
1189 .resume = max3107_resume,
1190};
1191
1192/* Driver init function */
1193static int __init max3107_init(void)
1194{
1195 pr_info("enter max3107 init\n");
1196 return spi_register_driver(&max3107_driver);
1197}
1198
1199/* Driver exit function */
1200static void __exit max3107_exit(void)
1201{
1202 pr_info("enter max3107 exit\n");
1203 /* Unregister UART driver */
1204 if (driver_registered)
1205 uart_unregister_driver(&max3107_uart_driver);
1206 spi_unregister_driver(&max3107_driver);
1207}
1208
1209module_init(max3107_init);
1210module_exit(max3107_exit);
1211
1212MODULE_DESCRIPTION("MAX3107 driver");
1213MODULE_AUTHOR("Aavamobile");
1214MODULE_ALIAS("spi:max3107");
1215MODULE_LICENSE("GPL v2");
diff --git a/drivers/tty/serial/max3107.h b/drivers/tty/serial/max3107.h
deleted file mode 100644
index 8415fc723b96..000000000000
--- a/drivers/tty/serial/max3107.h
+++ /dev/null
@@ -1,441 +0,0 @@
1/*
2 * max3107.h - spi uart protocol driver header for Maxim 3107
3 *
4 * Copyright (C) Aavamobile 2009
5 * Based on serial_max3100.h by Christian Pellegrin
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#ifndef _MAX3107_H
14#define _MAX3107_H
15
16/* Serial error status definitions */
17#define MAX3107_PARITY_ERROR 1
18#define MAX3107_FRAME_ERROR 2
19#define MAX3107_OVERRUN_ERROR 4
20#define MAX3107_ALL_ERRORS (MAX3107_PARITY_ERROR | \
21 MAX3107_FRAME_ERROR | \
22 MAX3107_OVERRUN_ERROR)
23
24/* GPIO definitions */
25#define MAX3107_GPIO_BASE 88
26#define MAX3107_GPIO_COUNT 4
27
28
29/* GPIO connected to chip's reset pin */
30#define MAX3107_RESET_GPIO 87
31
32
33/* Chip reset delay */
34#define MAX3107_RESET_DELAY 10
35
36/* Chip wakeup delay */
37#define MAX3107_WAKEUP_DELAY 50
38
39
40/* Sleep mode definitions */
41#define MAX3107_DISABLE_FORCED_SLEEP 0
42#define MAX3107_ENABLE_FORCED_SLEEP 1
43#define MAX3107_DISABLE_AUTOSLEEP 2
44#define MAX3107_ENABLE_AUTOSLEEP 3
45
46
47/* Definitions for register access with SPI transfers
48 *
49 * SPI transfer format:
50 *
51 * Master to slave bits xzzzzzzzyyyyyyyy
52 * Slave to master bits aaaaaaaabbbbbbbb
53 *
54 * where:
55 * x = 0 for reads, 1 for writes
56 * z = register address
57 * y = new register value if write, 0 if read
58 * a = unspecified
59 * b = register value if read, unspecified if write
60 */
61
62/* SPI speed */
63#define MAX3107_SPI_SPEED (3125000 * 2)
64
65/* Write bit */
66#define MAX3107_WRITE_BIT (1 << 15)
67
68/* SPI TX data mask */
69#define MAX3107_SPI_RX_DATA_MASK (0x00ff)
70
71/* SPI RX data mask */
72#define MAX3107_SPI_TX_DATA_MASK (0x00ff)
73
74/* Register access masks */
75#define MAX3107_RHR_REG (0x0000) /* RX FIFO */
76#define MAX3107_THR_REG (0x0000) /* TX FIFO */
77#define MAX3107_IRQEN_REG (0x0100) /* IRQ enable */
78#define MAX3107_IRQSTS_REG (0x0200) /* IRQ status */
79#define MAX3107_LSR_IRQEN_REG (0x0300) /* LSR IRQ enable */
80#define MAX3107_LSR_IRQSTS_REG (0x0400) /* LSR IRQ status */
81#define MAX3107_SPCHR_IRQEN_REG (0x0500) /* Special char IRQ enable */
82#define MAX3107_SPCHR_IRQSTS_REG (0x0600) /* Special char IRQ status */
83#define MAX3107_STS_IRQEN_REG (0x0700) /* Status IRQ enable */
84#define MAX3107_STS_IRQSTS_REG (0x0800) /* Status IRQ status */
85#define MAX3107_MODE1_REG (0x0900) /* MODE1 */
86#define MAX3107_MODE2_REG (0x0a00) /* MODE2 */
87#define MAX3107_LCR_REG (0x0b00) /* LCR */
88#define MAX3107_RXTO_REG (0x0c00) /* RX timeout */
89#define MAX3107_HDPIXDELAY_REG (0x0d00) /* Auto transceiver delays */
90#define MAX3107_IRDA_REG (0x0e00) /* IRDA settings */
91#define MAX3107_FLOWLVL_REG (0x0f00) /* Flow control levels */
92#define MAX3107_FIFOTRIGLVL_REG (0x1000) /* FIFO IRQ trigger levels */
93#define MAX3107_TXFIFOLVL_REG (0x1100) /* TX FIFO level */
94#define MAX3107_RXFIFOLVL_REG (0x1200) /* RX FIFO level */
95#define MAX3107_FLOWCTRL_REG (0x1300) /* Flow control */
96#define MAX3107_XON1_REG (0x1400) /* XON1 character */
97#define MAX3107_XON2_REG (0x1500) /* XON2 character */
98#define MAX3107_XOFF1_REG (0x1600) /* XOFF1 character */
99#define MAX3107_XOFF2_REG (0x1700) /* XOFF2 character */
100#define MAX3107_GPIOCFG_REG (0x1800) /* GPIO config */
101#define MAX3107_GPIODATA_REG (0x1900) /* GPIO data */
102#define MAX3107_PLLCFG_REG (0x1a00) /* PLL config */
103#define MAX3107_BRGCFG_REG (0x1b00) /* Baud rate generator conf */
104#define MAX3107_BRGDIVLSB_REG (0x1c00) /* Baud rate divisor LSB */
105#define MAX3107_BRGDIVMSB_REG (0x1d00) /* Baud rate divisor MSB */
106#define MAX3107_CLKSRC_REG (0x1e00) /* Clock source */
107#define MAX3107_REVID_REG (0x1f00) /* Revision identification */
108
109/* IRQ register bits */
110#define MAX3107_IRQ_LSR_BIT (1 << 0) /* LSR interrupt */
111#define MAX3107_IRQ_SPCHR_BIT (1 << 1) /* Special char interrupt */
112#define MAX3107_IRQ_STS_BIT (1 << 2) /* Status interrupt */
113#define MAX3107_IRQ_RXFIFO_BIT (1 << 3) /* RX FIFO interrupt */
114#define MAX3107_IRQ_TXFIFO_BIT (1 << 4) /* TX FIFO interrupt */
115#define MAX3107_IRQ_TXEMPTY_BIT (1 << 5) /* TX FIFO empty interrupt */
116#define MAX3107_IRQ_RXEMPTY_BIT (1 << 6) /* RX FIFO empty interrupt */
117#define MAX3107_IRQ_CTS_BIT (1 << 7) /* CTS interrupt */
118
119/* LSR register bits */
120#define MAX3107_LSR_RXTO_BIT (1 << 0) /* RX timeout */
121#define MAX3107_LSR_RXOVR_BIT (1 << 1) /* RX overrun */
122#define MAX3107_LSR_RXPAR_BIT (1 << 2) /* RX parity error */
123#define MAX3107_LSR_FRERR_BIT (1 << 3) /* Frame error */
124#define MAX3107_LSR_RXBRK_BIT (1 << 4) /* RX break */
125#define MAX3107_LSR_RXNOISE_BIT (1 << 5) /* RX noise */
126#define MAX3107_LSR_UNDEF6_BIT (1 << 6) /* Undefined/not used */
127#define MAX3107_LSR_CTS_BIT (1 << 7) /* CTS pin state */
128
129/* Special character register bits */
130#define MAX3107_SPCHR_XON1_BIT (1 << 0) /* XON1 character */
131#define MAX3107_SPCHR_XON2_BIT (1 << 1) /* XON2 character */
132#define MAX3107_SPCHR_XOFF1_BIT (1 << 2) /* XOFF1 character */
133#define MAX3107_SPCHR_XOFF2_BIT (1 << 3) /* XOFF2 character */
134#define MAX3107_SPCHR_BREAK_BIT (1 << 4) /* RX break */
135#define MAX3107_SPCHR_MULTIDROP_BIT (1 << 5) /* 9-bit multidrop addr char */
136#define MAX3107_SPCHR_UNDEF6_BIT (1 << 6) /* Undefined/not used */
137#define MAX3107_SPCHR_UNDEF7_BIT (1 << 7) /* Undefined/not used */
138
139/* Status register bits */
140#define MAX3107_STS_GPIO0_BIT (1 << 0) /* GPIO 0 interrupt */
141#define MAX3107_STS_GPIO1_BIT (1 << 1) /* GPIO 1 interrupt */
142#define MAX3107_STS_GPIO2_BIT (1 << 2) /* GPIO 2 interrupt */
143#define MAX3107_STS_GPIO3_BIT (1 << 3) /* GPIO 3 interrupt */
144#define MAX3107_STS_UNDEF4_BIT (1 << 4) /* Undefined/not used */
145#define MAX3107_STS_CLKREADY_BIT (1 << 5) /* Clock ready */
146#define MAX3107_STS_SLEEP_BIT (1 << 6) /* Sleep interrupt */
147#define MAX3107_STS_UNDEF7_BIT (1 << 7) /* Undefined/not used */
148
149/* MODE1 register bits */
150#define MAX3107_MODE1_RXDIS_BIT (1 << 0) /* RX disable */
151#define MAX3107_MODE1_TXDIS_BIT (1 << 1) /* TX disable */
152#define MAX3107_MODE1_TXHIZ_BIT (1 << 2) /* TX pin three-state */
153#define MAX3107_MODE1_RTSHIZ_BIT (1 << 3) /* RTS pin three-state */
154#define MAX3107_MODE1_TRNSCVCTRL_BIT (1 << 4) /* Transceiver ctrl enable */
155#define MAX3107_MODE1_FORCESLEEP_BIT (1 << 5) /* Force sleep mode */
156#define MAX3107_MODE1_AUTOSLEEP_BIT (1 << 6) /* Auto sleep enable */
157#define MAX3107_MODE1_IRQSEL_BIT (1 << 7) /* IRQ pin enable */
158
159/* MODE2 register bits */
160#define MAX3107_MODE2_RST_BIT (1 << 0) /* Chip reset */
161#define MAX3107_MODE2_FIFORST_BIT (1 << 1) /* FIFO reset */
162#define MAX3107_MODE2_RXTRIGINV_BIT (1 << 2) /* RX FIFO INT invert */
163#define MAX3107_MODE2_RXEMPTINV_BIT (1 << 3) /* RX FIFO empty INT invert */
164#define MAX3107_MODE2_SPCHR_BIT (1 << 4) /* Special chr detect enable */
165#define MAX3107_MODE2_LOOPBACK_BIT (1 << 5) /* Internal loopback enable */
166#define MAX3107_MODE2_MULTIDROP_BIT (1 << 6) /* 9-bit multidrop enable */
167#define MAX3107_MODE2_ECHOSUPR_BIT (1 << 7) /* ECHO suppression enable */
168
169/* LCR register bits */
170#define MAX3107_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */
171#define MAX3107_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1
172 *
173 * Word length bits table:
174 * 00 -> 5 bit words
175 * 01 -> 6 bit words
176 * 10 -> 7 bit words
177 * 11 -> 8 bit words
178 */
179#define MAX3107_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit
180 *
181 * STOP length bit table:
182 * 0 -> 1 stop bit
183 * 1 -> 1-1.5 stop bits if
184 * word length is 5,
185 * 2 stop bits otherwise
186 */
187#define MAX3107_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */
188#define MAX3107_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */
189#define MAX3107_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
190#define MAX3107_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */
191#define MAX3107_LCR_RTS_BIT (1 << 7) /* RTS pin control */
192#define MAX3107_LCR_WORD_LEN_5 (0x0000)
193#define MAX3107_LCR_WORD_LEN_6 (0x0001)
194#define MAX3107_LCR_WORD_LEN_7 (0x0002)
195#define MAX3107_LCR_WORD_LEN_8 (0x0003)
196
197
198/* IRDA register bits */
199#define MAX3107_IRDA_IRDAEN_BIT (1 << 0) /* IRDA mode enable */
200#define MAX3107_IRDA_SIR_BIT (1 << 1) /* SIR mode enable */
201#define MAX3107_IRDA_SHORTIR_BIT (1 << 2) /* Short SIR mode enable */
202#define MAX3107_IRDA_MIR_BIT (1 << 3) /* MIR mode enable */
203#define MAX3107_IRDA_RXINV_BIT (1 << 4) /* RX logic inversion enable */
204#define MAX3107_IRDA_TXINV_BIT (1 << 5) /* TX logic inversion enable */
205#define MAX3107_IRDA_UNDEF6_BIT (1 << 6) /* Undefined/not used */
206#define MAX3107_IRDA_UNDEF7_BIT (1 << 7) /* Undefined/not used */
207
208/* Flow control trigger level register masks */
209#define MAX3107_FLOWLVL_HALT_MASK (0x000f) /* Flow control halt level */
210#define MAX3107_FLOWLVL_RES_MASK (0x00f0) /* Flow control resume level */
211#define MAX3107_FLOWLVL_HALT(words) ((words/8) & 0x000f)
212#define MAX3107_FLOWLVL_RES(words) (((words/8) & 0x000f) << 4)
213
214/* FIFO interrupt trigger level register masks */
215#define MAX3107_FIFOTRIGLVL_TX_MASK (0x000f) /* TX FIFO trigger level */
216#define MAX3107_FIFOTRIGLVL_RX_MASK (0x00f0) /* RX FIFO trigger level */
217#define MAX3107_FIFOTRIGLVL_TX(words) ((words/8) & 0x000f)
218#define MAX3107_FIFOTRIGLVL_RX(words) (((words/8) & 0x000f) << 4)
219
220/* Flow control register bits */
221#define MAX3107_FLOWCTRL_AUTORTS_BIT (1 << 0) /* Auto RTS flow ctrl enable */
222#define MAX3107_FLOWCTRL_AUTOCTS_BIT (1 << 1) /* Auto CTS flow ctrl enable */
223#define MAX3107_FLOWCTRL_GPIADDR_BIT (1 << 2) /* Enables that GPIO inputs
224 * are used in conjunction with
225 * XOFF2 for definition of
226 * special character */
227#define MAX3107_FLOWCTRL_SWFLOWEN_BIT (1 << 3) /* Auto SW flow ctrl enable */
228#define MAX3107_FLOWCTRL_SWFLOW0_BIT (1 << 4) /* SWFLOW bit 0 */
229#define MAX3107_FLOWCTRL_SWFLOW1_BIT (1 << 5) /* SWFLOW bit 1
230 *
231 * SWFLOW bits 1 & 0 table:
232 * 00 -> no transmitter flow
233 * control
234 * 01 -> receiver compares
235 * XON2 and XOFF2
236 * and controls
237 * transmitter
238 * 10 -> receiver compares
239 * XON1 and XOFF1
240 * and controls
241 * transmitter
242 * 11 -> receiver compares
243 * XON1, XON2, XOFF1 and
244 * XOFF2 and controls
245 * transmitter
246 */
247#define MAX3107_FLOWCTRL_SWFLOW2_BIT (1 << 6) /* SWFLOW bit 2 */
248#define MAX3107_FLOWCTRL_SWFLOW3_BIT (1 << 7) /* SWFLOW bit 3
249 *
250 * SWFLOW bits 3 & 2 table:
251 * 00 -> no received flow
252 * control
253 * 01 -> transmitter generates
254 * XON2 and XOFF2
255 * 10 -> transmitter generates
256 * XON1 and XOFF1
257 * 11 -> transmitter generates
258 * XON1, XON2, XOFF1 and
259 * XOFF2
260 */
261
262/* GPIO configuration register bits */
263#define MAX3107_GPIOCFG_GP0OUT_BIT (1 << 0) /* GPIO 0 output enable */
264#define MAX3107_GPIOCFG_GP1OUT_BIT (1 << 1) /* GPIO 1 output enable */
265#define MAX3107_GPIOCFG_GP2OUT_BIT (1 << 2) /* GPIO 2 output enable */
266#define MAX3107_GPIOCFG_GP3OUT_BIT (1 << 3) /* GPIO 3 output enable */
267#define MAX3107_GPIOCFG_GP0OD_BIT (1 << 4) /* GPIO 0 open-drain enable */
268#define MAX3107_GPIOCFG_GP1OD_BIT (1 << 5) /* GPIO 1 open-drain enable */
269#define MAX3107_GPIOCFG_GP2OD_BIT (1 << 6) /* GPIO 2 open-drain enable */
270#define MAX3107_GPIOCFG_GP3OD_BIT (1 << 7) /* GPIO 3 open-drain enable */
271
272/* GPIO DATA register bits */
273#define MAX3107_GPIODATA_GP0OUT_BIT (1 << 0) /* GPIO 0 output value */
274#define MAX3107_GPIODATA_GP1OUT_BIT (1 << 1) /* GPIO 1 output value */
275#define MAX3107_GPIODATA_GP2OUT_BIT (1 << 2) /* GPIO 2 output value */
276#define MAX3107_GPIODATA_GP3OUT_BIT (1 << 3) /* GPIO 3 output value */
277#define MAX3107_GPIODATA_GP0IN_BIT (1 << 4) /* GPIO 0 input value */
278#define MAX3107_GPIODATA_GP1IN_BIT (1 << 5) /* GPIO 1 input value */
279#define MAX3107_GPIODATA_GP2IN_BIT (1 << 6) /* GPIO 2 input value */
280#define MAX3107_GPIODATA_GP3IN_BIT (1 << 7) /* GPIO 3 input value */
281
282/* PLL configuration register masks */
283#define MAX3107_PLLCFG_PREDIV_MASK (0x003f) /* PLL predivision value */
284#define MAX3107_PLLCFG_PLLFACTOR_MASK (0x00c0) /* PLL multiplication factor */
285
286/* Baud rate generator configuration register masks and bits */
287#define MAX3107_BRGCFG_FRACT_MASK (0x000f) /* Fractional portion of
288 * Baud rate generator divisor
289 */
290#define MAX3107_BRGCFG_2XMODE_BIT (1 << 4) /* Double baud rate */
291#define MAX3107_BRGCFG_4XMODE_BIT (1 << 5) /* Quadruple baud rate */
292#define MAX3107_BRGCFG_UNDEF6_BIT (1 << 6) /* Undefined/not used */
293#define MAX3107_BRGCFG_UNDEF7_BIT (1 << 7) /* Undefined/not used */
294
295/* Clock source register bits */
296#define MAX3107_CLKSRC_INTOSC_BIT (1 << 0) /* Internal osc enable */
297#define MAX3107_CLKSRC_CRYST_BIT (1 << 1) /* Crystal osc enable */
298#define MAX3107_CLKSRC_PLL_BIT (1 << 2) /* PLL enable */
299#define MAX3107_CLKSRC_PLLBYP_BIT (1 << 3) /* PLL bypass */
300#define MAX3107_CLKSRC_EXTCLK_BIT (1 << 4) /* External clock enable */
301#define MAX3107_CLKSRC_UNDEF5_BIT (1 << 5) /* Undefined/not used */
302#define MAX3107_CLKSRC_UNDEF6_BIT (1 << 6) /* Undefined/not used */
303#define MAX3107_CLKSRC_CLK2RTS_BIT (1 << 7) /* Baud clk to RTS pin */
304
305
306/* HW definitions */
307#define MAX3107_RX_FIFO_SIZE 128
308#define MAX3107_TX_FIFO_SIZE 128
309#define MAX3107_REVID1 0x00a0
310#define MAX3107_REVID2 0x00a1
311
312
313/* Baud rate generator configuration values for external clock 13MHz */
314#define MAX3107_BRG13_B300 (0x0A9400 | 0x05)
315#define MAX3107_BRG13_B600 (0x054A00 | 0x03)
316#define MAX3107_BRG13_B1200 (0x02A500 | 0x01)
317#define MAX3107_BRG13_B2400 (0x015200 | 0x09)
318#define MAX3107_BRG13_B4800 (0x00A900 | 0x04)
319#define MAX3107_BRG13_B9600 (0x005400 | 0x0A)
320#define MAX3107_BRG13_B19200 (0x002A00 | 0x05)
321#define MAX3107_BRG13_B38400 (0x001500 | 0x03)
322#define MAX3107_BRG13_B57600 (0x000E00 | 0x02)
323#define MAX3107_BRG13_B115200 (0x000700 | 0x01)
324#define MAX3107_BRG13_B230400 (0x000300 | 0x08)
325#define MAX3107_BRG13_B460800 (0x000100 | 0x0c)
326#define MAX3107_BRG13_B921600 (0x000100 | 0x1c)
327
328/* Baud rate generator configuration values for external clock 26MHz */
329#define MAX3107_BRG26_B300 (0x152800 | 0x0A)
330#define MAX3107_BRG26_B600 (0x0A9400 | 0x05)
331#define MAX3107_BRG26_B1200 (0x054A00 | 0x03)
332#define MAX3107_BRG26_B2400 (0x02A500 | 0x01)
333#define MAX3107_BRG26_B4800 (0x015200 | 0x09)
334#define MAX3107_BRG26_B9600 (0x00A900 | 0x04)
335#define MAX3107_BRG26_B19200 (0x005400 | 0x0A)
336#define MAX3107_BRG26_B38400 (0x002A00 | 0x05)
337#define MAX3107_BRG26_B57600 (0x001C00 | 0x03)
338#define MAX3107_BRG26_B115200 (0x000E00 | 0x02)
339#define MAX3107_BRG26_B230400 (0x000700 | 0x01)
340#define MAX3107_BRG26_B460800 (0x000300 | 0x08)
341#define MAX3107_BRG26_B921600 (0x000100 | 0x0C)
342
343/* Baud rate generator configuration values for internal clock */
344#define MAX3107_BRG13_IB300 (0x008000 | 0x00)
345#define MAX3107_BRG13_IB600 (0x004000 | 0x00)
346#define MAX3107_BRG13_IB1200 (0x002000 | 0x00)
347#define MAX3107_BRG13_IB2400 (0x001000 | 0x00)
348#define MAX3107_BRG13_IB4800 (0x000800 | 0x00)
349#define MAX3107_BRG13_IB9600 (0x000400 | 0x00)
350#define MAX3107_BRG13_IB19200 (0x000200 | 0x00)
351#define MAX3107_BRG13_IB38400 (0x000100 | 0x00)
352#define MAX3107_BRG13_IB57600 (0x000000 | 0x0B)
353#define MAX3107_BRG13_IB115200 (0x000000 | 0x05)
354#define MAX3107_BRG13_IB230400 (0x000000 | 0x03)
355#define MAX3107_BRG13_IB460800 (0x000000 | 0x00)
356#define MAX3107_BRG13_IB921600 (0x000000 | 0x00)
357
358
359struct baud_table {
360 int baud;
361 u32 new_brg;
362};
363
364struct max3107_port {
365 /* UART port structure */
366 struct uart_port port;
367
368 /* SPI device structure */
369 struct spi_device *spi;
370
371#if defined(CONFIG_GPIOLIB)
372 /* GPIO chip structure */
373 struct gpio_chip chip;
374#endif
375
376 /* Workqueue that does all the magic */
377 struct workqueue_struct *workqueue;
378 struct work_struct work;
379
380 /* Lock for shared data */
381 spinlock_t data_lock;
382
383 /* Device configuration */
384 int ext_clk; /* 1 if external clock used */
385 int loopback; /* Current loopback mode state */
386 int baud; /* Current baud rate */
387
388 /* State flags */
389 int suspended; /* Indicates suspend mode */
390 int tx_fifo_empty; /* Flag for TX FIFO state */
391 int rx_enabled; /* Flag for receiver state */
392 int tx_enabled; /* Flag for transmitter state */
393
394 u16 irqen_reg; /* Current IRQ enable register value */
395 /* Shared data */
396 u16 mode1_reg; /* Current mode1 register value*/
397 int mode1_commit; /* Flag for setting new mode1 register value */
398 u16 lcr_reg; /* Current LCR register value */
399 int lcr_commit; /* Flag for setting new LCR register value */
400 u32 brg_cfg; /* Current Baud rate generator config */
401 int brg_commit; /* Flag for setting new baud rate generator
402 * config
403 */
404 struct baud_table *baud_tbl;
405 int handle_irq; /* Indicates that IRQ should be handled */
406
407 /* Rx buffer and str*/
408 u16 *rxbuf;
409 u8 *rxstr;
410 /* Tx buffer*/
411 u16 *txbuf;
412
413 struct max3107_plat *pdata; /* Platform data */
414};
415
416/* Platform data structure */
417struct max3107_plat {
418 /* Loopback mode enable */
419 int loopback;
420 /* External clock enable */
421 int ext_clk;
422 /* Called during the register initialisation */
423 void (*init)(struct max3107_port *s);
424 /* Called when the port is found and configured */
425 int (*configure)(struct max3107_port *s);
426 /* HW suspend function */
427 void (*hw_suspend) (struct max3107_port *s, int suspend);
428 /* Polling mode enable */
429 int polled_mode;
430 /* Polling period if polling mode enabled */
431 int poll_time;
432};
433
434extern int max3107_rw(struct max3107_port *s, u8 *tx, u8 *rx, int len);
435extern void max3107_hw_susp(struct max3107_port *s, int suspend);
436extern int max3107_probe(struct spi_device *spi, struct max3107_plat *pdata);
437extern int max3107_remove(struct spi_device *spi);
438extern int max3107_suspend(struct spi_device *spi, pm_message_t state);
439extern int max3107_resume(struct spi_device *spi);
440
441#endif /* _LINUX_SERIAL_MAX3107_H */
diff --git a/drivers/tty/serial/max310x.c b/drivers/tty/serial/max310x.c
new file mode 100644
index 000000000000..2bc28a59d385
--- /dev/null
+++ b/drivers/tty/serial/max310x.c
@@ -0,0 +1,1260 @@
1/*
2 * Maxim (Dallas) MAX3107/8 serial driver
3 *
4 * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
5 *
6 * Based on max3100.c, by Christian Pellegrin <chripell@evolware.org>
7 * Based on max3110.c, by Feng Tang <feng.tang@intel.com>
8 * Based on max3107.c, by Aavamobile
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16/* TODO: MAX3109 support (Dual) */
17/* TODO: MAX14830 support (Quad) */
18
19#include <linux/module.h>
20#include <linux/device.h>
21#include <linux/serial_core.h>
22#include <linux/serial.h>
23#include <linux/tty.h>
24#include <linux/tty_flip.h>
25#include <linux/regmap.h>
26#include <linux/gpio.h>
27#include <linux/spi/spi.h>
28#include <linux/platform_data/max310x.h>
29
30#define MAX310X_MAJOR 204
31#define MAX310X_MINOR 209
32
33/* MAX310X register definitions */
34#define MAX310X_RHR_REG (0x00) /* RX FIFO */
35#define MAX310X_THR_REG (0x00) /* TX FIFO */
36#define MAX310X_IRQEN_REG (0x01) /* IRQ enable */
37#define MAX310X_IRQSTS_REG (0x02) /* IRQ status */
38#define MAX310X_LSR_IRQEN_REG (0x03) /* LSR IRQ enable */
39#define MAX310X_LSR_IRQSTS_REG (0x04) /* LSR IRQ status */
40#define MAX310X_SPCHR_IRQEN_REG (0x05) /* Special char IRQ enable */
41#define MAX310X_SPCHR_IRQSTS_REG (0x06) /* Special char IRQ status */
42#define MAX310X_STS_IRQEN_REG (0x07) /* Status IRQ enable */
43#define MAX310X_STS_IRQSTS_REG (0x08) /* Status IRQ status */
44#define MAX310X_MODE1_REG (0x09) /* MODE1 */
45#define MAX310X_MODE2_REG (0x0a) /* MODE2 */
46#define MAX310X_LCR_REG (0x0b) /* LCR */
47#define MAX310X_RXTO_REG (0x0c) /* RX timeout */
48#define MAX310X_HDPIXDELAY_REG (0x0d) /* Auto transceiver delays */
49#define MAX310X_IRDA_REG (0x0e) /* IRDA settings */
50#define MAX310X_FLOWLVL_REG (0x0f) /* Flow control levels */
51#define MAX310X_FIFOTRIGLVL_REG (0x10) /* FIFO IRQ trigger levels */
52#define MAX310X_TXFIFOLVL_REG (0x11) /* TX FIFO level */
53#define MAX310X_RXFIFOLVL_REG (0x12) /* RX FIFO level */
54#define MAX310X_FLOWCTRL_REG (0x13) /* Flow control */
55#define MAX310X_XON1_REG (0x14) /* XON1 character */
56#define MAX310X_XON2_REG (0x15) /* XON2 character */
57#define MAX310X_XOFF1_REG (0x16) /* XOFF1 character */
58#define MAX310X_XOFF2_REG (0x17) /* XOFF2 character */
59#define MAX310X_GPIOCFG_REG (0x18) /* GPIO config */
60#define MAX310X_GPIODATA_REG (0x19) /* GPIO data */
61#define MAX310X_PLLCFG_REG (0x1a) /* PLL config */
62#define MAX310X_BRGCFG_REG (0x1b) /* Baud rate generator conf */
63#define MAX310X_BRGDIVLSB_REG (0x1c) /* Baud rate divisor LSB */
64#define MAX310X_BRGDIVMSB_REG (0x1d) /* Baud rate divisor MSB */
65#define MAX310X_CLKSRC_REG (0x1e) /* Clock source */
66/* Only present in MAX3107 */
67#define MAX3107_REVID_REG (0x1f) /* Revision identification */
68
69/* IRQ register bits */
70#define MAX310X_IRQ_LSR_BIT (1 << 0) /* LSR interrupt */
71#define MAX310X_IRQ_SPCHR_BIT (1 << 1) /* Special char interrupt */
72#define MAX310X_IRQ_STS_BIT (1 << 2) /* Status interrupt */
73#define MAX310X_IRQ_RXFIFO_BIT (1 << 3) /* RX FIFO interrupt */
74#define MAX310X_IRQ_TXFIFO_BIT (1 << 4) /* TX FIFO interrupt */
75#define MAX310X_IRQ_TXEMPTY_BIT (1 << 5) /* TX FIFO empty interrupt */
76#define MAX310X_IRQ_RXEMPTY_BIT (1 << 6) /* RX FIFO empty interrupt */
77#define MAX310X_IRQ_CTS_BIT (1 << 7) /* CTS interrupt */
78
79/* LSR register bits */
80#define MAX310X_LSR_RXTO_BIT (1 << 0) /* RX timeout */
81#define MAX310X_LSR_RXOVR_BIT (1 << 1) /* RX overrun */
82#define MAX310X_LSR_RXPAR_BIT (1 << 2) /* RX parity error */
83#define MAX310X_LSR_FRERR_BIT (1 << 3) /* Frame error */
84#define MAX310X_LSR_RXBRK_BIT (1 << 4) /* RX break */
85#define MAX310X_LSR_RXNOISE_BIT (1 << 5) /* RX noise */
86#define MAX310X_LSR_CTS_BIT (1 << 7) /* CTS pin state */
87
88/* Special character register bits */
89#define MAX310X_SPCHR_XON1_BIT (1 << 0) /* XON1 character */
90#define MAX310X_SPCHR_XON2_BIT (1 << 1) /* XON2 character */
91#define MAX310X_SPCHR_XOFF1_BIT (1 << 2) /* XOFF1 character */
92#define MAX310X_SPCHR_XOFF2_BIT (1 << 3) /* XOFF2 character */
93#define MAX310X_SPCHR_BREAK_BIT (1 << 4) /* RX break */
94#define MAX310X_SPCHR_MULTIDROP_BIT (1 << 5) /* 9-bit multidrop addr char */
95
96/* Status register bits */
97#define MAX310X_STS_GPIO0_BIT (1 << 0) /* GPIO 0 interrupt */
98#define MAX310X_STS_GPIO1_BIT (1 << 1) /* GPIO 1 interrupt */
99#define MAX310X_STS_GPIO2_BIT (1 << 2) /* GPIO 2 interrupt */
100#define MAX310X_STS_GPIO3_BIT (1 << 3) /* GPIO 3 interrupt */
101#define MAX310X_STS_CLKREADY_BIT (1 << 5) /* Clock ready */
102#define MAX310X_STS_SLEEP_BIT (1 << 6) /* Sleep interrupt */
103
104/* MODE1 register bits */
105#define MAX310X_MODE1_RXDIS_BIT (1 << 0) /* RX disable */
106#define MAX310X_MODE1_TXDIS_BIT (1 << 1) /* TX disable */
107#define MAX310X_MODE1_TXHIZ_BIT (1 << 2) /* TX pin three-state */
108#define MAX310X_MODE1_RTSHIZ_BIT (1 << 3) /* RTS pin three-state */
109#define MAX310X_MODE1_TRNSCVCTRL_BIT (1 << 4) /* Transceiver ctrl enable */
110#define MAX310X_MODE1_FORCESLEEP_BIT (1 << 5) /* Force sleep mode */
111#define MAX310X_MODE1_AUTOSLEEP_BIT (1 << 6) /* Auto sleep enable */
112#define MAX310X_MODE1_IRQSEL_BIT (1 << 7) /* IRQ pin enable */
113
114/* MODE2 register bits */
115#define MAX310X_MODE2_RST_BIT (1 << 0) /* Chip reset */
116#define MAX310X_MODE2_FIFORST_BIT (1 << 1) /* FIFO reset */
117#define MAX310X_MODE2_RXTRIGINV_BIT (1 << 2) /* RX FIFO INT invert */
118#define MAX310X_MODE2_RXEMPTINV_BIT (1 << 3) /* RX FIFO empty INT invert */
119#define MAX310X_MODE2_SPCHR_BIT (1 << 4) /* Special chr detect enable */
120#define MAX310X_MODE2_LOOPBACK_BIT (1 << 5) /* Internal loopback enable */
121#define MAX310X_MODE2_MULTIDROP_BIT (1 << 6) /* 9-bit multidrop enable */
122#define MAX310X_MODE2_ECHOSUPR_BIT (1 << 7) /* ECHO suppression enable */
123
124/* LCR register bits */
125#define MAX310X_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */
126#define MAX310X_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1
127 *
128 * Word length bits table:
129 * 00 -> 5 bit words
130 * 01 -> 6 bit words
131 * 10 -> 7 bit words
132 * 11 -> 8 bit words
133 */
134#define MAX310X_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit
135 *
136 * STOP length bit table:
137 * 0 -> 1 stop bit
138 * 1 -> 1-1.5 stop bits if
139 * word length is 5,
140 * 2 stop bits otherwise
141 */
142#define MAX310X_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */
143#define MAX310X_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */
144#define MAX310X_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
145#define MAX310X_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */
146#define MAX310X_LCR_RTS_BIT (1 << 7) /* RTS pin control */
147#define MAX310X_LCR_WORD_LEN_5 (0x00)
148#define MAX310X_LCR_WORD_LEN_6 (0x01)
149#define MAX310X_LCR_WORD_LEN_7 (0x02)
150#define MAX310X_LCR_WORD_LEN_8 (0x03)
151
152/* IRDA register bits */
153#define MAX310X_IRDA_IRDAEN_BIT (1 << 0) /* IRDA mode enable */
154#define MAX310X_IRDA_SIR_BIT (1 << 1) /* SIR mode enable */
155#define MAX310X_IRDA_SHORTIR_BIT (1 << 2) /* Short SIR mode enable */
156#define MAX310X_IRDA_MIR_BIT (1 << 3) /* MIR mode enable */
157#define MAX310X_IRDA_RXINV_BIT (1 << 4) /* RX logic inversion enable */
158#define MAX310X_IRDA_TXINV_BIT (1 << 5) /* TX logic inversion enable */
159
160/* Flow control trigger level register masks */
161#define MAX310X_FLOWLVL_HALT_MASK (0x000f) /* Flow control halt level */
162#define MAX310X_FLOWLVL_RES_MASK (0x00f0) /* Flow control resume level */
163#define MAX310X_FLOWLVL_HALT(words) ((words / 8) & 0x0f)
164#define MAX310X_FLOWLVL_RES(words) (((words / 8) & 0x0f) << 4)
165
166/* FIFO interrupt trigger level register masks */
167#define MAX310X_FIFOTRIGLVL_TX_MASK (0x0f) /* TX FIFO trigger level */
168#define MAX310X_FIFOTRIGLVL_RX_MASK (0xf0) /* RX FIFO trigger level */
169#define MAX310X_FIFOTRIGLVL_TX(words) ((words / 8) & 0x0f)
170#define MAX310X_FIFOTRIGLVL_RX(words) (((words / 8) & 0x0f) << 4)
171
172/* Flow control register bits */
173#define MAX310X_FLOWCTRL_AUTORTS_BIT (1 << 0) /* Auto RTS flow ctrl enable */
174#define MAX310X_FLOWCTRL_AUTOCTS_BIT (1 << 1) /* Auto CTS flow ctrl enable */
175#define MAX310X_FLOWCTRL_GPIADDR_BIT (1 << 2) /* Enables that GPIO inputs
176 * are used in conjunction with
177 * XOFF2 for definition of
178 * special character */
179#define MAX310X_FLOWCTRL_SWFLOWEN_BIT (1 << 3) /* Auto SW flow ctrl enable */
180#define MAX310X_FLOWCTRL_SWFLOW0_BIT (1 << 4) /* SWFLOW bit 0 */
181#define MAX310X_FLOWCTRL_SWFLOW1_BIT (1 << 5) /* SWFLOW bit 1
182 *
183 * SWFLOW bits 1 & 0 table:
184 * 00 -> no transmitter flow
185 * control
186 * 01 -> receiver compares
187 * XON2 and XOFF2
188 * and controls
189 * transmitter
190 * 10 -> receiver compares
191 * XON1 and XOFF1
192 * and controls
193 * transmitter
194 * 11 -> receiver compares
195 * XON1, XON2, XOFF1 and
196 * XOFF2 and controls
197 * transmitter
198 */
199#define MAX310X_FLOWCTRL_SWFLOW2_BIT (1 << 6) /* SWFLOW bit 2 */
200#define MAX310X_FLOWCTRL_SWFLOW3_BIT (1 << 7) /* SWFLOW bit 3
201 *
202 * SWFLOW bits 3 & 2 table:
203 * 00 -> no received flow
204 * control
205 * 01 -> transmitter generates
206 * XON2 and XOFF2
207 * 10 -> transmitter generates
208 * XON1 and XOFF1
209 * 11 -> transmitter generates
210 * XON1, XON2, XOFF1 and
211 * XOFF2
212 */
213
214/* GPIO configuration register bits */
215#define MAX310X_GPIOCFG_GP0OUT_BIT (1 << 0) /* GPIO 0 output enable */
216#define MAX310X_GPIOCFG_GP1OUT_BIT (1 << 1) /* GPIO 1 output enable */
217#define MAX310X_GPIOCFG_GP2OUT_BIT (1 << 2) /* GPIO 2 output enable */
218#define MAX310X_GPIOCFG_GP3OUT_BIT (1 << 3) /* GPIO 3 output enable */
219#define MAX310X_GPIOCFG_GP0OD_BIT (1 << 4) /* GPIO 0 open-drain enable */
220#define MAX310X_GPIOCFG_GP1OD_BIT (1 << 5) /* GPIO 1 open-drain enable */
221#define MAX310X_GPIOCFG_GP2OD_BIT (1 << 6) /* GPIO 2 open-drain enable */
222#define MAX310X_GPIOCFG_GP3OD_BIT (1 << 7) /* GPIO 3 open-drain enable */
223
224/* GPIO DATA register bits */
225#define MAX310X_GPIODATA_GP0OUT_BIT (1 << 0) /* GPIO 0 output value */
226#define MAX310X_GPIODATA_GP1OUT_BIT (1 << 1) /* GPIO 1 output value */
227#define MAX310X_GPIODATA_GP2OUT_BIT (1 << 2) /* GPIO 2 output value */
228#define MAX310X_GPIODATA_GP3OUT_BIT (1 << 3) /* GPIO 3 output value */
229#define MAX310X_GPIODATA_GP0IN_BIT (1 << 4) /* GPIO 0 input value */
230#define MAX310X_GPIODATA_GP1IN_BIT (1 << 5) /* GPIO 1 input value */
231#define MAX310X_GPIODATA_GP2IN_BIT (1 << 6) /* GPIO 2 input value */
232#define MAX310X_GPIODATA_GP3IN_BIT (1 << 7) /* GPIO 3 input value */
233
234/* PLL configuration register masks */
235#define MAX310X_PLLCFG_PREDIV_MASK (0x3f) /* PLL predivision value */
236#define MAX310X_PLLCFG_PLLFACTOR_MASK (0xc0) /* PLL multiplication factor */
237
238/* Baud rate generator configuration register bits */
239#define MAX310X_BRGCFG_2XMODE_BIT (1 << 4) /* Double baud rate */
240#define MAX310X_BRGCFG_4XMODE_BIT (1 << 5) /* Quadruple baud rate */
241
242/* Clock source register bits */
243#define MAX310X_CLKSRC_CRYST_BIT (1 << 1) /* Crystal osc enable */
244#define MAX310X_CLKSRC_PLL_BIT (1 << 2) /* PLL enable */
245#define MAX310X_CLKSRC_PLLBYP_BIT (1 << 3) /* PLL bypass */
246#define MAX310X_CLKSRC_EXTCLK_BIT (1 << 4) /* External clock enable */
247#define MAX310X_CLKSRC_CLK2RTS_BIT (1 << 7) /* Baud clk to RTS pin */
248
249/* Misc definitions */
250#define MAX310X_FIFO_SIZE (128)
251
252/* MAX3107 specific */
253#define MAX3107_REV_ID (0xa0)
254#define MAX3107_REV_MASK (0xfe)
255
256/* IRQ status bits definitions */
257#define MAX310X_IRQ_TX (MAX310X_IRQ_TXFIFO_BIT | \
258 MAX310X_IRQ_TXEMPTY_BIT)
259#define MAX310X_IRQ_RX (MAX310X_IRQ_RXFIFO_BIT | \
260 MAX310X_IRQ_RXEMPTY_BIT)
261
262/* Supported chip types */
263enum {
264 MAX310X_TYPE_MAX3107 = 3107,
265 MAX310X_TYPE_MAX3108 = 3108,
266};
267
268struct max310x_port {
269 struct uart_driver uart;
270 struct uart_port port;
271
272 const char *name;
273 int uartclk;
274
275 unsigned int nr_gpio;
276#ifdef CONFIG_GPIOLIB
277 struct gpio_chip gpio;
278#endif
279
280 struct regmap *regmap;
281 struct regmap_config regcfg;
282
283 struct workqueue_struct *wq;
284 struct work_struct tx_work;
285
286 struct mutex max310x_mutex;
287
288 struct max310x_pdata *pdata;
289};
290
291static bool max3107_8_reg_writeable(struct device *dev, unsigned int reg)
292{
293 switch (reg) {
294 case MAX310X_IRQSTS_REG:
295 case MAX310X_LSR_IRQSTS_REG:
296 case MAX310X_SPCHR_IRQSTS_REG:
297 case MAX310X_STS_IRQSTS_REG:
298 case MAX310X_TXFIFOLVL_REG:
299 case MAX310X_RXFIFOLVL_REG:
300 case MAX3107_REVID_REG: /* Only available on MAX3107 */
301 return false;
302 default:
303 break;
304 }
305
306 return true;
307}
308
309static bool max310x_reg_volatile(struct device *dev, unsigned int reg)
310{
311 switch (reg) {
312 case MAX310X_RHR_REG:
313 case MAX310X_IRQSTS_REG:
314 case MAX310X_LSR_IRQSTS_REG:
315 case MAX310X_SPCHR_IRQSTS_REG:
316 case MAX310X_STS_IRQSTS_REG:
317 case MAX310X_TXFIFOLVL_REG:
318 case MAX310X_RXFIFOLVL_REG:
319 case MAX310X_GPIODATA_REG:
320 return true;
321 default:
322 break;
323 }
324
325 return false;
326}
327
328static bool max310x_reg_precious(struct device *dev, unsigned int reg)
329{
330 switch (reg) {
331 case MAX310X_RHR_REG:
332 case MAX310X_IRQSTS_REG:
333 case MAX310X_SPCHR_IRQSTS_REG:
334 case MAX310X_STS_IRQSTS_REG:
335 return true;
336 default:
337 break;
338 }
339
340 return false;
341}
342
343static void max310x_set_baud(struct max310x_port *s, int baud)
344{
345 unsigned int mode = 0, div = s->uartclk / baud;
346
347 if (!(div / 16)) {
348 /* Mode x2 */
349 mode = MAX310X_BRGCFG_2XMODE_BIT;
350 div = (s->uartclk * 2) / baud;
351 }
352
353 if (!(div / 16)) {
354 /* Mode x4 */
355 mode = MAX310X_BRGCFG_4XMODE_BIT;
356 div = (s->uartclk * 4) / baud;
357 }
358
359 regmap_write(s->regmap, MAX310X_BRGDIVMSB_REG,
360 ((div / 16) >> 8) & 0xff);
361 regmap_write(s->regmap, MAX310X_BRGDIVLSB_REG, (div / 16) & 0xff);
362 regmap_write(s->regmap, MAX310X_BRGCFG_REG, (div % 16) | mode);
363}
364
365static void max310x_wait_pll(struct max310x_port *s)
366{
367 int tryes = 1000;
368
369 /* Wait for PLL only if crystal is used */
370 if (!(s->pdata->driver_flags & MAX310X_EXT_CLK)) {
371 unsigned int sts = 0;
372
373 while (tryes--) {
374 regmap_read(s->regmap, MAX310X_STS_IRQSTS_REG, &sts);
375 if (sts & MAX310X_STS_CLKREADY_BIT)
376 break;
377 }
378 }
379}
380
381static int __devinit max310x_update_best_err(unsigned long f, long *besterr)
382{
383 /* Use baudrate 115200 for calculate error */
384 long err = f % (115200 * 16);
385
386 if ((*besterr < 0) || (*besterr > err)) {
387 *besterr = err;
388 return 0;
389 }
390
391 return 1;
392}
393
394static int __devinit max310x_set_ref_clk(struct max310x_port *s)
395{
396 unsigned int div, clksrc, pllcfg = 0;
397 long besterr = -1;
398 unsigned long fdiv, fmul, bestfreq = s->pdata->frequency;
399
400 /* First, update error without PLL */
401 max310x_update_best_err(s->pdata->frequency, &besterr);
402
403 /* Try all possible PLL dividers */
404 for (div = 1; (div <= 63) && besterr; div++) {
405 fdiv = DIV_ROUND_CLOSEST(s->pdata->frequency, div);
406
407 /* Try multiplier 6 */
408 fmul = fdiv * 6;
409 if ((fdiv >= 500000) && (fdiv <= 800000))
410 if (!max310x_update_best_err(fmul, &besterr)) {
411 pllcfg = (0 << 6) | div;
412 bestfreq = fmul;
413 }
414 /* Try multiplier 48 */
415 fmul = fdiv * 48;
416 if ((fdiv >= 850000) && (fdiv <= 1200000))
417 if (!max310x_update_best_err(fmul, &besterr)) {
418 pllcfg = (1 << 6) | div;
419 bestfreq = fmul;
420 }
421 /* Try multiplier 96 */
422 fmul = fdiv * 96;
423 if ((fdiv >= 425000) && (fdiv <= 1000000))
424 if (!max310x_update_best_err(fmul, &besterr)) {
425 pllcfg = (2 << 6) | div;
426 bestfreq = fmul;
427 }
428 /* Try multiplier 144 */
429 fmul = fdiv * 144;
430 if ((fdiv >= 390000) && (fdiv <= 667000))
431 if (!max310x_update_best_err(fmul, &besterr)) {
432 pllcfg = (3 << 6) | div;
433 bestfreq = fmul;
434 }
435 }
436
437 /* Configure clock source */
438 if (s->pdata->driver_flags & MAX310X_EXT_CLK)
439 clksrc = MAX310X_CLKSRC_EXTCLK_BIT;
440 else
441 clksrc = MAX310X_CLKSRC_CRYST_BIT;
442
443 /* Configure PLL */
444 if (pllcfg) {
445 clksrc |= MAX310X_CLKSRC_PLL_BIT;
446 regmap_write(s->regmap, MAX310X_PLLCFG_REG, pllcfg);
447 } else
448 clksrc |= MAX310X_CLKSRC_PLLBYP_BIT;
449
450 regmap_write(s->regmap, MAX310X_CLKSRC_REG, clksrc);
451
452 if (pllcfg)
453 max310x_wait_pll(s);
454
455 dev_dbg(s->port.dev, "Reference clock set to %lu Hz\n", bestfreq);
456
457 return (int)bestfreq;
458}
459
460static void max310x_handle_rx(struct max310x_port *s, unsigned int rxlen)
461{
462 unsigned int sts = 0, ch = 0, flag;
463 struct tty_struct *tty = tty_port_tty_get(&s->port.state->port);
464
465 if (!tty)
466 return;
467
468 if (unlikely(rxlen >= MAX310X_FIFO_SIZE)) {
469 dev_warn(s->port.dev, "Possible RX FIFO overrun %d\n", rxlen);
470 /* Ensure sanity of RX level */
471 rxlen = MAX310X_FIFO_SIZE;
472 }
473
474 dev_dbg(s->port.dev, "RX Len = %u\n", rxlen);
475
476 while (rxlen--) {
477 regmap_read(s->regmap, MAX310X_RHR_REG, &ch);
478 regmap_read(s->regmap, MAX310X_LSR_IRQSTS_REG, &sts);
479
480 sts &= MAX310X_LSR_RXPAR_BIT | MAX310X_LSR_FRERR_BIT |
481 MAX310X_LSR_RXOVR_BIT | MAX310X_LSR_RXBRK_BIT;
482
483 s->port.icount.rx++;
484 flag = TTY_NORMAL;
485
486 if (unlikely(sts)) {
487 if (sts & MAX310X_LSR_RXBRK_BIT) {
488 s->port.icount.brk++;
489 if (uart_handle_break(&s->port))
490 continue;
491 } else if (sts & MAX310X_LSR_RXPAR_BIT)
492 s->port.icount.parity++;
493 else if (sts & MAX310X_LSR_FRERR_BIT)
494 s->port.icount.frame++;
495 else if (sts & MAX310X_LSR_RXOVR_BIT)
496 s->port.icount.overrun++;
497
498 sts &= s->port.read_status_mask;
499 if (sts & MAX310X_LSR_RXBRK_BIT)
500 flag = TTY_BREAK;
501 else if (sts & MAX310X_LSR_RXPAR_BIT)
502 flag = TTY_PARITY;
503 else if (sts & MAX310X_LSR_FRERR_BIT)
504 flag = TTY_FRAME;
505 else if (sts & MAX310X_LSR_RXOVR_BIT)
506 flag = TTY_OVERRUN;
507 }
508
509 if (uart_handle_sysrq_char(s->port, ch))
510 continue;
511
512 if (sts & s->port.ignore_status_mask)
513 continue;
514
515 uart_insert_char(&s->port, sts, MAX310X_LSR_RXOVR_BIT,
516 ch, flag);
517 }
518
519 tty_flip_buffer_push(tty);
520
521 tty_kref_put(tty);
522}
523
524static void max310x_handle_tx(struct max310x_port *s)
525{
526 struct circ_buf *xmit = &s->port.state->xmit;
527 unsigned int txlen = 0, to_send;
528
529 if (unlikely(s->port.x_char)) {
530 regmap_write(s->regmap, MAX310X_THR_REG, s->port.x_char);
531 s->port.icount.tx++;
532 s->port.x_char = 0;
533 return;
534 }
535
536 if (uart_circ_empty(xmit) || uart_tx_stopped(&s->port))
537 return;
538
539 /* Get length of data pending in circular buffer */
540 to_send = uart_circ_chars_pending(xmit);
541 if (likely(to_send)) {
542 /* Limit to size of TX FIFO */
543 regmap_read(s->regmap, MAX310X_TXFIFOLVL_REG, &txlen);
544 txlen = MAX310X_FIFO_SIZE - txlen;
545 to_send = (to_send > txlen) ? txlen : to_send;
546
547 dev_dbg(s->port.dev, "TX Len = %u\n", to_send);
548
549 /* Add data to send */
550 s->port.icount.tx += to_send;
551 while (to_send--) {
552 regmap_write(s->regmap, MAX310X_THR_REG,
553 xmit->buf[xmit->tail]);
554 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
555 };
556 }
557
558 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
559 uart_write_wakeup(&s->port);
560}
561
562static irqreturn_t max310x_ist(int irq, void *dev_id)
563{
564 struct max310x_port *s = (struct max310x_port *)dev_id;
565 unsigned int ists = 0, lsr = 0, rxlen = 0;
566
567 mutex_lock(&s->max310x_mutex);
568
569 for (;;) {
570 /* Read IRQ status & RX FIFO level */
571 regmap_read(s->regmap, MAX310X_IRQSTS_REG, &ists);
572 regmap_read(s->regmap, MAX310X_LSR_IRQSTS_REG, &lsr);
573 regmap_read(s->regmap, MAX310X_RXFIFOLVL_REG, &rxlen);
574 if (!ists && !(lsr & MAX310X_LSR_RXTO_BIT) && !rxlen)
575 break;
576
577 dev_dbg(s->port.dev, "IRQ status: 0x%02x\n", ists);
578
579 if (rxlen)
580 max310x_handle_rx(s, rxlen);
581 if (ists & MAX310X_IRQ_TX)
582 max310x_handle_tx(s);
583 if (ists & MAX310X_IRQ_CTS_BIT)
584 uart_handle_cts_change(&s->port,
585 !!(lsr & MAX310X_LSR_CTS_BIT));
586 }
587
588 mutex_unlock(&s->max310x_mutex);
589
590 return IRQ_HANDLED;
591}
592
593static void max310x_wq_proc(struct work_struct *ws)
594{
595 struct max310x_port *s = container_of(ws, struct max310x_port, tx_work);
596
597 mutex_lock(&s->max310x_mutex);
598 max310x_handle_tx(s);
599 mutex_unlock(&s->max310x_mutex);
600}
601
602static void max310x_start_tx(struct uart_port *port)
603{
604 struct max310x_port *s = container_of(port, struct max310x_port, port);
605
606 queue_work(s->wq, &s->tx_work);
607}
608
609static void max310x_stop_tx(struct uart_port *port)
610{
611 /* Do nothing */
612}
613
614static void max310x_stop_rx(struct uart_port *port)
615{
616 /* Do nothing */
617}
618
619static unsigned int max310x_tx_empty(struct uart_port *port)
620{
621 unsigned int val = 0;
622 struct max310x_port *s = container_of(port, struct max310x_port, port);
623
624 mutex_lock(&s->max310x_mutex);
625 regmap_read(s->regmap, MAX310X_TXFIFOLVL_REG, &val);
626 mutex_unlock(&s->max310x_mutex);
627
628 return val ? 0 : TIOCSER_TEMT;
629}
630
631static void max310x_enable_ms(struct uart_port *port)
632{
633 /* Modem status not supported */
634}
635
636static unsigned int max310x_get_mctrl(struct uart_port *port)
637{
638 /* DCD and DSR are not wired and CTS/RTS is handled automatically
639 * so just indicate DSR and CAR asserted
640 */
641 return TIOCM_DSR | TIOCM_CAR;
642}
643
644static void max310x_set_mctrl(struct uart_port *port, unsigned int mctrl)
645{
646 /* DCD and DSR are not wired and CTS/RTS is hadnled automatically
647 * so do nothing
648 */
649}
650
651static void max310x_break_ctl(struct uart_port *port, int break_state)
652{
653 struct max310x_port *s = container_of(port, struct max310x_port, port);
654
655 mutex_lock(&s->max310x_mutex);
656 regmap_update_bits(s->regmap, MAX310X_LCR_REG,
657 MAX310X_LCR_TXBREAK_BIT,
658 break_state ? MAX310X_LCR_TXBREAK_BIT : 0);
659 mutex_unlock(&s->max310x_mutex);
660}
661
662static void max310x_set_termios(struct uart_port *port,
663 struct ktermios *termios,
664 struct ktermios *old)
665{
666 struct max310x_port *s = container_of(port, struct max310x_port, port);
667 unsigned int lcr, flow = 0;
668 int baud;
669
670 mutex_lock(&s->max310x_mutex);
671
672 /* Mask termios capabilities we don't support */
673 termios->c_cflag &= ~CMSPAR;
674 termios->c_iflag &= ~IXANY;
675
676 /* Word size */
677 switch (termios->c_cflag & CSIZE) {
678 case CS5:
679 lcr = MAX310X_LCR_WORD_LEN_5;
680 break;
681 case CS6:
682 lcr = MAX310X_LCR_WORD_LEN_6;
683 break;
684 case CS7:
685 lcr = MAX310X_LCR_WORD_LEN_7;
686 break;
687 case CS8:
688 default:
689 lcr = MAX310X_LCR_WORD_LEN_8;
690 break;
691 }
692
693 /* Parity */
694 if (termios->c_cflag & PARENB) {
695 lcr |= MAX310X_LCR_PARITY_BIT;
696 if (!(termios->c_cflag & PARODD))
697 lcr |= MAX310X_LCR_EVENPARITY_BIT;
698 }
699
700 /* Stop bits */
701 if (termios->c_cflag & CSTOPB)
702 lcr |= MAX310X_LCR_STOPLEN_BIT; /* 2 stops */
703
704 /* Update LCR register */
705 regmap_write(s->regmap, MAX310X_LCR_REG, lcr);
706
707 /* Set read status mask */
708 port->read_status_mask = MAX310X_LSR_RXOVR_BIT;
709 if (termios->c_iflag & INPCK)
710 port->read_status_mask |= MAX310X_LSR_RXPAR_BIT |
711 MAX310X_LSR_FRERR_BIT;
712 if (termios->c_iflag & (BRKINT | PARMRK))
713 port->read_status_mask |= MAX310X_LSR_RXBRK_BIT;
714
715 /* Set status ignore mask */
716 port->ignore_status_mask = 0;
717 if (termios->c_iflag & IGNBRK)
718 port->ignore_status_mask |= MAX310X_LSR_RXBRK_BIT;
719 if (!(termios->c_cflag & CREAD))
720 port->ignore_status_mask |= MAX310X_LSR_RXPAR_BIT |
721 MAX310X_LSR_RXOVR_BIT |
722 MAX310X_LSR_FRERR_BIT |
723 MAX310X_LSR_RXBRK_BIT;
724
725 /* Configure flow control */
726 regmap_write(s->regmap, MAX310X_XON1_REG, termios->c_cc[VSTART]);
727 regmap_write(s->regmap, MAX310X_XOFF1_REG, termios->c_cc[VSTOP]);
728 if (termios->c_cflag & CRTSCTS)
729 flow |= MAX310X_FLOWCTRL_AUTOCTS_BIT |
730 MAX310X_FLOWCTRL_AUTORTS_BIT;
731 if (termios->c_iflag & IXON)
732 flow |= MAX310X_FLOWCTRL_SWFLOW3_BIT |
733 MAX310X_FLOWCTRL_SWFLOWEN_BIT;
734 if (termios->c_iflag & IXOFF)
735 flow |= MAX310X_FLOWCTRL_SWFLOW1_BIT |
736 MAX310X_FLOWCTRL_SWFLOWEN_BIT;
737 regmap_write(s->regmap, MAX310X_FLOWCTRL_REG, flow);
738
739 /* Get baud rate generator configuration */
740 baud = uart_get_baud_rate(port, termios, old,
741 port->uartclk / 16 / 0xffff,
742 port->uartclk / 4);
743
744 /* Setup baudrate generator */
745 max310x_set_baud(s, baud);
746
747 /* Update timeout according to new baud rate */
748 uart_update_timeout(port, termios->c_cflag, baud);
749
750 mutex_unlock(&s->max310x_mutex);
751}
752
753static int max310x_startup(struct uart_port *port)
754{
755 unsigned int val, line = port->line;
756 struct max310x_port *s = container_of(port, struct max310x_port, port);
757
758 if (s->pdata->suspend)
759 s->pdata->suspend(0);
760
761 mutex_lock(&s->max310x_mutex);
762
763 /* Configure baud rate, 9600 as default */
764 max310x_set_baud(s, 9600);
765
766 /* Configure LCR register, 8N1 mode by default */
767 val = MAX310X_LCR_WORD_LEN_8;
768 regmap_write(s->regmap, MAX310X_LCR_REG, val);
769
770 /* Configure MODE1 register */
771 regmap_update_bits(s->regmap, MAX310X_MODE1_REG,
772 MAX310X_MODE1_TRNSCVCTRL_BIT,
773 (s->pdata->uart_flags[line] & MAX310X_AUTO_DIR_CTRL)
774 ? MAX310X_MODE1_TRNSCVCTRL_BIT : 0);
775
776 /* Configure MODE2 register */
777 val = MAX310X_MODE2_RXEMPTINV_BIT;
778 if (s->pdata->uart_flags[line] & MAX310X_LOOPBACK)
779 val |= MAX310X_MODE2_LOOPBACK_BIT;
780 if (s->pdata->uart_flags[line] & MAX310X_ECHO_SUPRESS)
781 val |= MAX310X_MODE2_ECHOSUPR_BIT;
782
783 /* Reset FIFOs */
784 val |= MAX310X_MODE2_FIFORST_BIT;
785 regmap_write(s->regmap, MAX310X_MODE2_REG, val);
786
787 /* Configure FIFO trigger level register */
788 /* RX FIFO trigger for 16 words, TX FIFO trigger for 64 words */
789 val = MAX310X_FIFOTRIGLVL_RX(16) | MAX310X_FIFOTRIGLVL_TX(64);
790 regmap_write(s->regmap, MAX310X_FIFOTRIGLVL_REG, val);
791
792 /* Configure flow control levels */
793 /* Flow control halt level 96, resume level 48 */
794 val = MAX310X_FLOWLVL_RES(48) | MAX310X_FLOWLVL_HALT(96);
795 regmap_write(s->regmap, MAX310X_FLOWLVL_REG, val);
796
797 /* Clear timeout register */
798 regmap_write(s->regmap, MAX310X_RXTO_REG, 0);
799
800 /* Configure LSR interrupt enable register */
801 /* Enable RX timeout interrupt */
802 val = MAX310X_LSR_RXTO_BIT;
803 regmap_write(s->regmap, MAX310X_LSR_IRQEN_REG, val);
804
805 /* Clear FIFO reset */
806 regmap_update_bits(s->regmap, MAX310X_MODE2_REG,
807 MAX310X_MODE2_FIFORST_BIT, 0);
808
809 /* Clear IRQ status register by reading it */
810 regmap_read(s->regmap, MAX310X_IRQSTS_REG, &val);
811
812 /* Configure interrupt enable register */
813 /* Enable CTS change interrupt */
814 val = MAX310X_IRQ_CTS_BIT;
815 /* Enable RX, TX interrupts */
816 val |= MAX310X_IRQ_RX | MAX310X_IRQ_TX;
817 regmap_write(s->regmap, MAX310X_IRQEN_REG, val);
818
819 mutex_unlock(&s->max310x_mutex);
820
821 return 0;
822}
823
824static void max310x_shutdown(struct uart_port *port)
825{
826 struct max310x_port *s = container_of(port, struct max310x_port, port);
827
828 /* Disable all interrupts */
829 mutex_lock(&s->max310x_mutex);
830 regmap_write(s->regmap, MAX310X_IRQEN_REG, 0);
831 mutex_unlock(&s->max310x_mutex);
832
833 if (s->pdata->suspend)
834 s->pdata->suspend(1);
835}
836
837static const char *max310x_type(struct uart_port *port)
838{
839 struct max310x_port *s = container_of(port, struct max310x_port, port);
840
841 return (port->type == PORT_MAX310X) ? s->name : NULL;
842}
843
844static int max310x_request_port(struct uart_port *port)
845{
846 /* Do nothing */
847 return 0;
848}
849
850static void max310x_release_port(struct uart_port *port)
851{
852 /* Do nothing */
853}
854
855static void max310x_config_port(struct uart_port *port, int flags)
856{
857 if (flags & UART_CONFIG_TYPE)
858 port->type = PORT_MAX310X;
859}
860
861static int max310x_verify_port(struct uart_port *port, struct serial_struct *ser)
862{
863 if ((ser->type == PORT_UNKNOWN) || (ser->type == PORT_MAX310X))
864 return 0;
865 if (ser->irq == port->irq)
866 return 0;
867
868 return -EINVAL;
869}
870
871static struct uart_ops max310x_ops = {
872 .tx_empty = max310x_tx_empty,
873 .set_mctrl = max310x_set_mctrl,
874 .get_mctrl = max310x_get_mctrl,
875 .stop_tx = max310x_stop_tx,
876 .start_tx = max310x_start_tx,
877 .stop_rx = max310x_stop_rx,
878 .enable_ms = max310x_enable_ms,
879 .break_ctl = max310x_break_ctl,
880 .startup = max310x_startup,
881 .shutdown = max310x_shutdown,
882 .set_termios = max310x_set_termios,
883 .type = max310x_type,
884 .request_port = max310x_request_port,
885 .release_port = max310x_release_port,
886 .config_port = max310x_config_port,
887 .verify_port = max310x_verify_port,
888};
889
890static int max310x_suspend(struct spi_device *spi, pm_message_t state)
891{
892 int ret;
893 struct max310x_port *s = dev_get_drvdata(&spi->dev);
894
895 dev_dbg(&spi->dev, "Suspend\n");
896
897 ret = uart_suspend_port(&s->uart, &s->port);
898
899 mutex_lock(&s->max310x_mutex);
900
901 /* Enable sleep mode */
902 regmap_update_bits(s->regmap, MAX310X_MODE1_REG,
903 MAX310X_MODE1_FORCESLEEP_BIT,
904 MAX310X_MODE1_FORCESLEEP_BIT);
905
906 mutex_unlock(&s->max310x_mutex);
907
908 if (s->pdata->suspend)
909 s->pdata->suspend(1);
910
911 return ret;
912}
913
914static int max310x_resume(struct spi_device *spi)
915{
916 struct max310x_port *s = dev_get_drvdata(&spi->dev);
917
918 dev_dbg(&spi->dev, "Resume\n");
919
920 if (s->pdata->suspend)
921 s->pdata->suspend(0);
922
923 mutex_lock(&s->max310x_mutex);
924
925 /* Disable sleep mode */
926 regmap_update_bits(s->regmap, MAX310X_MODE1_REG,
927 MAX310X_MODE1_FORCESLEEP_BIT,
928 0);
929
930 max310x_wait_pll(s);
931
932 mutex_unlock(&s->max310x_mutex);
933
934 return uart_resume_port(&s->uart, &s->port);
935}
936
937#ifdef CONFIG_GPIOLIB
938static int max310x_gpio_get(struct gpio_chip *chip, unsigned offset)
939{
940 unsigned int val = 0;
941 struct max310x_port *s = container_of(chip, struct max310x_port, gpio);
942
943 mutex_lock(&s->max310x_mutex);
944 regmap_read(s->regmap, MAX310X_GPIODATA_REG, &val);
945 mutex_unlock(&s->max310x_mutex);
946
947 return !!((val >> 4) & (1 << offset));
948}
949
950static void max310x_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
951{
952 struct max310x_port *s = container_of(chip, struct max310x_port, gpio);
953
954 mutex_lock(&s->max310x_mutex);
955 regmap_update_bits(s->regmap, MAX310X_GPIODATA_REG, 1 << offset, value ?
956 1 << offset : 0);
957 mutex_unlock(&s->max310x_mutex);
958}
959
960static int max310x_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
961{
962 struct max310x_port *s = container_of(chip, struct max310x_port, gpio);
963
964 mutex_lock(&s->max310x_mutex);
965
966 regmap_update_bits(s->regmap, MAX310X_GPIOCFG_REG, 1 << offset, 0);
967
968 mutex_unlock(&s->max310x_mutex);
969
970 return 0;
971}
972
973static int max310x_gpio_direction_output(struct gpio_chip *chip,
974 unsigned offset, int value)
975{
976 struct max310x_port *s = container_of(chip, struct max310x_port, gpio);
977
978 mutex_lock(&s->max310x_mutex);
979
980 regmap_update_bits(s->regmap, MAX310X_GPIOCFG_REG, 1 << offset,
981 1 << offset);
982 regmap_update_bits(s->regmap, MAX310X_GPIODATA_REG, 1 << offset, value ?
983 1 << offset : 0);
984
985 mutex_unlock(&s->max310x_mutex);
986
987 return 0;
988}
989#endif
990
991/* Generic platform data */
992static struct max310x_pdata generic_plat_data = {
993 .driver_flags = MAX310X_EXT_CLK,
994 .uart_flags[0] = MAX310X_ECHO_SUPRESS,
995 .frequency = 26000000,
996};
997
998static int __devinit max310x_probe(struct spi_device *spi)
999{
1000 struct max310x_port *s;
1001 struct device *dev = &spi->dev;
1002 int chiptype = spi_get_device_id(spi)->driver_data;
1003 struct max310x_pdata *pdata = dev->platform_data;
1004 unsigned int val = 0;
1005 int ret;
1006
1007 /* Check for IRQ */
1008 if (spi->irq <= 0) {
1009 dev_err(dev, "No IRQ specified\n");
1010 return -ENOTSUPP;
1011 }
1012
1013 /* Alloc port structure */
1014 s = devm_kzalloc(dev, sizeof(struct max310x_port), GFP_KERNEL);
1015 if (!s) {
1016 dev_err(dev, "Error allocating port structure\n");
1017 return -ENOMEM;
1018 }
1019 dev_set_drvdata(dev, s);
1020
1021 if (!pdata) {
1022 dev_warn(dev, "No platform data supplied, using defaults\n");
1023 pdata = &generic_plat_data;
1024 }
1025 s->pdata = pdata;
1026
1027 /* Individual chip settings */
1028 switch (chiptype) {
1029 case MAX310X_TYPE_MAX3107:
1030 s->name = "MAX3107";
1031 s->nr_gpio = 4;
1032 s->uart.nr = 1;
1033 s->regcfg.max_register = 0x1f;
1034 break;
1035 case MAX310X_TYPE_MAX3108:
1036 s->name = "MAX3108";
1037 s->nr_gpio = 4;
1038 s->uart.nr = 1;
1039 s->regcfg.max_register = 0x1e;
1040 break;
1041 default:
1042 dev_err(dev, "Unsupported chip type %i\n", chiptype);
1043 return -ENOTSUPP;
1044 }
1045
1046 /* Check input frequency */
1047 if ((pdata->driver_flags & MAX310X_EXT_CLK) &&
1048 ((pdata->frequency < 500000) || (pdata->frequency > 35000000)))
1049 goto err_freq;
1050 /* Check frequency for quartz */
1051 if (!(pdata->driver_flags & MAX310X_EXT_CLK) &&
1052 ((pdata->frequency < 1000000) || (pdata->frequency > 4000000)))
1053 goto err_freq;
1054
1055 mutex_init(&s->max310x_mutex);
1056
1057 /* Setup SPI bus */
1058 spi->mode = SPI_MODE_0;
1059 spi->bits_per_word = 8;
1060 spi->max_speed_hz = 26000000;
1061 spi_setup(spi);
1062
1063 /* Setup regmap */
1064 s->regcfg.reg_bits = 8;
1065 s->regcfg.val_bits = 8;
1066 s->regcfg.read_flag_mask = 0x00;
1067 s->regcfg.write_flag_mask = 0x80;
1068 s->regcfg.cache_type = REGCACHE_RBTREE;
1069 s->regcfg.writeable_reg = max3107_8_reg_writeable;
1070 s->regcfg.volatile_reg = max310x_reg_volatile;
1071 s->regcfg.precious_reg = max310x_reg_precious;
1072 s->regmap = devm_regmap_init_spi(spi, &s->regcfg);
1073 if (IS_ERR(s->regmap)) {
1074 ret = PTR_ERR(s->regmap);
1075 dev_err(dev, "Failed to initialize register map\n");
1076 goto err_out;
1077 }
1078
1079 /* Reset chip & check SPI function */
1080 ret = regmap_write(s->regmap, MAX310X_MODE2_REG, MAX310X_MODE2_RST_BIT);
1081 if (ret) {
1082 dev_err(dev, "SPI transfer failed\n");
1083 goto err_out;
1084 }
1085 /* Clear chip reset */
1086 regmap_write(s->regmap, MAX310X_MODE2_REG, 0);
1087
1088 switch (chiptype) {
1089 case MAX310X_TYPE_MAX3107:
1090 /* Check REV ID to ensure we are talking to what we expect */
1091 regmap_read(s->regmap, MAX3107_REVID_REG, &val);
1092 if (((val & MAX3107_REV_MASK) != MAX3107_REV_ID)) {
1093 dev_err(dev, "%s ID 0x%02x does not match\n",
1094 s->name, val);
1095 ret = -ENODEV;
1096 goto err_out;
1097 }
1098 break;
1099 case MAX310X_TYPE_MAX3108:
1100 /* MAX3108 have not REV ID register, we just check default value
1101 * from clocksource register to make sure everything works.
1102 */
1103 regmap_read(s->regmap, MAX310X_CLKSRC_REG, &val);
1104 if (val != (MAX310X_CLKSRC_EXTCLK_BIT |
1105 MAX310X_CLKSRC_PLLBYP_BIT)) {
1106 dev_err(dev, "%s not present\n", s->name);
1107 ret = -ENODEV;
1108 goto err_out;
1109 }
1110 break;
1111 }
1112
1113 /* Board specific configure */
1114 if (pdata->init)
1115 pdata->init();
1116 if (pdata->suspend)
1117 pdata->suspend(0);
1118
1119 /* Calculate referecne clock */
1120 s->uartclk = max310x_set_ref_clk(s);
1121
1122 /* Disable all interrupts */
1123 regmap_write(s->regmap, MAX310X_IRQEN_REG, 0);
1124
1125 /* Setup MODE1 register */
1126 val = MAX310X_MODE1_IRQSEL_BIT; /* Enable IRQ pin */
1127 if (pdata->driver_flags & MAX310X_AUTOSLEEP)
1128 val = MAX310X_MODE1_AUTOSLEEP_BIT;
1129 regmap_write(s->regmap, MAX310X_MODE1_REG, val);
1130
1131 /* Setup interrupt */
1132 ret = devm_request_threaded_irq(dev, spi->irq, NULL, max310x_ist,
1133 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1134 dev_name(dev), s);
1135 if (ret) {
1136 dev_err(dev, "Unable to reguest IRQ %i\n", spi->irq);
1137 goto err_out;
1138 }
1139
1140 /* Register UART driver */
1141 s->uart.owner = THIS_MODULE;
1142 s->uart.driver_name = dev_name(dev);
1143 s->uart.dev_name = "ttyMAX";
1144 s->uart.major = MAX310X_MAJOR;
1145 s->uart.minor = MAX310X_MINOR;
1146 ret = uart_register_driver(&s->uart);
1147 if (ret) {
1148 dev_err(dev, "Registering UART driver failed\n");
1149 goto err_out;
1150 }
1151
1152 /* Initialize workqueue for start TX */
1153 s->wq = create_freezable_workqueue(dev_name(dev));
1154 INIT_WORK(&s->tx_work, max310x_wq_proc);
1155
1156 /* Initialize UART port data */
1157 s->port.line = 0;
1158 s->port.dev = dev;
1159 s->port.irq = spi->irq;
1160 s->port.type = PORT_MAX310X;
1161 s->port.fifosize = MAX310X_FIFO_SIZE;
1162 s->port.flags = UPF_SKIP_TEST | UPF_FIXED_TYPE;
1163 s->port.iotype = UPIO_PORT;
1164 s->port.membase = (void __iomem *)0xffffffff; /* Bogus value */
1165 s->port.uartclk = s->uartclk;
1166 s->port.ops = &max310x_ops;
1167 uart_add_one_port(&s->uart, &s->port);
1168
1169#ifdef CONFIG_GPIOLIB
1170 /* Setup GPIO cotroller */
1171 if (pdata->gpio_base) {
1172 s->gpio.owner = THIS_MODULE;
1173 s->gpio.dev = dev;
1174 s->gpio.label = dev_name(dev);
1175 s->gpio.direction_input = max310x_gpio_direction_input;
1176 s->gpio.get = max310x_gpio_get;
1177 s->gpio.direction_output= max310x_gpio_direction_output;
1178 s->gpio.set = max310x_gpio_set;
1179 s->gpio.base = pdata->gpio_base;
1180 s->gpio.ngpio = s->nr_gpio;
1181 if (gpiochip_add(&s->gpio)) {
1182 /* Indicate that we should not call gpiochip_remove */
1183 s->gpio.base = 0;
1184 }
1185 } else
1186 dev_info(dev, "GPIO support not enabled\n");
1187#endif
1188
1189 /* Go to suspend mode */
1190 if (pdata->suspend)
1191 pdata->suspend(1);
1192
1193 return 0;
1194
1195err_freq:
1196 dev_err(dev, "Frequency parameter incorrect\n");
1197 ret = -EINVAL;
1198
1199err_out:
1200 dev_set_drvdata(dev, NULL);
1201
1202 return ret;
1203}
1204
1205static int __devexit max310x_remove(struct spi_device *spi)
1206{
1207 struct device *dev = &spi->dev;
1208 struct max310x_port *s = dev_get_drvdata(dev);
1209 int ret = 0;
1210
1211 dev_dbg(dev, "Removing port\n");
1212
1213 devm_free_irq(dev, s->port.irq, s);
1214
1215 destroy_workqueue(s->wq);
1216
1217 uart_remove_one_port(&s->uart, &s->port);
1218
1219 uart_unregister_driver(&s->uart);
1220
1221#ifdef CONFIG_GPIOLIB
1222 if (s->pdata->gpio_base) {
1223 ret = gpiochip_remove(&s->gpio);
1224 if (ret)
1225 dev_err(dev, "Failed to remove gpio chip: %d\n", ret);
1226 }
1227#endif
1228
1229 dev_set_drvdata(dev, NULL);
1230
1231 if (s->pdata->suspend)
1232 s->pdata->suspend(1);
1233 if (s->pdata->exit)
1234 s->pdata->exit();
1235
1236 return ret;
1237}
1238
1239static const struct spi_device_id max310x_id_table[] = {
1240 { "max3107", MAX310X_TYPE_MAX3107 },
1241 { "max3108", MAX310X_TYPE_MAX3108 },
1242};
1243MODULE_DEVICE_TABLE(spi, max310x_id_table);
1244
1245static struct spi_driver max310x_driver = {
1246 .driver = {
1247 .name = "max310x",
1248 .owner = THIS_MODULE,
1249 },
1250 .probe = max310x_probe,
1251 .remove = __devexit_p(max310x_remove),
1252 .suspend = max310x_suspend,
1253 .resume = max310x_resume,
1254 .id_table = max310x_id_table,
1255};
1256module_spi_driver(max310x_driver);
1257
1258MODULE_LICENSE("GPL v2");
1259MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
1260MODULE_DESCRIPTION("MAX310X serial driver");
diff --git a/drivers/tty/serial/mpc52xx_uart.c b/drivers/tty/serial/mpc52xx_uart.c
index bedac0d4c9ce..f19d04ed8586 100644
--- a/drivers/tty/serial/mpc52xx_uart.c
+++ b/drivers/tty/serial/mpc52xx_uart.c
@@ -775,11 +775,15 @@ mpc52xx_uart_set_termios(struct uart_port *port, struct ktermios *new,
775 } 775 }
776 776
777 if (new->c_cflag & PARENB) { 777 if (new->c_cflag & PARENB) {
778 if (new->c_cflag & CMSPAR)
779 mr1 |= MPC52xx_PSC_MODE_PARFORCE;
780
781 /* With CMSPAR, PARODD also means high parity (same as termios) */
778 mr1 |= (new->c_cflag & PARODD) ? 782 mr1 |= (new->c_cflag & PARODD) ?
779 MPC52xx_PSC_MODE_PARODD : MPC52xx_PSC_MODE_PAREVEN; 783 MPC52xx_PSC_MODE_PARODD : MPC52xx_PSC_MODE_PAREVEN;
780 } else 784 } else {
781 mr1 |= MPC52xx_PSC_MODE_PARNONE; 785 mr1 |= MPC52xx_PSC_MODE_PARNONE;
782 786 }
783 787
784 mr2 = 0; 788 mr2 = 0;
785 789
diff --git a/drivers/tty/serial/msm_serial.c b/drivers/tty/serial/msm_serial.c
index 8131e2c28015..033e0bc9ebab 100644
--- a/drivers/tty/serial/msm_serial.c
+++ b/drivers/tty/serial/msm_serial.c
@@ -896,7 +896,7 @@ static int __init msm_serial_probe(struct platform_device *pdev)
896 return PTR_ERR(msm_port->clk); 896 return PTR_ERR(msm_port->clk);
897 897
898 if (msm_port->is_uartdm) 898 if (msm_port->is_uartdm)
899 clk_set_rate(msm_port->clk, 7372800); 899 clk_set_rate(msm_port->clk, 1843200);
900 900
901 port->uartclk = clk_get_rate(msm_port->clk); 901 port->uartclk = clk_get_rate(msm_port->clk);
902 printk(KERN_INFO "uartclk = %d\n", port->uartclk); 902 printk(KERN_INFO "uartclk = %d\n", port->uartclk);
diff --git a/drivers/tty/serial/msm_smd_tty.c b/drivers/tty/serial/msm_smd_tty.c
index b25e6ee71443..925d1fa153db 100644
--- a/drivers/tty/serial/msm_smd_tty.c
+++ b/drivers/tty/serial/msm_smd_tty.c
@@ -223,9 +223,11 @@ static int __init smd_tty_init(void)
223 return ret; 223 return ret;
224 224
225 for (i = 0; i < smd_tty_channels_len; i++) { 225 for (i = 0; i < smd_tty_channels_len; i++) {
226 tty_port_init(&smd_tty[smd_tty_channels[i].id].port); 226 struct tty_port *port = &smd_tty[smd_tty_channels[i].id].port;
227 smd_tty[smd_tty_channels[i].id].port.ops = &smd_tty_port_ops; 227 tty_port_init(port);
228 tty_register_device(smd_tty_driver, smd_tty_channels[i].id, 0); 228 port->ops = &smd_tty_port_ops;
229 tty_port_register_device(port, smd_tty_driver,
230 smd_tty_channels[i].id, NULL);
229 } 231 }
230 232
231 return 0; 233 return 0;
diff --git a/drivers/tty/serial/mxs-auart.c b/drivers/tty/serial/mxs-auart.c
index 3a667eed63d6..68984136bfb1 100644
--- a/drivers/tty/serial/mxs-auart.c
+++ b/drivers/tty/serial/mxs-auart.c
@@ -262,7 +262,7 @@ static void mxs_auart_set_mctrl(struct uart_port *u, unsigned mctrl)
262 262
263 ctrl &= ~AUART_CTRL2_RTSEN; 263 ctrl &= ~AUART_CTRL2_RTSEN;
264 if (mctrl & TIOCM_RTS) { 264 if (mctrl & TIOCM_RTS) {
265 if (u->state->port.flags & ASYNC_CTS_FLOW) 265 if (tty_port_cts_enabled(&u->state->port))
266 ctrl |= AUART_CTRL2_RTSEN; 266 ctrl |= AUART_CTRL2_RTSEN;
267 } 267 }
268 268
@@ -457,11 +457,11 @@ static void mxs_auart_shutdown(struct uart_port *u)
457 457
458 writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_CLR); 458 writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_CLR);
459 459
460 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_SET);
461
462 writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN, 460 writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
463 u->membase + AUART_INTR_CLR); 461 u->membase + AUART_INTR_CLR);
464 462
463 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_SET);
464
465 clk_disable_unprepare(s->clk); 465 clk_disable_unprepare(s->clk);
466} 466}
467 467
@@ -796,6 +796,7 @@ static int __devexit mxs_auart_remove(struct platform_device *pdev)
796 796
797 auart_port[pdev->id] = NULL; 797 auart_port[pdev->id] = NULL;
798 798
799 put_device(s->dev);
799 clk_put(s->clk); 800 clk_put(s->clk);
800 free_irq(s->irq, s); 801 free_irq(s->irq, s);
801 kfree(s); 802 kfree(s);
diff --git a/drivers/tty/serial/of_serial.c b/drivers/tty/serial/of_serial.c
index 34e71874a892..df443b908ca3 100644
--- a/drivers/tty/serial/of_serial.c
+++ b/drivers/tty/serial/of_serial.c
@@ -105,6 +105,10 @@ static int __devinit of_platform_serial_setup(struct platform_device *ofdev,
105 port->uartclk = clk; 105 port->uartclk = clk;
106 port->flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_IOREMAP 106 port->flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_IOREMAP
107 | UPF_FIXED_PORT | UPF_FIXED_TYPE; 107 | UPF_FIXED_PORT | UPF_FIXED_TYPE;
108
109 if (of_find_property(np, "no-loopback-test", NULL))
110 port->flags |= UPF_SKIP_TEST;
111
108 port->dev = &ofdev->dev; 112 port->dev = &ofdev->dev;
109 113
110 if (type == PORT_TEGRA) 114 if (type == PORT_TEGRA)
@@ -144,8 +148,15 @@ static int __devinit of_platform_serial_probe(struct platform_device *ofdev)
144 switch (port_type) { 148 switch (port_type) {
145#ifdef CONFIG_SERIAL_8250 149#ifdef CONFIG_SERIAL_8250
146 case PORT_8250 ... PORT_MAX_8250: 150 case PORT_8250 ... PORT_MAX_8250:
147 ret = serial8250_register_port(&port); 151 {
152 /* For now the of bindings don't support the extra
153 8250 specific bits */
154 struct uart_8250_port port8250;
155 memset(&port8250, 0, sizeof(port8250));
156 port8250.port = port;
157 ret = serial8250_register_8250_port(&port8250);
148 break; 158 break;
159 }
149#endif 160#endif
150#ifdef CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL 161#ifdef CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL
151 case PORT_NWPSERIAL: 162 case PORT_NWPSERIAL:
diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index d3cda0cb2df0..f175385bb304 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -32,16 +32,16 @@
32#include <linux/slab.h> 32#include <linux/slab.h>
33#include <linux/tty.h> 33#include <linux/tty.h>
34#include <linux/tty_flip.h> 34#include <linux/tty_flip.h>
35#include <linux/platform_device.h>
35#include <linux/io.h> 36#include <linux/io.h>
36#include <linux/dma-mapping.h>
37#include <linux/clk.h> 37#include <linux/clk.h>
38#include <linux/serial_core.h> 38#include <linux/serial_core.h>
39#include <linux/irq.h> 39#include <linux/irq.h>
40#include <linux/pm_runtime.h> 40#include <linux/pm_runtime.h>
41#include <linux/of.h> 41#include <linux/of.h>
42#include <linux/gpio.h>
43#include <linux/pinctrl/consumer.h>
42 44
43#include <plat/dma.h>
44#include <plat/dmtimer.h>
45#include <plat/omap-serial.h> 45#include <plat/omap-serial.h>
46 46
47#define UART_BUILD_REVISION(x, y) (((x) << 8) | (y)) 47#define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
@@ -57,8 +57,8 @@
57#define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) 57#define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
58 58
59/* FCR register bitmasks */ 59/* FCR register bitmasks */
60#define OMAP_UART_FCR_RX_FIFO_TRIG_SHIFT 6
61#define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6) 60#define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6)
61#define OMAP_UART_FCR_TX_FIFO_TRIG_MASK (0x3 << 4)
62 62
63/* MVR register bitmasks */ 63/* MVR register bitmasks */
64#define OMAP_UART_MVR_SCHEME_SHIFT 30 64#define OMAP_UART_MVR_SCHEME_SHIFT 30
@@ -71,12 +71,52 @@
71#define OMAP_UART_MVR_MAJ_SHIFT 8 71#define OMAP_UART_MVR_MAJ_SHIFT 8
72#define OMAP_UART_MVR_MIN_MASK 0x3f 72#define OMAP_UART_MVR_MIN_MASK 0x3f
73 73
74struct uart_omap_port {
75 struct uart_port port;
76 struct uart_omap_dma uart_dma;
77 struct device *dev;
78
79 unsigned char ier;
80 unsigned char lcr;
81 unsigned char mcr;
82 unsigned char fcr;
83 unsigned char efr;
84 unsigned char dll;
85 unsigned char dlh;
86 unsigned char mdr1;
87 unsigned char scr;
88
89 int use_dma;
90 /*
91 * Some bits in registers are cleared on a read, so they must
92 * be saved whenever the register is read but the bits will not
93 * be immediately processed.
94 */
95 unsigned int lsr_break_flag;
96 unsigned char msr_saved_flags;
97 char name[20];
98 unsigned long port_activity;
99 u32 context_loss_cnt;
100 u32 errata;
101 u8 wakeups_enabled;
102 unsigned int irq_pending:1;
103
104 int DTR_gpio;
105 int DTR_inverted;
106 int DTR_active;
107
108 struct pm_qos_request pm_qos_request;
109 u32 latency;
110 u32 calc_latency;
111 struct work_struct qos_work;
112 struct pinctrl *pins;
113};
114
115#define to_uart_omap_port(p) ((container_of((p), struct uart_omap_port, port)))
116
74static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS]; 117static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
75 118
76/* Forward declaration of functions */ 119/* Forward declaration of functions */
77static void uart_tx_dma_callback(int lch, u16 ch_status, void *data);
78static void serial_omap_rxdma_poll(unsigned long uart_no);
79static int serial_omap_start_rxdma(struct uart_omap_port *up);
80static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1); 120static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
81 121
82static struct workqueue_struct *serial_omap_uart_wq; 122static struct workqueue_struct *serial_omap_uart_wq;
@@ -101,6 +141,46 @@ static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
101 serial_out(up, UART_FCR, 0); 141 serial_out(up, UART_FCR, 0);
102} 142}
103 143
144static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
145{
146 struct omap_uart_port_info *pdata = up->dev->platform_data;
147
148 if (!pdata || !pdata->get_context_loss_count)
149 return 0;
150
151 return pdata->get_context_loss_count(up->dev);
152}
153
154static void serial_omap_set_forceidle(struct uart_omap_port *up)
155{
156 struct omap_uart_port_info *pdata = up->dev->platform_data;
157
158 if (!pdata || !pdata->set_forceidle)
159 return;
160
161 pdata->set_forceidle(up->dev);
162}
163
164static void serial_omap_set_noidle(struct uart_omap_port *up)
165{
166 struct omap_uart_port_info *pdata = up->dev->platform_data;
167
168 if (!pdata || !pdata->set_noidle)
169 return;
170
171 pdata->set_noidle(up->dev);
172}
173
174static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
175{
176 struct omap_uart_port_info *pdata = up->dev->platform_data;
177
178 if (!pdata || !pdata->enable_wakeup)
179 return;
180
181 pdata->enable_wakeup(up->dev, enable);
182}
183
104/* 184/*
105 * serial_omap_get_divisor - calculate divisor value 185 * serial_omap_get_divisor - calculate divisor value
106 * @port: uart port info 186 * @port: uart port info
@@ -126,151 +206,55 @@ serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
126 return port->uartclk/(baud * divisor); 206 return port->uartclk/(baud * divisor);
127} 207}
128 208
129static void serial_omap_stop_rxdma(struct uart_omap_port *up)
130{
131 if (up->uart_dma.rx_dma_used) {
132 del_timer(&up->uart_dma.rx_timer);
133 omap_stop_dma(up->uart_dma.rx_dma_channel);
134 omap_free_dma(up->uart_dma.rx_dma_channel);
135 up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE;
136 up->uart_dma.rx_dma_used = false;
137 pm_runtime_mark_last_busy(&up->pdev->dev);
138 pm_runtime_put_autosuspend(&up->pdev->dev);
139 }
140}
141
142static void serial_omap_enable_ms(struct uart_port *port) 209static void serial_omap_enable_ms(struct uart_port *port)
143{ 210{
144 struct uart_omap_port *up = (struct uart_omap_port *)port; 211 struct uart_omap_port *up = to_uart_omap_port(port);
145 212
146 dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line); 213 dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
147 214
148 pm_runtime_get_sync(&up->pdev->dev); 215 pm_runtime_get_sync(up->dev);
149 up->ier |= UART_IER_MSI; 216 up->ier |= UART_IER_MSI;
150 serial_out(up, UART_IER, up->ier); 217 serial_out(up, UART_IER, up->ier);
151 pm_runtime_put(&up->pdev->dev); 218 pm_runtime_mark_last_busy(up->dev);
219 pm_runtime_put_autosuspend(up->dev);
152} 220}
153 221
154static void serial_omap_stop_tx(struct uart_port *port) 222static void serial_omap_stop_tx(struct uart_port *port)
155{ 223{
156 struct uart_omap_port *up = (struct uart_omap_port *)port; 224 struct uart_omap_port *up = to_uart_omap_port(port);
157 struct omap_uart_port_info *pdata = up->pdev->dev.platform_data;
158 225
159 if (up->use_dma && 226 pm_runtime_get_sync(up->dev);
160 up->uart_dma.tx_dma_channel != OMAP_UART_DMA_CH_FREE) {
161 /*
162 * Check if dma is still active. If yes do nothing,
163 * return. Else stop dma
164 */
165 if (omap_get_dma_active_status(up->uart_dma.tx_dma_channel))
166 return;
167 omap_stop_dma(up->uart_dma.tx_dma_channel);
168 omap_free_dma(up->uart_dma.tx_dma_channel);
169 up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE;
170 pm_runtime_mark_last_busy(&up->pdev->dev);
171 pm_runtime_put_autosuspend(&up->pdev->dev);
172 }
173
174 pm_runtime_get_sync(&up->pdev->dev);
175 if (up->ier & UART_IER_THRI) { 227 if (up->ier & UART_IER_THRI) {
176 up->ier &= ~UART_IER_THRI; 228 up->ier &= ~UART_IER_THRI;
177 serial_out(up, UART_IER, up->ier); 229 serial_out(up, UART_IER, up->ier);
178 } 230 }
179 231
180 if (!up->use_dma && pdata && pdata->set_forceidle) 232 serial_omap_set_forceidle(up);
181 pdata->set_forceidle(up->pdev);
182 233
183 pm_runtime_mark_last_busy(&up->pdev->dev); 234 pm_runtime_mark_last_busy(up->dev);
184 pm_runtime_put_autosuspend(&up->pdev->dev); 235 pm_runtime_put_autosuspend(up->dev);
185} 236}
186 237
187static void serial_omap_stop_rx(struct uart_port *port) 238static void serial_omap_stop_rx(struct uart_port *port)
188{ 239{
189 struct uart_omap_port *up = (struct uart_omap_port *)port; 240 struct uart_omap_port *up = to_uart_omap_port(port);
190 241
191 pm_runtime_get_sync(&up->pdev->dev); 242 pm_runtime_get_sync(up->dev);
192 if (up->use_dma)
193 serial_omap_stop_rxdma(up);
194 up->ier &= ~UART_IER_RLSI; 243 up->ier &= ~UART_IER_RLSI;
195 up->port.read_status_mask &= ~UART_LSR_DR; 244 up->port.read_status_mask &= ~UART_LSR_DR;
196 serial_out(up, UART_IER, up->ier); 245 serial_out(up, UART_IER, up->ier);
197 pm_runtime_mark_last_busy(&up->pdev->dev); 246 pm_runtime_mark_last_busy(up->dev);
198 pm_runtime_put_autosuspend(&up->pdev->dev); 247 pm_runtime_put_autosuspend(up->dev);
199}
200
201static inline void receive_chars(struct uart_omap_port *up,
202 unsigned int *status)
203{
204 struct tty_struct *tty = up->port.state->port.tty;
205 unsigned int flag, lsr = *status;
206 unsigned char ch = 0;
207 int max_count = 256;
208
209 do {
210 if (likely(lsr & UART_LSR_DR))
211 ch = serial_in(up, UART_RX);
212 flag = TTY_NORMAL;
213 up->port.icount.rx++;
214
215 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
216 /*
217 * For statistics only
218 */
219 if (lsr & UART_LSR_BI) {
220 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
221 up->port.icount.brk++;
222 /*
223 * We do the SysRQ and SAK checking
224 * here because otherwise the break
225 * may get masked by ignore_status_mask
226 * or read_status_mask.
227 */
228 if (uart_handle_break(&up->port))
229 goto ignore_char;
230 } else if (lsr & UART_LSR_PE) {
231 up->port.icount.parity++;
232 } else if (lsr & UART_LSR_FE) {
233 up->port.icount.frame++;
234 }
235
236 if (lsr & UART_LSR_OE)
237 up->port.icount.overrun++;
238
239 /*
240 * Mask off conditions which should be ignored.
241 */
242 lsr &= up->port.read_status_mask;
243
244#ifdef CONFIG_SERIAL_OMAP_CONSOLE
245 if (up->port.line == up->port.cons->index) {
246 /* Recover the break flag from console xmit */
247 lsr |= up->lsr_break_flag;
248 }
249#endif
250 if (lsr & UART_LSR_BI)
251 flag = TTY_BREAK;
252 else if (lsr & UART_LSR_PE)
253 flag = TTY_PARITY;
254 else if (lsr & UART_LSR_FE)
255 flag = TTY_FRAME;
256 }
257
258 if (uart_handle_sysrq_char(&up->port, ch))
259 goto ignore_char;
260 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
261ignore_char:
262 lsr = serial_in(up, UART_LSR);
263 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
264 spin_unlock(&up->port.lock);
265 tty_flip_buffer_push(tty);
266 spin_lock(&up->port.lock);
267} 248}
268 249
269static void transmit_chars(struct uart_omap_port *up) 250static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
270{ 251{
271 struct circ_buf *xmit = &up->port.state->xmit; 252 struct circ_buf *xmit = &up->port.state->xmit;
272 int count; 253 int count;
273 254
255 if (!(lsr & UART_LSR_THRE))
256 return;
257
274 if (up->port.x_char) { 258 if (up->port.x_char) {
275 serial_out(up, UART_TX, up->port.x_char); 259 serial_out(up, UART_TX, up->port.x_char);
276 up->port.icount.tx++; 260 up->port.icount.tx++;
@@ -290,8 +274,11 @@ static void transmit_chars(struct uart_omap_port *up)
290 break; 274 break;
291 } while (--count > 0); 275 } while (--count > 0);
292 276
293 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 277 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
278 spin_unlock(&up->port.lock);
294 uart_write_wakeup(&up->port); 279 uart_write_wakeup(&up->port);
280 spin_lock(&up->port.lock);
281 }
295 282
296 if (uart_circ_empty(xmit)) 283 if (uart_circ_empty(xmit))
297 serial_omap_stop_tx(&up->port); 284 serial_omap_stop_tx(&up->port);
@@ -307,70 +294,13 @@ static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
307 294
308static void serial_omap_start_tx(struct uart_port *port) 295static void serial_omap_start_tx(struct uart_port *port)
309{ 296{
310 struct uart_omap_port *up = (struct uart_omap_port *)port; 297 struct uart_omap_port *up = to_uart_omap_port(port);
311 struct omap_uart_port_info *pdata = up->pdev->dev.platform_data;
312 struct circ_buf *xmit;
313 unsigned int start;
314 int ret = 0;
315
316 if (!up->use_dma) {
317 pm_runtime_get_sync(&up->pdev->dev);
318 serial_omap_enable_ier_thri(up);
319 if (pdata && pdata->set_noidle)
320 pdata->set_noidle(up->pdev);
321 pm_runtime_mark_last_busy(&up->pdev->dev);
322 pm_runtime_put_autosuspend(&up->pdev->dev);
323 return;
324 }
325
326 if (up->uart_dma.tx_dma_used)
327 return;
328
329 xmit = &up->port.state->xmit;
330
331 if (up->uart_dma.tx_dma_channel == OMAP_UART_DMA_CH_FREE) {
332 pm_runtime_get_sync(&up->pdev->dev);
333 ret = omap_request_dma(up->uart_dma.uart_dma_tx,
334 "UART Tx DMA",
335 (void *)uart_tx_dma_callback, up,
336 &(up->uart_dma.tx_dma_channel));
337 298
338 if (ret < 0) { 299 pm_runtime_get_sync(up->dev);
339 serial_omap_enable_ier_thri(up); 300 serial_omap_enable_ier_thri(up);
340 return; 301 serial_omap_set_noidle(up);
341 } 302 pm_runtime_mark_last_busy(up->dev);
342 } 303 pm_runtime_put_autosuspend(up->dev);
343 spin_lock(&(up->uart_dma.tx_lock));
344 up->uart_dma.tx_dma_used = true;
345 spin_unlock(&(up->uart_dma.tx_lock));
346
347 start = up->uart_dma.tx_buf_dma_phys +
348 (xmit->tail & (UART_XMIT_SIZE - 1));
349
350 up->uart_dma.tx_buf_size = uart_circ_chars_pending(xmit);
351 /*
352 * It is a circular buffer. See if the buffer has wounded back.
353 * If yes it will have to be transferred in two separate dma
354 * transfers
355 */
356 if (start + up->uart_dma.tx_buf_size >=
357 up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE)
358 up->uart_dma.tx_buf_size =
359 (up->uart_dma.tx_buf_dma_phys +
360 UART_XMIT_SIZE) - start;
361
362 omap_set_dma_dest_params(up->uart_dma.tx_dma_channel, 0,
363 OMAP_DMA_AMODE_CONSTANT,
364 up->uart_dma.uart_base, 0, 0);
365 omap_set_dma_src_params(up->uart_dma.tx_dma_channel, 0,
366 OMAP_DMA_AMODE_POST_INC, start, 0, 0);
367 omap_set_dma_transfer_params(up->uart_dma.tx_dma_channel,
368 OMAP_DMA_DATA_TYPE_S8,
369 up->uart_dma.tx_buf_size, 1,
370 OMAP_DMA_SYNC_ELEMENT,
371 up->uart_dma.uart_dma_tx, 0);
372 /* FIXME: Cache maintenance needed here? */
373 omap_start_dma(up->uart_dma.tx_dma_channel);
374} 304}
375 305
376static unsigned int check_modem_status(struct uart_omap_port *up) 306static unsigned int check_modem_status(struct uart_omap_port *up)
@@ -401,76 +331,158 @@ static unsigned int check_modem_status(struct uart_omap_port *up)
401 return status; 331 return status;
402} 332}
403 333
334static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
335{
336 unsigned int flag;
337
338 up->port.icount.rx++;
339 flag = TTY_NORMAL;
340
341 if (lsr & UART_LSR_BI) {
342 flag = TTY_BREAK;
343 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
344 up->port.icount.brk++;
345 /*
346 * We do the SysRQ and SAK checking
347 * here because otherwise the break
348 * may get masked by ignore_status_mask
349 * or read_status_mask.
350 */
351 if (uart_handle_break(&up->port))
352 return;
353
354 }
355
356 if (lsr & UART_LSR_PE) {
357 flag = TTY_PARITY;
358 up->port.icount.parity++;
359 }
360
361 if (lsr & UART_LSR_FE) {
362 flag = TTY_FRAME;
363 up->port.icount.frame++;
364 }
365
366 if (lsr & UART_LSR_OE)
367 up->port.icount.overrun++;
368
369#ifdef CONFIG_SERIAL_OMAP_CONSOLE
370 if (up->port.line == up->port.cons->index) {
371 /* Recover the break flag from console xmit */
372 lsr |= up->lsr_break_flag;
373 }
374#endif
375 uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
376}
377
378static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
379{
380 unsigned char ch = 0;
381 unsigned int flag;
382
383 if (!(lsr & UART_LSR_DR))
384 return;
385
386 ch = serial_in(up, UART_RX);
387 flag = TTY_NORMAL;
388 up->port.icount.rx++;
389
390 if (uart_handle_sysrq_char(&up->port, ch))
391 return;
392
393 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
394}
395
404/** 396/**
405 * serial_omap_irq() - This handles the interrupt from one port 397 * serial_omap_irq() - This handles the interrupt from one port
406 * @irq: uart port irq number 398 * @irq: uart port irq number
407 * @dev_id: uart port info 399 * @dev_id: uart port info
408 */ 400 */
409static inline irqreturn_t serial_omap_irq(int irq, void *dev_id) 401static irqreturn_t serial_omap_irq(int irq, void *dev_id)
410{ 402{
411 struct uart_omap_port *up = dev_id; 403 struct uart_omap_port *up = dev_id;
404 struct tty_struct *tty = up->port.state->port.tty;
412 unsigned int iir, lsr; 405 unsigned int iir, lsr;
413 unsigned long flags; 406 unsigned int type;
407 irqreturn_t ret = IRQ_NONE;
408 int max_count = 256;
414 409
415 pm_runtime_get_sync(&up->pdev->dev); 410 spin_lock(&up->port.lock);
416 iir = serial_in(up, UART_IIR); 411 pm_runtime_get_sync(up->dev);
417 if (iir & UART_IIR_NO_INT) {
418 pm_runtime_mark_last_busy(&up->pdev->dev);
419 pm_runtime_put_autosuspend(&up->pdev->dev);
420 return IRQ_NONE;
421 }
422 412
423 spin_lock_irqsave(&up->port.lock, flags); 413 do {
424 lsr = serial_in(up, UART_LSR); 414 iir = serial_in(up, UART_IIR);
425 if (iir & UART_IIR_RLSI) { 415 if (iir & UART_IIR_NO_INT)
426 if (!up->use_dma) { 416 break;
427 if (lsr & UART_LSR_DR) 417
428 receive_chars(up, &lsr); 418 ret = IRQ_HANDLED;
429 } else { 419 lsr = serial_in(up, UART_LSR);
430 up->ier &= ~(UART_IER_RDI | UART_IER_RLSI); 420
431 serial_out(up, UART_IER, up->ier); 421 /* extract IRQ type from IIR register */
432 if ((serial_omap_start_rxdma(up) != 0) && 422 type = iir & 0x3e;
433 (lsr & UART_LSR_DR)) 423
434 receive_chars(up, &lsr); 424 switch (type) {
425 case UART_IIR_MSI:
426 check_modem_status(up);
427 break;
428 case UART_IIR_THRI:
429 transmit_chars(up, lsr);
430 break;
431 case UART_IIR_RX_TIMEOUT:
432 /* FALLTHROUGH */
433 case UART_IIR_RDI:
434 serial_omap_rdi(up, lsr);
435 break;
436 case UART_IIR_RLSI:
437 serial_omap_rlsi(up, lsr);
438 break;
439 case UART_IIR_CTS_RTS_DSR:
440 /* simply try again */
441 break;
442 case UART_IIR_XOFF:
443 /* FALLTHROUGH */
444 default:
445 break;
435 } 446 }
436 } 447 } while (!(iir & UART_IIR_NO_INT) && max_count--);
437 448
438 check_modem_status(up); 449 spin_unlock(&up->port.lock);
439 if ((lsr & UART_LSR_THRE) && (iir & UART_IIR_THRI))
440 transmit_chars(up);
441 450
442 spin_unlock_irqrestore(&up->port.lock, flags); 451 tty_flip_buffer_push(tty);
443 pm_runtime_mark_last_busy(&up->pdev->dev);
444 pm_runtime_put_autosuspend(&up->pdev->dev);
445 452
453 pm_runtime_mark_last_busy(up->dev);
454 pm_runtime_put_autosuspend(up->dev);
446 up->port_activity = jiffies; 455 up->port_activity = jiffies;
447 return IRQ_HANDLED; 456
457 return ret;
448} 458}
449 459
450static unsigned int serial_omap_tx_empty(struct uart_port *port) 460static unsigned int serial_omap_tx_empty(struct uart_port *port)
451{ 461{
452 struct uart_omap_port *up = (struct uart_omap_port *)port; 462 struct uart_omap_port *up = to_uart_omap_port(port);
453 unsigned long flags = 0; 463 unsigned long flags = 0;
454 unsigned int ret = 0; 464 unsigned int ret = 0;
455 465
456 pm_runtime_get_sync(&up->pdev->dev); 466 pm_runtime_get_sync(up->dev);
457 dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line); 467 dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
458 spin_lock_irqsave(&up->port.lock, flags); 468 spin_lock_irqsave(&up->port.lock, flags);
459 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; 469 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
460 spin_unlock_irqrestore(&up->port.lock, flags); 470 spin_unlock_irqrestore(&up->port.lock, flags);
461 pm_runtime_put(&up->pdev->dev); 471 pm_runtime_mark_last_busy(up->dev);
472 pm_runtime_put_autosuspend(up->dev);
462 return ret; 473 return ret;
463} 474}
464 475
465static unsigned int serial_omap_get_mctrl(struct uart_port *port) 476static unsigned int serial_omap_get_mctrl(struct uart_port *port)
466{ 477{
467 struct uart_omap_port *up = (struct uart_omap_port *)port; 478 struct uart_omap_port *up = to_uart_omap_port(port);
468 unsigned int status; 479 unsigned int status;
469 unsigned int ret = 0; 480 unsigned int ret = 0;
470 481
471 pm_runtime_get_sync(&up->pdev->dev); 482 pm_runtime_get_sync(up->dev);
472 status = check_modem_status(up); 483 status = check_modem_status(up);
473 pm_runtime_put(&up->pdev->dev); 484 pm_runtime_mark_last_busy(up->dev);
485 pm_runtime_put_autosuspend(up->dev);
474 486
475 dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line); 487 dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
476 488
@@ -487,7 +499,7 @@ static unsigned int serial_omap_get_mctrl(struct uart_port *port)
487 499
488static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl) 500static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
489{ 501{
490 struct uart_omap_port *up = (struct uart_omap_port *)port; 502 struct uart_omap_port *up = to_uart_omap_port(port);
491 unsigned char mcr = 0; 503 unsigned char mcr = 0;
492 504
493 dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line); 505 dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
@@ -502,20 +514,31 @@ static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
502 if (mctrl & TIOCM_LOOP) 514 if (mctrl & TIOCM_LOOP)
503 mcr |= UART_MCR_LOOP; 515 mcr |= UART_MCR_LOOP;
504 516
505 pm_runtime_get_sync(&up->pdev->dev); 517 pm_runtime_get_sync(up->dev);
506 up->mcr = serial_in(up, UART_MCR); 518 up->mcr = serial_in(up, UART_MCR);
507 up->mcr |= mcr; 519 up->mcr |= mcr;
508 serial_out(up, UART_MCR, up->mcr); 520 serial_out(up, UART_MCR, up->mcr);
509 pm_runtime_put(&up->pdev->dev); 521 pm_runtime_mark_last_busy(up->dev);
522 pm_runtime_put_autosuspend(up->dev);
523
524 if (gpio_is_valid(up->DTR_gpio) &&
525 !!(mctrl & TIOCM_DTR) != up->DTR_active) {
526 up->DTR_active = !up->DTR_active;
527 if (gpio_cansleep(up->DTR_gpio))
528 schedule_work(&up->qos_work);
529 else
530 gpio_set_value(up->DTR_gpio,
531 up->DTR_active != up->DTR_inverted);
532 }
510} 533}
511 534
512static void serial_omap_break_ctl(struct uart_port *port, int break_state) 535static void serial_omap_break_ctl(struct uart_port *port, int break_state)
513{ 536{
514 struct uart_omap_port *up = (struct uart_omap_port *)port; 537 struct uart_omap_port *up = to_uart_omap_port(port);
515 unsigned long flags = 0; 538 unsigned long flags = 0;
516 539
517 dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line); 540 dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
518 pm_runtime_get_sync(&up->pdev->dev); 541 pm_runtime_get_sync(up->dev);
519 spin_lock_irqsave(&up->port.lock, flags); 542 spin_lock_irqsave(&up->port.lock, flags);
520 if (break_state == -1) 543 if (break_state == -1)
521 up->lcr |= UART_LCR_SBC; 544 up->lcr |= UART_LCR_SBC;
@@ -523,12 +546,13 @@ static void serial_omap_break_ctl(struct uart_port *port, int break_state)
523 up->lcr &= ~UART_LCR_SBC; 546 up->lcr &= ~UART_LCR_SBC;
524 serial_out(up, UART_LCR, up->lcr); 547 serial_out(up, UART_LCR, up->lcr);
525 spin_unlock_irqrestore(&up->port.lock, flags); 548 spin_unlock_irqrestore(&up->port.lock, flags);
526 pm_runtime_put(&up->pdev->dev); 549 pm_runtime_mark_last_busy(up->dev);
550 pm_runtime_put_autosuspend(up->dev);
527} 551}
528 552
529static int serial_omap_startup(struct uart_port *port) 553static int serial_omap_startup(struct uart_port *port)
530{ 554{
531 struct uart_omap_port *up = (struct uart_omap_port *)port; 555 struct uart_omap_port *up = to_uart_omap_port(port);
532 unsigned long flags = 0; 556 unsigned long flags = 0;
533 int retval; 557 int retval;
534 558
@@ -542,7 +566,7 @@ static int serial_omap_startup(struct uart_port *port)
542 566
543 dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line); 567 dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
544 568
545 pm_runtime_get_sync(&up->pdev->dev); 569 pm_runtime_get_sync(up->dev);
546 /* 570 /*
547 * Clear the FIFO buffers and disable them. 571 * Clear the FIFO buffers and disable them.
548 * (they will be reenabled in set_termios()) 572 * (they will be reenabled in set_termios())
@@ -573,20 +597,6 @@ static int serial_omap_startup(struct uart_port *port)
573 spin_unlock_irqrestore(&up->port.lock, flags); 597 spin_unlock_irqrestore(&up->port.lock, flags);
574 598
575 up->msr_saved_flags = 0; 599 up->msr_saved_flags = 0;
576 if (up->use_dma) {
577 free_page((unsigned long)up->port.state->xmit.buf);
578 up->port.state->xmit.buf = dma_alloc_coherent(NULL,
579 UART_XMIT_SIZE,
580 (dma_addr_t *)&(up->uart_dma.tx_buf_dma_phys),
581 0);
582 init_timer(&(up->uart_dma.rx_timer));
583 up->uart_dma.rx_timer.function = serial_omap_rxdma_poll;
584 up->uart_dma.rx_timer.data = up->port.line;
585 /* Currently the buffer size is 4KB. Can increase it */
586 up->uart_dma.rx_buf = dma_alloc_coherent(NULL,
587 up->uart_dma.rx_buf_size,
588 (dma_addr_t *)&(up->uart_dma.rx_buf_dma_phys), 0);
589 }
590 /* 600 /*
591 * Finally, enable interrupts. Note: Modem status interrupts 601 * Finally, enable interrupts. Note: Modem status interrupts
592 * are set via set_termios(), which will be occurring imminently 602 * are set via set_termios(), which will be occurring imminently
@@ -598,20 +608,20 @@ static int serial_omap_startup(struct uart_port *port)
598 /* Enable module level wake up */ 608 /* Enable module level wake up */
599 serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP); 609 serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP);
600 610
601 pm_runtime_mark_last_busy(&up->pdev->dev); 611 pm_runtime_mark_last_busy(up->dev);
602 pm_runtime_put_autosuspend(&up->pdev->dev); 612 pm_runtime_put_autosuspend(up->dev);
603 up->port_activity = jiffies; 613 up->port_activity = jiffies;
604 return 0; 614 return 0;
605} 615}
606 616
607static void serial_omap_shutdown(struct uart_port *port) 617static void serial_omap_shutdown(struct uart_port *port)
608{ 618{
609 struct uart_omap_port *up = (struct uart_omap_port *)port; 619 struct uart_omap_port *up = to_uart_omap_port(port);
610 unsigned long flags = 0; 620 unsigned long flags = 0;
611 621
612 dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line); 622 dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
613 623
614 pm_runtime_get_sync(&up->pdev->dev); 624 pm_runtime_get_sync(up->dev);
615 /* 625 /*
616 * Disable interrupts from this port 626 * Disable interrupts from this port
617 */ 627 */
@@ -634,19 +644,9 @@ static void serial_omap_shutdown(struct uart_port *port)
634 */ 644 */
635 if (serial_in(up, UART_LSR) & UART_LSR_DR) 645 if (serial_in(up, UART_LSR) & UART_LSR_DR)
636 (void) serial_in(up, UART_RX); 646 (void) serial_in(up, UART_RX);
637 if (up->use_dma) {
638 dma_free_coherent(up->port.dev,
639 UART_XMIT_SIZE, up->port.state->xmit.buf,
640 up->uart_dma.tx_buf_dma_phys);
641 up->port.state->xmit.buf = NULL;
642 serial_omap_stop_rx(port);
643 dma_free_coherent(up->port.dev,
644 up->uart_dma.rx_buf_size, up->uart_dma.rx_buf,
645 up->uart_dma.rx_buf_dma_phys);
646 up->uart_dma.rx_buf = NULL;
647 }
648 647
649 pm_runtime_put(&up->pdev->dev); 648 pm_runtime_mark_last_busy(up->dev);
649 pm_runtime_put_autosuspend(up->dev);
650 free_irq(up->port.irq, up); 650 free_irq(up->port.irq, up);
651} 651}
652 652
@@ -667,19 +667,19 @@ serial_omap_configure_xonxoff
667 667
668 /* 668 /*
669 * IXON Flag: 669 * IXON Flag:
670 * Enable XON/XOFF flow control on output. 670 * Flow control for OMAP.TX
671 * Transmit XON1, XOFF1 671 * OMAP.RX should listen for XON/XOFF
672 */ 672 */
673 if (termios->c_iflag & IXON) 673 if (termios->c_iflag & IXON)
674 up->efr |= OMAP_UART_SW_TX; 674 up->efr |= OMAP_UART_SW_RX;
675 675
676 /* 676 /*
677 * IXOFF Flag: 677 * IXOFF Flag:
678 * Enable XON/XOFF flow control on input. 678 * Flow control for OMAP.RX
679 * Receiver compares XON1, XOFF1. 679 * OMAP.TX should send XON/XOFF
680 */ 680 */
681 if (termios->c_iflag & IXOFF) 681 if (termios->c_iflag & IXOFF)
682 up->efr |= OMAP_UART_SW_RX; 682 up->efr |= OMAP_UART_SW_TX;
683 683
684 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); 684 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
685 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 685 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
@@ -715,13 +715,16 @@ static void serial_omap_uart_qos_work(struct work_struct *work)
715 qos_work); 715 qos_work);
716 716
717 pm_qos_update_request(&up->pm_qos_request, up->latency); 717 pm_qos_update_request(&up->pm_qos_request, up->latency);
718 if (gpio_is_valid(up->DTR_gpio))
719 gpio_set_value_cansleep(up->DTR_gpio,
720 up->DTR_active != up->DTR_inverted);
718} 721}
719 722
720static void 723static void
721serial_omap_set_termios(struct uart_port *port, struct ktermios *termios, 724serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
722 struct ktermios *old) 725 struct ktermios *old)
723{ 726{
724 struct uart_omap_port *up = (struct uart_omap_port *)port; 727 struct uart_omap_port *up = to_uart_omap_port(port);
725 unsigned char cval = 0; 728 unsigned char cval = 0;
726 unsigned char efr = 0; 729 unsigned char efr = 0;
727 unsigned long flags = 0; 730 unsigned long flags = 0;
@@ -768,14 +771,12 @@ serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
768 771
769 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 | 772 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
770 UART_FCR_ENABLE_FIFO; 773 UART_FCR_ENABLE_FIFO;
771 if (up->use_dma)
772 up->fcr |= UART_FCR_DMA_SELECT;
773 774
774 /* 775 /*
775 * Ok, we're now changing the port state. Do it with 776 * Ok, we're now changing the port state. Do it with
776 * interrupts disabled. 777 * interrupts disabled.
777 */ 778 */
778 pm_runtime_get_sync(&up->pdev->dev); 779 pm_runtime_get_sync(up->dev);
779 spin_lock_irqsave(&up->port.lock, flags); 780 spin_lock_irqsave(&up->port.lock, flags);
780 781
781 /* 782 /*
@@ -845,14 +846,13 @@ serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
845 846
846 up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK; 847 up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
847 848
848 if (up->use_dma) { 849 /* Set receive FIFO threshold to 16 characters and
849 serial_out(up, UART_TI752_TLR, 0); 850 * transmit FIFO threshold to 16 spaces
850 up->scr |= UART_FCR_TRIGGER_4; 851 */
851 } else { 852 up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
852 /* Set receive FIFO threshold to 1 byte */ 853 up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK;
853 up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK; 854 up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 |
854 up->fcr |= (0x1 << OMAP_UART_FCR_RX_FIFO_TRIG_SHIFT); 855 UART_FCR_ENABLE_FIFO;
855 }
856 856
857 serial_out(up, UART_FCR, up->fcr); 857 serial_out(up, UART_FCR, up->fcr);
858 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 858 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
@@ -924,20 +924,30 @@ serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
924 serial_omap_configure_xonxoff(up, termios); 924 serial_omap_configure_xonxoff(up, termios);
925 925
926 spin_unlock_irqrestore(&up->port.lock, flags); 926 spin_unlock_irqrestore(&up->port.lock, flags);
927 pm_runtime_put(&up->pdev->dev); 927 pm_runtime_mark_last_busy(up->dev);
928 pm_runtime_put_autosuspend(up->dev);
928 dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line); 929 dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
929} 930}
930 931
932static int serial_omap_set_wake(struct uart_port *port, unsigned int state)
933{
934 struct uart_omap_port *up = to_uart_omap_port(port);
935
936 serial_omap_enable_wakeup(up, state);
937
938 return 0;
939}
940
931static void 941static void
932serial_omap_pm(struct uart_port *port, unsigned int state, 942serial_omap_pm(struct uart_port *port, unsigned int state,
933 unsigned int oldstate) 943 unsigned int oldstate)
934{ 944{
935 struct uart_omap_port *up = (struct uart_omap_port *)port; 945 struct uart_omap_port *up = to_uart_omap_port(port);
936 unsigned char efr; 946 unsigned char efr;
937 947
938 dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line); 948 dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
939 949
940 pm_runtime_get_sync(&up->pdev->dev); 950 pm_runtime_get_sync(up->dev);
941 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 951 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
942 efr = serial_in(up, UART_EFR); 952 efr = serial_in(up, UART_EFR);
943 serial_out(up, UART_EFR, efr | UART_EFR_ECB); 953 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
@@ -948,14 +958,15 @@ serial_omap_pm(struct uart_port *port, unsigned int state,
948 serial_out(up, UART_EFR, efr); 958 serial_out(up, UART_EFR, efr);
949 serial_out(up, UART_LCR, 0); 959 serial_out(up, UART_LCR, 0);
950 960
951 if (!device_may_wakeup(&up->pdev->dev)) { 961 if (!device_may_wakeup(up->dev)) {
952 if (!state) 962 if (!state)
953 pm_runtime_forbid(&up->pdev->dev); 963 pm_runtime_forbid(up->dev);
954 else 964 else
955 pm_runtime_allow(&up->pdev->dev); 965 pm_runtime_allow(up->dev);
956 } 966 }
957 967
958 pm_runtime_put(&up->pdev->dev); 968 pm_runtime_mark_last_busy(up->dev);
969 pm_runtime_put_autosuspend(up->dev);
959} 970}
960 971
961static void serial_omap_release_port(struct uart_port *port) 972static void serial_omap_release_port(struct uart_port *port)
@@ -971,7 +982,7 @@ static int serial_omap_request_port(struct uart_port *port)
971 982
972static void serial_omap_config_port(struct uart_port *port, int flags) 983static void serial_omap_config_port(struct uart_port *port, int flags)
973{ 984{
974 struct uart_omap_port *up = (struct uart_omap_port *)port; 985 struct uart_omap_port *up = to_uart_omap_port(port);
975 986
976 dev_dbg(up->port.dev, "serial_omap_config_port+%d\n", 987 dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
977 up->port.line); 988 up->port.line);
@@ -989,7 +1000,7 @@ serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
989static const char * 1000static const char *
990serial_omap_type(struct uart_port *port) 1001serial_omap_type(struct uart_port *port)
991{ 1002{
992 struct uart_omap_port *up = (struct uart_omap_port *)port; 1003 struct uart_omap_port *up = to_uart_omap_port(port);
993 1004
994 dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line); 1005 dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
995 return up->name; 1006 return up->name;
@@ -1032,26 +1043,33 @@ static inline void wait_for_xmitr(struct uart_omap_port *up)
1032 1043
1033static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch) 1044static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
1034{ 1045{
1035 struct uart_omap_port *up = (struct uart_omap_port *)port; 1046 struct uart_omap_port *up = to_uart_omap_port(port);
1036 1047
1037 pm_runtime_get_sync(&up->pdev->dev); 1048 pm_runtime_get_sync(up->dev);
1038 wait_for_xmitr(up); 1049 wait_for_xmitr(up);
1039 serial_out(up, UART_TX, ch); 1050 serial_out(up, UART_TX, ch);
1040 pm_runtime_put(&up->pdev->dev); 1051 pm_runtime_mark_last_busy(up->dev);
1052 pm_runtime_put_autosuspend(up->dev);
1041} 1053}
1042 1054
1043static int serial_omap_poll_get_char(struct uart_port *port) 1055static int serial_omap_poll_get_char(struct uart_port *port)
1044{ 1056{
1045 struct uart_omap_port *up = (struct uart_omap_port *)port; 1057 struct uart_omap_port *up = to_uart_omap_port(port);
1046 unsigned int status; 1058 unsigned int status;
1047 1059
1048 pm_runtime_get_sync(&up->pdev->dev); 1060 pm_runtime_get_sync(up->dev);
1049 status = serial_in(up, UART_LSR); 1061 status = serial_in(up, UART_LSR);
1050 if (!(status & UART_LSR_DR)) 1062 if (!(status & UART_LSR_DR)) {
1051 return NO_POLL_CHAR; 1063 status = NO_POLL_CHAR;
1064 goto out;
1065 }
1052 1066
1053 status = serial_in(up, UART_RX); 1067 status = serial_in(up, UART_RX);
1054 pm_runtime_put(&up->pdev->dev); 1068
1069out:
1070 pm_runtime_mark_last_busy(up->dev);
1071 pm_runtime_put_autosuspend(up->dev);
1072
1055 return status; 1073 return status;
1056} 1074}
1057 1075
@@ -1065,7 +1083,7 @@ static struct uart_driver serial_omap_reg;
1065 1083
1066static void serial_omap_console_putchar(struct uart_port *port, int ch) 1084static void serial_omap_console_putchar(struct uart_port *port, int ch)
1067{ 1085{
1068 struct uart_omap_port *up = (struct uart_omap_port *)port; 1086 struct uart_omap_port *up = to_uart_omap_port(port);
1069 1087
1070 wait_for_xmitr(up); 1088 wait_for_xmitr(up);
1071 serial_out(up, UART_TX, ch); 1089 serial_out(up, UART_TX, ch);
@@ -1080,7 +1098,7 @@ serial_omap_console_write(struct console *co, const char *s,
1080 unsigned int ier; 1098 unsigned int ier;
1081 int locked = 1; 1099 int locked = 1;
1082 1100
1083 pm_runtime_get_sync(&up->pdev->dev); 1101 pm_runtime_get_sync(up->dev);
1084 1102
1085 local_irq_save(flags); 1103 local_irq_save(flags);
1086 if (up->port.sysrq) 1104 if (up->port.sysrq)
@@ -1114,8 +1132,8 @@ serial_omap_console_write(struct console *co, const char *s,
1114 if (up->msr_saved_flags) 1132 if (up->msr_saved_flags)
1115 check_modem_status(up); 1133 check_modem_status(up);
1116 1134
1117 pm_runtime_mark_last_busy(&up->pdev->dev); 1135 pm_runtime_mark_last_busy(up->dev);
1118 pm_runtime_put_autosuspend(&up->pdev->dev); 1136 pm_runtime_put_autosuspend(up->dev);
1119 if (locked) 1137 if (locked)
1120 spin_unlock(&up->port.lock); 1138 spin_unlock(&up->port.lock);
1121 local_irq_restore(flags); 1139 local_irq_restore(flags);
@@ -1179,6 +1197,7 @@ static struct uart_ops serial_omap_pops = {
1179 .shutdown = serial_omap_shutdown, 1197 .shutdown = serial_omap_shutdown,
1180 .set_termios = serial_omap_set_termios, 1198 .set_termios = serial_omap_set_termios,
1181 .pm = serial_omap_pm, 1199 .pm = serial_omap_pm,
1200 .set_wake = serial_omap_set_wake,
1182 .type = serial_omap_type, 1201 .type = serial_omap_type,
1183 .release_port = serial_omap_release_port, 1202 .release_port = serial_omap_release_port,
1184 .request_port = serial_omap_request_port, 1203 .request_port = serial_omap_request_port,
@@ -1221,150 +1240,7 @@ static int serial_omap_resume(struct device *dev)
1221} 1240}
1222#endif 1241#endif
1223 1242
1224static void serial_omap_rxdma_poll(unsigned long uart_no) 1243static void __devinit omap_serial_fill_features_erratas(struct uart_omap_port *up)
1225{
1226 struct uart_omap_port *up = ui[uart_no];
1227 unsigned int curr_dma_pos, curr_transmitted_size;
1228 int ret = 0;
1229
1230 curr_dma_pos = omap_get_dma_dst_pos(up->uart_dma.rx_dma_channel);
1231 if ((curr_dma_pos == up->uart_dma.prev_rx_dma_pos) ||
1232 (curr_dma_pos == 0)) {
1233 if (jiffies_to_msecs(jiffies - up->port_activity) <
1234 up->uart_dma.rx_timeout) {
1235 mod_timer(&up->uart_dma.rx_timer, jiffies +
1236 usecs_to_jiffies(up->uart_dma.rx_poll_rate));
1237 } else {
1238 serial_omap_stop_rxdma(up);
1239 up->ier |= (UART_IER_RDI | UART_IER_RLSI);
1240 serial_out(up, UART_IER, up->ier);
1241 }
1242 return;
1243 }
1244
1245 curr_transmitted_size = curr_dma_pos -
1246 up->uart_dma.prev_rx_dma_pos;
1247 up->port.icount.rx += curr_transmitted_size;
1248 tty_insert_flip_string(up->port.state->port.tty,
1249 up->uart_dma.rx_buf +
1250 (up->uart_dma.prev_rx_dma_pos -
1251 up->uart_dma.rx_buf_dma_phys),
1252 curr_transmitted_size);
1253 tty_flip_buffer_push(up->port.state->port.tty);
1254 up->uart_dma.prev_rx_dma_pos = curr_dma_pos;
1255 if (up->uart_dma.rx_buf_size +
1256 up->uart_dma.rx_buf_dma_phys == curr_dma_pos) {
1257 ret = serial_omap_start_rxdma(up);
1258 if (ret < 0) {
1259 serial_omap_stop_rxdma(up);
1260 up->ier |= (UART_IER_RDI | UART_IER_RLSI);
1261 serial_out(up, UART_IER, up->ier);
1262 }
1263 } else {
1264 mod_timer(&up->uart_dma.rx_timer, jiffies +
1265 usecs_to_jiffies(up->uart_dma.rx_poll_rate));
1266 }
1267 up->port_activity = jiffies;
1268}
1269
1270static void uart_rx_dma_callback(int lch, u16 ch_status, void *data)
1271{
1272 return;
1273}
1274
1275static int serial_omap_start_rxdma(struct uart_omap_port *up)
1276{
1277 int ret = 0;
1278
1279 if (up->uart_dma.rx_dma_channel == -1) {
1280 pm_runtime_get_sync(&up->pdev->dev);
1281 ret = omap_request_dma(up->uart_dma.uart_dma_rx,
1282 "UART Rx DMA",
1283 (void *)uart_rx_dma_callback, up,
1284 &(up->uart_dma.rx_dma_channel));
1285 if (ret < 0)
1286 return ret;
1287
1288 omap_set_dma_src_params(up->uart_dma.rx_dma_channel, 0,
1289 OMAP_DMA_AMODE_CONSTANT,
1290 up->uart_dma.uart_base, 0, 0);
1291 omap_set_dma_dest_params(up->uart_dma.rx_dma_channel, 0,
1292 OMAP_DMA_AMODE_POST_INC,
1293 up->uart_dma.rx_buf_dma_phys, 0, 0);
1294 omap_set_dma_transfer_params(up->uart_dma.rx_dma_channel,
1295 OMAP_DMA_DATA_TYPE_S8,
1296 up->uart_dma.rx_buf_size, 1,
1297 OMAP_DMA_SYNC_ELEMENT,
1298 up->uart_dma.uart_dma_rx, 0);
1299 }
1300 up->uart_dma.prev_rx_dma_pos = up->uart_dma.rx_buf_dma_phys;
1301 /* FIXME: Cache maintenance needed here? */
1302 omap_start_dma(up->uart_dma.rx_dma_channel);
1303 mod_timer(&up->uart_dma.rx_timer, jiffies +
1304 usecs_to_jiffies(up->uart_dma.rx_poll_rate));
1305 up->uart_dma.rx_dma_used = true;
1306 return ret;
1307}
1308
1309static void serial_omap_continue_tx(struct uart_omap_port *up)
1310{
1311 struct circ_buf *xmit = &up->port.state->xmit;
1312 unsigned int start = up->uart_dma.tx_buf_dma_phys
1313 + (xmit->tail & (UART_XMIT_SIZE - 1));
1314
1315 if (uart_circ_empty(xmit))
1316 return;
1317
1318 up->uart_dma.tx_buf_size = uart_circ_chars_pending(xmit);
1319 /*
1320 * It is a circular buffer. See if the buffer has wounded back.
1321 * If yes it will have to be transferred in two separate dma
1322 * transfers
1323 */
1324 if (start + up->uart_dma.tx_buf_size >=
1325 up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE)
1326 up->uart_dma.tx_buf_size =
1327 (up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE) - start;
1328 omap_set_dma_dest_params(up->uart_dma.tx_dma_channel, 0,
1329 OMAP_DMA_AMODE_CONSTANT,
1330 up->uart_dma.uart_base, 0, 0);
1331 omap_set_dma_src_params(up->uart_dma.tx_dma_channel, 0,
1332 OMAP_DMA_AMODE_POST_INC, start, 0, 0);
1333 omap_set_dma_transfer_params(up->uart_dma.tx_dma_channel,
1334 OMAP_DMA_DATA_TYPE_S8,
1335 up->uart_dma.tx_buf_size, 1,
1336 OMAP_DMA_SYNC_ELEMENT,
1337 up->uart_dma.uart_dma_tx, 0);
1338 /* FIXME: Cache maintenance needed here? */
1339 omap_start_dma(up->uart_dma.tx_dma_channel);
1340}
1341
1342static void uart_tx_dma_callback(int lch, u16 ch_status, void *data)
1343{
1344 struct uart_omap_port *up = (struct uart_omap_port *)data;
1345 struct circ_buf *xmit = &up->port.state->xmit;
1346
1347 xmit->tail = (xmit->tail + up->uart_dma.tx_buf_size) & \
1348 (UART_XMIT_SIZE - 1);
1349 up->port.icount.tx += up->uart_dma.tx_buf_size;
1350
1351 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1352 uart_write_wakeup(&up->port);
1353
1354 if (uart_circ_empty(xmit)) {
1355 spin_lock(&(up->uart_dma.tx_lock));
1356 serial_omap_stop_tx(&up->port);
1357 up->uart_dma.tx_dma_used = false;
1358 spin_unlock(&(up->uart_dma.tx_lock));
1359 } else {
1360 omap_stop_dma(up->uart_dma.tx_dma_channel);
1361 serial_omap_continue_tx(up);
1362 }
1363 up->port_activity = jiffies;
1364 return;
1365}
1366
1367static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
1368{ 1244{
1369 u32 mvr, scheme; 1245 u32 mvr, scheme;
1370 u16 revision, major, minor; 1246 u16 revision, major, minor;
@@ -1389,7 +1265,7 @@ static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
1389 minor = (mvr & OMAP_UART_MVR_MIN_MASK); 1265 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
1390 break; 1266 break;
1391 default: 1267 default:
1392 dev_warn(&up->pdev->dev, 1268 dev_warn(up->dev,
1393 "Unknown %s revision, defaulting to highest\n", 1269 "Unknown %s revision, defaulting to highest\n",
1394 up->name); 1270 up->name);
1395 /* highest possible revision */ 1271 /* highest possible revision */
@@ -1417,7 +1293,7 @@ static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
1417 } 1293 }
1418} 1294}
1419 1295
1420static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev) 1296static __devinit struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
1421{ 1297{
1422 struct omap_uart_port_info *omap_up_info; 1298 struct omap_uart_port_info *omap_up_info;
1423 1299
@@ -1430,12 +1306,12 @@ static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
1430 return omap_up_info; 1306 return omap_up_info;
1431} 1307}
1432 1308
1433static int serial_omap_probe(struct platform_device *pdev) 1309static int __devinit serial_omap_probe(struct platform_device *pdev)
1434{ 1310{
1435 struct uart_omap_port *up; 1311 struct uart_omap_port *up;
1436 struct resource *mem, *irq, *dma_tx, *dma_rx; 1312 struct resource *mem, *irq;
1437 struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data; 1313 struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data;
1438 int ret = -ENOSPC; 1314 int ret;
1439 1315
1440 if (pdev->dev.of_node) 1316 if (pdev->dev.of_node)
1441 omap_up_info = of_get_uart_port_info(&pdev->dev); 1317 omap_up_info = of_get_uart_port_info(&pdev->dev);
@@ -1458,19 +1334,30 @@ static int serial_omap_probe(struct platform_device *pdev)
1458 return -EBUSY; 1334 return -EBUSY;
1459 } 1335 }
1460 1336
1461 dma_rx = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx"); 1337 if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1462 if (!dma_rx) 1338 omap_up_info->DTR_present) {
1463 return -ENXIO; 1339 ret = gpio_request(omap_up_info->DTR_gpio, "omap-serial");
1464 1340 if (ret < 0)
1465 dma_tx = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx"); 1341 return ret;
1466 if (!dma_tx) 1342 ret = gpio_direction_output(omap_up_info->DTR_gpio,
1467 return -ENXIO; 1343 omap_up_info->DTR_inverted);
1344 if (ret < 0)
1345 return ret;
1346 }
1468 1347
1469 up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL); 1348 up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
1470 if (!up) 1349 if (!up)
1471 return -ENOMEM; 1350 return -ENOMEM;
1472 1351
1473 up->pdev = pdev; 1352 if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1353 omap_up_info->DTR_present) {
1354 up->DTR_gpio = omap_up_info->DTR_gpio;
1355 up->DTR_inverted = omap_up_info->DTR_inverted;
1356 } else
1357 up->DTR_gpio = -EINVAL;
1358 up->DTR_active = 0;
1359
1360 up->dev = &pdev->dev;
1474 up->port.dev = &pdev->dev; 1361 up->port.dev = &pdev->dev;
1475 up->port.type = PORT_OMAP; 1362 up->port.type = PORT_OMAP;
1476 up->port.iotype = UPIO_MEM; 1363 up->port.iotype = UPIO_MEM;
@@ -1492,6 +1379,13 @@ static int serial_omap_probe(struct platform_device *pdev)
1492 goto err_port_line; 1379 goto err_port_line;
1493 } 1380 }
1494 1381
1382 up->pins = devm_pinctrl_get_select_default(&pdev->dev);
1383 if (IS_ERR(up->pins)) {
1384 dev_warn(&pdev->dev, "did not get pins for uart%i error: %li\n",
1385 up->port.line, PTR_ERR(up->pins));
1386 up->pins = NULL;
1387 }
1388
1495 sprintf(up->name, "OMAP UART%d", up->port.line); 1389 sprintf(up->name, "OMAP UART%d", up->port.line);
1496 up->port.mapbase = mem->start; 1390 up->port.mapbase = mem->start;
1497 up->port.membase = devm_ioremap(&pdev->dev, mem->start, 1391 up->port.membase = devm_ioremap(&pdev->dev, mem->start,
@@ -1509,20 +1403,6 @@ static int serial_omap_probe(struct platform_device *pdev)
1509 dev_warn(&pdev->dev, "No clock speed specified: using default:" 1403 dev_warn(&pdev->dev, "No clock speed specified: using default:"
1510 "%d\n", DEFAULT_CLK_SPEED); 1404 "%d\n", DEFAULT_CLK_SPEED);
1511 } 1405 }
1512 up->uart_dma.uart_base = mem->start;
1513
1514 if (omap_up_info->dma_enabled) {
1515 up->uart_dma.uart_dma_tx = dma_tx->start;
1516 up->uart_dma.uart_dma_rx = dma_rx->start;
1517 up->use_dma = 1;
1518 up->uart_dma.rx_buf_size = omap_up_info->dma_rx_buf_size;
1519 up->uart_dma.rx_timeout = omap_up_info->dma_rx_timeout;
1520 up->uart_dma.rx_poll_rate = omap_up_info->dma_rx_poll_rate;
1521 spin_lock_init(&(up->uart_dma.tx_lock));
1522 spin_lock_init(&(up->uart_dma.rx_lock));
1523 up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE;
1524 up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE;
1525 }
1526 1406
1527 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1407 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1528 up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1408 up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
@@ -1531,12 +1411,13 @@ static int serial_omap_probe(struct platform_device *pdev)
1531 serial_omap_uart_wq = create_singlethread_workqueue(up->name); 1411 serial_omap_uart_wq = create_singlethread_workqueue(up->name);
1532 INIT_WORK(&up->qos_work, serial_omap_uart_qos_work); 1412 INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1533 1413
1414 platform_set_drvdata(pdev, up);
1415 pm_runtime_enable(&pdev->dev);
1534 pm_runtime_use_autosuspend(&pdev->dev); 1416 pm_runtime_use_autosuspend(&pdev->dev);
1535 pm_runtime_set_autosuspend_delay(&pdev->dev, 1417 pm_runtime_set_autosuspend_delay(&pdev->dev,
1536 omap_up_info->autosuspend_timeout); 1418 omap_up_info->autosuspend_timeout);
1537 1419
1538 pm_runtime_irq_safe(&pdev->dev); 1420 pm_runtime_irq_safe(&pdev->dev);
1539 pm_runtime_enable(&pdev->dev);
1540 pm_runtime_get_sync(&pdev->dev); 1421 pm_runtime_get_sync(&pdev->dev);
1541 1422
1542 omap_serial_fill_features_erratas(up); 1423 omap_serial_fill_features_erratas(up);
@@ -1548,8 +1429,8 @@ static int serial_omap_probe(struct platform_device *pdev)
1548 if (ret != 0) 1429 if (ret != 0)
1549 goto err_add_port; 1430 goto err_add_port;
1550 1431
1551 pm_runtime_put(&pdev->dev); 1432 pm_runtime_mark_last_busy(up->dev);
1552 platform_set_drvdata(pdev, up); 1433 pm_runtime_put_autosuspend(up->dev);
1553 return 0; 1434 return 0;
1554 1435
1555err_add_port: 1436err_add_port:
@@ -1562,17 +1443,15 @@ err_port_line:
1562 return ret; 1443 return ret;
1563} 1444}
1564 1445
1565static int serial_omap_remove(struct platform_device *dev) 1446static int __devexit serial_omap_remove(struct platform_device *dev)
1566{ 1447{
1567 struct uart_omap_port *up = platform_get_drvdata(dev); 1448 struct uart_omap_port *up = platform_get_drvdata(dev);
1568 1449
1569 if (up) { 1450 pm_runtime_put_sync(up->dev);
1570 pm_runtime_disable(&up->pdev->dev); 1451 pm_runtime_disable(up->dev);
1571 uart_remove_one_port(&serial_omap_reg, &up->port); 1452 uart_remove_one_port(&serial_omap_reg, &up->port);
1572 pm_qos_remove_request(&up->pm_qos_request); 1453 pm_qos_remove_request(&up->pm_qos_request);
1573 }
1574 1454
1575 platform_set_drvdata(dev, NULL);
1576 return 0; 1455 return 0;
1577} 1456}
1578 1457
@@ -1602,7 +1481,7 @@ static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1602 timeout--; 1481 timeout--;
1603 if (!timeout) { 1482 if (!timeout) {
1604 /* Should *never* happen. we warn and carry on */ 1483 /* Should *never* happen. we warn and carry on */
1605 dev_crit(&up->pdev->dev, "Errata i202: timedout %x\n", 1484 dev_crit(up->dev, "Errata i202: timedout %x\n",
1606 serial_in(up, UART_LSR)); 1485 serial_in(up, UART_LSR));
1607 break; 1486 break;
1608 } 1487 }
@@ -1648,29 +1527,23 @@ static int serial_omap_runtime_suspend(struct device *dev)
1648 if (!up) 1527 if (!up)
1649 return -EINVAL; 1528 return -EINVAL;
1650 1529
1651 if (!pdata || !pdata->enable_wakeup) 1530 if (!pdata)
1652 return 0; 1531 return 0;
1653 1532
1654 if (pdata->get_context_loss_count) 1533 up->context_loss_cnt = serial_omap_get_context_loss_count(up);
1655 up->context_loss_cnt = pdata->get_context_loss_count(dev);
1656 1534
1657 if (device_may_wakeup(dev)) { 1535 if (device_may_wakeup(dev)) {
1658 if (!up->wakeups_enabled) { 1536 if (!up->wakeups_enabled) {
1659 pdata->enable_wakeup(up->pdev, true); 1537 serial_omap_enable_wakeup(up, true);
1660 up->wakeups_enabled = true; 1538 up->wakeups_enabled = true;
1661 } 1539 }
1662 } else { 1540 } else {
1663 if (up->wakeups_enabled) { 1541 if (up->wakeups_enabled) {
1664 pdata->enable_wakeup(up->pdev, false); 1542 serial_omap_enable_wakeup(up, false);
1665 up->wakeups_enabled = false; 1543 up->wakeups_enabled = false;
1666 } 1544 }
1667 } 1545 }
1668 1546
1669 /* Errata i291 */
1670 if (up->use_dma && pdata->set_forceidle &&
1671 (up->errata & UART_ERRATA_i291_DMA_FORCEIDLE))
1672 pdata->set_forceidle(up->pdev);
1673
1674 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1547 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1675 schedule_work(&up->qos_work); 1548 schedule_work(&up->qos_work);
1676 1549
@@ -1683,17 +1556,10 @@ static int serial_omap_runtime_resume(struct device *dev)
1683 struct omap_uart_port_info *pdata = dev->platform_data; 1556 struct omap_uart_port_info *pdata = dev->platform_data;
1684 1557
1685 if (up && pdata) { 1558 if (up && pdata) {
1686 if (pdata->get_context_loss_count) { 1559 u32 loss_cnt = serial_omap_get_context_loss_count(up);
1687 u32 loss_cnt = pdata->get_context_loss_count(dev);
1688 1560
1689 if (up->context_loss_cnt != loss_cnt) 1561 if (up->context_loss_cnt != loss_cnt)
1690 serial_omap_restore_context(up); 1562 serial_omap_restore_context(up);
1691 }
1692
1693 /* Errata i291 */
1694 if (up->use_dma && pdata->set_noidle &&
1695 (up->errata & UART_ERRATA_i291_DMA_FORCEIDLE))
1696 pdata->set_noidle(up->pdev);
1697 1563
1698 up->latency = up->calc_latency; 1564 up->latency = up->calc_latency;
1699 schedule_work(&up->qos_work); 1565 schedule_work(&up->qos_work);
@@ -1721,7 +1587,7 @@ MODULE_DEVICE_TABLE(of, omap_serial_of_match);
1721 1587
1722static struct platform_driver serial_omap_driver = { 1588static struct platform_driver serial_omap_driver = {
1723 .probe = serial_omap_probe, 1589 .probe = serial_omap_probe,
1724 .remove = serial_omap_remove, 1590 .remove = __devexit_p(serial_omap_remove),
1725 .driver = { 1591 .driver = {
1726 .name = DRIVER_NAME, 1592 .name = DRIVER_NAME,
1727 .pm = &serial_omap_dev_pm_ops, 1593 .pm = &serial_omap_dev_pm_ops,
diff --git a/drivers/tty/serial/pch_uart.c b/drivers/tty/serial/pch_uart.c
index 558ce8509a9a..4cd6c2381528 100644
--- a/drivers/tty/serial/pch_uart.c
+++ b/drivers/tty/serial/pch_uart.c
@@ -979,6 +979,10 @@ static unsigned int dma_handle_tx(struct eg20t_port *priv)
979 priv->tx_dma_use = 1; 979 priv->tx_dma_use = 1;
980 980
981 priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC); 981 priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
982 if (!priv->sg_tx_p) {
983 dev_err(priv->port.dev, "%s:kzalloc Failed\n", __func__);
984 return 0;
985 }
982 986
983 sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */ 987 sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
984 sg = priv->sg_tx_p; 988 sg = priv->sg_tx_p;
diff --git a/drivers/tty/serial/pxa.c b/drivers/tty/serial/pxa.c
index 5847a4b855f7..9033fc6e0e4e 100644
--- a/drivers/tty/serial/pxa.c
+++ b/drivers/tty/serial/pxa.c
@@ -670,9 +670,19 @@ serial_pxa_console_write(struct console *co, const char *s, unsigned int count)
670{ 670{
671 struct uart_pxa_port *up = serial_pxa_ports[co->index]; 671 struct uart_pxa_port *up = serial_pxa_ports[co->index];
672 unsigned int ier; 672 unsigned int ier;
673 unsigned long flags;
674 int locked = 1;
673 675
674 clk_prepare_enable(up->clk); 676 clk_prepare_enable(up->clk);
675 677
678 local_irq_save(flags);
679 if (up->port.sysrq)
680 locked = 0;
681 else if (oops_in_progress)
682 locked = spin_trylock(&up->port.lock);
683 else
684 spin_lock(&up->port.lock);
685
676 /* 686 /*
677 * First save the IER then disable the interrupts 687 * First save the IER then disable the interrupts
678 */ 688 */
@@ -688,6 +698,10 @@ serial_pxa_console_write(struct console *co, const char *s, unsigned int count)
688 wait_for_xmitr(up); 698 wait_for_xmitr(up);
689 serial_out(up, UART_IER, ier); 699 serial_out(up, UART_IER, ier);
690 700
701 if (locked)
702 spin_unlock(&up->port.lock);
703 local_irq_restore(flags);
704
691 clk_disable_unprepare(up->clk); 705 clk_disable_unprepare(up->clk);
692} 706}
693 707
diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c
index 02d07bfcfa8a..bdaa06f3ab69 100644
--- a/drivers/tty/serial/samsung.c
+++ b/drivers/tty/serial/samsung.c
@@ -82,7 +82,7 @@ static inline const char *s3c24xx_serial_portname(struct uart_port *port)
82 82
83static int s3c24xx_serial_txempty_nofifo(struct uart_port *port) 83static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
84{ 84{
85 return (rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE); 85 return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
86} 86}
87 87
88/* 88/*
@@ -268,7 +268,7 @@ s3c24xx_serial_rx_chars(int irq, void *dev_id)
268 dbg("break!\n"); 268 dbg("break!\n");
269 port->icount.brk++; 269 port->icount.brk++;
270 if (uart_handle_break(port)) 270 if (uart_handle_break(port))
271 goto ignore_char; 271 goto ignore_char;
272 } 272 }
273 273
274 if (uerstat & S3C2410_UERSTAT_FRAME) 274 if (uerstat & S3C2410_UERSTAT_FRAME)
@@ -459,7 +459,7 @@ static int s3c24xx_serial_startup(struct uart_port *port)
459 s3c24xx_serial_portname(port), ourport); 459 s3c24xx_serial_portname(port), ourport);
460 460
461 if (ret != 0) { 461 if (ret != 0) {
462 printk(KERN_ERR "cannot get irq %d\n", ourport->rx_irq); 462 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
463 return ret; 463 return ret;
464 } 464 }
465 465
@@ -473,7 +473,7 @@ static int s3c24xx_serial_startup(struct uart_port *port)
473 s3c24xx_serial_portname(port), ourport); 473 s3c24xx_serial_portname(port), ourport);
474 474
475 if (ret) { 475 if (ret) {
476 printk(KERN_ERR "cannot get irq %d\n", ourport->tx_irq); 476 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
477 goto err; 477 goto err;
478 } 478 }
479 479
@@ -502,7 +502,7 @@ static int s3c64xx_serial_startup(struct uart_port *port)
502 ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED, 502 ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
503 s3c24xx_serial_portname(port), ourport); 503 s3c24xx_serial_portname(port), ourport);
504 if (ret) { 504 if (ret) {
505 printk(KERN_ERR "cannot get irq %d\n", port->irq); 505 dev_err(port->dev, "cannot get irq %d\n", port->irq);
506 return ret; 506 return ret;
507 } 507 }
508 508
@@ -529,7 +529,7 @@ static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
529 529
530 switch (level) { 530 switch (level) {
531 case 3: 531 case 3:
532 if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL) 532 if (!IS_ERR(ourport->baudclk))
533 clk_disable(ourport->baudclk); 533 clk_disable(ourport->baudclk);
534 534
535 clk_disable(ourport->clk); 535 clk_disable(ourport->clk);
@@ -538,12 +538,12 @@ static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
538 case 0: 538 case 0:
539 clk_enable(ourport->clk); 539 clk_enable(ourport->clk);
540 540
541 if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL) 541 if (!IS_ERR(ourport->baudclk))
542 clk_enable(ourport->baudclk); 542 clk_enable(ourport->baudclk);
543 543
544 break; 544 break;
545 default: 545 default:
546 printk(KERN_ERR "s3c24xx_serial: unknown pm %d\n", level); 546 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
547 } 547 }
548} 548}
549 549
@@ -604,7 +604,6 @@ static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
604 char clkname[MAX_CLK_NAME_LENGTH]; 604 char clkname[MAX_CLK_NAME_LENGTH];
605 int calc_deviation, deviation = (1 << 30) - 1; 605 int calc_deviation, deviation = (1 << 30) - 1;
606 606
607 *best_clk = NULL;
608 clk_sel = (ourport->cfg->clk_sel) ? ourport->cfg->clk_sel : 607 clk_sel = (ourport->cfg->clk_sel) ? ourport->cfg->clk_sel :
609 ourport->info->def_clk_sel; 608 ourport->info->def_clk_sel;
610 for (cnt = 0; cnt < info->num_clks; cnt++) { 609 for (cnt = 0; cnt < info->num_clks; cnt++) {
@@ -613,7 +612,7 @@ static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
613 612
614 sprintf(clkname, "clk_uart_baud%d", cnt); 613 sprintf(clkname, "clk_uart_baud%d", cnt);
615 clk = clk_get(ourport->port.dev, clkname); 614 clk = clk_get(ourport->port.dev, clkname);
616 if (IS_ERR_OR_NULL(clk)) 615 if (IS_ERR(clk))
617 continue; 616 continue;
618 617
619 rate = clk_get_rate(clk); 618 rate = clk_get_rate(clk);
@@ -684,7 +683,7 @@ static void s3c24xx_serial_set_termios(struct uart_port *port,
684{ 683{
685 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port); 684 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
686 struct s3c24xx_uart_port *ourport = to_ourport(port); 685 struct s3c24xx_uart_port *ourport = to_ourport(port);
687 struct clk *clk = NULL; 686 struct clk *clk = ERR_PTR(-EINVAL);
688 unsigned long flags; 687 unsigned long flags;
689 unsigned int baud, quot, clk_sel = 0; 688 unsigned int baud, quot, clk_sel = 0;
690 unsigned int ulcon; 689 unsigned int ulcon;
@@ -705,7 +704,7 @@ static void s3c24xx_serial_set_termios(struct uart_port *port,
705 quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel); 704 quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
706 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) 705 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
707 quot = port->custom_divisor; 706 quot = port->custom_divisor;
708 if (!clk) 707 if (IS_ERR(clk))
709 return; 708 return;
710 709
711 /* check to see if we need to change clock source */ 710 /* check to see if we need to change clock source */
@@ -713,9 +712,9 @@ static void s3c24xx_serial_set_termios(struct uart_port *port,
713 if (ourport->baudclk != clk) { 712 if (ourport->baudclk != clk) {
714 s3c24xx_serial_setsource(port, clk_sel); 713 s3c24xx_serial_setsource(port, clk_sel);
715 714
716 if (ourport->baudclk != NULL && !IS_ERR(ourport->baudclk)) { 715 if (!IS_ERR(ourport->baudclk)) {
717 clk_disable(ourport->baudclk); 716 clk_disable(ourport->baudclk);
718 ourport->baudclk = NULL; 717 ourport->baudclk = ERR_PTR(-EINVAL);
719 } 718 }
720 719
721 clk_enable(clk); 720 clk_enable(clk);
@@ -1036,10 +1035,10 @@ static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1036 if (tty == NULL) 1035 if (tty == NULL)
1037 goto exit; 1036 goto exit;
1038 1037
1039 termios = tty->termios; 1038 termios = &tty->termios;
1040 1039
1041 if (termios == NULL) { 1040 if (termios == NULL) {
1042 printk(KERN_WARNING "%s: no termios?\n", __func__); 1041 dev_warn(uport->dev, "%s: no termios?\n", __func__);
1043 goto exit; 1042 goto exit;
1044 } 1043 }
1045 1044
@@ -1114,7 +1113,7 @@ static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1114 1113
1115 res = platform_get_resource(platdev, IORESOURCE_MEM, 0); 1114 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1116 if (res == NULL) { 1115 if (res == NULL) {
1117 printk(KERN_ERR "failed to find memory resource for uart\n"); 1116 dev_err(port->dev, "failed to find memory resource for uart\n");
1118 return -EINVAL; 1117 return -EINVAL;
1119 } 1118 }
1120 1119
@@ -1130,7 +1129,7 @@ static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1130 ourport->rx_irq = ret; 1129 ourport->rx_irq = ret;
1131 ourport->tx_irq = ret + 1; 1130 ourport->tx_irq = ret + 1;
1132 } 1131 }
1133 1132
1134 ret = platform_get_irq(platdev, 1); 1133 ret = platform_get_irq(platdev, 1);
1135 if (ret > 0) 1134 if (ret > 0)
1136 ourport->tx_irq = ret; 1135 ourport->tx_irq = ret;
@@ -1160,7 +1159,11 @@ static ssize_t s3c24xx_serial_show_clksrc(struct device *dev,
1160 struct uart_port *port = s3c24xx_dev_to_port(dev); 1159 struct uart_port *port = s3c24xx_dev_to_port(dev);
1161 struct s3c24xx_uart_port *ourport = to_ourport(port); 1160 struct s3c24xx_uart_port *ourport = to_ourport(port);
1162 1161
1163 return snprintf(buf, PAGE_SIZE, "* %s\n", ourport->baudclk->name); 1162 if (IS_ERR(ourport->baudclk))
1163 return -EINVAL;
1164
1165 return snprintf(buf, PAGE_SIZE, "* %s\n",
1166 ourport->baudclk->name ?: "(null)");
1164} 1167}
1165 1168
1166static DEVICE_ATTR(clock_source, S_IRUGO, s3c24xx_serial_show_clksrc, NULL); 1169static DEVICE_ATTR(clock_source, S_IRUGO, s3c24xx_serial_show_clksrc, NULL);
@@ -1200,6 +1203,7 @@ static int s3c24xx_serial_probe(struct platform_device *pdev)
1200 return -ENODEV; 1203 return -ENODEV;
1201 } 1204 }
1202 1205
1206 ourport->baudclk = ERR_PTR(-EINVAL);
1203 ourport->info = ourport->drv_data->info; 1207 ourport->info = ourport->drv_data->info;
1204 ourport->cfg = (pdev->dev.platform_data) ? 1208 ourport->cfg = (pdev->dev.platform_data) ?
1205 (struct s3c2410_uartcfg *)pdev->dev.platform_data : 1209 (struct s3c2410_uartcfg *)pdev->dev.platform_data :
@@ -1387,7 +1391,7 @@ s3c24xx_serial_get_options(struct uart_port *port, int *baud,
1387 sprintf(clk_name, "clk_uart_baud%d", clk_sel); 1391 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
1388 1392
1389 clk = clk_get(port->dev, clk_name); 1393 clk = clk_get(port->dev, clk_name);
1390 if (!IS_ERR(clk) && clk != NULL) 1394 if (!IS_ERR(clk))
1391 rate = clk_get_rate(clk); 1395 rate = clk_get_rate(clk);
1392 else 1396 else
1393 rate = 1; 1397 rate = 1;
@@ -1679,7 +1683,7 @@ static int __init s3c24xx_serial_modinit(void)
1679 1683
1680 ret = uart_register_driver(&s3c24xx_uart_drv); 1684 ret = uart_register_driver(&s3c24xx_uart_drv);
1681 if (ret < 0) { 1685 if (ret < 0) {
1682 printk(KERN_ERR "failed to register UART driver\n"); 1686 pr_err("Failed to register Samsung UART driver\n");
1683 return -1; 1687 return -1;
1684 } 1688 }
1685 1689
diff --git a/drivers/tty/serial/sc26xx.c b/drivers/tty/serial/sc26xx.c
index e0b4b0a30a5a..9d664242b312 100644
--- a/drivers/tty/serial/sc26xx.c
+++ b/drivers/tty/serial/sc26xx.c
@@ -20,6 +20,10 @@
20#include <linux/init.h> 20#include <linux/init.h>
21#include <linux/platform_device.h> 21#include <linux/platform_device.h>
22#include <linux/irq.h> 22#include <linux/irq.h>
23#include <linux/io.h>
24
25#warning "Please try migrate to use new driver SCCNXP and report the status" \
26 "in the linux-serial mailing list."
23 27
24#if defined(CONFIG_MAGIC_SYSRQ) 28#if defined(CONFIG_MAGIC_SYSRQ)
25#define SUPPORT_SYSRQ 29#define SUPPORT_SYSRQ
diff --git a/drivers/tty/serial/sccnxp.c b/drivers/tty/serial/sccnxp.c
new file mode 100644
index 000000000000..05d767cf82a7
--- /dev/null
+++ b/drivers/tty/serial/sccnxp.c
@@ -0,0 +1,985 @@
1/*
2 * NXP (Philips) SCC+++(SCN+++) serial driver
3 *
4 * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
5 *
6 * Based on sc26xx.c, by Thomas Bogendörfer (tsbogend@alpha.franken.de)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
15#define SUPPORT_SYSRQ
16#endif
17
18#include <linux/module.h>
19#include <linux/device.h>
20#include <linux/console.h>
21#include <linux/serial_core.h>
22#include <linux/serial.h>
23#include <linux/io.h>
24#include <linux/tty.h>
25#include <linux/tty_flip.h>
26#include <linux/platform_device.h>
27#include <linux/platform_data/sccnxp.h>
28
29#define SCCNXP_NAME "uart-sccnxp"
30#define SCCNXP_MAJOR 204
31#define SCCNXP_MINOR 205
32
33#define SCCNXP_MR_REG (0x00)
34# define MR0_BAUD_NORMAL (0 << 0)
35# define MR0_BAUD_EXT1 (1 << 0)
36# define MR0_BAUD_EXT2 (5 << 0)
37# define MR0_FIFO (1 << 3)
38# define MR0_TXLVL (1 << 4)
39# define MR1_BITS_5 (0 << 0)
40# define MR1_BITS_6 (1 << 0)
41# define MR1_BITS_7 (2 << 0)
42# define MR1_BITS_8 (3 << 0)
43# define MR1_PAR_EVN (0 << 2)
44# define MR1_PAR_ODD (1 << 2)
45# define MR1_PAR_NO (4 << 2)
46# define MR2_STOP1 (7 << 0)
47# define MR2_STOP2 (0xf << 0)
48#define SCCNXP_SR_REG (0x01)
49#define SCCNXP_CSR_REG SCCNXP_SR_REG
50# define SR_RXRDY (1 << 0)
51# define SR_FULL (1 << 1)
52# define SR_TXRDY (1 << 2)
53# define SR_TXEMT (1 << 3)
54# define SR_OVR (1 << 4)
55# define SR_PE (1 << 5)
56# define SR_FE (1 << 6)
57# define SR_BRK (1 << 7)
58#define SCCNXP_CR_REG (0x02)
59# define CR_RX_ENABLE (1 << 0)
60# define CR_RX_DISABLE (1 << 1)
61# define CR_TX_ENABLE (1 << 2)
62# define CR_TX_DISABLE (1 << 3)
63# define CR_CMD_MRPTR1 (0x01 << 4)
64# define CR_CMD_RX_RESET (0x02 << 4)
65# define CR_CMD_TX_RESET (0x03 << 4)
66# define CR_CMD_STATUS_RESET (0x04 << 4)
67# define CR_CMD_BREAK_RESET (0x05 << 4)
68# define CR_CMD_START_BREAK (0x06 << 4)
69# define CR_CMD_STOP_BREAK (0x07 << 4)
70# define CR_CMD_MRPTR0 (0x0b << 4)
71#define SCCNXP_RHR_REG (0x03)
72#define SCCNXP_THR_REG SCCNXP_RHR_REG
73#define SCCNXP_IPCR_REG (0x04)
74#define SCCNXP_ACR_REG SCCNXP_IPCR_REG
75# define ACR_BAUD0 (0 << 7)
76# define ACR_BAUD1 (1 << 7)
77# define ACR_TIMER_MODE (6 << 4)
78#define SCCNXP_ISR_REG (0x05)
79#define SCCNXP_IMR_REG SCCNXP_ISR_REG
80# define IMR_TXRDY (1 << 0)
81# define IMR_RXRDY (1 << 1)
82# define ISR_TXRDY(x) (1 << ((x * 4) + 0))
83# define ISR_RXRDY(x) (1 << ((x * 4) + 1))
84#define SCCNXP_IPR_REG (0x0d)
85#define SCCNXP_OPCR_REG SCCNXP_IPR_REG
86#define SCCNXP_SOP_REG (0x0e)
87#define SCCNXP_ROP_REG (0x0f)
88
89/* Route helpers */
90#define MCTRL_MASK(sig) (0xf << (sig))
91#define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
92#define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
93
94/* Supported chip types */
95enum {
96 SCCNXP_TYPE_SC2681 = 2681,
97 SCCNXP_TYPE_SC2691 = 2691,
98 SCCNXP_TYPE_SC2692 = 2692,
99 SCCNXP_TYPE_SC2891 = 2891,
100 SCCNXP_TYPE_SC2892 = 2892,
101 SCCNXP_TYPE_SC28202 = 28202,
102 SCCNXP_TYPE_SC68681 = 68681,
103 SCCNXP_TYPE_SC68692 = 68692,
104};
105
106struct sccnxp_port {
107 struct uart_driver uart;
108 struct uart_port port[SCCNXP_MAX_UARTS];
109
110 const char *name;
111 int irq;
112
113 u8 imr;
114 u8 addr_mask;
115 int freq_std;
116
117 int flags;
118#define SCCNXP_HAVE_IO 0x00000001
119#define SCCNXP_HAVE_MR0 0x00000002
120
121#ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
122 struct console console;
123#endif
124
125 struct mutex sccnxp_mutex;
126
127 struct sccnxp_pdata pdata;
128};
129
130static inline u8 sccnxp_raw_read(void __iomem *base, u8 reg, u8 shift)
131{
132 return readb(base + (reg << shift));
133}
134
135static inline void sccnxp_raw_write(void __iomem *base, u8 reg, u8 shift, u8 v)
136{
137 writeb(v, base + (reg << shift));
138}
139
140static inline u8 sccnxp_read(struct uart_port *port, u8 reg)
141{
142 struct sccnxp_port *s = dev_get_drvdata(port->dev);
143
144 return sccnxp_raw_read(port->membase, reg & s->addr_mask,
145 port->regshift);
146}
147
148static inline void sccnxp_write(struct uart_port *port, u8 reg, u8 v)
149{
150 struct sccnxp_port *s = dev_get_drvdata(port->dev);
151
152 sccnxp_raw_write(port->membase, reg & s->addr_mask, port->regshift, v);
153}
154
155static inline u8 sccnxp_port_read(struct uart_port *port, u8 reg)
156{
157 return sccnxp_read(port, (port->line << 3) + reg);
158}
159
160static inline void sccnxp_port_write(struct uart_port *port, u8 reg, u8 v)
161{
162 sccnxp_write(port, (port->line << 3) + reg, v);
163}
164
165static int sccnxp_update_best_err(int a, int b, int *besterr)
166{
167 int err = abs(a - b);
168
169 if ((*besterr < 0) || (*besterr > err)) {
170 *besterr = err;
171 return 0;
172 }
173
174 return 1;
175}
176
177struct baud_table {
178 u8 csr;
179 u8 acr;
180 u8 mr0;
181 int baud;
182};
183
184const struct baud_table baud_std[] = {
185 { 0, ACR_BAUD0, MR0_BAUD_NORMAL, 50, },
186 { 0, ACR_BAUD1, MR0_BAUD_NORMAL, 75, },
187 { 1, ACR_BAUD0, MR0_BAUD_NORMAL, 110, },
188 { 2, ACR_BAUD0, MR0_BAUD_NORMAL, 134, },
189 { 3, ACR_BAUD1, MR0_BAUD_NORMAL, 150, },
190 { 3, ACR_BAUD0, MR0_BAUD_NORMAL, 200, },
191 { 4, ACR_BAUD0, MR0_BAUD_NORMAL, 300, },
192 { 0, ACR_BAUD1, MR0_BAUD_EXT1, 450, },
193 { 1, ACR_BAUD0, MR0_BAUD_EXT2, 880, },
194 { 3, ACR_BAUD1, MR0_BAUD_EXT1, 900, },
195 { 5, ACR_BAUD0, MR0_BAUD_NORMAL, 600, },
196 { 7, ACR_BAUD0, MR0_BAUD_NORMAL, 1050, },
197 { 2, ACR_BAUD0, MR0_BAUD_EXT2, 1076, },
198 { 6, ACR_BAUD0, MR0_BAUD_NORMAL, 1200, },
199 { 10, ACR_BAUD1, MR0_BAUD_NORMAL, 1800, },
200 { 7, ACR_BAUD1, MR0_BAUD_NORMAL, 2000, },
201 { 8, ACR_BAUD0, MR0_BAUD_NORMAL, 2400, },
202 { 5, ACR_BAUD1, MR0_BAUD_EXT1, 3600, },
203 { 9, ACR_BAUD0, MR0_BAUD_NORMAL, 4800, },
204 { 10, ACR_BAUD0, MR0_BAUD_NORMAL, 7200, },
205 { 11, ACR_BAUD0, MR0_BAUD_NORMAL, 9600, },
206 { 8, ACR_BAUD0, MR0_BAUD_EXT1, 14400, },
207 { 12, ACR_BAUD1, MR0_BAUD_NORMAL, 19200, },
208 { 9, ACR_BAUD0, MR0_BAUD_EXT1, 28800, },
209 { 12, ACR_BAUD0, MR0_BAUD_NORMAL, 38400, },
210 { 11, ACR_BAUD0, MR0_BAUD_EXT1, 57600, },
211 { 12, ACR_BAUD1, MR0_BAUD_EXT1, 115200, },
212 { 12, ACR_BAUD0, MR0_BAUD_EXT1, 230400, },
213 { 0, 0, 0, 0 }
214};
215
216static void sccnxp_set_baud(struct uart_port *port, int baud)
217{
218 struct sccnxp_port *s = dev_get_drvdata(port->dev);
219 int div_std, tmp_baud, bestbaud = baud, besterr = -1;
220 u8 i, acr = 0, csr = 0, mr0 = 0;
221
222 /* Find best baud from table */
223 for (i = 0; baud_std[i].baud && besterr; i++) {
224 if (baud_std[i].mr0 && !(s->flags & SCCNXP_HAVE_MR0))
225 continue;
226 div_std = DIV_ROUND_CLOSEST(s->freq_std, baud_std[i].baud);
227 tmp_baud = DIV_ROUND_CLOSEST(port->uartclk, div_std);
228 if (!sccnxp_update_best_err(baud, tmp_baud, &besterr)) {
229 acr = baud_std[i].acr;
230 csr = baud_std[i].csr;
231 mr0 = baud_std[i].mr0;
232 bestbaud = tmp_baud;
233 }
234 }
235
236 if (s->flags & SCCNXP_HAVE_MR0) {
237 /* Enable FIFO, set half level for TX */
238 mr0 |= MR0_FIFO | MR0_TXLVL;
239 /* Update MR0 */
240 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR0);
241 sccnxp_port_write(port, SCCNXP_MR_REG, mr0);
242 }
243
244 sccnxp_port_write(port, SCCNXP_ACR_REG, acr | ACR_TIMER_MODE);
245 sccnxp_port_write(port, SCCNXP_CSR_REG, (csr << 4) | csr);
246
247 dev_dbg(port->dev, "Baudrate desired: %i, calculated: %i\n",
248 baud, bestbaud);
249}
250
251static void sccnxp_enable_irq(struct uart_port *port, int mask)
252{
253 struct sccnxp_port *s = dev_get_drvdata(port->dev);
254
255 s->imr |= mask << (port->line * 4);
256 sccnxp_write(port, SCCNXP_IMR_REG, s->imr);
257}
258
259static void sccnxp_disable_irq(struct uart_port *port, int mask)
260{
261 struct sccnxp_port *s = dev_get_drvdata(port->dev);
262
263 s->imr &= ~(mask << (port->line * 4));
264 sccnxp_write(port, SCCNXP_IMR_REG, s->imr);
265}
266
267static void sccnxp_set_bit(struct uart_port *port, int sig, int state)
268{
269 u8 bitmask;
270 struct sccnxp_port *s = dev_get_drvdata(port->dev);
271
272 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(sig)) {
273 bitmask = 1 << MCTRL_OBIT(s->pdata.mctrl_cfg[port->line], sig);
274 if (state)
275 sccnxp_write(port, SCCNXP_SOP_REG, bitmask);
276 else
277 sccnxp_write(port, SCCNXP_ROP_REG, bitmask);
278 }
279}
280
281static void sccnxp_handle_rx(struct uart_port *port)
282{
283 u8 sr;
284 unsigned int ch, flag;
285 struct tty_struct *tty = tty_port_tty_get(&port->state->port);
286
287 if (!tty)
288 return;
289
290 for (;;) {
291 sr = sccnxp_port_read(port, SCCNXP_SR_REG);
292 if (!(sr & SR_RXRDY))
293 break;
294 sr &= SR_PE | SR_FE | SR_OVR | SR_BRK;
295
296 ch = sccnxp_port_read(port, SCCNXP_RHR_REG);
297
298 port->icount.rx++;
299 flag = TTY_NORMAL;
300
301 if (unlikely(sr)) {
302 if (sr & SR_BRK) {
303 port->icount.brk++;
304 if (uart_handle_break(port))
305 continue;
306 } else if (sr & SR_PE)
307 port->icount.parity++;
308 else if (sr & SR_FE)
309 port->icount.frame++;
310 else if (sr & SR_OVR)
311 port->icount.overrun++;
312
313 sr &= port->read_status_mask;
314 if (sr & SR_BRK)
315 flag = TTY_BREAK;
316 else if (sr & SR_PE)
317 flag = TTY_PARITY;
318 else if (sr & SR_FE)
319 flag = TTY_FRAME;
320 else if (sr & SR_OVR)
321 flag = TTY_OVERRUN;
322 }
323
324 if (uart_handle_sysrq_char(port, ch))
325 continue;
326
327 if (sr & port->ignore_status_mask)
328 continue;
329
330 uart_insert_char(port, sr, SR_OVR, ch, flag);
331 }
332
333 tty_flip_buffer_push(tty);
334
335 tty_kref_put(tty);
336}
337
338static void sccnxp_handle_tx(struct uart_port *port)
339{
340 u8 sr;
341 struct circ_buf *xmit = &port->state->xmit;
342 struct sccnxp_port *s = dev_get_drvdata(port->dev);
343
344 if (unlikely(port->x_char)) {
345 sccnxp_port_write(port, SCCNXP_THR_REG, port->x_char);
346 port->icount.tx++;
347 port->x_char = 0;
348 return;
349 }
350
351 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
352 /* Disable TX if FIFO is empty */
353 if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXEMT) {
354 sccnxp_disable_irq(port, IMR_TXRDY);
355
356 /* Set direction to input */
357 if (s->flags & SCCNXP_HAVE_IO)
358 sccnxp_set_bit(port, DIR_OP, 0);
359 }
360 return;
361 }
362
363 while (!uart_circ_empty(xmit)) {
364 sr = sccnxp_port_read(port, SCCNXP_SR_REG);
365 if (!(sr & SR_TXRDY))
366 break;
367
368 sccnxp_port_write(port, SCCNXP_THR_REG, xmit->buf[xmit->tail]);
369 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
370 port->icount.tx++;
371 }
372
373 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
374 uart_write_wakeup(port);
375}
376
377static irqreturn_t sccnxp_ist(int irq, void *dev_id)
378{
379 int i;
380 u8 isr;
381 struct sccnxp_port *s = (struct sccnxp_port *)dev_id;
382
383 mutex_lock(&s->sccnxp_mutex);
384
385 for (;;) {
386 isr = sccnxp_read(&s->port[0], SCCNXP_ISR_REG);
387 isr &= s->imr;
388 if (!isr)
389 break;
390
391 dev_dbg(s->port[0].dev, "IRQ status: 0x%02x\n", isr);
392
393 for (i = 0; i < s->uart.nr; i++) {
394 if (isr & ISR_RXRDY(i))
395 sccnxp_handle_rx(&s->port[i]);
396 if (isr & ISR_TXRDY(i))
397 sccnxp_handle_tx(&s->port[i]);
398 }
399 }
400
401 mutex_unlock(&s->sccnxp_mutex);
402
403 return IRQ_HANDLED;
404}
405
406static void sccnxp_start_tx(struct uart_port *port)
407{
408 struct sccnxp_port *s = dev_get_drvdata(port->dev);
409
410 mutex_lock(&s->sccnxp_mutex);
411
412 /* Set direction to output */
413 if (s->flags & SCCNXP_HAVE_IO)
414 sccnxp_set_bit(port, DIR_OP, 1);
415
416 sccnxp_enable_irq(port, IMR_TXRDY);
417
418 mutex_unlock(&s->sccnxp_mutex);
419}
420
421static void sccnxp_stop_tx(struct uart_port *port)
422{
423 /* Do nothing */
424}
425
426static void sccnxp_stop_rx(struct uart_port *port)
427{
428 struct sccnxp_port *s = dev_get_drvdata(port->dev);
429
430 mutex_lock(&s->sccnxp_mutex);
431 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE);
432 mutex_unlock(&s->sccnxp_mutex);
433}
434
435static unsigned int sccnxp_tx_empty(struct uart_port *port)
436{
437 u8 val;
438 struct sccnxp_port *s = dev_get_drvdata(port->dev);
439
440 mutex_lock(&s->sccnxp_mutex);
441 val = sccnxp_port_read(port, SCCNXP_SR_REG);
442 mutex_unlock(&s->sccnxp_mutex);
443
444 return (val & SR_TXEMT) ? TIOCSER_TEMT : 0;
445}
446
447static void sccnxp_enable_ms(struct uart_port *port)
448{
449 /* Do nothing */
450}
451
452static void sccnxp_set_mctrl(struct uart_port *port, unsigned int mctrl)
453{
454 struct sccnxp_port *s = dev_get_drvdata(port->dev);
455
456 if (!(s->flags & SCCNXP_HAVE_IO))
457 return;
458
459 mutex_lock(&s->sccnxp_mutex);
460
461 sccnxp_set_bit(port, DTR_OP, mctrl & TIOCM_DTR);
462 sccnxp_set_bit(port, RTS_OP, mctrl & TIOCM_RTS);
463
464 mutex_unlock(&s->sccnxp_mutex);
465}
466
467static unsigned int sccnxp_get_mctrl(struct uart_port *port)
468{
469 u8 bitmask, ipr;
470 struct sccnxp_port *s = dev_get_drvdata(port->dev);
471 unsigned int mctrl = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR;
472
473 if (!(s->flags & SCCNXP_HAVE_IO))
474 return mctrl;
475
476 mutex_lock(&s->sccnxp_mutex);
477
478 ipr = ~sccnxp_read(port, SCCNXP_IPCR_REG);
479
480 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DSR_IP)) {
481 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
482 DSR_IP);
483 mctrl &= ~TIOCM_DSR;
484 mctrl |= (ipr & bitmask) ? TIOCM_DSR : 0;
485 }
486 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(CTS_IP)) {
487 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
488 CTS_IP);
489 mctrl &= ~TIOCM_CTS;
490 mctrl |= (ipr & bitmask) ? TIOCM_CTS : 0;
491 }
492 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DCD_IP)) {
493 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
494 DCD_IP);
495 mctrl &= ~TIOCM_CAR;
496 mctrl |= (ipr & bitmask) ? TIOCM_CAR : 0;
497 }
498 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(RNG_IP)) {
499 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
500 RNG_IP);
501 mctrl &= ~TIOCM_RNG;
502 mctrl |= (ipr & bitmask) ? TIOCM_RNG : 0;
503 }
504
505 mutex_unlock(&s->sccnxp_mutex);
506
507 return mctrl;
508}
509
510static void sccnxp_break_ctl(struct uart_port *port, int break_state)
511{
512 struct sccnxp_port *s = dev_get_drvdata(port->dev);
513
514 mutex_lock(&s->sccnxp_mutex);
515 sccnxp_port_write(port, SCCNXP_CR_REG, break_state ?
516 CR_CMD_START_BREAK : CR_CMD_STOP_BREAK);
517 mutex_unlock(&s->sccnxp_mutex);
518}
519
520static void sccnxp_set_termios(struct uart_port *port,
521 struct ktermios *termios, struct ktermios *old)
522{
523 struct sccnxp_port *s = dev_get_drvdata(port->dev);
524 u8 mr1, mr2;
525 int baud;
526
527 mutex_lock(&s->sccnxp_mutex);
528
529 /* Mask termios capabilities we don't support */
530 termios->c_cflag &= ~CMSPAR;
531 termios->c_iflag &= ~(IXON | IXOFF | IXANY);
532
533 /* Disable RX & TX, reset break condition, status and FIFOs */
534 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET |
535 CR_RX_DISABLE | CR_TX_DISABLE);
536 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET);
537 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET);
538 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET);
539
540 /* Word size */
541 switch (termios->c_cflag & CSIZE) {
542 case CS5:
543 mr1 = MR1_BITS_5;
544 break;
545 case CS6:
546 mr1 = MR1_BITS_6;
547 break;
548 case CS7:
549 mr1 = MR1_BITS_7;
550 break;
551 default:
552 case CS8:
553 mr1 = MR1_BITS_8;
554 break;
555 }
556
557 /* Parity */
558 if (termios->c_cflag & PARENB) {
559 if (termios->c_cflag & PARODD)
560 mr1 |= MR1_PAR_ODD;
561 } else
562 mr1 |= MR1_PAR_NO;
563
564 /* Stop bits */
565 mr2 = (termios->c_cflag & CSTOPB) ? MR2_STOP2 : MR2_STOP1;
566
567 /* Update desired format */
568 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR1);
569 sccnxp_port_write(port, SCCNXP_MR_REG, mr1);
570 sccnxp_port_write(port, SCCNXP_MR_REG, mr2);
571
572 /* Set read status mask */
573 port->read_status_mask = SR_OVR;
574 if (termios->c_iflag & INPCK)
575 port->read_status_mask |= SR_PE | SR_FE;
576 if (termios->c_iflag & (BRKINT | PARMRK))
577 port->read_status_mask |= SR_BRK;
578
579 /* Set status ignore mask */
580 port->ignore_status_mask = 0;
581 if (termios->c_iflag & IGNBRK)
582 port->ignore_status_mask |= SR_BRK;
583 if (!(termios->c_cflag & CREAD))
584 port->ignore_status_mask |= SR_PE | SR_OVR | SR_FE | SR_BRK;
585
586 /* Setup baudrate */
587 baud = uart_get_baud_rate(port, termios, old, 50,
588 (s->flags & SCCNXP_HAVE_MR0) ?
589 230400 : 38400);
590 sccnxp_set_baud(port, baud);
591
592 /* Update timeout according to new baud rate */
593 uart_update_timeout(port, termios->c_cflag, baud);
594
595 /* Enable RX & TX */
596 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE);
597
598 mutex_unlock(&s->sccnxp_mutex);
599}
600
601static int sccnxp_startup(struct uart_port *port)
602{
603 struct sccnxp_port *s = dev_get_drvdata(port->dev);
604
605 mutex_lock(&s->sccnxp_mutex);
606
607 if (s->flags & SCCNXP_HAVE_IO) {
608 /* Outputs are controlled manually */
609 sccnxp_write(port, SCCNXP_OPCR_REG, 0);
610 }
611
612 /* Reset break condition, status and FIFOs */
613 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET);
614 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET);
615 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET);
616 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET);
617
618 /* Enable RX & TX */
619 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE);
620
621 /* Enable RX interrupt */
622 sccnxp_enable_irq(port, IMR_RXRDY);
623
624 mutex_unlock(&s->sccnxp_mutex);
625
626 return 0;
627}
628
629static void sccnxp_shutdown(struct uart_port *port)
630{
631 struct sccnxp_port *s = dev_get_drvdata(port->dev);
632
633 mutex_lock(&s->sccnxp_mutex);
634
635 /* Disable interrupts */
636 sccnxp_disable_irq(port, IMR_TXRDY | IMR_RXRDY);
637
638 /* Disable TX & RX */
639 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE | CR_TX_DISABLE);
640
641 /* Leave direction to input */
642 if (s->flags & SCCNXP_HAVE_IO)
643 sccnxp_set_bit(port, DIR_OP, 0);
644
645 mutex_unlock(&s->sccnxp_mutex);
646}
647
648static const char *sccnxp_type(struct uart_port *port)
649{
650 struct sccnxp_port *s = dev_get_drvdata(port->dev);
651
652 return (port->type == PORT_SC26XX) ? s->name : NULL;
653}
654
655static void sccnxp_release_port(struct uart_port *port)
656{
657 /* Do nothing */
658}
659
660static int sccnxp_request_port(struct uart_port *port)
661{
662 /* Do nothing */
663 return 0;
664}
665
666static void sccnxp_config_port(struct uart_port *port, int flags)
667{
668 if (flags & UART_CONFIG_TYPE)
669 port->type = PORT_SC26XX;
670}
671
672static int sccnxp_verify_port(struct uart_port *port, struct serial_struct *s)
673{
674 if ((s->type == PORT_UNKNOWN) || (s->type == PORT_SC26XX))
675 return 0;
676 if (s->irq == port->irq)
677 return 0;
678
679 return -EINVAL;
680}
681
682static const struct uart_ops sccnxp_ops = {
683 .tx_empty = sccnxp_tx_empty,
684 .set_mctrl = sccnxp_set_mctrl,
685 .get_mctrl = sccnxp_get_mctrl,
686 .stop_tx = sccnxp_stop_tx,
687 .start_tx = sccnxp_start_tx,
688 .stop_rx = sccnxp_stop_rx,
689 .enable_ms = sccnxp_enable_ms,
690 .break_ctl = sccnxp_break_ctl,
691 .startup = sccnxp_startup,
692 .shutdown = sccnxp_shutdown,
693 .set_termios = sccnxp_set_termios,
694 .type = sccnxp_type,
695 .release_port = sccnxp_release_port,
696 .request_port = sccnxp_request_port,
697 .config_port = sccnxp_config_port,
698 .verify_port = sccnxp_verify_port,
699};
700
701#ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
702static void sccnxp_console_putchar(struct uart_port *port, int c)
703{
704 int tryes = 100000;
705
706 while (tryes--) {
707 if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXRDY) {
708 sccnxp_port_write(port, SCCNXP_THR_REG, c);
709 break;
710 }
711 barrier();
712 }
713}
714
715static void sccnxp_console_write(struct console *co, const char *c, unsigned n)
716{
717 struct sccnxp_port *s = (struct sccnxp_port *)co->data;
718 struct uart_port *port = &s->port[co->index];
719
720 mutex_lock(&s->sccnxp_mutex);
721 uart_console_write(port, c, n, sccnxp_console_putchar);
722 mutex_unlock(&s->sccnxp_mutex);
723}
724
725static int sccnxp_console_setup(struct console *co, char *options)
726{
727 struct sccnxp_port *s = (struct sccnxp_port *)co->data;
728 struct uart_port *port = &s->port[(co->index > 0) ? co->index : 0];
729 int baud = 9600, bits = 8, parity = 'n', flow = 'n';
730
731 if (options)
732 uart_parse_options(options, &baud, &parity, &bits, &flow);
733
734 return uart_set_options(port, co, baud, parity, bits, flow);
735}
736#endif
737
738static int __devinit sccnxp_probe(struct platform_device *pdev)
739{
740 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
741 int chiptype = pdev->id_entry->driver_data;
742 struct sccnxp_pdata *pdata = dev_get_platdata(&pdev->dev);
743 int i, ret, fifosize, freq_min, freq_max;
744 struct sccnxp_port *s;
745 void __iomem *membase;
746
747 if (!res) {
748 dev_err(&pdev->dev, "Missing memory resource data\n");
749 return -EADDRNOTAVAIL;
750 }
751
752 dev_set_name(&pdev->dev, SCCNXP_NAME);
753
754 s = devm_kzalloc(&pdev->dev, sizeof(struct sccnxp_port), GFP_KERNEL);
755 if (!s) {
756 dev_err(&pdev->dev, "Error allocating port structure\n");
757 return -ENOMEM;
758 }
759 platform_set_drvdata(pdev, s);
760
761 mutex_init(&s->sccnxp_mutex);
762
763 /* Individual chip settings */
764 switch (chiptype) {
765 case SCCNXP_TYPE_SC2681:
766 s->name = "SC2681";
767 s->uart.nr = 2;
768 s->freq_std = 3686400;
769 s->addr_mask = 0x0f;
770 s->flags = SCCNXP_HAVE_IO;
771 fifosize = 3;
772 freq_min = 1000000;
773 freq_max = 4000000;
774 break;
775 case SCCNXP_TYPE_SC2691:
776 s->name = "SC2691";
777 s->uart.nr = 1;
778 s->freq_std = 3686400;
779 s->addr_mask = 0x07;
780 s->flags = 0;
781 fifosize = 3;
782 freq_min = 1000000;
783 freq_max = 4000000;
784 break;
785 case SCCNXP_TYPE_SC2692:
786 s->name = "SC2692";
787 s->uart.nr = 2;
788 s->freq_std = 3686400;
789 s->addr_mask = 0x0f;
790 s->flags = SCCNXP_HAVE_IO;
791 fifosize = 3;
792 freq_min = 1000000;
793 freq_max = 4000000;
794 break;
795 case SCCNXP_TYPE_SC2891:
796 s->name = "SC2891";
797 s->uart.nr = 1;
798 s->freq_std = 3686400;
799 s->addr_mask = 0x0f;
800 s->flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0;
801 fifosize = 16;
802 freq_min = 100000;
803 freq_max = 8000000;
804 break;
805 case SCCNXP_TYPE_SC2892:
806 s->name = "SC2892";
807 s->uart.nr = 2;
808 s->freq_std = 3686400;
809 s->addr_mask = 0x0f;
810 s->flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0;
811 fifosize = 16;
812 freq_min = 100000;
813 freq_max = 8000000;
814 break;
815 case SCCNXP_TYPE_SC28202:
816 s->name = "SC28202";
817 s->uart.nr = 2;
818 s->freq_std = 14745600;
819 s->addr_mask = 0x7f;
820 s->flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0;
821 fifosize = 256;
822 freq_min = 1000000;
823 freq_max = 50000000;
824 break;
825 case SCCNXP_TYPE_SC68681:
826 s->name = "SC68681";
827 s->uart.nr = 2;
828 s->freq_std = 3686400;
829 s->addr_mask = 0x0f;
830 s->flags = SCCNXP_HAVE_IO;
831 fifosize = 3;
832 freq_min = 1000000;
833 freq_max = 4000000;
834 break;
835 case SCCNXP_TYPE_SC68692:
836 s->name = "SC68692";
837 s->uart.nr = 2;
838 s->freq_std = 3686400;
839 s->addr_mask = 0x0f;
840 s->flags = SCCNXP_HAVE_IO;
841 fifosize = 3;
842 freq_min = 1000000;
843 freq_max = 4000000;
844 break;
845 default:
846 dev_err(&pdev->dev, "Unsupported chip type %i\n", chiptype);
847 ret = -ENOTSUPP;
848 goto err_out;
849 }
850
851 if (!pdata) {
852 dev_warn(&pdev->dev,
853 "No platform data supplied, using defaults\n");
854 s->pdata.frequency = s->freq_std;
855 } else
856 memcpy(&s->pdata, pdata, sizeof(struct sccnxp_pdata));
857
858 s->irq = platform_get_irq(pdev, 0);
859 if (s->irq <= 0) {
860 dev_err(&pdev->dev, "Missing irq resource data\n");
861 ret = -ENXIO;
862 goto err_out;
863 }
864
865 /* Check input frequency */
866 if ((s->pdata.frequency < freq_min) ||
867 (s->pdata.frequency > freq_max)) {
868 dev_err(&pdev->dev, "Frequency out of bounds\n");
869 ret = -EINVAL;
870 goto err_out;
871 }
872
873 membase = devm_request_and_ioremap(&pdev->dev, res);
874 if (!membase) {
875 dev_err(&pdev->dev, "Failed to ioremap\n");
876 ret = -EIO;
877 goto err_out;
878 }
879
880 s->uart.owner = THIS_MODULE;
881 s->uart.dev_name = "ttySC";
882 s->uart.major = SCCNXP_MAJOR;
883 s->uart.minor = SCCNXP_MINOR;
884#ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
885 s->uart.cons = &s->console;
886 s->uart.cons->device = uart_console_device;
887 s->uart.cons->write = sccnxp_console_write;
888 s->uart.cons->setup = sccnxp_console_setup;
889 s->uart.cons->flags = CON_PRINTBUFFER;
890 s->uart.cons->index = -1;
891 s->uart.cons->data = s;
892 strcpy(s->uart.cons->name, "ttySC");
893#endif
894 ret = uart_register_driver(&s->uart);
895 if (ret) {
896 dev_err(&pdev->dev, "Registering UART driver failed\n");
897 goto err_out;
898 }
899
900 for (i = 0; i < s->uart.nr; i++) {
901 s->port[i].line = i;
902 s->port[i].dev = &pdev->dev;
903 s->port[i].irq = s->irq;
904 s->port[i].type = PORT_SC26XX;
905 s->port[i].fifosize = fifosize;
906 s->port[i].flags = UPF_SKIP_TEST | UPF_FIXED_TYPE;
907 s->port[i].iotype = UPIO_MEM;
908 s->port[i].mapbase = res->start;
909 s->port[i].membase = membase;
910 s->port[i].regshift = s->pdata.reg_shift;
911 s->port[i].uartclk = s->pdata.frequency;
912 s->port[i].ops = &sccnxp_ops;
913 uart_add_one_port(&s->uart, &s->port[i]);
914 /* Set direction to input */
915 if (s->flags & SCCNXP_HAVE_IO)
916 sccnxp_set_bit(&s->port[i], DIR_OP, 0);
917 }
918
919 /* Disable interrupts */
920 s->imr = 0;
921 sccnxp_write(&s->port[0], SCCNXP_IMR_REG, 0);
922
923 /* Board specific configure */
924 if (s->pdata.init)
925 s->pdata.init();
926
927 ret = devm_request_threaded_irq(&pdev->dev, s->irq, NULL, sccnxp_ist,
928 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
929 dev_name(&pdev->dev), s);
930 if (!ret)
931 return 0;
932
933 dev_err(&pdev->dev, "Unable to reguest IRQ %i\n", s->irq);
934
935err_out:
936 platform_set_drvdata(pdev, NULL);
937
938 return ret;
939}
940
941static int __devexit sccnxp_remove(struct platform_device *pdev)
942{
943 int i;
944 struct sccnxp_port *s = platform_get_drvdata(pdev);
945
946 devm_free_irq(&pdev->dev, s->irq, s);
947
948 for (i = 0; i < s->uart.nr; i++)
949 uart_remove_one_port(&s->uart, &s->port[i]);
950
951 uart_unregister_driver(&s->uart);
952 platform_set_drvdata(pdev, NULL);
953
954 if (s->pdata.exit)
955 s->pdata.exit();
956
957 return 0;
958}
959
960static const struct platform_device_id sccnxp_id_table[] = {
961 { "sc2681", SCCNXP_TYPE_SC2681 },
962 { "sc2691", SCCNXP_TYPE_SC2691 },
963 { "sc2692", SCCNXP_TYPE_SC2692 },
964 { "sc2891", SCCNXP_TYPE_SC2891 },
965 { "sc2892", SCCNXP_TYPE_SC2892 },
966 { "sc28202", SCCNXP_TYPE_SC28202 },
967 { "sc68681", SCCNXP_TYPE_SC68681 },
968 { "sc68692", SCCNXP_TYPE_SC68692 },
969};
970MODULE_DEVICE_TABLE(platform, sccnxp_id_table);
971
972static struct platform_driver sccnxp_uart_driver = {
973 .driver = {
974 .name = SCCNXP_NAME,
975 .owner = THIS_MODULE,
976 },
977 .probe = sccnxp_probe,
978 .remove = __devexit_p(sccnxp_remove),
979 .id_table = sccnxp_id_table,
980};
981module_platform_driver(sccnxp_uart_driver);
982
983MODULE_LICENSE("GPL v2");
984MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
985MODULE_DESCRIPTION("SCCNXP serial driver");
diff --git a/drivers/tty/serial/serial_core.c b/drivers/tty/serial/serial_core.c
index a21dc8e3b7c0..046279ce3e8d 100644
--- a/drivers/tty/serial/serial_core.c
+++ b/drivers/tty/serial/serial_core.c
@@ -159,7 +159,7 @@ static int uart_port_startup(struct tty_struct *tty, struct uart_state *state,
159 retval = uport->ops->startup(uport); 159 retval = uport->ops->startup(uport);
160 if (retval == 0) { 160 if (retval == 0) {
161 if (uart_console(uport) && uport->cons->cflag) { 161 if (uart_console(uport) && uport->cons->cflag) {
162 tty->termios->c_cflag = uport->cons->cflag; 162 tty->termios.c_cflag = uport->cons->cflag;
163 uport->cons->cflag = 0; 163 uport->cons->cflag = 0;
164 } 164 }
165 /* 165 /*
@@ -172,11 +172,11 @@ static int uart_port_startup(struct tty_struct *tty, struct uart_state *state,
172 * Setup the RTS and DTR signals once the 172 * Setup the RTS and DTR signals once the
173 * port is open and ready to respond. 173 * port is open and ready to respond.
174 */ 174 */
175 if (tty->termios->c_cflag & CBAUD) 175 if (tty->termios.c_cflag & CBAUD)
176 uart_set_mctrl(uport, TIOCM_RTS | TIOCM_DTR); 176 uart_set_mctrl(uport, TIOCM_RTS | TIOCM_DTR);
177 } 177 }
178 178
179 if (port->flags & ASYNC_CTS_FLOW) { 179 if (tty_port_cts_enabled(port)) {
180 spin_lock_irq(&uport->lock); 180 spin_lock_irq(&uport->lock);
181 if (!(uport->ops->get_mctrl(uport) & TIOCM_CTS)) 181 if (!(uport->ops->get_mctrl(uport) & TIOCM_CTS))
182 tty->hw_stopped = 1; 182 tty->hw_stopped = 1;
@@ -240,7 +240,7 @@ static void uart_shutdown(struct tty_struct *tty, struct uart_state *state)
240 /* 240 /*
241 * Turn off DTR and RTS early. 241 * Turn off DTR and RTS early.
242 */ 242 */
243 if (!tty || (tty->termios->c_cflag & HUPCL)) 243 if (!tty || (tty->termios.c_cflag & HUPCL))
244 uart_clear_mctrl(uport, TIOCM_DTR | TIOCM_RTS); 244 uart_clear_mctrl(uport, TIOCM_DTR | TIOCM_RTS);
245 245
246 uart_port_shutdown(port); 246 uart_port_shutdown(port);
@@ -440,10 +440,10 @@ static void uart_change_speed(struct tty_struct *tty, struct uart_state *state,
440 * If we have no tty, termios, or the port does not exist, 440 * If we have no tty, termios, or the port does not exist,
441 * then we can't set the parameters for this port. 441 * then we can't set the parameters for this port.
442 */ 442 */
443 if (!tty || !tty->termios || uport->type == PORT_UNKNOWN) 443 if (!tty || uport->type == PORT_UNKNOWN)
444 return; 444 return;
445 445
446 termios = tty->termios; 446 termios = &tty->termios;
447 447
448 /* 448 /*
449 * Set flags based on termios cflag 449 * Set flags based on termios cflag
@@ -614,7 +614,7 @@ static void uart_throttle(struct tty_struct *tty)
614 if (I_IXOFF(tty)) 614 if (I_IXOFF(tty))
615 uart_send_xchar(tty, STOP_CHAR(tty)); 615 uart_send_xchar(tty, STOP_CHAR(tty));
616 616
617 if (tty->termios->c_cflag & CRTSCTS) 617 if (tty->termios.c_cflag & CRTSCTS)
618 uart_clear_mctrl(state->uart_port, TIOCM_RTS); 618 uart_clear_mctrl(state->uart_port, TIOCM_RTS);
619} 619}
620 620
@@ -630,42 +630,48 @@ static void uart_unthrottle(struct tty_struct *tty)
630 uart_send_xchar(tty, START_CHAR(tty)); 630 uart_send_xchar(tty, START_CHAR(tty));
631 } 631 }
632 632
633 if (tty->termios->c_cflag & CRTSCTS) 633 if (tty->termios.c_cflag & CRTSCTS)
634 uart_set_mctrl(port, TIOCM_RTS); 634 uart_set_mctrl(port, TIOCM_RTS);
635} 635}
636 636
637static int uart_get_info(struct uart_state *state, 637static void uart_get_info(struct tty_port *port,
638 struct serial_struct __user *retinfo) 638 struct uart_state *state,
639 struct serial_struct *retinfo)
639{ 640{
640 struct uart_port *uport = state->uart_port; 641 struct uart_port *uport = state->uart_port;
641 struct tty_port *port = &state->port;
642 struct serial_struct tmp;
643
644 memset(&tmp, 0, sizeof(tmp));
645 642
646 /* Ensure the state we copy is consistent and no hardware changes 643 memset(retinfo, 0, sizeof(*retinfo));
647 occur as we go */
648 mutex_lock(&port->mutex);
649 644
650 tmp.type = uport->type; 645 retinfo->type = uport->type;
651 tmp.line = uport->line; 646 retinfo->line = uport->line;
652 tmp.port = uport->iobase; 647 retinfo->port = uport->iobase;
653 if (HIGH_BITS_OFFSET) 648 if (HIGH_BITS_OFFSET)
654 tmp.port_high = (long) uport->iobase >> HIGH_BITS_OFFSET; 649 retinfo->port_high = (long) uport->iobase >> HIGH_BITS_OFFSET;
655 tmp.irq = uport->irq; 650 retinfo->irq = uport->irq;
656 tmp.flags = uport->flags; 651 retinfo->flags = uport->flags;
657 tmp.xmit_fifo_size = uport->fifosize; 652 retinfo->xmit_fifo_size = uport->fifosize;
658 tmp.baud_base = uport->uartclk / 16; 653 retinfo->baud_base = uport->uartclk / 16;
659 tmp.close_delay = jiffies_to_msecs(port->close_delay) / 10; 654 retinfo->close_delay = jiffies_to_msecs(port->close_delay) / 10;
660 tmp.closing_wait = port->closing_wait == ASYNC_CLOSING_WAIT_NONE ? 655 retinfo->closing_wait = port->closing_wait == ASYNC_CLOSING_WAIT_NONE ?
661 ASYNC_CLOSING_WAIT_NONE : 656 ASYNC_CLOSING_WAIT_NONE :
662 jiffies_to_msecs(port->closing_wait) / 10; 657 jiffies_to_msecs(port->closing_wait) / 10;
663 tmp.custom_divisor = uport->custom_divisor; 658 retinfo->custom_divisor = uport->custom_divisor;
664 tmp.hub6 = uport->hub6; 659 retinfo->hub6 = uport->hub6;
665 tmp.io_type = uport->iotype; 660 retinfo->io_type = uport->iotype;
666 tmp.iomem_reg_shift = uport->regshift; 661 retinfo->iomem_reg_shift = uport->regshift;
667 tmp.iomem_base = (void *)(unsigned long)uport->mapbase; 662 retinfo->iomem_base = (void *)(unsigned long)uport->mapbase;
663}
668 664
665static int uart_get_info_user(struct uart_state *state,
666 struct serial_struct __user *retinfo)
667{
668 struct tty_port *port = &state->port;
669 struct serial_struct tmp;
670
671 /* Ensure the state we copy is consistent and no hardware changes
672 occur as we go */
673 mutex_lock(&port->mutex);
674 uart_get_info(port, state, &tmp);
669 mutex_unlock(&port->mutex); 675 mutex_unlock(&port->mutex);
670 676
671 if (copy_to_user(retinfo, &tmp, sizeof(*retinfo))) 677 if (copy_to_user(retinfo, &tmp, sizeof(*retinfo)))
@@ -673,42 +679,30 @@ static int uart_get_info(struct uart_state *state,
673 return 0; 679 return 0;
674} 680}
675 681
676static int uart_set_info(struct tty_struct *tty, struct uart_state *state, 682static int uart_set_info(struct tty_struct *tty, struct tty_port *port,
677 struct serial_struct __user *newinfo) 683 struct uart_state *state,
684 struct serial_struct *new_info)
678{ 685{
679 struct serial_struct new_serial;
680 struct uart_port *uport = state->uart_port; 686 struct uart_port *uport = state->uart_port;
681 struct tty_port *port = &state->port;
682 unsigned long new_port; 687 unsigned long new_port;
683 unsigned int change_irq, change_port, closing_wait; 688 unsigned int change_irq, change_port, closing_wait;
684 unsigned int old_custom_divisor, close_delay; 689 unsigned int old_custom_divisor, close_delay;
685 upf_t old_flags, new_flags; 690 upf_t old_flags, new_flags;
686 int retval = 0; 691 int retval = 0;
687 692
688 if (copy_from_user(&new_serial, newinfo, sizeof(new_serial))) 693 new_port = new_info->port;
689 return -EFAULT;
690
691 new_port = new_serial.port;
692 if (HIGH_BITS_OFFSET) 694 if (HIGH_BITS_OFFSET)
693 new_port += (unsigned long) new_serial.port_high << HIGH_BITS_OFFSET; 695 new_port += (unsigned long) new_info->port_high << HIGH_BITS_OFFSET;
694 696
695 new_serial.irq = irq_canonicalize(new_serial.irq); 697 new_info->irq = irq_canonicalize(new_info->irq);
696 close_delay = msecs_to_jiffies(new_serial.close_delay * 10); 698 close_delay = msecs_to_jiffies(new_info->close_delay * 10);
697 closing_wait = new_serial.closing_wait == ASYNC_CLOSING_WAIT_NONE ? 699 closing_wait = new_info->closing_wait == ASYNC_CLOSING_WAIT_NONE ?
698 ASYNC_CLOSING_WAIT_NONE : 700 ASYNC_CLOSING_WAIT_NONE :
699 msecs_to_jiffies(new_serial.closing_wait * 10); 701 msecs_to_jiffies(new_info->closing_wait * 10);
700 702
701 /*
702 * This semaphore protects port->count. It is also
703 * very useful to prevent opens. Also, take the
704 * port configuration semaphore to make sure that a
705 * module insertion/removal doesn't change anything
706 * under us.
707 */
708 mutex_lock(&port->mutex);
709 703
710 change_irq = !(uport->flags & UPF_FIXED_PORT) 704 change_irq = !(uport->flags & UPF_FIXED_PORT)
711 && new_serial.irq != uport->irq; 705 && new_info->irq != uport->irq;
712 706
713 /* 707 /*
714 * Since changing the 'type' of the port changes its resource 708 * Since changing the 'type' of the port changes its resource
@@ -717,29 +711,29 @@ static int uart_set_info(struct tty_struct *tty, struct uart_state *state,
717 */ 711 */
718 change_port = !(uport->flags & UPF_FIXED_PORT) 712 change_port = !(uport->flags & UPF_FIXED_PORT)
719 && (new_port != uport->iobase || 713 && (new_port != uport->iobase ||
720 (unsigned long)new_serial.iomem_base != uport->mapbase || 714 (unsigned long)new_info->iomem_base != uport->mapbase ||
721 new_serial.hub6 != uport->hub6 || 715 new_info->hub6 != uport->hub6 ||
722 new_serial.io_type != uport->iotype || 716 new_info->io_type != uport->iotype ||
723 new_serial.iomem_reg_shift != uport->regshift || 717 new_info->iomem_reg_shift != uport->regshift ||
724 new_serial.type != uport->type); 718 new_info->type != uport->type);
725 719
726 old_flags = uport->flags; 720 old_flags = uport->flags;
727 new_flags = new_serial.flags; 721 new_flags = new_info->flags;
728 old_custom_divisor = uport->custom_divisor; 722 old_custom_divisor = uport->custom_divisor;
729 723
730 if (!capable(CAP_SYS_ADMIN)) { 724 if (!capable(CAP_SYS_ADMIN)) {
731 retval = -EPERM; 725 retval = -EPERM;
732 if (change_irq || change_port || 726 if (change_irq || change_port ||
733 (new_serial.baud_base != uport->uartclk / 16) || 727 (new_info->baud_base != uport->uartclk / 16) ||
734 (close_delay != port->close_delay) || 728 (close_delay != port->close_delay) ||
735 (closing_wait != port->closing_wait) || 729 (closing_wait != port->closing_wait) ||
736 (new_serial.xmit_fifo_size && 730 (new_info->xmit_fifo_size &&
737 new_serial.xmit_fifo_size != uport->fifosize) || 731 new_info->xmit_fifo_size != uport->fifosize) ||
738 (((new_flags ^ old_flags) & ~UPF_USR_MASK) != 0)) 732 (((new_flags ^ old_flags) & ~UPF_USR_MASK) != 0))
739 goto exit; 733 goto exit;
740 uport->flags = ((uport->flags & ~UPF_USR_MASK) | 734 uport->flags = ((uport->flags & ~UPF_USR_MASK) |
741 (new_flags & UPF_USR_MASK)); 735 (new_flags & UPF_USR_MASK));
742 uport->custom_divisor = new_serial.custom_divisor; 736 uport->custom_divisor = new_info->custom_divisor;
743 goto check_and_exit; 737 goto check_and_exit;
744 } 738 }
745 739
@@ -747,10 +741,10 @@ static int uart_set_info(struct tty_struct *tty, struct uart_state *state,
747 * Ask the low level driver to verify the settings. 741 * Ask the low level driver to verify the settings.
748 */ 742 */
749 if (uport->ops->verify_port) 743 if (uport->ops->verify_port)
750 retval = uport->ops->verify_port(uport, &new_serial); 744 retval = uport->ops->verify_port(uport, new_info);
751 745
752 if ((new_serial.irq >= nr_irqs) || (new_serial.irq < 0) || 746 if ((new_info->irq >= nr_irqs) || (new_info->irq < 0) ||
753 (new_serial.baud_base < 9600)) 747 (new_info->baud_base < 9600))
754 retval = -EINVAL; 748 retval = -EINVAL;
755 749
756 if (retval) 750 if (retval)
@@ -790,11 +784,11 @@ static int uart_set_info(struct tty_struct *tty, struct uart_state *state,
790 uport->ops->release_port(uport); 784 uport->ops->release_port(uport);
791 785
792 uport->iobase = new_port; 786 uport->iobase = new_port;
793 uport->type = new_serial.type; 787 uport->type = new_info->type;
794 uport->hub6 = new_serial.hub6; 788 uport->hub6 = new_info->hub6;
795 uport->iotype = new_serial.io_type; 789 uport->iotype = new_info->io_type;
796 uport->regshift = new_serial.iomem_reg_shift; 790 uport->regshift = new_info->iomem_reg_shift;
797 uport->mapbase = (unsigned long)new_serial.iomem_base; 791 uport->mapbase = (unsigned long)new_info->iomem_base;
798 792
799 /* 793 /*
800 * Claim and map the new regions 794 * Claim and map the new regions
@@ -835,16 +829,16 @@ static int uart_set_info(struct tty_struct *tty, struct uart_state *state,
835 } 829 }
836 830
837 if (change_irq) 831 if (change_irq)
838 uport->irq = new_serial.irq; 832 uport->irq = new_info->irq;
839 if (!(uport->flags & UPF_FIXED_PORT)) 833 if (!(uport->flags & UPF_FIXED_PORT))
840 uport->uartclk = new_serial.baud_base * 16; 834 uport->uartclk = new_info->baud_base * 16;
841 uport->flags = (uport->flags & ~UPF_CHANGE_MASK) | 835 uport->flags = (uport->flags & ~UPF_CHANGE_MASK) |
842 (new_flags & UPF_CHANGE_MASK); 836 (new_flags & UPF_CHANGE_MASK);
843 uport->custom_divisor = new_serial.custom_divisor; 837 uport->custom_divisor = new_info->custom_divisor;
844 port->close_delay = close_delay; 838 port->close_delay = close_delay;
845 port->closing_wait = closing_wait; 839 port->closing_wait = closing_wait;
846 if (new_serial.xmit_fifo_size) 840 if (new_info->xmit_fifo_size)
847 uport->fifosize = new_serial.xmit_fifo_size; 841 uport->fifosize = new_info->xmit_fifo_size;
848 if (port->tty) 842 if (port->tty)
849 port->tty->low_latency = 843 port->tty->low_latency =
850 (uport->flags & UPF_LOW_LATENCY) ? 1 : 0; 844 (uport->flags & UPF_LOW_LATENCY) ? 1 : 0;
@@ -873,6 +867,28 @@ static int uart_set_info(struct tty_struct *tty, struct uart_state *state,
873 } else 867 } else
874 retval = uart_startup(tty, state, 1); 868 retval = uart_startup(tty, state, 1);
875 exit: 869 exit:
870 return retval;
871}
872
873static int uart_set_info_user(struct tty_struct *tty, struct uart_state *state,
874 struct serial_struct __user *newinfo)
875{
876 struct serial_struct new_serial;
877 struct tty_port *port = &state->port;
878 int retval;
879
880 if (copy_from_user(&new_serial, newinfo, sizeof(new_serial)))
881 return -EFAULT;
882
883 /*
884 * This semaphore protects port->count. It is also
885 * very useful to prevent opens. Also, take the
886 * port configuration semaphore to make sure that a
887 * module insertion/removal doesn't change anything
888 * under us.
889 */
890 mutex_lock(&port->mutex);
891 retval = uart_set_info(tty, port, state, &new_serial);
876 mutex_unlock(&port->mutex); 892 mutex_unlock(&port->mutex);
877 return retval; 893 return retval;
878} 894}
@@ -1115,11 +1131,11 @@ uart_ioctl(struct tty_struct *tty, unsigned int cmd,
1115 */ 1131 */
1116 switch (cmd) { 1132 switch (cmd) {
1117 case TIOCGSERIAL: 1133 case TIOCGSERIAL:
1118 ret = uart_get_info(state, uarg); 1134 ret = uart_get_info_user(state, uarg);
1119 break; 1135 break;
1120 1136
1121 case TIOCSSERIAL: 1137 case TIOCSSERIAL:
1122 ret = uart_set_info(tty, state, uarg); 1138 ret = uart_set_info_user(tty, state, uarg);
1123 break; 1139 break;
1124 1140
1125 case TIOCSERCONFIG: 1141 case TIOCSERCONFIG:
@@ -1187,7 +1203,7 @@ static void uart_set_ldisc(struct tty_struct *tty)
1187 struct uart_port *uport = state->uart_port; 1203 struct uart_port *uport = state->uart_port;
1188 1204
1189 if (uport->ops->set_ldisc) 1205 if (uport->ops->set_ldisc)
1190 uport->ops->set_ldisc(uport, tty->termios->c_line); 1206 uport->ops->set_ldisc(uport, tty->termios.c_line);
1191} 1207}
1192 1208
1193static void uart_set_termios(struct tty_struct *tty, 1209static void uart_set_termios(struct tty_struct *tty,
@@ -1195,7 +1211,7 @@ static void uart_set_termios(struct tty_struct *tty,
1195{ 1211{
1196 struct uart_state *state = tty->driver_data; 1212 struct uart_state *state = tty->driver_data;
1197 unsigned long flags; 1213 unsigned long flags;
1198 unsigned int cflag = tty->termios->c_cflag; 1214 unsigned int cflag = tty->termios.c_cflag;
1199 1215
1200 1216
1201 /* 1217 /*
@@ -1206,9 +1222,9 @@ static void uart_set_termios(struct tty_struct *tty,
1206 */ 1222 */
1207#define RELEVANT_IFLAG(iflag) ((iflag) & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK)) 1223#define RELEVANT_IFLAG(iflag) ((iflag) & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
1208 if ((cflag ^ old_termios->c_cflag) == 0 && 1224 if ((cflag ^ old_termios->c_cflag) == 0 &&
1209 tty->termios->c_ospeed == old_termios->c_ospeed && 1225 tty->termios.c_ospeed == old_termios->c_ospeed &&
1210 tty->termios->c_ispeed == old_termios->c_ispeed && 1226 tty->termios.c_ispeed == old_termios->c_ispeed &&
1211 RELEVANT_IFLAG(tty->termios->c_iflag ^ old_termios->c_iflag) == 0) { 1227 RELEVANT_IFLAG(tty->termios.c_iflag ^ old_termios->c_iflag) == 0) {
1212 return; 1228 return;
1213 } 1229 }
1214 1230
@@ -1960,8 +1976,8 @@ int uart_resume_port(struct uart_driver *drv, struct uart_port *uport)
1960 /* 1976 /*
1961 * If that's unset, use the tty termios setting. 1977 * If that's unset, use the tty termios setting.
1962 */ 1978 */
1963 if (port->tty && port->tty->termios && termios.c_cflag == 0) 1979 if (port->tty && termios.c_cflag == 0)
1964 termios = *(port->tty->termios); 1980 termios = port->tty->termios;
1965 1981
1966 if (console_suspend_enabled) 1982 if (console_suspend_enabled)
1967 uart_change_pm(state, 0); 1983 uart_change_pm(state, 0);
@@ -2293,6 +2309,36 @@ struct tty_driver *uart_console_device(struct console *co, int *index)
2293 return p->tty_driver; 2309 return p->tty_driver;
2294} 2310}
2295 2311
2312static ssize_t uart_get_attr_uartclk(struct device *dev,
2313 struct device_attribute *attr, char *buf)
2314{
2315 int ret;
2316 struct tty_port *port = dev_get_drvdata(dev);
2317 struct uart_state *state = container_of(port, struct uart_state, port);
2318
2319 mutex_lock(&state->port.mutex);
2320 ret = snprintf(buf, PAGE_SIZE, "%d\n", state->uart_port->uartclk);
2321 mutex_unlock(&state->port.mutex);
2322
2323 return ret;
2324}
2325
2326static DEVICE_ATTR(uartclk, S_IRUSR | S_IRGRP, uart_get_attr_uartclk, NULL);
2327
2328static struct attribute *tty_dev_attrs[] = {
2329 &dev_attr_uartclk.attr,
2330 NULL,
2331 };
2332
2333static const struct attribute_group tty_dev_attr_group = {
2334 .attrs = tty_dev_attrs,
2335 };
2336
2337static const struct attribute_group *tty_dev_attr_groups[] = {
2338 &tty_dev_attr_group,
2339 NULL
2340 };
2341
2296/** 2342/**
2297 * uart_add_one_port - attach a driver-defined port structure 2343 * uart_add_one_port - attach a driver-defined port structure
2298 * @drv: pointer to the uart low level driver structure for this port 2344 * @drv: pointer to the uart low level driver structure for this port
@@ -2346,7 +2392,8 @@ int uart_add_one_port(struct uart_driver *drv, struct uart_port *uport)
2346 * Register the port whether it's detected or not. This allows 2392 * Register the port whether it's detected or not. This allows
2347 * setserial to be used to alter this ports parameters. 2393 * setserial to be used to alter this ports parameters.
2348 */ 2394 */
2349 tty_dev = tty_register_device(drv->tty_driver, uport->line, uport->dev); 2395 tty_dev = tty_port_register_device_attr(port, drv->tty_driver,
2396 uport->line, uport->dev, port, tty_dev_attr_groups);
2350 if (likely(!IS_ERR(tty_dev))) { 2397 if (likely(!IS_ERR(tty_dev))) {
2351 device_set_wakeup_capable(tty_dev, 1); 2398 device_set_wakeup_capable(tty_dev, 1);
2352 } else { 2399 } else {
@@ -2492,7 +2539,7 @@ void uart_handle_cts_change(struct uart_port *uport, unsigned int status)
2492 2539
2493 uport->icount.cts++; 2540 uport->icount.cts++;
2494 2541
2495 if (port->flags & ASYNC_CTS_FLOW) { 2542 if (tty_port_cts_enabled(port)) {
2496 if (tty->hw_stopped) { 2543 if (tty->hw_stopped) {
2497 if (status) { 2544 if (status) {
2498 tty->hw_stopped = 0; 2545 tty->hw_stopped = 0;
diff --git a/drivers/tty/serial/sirfsoc_uart.c b/drivers/tty/serial/sirfsoc_uart.c
index 5b3eda2024fe..a9e2bd1ab534 100644
--- a/drivers/tty/serial/sirfsoc_uart.c
+++ b/drivers/tty/serial/sirfsoc_uart.c
@@ -668,7 +668,7 @@ int sirfsoc_uart_probe(struct platform_device *pdev)
668 if (res == NULL) { 668 if (res == NULL) {
669 dev_err(&pdev->dev, "Insufficient resources.\n"); 669 dev_err(&pdev->dev, "Insufficient resources.\n");
670 ret = -EFAULT; 670 ret = -EFAULT;
671 goto irq_err; 671 goto err;
672 } 672 }
673 port->irq = res->start; 673 port->irq = res->start;
674 674
@@ -676,7 +676,7 @@ int sirfsoc_uart_probe(struct platform_device *pdev)
676 sirfport->p = pinctrl_get_select_default(&pdev->dev); 676 sirfport->p = pinctrl_get_select_default(&pdev->dev);
677 ret = IS_ERR(sirfport->p); 677 ret = IS_ERR(sirfport->p);
678 if (ret) 678 if (ret)
679 goto pin_err; 679 goto err;
680 } 680 }
681 681
682 port->ops = &sirfsoc_uart_ops; 682 port->ops = &sirfsoc_uart_ops;
@@ -695,9 +695,6 @@ port_err:
695 platform_set_drvdata(pdev, NULL); 695 platform_set_drvdata(pdev, NULL);
696 if (sirfport->hw_flow_ctrl) 696 if (sirfport->hw_flow_ctrl)
697 pinctrl_put(sirfport->p); 697 pinctrl_put(sirfport->p);
698pin_err:
699irq_err:
700 devm_iounmap(&pdev->dev, port->membase);
701err: 698err:
702 return ret; 699 return ret;
703} 700}
@@ -709,7 +706,6 @@ static int sirfsoc_uart_remove(struct platform_device *pdev)
709 platform_set_drvdata(pdev, NULL); 706 platform_set_drvdata(pdev, NULL);
710 if (sirfport->hw_flow_ctrl) 707 if (sirfport->hw_flow_ctrl)
711 pinctrl_put(sirfport->p); 708 pinctrl_put(sirfport->p);
712 devm_iounmap(&pdev->dev, port->membase);
713 uart_remove_one_port(&sirfsoc_uart_drv, port); 709 uart_remove_one_port(&sirfsoc_uart_drv, port);
714 return 0; 710 return 0;
715} 711}
diff --git a/drivers/tty/serial/sunsu.c b/drivers/tty/serial/sunsu.c
index 675303b8ed84..b97913dcdbff 100644
--- a/drivers/tty/serial/sunsu.c
+++ b/drivers/tty/serial/sunsu.c
@@ -58,10 +58,16 @@
58enum su_type { SU_PORT_NONE, SU_PORT_MS, SU_PORT_KBD, SU_PORT_PORT }; 58enum su_type { SU_PORT_NONE, SU_PORT_MS, SU_PORT_KBD, SU_PORT_PORT };
59static char *su_typev[] = { "su(???)", "su(mouse)", "su(kbd)", "su(serial)" }; 59static char *su_typev[] = { "su(???)", "su(mouse)", "su(kbd)", "su(serial)" };
60 60
61struct serial_uart_config {
62 char *name;
63 int dfl_xmit_fifo_size;
64 int flags;
65};
66
61/* 67/*
62 * Here we define the default xmit fifo size used for each type of UART. 68 * Here we define the default xmit fifo size used for each type of UART.
63 */ 69 */
64static const struct serial_uart_config uart_config[PORT_MAX_8250+1] = { 70static const struct serial_uart_config uart_config[] = {
65 { "unknown", 1, 0 }, 71 { "unknown", 1, 0 },
66 { "8250", 1, 0 }, 72 { "8250", 1, 0 },
67 { "16450", 1, 0 }, 73 { "16450", 1, 0 },
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-18 03:55:17 -0500