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-rw-r--r--drivers/tty/serial/sh-sci.c2027
1 files changed, 2027 insertions, 0 deletions
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
new file mode 100644
index 000000000000..c291b3add1d2
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+++ b/drivers/tty/serial/sh-sci.c
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1/*
2 * drivers/serial/sh-sci.c
3 *
4 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
5 *
6 * Copyright (C) 2002 - 2008 Paul Mundt
7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
8 *
9 * based off of the old drivers/char/sh-sci.c by:
10 *
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
16 * Removed SH7300 support (Jul 2007).
17 *
18 * This file is subject to the terms and conditions of the GNU General Public
19 * License. See the file "COPYING" in the main directory of this archive
20 * for more details.
21 */
22#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
23#define SUPPORT_SYSRQ
24#endif
25
26#undef DEBUG
27
28#include <linux/module.h>
29#include <linux/errno.h>
30#include <linux/timer.h>
31#include <linux/interrupt.h>
32#include <linux/tty.h>
33#include <linux/tty_flip.h>
34#include <linux/serial.h>
35#include <linux/major.h>
36#include <linux/string.h>
37#include <linux/sysrq.h>
38#include <linux/ioport.h>
39#include <linux/mm.h>
40#include <linux/init.h>
41#include <linux/delay.h>
42#include <linux/console.h>
43#include <linux/platform_device.h>
44#include <linux/serial_sci.h>
45#include <linux/notifier.h>
46#include <linux/cpufreq.h>
47#include <linux/clk.h>
48#include <linux/ctype.h>
49#include <linux/err.h>
50#include <linux/list.h>
51#include <linux/dmaengine.h>
52#include <linux/scatterlist.h>
53#include <linux/slab.h>
54
55#ifdef CONFIG_SUPERH
56#include <asm/sh_bios.h>
57#endif
58
59#ifdef CONFIG_H8300
60#include <asm/gpio.h>
61#endif
62
63#include "sh-sci.h"
64
65struct sci_port {
66 struct uart_port port;
67
68 /* Port type */
69 unsigned int type;
70
71 /* Port IRQs: ERI, RXI, TXI, BRI (optional) */
72 unsigned int irqs[SCIx_NR_IRQS];
73
74 /* Port enable callback */
75 void (*enable)(struct uart_port *port);
76
77 /* Port disable callback */
78 void (*disable)(struct uart_port *port);
79
80 /* Break timer */
81 struct timer_list break_timer;
82 int break_flag;
83
84 /* Interface clock */
85 struct clk *iclk;
86 /* Function clock */
87 struct clk *fclk;
88
89 struct list_head node;
90 struct dma_chan *chan_tx;
91 struct dma_chan *chan_rx;
92#ifdef CONFIG_SERIAL_SH_SCI_DMA
93 struct device *dma_dev;
94 unsigned int slave_tx;
95 unsigned int slave_rx;
96 struct dma_async_tx_descriptor *desc_tx;
97 struct dma_async_tx_descriptor *desc_rx[2];
98 dma_cookie_t cookie_tx;
99 dma_cookie_t cookie_rx[2];
100 dma_cookie_t active_rx;
101 struct scatterlist sg_tx;
102 unsigned int sg_len_tx;
103 struct scatterlist sg_rx[2];
104 size_t buf_len_rx;
105 struct sh_dmae_slave param_tx;
106 struct sh_dmae_slave param_rx;
107 struct work_struct work_tx;
108 struct work_struct work_rx;
109 struct timer_list rx_timer;
110 unsigned int rx_timeout;
111#endif
112};
113
114struct sh_sci_priv {
115 spinlock_t lock;
116 struct list_head ports;
117 struct notifier_block clk_nb;
118};
119
120/* Function prototypes */
121static void sci_stop_tx(struct uart_port *port);
122
123#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
124
125static struct sci_port sci_ports[SCI_NPORTS];
126static struct uart_driver sci_uart_driver;
127
128static inline struct sci_port *
129to_sci_port(struct uart_port *uart)
130{
131 return container_of(uart, struct sci_port, port);
132}
133
134#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
135
136#ifdef CONFIG_CONSOLE_POLL
137static inline void handle_error(struct uart_port *port)
138{
139 /* Clear error flags */
140 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
141}
142
143static int sci_poll_get_char(struct uart_port *port)
144{
145 unsigned short status;
146 int c;
147
148 do {
149 status = sci_in(port, SCxSR);
150 if (status & SCxSR_ERRORS(port)) {
151 handle_error(port);
152 continue;
153 }
154 break;
155 } while (1);
156
157 if (!(status & SCxSR_RDxF(port)))
158 return NO_POLL_CHAR;
159
160 c = sci_in(port, SCxRDR);
161
162 /* Dummy read */
163 sci_in(port, SCxSR);
164 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
165
166 return c;
167}
168#endif
169
170static void sci_poll_put_char(struct uart_port *port, unsigned char c)
171{
172 unsigned short status;
173
174 do {
175 status = sci_in(port, SCxSR);
176 } while (!(status & SCxSR_TDxE(port)));
177
178 sci_out(port, SCxTDR, c);
179 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
180}
181#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
182
183#if defined(__H8300H__) || defined(__H8300S__)
184static void sci_init_pins(struct uart_port *port, unsigned int cflag)
185{
186 int ch = (port->mapbase - SMR0) >> 3;
187
188 /* set DDR regs */
189 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
190 h8300_sci_pins[ch].rx,
191 H8300_GPIO_INPUT);
192 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
193 h8300_sci_pins[ch].tx,
194 H8300_GPIO_OUTPUT);
195
196 /* tx mark output*/
197 H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
198}
199#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
200static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
201{
202 if (port->mapbase == 0xA4400000) {
203 __raw_writew(__raw_readw(PACR) & 0xffc0, PACR);
204 __raw_writew(__raw_readw(PBCR) & 0x0fff, PBCR);
205 } else if (port->mapbase == 0xA4410000)
206 __raw_writew(__raw_readw(PBCR) & 0xf003, PBCR);
207}
208#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721)
209static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
210{
211 unsigned short data;
212
213 if (cflag & CRTSCTS) {
214 /* enable RTS/CTS */
215 if (port->mapbase == 0xa4430000) { /* SCIF0 */
216 /* Clear PTCR bit 9-2; enable all scif pins but sck */
217 data = __raw_readw(PORT_PTCR);
218 __raw_writew((data & 0xfc03), PORT_PTCR);
219 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
220 /* Clear PVCR bit 9-2 */
221 data = __raw_readw(PORT_PVCR);
222 __raw_writew((data & 0xfc03), PORT_PVCR);
223 }
224 } else {
225 if (port->mapbase == 0xa4430000) { /* SCIF0 */
226 /* Clear PTCR bit 5-2; enable only tx and rx */
227 data = __raw_readw(PORT_PTCR);
228 __raw_writew((data & 0xffc3), PORT_PTCR);
229 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
230 /* Clear PVCR bit 5-2 */
231 data = __raw_readw(PORT_PVCR);
232 __raw_writew((data & 0xffc3), PORT_PVCR);
233 }
234 }
235}
236#elif defined(CONFIG_CPU_SH3)
237/* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
238static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
239{
240 unsigned short data;
241
242 /* We need to set SCPCR to enable RTS/CTS */
243 data = __raw_readw(SCPCR);
244 /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
245 __raw_writew(data & 0x0fcf, SCPCR);
246
247 if (!(cflag & CRTSCTS)) {
248 /* We need to set SCPCR to enable RTS/CTS */
249 data = __raw_readw(SCPCR);
250 /* Clear out SCP7MD1,0, SCP4MD1,0,
251 Set SCP6MD1,0 = {01} (output) */
252 __raw_writew((data & 0x0fcf) | 0x1000, SCPCR);
253
254 data = __raw_readb(SCPDR);
255 /* Set /RTS2 (bit6) = 0 */
256 __raw_writeb(data & 0xbf, SCPDR);
257 }
258}
259#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
260static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
261{
262 unsigned short data;
263
264 if (port->mapbase == 0xffe00000) {
265 data = __raw_readw(PSCR);
266 data &= ~0x03cf;
267 if (!(cflag & CRTSCTS))
268 data |= 0x0340;
269
270 __raw_writew(data, PSCR);
271 }
272}
273#elif defined(CONFIG_CPU_SUBTYPE_SH7757) || \
274 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
275 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
276 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
277 defined(CONFIG_CPU_SUBTYPE_SH7786) || \
278 defined(CONFIG_CPU_SUBTYPE_SHX3)
279static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
280{
281 if (!(cflag & CRTSCTS))
282 __raw_writew(0x0080, SCSPTR0); /* Set RTS = 1 */
283}
284#elif defined(CONFIG_CPU_SH4) && !defined(CONFIG_CPU_SH4A)
285static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
286{
287 if (!(cflag & CRTSCTS))
288 __raw_writew(0x0080, SCSPTR2); /* Set RTS = 1 */
289}
290#else
291static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
292{
293 /* Nothing to do */
294}
295#endif
296
297#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
298 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
299 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
300 defined(CONFIG_CPU_SUBTYPE_SH7786)
301static int scif_txfill(struct uart_port *port)
302{
303 return sci_in(port, SCTFDR) & 0xff;
304}
305
306static int scif_txroom(struct uart_port *port)
307{
308 return SCIF_TXROOM_MAX - scif_txfill(port);
309}
310
311static int scif_rxfill(struct uart_port *port)
312{
313 return sci_in(port, SCRFDR) & 0xff;
314}
315#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
316static int scif_txfill(struct uart_port *port)
317{
318 if (port->mapbase == 0xffe00000 ||
319 port->mapbase == 0xffe08000)
320 /* SCIF0/1*/
321 return sci_in(port, SCTFDR) & 0xff;
322 else
323 /* SCIF2 */
324 return sci_in(port, SCFDR) >> 8;
325}
326
327static int scif_txroom(struct uart_port *port)
328{
329 if (port->mapbase == 0xffe00000 ||
330 port->mapbase == 0xffe08000)
331 /* SCIF0/1*/
332 return SCIF_TXROOM_MAX - scif_txfill(port);
333 else
334 /* SCIF2 */
335 return SCIF2_TXROOM_MAX - scif_txfill(port);
336}
337
338static int scif_rxfill(struct uart_port *port)
339{
340 if ((port->mapbase == 0xffe00000) ||
341 (port->mapbase == 0xffe08000)) {
342 /* SCIF0/1*/
343 return sci_in(port, SCRFDR) & 0xff;
344 } else {
345 /* SCIF2 */
346 return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
347 }
348}
349#elif defined(CONFIG_ARCH_SH7372)
350static int scif_txfill(struct uart_port *port)
351{
352 if (port->type == PORT_SCIFA)
353 return sci_in(port, SCFDR) >> 8;
354 else
355 return sci_in(port, SCTFDR);
356}
357
358static int scif_txroom(struct uart_port *port)
359{
360 return port->fifosize - scif_txfill(port);
361}
362
363static int scif_rxfill(struct uart_port *port)
364{
365 if (port->type == PORT_SCIFA)
366 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
367 else
368 return sci_in(port, SCRFDR);
369}
370#else
371static int scif_txfill(struct uart_port *port)
372{
373 return sci_in(port, SCFDR) >> 8;
374}
375
376static int scif_txroom(struct uart_port *port)
377{
378 return SCIF_TXROOM_MAX - scif_txfill(port);
379}
380
381static int scif_rxfill(struct uart_port *port)
382{
383 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
384}
385#endif
386
387static int sci_txfill(struct uart_port *port)
388{
389 return !(sci_in(port, SCxSR) & SCI_TDRE);
390}
391
392static int sci_txroom(struct uart_port *port)
393{
394 return !sci_txfill(port);
395}
396
397static int sci_rxfill(struct uart_port *port)
398{
399 return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
400}
401
402/* ********************************************************************** *
403 * the interrupt related routines *
404 * ********************************************************************** */
405
406static void sci_transmit_chars(struct uart_port *port)
407{
408 struct circ_buf *xmit = &port->state->xmit;
409 unsigned int stopped = uart_tx_stopped(port);
410 unsigned short status;
411 unsigned short ctrl;
412 int count;
413
414 status = sci_in(port, SCxSR);
415 if (!(status & SCxSR_TDxE(port))) {
416 ctrl = sci_in(port, SCSCR);
417 if (uart_circ_empty(xmit))
418 ctrl &= ~SCI_CTRL_FLAGS_TIE;
419 else
420 ctrl |= SCI_CTRL_FLAGS_TIE;
421 sci_out(port, SCSCR, ctrl);
422 return;
423 }
424
425 if (port->type == PORT_SCI)
426 count = sci_txroom(port);
427 else
428 count = scif_txroom(port);
429
430 do {
431 unsigned char c;
432
433 if (port->x_char) {
434 c = port->x_char;
435 port->x_char = 0;
436 } else if (!uart_circ_empty(xmit) && !stopped) {
437 c = xmit->buf[xmit->tail];
438 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
439 } else {
440 break;
441 }
442
443 sci_out(port, SCxTDR, c);
444
445 port->icount.tx++;
446 } while (--count > 0);
447
448 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
449
450 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
451 uart_write_wakeup(port);
452 if (uart_circ_empty(xmit)) {
453 sci_stop_tx(port);
454 } else {
455 ctrl = sci_in(port, SCSCR);
456
457 if (port->type != PORT_SCI) {
458 sci_in(port, SCxSR); /* Dummy read */
459 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
460 }
461
462 ctrl |= SCI_CTRL_FLAGS_TIE;
463 sci_out(port, SCSCR, ctrl);
464 }
465}
466
467/* On SH3, SCIF may read end-of-break as a space->mark char */
468#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
469
470static inline void sci_receive_chars(struct uart_port *port)
471{
472 struct sci_port *sci_port = to_sci_port(port);
473 struct tty_struct *tty = port->state->port.tty;
474 int i, count, copied = 0;
475 unsigned short status;
476 unsigned char flag;
477
478 status = sci_in(port, SCxSR);
479 if (!(status & SCxSR_RDxF(port)))
480 return;
481
482 while (1) {
483 if (port->type == PORT_SCI)
484 count = sci_rxfill(port);
485 else
486 count = scif_rxfill(port);
487
488 /* Don't copy more bytes than there is room for in the buffer */
489 count = tty_buffer_request_room(tty, count);
490
491 /* If for any reason we can't copy more data, we're done! */
492 if (count == 0)
493 break;
494
495 if (port->type == PORT_SCI) {
496 char c = sci_in(port, SCxRDR);
497 if (uart_handle_sysrq_char(port, c) ||
498 sci_port->break_flag)
499 count = 0;
500 else
501 tty_insert_flip_char(tty, c, TTY_NORMAL);
502 } else {
503 for (i = 0; i < count; i++) {
504 char c = sci_in(port, SCxRDR);
505 status = sci_in(port, SCxSR);
506#if defined(CONFIG_CPU_SH3)
507 /* Skip "chars" during break */
508 if (sci_port->break_flag) {
509 if ((c == 0) &&
510 (status & SCxSR_FER(port))) {
511 count--; i--;
512 continue;
513 }
514
515 /* Nonzero => end-of-break */
516 dev_dbg(port->dev, "debounce<%02x>\n", c);
517 sci_port->break_flag = 0;
518
519 if (STEPFN(c)) {
520 count--; i--;
521 continue;
522 }
523 }
524#endif /* CONFIG_CPU_SH3 */
525 if (uart_handle_sysrq_char(port, c)) {
526 count--; i--;
527 continue;
528 }
529
530 /* Store data and status */
531 if (status & SCxSR_FER(port)) {
532 flag = TTY_FRAME;
533 dev_notice(port->dev, "frame error\n");
534 } else if (status & SCxSR_PER(port)) {
535 flag = TTY_PARITY;
536 dev_notice(port->dev, "parity error\n");
537 } else
538 flag = TTY_NORMAL;
539
540 tty_insert_flip_char(tty, c, flag);
541 }
542 }
543
544 sci_in(port, SCxSR); /* dummy read */
545 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
546
547 copied += count;
548 port->icount.rx += count;
549 }
550
551 if (copied) {
552 /* Tell the rest of the system the news. New characters! */
553 tty_flip_buffer_push(tty);
554 } else {
555 sci_in(port, SCxSR); /* dummy read */
556 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
557 }
558}
559
560#define SCI_BREAK_JIFFIES (HZ/20)
561/* The sci generates interrupts during the break,
562 * 1 per millisecond or so during the break period, for 9600 baud.
563 * So dont bother disabling interrupts.
564 * But dont want more than 1 break event.
565 * Use a kernel timer to periodically poll the rx line until
566 * the break is finished.
567 */
568static void sci_schedule_break_timer(struct sci_port *port)
569{
570 port->break_timer.expires = jiffies + SCI_BREAK_JIFFIES;
571 add_timer(&port->break_timer);
572}
573/* Ensure that two consecutive samples find the break over. */
574static void sci_break_timer(unsigned long data)
575{
576 struct sci_port *port = (struct sci_port *)data;
577
578 if (sci_rxd_in(&port->port) == 0) {
579 port->break_flag = 1;
580 sci_schedule_break_timer(port);
581 } else if (port->break_flag == 1) {
582 /* break is over. */
583 port->break_flag = 2;
584 sci_schedule_break_timer(port);
585 } else
586 port->break_flag = 0;
587}
588
589static inline int sci_handle_errors(struct uart_port *port)
590{
591 int copied = 0;
592 unsigned short status = sci_in(port, SCxSR);
593 struct tty_struct *tty = port->state->port.tty;
594
595 if (status & SCxSR_ORER(port)) {
596 /* overrun error */
597 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
598 copied++;
599
600 dev_notice(port->dev, "overrun error");
601 }
602
603 if (status & SCxSR_FER(port)) {
604 if (sci_rxd_in(port) == 0) {
605 /* Notify of BREAK */
606 struct sci_port *sci_port = to_sci_port(port);
607
608 if (!sci_port->break_flag) {
609 sci_port->break_flag = 1;
610 sci_schedule_break_timer(sci_port);
611
612 /* Do sysrq handling. */
613 if (uart_handle_break(port))
614 return 0;
615
616 dev_dbg(port->dev, "BREAK detected\n");
617
618 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
619 copied++;
620 }
621
622 } else {
623 /* frame error */
624 if (tty_insert_flip_char(tty, 0, TTY_FRAME))
625 copied++;
626
627 dev_notice(port->dev, "frame error\n");
628 }
629 }
630
631 if (status & SCxSR_PER(port)) {
632 /* parity error */
633 if (tty_insert_flip_char(tty, 0, TTY_PARITY))
634 copied++;
635
636 dev_notice(port->dev, "parity error");
637 }
638
639 if (copied)
640 tty_flip_buffer_push(tty);
641
642 return copied;
643}
644
645static inline int sci_handle_fifo_overrun(struct uart_port *port)
646{
647 struct tty_struct *tty = port->state->port.tty;
648 int copied = 0;
649
650 if (port->type != PORT_SCIF)
651 return 0;
652
653 if ((sci_in(port, SCLSR) & SCIF_ORER) != 0) {
654 sci_out(port, SCLSR, 0);
655
656 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
657 tty_flip_buffer_push(tty);
658
659 dev_notice(port->dev, "overrun error\n");
660 copied++;
661 }
662
663 return copied;
664}
665
666static inline int sci_handle_breaks(struct uart_port *port)
667{
668 int copied = 0;
669 unsigned short status = sci_in(port, SCxSR);
670 struct tty_struct *tty = port->state->port.tty;
671 struct sci_port *s = to_sci_port(port);
672
673 if (uart_handle_break(port))
674 return 0;
675
676 if (!s->break_flag && status & SCxSR_BRK(port)) {
677#if defined(CONFIG_CPU_SH3)
678 /* Debounce break */
679 s->break_flag = 1;
680#endif
681 /* Notify of BREAK */
682 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
683 copied++;
684
685 dev_dbg(port->dev, "BREAK detected\n");
686 }
687
688 if (copied)
689 tty_flip_buffer_push(tty);
690
691 copied += sci_handle_fifo_overrun(port);
692
693 return copied;
694}
695
696static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
697{
698#ifdef CONFIG_SERIAL_SH_SCI_DMA
699 struct uart_port *port = ptr;
700 struct sci_port *s = to_sci_port(port);
701
702 if (s->chan_rx) {
703 u16 scr = sci_in(port, SCSCR);
704 u16 ssr = sci_in(port, SCxSR);
705
706 /* Disable future Rx interrupts */
707 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
708 disable_irq_nosync(irq);
709 scr |= 0x4000;
710 } else {
711 scr &= ~SCI_CTRL_FLAGS_RIE;
712 }
713 sci_out(port, SCSCR, scr);
714 /* Clear current interrupt */
715 sci_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port)));
716 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
717 jiffies, s->rx_timeout);
718 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
719
720 return IRQ_HANDLED;
721 }
722#endif
723
724 /* I think sci_receive_chars has to be called irrespective
725 * of whether the I_IXOFF is set, otherwise, how is the interrupt
726 * to be disabled?
727 */
728 sci_receive_chars(ptr);
729
730 return IRQ_HANDLED;
731}
732
733static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
734{
735 struct uart_port *port = ptr;
736 unsigned long flags;
737
738 spin_lock_irqsave(&port->lock, flags);
739 sci_transmit_chars(port);
740 spin_unlock_irqrestore(&port->lock, flags);
741
742 return IRQ_HANDLED;
743}
744
745static irqreturn_t sci_er_interrupt(int irq, void *ptr)
746{
747 struct uart_port *port = ptr;
748
749 /* Handle errors */
750 if (port->type == PORT_SCI) {
751 if (sci_handle_errors(port)) {
752 /* discard character in rx buffer */
753 sci_in(port, SCxSR);
754 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
755 }
756 } else {
757 sci_handle_fifo_overrun(port);
758 sci_rx_interrupt(irq, ptr);
759 }
760
761 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
762
763 /* Kick the transmission */
764 sci_tx_interrupt(irq, ptr);
765
766 return IRQ_HANDLED;
767}
768
769static irqreturn_t sci_br_interrupt(int irq, void *ptr)
770{
771 struct uart_port *port = ptr;
772
773 /* Handle BREAKs */
774 sci_handle_breaks(port);
775 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
776
777 return IRQ_HANDLED;
778}
779
780static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
781{
782 unsigned short ssr_status, scr_status, err_enabled;
783 struct uart_port *port = ptr;
784 struct sci_port *s = to_sci_port(port);
785 irqreturn_t ret = IRQ_NONE;
786
787 ssr_status = sci_in(port, SCxSR);
788 scr_status = sci_in(port, SCSCR);
789 err_enabled = scr_status & (SCI_CTRL_FLAGS_REIE | SCI_CTRL_FLAGS_RIE);
790
791 /* Tx Interrupt */
792 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCI_CTRL_FLAGS_TIE) &&
793 !s->chan_tx)
794 ret = sci_tx_interrupt(irq, ptr);
795 /*
796 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
797 * DR flags
798 */
799 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
800 (scr_status & SCI_CTRL_FLAGS_RIE))
801 ret = sci_rx_interrupt(irq, ptr);
802 /* Error Interrupt */
803 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
804 ret = sci_er_interrupt(irq, ptr);
805 /* Break Interrupt */
806 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
807 ret = sci_br_interrupt(irq, ptr);
808
809 return ret;
810}
811
812/*
813 * Here we define a transistion notifier so that we can update all of our
814 * ports' baud rate when the peripheral clock changes.
815 */
816static int sci_notifier(struct notifier_block *self,
817 unsigned long phase, void *p)
818{
819 struct sh_sci_priv *priv = container_of(self,
820 struct sh_sci_priv, clk_nb);
821 struct sci_port *sci_port;
822 unsigned long flags;
823
824 if ((phase == CPUFREQ_POSTCHANGE) ||
825 (phase == CPUFREQ_RESUMECHANGE)) {
826 spin_lock_irqsave(&priv->lock, flags);
827 list_for_each_entry(sci_port, &priv->ports, node)
828 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
829 spin_unlock_irqrestore(&priv->lock, flags);
830 }
831
832 return NOTIFY_OK;
833}
834
835static void sci_clk_enable(struct uart_port *port)
836{
837 struct sci_port *sci_port = to_sci_port(port);
838
839 clk_enable(sci_port->iclk);
840 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
841 clk_enable(sci_port->fclk);
842}
843
844static void sci_clk_disable(struct uart_port *port)
845{
846 struct sci_port *sci_port = to_sci_port(port);
847
848 clk_disable(sci_port->fclk);
849 clk_disable(sci_port->iclk);
850}
851
852static int sci_request_irq(struct sci_port *port)
853{
854 int i;
855 irqreturn_t (*handlers[4])(int irq, void *ptr) = {
856 sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt,
857 sci_br_interrupt,
858 };
859 const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full",
860 "SCI Transmit Data Empty", "SCI Break" };
861
862 if (port->irqs[0] == port->irqs[1]) {
863 if (unlikely(!port->irqs[0]))
864 return -ENODEV;
865
866 if (request_irq(port->irqs[0], sci_mpxed_interrupt,
867 IRQF_DISABLED, "sci", port)) {
868 dev_err(port->port.dev, "Can't allocate IRQ\n");
869 return -ENODEV;
870 }
871 } else {
872 for (i = 0; i < ARRAY_SIZE(handlers); i++) {
873 if (unlikely(!port->irqs[i]))
874 continue;
875
876 if (request_irq(port->irqs[i], handlers[i],
877 IRQF_DISABLED, desc[i], port)) {
878 dev_err(port->port.dev, "Can't allocate IRQ\n");
879 return -ENODEV;
880 }
881 }
882 }
883
884 return 0;
885}
886
887static void sci_free_irq(struct sci_port *port)
888{
889 int i;
890
891 if (port->irqs[0] == port->irqs[1])
892 free_irq(port->irqs[0], port);
893 else {
894 for (i = 0; i < ARRAY_SIZE(port->irqs); i++) {
895 if (!port->irqs[i])
896 continue;
897
898 free_irq(port->irqs[i], port);
899 }
900 }
901}
902
903static unsigned int sci_tx_empty(struct uart_port *port)
904{
905 unsigned short status = sci_in(port, SCxSR);
906 unsigned short in_tx_fifo = scif_txfill(port);
907
908 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
909}
910
911static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
912{
913 /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */
914 /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */
915 /* If you have signals for DTR and DCD, please implement here. */
916}
917
918static unsigned int sci_get_mctrl(struct uart_port *port)
919{
920 /* This routine is used for getting signals of: DTR, DCD, DSR, RI,
921 and CTS/RTS */
922
923 return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR;
924}
925
926#ifdef CONFIG_SERIAL_SH_SCI_DMA
927static void sci_dma_tx_complete(void *arg)
928{
929 struct sci_port *s = arg;
930 struct uart_port *port = &s->port;
931 struct circ_buf *xmit = &port->state->xmit;
932 unsigned long flags;
933
934 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
935
936 spin_lock_irqsave(&port->lock, flags);
937
938 xmit->tail += sg_dma_len(&s->sg_tx);
939 xmit->tail &= UART_XMIT_SIZE - 1;
940
941 port->icount.tx += sg_dma_len(&s->sg_tx);
942
943 async_tx_ack(s->desc_tx);
944 s->cookie_tx = -EINVAL;
945 s->desc_tx = NULL;
946
947 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
948 uart_write_wakeup(port);
949
950 if (!uart_circ_empty(xmit)) {
951 schedule_work(&s->work_tx);
952 } else if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
953 u16 ctrl = sci_in(port, SCSCR);
954 sci_out(port, SCSCR, ctrl & ~SCI_CTRL_FLAGS_TIE);
955 }
956
957 spin_unlock_irqrestore(&port->lock, flags);
958}
959
960/* Locking: called with port lock held */
961static int sci_dma_rx_push(struct sci_port *s, struct tty_struct *tty,
962 size_t count)
963{
964 struct uart_port *port = &s->port;
965 int i, active, room;
966
967 room = tty_buffer_request_room(tty, count);
968
969 if (s->active_rx == s->cookie_rx[0]) {
970 active = 0;
971 } else if (s->active_rx == s->cookie_rx[1]) {
972 active = 1;
973 } else {
974 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
975 return 0;
976 }
977
978 if (room < count)
979 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
980 count - room);
981 if (!room)
982 return room;
983
984 for (i = 0; i < room; i++)
985 tty_insert_flip_char(tty, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
986 TTY_NORMAL);
987
988 port->icount.rx += room;
989
990 return room;
991}
992
993static void sci_dma_rx_complete(void *arg)
994{
995 struct sci_port *s = arg;
996 struct uart_port *port = &s->port;
997 struct tty_struct *tty = port->state->port.tty;
998 unsigned long flags;
999 int count;
1000
1001 dev_dbg(port->dev, "%s(%d) active #%d\n", __func__, port->line, s->active_rx);
1002
1003 spin_lock_irqsave(&port->lock, flags);
1004
1005 count = sci_dma_rx_push(s, tty, s->buf_len_rx);
1006
1007 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1008
1009 spin_unlock_irqrestore(&port->lock, flags);
1010
1011 if (count)
1012 tty_flip_buffer_push(tty);
1013
1014 schedule_work(&s->work_rx);
1015}
1016
1017static void sci_start_rx(struct uart_port *port);
1018static void sci_start_tx(struct uart_port *port);
1019
1020static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1021{
1022 struct dma_chan *chan = s->chan_rx;
1023 struct uart_port *port = &s->port;
1024
1025 s->chan_rx = NULL;
1026 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1027 dma_release_channel(chan);
1028 if (sg_dma_address(&s->sg_rx[0]))
1029 dma_free_coherent(port->dev, s->buf_len_rx * 2,
1030 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
1031 if (enable_pio)
1032 sci_start_rx(port);
1033}
1034
1035static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1036{
1037 struct dma_chan *chan = s->chan_tx;
1038 struct uart_port *port = &s->port;
1039
1040 s->chan_tx = NULL;
1041 s->cookie_tx = -EINVAL;
1042 dma_release_channel(chan);
1043 if (enable_pio)
1044 sci_start_tx(port);
1045}
1046
1047static void sci_submit_rx(struct sci_port *s)
1048{
1049 struct dma_chan *chan = s->chan_rx;
1050 int i;
1051
1052 for (i = 0; i < 2; i++) {
1053 struct scatterlist *sg = &s->sg_rx[i];
1054 struct dma_async_tx_descriptor *desc;
1055
1056 desc = chan->device->device_prep_slave_sg(chan,
1057 sg, 1, DMA_FROM_DEVICE, DMA_PREP_INTERRUPT);
1058
1059 if (desc) {
1060 s->desc_rx[i] = desc;
1061 desc->callback = sci_dma_rx_complete;
1062 desc->callback_param = s;
1063 s->cookie_rx[i] = desc->tx_submit(desc);
1064 }
1065
1066 if (!desc || s->cookie_rx[i] < 0) {
1067 if (i) {
1068 async_tx_ack(s->desc_rx[0]);
1069 s->cookie_rx[0] = -EINVAL;
1070 }
1071 if (desc) {
1072 async_tx_ack(desc);
1073 s->cookie_rx[i] = -EINVAL;
1074 }
1075 dev_warn(s->port.dev,
1076 "failed to re-start DMA, using PIO\n");
1077 sci_rx_dma_release(s, true);
1078 return;
1079 }
1080 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1081 s->cookie_rx[i], i);
1082 }
1083
1084 s->active_rx = s->cookie_rx[0];
1085
1086 dma_async_issue_pending(chan);
1087}
1088
1089static void work_fn_rx(struct work_struct *work)
1090{
1091 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1092 struct uart_port *port = &s->port;
1093 struct dma_async_tx_descriptor *desc;
1094 int new;
1095
1096 if (s->active_rx == s->cookie_rx[0]) {
1097 new = 0;
1098 } else if (s->active_rx == s->cookie_rx[1]) {
1099 new = 1;
1100 } else {
1101 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1102 return;
1103 }
1104 desc = s->desc_rx[new];
1105
1106 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
1107 DMA_SUCCESS) {
1108 /* Handle incomplete DMA receive */
1109 struct tty_struct *tty = port->state->port.tty;
1110 struct dma_chan *chan = s->chan_rx;
1111 struct sh_desc *sh_desc = container_of(desc, struct sh_desc,
1112 async_tx);
1113 unsigned long flags;
1114 int count;
1115
1116 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
1117 dev_dbg(port->dev, "Read %u bytes with cookie %d\n",
1118 sh_desc->partial, sh_desc->cookie);
1119
1120 spin_lock_irqsave(&port->lock, flags);
1121 count = sci_dma_rx_push(s, tty, sh_desc->partial);
1122 spin_unlock_irqrestore(&port->lock, flags);
1123
1124 if (count)
1125 tty_flip_buffer_push(tty);
1126
1127 sci_submit_rx(s);
1128
1129 return;
1130 }
1131
1132 s->cookie_rx[new] = desc->tx_submit(desc);
1133 if (s->cookie_rx[new] < 0) {
1134 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1135 sci_rx_dma_release(s, true);
1136 return;
1137 }
1138
1139 s->active_rx = s->cookie_rx[!new];
1140
1141 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n", __func__,
1142 s->cookie_rx[new], new, s->active_rx);
1143}
1144
1145static void work_fn_tx(struct work_struct *work)
1146{
1147 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1148 struct dma_async_tx_descriptor *desc;
1149 struct dma_chan *chan = s->chan_tx;
1150 struct uart_port *port = &s->port;
1151 struct circ_buf *xmit = &port->state->xmit;
1152 struct scatterlist *sg = &s->sg_tx;
1153
1154 /*
1155 * DMA is idle now.
1156 * Port xmit buffer is already mapped, and it is one page... Just adjust
1157 * offsets and lengths. Since it is a circular buffer, we have to
1158 * transmit till the end, and then the rest. Take the port lock to get a
1159 * consistent xmit buffer state.
1160 */
1161 spin_lock_irq(&port->lock);
1162 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
1163 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
1164 sg->offset;
1165 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1166 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1167 spin_unlock_irq(&port->lock);
1168
1169 BUG_ON(!sg_dma_len(sg));
1170
1171 desc = chan->device->device_prep_slave_sg(chan,
1172 sg, s->sg_len_tx, DMA_TO_DEVICE,
1173 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1174 if (!desc) {
1175 /* switch to PIO */
1176 sci_tx_dma_release(s, true);
1177 return;
1178 }
1179
1180 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
1181
1182 spin_lock_irq(&port->lock);
1183 s->desc_tx = desc;
1184 desc->callback = sci_dma_tx_complete;
1185 desc->callback_param = s;
1186 spin_unlock_irq(&port->lock);
1187 s->cookie_tx = desc->tx_submit(desc);
1188 if (s->cookie_tx < 0) {
1189 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1190 /* switch to PIO */
1191 sci_tx_dma_release(s, true);
1192 return;
1193 }
1194
1195 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__,
1196 xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1197
1198 dma_async_issue_pending(chan);
1199}
1200#endif
1201
1202static void sci_start_tx(struct uart_port *port)
1203{
1204 struct sci_port *s = to_sci_port(port);
1205 unsigned short ctrl;
1206
1207#ifdef CONFIG_SERIAL_SH_SCI_DMA
1208 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1209 u16 new, scr = sci_in(port, SCSCR);
1210 if (s->chan_tx)
1211 new = scr | 0x8000;
1212 else
1213 new = scr & ~0x8000;
1214 if (new != scr)
1215 sci_out(port, SCSCR, new);
1216 }
1217 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
1218 s->cookie_tx < 0)
1219 schedule_work(&s->work_tx);
1220#endif
1221 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1222 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
1223 ctrl = sci_in(port, SCSCR);
1224 sci_out(port, SCSCR, ctrl | SCI_CTRL_FLAGS_TIE);
1225 }
1226}
1227
1228static void sci_stop_tx(struct uart_port *port)
1229{
1230 unsigned short ctrl;
1231
1232 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
1233 ctrl = sci_in(port, SCSCR);
1234 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1235 ctrl &= ~0x8000;
1236 ctrl &= ~SCI_CTRL_FLAGS_TIE;
1237 sci_out(port, SCSCR, ctrl);
1238}
1239
1240static void sci_start_rx(struct uart_port *port)
1241{
1242 unsigned short ctrl = SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE;
1243
1244 /* Set RIE (Receive Interrupt Enable) bit in SCSCR */
1245 ctrl |= sci_in(port, SCSCR);
1246 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1247 ctrl &= ~0x4000;
1248 sci_out(port, SCSCR, ctrl);
1249}
1250
1251static void sci_stop_rx(struct uart_port *port)
1252{
1253 unsigned short ctrl;
1254
1255 /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */
1256 ctrl = sci_in(port, SCSCR);
1257 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1258 ctrl &= ~0x4000;
1259 ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE);
1260 sci_out(port, SCSCR, ctrl);
1261}
1262
1263static void sci_enable_ms(struct uart_port *port)
1264{
1265 /* Nothing here yet .. */
1266}
1267
1268static void sci_break_ctl(struct uart_port *port, int break_state)
1269{
1270 /* Nothing here yet .. */
1271}
1272
1273#ifdef CONFIG_SERIAL_SH_SCI_DMA
1274static bool filter(struct dma_chan *chan, void *slave)
1275{
1276 struct sh_dmae_slave *param = slave;
1277
1278 dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__,
1279 param->slave_id);
1280
1281 if (param->dma_dev == chan->device->dev) {
1282 chan->private = param;
1283 return true;
1284 } else {
1285 return false;
1286 }
1287}
1288
1289static void rx_timer_fn(unsigned long arg)
1290{
1291 struct sci_port *s = (struct sci_port *)arg;
1292 struct uart_port *port = &s->port;
1293 u16 scr = sci_in(port, SCSCR);
1294
1295 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1296 scr &= ~0x4000;
1297 enable_irq(s->irqs[1]);
1298 }
1299 sci_out(port, SCSCR, scr | SCI_CTRL_FLAGS_RIE);
1300 dev_dbg(port->dev, "DMA Rx timed out\n");
1301 schedule_work(&s->work_rx);
1302}
1303
1304static void sci_request_dma(struct uart_port *port)
1305{
1306 struct sci_port *s = to_sci_port(port);
1307 struct sh_dmae_slave *param;
1308 struct dma_chan *chan;
1309 dma_cap_mask_t mask;
1310 int nent;
1311
1312 dev_dbg(port->dev, "%s: port %d DMA %p\n", __func__,
1313 port->line, s->dma_dev);
1314
1315 if (!s->dma_dev)
1316 return;
1317
1318 dma_cap_zero(mask);
1319 dma_cap_set(DMA_SLAVE, mask);
1320
1321 param = &s->param_tx;
1322
1323 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
1324 param->slave_id = s->slave_tx;
1325 param->dma_dev = s->dma_dev;
1326
1327 s->cookie_tx = -EINVAL;
1328 chan = dma_request_channel(mask, filter, param);
1329 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1330 if (chan) {
1331 s->chan_tx = chan;
1332 sg_init_table(&s->sg_tx, 1);
1333 /* UART circular tx buffer is an aligned page. */
1334 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK);
1335 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf),
1336 UART_XMIT_SIZE, (int)port->state->xmit.buf & ~PAGE_MASK);
1337 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE);
1338 if (!nent)
1339 sci_tx_dma_release(s, false);
1340 else
1341 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__,
1342 sg_dma_len(&s->sg_tx),
1343 port->state->xmit.buf, sg_dma_address(&s->sg_tx));
1344
1345 s->sg_len_tx = nent;
1346
1347 INIT_WORK(&s->work_tx, work_fn_tx);
1348 }
1349
1350 param = &s->param_rx;
1351
1352 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
1353 param->slave_id = s->slave_rx;
1354 param->dma_dev = s->dma_dev;
1355
1356 chan = dma_request_channel(mask, filter, param);
1357 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1358 if (chan) {
1359 dma_addr_t dma[2];
1360 void *buf[2];
1361 int i;
1362
1363 s->chan_rx = chan;
1364
1365 s->buf_len_rx = 2 * max(16, (int)port->fifosize);
1366 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2,
1367 &dma[0], GFP_KERNEL);
1368
1369 if (!buf[0]) {
1370 dev_warn(port->dev,
1371 "failed to allocate dma buffer, using PIO\n");
1372 sci_rx_dma_release(s, true);
1373 return;
1374 }
1375
1376 buf[1] = buf[0] + s->buf_len_rx;
1377 dma[1] = dma[0] + s->buf_len_rx;
1378
1379 for (i = 0; i < 2; i++) {
1380 struct scatterlist *sg = &s->sg_rx[i];
1381
1382 sg_init_table(sg, 1);
1383 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
1384 (int)buf[i] & ~PAGE_MASK);
1385 sg_dma_address(sg) = dma[i];
1386 }
1387
1388 INIT_WORK(&s->work_rx, work_fn_rx);
1389 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1390
1391 sci_submit_rx(s);
1392 }
1393}
1394
1395static void sci_free_dma(struct uart_port *port)
1396{
1397 struct sci_port *s = to_sci_port(port);
1398
1399 if (!s->dma_dev)
1400 return;
1401
1402 if (s->chan_tx)
1403 sci_tx_dma_release(s, false);
1404 if (s->chan_rx)
1405 sci_rx_dma_release(s, false);
1406}
1407#endif
1408
1409static int sci_startup(struct uart_port *port)
1410{
1411 struct sci_port *s = to_sci_port(port);
1412
1413 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1414
1415 if (s->enable)
1416 s->enable(port);
1417
1418 sci_request_irq(s);
1419#ifdef CONFIG_SERIAL_SH_SCI_DMA
1420 sci_request_dma(port);
1421#endif
1422 sci_start_tx(port);
1423 sci_start_rx(port);
1424
1425 return 0;
1426}
1427
1428static void sci_shutdown(struct uart_port *port)
1429{
1430 struct sci_port *s = to_sci_port(port);
1431
1432 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1433
1434 sci_stop_rx(port);
1435 sci_stop_tx(port);
1436#ifdef CONFIG_SERIAL_SH_SCI_DMA
1437 sci_free_dma(port);
1438#endif
1439 sci_free_irq(s);
1440
1441 if (s->disable)
1442 s->disable(port);
1443}
1444
1445static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1446 struct ktermios *old)
1447{
1448#ifdef CONFIG_SERIAL_SH_SCI_DMA
1449 struct sci_port *s = to_sci_port(port);
1450#endif
1451 unsigned int status, baud, smr_val, max_baud;
1452 int t = -1;
1453 u16 scfcr = 0;
1454
1455 /*
1456 * earlyprintk comes here early on with port->uartclk set to zero.
1457 * the clock framework is not up and running at this point so here
1458 * we assume that 115200 is the maximum baud rate. please note that
1459 * the baud rate is not programmed during earlyprintk - it is assumed
1460 * that the previous boot loader has enabled required clocks and
1461 * setup the baud rate generator hardware for us already.
1462 */
1463 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1464
1465 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1466 if (likely(baud && port->uartclk))
1467 t = SCBRR_VALUE(baud, port->uartclk);
1468
1469 do {
1470 status = sci_in(port, SCxSR);
1471 } while (!(status & SCxSR_TEND(port)));
1472
1473 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1474
1475 if (port->type != PORT_SCI)
1476 sci_out(port, SCFCR, scfcr | SCFCR_RFRST | SCFCR_TFRST);
1477
1478 smr_val = sci_in(port, SCSMR) & 3;
1479 if ((termios->c_cflag & CSIZE) == CS7)
1480 smr_val |= 0x40;
1481 if (termios->c_cflag & PARENB)
1482 smr_val |= 0x20;
1483 if (termios->c_cflag & PARODD)
1484 smr_val |= 0x30;
1485 if (termios->c_cflag & CSTOPB)
1486 smr_val |= 0x08;
1487
1488 uart_update_timeout(port, termios->c_cflag, baud);
1489
1490 sci_out(port, SCSMR, smr_val);
1491
1492 dev_dbg(port->dev, "%s: SMR %x, t %x, SCSCR %x\n", __func__, smr_val, t,
1493 SCSCR_INIT(port));
1494
1495 if (t > 0) {
1496 if (t >= 256) {
1497 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
1498 t >>= 2;
1499 } else
1500 sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3);
1501
1502 sci_out(port, SCBRR, t);
1503 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1504 }
1505
1506 sci_init_pins(port, termios->c_cflag);
1507 sci_out(port, SCFCR, scfcr | ((termios->c_cflag & CRTSCTS) ? SCFCR_MCE : 0));
1508
1509 sci_out(port, SCSCR, SCSCR_INIT(port));
1510
1511#ifdef CONFIG_SERIAL_SH_SCI_DMA
1512 /*
1513 * Calculate delay for 1.5 DMA buffers: see
1514 * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits
1515 * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function
1516 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)."
1517 * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO
1518 * sizes), but it has been found out experimentally, that this is not
1519 * enough: the driver too often needlessly runs on a DMA timeout. 20ms
1520 * as a minimum seem to work perfectly.
1521 */
1522 if (s->chan_rx) {
1523 s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 /
1524 port->fifosize / 2;
1525 dev_dbg(port->dev,
1526 "DMA Rx t-out %ums, tty t-out %u jiffies\n",
1527 s->rx_timeout * 1000 / HZ, port->timeout);
1528 if (s->rx_timeout < msecs_to_jiffies(20))
1529 s->rx_timeout = msecs_to_jiffies(20);
1530 }
1531#endif
1532
1533 if ((termios->c_cflag & CREAD) != 0)
1534 sci_start_rx(port);
1535}
1536
1537static const char *sci_type(struct uart_port *port)
1538{
1539 switch (port->type) {
1540 case PORT_IRDA:
1541 return "irda";
1542 case PORT_SCI:
1543 return "sci";
1544 case PORT_SCIF:
1545 return "scif";
1546 case PORT_SCIFA:
1547 return "scifa";
1548 case PORT_SCIFB:
1549 return "scifb";
1550 }
1551
1552 return NULL;
1553}
1554
1555static void sci_release_port(struct uart_port *port)
1556{
1557 /* Nothing here yet .. */
1558}
1559
1560static int sci_request_port(struct uart_port *port)
1561{
1562 /* Nothing here yet .. */
1563 return 0;
1564}
1565
1566static void sci_config_port(struct uart_port *port, int flags)
1567{
1568 struct sci_port *s = to_sci_port(port);
1569
1570 port->type = s->type;
1571
1572 if (port->membase)
1573 return;
1574
1575 if (port->flags & UPF_IOREMAP) {
1576 port->membase = ioremap_nocache(port->mapbase, 0x40);
1577
1578 if (IS_ERR(port->membase))
1579 dev_err(port->dev, "can't remap port#%d\n", port->line);
1580 } else {
1581 /*
1582 * For the simple (and majority of) cases where we don't
1583 * need to do any remapping, just cast the cookie
1584 * directly.
1585 */
1586 port->membase = (void __iomem *)port->mapbase;
1587 }
1588}
1589
1590static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
1591{
1592 struct sci_port *s = to_sci_port(port);
1593
1594 if (ser->irq != s->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs)
1595 return -EINVAL;
1596 if (ser->baud_base < 2400)
1597 /* No paper tape reader for Mitch.. */
1598 return -EINVAL;
1599
1600 return 0;
1601}
1602
1603static struct uart_ops sci_uart_ops = {
1604 .tx_empty = sci_tx_empty,
1605 .set_mctrl = sci_set_mctrl,
1606 .get_mctrl = sci_get_mctrl,
1607 .start_tx = sci_start_tx,
1608 .stop_tx = sci_stop_tx,
1609 .stop_rx = sci_stop_rx,
1610 .enable_ms = sci_enable_ms,
1611 .break_ctl = sci_break_ctl,
1612 .startup = sci_startup,
1613 .shutdown = sci_shutdown,
1614 .set_termios = sci_set_termios,
1615 .type = sci_type,
1616 .release_port = sci_release_port,
1617 .request_port = sci_request_port,
1618 .config_port = sci_config_port,
1619 .verify_port = sci_verify_port,
1620#ifdef CONFIG_CONSOLE_POLL
1621 .poll_get_char = sci_poll_get_char,
1622 .poll_put_char = sci_poll_put_char,
1623#endif
1624};
1625
1626static int __devinit sci_init_single(struct platform_device *dev,
1627 struct sci_port *sci_port,
1628 unsigned int index,
1629 struct plat_sci_port *p)
1630{
1631 struct uart_port *port = &sci_port->port;
1632
1633 port->ops = &sci_uart_ops;
1634 port->iotype = UPIO_MEM;
1635 port->line = index;
1636
1637 switch (p->type) {
1638 case PORT_SCIFB:
1639 port->fifosize = 256;
1640 break;
1641 case PORT_SCIFA:
1642 port->fifosize = 64;
1643 break;
1644 case PORT_SCIF:
1645 port->fifosize = 16;
1646 break;
1647 default:
1648 port->fifosize = 1;
1649 break;
1650 }
1651
1652 if (dev) {
1653 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
1654 if (IS_ERR(sci_port->iclk)) {
1655 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
1656 if (IS_ERR(sci_port->iclk)) {
1657 dev_err(&dev->dev, "can't get iclk\n");
1658 return PTR_ERR(sci_port->iclk);
1659 }
1660 }
1661
1662 /*
1663 * The function clock is optional, ignore it if we can't
1664 * find it.
1665 */
1666 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
1667 if (IS_ERR(sci_port->fclk))
1668 sci_port->fclk = NULL;
1669
1670 sci_port->enable = sci_clk_enable;
1671 sci_port->disable = sci_clk_disable;
1672 port->dev = &dev->dev;
1673 }
1674
1675 sci_port->break_timer.data = (unsigned long)sci_port;
1676 sci_port->break_timer.function = sci_break_timer;
1677 init_timer(&sci_port->break_timer);
1678
1679 port->mapbase = p->mapbase;
1680 port->membase = p->membase;
1681
1682 port->irq = p->irqs[SCIx_TXI_IRQ];
1683 port->flags = p->flags;
1684 sci_port->type = port->type = p->type;
1685
1686#ifdef CONFIG_SERIAL_SH_SCI_DMA
1687 sci_port->dma_dev = p->dma_dev;
1688 sci_port->slave_tx = p->dma_slave_tx;
1689 sci_port->slave_rx = p->dma_slave_rx;
1690
1691 dev_dbg(port->dev, "%s: DMA device %p, tx %d, rx %d\n", __func__,
1692 p->dma_dev, p->dma_slave_tx, p->dma_slave_rx);
1693#endif
1694
1695 memcpy(&sci_port->irqs, &p->irqs, sizeof(p->irqs));
1696 return 0;
1697}
1698
1699#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1700static struct tty_driver *serial_console_device(struct console *co, int *index)
1701{
1702 struct uart_driver *p = &sci_uart_driver;
1703 *index = co->index;
1704 return p->tty_driver;
1705}
1706
1707static void serial_console_putchar(struct uart_port *port, int ch)
1708{
1709 sci_poll_put_char(port, ch);
1710}
1711
1712/*
1713 * Print a string to the serial port trying not to disturb
1714 * any possible real use of the port...
1715 */
1716static void serial_console_write(struct console *co, const char *s,
1717 unsigned count)
1718{
1719 struct uart_port *port = co->data;
1720 struct sci_port *sci_port = to_sci_port(port);
1721 unsigned short bits;
1722
1723 if (sci_port->enable)
1724 sci_port->enable(port);
1725
1726 uart_console_write(port, s, count, serial_console_putchar);
1727
1728 /* wait until fifo is empty and last bit has been transmitted */
1729 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
1730 while ((sci_in(port, SCxSR) & bits) != bits)
1731 cpu_relax();
1732
1733 if (sci_port->disable)
1734 sci_port->disable(port);
1735}
1736
1737static int __devinit serial_console_setup(struct console *co, char *options)
1738{
1739 struct sci_port *sci_port;
1740 struct uart_port *port;
1741 int baud = 115200;
1742 int bits = 8;
1743 int parity = 'n';
1744 int flow = 'n';
1745 int ret;
1746
1747 /*
1748 * Check whether an invalid uart number has been specified, and
1749 * if so, search for the first available port that does have
1750 * console support.
1751 */
1752 if (co->index >= SCI_NPORTS)
1753 co->index = 0;
1754
1755 if (co->data) {
1756 port = co->data;
1757 sci_port = to_sci_port(port);
1758 } else {
1759 sci_port = &sci_ports[co->index];
1760 port = &sci_port->port;
1761 co->data = port;
1762 }
1763
1764 /*
1765 * Also need to check port->type, we don't actually have any
1766 * UPIO_PORT ports, but uart_report_port() handily misreports
1767 * it anyways if we don't have a port available by the time this is
1768 * called.
1769 */
1770 if (!port->type)
1771 return -ENODEV;
1772
1773 sci_config_port(port, 0);
1774
1775 if (sci_port->enable)
1776 sci_port->enable(port);
1777
1778 if (options)
1779 uart_parse_options(options, &baud, &parity, &bits, &flow);
1780
1781 ret = uart_set_options(port, co, baud, parity, bits, flow);
1782#if defined(__H8300H__) || defined(__H8300S__)
1783 /* disable rx interrupt */
1784 if (ret == 0)
1785 sci_stop_rx(port);
1786#endif
1787 /* TODO: disable clock */
1788 return ret;
1789}
1790
1791static struct console serial_console = {
1792 .name = "ttySC",
1793 .device = serial_console_device,
1794 .write = serial_console_write,
1795 .setup = serial_console_setup,
1796 .flags = CON_PRINTBUFFER,
1797 .index = -1,
1798};
1799
1800static int __init sci_console_init(void)
1801{
1802 register_console(&serial_console);
1803 return 0;
1804}
1805console_initcall(sci_console_init);
1806
1807static struct sci_port early_serial_port;
1808static struct console early_serial_console = {
1809 .name = "early_ttySC",
1810 .write = serial_console_write,
1811 .flags = CON_PRINTBUFFER,
1812};
1813static char early_serial_buf[32];
1814
1815#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1816
1817#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1818#define SCI_CONSOLE (&serial_console)
1819#else
1820#define SCI_CONSOLE 0
1821#endif
1822
1823static char banner[] __initdata =
1824 KERN_INFO "SuperH SCI(F) driver initialized\n";
1825
1826static struct uart_driver sci_uart_driver = {
1827 .owner = THIS_MODULE,
1828 .driver_name = "sci",
1829 .dev_name = "ttySC",
1830 .major = SCI_MAJOR,
1831 .minor = SCI_MINOR_START,
1832 .nr = SCI_NPORTS,
1833 .cons = SCI_CONSOLE,
1834};
1835
1836
1837static int sci_remove(struct platform_device *dev)
1838{
1839 struct sh_sci_priv *priv = platform_get_drvdata(dev);
1840 struct sci_port *p;
1841 unsigned long flags;
1842
1843 cpufreq_unregister_notifier(&priv->clk_nb, CPUFREQ_TRANSITION_NOTIFIER);
1844
1845 spin_lock_irqsave(&priv->lock, flags);
1846 list_for_each_entry(p, &priv->ports, node) {
1847 uart_remove_one_port(&sci_uart_driver, &p->port);
1848 clk_put(p->iclk);
1849 clk_put(p->fclk);
1850 }
1851 spin_unlock_irqrestore(&priv->lock, flags);
1852
1853 kfree(priv);
1854 return 0;
1855}
1856
1857static int __devinit sci_probe_single(struct platform_device *dev,
1858 unsigned int index,
1859 struct plat_sci_port *p,
1860 struct sci_port *sciport)
1861{
1862 struct sh_sci_priv *priv = platform_get_drvdata(dev);
1863 unsigned long flags;
1864 int ret;
1865
1866 /* Sanity check */
1867 if (unlikely(index >= SCI_NPORTS)) {
1868 dev_notice(&dev->dev, "Attempting to register port "
1869 "%d when only %d are available.\n",
1870 index+1, SCI_NPORTS);
1871 dev_notice(&dev->dev, "Consider bumping "
1872 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
1873 return 0;
1874 }
1875
1876 ret = sci_init_single(dev, sciport, index, p);
1877 if (ret)
1878 return ret;
1879
1880 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
1881 if (ret)
1882 return ret;
1883
1884 INIT_LIST_HEAD(&sciport->node);
1885
1886 spin_lock_irqsave(&priv->lock, flags);
1887 list_add(&sciport->node, &priv->ports);
1888 spin_unlock_irqrestore(&priv->lock, flags);
1889
1890 return 0;
1891}
1892
1893/*
1894 * Register a set of serial devices attached to a platform device. The
1895 * list is terminated with a zero flags entry, which means we expect
1896 * all entries to have at least UPF_BOOT_AUTOCONF set. Platforms that need
1897 * remapping (such as sh64) should also set UPF_IOREMAP.
1898 */
1899static int __devinit sci_probe(struct platform_device *dev)
1900{
1901 struct plat_sci_port *p = dev->dev.platform_data;
1902 struct sh_sci_priv *priv;
1903 int i, ret = -EINVAL;
1904
1905#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1906 if (is_early_platform_device(dev)) {
1907 if (dev->id == -1)
1908 return -ENOTSUPP;
1909 early_serial_console.index = dev->id;
1910 early_serial_console.data = &early_serial_port.port;
1911 sci_init_single(NULL, &early_serial_port, dev->id, p);
1912 serial_console_setup(&early_serial_console, early_serial_buf);
1913 if (!strstr(early_serial_buf, "keep"))
1914 early_serial_console.flags |= CON_BOOT;
1915 register_console(&early_serial_console);
1916 return 0;
1917 }
1918#endif
1919
1920 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1921 if (!priv)
1922 return -ENOMEM;
1923
1924 INIT_LIST_HEAD(&priv->ports);
1925 spin_lock_init(&priv->lock);
1926 platform_set_drvdata(dev, priv);
1927
1928 priv->clk_nb.notifier_call = sci_notifier;
1929 cpufreq_register_notifier(&priv->clk_nb, CPUFREQ_TRANSITION_NOTIFIER);
1930
1931 if (dev->id != -1) {
1932 ret = sci_probe_single(dev, dev->id, p, &sci_ports[dev->id]);
1933 if (ret)
1934 goto err_unreg;
1935 } else {
1936 for (i = 0; p && p->flags != 0; p++, i++) {
1937 ret = sci_probe_single(dev, i, p, &sci_ports[i]);
1938 if (ret)
1939 goto err_unreg;
1940 }
1941 }
1942
1943#ifdef CONFIG_SH_STANDARD_BIOS
1944 sh_bios_gdb_detach();
1945#endif
1946
1947 return 0;
1948
1949err_unreg:
1950 sci_remove(dev);
1951 return ret;
1952}
1953
1954static int sci_suspend(struct device *dev)
1955{
1956 struct sh_sci_priv *priv = dev_get_drvdata(dev);
1957 struct sci_port *p;
1958 unsigned long flags;
1959
1960 spin_lock_irqsave(&priv->lock, flags);
1961 list_for_each_entry(p, &priv->ports, node)
1962 uart_suspend_port(&sci_uart_driver, &p->port);
1963 spin_unlock_irqrestore(&priv->lock, flags);
1964
1965 return 0;
1966}
1967
1968static int sci_resume(struct device *dev)
1969{
1970 struct sh_sci_priv *priv = dev_get_drvdata(dev);
1971 struct sci_port *p;
1972 unsigned long flags;
1973
1974 spin_lock_irqsave(&priv->lock, flags);
1975 list_for_each_entry(p, &priv->ports, node)
1976 uart_resume_port(&sci_uart_driver, &p->port);
1977 spin_unlock_irqrestore(&priv->lock, flags);
1978
1979 return 0;
1980}
1981
1982static const struct dev_pm_ops sci_dev_pm_ops = {
1983 .suspend = sci_suspend,
1984 .resume = sci_resume,
1985};
1986
1987static struct platform_driver sci_driver = {
1988 .probe = sci_probe,
1989 .remove = sci_remove,
1990 .driver = {
1991 .name = "sh-sci",
1992 .owner = THIS_MODULE,
1993 .pm = &sci_dev_pm_ops,
1994 },
1995};
1996
1997static int __init sci_init(void)
1998{
1999 int ret;
2000
2001 printk(banner);
2002
2003 ret = uart_register_driver(&sci_uart_driver);
2004 if (likely(ret == 0)) {
2005 ret = platform_driver_register(&sci_driver);
2006 if (unlikely(ret))
2007 uart_unregister_driver(&sci_uart_driver);
2008 }
2009
2010 return ret;
2011}
2012
2013static void __exit sci_exit(void)
2014{
2015 platform_driver_unregister(&sci_driver);
2016 uart_unregister_driver(&sci_uart_driver);
2017}
2018
2019#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2020early_platform_init_buffer("earlyprintk", &sci_driver,
2021 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2022#endif
2023module_init(sci_init);
2024module_exit(sci_exit);
2025
2026MODULE_LICENSE("GPL");
2027MODULE_ALIAS("platform:sh-sci");
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 10:14:25 -0500