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-rw-r--r--drivers/tty/serial/omap-serial.c1359
1 files changed, 1359 insertions, 0 deletions
diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
new file mode 100644
index 000000000000..7f2f01058789
--- /dev/null
+++ b/drivers/tty/serial/omap-serial.c
@@ -0,0 +1,1359 @@
1/*
2 * Driver for OMAP-UART controller.
3 * Based on drivers/serial/8250.c
4 *
5 * Copyright (C) 2010 Texas Instruments.
6 *
7 * Authors:
8 * Govindraj R <govindraj.raja@ti.com>
9 * Thara Gopinath <thara@ti.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * Note: This driver is made seperate from 8250 driver as we cannot
17 * over load 8250 driver with omap platform specific configuration for
18 * features like DMA, it makes easier to implement features like DMA and
19 * hardware flow control and software flow control configuration with
20 * this driver as required for the omap-platform.
21 */
22
23#include <linux/module.h>
24#include <linux/init.h>
25#include <linux/console.h>
26#include <linux/serial_reg.h>
27#include <linux/delay.h>
28#include <linux/slab.h>
29#include <linux/tty.h>
30#include <linux/tty_flip.h>
31#include <linux/io.h>
32#include <linux/dma-mapping.h>
33#include <linux/clk.h>
34#include <linux/serial_core.h>
35#include <linux/irq.h>
36
37#include <plat/dma.h>
38#include <plat/dmtimer.h>
39#include <plat/omap-serial.h>
40
41static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
42
43/* Forward declaration of functions */
44static void uart_tx_dma_callback(int lch, u16 ch_status, void *data);
45static void serial_omap_rx_timeout(unsigned long uart_no);
46static int serial_omap_start_rxdma(struct uart_omap_port *up);
47
48static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
49{
50 offset <<= up->port.regshift;
51 return readw(up->port.membase + offset);
52}
53
54static inline void serial_out(struct uart_omap_port *up, int offset, int value)
55{
56 offset <<= up->port.regshift;
57 writew(value, up->port.membase + offset);
58}
59
60static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
61{
62 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
63 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
64 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
65 serial_out(up, UART_FCR, 0);
66}
67
68/*
69 * serial_omap_get_divisor - calculate divisor value
70 * @port: uart port info
71 * @baud: baudrate for which divisor needs to be calculated.
72 *
73 * We have written our own function to get the divisor so as to support
74 * 13x mode. 3Mbps Baudrate as an different divisor.
75 * Reference OMAP TRM Chapter 17:
76 * Table 17-1. UART Mode Baud Rates, Divisor Values, and Error Rates
77 * referring to oversampling - divisor value
78 * baudrate 460,800 to 3,686,400 all have divisor 13
79 * except 3,000,000 which has divisor value 16
80 */
81static unsigned int
82serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
83{
84 unsigned int divisor;
85
86 if (baud > OMAP_MODE13X_SPEED && baud != 3000000)
87 divisor = 13;
88 else
89 divisor = 16;
90 return port->uartclk/(baud * divisor);
91}
92
93static void serial_omap_stop_rxdma(struct uart_omap_port *up)
94{
95 if (up->uart_dma.rx_dma_used) {
96 del_timer(&up->uart_dma.rx_timer);
97 omap_stop_dma(up->uart_dma.rx_dma_channel);
98 omap_free_dma(up->uart_dma.rx_dma_channel);
99 up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE;
100 up->uart_dma.rx_dma_used = false;
101 }
102}
103
104static void serial_omap_enable_ms(struct uart_port *port)
105{
106 struct uart_omap_port *up = (struct uart_omap_port *)port;
107
108 dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->pdev->id);
109 up->ier |= UART_IER_MSI;
110 serial_out(up, UART_IER, up->ier);
111}
112
113static void serial_omap_stop_tx(struct uart_port *port)
114{
115 struct uart_omap_port *up = (struct uart_omap_port *)port;
116
117 if (up->use_dma &&
118 up->uart_dma.tx_dma_channel != OMAP_UART_DMA_CH_FREE) {
119 /*
120 * Check if dma is still active. If yes do nothing,
121 * return. Else stop dma
122 */
123 if (omap_get_dma_active_status(up->uart_dma.tx_dma_channel))
124 return;
125 omap_stop_dma(up->uart_dma.tx_dma_channel);
126 omap_free_dma(up->uart_dma.tx_dma_channel);
127 up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE;
128 }
129
130 if (up->ier & UART_IER_THRI) {
131 up->ier &= ~UART_IER_THRI;
132 serial_out(up, UART_IER, up->ier);
133 }
134}
135
136static void serial_omap_stop_rx(struct uart_port *port)
137{
138 struct uart_omap_port *up = (struct uart_omap_port *)port;
139
140 if (up->use_dma)
141 serial_omap_stop_rxdma(up);
142 up->ier &= ~UART_IER_RLSI;
143 up->port.read_status_mask &= ~UART_LSR_DR;
144 serial_out(up, UART_IER, up->ier);
145}
146
147static inline void receive_chars(struct uart_omap_port *up, int *status)
148{
149 struct tty_struct *tty = up->port.state->port.tty;
150 unsigned int flag;
151 unsigned char ch, lsr = *status;
152 int max_count = 256;
153
154 do {
155 if (likely(lsr & UART_LSR_DR))
156 ch = serial_in(up, UART_RX);
157 flag = TTY_NORMAL;
158 up->port.icount.rx++;
159
160 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
161 /*
162 * For statistics only
163 */
164 if (lsr & UART_LSR_BI) {
165 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
166 up->port.icount.brk++;
167 /*
168 * We do the SysRQ and SAK checking
169 * here because otherwise the break
170 * may get masked by ignore_status_mask
171 * or read_status_mask.
172 */
173 if (uart_handle_break(&up->port))
174 goto ignore_char;
175 } else if (lsr & UART_LSR_PE) {
176 up->port.icount.parity++;
177 } else if (lsr & UART_LSR_FE) {
178 up->port.icount.frame++;
179 }
180
181 if (lsr & UART_LSR_OE)
182 up->port.icount.overrun++;
183
184 /*
185 * Mask off conditions which should be ignored.
186 */
187 lsr &= up->port.read_status_mask;
188
189#ifdef CONFIG_SERIAL_OMAP_CONSOLE
190 if (up->port.line == up->port.cons->index) {
191 /* Recover the break flag from console xmit */
192 lsr |= up->lsr_break_flag;
193 up->lsr_break_flag = 0;
194 }
195#endif
196 if (lsr & UART_LSR_BI)
197 flag = TTY_BREAK;
198 else if (lsr & UART_LSR_PE)
199 flag = TTY_PARITY;
200 else if (lsr & UART_LSR_FE)
201 flag = TTY_FRAME;
202 }
203
204 if (uart_handle_sysrq_char(&up->port, ch))
205 goto ignore_char;
206 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
207ignore_char:
208 lsr = serial_in(up, UART_LSR);
209 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
210 spin_unlock(&up->port.lock);
211 tty_flip_buffer_push(tty);
212 spin_lock(&up->port.lock);
213}
214
215static void transmit_chars(struct uart_omap_port *up)
216{
217 struct circ_buf *xmit = &up->port.state->xmit;
218 int count;
219
220 if (up->port.x_char) {
221 serial_out(up, UART_TX, up->port.x_char);
222 up->port.icount.tx++;
223 up->port.x_char = 0;
224 return;
225 }
226 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
227 serial_omap_stop_tx(&up->port);
228 return;
229 }
230 count = up->port.fifosize / 4;
231 do {
232 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
233 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
234 up->port.icount.tx++;
235 if (uart_circ_empty(xmit))
236 break;
237 } while (--count > 0);
238
239 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
240 uart_write_wakeup(&up->port);
241
242 if (uart_circ_empty(xmit))
243 serial_omap_stop_tx(&up->port);
244}
245
246static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
247{
248 if (!(up->ier & UART_IER_THRI)) {
249 up->ier |= UART_IER_THRI;
250 serial_out(up, UART_IER, up->ier);
251 }
252}
253
254static void serial_omap_start_tx(struct uart_port *port)
255{
256 struct uart_omap_port *up = (struct uart_omap_port *)port;
257 struct circ_buf *xmit;
258 unsigned int start;
259 int ret = 0;
260
261 if (!up->use_dma) {
262 serial_omap_enable_ier_thri(up);
263 return;
264 }
265
266 if (up->uart_dma.tx_dma_used)
267 return;
268
269 xmit = &up->port.state->xmit;
270
271 if (up->uart_dma.tx_dma_channel == OMAP_UART_DMA_CH_FREE) {
272 ret = omap_request_dma(up->uart_dma.uart_dma_tx,
273 "UART Tx DMA",
274 (void *)uart_tx_dma_callback, up,
275 &(up->uart_dma.tx_dma_channel));
276
277 if (ret < 0) {
278 serial_omap_enable_ier_thri(up);
279 return;
280 }
281 }
282 spin_lock(&(up->uart_dma.tx_lock));
283 up->uart_dma.tx_dma_used = true;
284 spin_unlock(&(up->uart_dma.tx_lock));
285
286 start = up->uart_dma.tx_buf_dma_phys +
287 (xmit->tail & (UART_XMIT_SIZE - 1));
288
289 up->uart_dma.tx_buf_size = uart_circ_chars_pending(xmit);
290 /*
291 * It is a circular buffer. See if the buffer has wounded back.
292 * If yes it will have to be transferred in two separate dma
293 * transfers
294 */
295 if (start + up->uart_dma.tx_buf_size >=
296 up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE)
297 up->uart_dma.tx_buf_size =
298 (up->uart_dma.tx_buf_dma_phys +
299 UART_XMIT_SIZE) - start;
300
301 omap_set_dma_dest_params(up->uart_dma.tx_dma_channel, 0,
302 OMAP_DMA_AMODE_CONSTANT,
303 up->uart_dma.uart_base, 0, 0);
304 omap_set_dma_src_params(up->uart_dma.tx_dma_channel, 0,
305 OMAP_DMA_AMODE_POST_INC, start, 0, 0);
306 omap_set_dma_transfer_params(up->uart_dma.tx_dma_channel,
307 OMAP_DMA_DATA_TYPE_S8,
308 up->uart_dma.tx_buf_size, 1,
309 OMAP_DMA_SYNC_ELEMENT,
310 up->uart_dma.uart_dma_tx, 0);
311 /* FIXME: Cache maintenance needed here? */
312 omap_start_dma(up->uart_dma.tx_dma_channel);
313}
314
315static unsigned int check_modem_status(struct uart_omap_port *up)
316{
317 unsigned int status;
318
319 status = serial_in(up, UART_MSR);
320 status |= up->msr_saved_flags;
321 up->msr_saved_flags = 0;
322 if ((status & UART_MSR_ANY_DELTA) == 0)
323 return status;
324
325 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
326 up->port.state != NULL) {
327 if (status & UART_MSR_TERI)
328 up->port.icount.rng++;
329 if (status & UART_MSR_DDSR)
330 up->port.icount.dsr++;
331 if (status & UART_MSR_DDCD)
332 uart_handle_dcd_change
333 (&up->port, status & UART_MSR_DCD);
334 if (status & UART_MSR_DCTS)
335 uart_handle_cts_change
336 (&up->port, status & UART_MSR_CTS);
337 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
338 }
339
340 return status;
341}
342
343/**
344 * serial_omap_irq() - This handles the interrupt from one port
345 * @irq: uart port irq number
346 * @dev_id: uart port info
347 */
348static inline irqreturn_t serial_omap_irq(int irq, void *dev_id)
349{
350 struct uart_omap_port *up = dev_id;
351 unsigned int iir, lsr;
352 unsigned long flags;
353
354 iir = serial_in(up, UART_IIR);
355 if (iir & UART_IIR_NO_INT)
356 return IRQ_NONE;
357
358 spin_lock_irqsave(&up->port.lock, flags);
359 lsr = serial_in(up, UART_LSR);
360 if (iir & UART_IIR_RLSI) {
361 if (!up->use_dma) {
362 if (lsr & UART_LSR_DR)
363 receive_chars(up, &lsr);
364 } else {
365 up->ier &= ~(UART_IER_RDI | UART_IER_RLSI);
366 serial_out(up, UART_IER, up->ier);
367 if ((serial_omap_start_rxdma(up) != 0) &&
368 (lsr & UART_LSR_DR))
369 receive_chars(up, &lsr);
370 }
371 }
372
373 check_modem_status(up);
374 if ((lsr & UART_LSR_THRE) && (iir & UART_IIR_THRI))
375 transmit_chars(up);
376
377 spin_unlock_irqrestore(&up->port.lock, flags);
378 up->port_activity = jiffies;
379 return IRQ_HANDLED;
380}
381
382static unsigned int serial_omap_tx_empty(struct uart_port *port)
383{
384 struct uart_omap_port *up = (struct uart_omap_port *)port;
385 unsigned long flags = 0;
386 unsigned int ret = 0;
387
388 dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->pdev->id);
389 spin_lock_irqsave(&up->port.lock, flags);
390 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
391 spin_unlock_irqrestore(&up->port.lock, flags);
392
393 return ret;
394}
395
396static unsigned int serial_omap_get_mctrl(struct uart_port *port)
397{
398 struct uart_omap_port *up = (struct uart_omap_port *)port;
399 unsigned char status;
400 unsigned int ret = 0;
401
402 status = check_modem_status(up);
403 dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->pdev->id);
404
405 if (status & UART_MSR_DCD)
406 ret |= TIOCM_CAR;
407 if (status & UART_MSR_RI)
408 ret |= TIOCM_RNG;
409 if (status & UART_MSR_DSR)
410 ret |= TIOCM_DSR;
411 if (status & UART_MSR_CTS)
412 ret |= TIOCM_CTS;
413 return ret;
414}
415
416static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
417{
418 struct uart_omap_port *up = (struct uart_omap_port *)port;
419 unsigned char mcr = 0;
420
421 dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->pdev->id);
422 if (mctrl & TIOCM_RTS)
423 mcr |= UART_MCR_RTS;
424 if (mctrl & TIOCM_DTR)
425 mcr |= UART_MCR_DTR;
426 if (mctrl & TIOCM_OUT1)
427 mcr |= UART_MCR_OUT1;
428 if (mctrl & TIOCM_OUT2)
429 mcr |= UART_MCR_OUT2;
430 if (mctrl & TIOCM_LOOP)
431 mcr |= UART_MCR_LOOP;
432
433 mcr |= up->mcr;
434 serial_out(up, UART_MCR, mcr);
435}
436
437static void serial_omap_break_ctl(struct uart_port *port, int break_state)
438{
439 struct uart_omap_port *up = (struct uart_omap_port *)port;
440 unsigned long flags = 0;
441
442 dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->pdev->id);
443 spin_lock_irqsave(&up->port.lock, flags);
444 if (break_state == -1)
445 up->lcr |= UART_LCR_SBC;
446 else
447 up->lcr &= ~UART_LCR_SBC;
448 serial_out(up, UART_LCR, up->lcr);
449 spin_unlock_irqrestore(&up->port.lock, flags);
450}
451
452static int serial_omap_startup(struct uart_port *port)
453{
454 struct uart_omap_port *up = (struct uart_omap_port *)port;
455 unsigned long flags = 0;
456 int retval;
457
458 /*
459 * Allocate the IRQ
460 */
461 retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
462 up->name, up);
463 if (retval)
464 return retval;
465
466 dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->pdev->id);
467
468 /*
469 * Clear the FIFO buffers and disable them.
470 * (they will be reenabled in set_termios())
471 */
472 serial_omap_clear_fifos(up);
473 /* For Hardware flow control */
474 serial_out(up, UART_MCR, UART_MCR_RTS);
475
476 /*
477 * Clear the interrupt registers.
478 */
479 (void) serial_in(up, UART_LSR);
480 if (serial_in(up, UART_LSR) & UART_LSR_DR)
481 (void) serial_in(up, UART_RX);
482 (void) serial_in(up, UART_IIR);
483 (void) serial_in(up, UART_MSR);
484
485 /*
486 * Now, initialize the UART
487 */
488 serial_out(up, UART_LCR, UART_LCR_WLEN8);
489 spin_lock_irqsave(&up->port.lock, flags);
490 /*
491 * Most PC uarts need OUT2 raised to enable interrupts.
492 */
493 up->port.mctrl |= TIOCM_OUT2;
494 serial_omap_set_mctrl(&up->port, up->port.mctrl);
495 spin_unlock_irqrestore(&up->port.lock, flags);
496
497 up->msr_saved_flags = 0;
498 if (up->use_dma) {
499 free_page((unsigned long)up->port.state->xmit.buf);
500 up->port.state->xmit.buf = dma_alloc_coherent(NULL,
501 UART_XMIT_SIZE,
502 (dma_addr_t *)&(up->uart_dma.tx_buf_dma_phys),
503 0);
504 init_timer(&(up->uart_dma.rx_timer));
505 up->uart_dma.rx_timer.function = serial_omap_rx_timeout;
506 up->uart_dma.rx_timer.data = up->pdev->id;
507 /* Currently the buffer size is 4KB. Can increase it */
508 up->uart_dma.rx_buf = dma_alloc_coherent(NULL,
509 up->uart_dma.rx_buf_size,
510 (dma_addr_t *)&(up->uart_dma.rx_buf_dma_phys), 0);
511 }
512 /*
513 * Finally, enable interrupts. Note: Modem status interrupts
514 * are set via set_termios(), which will be occurring imminently
515 * anyway, so we don't enable them here.
516 */
517 up->ier = UART_IER_RLSI | UART_IER_RDI;
518 serial_out(up, UART_IER, up->ier);
519
520 up->port_activity = jiffies;
521 return 0;
522}
523
524static void serial_omap_shutdown(struct uart_port *port)
525{
526 struct uart_omap_port *up = (struct uart_omap_port *)port;
527 unsigned long flags = 0;
528
529 dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->pdev->id);
530 /*
531 * Disable interrupts from this port
532 */
533 up->ier = 0;
534 serial_out(up, UART_IER, 0);
535
536 spin_lock_irqsave(&up->port.lock, flags);
537 up->port.mctrl &= ~TIOCM_OUT2;
538 serial_omap_set_mctrl(&up->port, up->port.mctrl);
539 spin_unlock_irqrestore(&up->port.lock, flags);
540
541 /*
542 * Disable break condition and FIFOs
543 */
544 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
545 serial_omap_clear_fifos(up);
546
547 /*
548 * Read data port to reset things, and then free the irq
549 */
550 if (serial_in(up, UART_LSR) & UART_LSR_DR)
551 (void) serial_in(up, UART_RX);
552 if (up->use_dma) {
553 dma_free_coherent(up->port.dev,
554 UART_XMIT_SIZE, up->port.state->xmit.buf,
555 up->uart_dma.tx_buf_dma_phys);
556 up->port.state->xmit.buf = NULL;
557 serial_omap_stop_rx(port);
558 dma_free_coherent(up->port.dev,
559 up->uart_dma.rx_buf_size, up->uart_dma.rx_buf,
560 up->uart_dma.rx_buf_dma_phys);
561 up->uart_dma.rx_buf = NULL;
562 }
563 free_irq(up->port.irq, up);
564}
565
566static inline void
567serial_omap_configure_xonxoff
568 (struct uart_omap_port *up, struct ktermios *termios)
569{
570 unsigned char efr = 0;
571
572 up->lcr = serial_in(up, UART_LCR);
573 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
574 up->efr = serial_in(up, UART_EFR);
575 serial_out(up, UART_EFR, up->efr & ~UART_EFR_ECB);
576
577 serial_out(up, UART_XON1, termios->c_cc[VSTART]);
578 serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
579
580 /* clear SW control mode bits */
581 efr = up->efr;
582 efr &= OMAP_UART_SW_CLR;
583
584 /*
585 * IXON Flag:
586 * Enable XON/XOFF flow control on output.
587 * Transmit XON1, XOFF1
588 */
589 if (termios->c_iflag & IXON)
590 efr |= OMAP_UART_SW_TX;
591
592 /*
593 * IXOFF Flag:
594 * Enable XON/XOFF flow control on input.
595 * Receiver compares XON1, XOFF1.
596 */
597 if (termios->c_iflag & IXOFF)
598 efr |= OMAP_UART_SW_RX;
599
600 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
601 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
602
603 up->mcr = serial_in(up, UART_MCR);
604
605 /*
606 * IXANY Flag:
607 * Enable any character to restart output.
608 * Operation resumes after receiving any
609 * character after recognition of the XOFF character
610 */
611 if (termios->c_iflag & IXANY)
612 up->mcr |= UART_MCR_XONANY;
613
614 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
615 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
616 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
617 /* Enable special char function UARTi.EFR_REG[5] and
618 * load the new software flow control mode IXON or IXOFF
619 * and restore the UARTi.EFR_REG[4] ENHANCED_EN value.
620 */
621 serial_out(up, UART_EFR, efr | UART_EFR_SCD);
622 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
623
624 serial_out(up, UART_MCR, up->mcr & ~UART_MCR_TCRTLR);
625 serial_out(up, UART_LCR, up->lcr);
626}
627
628static void
629serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
630 struct ktermios *old)
631{
632 struct uart_omap_port *up = (struct uart_omap_port *)port;
633 unsigned char cval = 0;
634 unsigned char efr = 0;
635 unsigned long flags = 0;
636 unsigned int baud, quot;
637
638 switch (termios->c_cflag & CSIZE) {
639 case CS5:
640 cval = UART_LCR_WLEN5;
641 break;
642 case CS6:
643 cval = UART_LCR_WLEN6;
644 break;
645 case CS7:
646 cval = UART_LCR_WLEN7;
647 break;
648 default:
649 case CS8:
650 cval = UART_LCR_WLEN8;
651 break;
652 }
653
654 if (termios->c_cflag & CSTOPB)
655 cval |= UART_LCR_STOP;
656 if (termios->c_cflag & PARENB)
657 cval |= UART_LCR_PARITY;
658 if (!(termios->c_cflag & PARODD))
659 cval |= UART_LCR_EPAR;
660
661 /*
662 * Ask the core to calculate the divisor for us.
663 */
664
665 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
666 quot = serial_omap_get_divisor(port, baud);
667
668 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
669 UART_FCR_ENABLE_FIFO;
670 if (up->use_dma)
671 up->fcr |= UART_FCR_DMA_SELECT;
672
673 /*
674 * Ok, we're now changing the port state. Do it with
675 * interrupts disabled.
676 */
677 spin_lock_irqsave(&up->port.lock, flags);
678
679 /*
680 * Update the per-port timeout.
681 */
682 uart_update_timeout(port, termios->c_cflag, baud);
683
684 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
685 if (termios->c_iflag & INPCK)
686 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
687 if (termios->c_iflag & (BRKINT | PARMRK))
688 up->port.read_status_mask |= UART_LSR_BI;
689
690 /*
691 * Characters to ignore
692 */
693 up->port.ignore_status_mask = 0;
694 if (termios->c_iflag & IGNPAR)
695 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
696 if (termios->c_iflag & IGNBRK) {
697 up->port.ignore_status_mask |= UART_LSR_BI;
698 /*
699 * If we're ignoring parity and break indicators,
700 * ignore overruns too (for real raw support).
701 */
702 if (termios->c_iflag & IGNPAR)
703 up->port.ignore_status_mask |= UART_LSR_OE;
704 }
705
706 /*
707 * ignore all characters if CREAD is not set
708 */
709 if ((termios->c_cflag & CREAD) == 0)
710 up->port.ignore_status_mask |= UART_LSR_DR;
711
712 /*
713 * Modem status interrupts
714 */
715 up->ier &= ~UART_IER_MSI;
716 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
717 up->ier |= UART_IER_MSI;
718 serial_out(up, UART_IER, up->ier);
719 serial_out(up, UART_LCR, cval); /* reset DLAB */
720
721 /* FIFOs and DMA Settings */
722
723 /* FCR can be changed only when the
724 * baud clock is not running
725 * DLL_REG and DLH_REG set to 0.
726 */
727 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
728 serial_out(up, UART_DLL, 0);
729 serial_out(up, UART_DLM, 0);
730 serial_out(up, UART_LCR, 0);
731
732 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
733
734 up->efr = serial_in(up, UART_EFR);
735 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
736
737 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
738 up->mcr = serial_in(up, UART_MCR);
739 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
740 /* FIFO ENABLE, DMA MODE */
741 serial_out(up, UART_FCR, up->fcr);
742 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
743
744 if (up->use_dma) {
745 serial_out(up, UART_TI752_TLR, 0);
746 serial_out(up, UART_OMAP_SCR,
747 (UART_FCR_TRIGGER_4 | UART_FCR_TRIGGER_8));
748 }
749
750 serial_out(up, UART_EFR, up->efr);
751 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
752 serial_out(up, UART_MCR, up->mcr);
753
754 /* Protocol, Baud Rate, and Interrupt Settings */
755
756 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
757 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
758
759 up->efr = serial_in(up, UART_EFR);
760 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
761
762 serial_out(up, UART_LCR, 0);
763 serial_out(up, UART_IER, 0);
764 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
765
766 serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */
767 serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */
768
769 serial_out(up, UART_LCR, 0);
770 serial_out(up, UART_IER, up->ier);
771 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
772
773 serial_out(up, UART_EFR, up->efr);
774 serial_out(up, UART_LCR, cval);
775
776 if (baud > 230400 && baud != 3000000)
777 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_13X_MODE);
778 else
779 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_16X_MODE);
780
781 /* Hardware Flow Control Configuration */
782
783 if (termios->c_cflag & CRTSCTS) {
784 efr |= (UART_EFR_CTS | UART_EFR_RTS);
785 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
786
787 up->mcr = serial_in(up, UART_MCR);
788 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
789
790 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
791 up->efr = serial_in(up, UART_EFR);
792 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
793
794 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
795 serial_out(up, UART_EFR, efr); /* Enable AUTORTS and AUTOCTS */
796 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
797 serial_out(up, UART_MCR, up->mcr | UART_MCR_RTS);
798 serial_out(up, UART_LCR, cval);
799 }
800
801 serial_omap_set_mctrl(&up->port, up->port.mctrl);
802 /* Software Flow Control Configuration */
803 if (termios->c_iflag & (IXON | IXOFF))
804 serial_omap_configure_xonxoff(up, termios);
805
806 spin_unlock_irqrestore(&up->port.lock, flags);
807 dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->pdev->id);
808}
809
810static void
811serial_omap_pm(struct uart_port *port, unsigned int state,
812 unsigned int oldstate)
813{
814 struct uart_omap_port *up = (struct uart_omap_port *)port;
815 unsigned char efr;
816
817 dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->pdev->id);
818 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
819 efr = serial_in(up, UART_EFR);
820 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
821 serial_out(up, UART_LCR, 0);
822
823 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
824 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
825 serial_out(up, UART_EFR, efr);
826 serial_out(up, UART_LCR, 0);
827 /* Enable module level wake up */
828 serial_out(up, UART_OMAP_WER,
829 (state != 0) ? OMAP_UART_WER_MOD_WKUP : 0);
830}
831
832static void serial_omap_release_port(struct uart_port *port)
833{
834 dev_dbg(port->dev, "serial_omap_release_port+\n");
835}
836
837static int serial_omap_request_port(struct uart_port *port)
838{
839 dev_dbg(port->dev, "serial_omap_request_port+\n");
840 return 0;
841}
842
843static void serial_omap_config_port(struct uart_port *port, int flags)
844{
845 struct uart_omap_port *up = (struct uart_omap_port *)port;
846
847 dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
848 up->pdev->id);
849 up->port.type = PORT_OMAP;
850}
851
852static int
853serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
854{
855 /* we don't want the core code to modify any port params */
856 dev_dbg(port->dev, "serial_omap_verify_port+\n");
857 return -EINVAL;
858}
859
860static const char *
861serial_omap_type(struct uart_port *port)
862{
863 struct uart_omap_port *up = (struct uart_omap_port *)port;
864
865 dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->pdev->id);
866 return up->name;
867}
868
869#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
870
871static inline void wait_for_xmitr(struct uart_omap_port *up)
872{
873 unsigned int status, tmout = 10000;
874
875 /* Wait up to 10ms for the character(s) to be sent. */
876 do {
877 status = serial_in(up, UART_LSR);
878
879 if (status & UART_LSR_BI)
880 up->lsr_break_flag = UART_LSR_BI;
881
882 if (--tmout == 0)
883 break;
884 udelay(1);
885 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
886
887 /* Wait up to 1s for flow control if necessary */
888 if (up->port.flags & UPF_CONS_FLOW) {
889 tmout = 1000000;
890 for (tmout = 1000000; tmout; tmout--) {
891 unsigned int msr = serial_in(up, UART_MSR);
892
893 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
894 if (msr & UART_MSR_CTS)
895 break;
896
897 udelay(1);
898 }
899 }
900}
901
902#ifdef CONFIG_CONSOLE_POLL
903
904static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
905{
906 struct uart_omap_port *up = (struct uart_omap_port *)port;
907 wait_for_xmitr(up);
908 serial_out(up, UART_TX, ch);
909}
910
911static int serial_omap_poll_get_char(struct uart_port *port)
912{
913 struct uart_omap_port *up = (struct uart_omap_port *)port;
914 unsigned int status = serial_in(up, UART_LSR);
915
916 if (!(status & UART_LSR_DR))
917 return NO_POLL_CHAR;
918
919 return serial_in(up, UART_RX);
920}
921
922#endif /* CONFIG_CONSOLE_POLL */
923
924#ifdef CONFIG_SERIAL_OMAP_CONSOLE
925
926static struct uart_omap_port *serial_omap_console_ports[4];
927
928static struct uart_driver serial_omap_reg;
929
930static void serial_omap_console_putchar(struct uart_port *port, int ch)
931{
932 struct uart_omap_port *up = (struct uart_omap_port *)port;
933
934 wait_for_xmitr(up);
935 serial_out(up, UART_TX, ch);
936}
937
938static void
939serial_omap_console_write(struct console *co, const char *s,
940 unsigned int count)
941{
942 struct uart_omap_port *up = serial_omap_console_ports[co->index];
943 unsigned long flags;
944 unsigned int ier;
945 int locked = 1;
946
947 local_irq_save(flags);
948 if (up->port.sysrq)
949 locked = 0;
950 else if (oops_in_progress)
951 locked = spin_trylock(&up->port.lock);
952 else
953 spin_lock(&up->port.lock);
954
955 /*
956 * First save the IER then disable the interrupts
957 */
958 ier = serial_in(up, UART_IER);
959 serial_out(up, UART_IER, 0);
960
961 uart_console_write(&up->port, s, count, serial_omap_console_putchar);
962
963 /*
964 * Finally, wait for transmitter to become empty
965 * and restore the IER
966 */
967 wait_for_xmitr(up);
968 serial_out(up, UART_IER, ier);
969 /*
970 * The receive handling will happen properly because the
971 * receive ready bit will still be set; it is not cleared
972 * on read. However, modem control will not, we must
973 * call it if we have saved something in the saved flags
974 * while processing with interrupts off.
975 */
976 if (up->msr_saved_flags)
977 check_modem_status(up);
978
979 if (locked)
980 spin_unlock(&up->port.lock);
981 local_irq_restore(flags);
982}
983
984static int __init
985serial_omap_console_setup(struct console *co, char *options)
986{
987 struct uart_omap_port *up;
988 int baud = 115200;
989 int bits = 8;
990 int parity = 'n';
991 int flow = 'n';
992
993 if (serial_omap_console_ports[co->index] == NULL)
994 return -ENODEV;
995 up = serial_omap_console_ports[co->index];
996
997 if (options)
998 uart_parse_options(options, &baud, &parity, &bits, &flow);
999
1000 return uart_set_options(&up->port, co, baud, parity, bits, flow);
1001}
1002
1003static struct console serial_omap_console = {
1004 .name = OMAP_SERIAL_NAME,
1005 .write = serial_omap_console_write,
1006 .device = uart_console_device,
1007 .setup = serial_omap_console_setup,
1008 .flags = CON_PRINTBUFFER,
1009 .index = -1,
1010 .data = &serial_omap_reg,
1011};
1012
1013static void serial_omap_add_console_port(struct uart_omap_port *up)
1014{
1015 serial_omap_console_ports[up->pdev->id] = up;
1016}
1017
1018#define OMAP_CONSOLE (&serial_omap_console)
1019
1020#else
1021
1022#define OMAP_CONSOLE NULL
1023
1024static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1025{}
1026
1027#endif
1028
1029static struct uart_ops serial_omap_pops = {
1030 .tx_empty = serial_omap_tx_empty,
1031 .set_mctrl = serial_omap_set_mctrl,
1032 .get_mctrl = serial_omap_get_mctrl,
1033 .stop_tx = serial_omap_stop_tx,
1034 .start_tx = serial_omap_start_tx,
1035 .stop_rx = serial_omap_stop_rx,
1036 .enable_ms = serial_omap_enable_ms,
1037 .break_ctl = serial_omap_break_ctl,
1038 .startup = serial_omap_startup,
1039 .shutdown = serial_omap_shutdown,
1040 .set_termios = serial_omap_set_termios,
1041 .pm = serial_omap_pm,
1042 .type = serial_omap_type,
1043 .release_port = serial_omap_release_port,
1044 .request_port = serial_omap_request_port,
1045 .config_port = serial_omap_config_port,
1046 .verify_port = serial_omap_verify_port,
1047#ifdef CONFIG_CONSOLE_POLL
1048 .poll_put_char = serial_omap_poll_put_char,
1049 .poll_get_char = serial_omap_poll_get_char,
1050#endif
1051};
1052
1053static struct uart_driver serial_omap_reg = {
1054 .owner = THIS_MODULE,
1055 .driver_name = "OMAP-SERIAL",
1056 .dev_name = OMAP_SERIAL_NAME,
1057 .nr = OMAP_MAX_HSUART_PORTS,
1058 .cons = OMAP_CONSOLE,
1059};
1060
1061static int
1062serial_omap_suspend(struct platform_device *pdev, pm_message_t state)
1063{
1064 struct uart_omap_port *up = platform_get_drvdata(pdev);
1065
1066 if (up)
1067 uart_suspend_port(&serial_omap_reg, &up->port);
1068 return 0;
1069}
1070
1071static int serial_omap_resume(struct platform_device *dev)
1072{
1073 struct uart_omap_port *up = platform_get_drvdata(dev);
1074
1075 if (up)
1076 uart_resume_port(&serial_omap_reg, &up->port);
1077 return 0;
1078}
1079
1080static void serial_omap_rx_timeout(unsigned long uart_no)
1081{
1082 struct uart_omap_port *up = ui[uart_no];
1083 unsigned int curr_dma_pos, curr_transmitted_size;
1084 int ret = 0;
1085
1086 curr_dma_pos = omap_get_dma_dst_pos(up->uart_dma.rx_dma_channel);
1087 if ((curr_dma_pos == up->uart_dma.prev_rx_dma_pos) ||
1088 (curr_dma_pos == 0)) {
1089 if (jiffies_to_msecs(jiffies - up->port_activity) <
1090 RX_TIMEOUT) {
1091 mod_timer(&up->uart_dma.rx_timer, jiffies +
1092 usecs_to_jiffies(up->uart_dma.rx_timeout));
1093 } else {
1094 serial_omap_stop_rxdma(up);
1095 up->ier |= (UART_IER_RDI | UART_IER_RLSI);
1096 serial_out(up, UART_IER, up->ier);
1097 }
1098 return;
1099 }
1100
1101 curr_transmitted_size = curr_dma_pos -
1102 up->uart_dma.prev_rx_dma_pos;
1103 up->port.icount.rx += curr_transmitted_size;
1104 tty_insert_flip_string(up->port.state->port.tty,
1105 up->uart_dma.rx_buf +
1106 (up->uart_dma.prev_rx_dma_pos -
1107 up->uart_dma.rx_buf_dma_phys),
1108 curr_transmitted_size);
1109 tty_flip_buffer_push(up->port.state->port.tty);
1110 up->uart_dma.prev_rx_dma_pos = curr_dma_pos;
1111 if (up->uart_dma.rx_buf_size +
1112 up->uart_dma.rx_buf_dma_phys == curr_dma_pos) {
1113 ret = serial_omap_start_rxdma(up);
1114 if (ret < 0) {
1115 serial_omap_stop_rxdma(up);
1116 up->ier |= (UART_IER_RDI | UART_IER_RLSI);
1117 serial_out(up, UART_IER, up->ier);
1118 }
1119 } else {
1120 mod_timer(&up->uart_dma.rx_timer, jiffies +
1121 usecs_to_jiffies(up->uart_dma.rx_timeout));
1122 }
1123 up->port_activity = jiffies;
1124}
1125
1126static void uart_rx_dma_callback(int lch, u16 ch_status, void *data)
1127{
1128 return;
1129}
1130
1131static int serial_omap_start_rxdma(struct uart_omap_port *up)
1132{
1133 int ret = 0;
1134
1135 if (up->uart_dma.rx_dma_channel == -1) {
1136 ret = omap_request_dma(up->uart_dma.uart_dma_rx,
1137 "UART Rx DMA",
1138 (void *)uart_rx_dma_callback, up,
1139 &(up->uart_dma.rx_dma_channel));
1140 if (ret < 0)
1141 return ret;
1142
1143 omap_set_dma_src_params(up->uart_dma.rx_dma_channel, 0,
1144 OMAP_DMA_AMODE_CONSTANT,
1145 up->uart_dma.uart_base, 0, 0);
1146 omap_set_dma_dest_params(up->uart_dma.rx_dma_channel, 0,
1147 OMAP_DMA_AMODE_POST_INC,
1148 up->uart_dma.rx_buf_dma_phys, 0, 0);
1149 omap_set_dma_transfer_params(up->uart_dma.rx_dma_channel,
1150 OMAP_DMA_DATA_TYPE_S8,
1151 up->uart_dma.rx_buf_size, 1,
1152 OMAP_DMA_SYNC_ELEMENT,
1153 up->uart_dma.uart_dma_rx, 0);
1154 }
1155 up->uart_dma.prev_rx_dma_pos = up->uart_dma.rx_buf_dma_phys;
1156 /* FIXME: Cache maintenance needed here? */
1157 omap_start_dma(up->uart_dma.rx_dma_channel);
1158 mod_timer(&up->uart_dma.rx_timer, jiffies +
1159 usecs_to_jiffies(up->uart_dma.rx_timeout));
1160 up->uart_dma.rx_dma_used = true;
1161 return ret;
1162}
1163
1164static void serial_omap_continue_tx(struct uart_omap_port *up)
1165{
1166 struct circ_buf *xmit = &up->port.state->xmit;
1167 unsigned int start = up->uart_dma.tx_buf_dma_phys
1168 + (xmit->tail & (UART_XMIT_SIZE - 1));
1169
1170 if (uart_circ_empty(xmit))
1171 return;
1172
1173 up->uart_dma.tx_buf_size = uart_circ_chars_pending(xmit);
1174 /*
1175 * It is a circular buffer. See if the buffer has wounded back.
1176 * If yes it will have to be transferred in two separate dma
1177 * transfers
1178 */
1179 if (start + up->uart_dma.tx_buf_size >=
1180 up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE)
1181 up->uart_dma.tx_buf_size =
1182 (up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE) - start;
1183 omap_set_dma_dest_params(up->uart_dma.tx_dma_channel, 0,
1184 OMAP_DMA_AMODE_CONSTANT,
1185 up->uart_dma.uart_base, 0, 0);
1186 omap_set_dma_src_params(up->uart_dma.tx_dma_channel, 0,
1187 OMAP_DMA_AMODE_POST_INC, start, 0, 0);
1188 omap_set_dma_transfer_params(up->uart_dma.tx_dma_channel,
1189 OMAP_DMA_DATA_TYPE_S8,
1190 up->uart_dma.tx_buf_size, 1,
1191 OMAP_DMA_SYNC_ELEMENT,
1192 up->uart_dma.uart_dma_tx, 0);
1193 /* FIXME: Cache maintenance needed here? */
1194 omap_start_dma(up->uart_dma.tx_dma_channel);
1195}
1196
1197static void uart_tx_dma_callback(int lch, u16 ch_status, void *data)
1198{
1199 struct uart_omap_port *up = (struct uart_omap_port *)data;
1200 struct circ_buf *xmit = &up->port.state->xmit;
1201
1202 xmit->tail = (xmit->tail + up->uart_dma.tx_buf_size) & \
1203 (UART_XMIT_SIZE - 1);
1204 up->port.icount.tx += up->uart_dma.tx_buf_size;
1205
1206 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1207 uart_write_wakeup(&up->port);
1208
1209 if (uart_circ_empty(xmit)) {
1210 spin_lock(&(up->uart_dma.tx_lock));
1211 serial_omap_stop_tx(&up->port);
1212 up->uart_dma.tx_dma_used = false;
1213 spin_unlock(&(up->uart_dma.tx_lock));
1214 } else {
1215 omap_stop_dma(up->uart_dma.tx_dma_channel);
1216 serial_omap_continue_tx(up);
1217 }
1218 up->port_activity = jiffies;
1219 return;
1220}
1221
1222static int serial_omap_probe(struct platform_device *pdev)
1223{
1224 struct uart_omap_port *up;
1225 struct resource *mem, *irq, *dma_tx, *dma_rx;
1226 struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data;
1227 int ret = -ENOSPC;
1228
1229 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1230 if (!mem) {
1231 dev_err(&pdev->dev, "no mem resource?\n");
1232 return -ENODEV;
1233 }
1234
1235 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1236 if (!irq) {
1237 dev_err(&pdev->dev, "no irq resource?\n");
1238 return -ENODEV;
1239 }
1240
1241 if (!request_mem_region(mem->start, (mem->end - mem->start) + 1,
1242 pdev->dev.driver->name)) {
1243 dev_err(&pdev->dev, "memory region already claimed\n");
1244 return -EBUSY;
1245 }
1246
1247 dma_rx = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1248 if (!dma_rx) {
1249 ret = -EINVAL;
1250 goto err;
1251 }
1252
1253 dma_tx = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1254 if (!dma_tx) {
1255 ret = -EINVAL;
1256 goto err;
1257 }
1258
1259 up = kzalloc(sizeof(*up), GFP_KERNEL);
1260 if (up == NULL) {
1261 ret = -ENOMEM;
1262 goto do_release_region;
1263 }
1264 sprintf(up->name, "OMAP UART%d", pdev->id);
1265 up->pdev = pdev;
1266 up->port.dev = &pdev->dev;
1267 up->port.type = PORT_OMAP;
1268 up->port.iotype = UPIO_MEM;
1269 up->port.irq = irq->start;
1270
1271 up->port.regshift = 2;
1272 up->port.fifosize = 64;
1273 up->port.ops = &serial_omap_pops;
1274 up->port.line = pdev->id;
1275
1276 up->port.membase = omap_up_info->membase;
1277 up->port.mapbase = omap_up_info->mapbase;
1278 up->port.flags = omap_up_info->flags;
1279 up->port.irqflags = omap_up_info->irqflags;
1280 up->port.uartclk = omap_up_info->uartclk;
1281 up->uart_dma.uart_base = mem->start;
1282
1283 if (omap_up_info->dma_enabled) {
1284 up->uart_dma.uart_dma_tx = dma_tx->start;
1285 up->uart_dma.uart_dma_rx = dma_rx->start;
1286 up->use_dma = 1;
1287 up->uart_dma.rx_buf_size = 4096;
1288 up->uart_dma.rx_timeout = 2;
1289 spin_lock_init(&(up->uart_dma.tx_lock));
1290 spin_lock_init(&(up->uart_dma.rx_lock));
1291 up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE;
1292 up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE;
1293 }
1294
1295 ui[pdev->id] = up;
1296 serial_omap_add_console_port(up);
1297
1298 ret = uart_add_one_port(&serial_omap_reg, &up->port);
1299 if (ret != 0)
1300 goto do_release_region;
1301
1302 platform_set_drvdata(pdev, up);
1303 return 0;
1304err:
1305 dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n",
1306 pdev->id, __func__, ret);
1307do_release_region:
1308 release_mem_region(mem->start, (mem->end - mem->start) + 1);
1309 return ret;
1310}
1311
1312static int serial_omap_remove(struct platform_device *dev)
1313{
1314 struct uart_omap_port *up = platform_get_drvdata(dev);
1315
1316 platform_set_drvdata(dev, NULL);
1317 if (up) {
1318 uart_remove_one_port(&serial_omap_reg, &up->port);
1319 kfree(up);
1320 }
1321 return 0;
1322}
1323
1324static struct platform_driver serial_omap_driver = {
1325 .probe = serial_omap_probe,
1326 .remove = serial_omap_remove,
1327
1328 .suspend = serial_omap_suspend,
1329 .resume = serial_omap_resume,
1330 .driver = {
1331 .name = DRIVER_NAME,
1332 },
1333};
1334
1335static int __init serial_omap_init(void)
1336{
1337 int ret;
1338
1339 ret = uart_register_driver(&serial_omap_reg);
1340 if (ret != 0)
1341 return ret;
1342 ret = platform_driver_register(&serial_omap_driver);
1343 if (ret != 0)
1344 uart_unregister_driver(&serial_omap_reg);
1345 return ret;
1346}
1347
1348static void __exit serial_omap_exit(void)
1349{
1350 platform_driver_unregister(&serial_omap_driver);
1351 uart_unregister_driver(&serial_omap_reg);
1352}
1353
1354module_init(serial_omap_init);
1355module_exit(serial_omap_exit);
1356
1357MODULE_DESCRIPTION("OMAP High Speed UART driver");
1358MODULE_LICENSE("GPL");
1359MODULE_AUTHOR("Texas Instruments Inc");
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-24 01:43:55 -0500