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-rw-r--r--drivers/tty/serial/msm_serial.h28
1 files changed, 22 insertions, 6 deletions
diff --git a/drivers/tty/serial/msm_serial.h b/drivers/tty/serial/msm_serial.h
index f6ca9ca79e98..9b8dc5d0d855 100644
--- a/drivers/tty/serial/msm_serial.h
+++ b/drivers/tty/serial/msm_serial.h
@@ -3,6 +3,7 @@
3 * 3 *
4 * Copyright (C) 2007 Google, Inc. 4 * Copyright (C) 2007 Google, Inc.
5 * Author: Robert Love <rlove@google.com> 5 * Author: Robert Love <rlove@google.com>
6 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
6 * 7 *
7 * This software is licensed under the terms of the GNU General Public 8 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and 9 * License version 2, as published by the Free Software Foundation, and
@@ -54,6 +55,7 @@
54#define UART_CSR_300 0x22 55#define UART_CSR_300 0x22
55 56
56#define UART_TF 0x000C 57#define UART_TF 0x000C
58#define UARTDM_TF 0x0070
57 59
58#define UART_CR 0x0010 60#define UART_CR 0x0010
59#define UART_CR_CMD_NULL (0 << 4) 61#define UART_CR_CMD_NULL (0 << 4)
@@ -64,14 +66,17 @@
64#define UART_CR_CMD_START_BREAK (5 << 4) 66#define UART_CR_CMD_START_BREAK (5 << 4)
65#define UART_CR_CMD_STOP_BREAK (6 << 4) 67#define UART_CR_CMD_STOP_BREAK (6 << 4)
66#define UART_CR_CMD_RESET_CTS (7 << 4) 68#define UART_CR_CMD_RESET_CTS (7 << 4)
69#define UART_CR_CMD_RESET_STALE_INT (8 << 4)
67#define UART_CR_CMD_PACKET_MODE (9 << 4) 70#define UART_CR_CMD_PACKET_MODE (9 << 4)
68#define UART_CR_CMD_MODE_RESET (12 << 4) 71#define UART_CR_CMD_MODE_RESET (12 << 4)
69#define UART_CR_CMD_SET_RFR (13 << 4) 72#define UART_CR_CMD_SET_RFR (13 << 4)
70#define UART_CR_CMD_RESET_RFR (14 << 4) 73#define UART_CR_CMD_RESET_RFR (14 << 4)
74#define UART_CR_CMD_PROTECTION_EN (16 << 4)
75#define UART_CR_CMD_STALE_EVENT_ENABLE (80 << 4)
71#define UART_CR_TX_DISABLE (1 << 3) 76#define UART_CR_TX_DISABLE (1 << 3)
72#define UART_CR_TX_ENABLE (1 << 3) 77#define UART_CR_TX_ENABLE (1 << 2)
73#define UART_CR_RX_DISABLE (1 << 3) 78#define UART_CR_RX_DISABLE (1 << 1)
74#define UART_CR_RX_ENABLE (1 << 3) 79#define UART_CR_RX_ENABLE (1 << 0)
75 80
76#define UART_IMR 0x0014 81#define UART_IMR 0x0014
77#define UART_IMR_TXLEV (1 << 0) 82#define UART_IMR_TXLEV (1 << 0)
@@ -110,9 +115,20 @@
110#define UART_SR_RX_FULL (1 << 1) 115#define UART_SR_RX_FULL (1 << 1)
111#define UART_SR_RX_READY (1 << 0) 116#define UART_SR_RX_READY (1 << 0)
112 117
113#define UART_RF 0x000C 118#define UART_RF 0x000C
114#define UART_MISR 0x0010 119#define UARTDM_RF 0x0070
115#define UART_ISR 0x0014 120#define UART_MISR 0x0010
121#define UART_ISR 0x0014
122#define UART_ISR_TX_READY (1 << 7)
123
124#define GSBI_CONTROL 0x0
125#define GSBI_PROTOCOL_CODE 0x30
126#define GSBI_PROTOCOL_UART 0x40
127#define GSBI_PROTOCOL_IDLE 0x0
128
129#define UARTDM_DMRX 0x34
130#define UARTDM_NCF_TX 0x40
131#define UARTDM_RX_TOTAL_SNAP 0x38
116 132
117#define UART_TO_MSM(uart_port) ((struct msm_port *) uart_port) 133#define UART_TO_MSM(uart_port) ((struct msm_port *) uart_port)
118 134