diff options
Diffstat (limited to 'drivers/tty/serial/mfd.c')
-rw-r--r-- | drivers/tty/serial/mfd.c | 1513 |
1 files changed, 1513 insertions, 0 deletions
diff --git a/drivers/tty/serial/mfd.c b/drivers/tty/serial/mfd.c new file mode 100644 index 000000000000..d40010a22ecd --- /dev/null +++ b/drivers/tty/serial/mfd.c | |||
@@ -0,0 +1,1513 @@ | |||
1 | /* | ||
2 | * mfd.c: driver for High Speed UART device of Intel Medfield platform | ||
3 | * | ||
4 | * Refer pxa.c, 8250.c and some other drivers in drivers/serial/ | ||
5 | * | ||
6 | * (C) Copyright 2010 Intel Corporation | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or | ||
9 | * modify it under the terms of the GNU General Public License | ||
10 | * as published by the Free Software Foundation; version 2 | ||
11 | * of the License. | ||
12 | */ | ||
13 | |||
14 | /* Notes: | ||
15 | * 1. DMA channel allocation: 0/1 channel are assigned to port 0, | ||
16 | * 2/3 chan to port 1, 4/5 chan to port 3. Even number chans | ||
17 | * are used for RX, odd chans for TX | ||
18 | * | ||
19 | * 2. In A0 stepping, UART will not support TX half empty flag | ||
20 | * | ||
21 | * 3. The RI/DSR/DCD/DTR are not pinned out, DCD & DSR are always | ||
22 | * asserted, only when the HW is reset the DDCD and DDSR will | ||
23 | * be triggered | ||
24 | */ | ||
25 | |||
26 | #include <linux/module.h> | ||
27 | #include <linux/init.h> | ||
28 | #include <linux/console.h> | ||
29 | #include <linux/sysrq.h> | ||
30 | #include <linux/slab.h> | ||
31 | #include <linux/serial_reg.h> | ||
32 | #include <linux/circ_buf.h> | ||
33 | #include <linux/delay.h> | ||
34 | #include <linux/interrupt.h> | ||
35 | #include <linux/tty.h> | ||
36 | #include <linux/tty_flip.h> | ||
37 | #include <linux/serial_core.h> | ||
38 | #include <linux/serial_mfd.h> | ||
39 | #include <linux/dma-mapping.h> | ||
40 | #include <linux/pci.h> | ||
41 | #include <linux/io.h> | ||
42 | #include <linux/debugfs.h> | ||
43 | |||
44 | #define MFD_HSU_A0_STEPPING 1 | ||
45 | |||
46 | #define HSU_DMA_BUF_SIZE 2048 | ||
47 | |||
48 | #define chan_readl(chan, offset) readl(chan->reg + offset) | ||
49 | #define chan_writel(chan, offset, val) writel(val, chan->reg + offset) | ||
50 | |||
51 | #define mfd_readl(obj, offset) readl(obj->reg + offset) | ||
52 | #define mfd_writel(obj, offset, val) writel(val, obj->reg + offset) | ||
53 | |||
54 | #define HSU_DMA_TIMEOUT_CHECK_FREQ (HZ/10) | ||
55 | |||
56 | struct hsu_dma_buffer { | ||
57 | u8 *buf; | ||
58 | dma_addr_t dma_addr; | ||
59 | u32 dma_size; | ||
60 | u32 ofs; | ||
61 | }; | ||
62 | |||
63 | struct hsu_dma_chan { | ||
64 | u32 id; | ||
65 | enum dma_data_direction dirt; | ||
66 | struct uart_hsu_port *uport; | ||
67 | void __iomem *reg; | ||
68 | struct timer_list rx_timer; /* only needed by RX channel */ | ||
69 | }; | ||
70 | |||
71 | struct uart_hsu_port { | ||
72 | struct uart_port port; | ||
73 | unsigned char ier; | ||
74 | unsigned char lcr; | ||
75 | unsigned char mcr; | ||
76 | unsigned int lsr_break_flag; | ||
77 | char name[12]; | ||
78 | int index; | ||
79 | struct device *dev; | ||
80 | |||
81 | struct hsu_dma_chan *txc; | ||
82 | struct hsu_dma_chan *rxc; | ||
83 | struct hsu_dma_buffer txbuf; | ||
84 | struct hsu_dma_buffer rxbuf; | ||
85 | int use_dma; /* flag for DMA/PIO */ | ||
86 | int running; | ||
87 | int dma_tx_on; | ||
88 | }; | ||
89 | |||
90 | /* Top level data structure of HSU */ | ||
91 | struct hsu_port { | ||
92 | void __iomem *reg; | ||
93 | unsigned long paddr; | ||
94 | unsigned long iolen; | ||
95 | u32 irq; | ||
96 | |||
97 | struct uart_hsu_port port[3]; | ||
98 | struct hsu_dma_chan chans[10]; | ||
99 | |||
100 | struct dentry *debugfs; | ||
101 | }; | ||
102 | |||
103 | static inline unsigned int serial_in(struct uart_hsu_port *up, int offset) | ||
104 | { | ||
105 | unsigned int val; | ||
106 | |||
107 | if (offset > UART_MSR) { | ||
108 | offset <<= 2; | ||
109 | val = readl(up->port.membase + offset); | ||
110 | } else | ||
111 | val = (unsigned int)readb(up->port.membase + offset); | ||
112 | |||
113 | return val; | ||
114 | } | ||
115 | |||
116 | static inline void serial_out(struct uart_hsu_port *up, int offset, int value) | ||
117 | { | ||
118 | if (offset > UART_MSR) { | ||
119 | offset <<= 2; | ||
120 | writel(value, up->port.membase + offset); | ||
121 | } else { | ||
122 | unsigned char val = value & 0xff; | ||
123 | writeb(val, up->port.membase + offset); | ||
124 | } | ||
125 | } | ||
126 | |||
127 | #ifdef CONFIG_DEBUG_FS | ||
128 | |||
129 | #define HSU_REGS_BUFSIZE 1024 | ||
130 | |||
131 | static int hsu_show_regs_open(struct inode *inode, struct file *file) | ||
132 | { | ||
133 | file->private_data = inode->i_private; | ||
134 | return 0; | ||
135 | } | ||
136 | |||
137 | static ssize_t port_show_regs(struct file *file, char __user *user_buf, | ||
138 | size_t count, loff_t *ppos) | ||
139 | { | ||
140 | struct uart_hsu_port *up = file->private_data; | ||
141 | char *buf; | ||
142 | u32 len = 0; | ||
143 | ssize_t ret; | ||
144 | |||
145 | buf = kzalloc(HSU_REGS_BUFSIZE, GFP_KERNEL); | ||
146 | if (!buf) | ||
147 | return 0; | ||
148 | |||
149 | len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, | ||
150 | "MFD HSU port[%d] regs:\n", up->index); | ||
151 | |||
152 | len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, | ||
153 | "=================================\n"); | ||
154 | len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, | ||
155 | "IER: \t\t0x%08x\n", serial_in(up, UART_IER)); | ||
156 | len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, | ||
157 | "IIR: \t\t0x%08x\n", serial_in(up, UART_IIR)); | ||
158 | len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, | ||
159 | "LCR: \t\t0x%08x\n", serial_in(up, UART_LCR)); | ||
160 | len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, | ||
161 | "MCR: \t\t0x%08x\n", serial_in(up, UART_MCR)); | ||
162 | len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, | ||
163 | "LSR: \t\t0x%08x\n", serial_in(up, UART_LSR)); | ||
164 | len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, | ||
165 | "MSR: \t\t0x%08x\n", serial_in(up, UART_MSR)); | ||
166 | len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, | ||
167 | "FOR: \t\t0x%08x\n", serial_in(up, UART_FOR)); | ||
168 | len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, | ||
169 | "PS: \t\t0x%08x\n", serial_in(up, UART_PS)); | ||
170 | len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, | ||
171 | "MUL: \t\t0x%08x\n", serial_in(up, UART_MUL)); | ||
172 | len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, | ||
173 | "DIV: \t\t0x%08x\n", serial_in(up, UART_DIV)); | ||
174 | |||
175 | if (len > HSU_REGS_BUFSIZE) | ||
176 | len = HSU_REGS_BUFSIZE; | ||
177 | |||
178 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); | ||
179 | kfree(buf); | ||
180 | return ret; | ||
181 | } | ||
182 | |||
183 | static ssize_t dma_show_regs(struct file *file, char __user *user_buf, | ||
184 | size_t count, loff_t *ppos) | ||
185 | { | ||
186 | struct hsu_dma_chan *chan = file->private_data; | ||
187 | char *buf; | ||
188 | u32 len = 0; | ||
189 | ssize_t ret; | ||
190 | |||
191 | buf = kzalloc(HSU_REGS_BUFSIZE, GFP_KERNEL); | ||
192 | if (!buf) | ||
193 | return 0; | ||
194 | |||
195 | len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, | ||
196 | "MFD HSU DMA channel [%d] regs:\n", chan->id); | ||
197 | |||
198 | len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, | ||
199 | "=================================\n"); | ||
200 | len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, | ||
201 | "CR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_CR)); | ||
202 | len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, | ||
203 | "DCR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_DCR)); | ||
204 | len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, | ||
205 | "BSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_BSR)); | ||
206 | len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, | ||
207 | "MOTSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_MOTSR)); | ||
208 | len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, | ||
209 | "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D0SAR)); | ||
210 | len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, | ||
211 | "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D0TSR)); | ||
212 | len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, | ||
213 | "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D1SAR)); | ||
214 | len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, | ||
215 | "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D1TSR)); | ||
216 | len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, | ||
217 | "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D2SAR)); | ||
218 | len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, | ||
219 | "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D2TSR)); | ||
220 | len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, | ||
221 | "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D3SAR)); | ||
222 | len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, | ||
223 | "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D3TSR)); | ||
224 | |||
225 | if (len > HSU_REGS_BUFSIZE) | ||
226 | len = HSU_REGS_BUFSIZE; | ||
227 | |||
228 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); | ||
229 | kfree(buf); | ||
230 | return ret; | ||
231 | } | ||
232 | |||
233 | static const struct file_operations port_regs_ops = { | ||
234 | .owner = THIS_MODULE, | ||
235 | .open = hsu_show_regs_open, | ||
236 | .read = port_show_regs, | ||
237 | .llseek = default_llseek, | ||
238 | }; | ||
239 | |||
240 | static const struct file_operations dma_regs_ops = { | ||
241 | .owner = THIS_MODULE, | ||
242 | .open = hsu_show_regs_open, | ||
243 | .read = dma_show_regs, | ||
244 | .llseek = default_llseek, | ||
245 | }; | ||
246 | |||
247 | static int hsu_debugfs_init(struct hsu_port *hsu) | ||
248 | { | ||
249 | int i; | ||
250 | char name[32]; | ||
251 | |||
252 | hsu->debugfs = debugfs_create_dir("hsu", NULL); | ||
253 | if (!hsu->debugfs) | ||
254 | return -ENOMEM; | ||
255 | |||
256 | for (i = 0; i < 3; i++) { | ||
257 | snprintf(name, sizeof(name), "port_%d_regs", i); | ||
258 | debugfs_create_file(name, S_IFREG | S_IRUGO, | ||
259 | hsu->debugfs, (void *)(&hsu->port[i]), &port_regs_ops); | ||
260 | } | ||
261 | |||
262 | for (i = 0; i < 6; i++) { | ||
263 | snprintf(name, sizeof(name), "dma_chan_%d_regs", i); | ||
264 | debugfs_create_file(name, S_IFREG | S_IRUGO, | ||
265 | hsu->debugfs, (void *)&hsu->chans[i], &dma_regs_ops); | ||
266 | } | ||
267 | |||
268 | return 0; | ||
269 | } | ||
270 | |||
271 | static void hsu_debugfs_remove(struct hsu_port *hsu) | ||
272 | { | ||
273 | if (hsu->debugfs) | ||
274 | debugfs_remove_recursive(hsu->debugfs); | ||
275 | } | ||
276 | |||
277 | #else | ||
278 | static inline int hsu_debugfs_init(struct hsu_port *hsu) | ||
279 | { | ||
280 | return 0; | ||
281 | } | ||
282 | |||
283 | static inline void hsu_debugfs_remove(struct hsu_port *hsu) | ||
284 | { | ||
285 | } | ||
286 | #endif /* CONFIG_DEBUG_FS */ | ||
287 | |||
288 | static void serial_hsu_enable_ms(struct uart_port *port) | ||
289 | { | ||
290 | struct uart_hsu_port *up = | ||
291 | container_of(port, struct uart_hsu_port, port); | ||
292 | |||
293 | up->ier |= UART_IER_MSI; | ||
294 | serial_out(up, UART_IER, up->ier); | ||
295 | } | ||
296 | |||
297 | void hsu_dma_tx(struct uart_hsu_port *up) | ||
298 | { | ||
299 | struct circ_buf *xmit = &up->port.state->xmit; | ||
300 | struct hsu_dma_buffer *dbuf = &up->txbuf; | ||
301 | int count; | ||
302 | |||
303 | /* test_and_set_bit may be better, but anyway it's in lock protected mode */ | ||
304 | if (up->dma_tx_on) | ||
305 | return; | ||
306 | |||
307 | /* Update the circ buf info */ | ||
308 | xmit->tail += dbuf->ofs; | ||
309 | xmit->tail &= UART_XMIT_SIZE - 1; | ||
310 | |||
311 | up->port.icount.tx += dbuf->ofs; | ||
312 | dbuf->ofs = 0; | ||
313 | |||
314 | /* Disable the channel */ | ||
315 | chan_writel(up->txc, HSU_CH_CR, 0x0); | ||
316 | |||
317 | if (!uart_circ_empty(xmit) && !uart_tx_stopped(&up->port)) { | ||
318 | dma_sync_single_for_device(up->port.dev, | ||
319 | dbuf->dma_addr, | ||
320 | dbuf->dma_size, | ||
321 | DMA_TO_DEVICE); | ||
322 | |||
323 | count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); | ||
324 | dbuf->ofs = count; | ||
325 | |||
326 | /* Reprogram the channel */ | ||
327 | chan_writel(up->txc, HSU_CH_D0SAR, dbuf->dma_addr + xmit->tail); | ||
328 | chan_writel(up->txc, HSU_CH_D0TSR, count); | ||
329 | |||
330 | /* Reenable the channel */ | ||
331 | chan_writel(up->txc, HSU_CH_DCR, 0x1 | ||
332 | | (0x1 << 8) | ||
333 | | (0x1 << 16) | ||
334 | | (0x1 << 24)); | ||
335 | up->dma_tx_on = 1; | ||
336 | chan_writel(up->txc, HSU_CH_CR, 0x1); | ||
337 | } | ||
338 | |||
339 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | ||
340 | uart_write_wakeup(&up->port); | ||
341 | } | ||
342 | |||
343 | /* The buffer is already cache coherent */ | ||
344 | void hsu_dma_start_rx_chan(struct hsu_dma_chan *rxc, struct hsu_dma_buffer *dbuf) | ||
345 | { | ||
346 | dbuf->ofs = 0; | ||
347 | |||
348 | chan_writel(rxc, HSU_CH_BSR, 32); | ||
349 | chan_writel(rxc, HSU_CH_MOTSR, 4); | ||
350 | |||
351 | chan_writel(rxc, HSU_CH_D0SAR, dbuf->dma_addr); | ||
352 | chan_writel(rxc, HSU_CH_D0TSR, dbuf->dma_size); | ||
353 | chan_writel(rxc, HSU_CH_DCR, 0x1 | (0x1 << 8) | ||
354 | | (0x1 << 16) | ||
355 | | (0x1 << 24) /* timeout bit, see HSU Errata 1 */ | ||
356 | ); | ||
357 | chan_writel(rxc, HSU_CH_CR, 0x3); | ||
358 | |||
359 | mod_timer(&rxc->rx_timer, jiffies + HSU_DMA_TIMEOUT_CHECK_FREQ); | ||
360 | } | ||
361 | |||
362 | /* Protected by spin_lock_irqsave(port->lock) */ | ||
363 | static void serial_hsu_start_tx(struct uart_port *port) | ||
364 | { | ||
365 | struct uart_hsu_port *up = | ||
366 | container_of(port, struct uart_hsu_port, port); | ||
367 | |||
368 | if (up->use_dma) { | ||
369 | hsu_dma_tx(up); | ||
370 | } else if (!(up->ier & UART_IER_THRI)) { | ||
371 | up->ier |= UART_IER_THRI; | ||
372 | serial_out(up, UART_IER, up->ier); | ||
373 | } | ||
374 | } | ||
375 | |||
376 | static void serial_hsu_stop_tx(struct uart_port *port) | ||
377 | { | ||
378 | struct uart_hsu_port *up = | ||
379 | container_of(port, struct uart_hsu_port, port); | ||
380 | struct hsu_dma_chan *txc = up->txc; | ||
381 | |||
382 | if (up->use_dma) | ||
383 | chan_writel(txc, HSU_CH_CR, 0x0); | ||
384 | else if (up->ier & UART_IER_THRI) { | ||
385 | up->ier &= ~UART_IER_THRI; | ||
386 | serial_out(up, UART_IER, up->ier); | ||
387 | } | ||
388 | } | ||
389 | |||
390 | /* This is always called in spinlock protected mode, so | ||
391 | * modify timeout timer is safe here */ | ||
392 | void hsu_dma_rx(struct uart_hsu_port *up, u32 int_sts) | ||
393 | { | ||
394 | struct hsu_dma_buffer *dbuf = &up->rxbuf; | ||
395 | struct hsu_dma_chan *chan = up->rxc; | ||
396 | struct uart_port *port = &up->port; | ||
397 | struct tty_struct *tty = port->state->port.tty; | ||
398 | int count; | ||
399 | |||
400 | if (!tty) | ||
401 | return; | ||
402 | |||
403 | /* | ||
404 | * First need to know how many is already transferred, | ||
405 | * then check if its a timeout DMA irq, and return | ||
406 | * the trail bytes out, push them up and reenable the | ||
407 | * channel | ||
408 | */ | ||
409 | |||
410 | /* Timeout IRQ, need wait some time, see Errata 2 */ | ||
411 | if (int_sts & 0xf00) | ||
412 | udelay(2); | ||
413 | |||
414 | /* Stop the channel */ | ||
415 | chan_writel(chan, HSU_CH_CR, 0x0); | ||
416 | |||
417 | count = chan_readl(chan, HSU_CH_D0SAR) - dbuf->dma_addr; | ||
418 | if (!count) { | ||
419 | /* Restart the channel before we leave */ | ||
420 | chan_writel(chan, HSU_CH_CR, 0x3); | ||
421 | return; | ||
422 | } | ||
423 | del_timer(&chan->rx_timer); | ||
424 | |||
425 | dma_sync_single_for_cpu(port->dev, dbuf->dma_addr, | ||
426 | dbuf->dma_size, DMA_FROM_DEVICE); | ||
427 | |||
428 | /* | ||
429 | * Head will only wrap around when we recycle | ||
430 | * the DMA buffer, and when that happens, we | ||
431 | * explicitly set tail to 0. So head will | ||
432 | * always be greater than tail. | ||
433 | */ | ||
434 | tty_insert_flip_string(tty, dbuf->buf, count); | ||
435 | port->icount.rx += count; | ||
436 | |||
437 | dma_sync_single_for_device(up->port.dev, dbuf->dma_addr, | ||
438 | dbuf->dma_size, DMA_FROM_DEVICE); | ||
439 | |||
440 | /* Reprogram the channel */ | ||
441 | chan_writel(chan, HSU_CH_D0SAR, dbuf->dma_addr); | ||
442 | chan_writel(chan, HSU_CH_D0TSR, dbuf->dma_size); | ||
443 | chan_writel(chan, HSU_CH_DCR, 0x1 | ||
444 | | (0x1 << 8) | ||
445 | | (0x1 << 16) | ||
446 | | (0x1 << 24) /* timeout bit, see HSU Errata 1 */ | ||
447 | ); | ||
448 | tty_flip_buffer_push(tty); | ||
449 | |||
450 | chan_writel(chan, HSU_CH_CR, 0x3); | ||
451 | chan->rx_timer.expires = jiffies + HSU_DMA_TIMEOUT_CHECK_FREQ; | ||
452 | add_timer(&chan->rx_timer); | ||
453 | |||
454 | } | ||
455 | |||
456 | static void serial_hsu_stop_rx(struct uart_port *port) | ||
457 | { | ||
458 | struct uart_hsu_port *up = | ||
459 | container_of(port, struct uart_hsu_port, port); | ||
460 | struct hsu_dma_chan *chan = up->rxc; | ||
461 | |||
462 | if (up->use_dma) | ||
463 | chan_writel(chan, HSU_CH_CR, 0x2); | ||
464 | else { | ||
465 | up->ier &= ~UART_IER_RLSI; | ||
466 | up->port.read_status_mask &= ~UART_LSR_DR; | ||
467 | serial_out(up, UART_IER, up->ier); | ||
468 | } | ||
469 | } | ||
470 | |||
471 | static inline void receive_chars(struct uart_hsu_port *up, int *status) | ||
472 | { | ||
473 | struct tty_struct *tty = up->port.state->port.tty; | ||
474 | unsigned int ch, flag; | ||
475 | unsigned int max_count = 256; | ||
476 | |||
477 | if (!tty) | ||
478 | return; | ||
479 | |||
480 | do { | ||
481 | ch = serial_in(up, UART_RX); | ||
482 | flag = TTY_NORMAL; | ||
483 | up->port.icount.rx++; | ||
484 | |||
485 | if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE | | ||
486 | UART_LSR_FE | UART_LSR_OE))) { | ||
487 | |||
488 | dev_warn(up->dev, "We really rush into ERR/BI case" | ||
489 | "status = 0x%02x", *status); | ||
490 | /* For statistics only */ | ||
491 | if (*status & UART_LSR_BI) { | ||
492 | *status &= ~(UART_LSR_FE | UART_LSR_PE); | ||
493 | up->port.icount.brk++; | ||
494 | /* | ||
495 | * We do the SysRQ and SAK checking | ||
496 | * here because otherwise the break | ||
497 | * may get masked by ignore_status_mask | ||
498 | * or read_status_mask. | ||
499 | */ | ||
500 | if (uart_handle_break(&up->port)) | ||
501 | goto ignore_char; | ||
502 | } else if (*status & UART_LSR_PE) | ||
503 | up->port.icount.parity++; | ||
504 | else if (*status & UART_LSR_FE) | ||
505 | up->port.icount.frame++; | ||
506 | if (*status & UART_LSR_OE) | ||
507 | up->port.icount.overrun++; | ||
508 | |||
509 | /* Mask off conditions which should be ignored. */ | ||
510 | *status &= up->port.read_status_mask; | ||
511 | |||
512 | #ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE | ||
513 | if (up->port.cons && | ||
514 | up->port.cons->index == up->port.line) { | ||
515 | /* Recover the break flag from console xmit */ | ||
516 | *status |= up->lsr_break_flag; | ||
517 | up->lsr_break_flag = 0; | ||
518 | } | ||
519 | #endif | ||
520 | if (*status & UART_LSR_BI) { | ||
521 | flag = TTY_BREAK; | ||
522 | } else if (*status & UART_LSR_PE) | ||
523 | flag = TTY_PARITY; | ||
524 | else if (*status & UART_LSR_FE) | ||
525 | flag = TTY_FRAME; | ||
526 | } | ||
527 | |||
528 | if (uart_handle_sysrq_char(&up->port, ch)) | ||
529 | goto ignore_char; | ||
530 | |||
531 | uart_insert_char(&up->port, *status, UART_LSR_OE, ch, flag); | ||
532 | ignore_char: | ||
533 | *status = serial_in(up, UART_LSR); | ||
534 | } while ((*status & UART_LSR_DR) && max_count--); | ||
535 | tty_flip_buffer_push(tty); | ||
536 | } | ||
537 | |||
538 | static void transmit_chars(struct uart_hsu_port *up) | ||
539 | { | ||
540 | struct circ_buf *xmit = &up->port.state->xmit; | ||
541 | int count; | ||
542 | |||
543 | if (up->port.x_char) { | ||
544 | serial_out(up, UART_TX, up->port.x_char); | ||
545 | up->port.icount.tx++; | ||
546 | up->port.x_char = 0; | ||
547 | return; | ||
548 | } | ||
549 | if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { | ||
550 | serial_hsu_stop_tx(&up->port); | ||
551 | return; | ||
552 | } | ||
553 | |||
554 | #ifndef MFD_HSU_A0_STEPPING | ||
555 | count = up->port.fifosize / 2; | ||
556 | #else | ||
557 | /* | ||
558 | * A0 only supports fully empty IRQ, and the first char written | ||
559 | * into it won't clear the EMPT bit, so we may need be cautious | ||
560 | * by useing a shorter buffer | ||
561 | */ | ||
562 | count = up->port.fifosize - 4; | ||
563 | #endif | ||
564 | do { | ||
565 | serial_out(up, UART_TX, xmit->buf[xmit->tail]); | ||
566 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | ||
567 | |||
568 | up->port.icount.tx++; | ||
569 | if (uart_circ_empty(xmit)) | ||
570 | break; | ||
571 | } while (--count > 0); | ||
572 | |||
573 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | ||
574 | uart_write_wakeup(&up->port); | ||
575 | |||
576 | if (uart_circ_empty(xmit)) | ||
577 | serial_hsu_stop_tx(&up->port); | ||
578 | } | ||
579 | |||
580 | static inline void check_modem_status(struct uart_hsu_port *up) | ||
581 | { | ||
582 | int status; | ||
583 | |||
584 | status = serial_in(up, UART_MSR); | ||
585 | |||
586 | if ((status & UART_MSR_ANY_DELTA) == 0) | ||
587 | return; | ||
588 | |||
589 | if (status & UART_MSR_TERI) | ||
590 | up->port.icount.rng++; | ||
591 | if (status & UART_MSR_DDSR) | ||
592 | up->port.icount.dsr++; | ||
593 | /* We may only get DDCD when HW init and reset */ | ||
594 | if (status & UART_MSR_DDCD) | ||
595 | uart_handle_dcd_change(&up->port, status & UART_MSR_DCD); | ||
596 | /* Will start/stop_tx accordingly */ | ||
597 | if (status & UART_MSR_DCTS) | ||
598 | uart_handle_cts_change(&up->port, status & UART_MSR_CTS); | ||
599 | |||
600 | wake_up_interruptible(&up->port.state->port.delta_msr_wait); | ||
601 | } | ||
602 | |||
603 | /* | ||
604 | * This handles the interrupt from one port. | ||
605 | */ | ||
606 | static irqreturn_t port_irq(int irq, void *dev_id) | ||
607 | { | ||
608 | struct uart_hsu_port *up = dev_id; | ||
609 | unsigned int iir, lsr; | ||
610 | unsigned long flags; | ||
611 | |||
612 | if (unlikely(!up->running)) | ||
613 | return IRQ_NONE; | ||
614 | |||
615 | spin_lock_irqsave(&up->port.lock, flags); | ||
616 | if (up->use_dma) { | ||
617 | lsr = serial_in(up, UART_LSR); | ||
618 | if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE | | ||
619 | UART_LSR_FE | UART_LSR_OE))) | ||
620 | dev_warn(up->dev, | ||
621 | "Got lsr irq while using DMA, lsr = 0x%2x\n", | ||
622 | lsr); | ||
623 | check_modem_status(up); | ||
624 | spin_unlock_irqrestore(&up->port.lock, flags); | ||
625 | return IRQ_HANDLED; | ||
626 | } | ||
627 | |||
628 | iir = serial_in(up, UART_IIR); | ||
629 | if (iir & UART_IIR_NO_INT) { | ||
630 | spin_unlock_irqrestore(&up->port.lock, flags); | ||
631 | return IRQ_NONE; | ||
632 | } | ||
633 | |||
634 | lsr = serial_in(up, UART_LSR); | ||
635 | if (lsr & UART_LSR_DR) | ||
636 | receive_chars(up, &lsr); | ||
637 | check_modem_status(up); | ||
638 | |||
639 | /* lsr will be renewed during the receive_chars */ | ||
640 | if (lsr & UART_LSR_THRE) | ||
641 | transmit_chars(up); | ||
642 | |||
643 | spin_unlock_irqrestore(&up->port.lock, flags); | ||
644 | return IRQ_HANDLED; | ||
645 | } | ||
646 | |||
647 | static inline void dma_chan_irq(struct hsu_dma_chan *chan) | ||
648 | { | ||
649 | struct uart_hsu_port *up = chan->uport; | ||
650 | unsigned long flags; | ||
651 | u32 int_sts; | ||
652 | |||
653 | spin_lock_irqsave(&up->port.lock, flags); | ||
654 | |||
655 | if (!up->use_dma || !up->running) | ||
656 | goto exit; | ||
657 | |||
658 | /* | ||
659 | * No matter what situation, need read clear the IRQ status | ||
660 | * There is a bug, see Errata 5, HSD 2900918 | ||
661 | */ | ||
662 | int_sts = chan_readl(chan, HSU_CH_SR); | ||
663 | |||
664 | /* Rx channel */ | ||
665 | if (chan->dirt == DMA_FROM_DEVICE) | ||
666 | hsu_dma_rx(up, int_sts); | ||
667 | |||
668 | /* Tx channel */ | ||
669 | if (chan->dirt == DMA_TO_DEVICE) { | ||
670 | chan_writel(chan, HSU_CH_CR, 0x0); | ||
671 | up->dma_tx_on = 0; | ||
672 | hsu_dma_tx(up); | ||
673 | } | ||
674 | |||
675 | exit: | ||
676 | spin_unlock_irqrestore(&up->port.lock, flags); | ||
677 | return; | ||
678 | } | ||
679 | |||
680 | static irqreturn_t dma_irq(int irq, void *dev_id) | ||
681 | { | ||
682 | struct hsu_port *hsu = dev_id; | ||
683 | u32 int_sts, i; | ||
684 | |||
685 | int_sts = mfd_readl(hsu, HSU_GBL_DMAISR); | ||
686 | |||
687 | /* Currently we only have 6 channels may be used */ | ||
688 | for (i = 0; i < 6; i++) { | ||
689 | if (int_sts & 0x1) | ||
690 | dma_chan_irq(&hsu->chans[i]); | ||
691 | int_sts >>= 1; | ||
692 | } | ||
693 | |||
694 | return IRQ_HANDLED; | ||
695 | } | ||
696 | |||
697 | static unsigned int serial_hsu_tx_empty(struct uart_port *port) | ||
698 | { | ||
699 | struct uart_hsu_port *up = | ||
700 | container_of(port, struct uart_hsu_port, port); | ||
701 | unsigned long flags; | ||
702 | unsigned int ret; | ||
703 | |||
704 | spin_lock_irqsave(&up->port.lock, flags); | ||
705 | ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; | ||
706 | spin_unlock_irqrestore(&up->port.lock, flags); | ||
707 | |||
708 | return ret; | ||
709 | } | ||
710 | |||
711 | static unsigned int serial_hsu_get_mctrl(struct uart_port *port) | ||
712 | { | ||
713 | struct uart_hsu_port *up = | ||
714 | container_of(port, struct uart_hsu_port, port); | ||
715 | unsigned char status; | ||
716 | unsigned int ret; | ||
717 | |||
718 | status = serial_in(up, UART_MSR); | ||
719 | |||
720 | ret = 0; | ||
721 | if (status & UART_MSR_DCD) | ||
722 | ret |= TIOCM_CAR; | ||
723 | if (status & UART_MSR_RI) | ||
724 | ret |= TIOCM_RNG; | ||
725 | if (status & UART_MSR_DSR) | ||
726 | ret |= TIOCM_DSR; | ||
727 | if (status & UART_MSR_CTS) | ||
728 | ret |= TIOCM_CTS; | ||
729 | return ret; | ||
730 | } | ||
731 | |||
732 | static void serial_hsu_set_mctrl(struct uart_port *port, unsigned int mctrl) | ||
733 | { | ||
734 | struct uart_hsu_port *up = | ||
735 | container_of(port, struct uart_hsu_port, port); | ||
736 | unsigned char mcr = 0; | ||
737 | |||
738 | if (mctrl & TIOCM_RTS) | ||
739 | mcr |= UART_MCR_RTS; | ||
740 | if (mctrl & TIOCM_DTR) | ||
741 | mcr |= UART_MCR_DTR; | ||
742 | if (mctrl & TIOCM_OUT1) | ||
743 | mcr |= UART_MCR_OUT1; | ||
744 | if (mctrl & TIOCM_OUT2) | ||
745 | mcr |= UART_MCR_OUT2; | ||
746 | if (mctrl & TIOCM_LOOP) | ||
747 | mcr |= UART_MCR_LOOP; | ||
748 | |||
749 | mcr |= up->mcr; | ||
750 | |||
751 | serial_out(up, UART_MCR, mcr); | ||
752 | } | ||
753 | |||
754 | static void serial_hsu_break_ctl(struct uart_port *port, int break_state) | ||
755 | { | ||
756 | struct uart_hsu_port *up = | ||
757 | container_of(port, struct uart_hsu_port, port); | ||
758 | unsigned long flags; | ||
759 | |||
760 | spin_lock_irqsave(&up->port.lock, flags); | ||
761 | if (break_state == -1) | ||
762 | up->lcr |= UART_LCR_SBC; | ||
763 | else | ||
764 | up->lcr &= ~UART_LCR_SBC; | ||
765 | serial_out(up, UART_LCR, up->lcr); | ||
766 | spin_unlock_irqrestore(&up->port.lock, flags); | ||
767 | } | ||
768 | |||
769 | /* | ||
770 | * What special to do: | ||
771 | * 1. chose the 64B fifo mode | ||
772 | * 2. make sure not to select half empty mode for A0 stepping | ||
773 | * 3. start dma or pio depends on configuration | ||
774 | * 4. we only allocate dma memory when needed | ||
775 | */ | ||
776 | static int serial_hsu_startup(struct uart_port *port) | ||
777 | { | ||
778 | struct uart_hsu_port *up = | ||
779 | container_of(port, struct uart_hsu_port, port); | ||
780 | unsigned long flags; | ||
781 | |||
782 | /* | ||
783 | * Clear the FIFO buffers and disable them. | ||
784 | * (they will be reenabled in set_termios()) | ||
785 | */ | ||
786 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); | ||
787 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | | ||
788 | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); | ||
789 | serial_out(up, UART_FCR, 0); | ||
790 | |||
791 | /* Clear the interrupt registers. */ | ||
792 | (void) serial_in(up, UART_LSR); | ||
793 | (void) serial_in(up, UART_RX); | ||
794 | (void) serial_in(up, UART_IIR); | ||
795 | (void) serial_in(up, UART_MSR); | ||
796 | |||
797 | /* Now, initialize the UART, default is 8n1 */ | ||
798 | serial_out(up, UART_LCR, UART_LCR_WLEN8); | ||
799 | |||
800 | spin_lock_irqsave(&up->port.lock, flags); | ||
801 | |||
802 | up->port.mctrl |= TIOCM_OUT2; | ||
803 | serial_hsu_set_mctrl(&up->port, up->port.mctrl); | ||
804 | |||
805 | /* | ||
806 | * Finally, enable interrupts. Note: Modem status interrupts | ||
807 | * are set via set_termios(), which will be occurring imminently | ||
808 | * anyway, so we don't enable them here. | ||
809 | */ | ||
810 | if (!up->use_dma) | ||
811 | up->ier = UART_IER_RLSI | UART_IER_RDI | UART_IER_RTOIE; | ||
812 | else | ||
813 | up->ier = 0; | ||
814 | serial_out(up, UART_IER, up->ier); | ||
815 | |||
816 | spin_unlock_irqrestore(&up->port.lock, flags); | ||
817 | |||
818 | /* DMA init */ | ||
819 | if (up->use_dma) { | ||
820 | struct hsu_dma_buffer *dbuf; | ||
821 | struct circ_buf *xmit = &port->state->xmit; | ||
822 | |||
823 | up->dma_tx_on = 0; | ||
824 | |||
825 | /* First allocate the RX buffer */ | ||
826 | dbuf = &up->rxbuf; | ||
827 | dbuf->buf = kzalloc(HSU_DMA_BUF_SIZE, GFP_KERNEL); | ||
828 | if (!dbuf->buf) { | ||
829 | up->use_dma = 0; | ||
830 | goto exit; | ||
831 | } | ||
832 | dbuf->dma_addr = dma_map_single(port->dev, | ||
833 | dbuf->buf, | ||
834 | HSU_DMA_BUF_SIZE, | ||
835 | DMA_FROM_DEVICE); | ||
836 | dbuf->dma_size = HSU_DMA_BUF_SIZE; | ||
837 | |||
838 | /* Start the RX channel right now */ | ||
839 | hsu_dma_start_rx_chan(up->rxc, dbuf); | ||
840 | |||
841 | /* Next init the TX DMA */ | ||
842 | dbuf = &up->txbuf; | ||
843 | dbuf->buf = xmit->buf; | ||
844 | dbuf->dma_addr = dma_map_single(port->dev, | ||
845 | dbuf->buf, | ||
846 | UART_XMIT_SIZE, | ||
847 | DMA_TO_DEVICE); | ||
848 | dbuf->dma_size = UART_XMIT_SIZE; | ||
849 | |||
850 | /* This should not be changed all around */ | ||
851 | chan_writel(up->txc, HSU_CH_BSR, 32); | ||
852 | chan_writel(up->txc, HSU_CH_MOTSR, 4); | ||
853 | dbuf->ofs = 0; | ||
854 | } | ||
855 | |||
856 | exit: | ||
857 | /* And clear the interrupt registers again for luck. */ | ||
858 | (void) serial_in(up, UART_LSR); | ||
859 | (void) serial_in(up, UART_RX); | ||
860 | (void) serial_in(up, UART_IIR); | ||
861 | (void) serial_in(up, UART_MSR); | ||
862 | |||
863 | up->running = 1; | ||
864 | return 0; | ||
865 | } | ||
866 | |||
867 | static void serial_hsu_shutdown(struct uart_port *port) | ||
868 | { | ||
869 | struct uart_hsu_port *up = | ||
870 | container_of(port, struct uart_hsu_port, port); | ||
871 | unsigned long flags; | ||
872 | |||
873 | del_timer_sync(&up->rxc->rx_timer); | ||
874 | |||
875 | /* Disable interrupts from this port */ | ||
876 | up->ier = 0; | ||
877 | serial_out(up, UART_IER, 0); | ||
878 | up->running = 0; | ||
879 | |||
880 | spin_lock_irqsave(&up->port.lock, flags); | ||
881 | up->port.mctrl &= ~TIOCM_OUT2; | ||
882 | serial_hsu_set_mctrl(&up->port, up->port.mctrl); | ||
883 | spin_unlock_irqrestore(&up->port.lock, flags); | ||
884 | |||
885 | /* Disable break condition and FIFOs */ | ||
886 | serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC); | ||
887 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | | ||
888 | UART_FCR_CLEAR_RCVR | | ||
889 | UART_FCR_CLEAR_XMIT); | ||
890 | serial_out(up, UART_FCR, 0); | ||
891 | } | ||
892 | |||
893 | static void | ||
894 | serial_hsu_set_termios(struct uart_port *port, struct ktermios *termios, | ||
895 | struct ktermios *old) | ||
896 | { | ||
897 | struct uart_hsu_port *up = | ||
898 | container_of(port, struct uart_hsu_port, port); | ||
899 | struct tty_struct *tty = port->state->port.tty; | ||
900 | unsigned char cval, fcr = 0; | ||
901 | unsigned long flags; | ||
902 | unsigned int baud, quot; | ||
903 | u32 ps, mul; | ||
904 | |||
905 | switch (termios->c_cflag & CSIZE) { | ||
906 | case CS5: | ||
907 | cval = UART_LCR_WLEN5; | ||
908 | break; | ||
909 | case CS6: | ||
910 | cval = UART_LCR_WLEN6; | ||
911 | break; | ||
912 | case CS7: | ||
913 | cval = UART_LCR_WLEN7; | ||
914 | break; | ||
915 | default: | ||
916 | case CS8: | ||
917 | cval = UART_LCR_WLEN8; | ||
918 | break; | ||
919 | } | ||
920 | |||
921 | /* CMSPAR isn't supported by this driver */ | ||
922 | if (tty) | ||
923 | tty->termios->c_cflag &= ~CMSPAR; | ||
924 | |||
925 | if (termios->c_cflag & CSTOPB) | ||
926 | cval |= UART_LCR_STOP; | ||
927 | if (termios->c_cflag & PARENB) | ||
928 | cval |= UART_LCR_PARITY; | ||
929 | if (!(termios->c_cflag & PARODD)) | ||
930 | cval |= UART_LCR_EPAR; | ||
931 | |||
932 | /* | ||
933 | * The base clk is 50Mhz, and the baud rate come from: | ||
934 | * baud = 50M * MUL / (DIV * PS * DLAB) | ||
935 | * | ||
936 | * For those basic low baud rate we can get the direct | ||
937 | * scalar from 2746800, like 115200 = 2746800/24. For those | ||
938 | * higher baud rate, we handle them case by case, mainly by | ||
939 | * adjusting the MUL/PS registers, and DIV register is kept | ||
940 | * as default value 0x3d09 to make things simple | ||
941 | */ | ||
942 | baud = uart_get_baud_rate(port, termios, old, 0, 4000000); | ||
943 | |||
944 | quot = 1; | ||
945 | ps = 0x10; | ||
946 | mul = 0x3600; | ||
947 | switch (baud) { | ||
948 | case 3500000: | ||
949 | mul = 0x3345; | ||
950 | ps = 0xC; | ||
951 | break; | ||
952 | case 1843200: | ||
953 | mul = 0x2400; | ||
954 | break; | ||
955 | case 3000000: | ||
956 | case 2500000: | ||
957 | case 2000000: | ||
958 | case 1500000: | ||
959 | case 1000000: | ||
960 | case 500000: | ||
961 | /* mul/ps/quot = 0x9C4/0x10/0x1 will make a 500000 bps */ | ||
962 | mul = baud / 500000 * 0x9C4; | ||
963 | break; | ||
964 | default: | ||
965 | /* Use uart_get_divisor to get quot for other baud rates */ | ||
966 | quot = 0; | ||
967 | } | ||
968 | |||
969 | if (!quot) | ||
970 | quot = uart_get_divisor(port, baud); | ||
971 | |||
972 | if ((up->port.uartclk / quot) < (2400 * 16)) | ||
973 | fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_1B; | ||
974 | else if ((up->port.uartclk / quot) < (230400 * 16)) | ||
975 | fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_16B; | ||
976 | else | ||
977 | fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_32B; | ||
978 | |||
979 | fcr |= UART_FCR_HSU_64B_FIFO; | ||
980 | #ifdef MFD_HSU_A0_STEPPING | ||
981 | /* A0 doesn't support half empty IRQ */ | ||
982 | fcr |= UART_FCR_FULL_EMPT_TXI; | ||
983 | #endif | ||
984 | |||
985 | /* | ||
986 | * Ok, we're now changing the port state. Do it with | ||
987 | * interrupts disabled. | ||
988 | */ | ||
989 | spin_lock_irqsave(&up->port.lock, flags); | ||
990 | |||
991 | /* Update the per-port timeout */ | ||
992 | uart_update_timeout(port, termios->c_cflag, baud); | ||
993 | |||
994 | up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; | ||
995 | if (termios->c_iflag & INPCK) | ||
996 | up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; | ||
997 | if (termios->c_iflag & (BRKINT | PARMRK)) | ||
998 | up->port.read_status_mask |= UART_LSR_BI; | ||
999 | |||
1000 | /* Characters to ignore */ | ||
1001 | up->port.ignore_status_mask = 0; | ||
1002 | if (termios->c_iflag & IGNPAR) | ||
1003 | up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; | ||
1004 | if (termios->c_iflag & IGNBRK) { | ||
1005 | up->port.ignore_status_mask |= UART_LSR_BI; | ||
1006 | /* | ||
1007 | * If we're ignoring parity and break indicators, | ||
1008 | * ignore overruns too (for real raw support). | ||
1009 | */ | ||
1010 | if (termios->c_iflag & IGNPAR) | ||
1011 | up->port.ignore_status_mask |= UART_LSR_OE; | ||
1012 | } | ||
1013 | |||
1014 | /* Ignore all characters if CREAD is not set */ | ||
1015 | if ((termios->c_cflag & CREAD) == 0) | ||
1016 | up->port.ignore_status_mask |= UART_LSR_DR; | ||
1017 | |||
1018 | /* | ||
1019 | * CTS flow control flag and modem status interrupts, disable | ||
1020 | * MSI by default | ||
1021 | */ | ||
1022 | up->ier &= ~UART_IER_MSI; | ||
1023 | if (UART_ENABLE_MS(&up->port, termios->c_cflag)) | ||
1024 | up->ier |= UART_IER_MSI; | ||
1025 | |||
1026 | serial_out(up, UART_IER, up->ier); | ||
1027 | |||
1028 | if (termios->c_cflag & CRTSCTS) | ||
1029 | up->mcr |= UART_MCR_AFE | UART_MCR_RTS; | ||
1030 | else | ||
1031 | up->mcr &= ~UART_MCR_AFE; | ||
1032 | |||
1033 | serial_out(up, UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */ | ||
1034 | serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */ | ||
1035 | serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */ | ||
1036 | serial_out(up, UART_LCR, cval); /* reset DLAB */ | ||
1037 | serial_out(up, UART_MUL, mul); /* set MUL */ | ||
1038 | serial_out(up, UART_PS, ps); /* set PS */ | ||
1039 | up->lcr = cval; /* Save LCR */ | ||
1040 | serial_hsu_set_mctrl(&up->port, up->port.mctrl); | ||
1041 | serial_out(up, UART_FCR, fcr); | ||
1042 | spin_unlock_irqrestore(&up->port.lock, flags); | ||
1043 | } | ||
1044 | |||
1045 | static void | ||
1046 | serial_hsu_pm(struct uart_port *port, unsigned int state, | ||
1047 | unsigned int oldstate) | ||
1048 | { | ||
1049 | } | ||
1050 | |||
1051 | static void serial_hsu_release_port(struct uart_port *port) | ||
1052 | { | ||
1053 | } | ||
1054 | |||
1055 | static int serial_hsu_request_port(struct uart_port *port) | ||
1056 | { | ||
1057 | return 0; | ||
1058 | } | ||
1059 | |||
1060 | static void serial_hsu_config_port(struct uart_port *port, int flags) | ||
1061 | { | ||
1062 | struct uart_hsu_port *up = | ||
1063 | container_of(port, struct uart_hsu_port, port); | ||
1064 | up->port.type = PORT_MFD; | ||
1065 | } | ||
1066 | |||
1067 | static int | ||
1068 | serial_hsu_verify_port(struct uart_port *port, struct serial_struct *ser) | ||
1069 | { | ||
1070 | /* We don't want the core code to modify any port params */ | ||
1071 | return -EINVAL; | ||
1072 | } | ||
1073 | |||
1074 | static const char * | ||
1075 | serial_hsu_type(struct uart_port *port) | ||
1076 | { | ||
1077 | struct uart_hsu_port *up = | ||
1078 | container_of(port, struct uart_hsu_port, port); | ||
1079 | return up->name; | ||
1080 | } | ||
1081 | |||
1082 | /* Mainly for uart console use */ | ||
1083 | static struct uart_hsu_port *serial_hsu_ports[3]; | ||
1084 | static struct uart_driver serial_hsu_reg; | ||
1085 | |||
1086 | #ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE | ||
1087 | |||
1088 | #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) | ||
1089 | |||
1090 | /* Wait for transmitter & holding register to empty */ | ||
1091 | static inline void wait_for_xmitr(struct uart_hsu_port *up) | ||
1092 | { | ||
1093 | unsigned int status, tmout = 1000; | ||
1094 | |||
1095 | /* Wait up to 1ms for the character to be sent. */ | ||
1096 | do { | ||
1097 | status = serial_in(up, UART_LSR); | ||
1098 | |||
1099 | if (status & UART_LSR_BI) | ||
1100 | up->lsr_break_flag = UART_LSR_BI; | ||
1101 | |||
1102 | if (--tmout == 0) | ||
1103 | break; | ||
1104 | udelay(1); | ||
1105 | } while (!(status & BOTH_EMPTY)); | ||
1106 | |||
1107 | /* Wait up to 1s for flow control if necessary */ | ||
1108 | if (up->port.flags & UPF_CONS_FLOW) { | ||
1109 | tmout = 1000000; | ||
1110 | while (--tmout && | ||
1111 | ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0)) | ||
1112 | udelay(1); | ||
1113 | } | ||
1114 | } | ||
1115 | |||
1116 | static void serial_hsu_console_putchar(struct uart_port *port, int ch) | ||
1117 | { | ||
1118 | struct uart_hsu_port *up = | ||
1119 | container_of(port, struct uart_hsu_port, port); | ||
1120 | |||
1121 | wait_for_xmitr(up); | ||
1122 | serial_out(up, UART_TX, ch); | ||
1123 | } | ||
1124 | |||
1125 | /* | ||
1126 | * Print a string to the serial port trying not to disturb | ||
1127 | * any possible real use of the port... | ||
1128 | * | ||
1129 | * The console_lock must be held when we get here. | ||
1130 | */ | ||
1131 | static void | ||
1132 | serial_hsu_console_write(struct console *co, const char *s, unsigned int count) | ||
1133 | { | ||
1134 | struct uart_hsu_port *up = serial_hsu_ports[co->index]; | ||
1135 | unsigned long flags; | ||
1136 | unsigned int ier; | ||
1137 | int locked = 1; | ||
1138 | |||
1139 | local_irq_save(flags); | ||
1140 | if (up->port.sysrq) | ||
1141 | locked = 0; | ||
1142 | else if (oops_in_progress) { | ||
1143 | locked = spin_trylock(&up->port.lock); | ||
1144 | } else | ||
1145 | spin_lock(&up->port.lock); | ||
1146 | |||
1147 | /* First save the IER then disable the interrupts */ | ||
1148 | ier = serial_in(up, UART_IER); | ||
1149 | serial_out(up, UART_IER, 0); | ||
1150 | |||
1151 | uart_console_write(&up->port, s, count, serial_hsu_console_putchar); | ||
1152 | |||
1153 | /* | ||
1154 | * Finally, wait for transmitter to become empty | ||
1155 | * and restore the IER | ||
1156 | */ | ||
1157 | wait_for_xmitr(up); | ||
1158 | serial_out(up, UART_IER, ier); | ||
1159 | |||
1160 | if (locked) | ||
1161 | spin_unlock(&up->port.lock); | ||
1162 | local_irq_restore(flags); | ||
1163 | } | ||
1164 | |||
1165 | static struct console serial_hsu_console; | ||
1166 | |||
1167 | static int __init | ||
1168 | serial_hsu_console_setup(struct console *co, char *options) | ||
1169 | { | ||
1170 | struct uart_hsu_port *up; | ||
1171 | int baud = 115200; | ||
1172 | int bits = 8; | ||
1173 | int parity = 'n'; | ||
1174 | int flow = 'n'; | ||
1175 | int ret; | ||
1176 | |||
1177 | if (co->index == -1 || co->index >= serial_hsu_reg.nr) | ||
1178 | co->index = 0; | ||
1179 | up = serial_hsu_ports[co->index]; | ||
1180 | if (!up) | ||
1181 | return -ENODEV; | ||
1182 | |||
1183 | if (options) | ||
1184 | uart_parse_options(options, &baud, &parity, &bits, &flow); | ||
1185 | |||
1186 | ret = uart_set_options(&up->port, co, baud, parity, bits, flow); | ||
1187 | |||
1188 | return ret; | ||
1189 | } | ||
1190 | |||
1191 | static struct console serial_hsu_console = { | ||
1192 | .name = "ttyMFD", | ||
1193 | .write = serial_hsu_console_write, | ||
1194 | .device = uart_console_device, | ||
1195 | .setup = serial_hsu_console_setup, | ||
1196 | .flags = CON_PRINTBUFFER, | ||
1197 | .index = 2, | ||
1198 | .data = &serial_hsu_reg, | ||
1199 | }; | ||
1200 | #endif | ||
1201 | |||
1202 | struct uart_ops serial_hsu_pops = { | ||
1203 | .tx_empty = serial_hsu_tx_empty, | ||
1204 | .set_mctrl = serial_hsu_set_mctrl, | ||
1205 | .get_mctrl = serial_hsu_get_mctrl, | ||
1206 | .stop_tx = serial_hsu_stop_tx, | ||
1207 | .start_tx = serial_hsu_start_tx, | ||
1208 | .stop_rx = serial_hsu_stop_rx, | ||
1209 | .enable_ms = serial_hsu_enable_ms, | ||
1210 | .break_ctl = serial_hsu_break_ctl, | ||
1211 | .startup = serial_hsu_startup, | ||
1212 | .shutdown = serial_hsu_shutdown, | ||
1213 | .set_termios = serial_hsu_set_termios, | ||
1214 | .pm = serial_hsu_pm, | ||
1215 | .type = serial_hsu_type, | ||
1216 | .release_port = serial_hsu_release_port, | ||
1217 | .request_port = serial_hsu_request_port, | ||
1218 | .config_port = serial_hsu_config_port, | ||
1219 | .verify_port = serial_hsu_verify_port, | ||
1220 | }; | ||
1221 | |||
1222 | static struct uart_driver serial_hsu_reg = { | ||
1223 | .owner = THIS_MODULE, | ||
1224 | .driver_name = "MFD serial", | ||
1225 | .dev_name = "ttyMFD", | ||
1226 | .major = TTY_MAJOR, | ||
1227 | .minor = 128, | ||
1228 | .nr = 3, | ||
1229 | }; | ||
1230 | |||
1231 | #ifdef CONFIG_PM | ||
1232 | static int serial_hsu_suspend(struct pci_dev *pdev, pm_message_t state) | ||
1233 | { | ||
1234 | void *priv = pci_get_drvdata(pdev); | ||
1235 | struct uart_hsu_port *up; | ||
1236 | |||
1237 | /* Make sure this is not the internal dma controller */ | ||
1238 | if (priv && (pdev->device != 0x081E)) { | ||
1239 | up = priv; | ||
1240 | uart_suspend_port(&serial_hsu_reg, &up->port); | ||
1241 | } | ||
1242 | |||
1243 | pci_save_state(pdev); | ||
1244 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | ||
1245 | return 0; | ||
1246 | } | ||
1247 | |||
1248 | static int serial_hsu_resume(struct pci_dev *pdev) | ||
1249 | { | ||
1250 | void *priv = pci_get_drvdata(pdev); | ||
1251 | struct uart_hsu_port *up; | ||
1252 | int ret; | ||
1253 | |||
1254 | pci_set_power_state(pdev, PCI_D0); | ||
1255 | pci_restore_state(pdev); | ||
1256 | |||
1257 | ret = pci_enable_device(pdev); | ||
1258 | if (ret) | ||
1259 | dev_warn(&pdev->dev, | ||
1260 | "HSU: can't re-enable device, try to continue\n"); | ||
1261 | |||
1262 | if (priv && (pdev->device != 0x081E)) { | ||
1263 | up = priv; | ||
1264 | uart_resume_port(&serial_hsu_reg, &up->port); | ||
1265 | } | ||
1266 | return 0; | ||
1267 | } | ||
1268 | #else | ||
1269 | #define serial_hsu_suspend NULL | ||
1270 | #define serial_hsu_resume NULL | ||
1271 | #endif | ||
1272 | |||
1273 | /* temp global pointer before we settle down on using one or four PCI dev */ | ||
1274 | static struct hsu_port *phsu; | ||
1275 | |||
1276 | static int serial_hsu_probe(struct pci_dev *pdev, | ||
1277 | const struct pci_device_id *ent) | ||
1278 | { | ||
1279 | struct uart_hsu_port *uport; | ||
1280 | int index, ret; | ||
1281 | |||
1282 | printk(KERN_INFO "HSU: found PCI Serial controller(ID: %04x:%04x)\n", | ||
1283 | pdev->vendor, pdev->device); | ||
1284 | |||
1285 | switch (pdev->device) { | ||
1286 | case 0x081B: | ||
1287 | index = 0; | ||
1288 | break; | ||
1289 | case 0x081C: | ||
1290 | index = 1; | ||
1291 | break; | ||
1292 | case 0x081D: | ||
1293 | index = 2; | ||
1294 | break; | ||
1295 | case 0x081E: | ||
1296 | /* internal DMA controller */ | ||
1297 | index = 3; | ||
1298 | break; | ||
1299 | default: | ||
1300 | dev_err(&pdev->dev, "HSU: out of index!"); | ||
1301 | return -ENODEV; | ||
1302 | } | ||
1303 | |||
1304 | ret = pci_enable_device(pdev); | ||
1305 | if (ret) | ||
1306 | return ret; | ||
1307 | |||
1308 | if (index == 3) { | ||
1309 | /* DMA controller */ | ||
1310 | ret = request_irq(pdev->irq, dma_irq, 0, "hsu_dma", phsu); | ||
1311 | if (ret) { | ||
1312 | dev_err(&pdev->dev, "can not get IRQ\n"); | ||
1313 | goto err_disable; | ||
1314 | } | ||
1315 | pci_set_drvdata(pdev, phsu); | ||
1316 | } else { | ||
1317 | /* UART port 0~2 */ | ||
1318 | uport = &phsu->port[index]; | ||
1319 | uport->port.irq = pdev->irq; | ||
1320 | uport->port.dev = &pdev->dev; | ||
1321 | uport->dev = &pdev->dev; | ||
1322 | |||
1323 | ret = request_irq(pdev->irq, port_irq, 0, uport->name, uport); | ||
1324 | if (ret) { | ||
1325 | dev_err(&pdev->dev, "can not get IRQ\n"); | ||
1326 | goto err_disable; | ||
1327 | } | ||
1328 | uart_add_one_port(&serial_hsu_reg, &uport->port); | ||
1329 | |||
1330 | #ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE | ||
1331 | if (index == 2) { | ||
1332 | register_console(&serial_hsu_console); | ||
1333 | uport->port.cons = &serial_hsu_console; | ||
1334 | } | ||
1335 | #endif | ||
1336 | pci_set_drvdata(pdev, uport); | ||
1337 | } | ||
1338 | |||
1339 | return 0; | ||
1340 | |||
1341 | err_disable: | ||
1342 | pci_disable_device(pdev); | ||
1343 | return ret; | ||
1344 | } | ||
1345 | |||
1346 | static void hsu_dma_rx_timeout(unsigned long data) | ||
1347 | { | ||
1348 | struct hsu_dma_chan *chan = (void *)data; | ||
1349 | struct uart_hsu_port *up = chan->uport; | ||
1350 | struct hsu_dma_buffer *dbuf = &up->rxbuf; | ||
1351 | int count = 0; | ||
1352 | unsigned long flags; | ||
1353 | |||
1354 | spin_lock_irqsave(&up->port.lock, flags); | ||
1355 | |||
1356 | count = chan_readl(chan, HSU_CH_D0SAR) - dbuf->dma_addr; | ||
1357 | |||
1358 | if (!count) { | ||
1359 | mod_timer(&chan->rx_timer, jiffies + HSU_DMA_TIMEOUT_CHECK_FREQ); | ||
1360 | goto exit; | ||
1361 | } | ||
1362 | |||
1363 | hsu_dma_rx(up, 0); | ||
1364 | exit: | ||
1365 | spin_unlock_irqrestore(&up->port.lock, flags); | ||
1366 | } | ||
1367 | |||
1368 | static void hsu_global_init(void) | ||
1369 | { | ||
1370 | struct hsu_port *hsu; | ||
1371 | struct uart_hsu_port *uport; | ||
1372 | struct hsu_dma_chan *dchan; | ||
1373 | int i, ret; | ||
1374 | |||
1375 | hsu = kzalloc(sizeof(struct hsu_port), GFP_KERNEL); | ||
1376 | if (!hsu) | ||
1377 | return; | ||
1378 | |||
1379 | /* Get basic io resource and map it */ | ||
1380 | hsu->paddr = 0xffa28000; | ||
1381 | hsu->iolen = 0x1000; | ||
1382 | |||
1383 | if (!(request_mem_region(hsu->paddr, hsu->iolen, "HSU global"))) | ||
1384 | pr_warning("HSU: error in request mem region\n"); | ||
1385 | |||
1386 | hsu->reg = ioremap_nocache((unsigned long)hsu->paddr, hsu->iolen); | ||
1387 | if (!hsu->reg) { | ||
1388 | pr_err("HSU: error in ioremap\n"); | ||
1389 | ret = -ENOMEM; | ||
1390 | goto err_free_region; | ||
1391 | } | ||
1392 | |||
1393 | /* Initialise the 3 UART ports */ | ||
1394 | uport = hsu->port; | ||
1395 | for (i = 0; i < 3; i++) { | ||
1396 | uport->port.type = PORT_MFD; | ||
1397 | uport->port.iotype = UPIO_MEM; | ||
1398 | uport->port.mapbase = (resource_size_t)hsu->paddr | ||
1399 | + HSU_PORT_REG_OFFSET | ||
1400 | + i * HSU_PORT_REG_LENGTH; | ||
1401 | uport->port.membase = hsu->reg + HSU_PORT_REG_OFFSET | ||
1402 | + i * HSU_PORT_REG_LENGTH; | ||
1403 | |||
1404 | sprintf(uport->name, "hsu_port%d", i); | ||
1405 | uport->port.fifosize = 64; | ||
1406 | uport->port.ops = &serial_hsu_pops; | ||
1407 | uport->port.line = i; | ||
1408 | uport->port.flags = UPF_IOREMAP; | ||
1409 | /* set the scalable maxim support rate to 2746800 bps */ | ||
1410 | uport->port.uartclk = 115200 * 24 * 16; | ||
1411 | |||
1412 | uport->running = 0; | ||
1413 | uport->txc = &hsu->chans[i * 2]; | ||
1414 | uport->rxc = &hsu->chans[i * 2 + 1]; | ||
1415 | |||
1416 | serial_hsu_ports[i] = uport; | ||
1417 | uport->index = i; | ||
1418 | uport++; | ||
1419 | } | ||
1420 | |||
1421 | /* Initialise 6 dma channels */ | ||
1422 | dchan = hsu->chans; | ||
1423 | for (i = 0; i < 6; i++) { | ||
1424 | dchan->id = i; | ||
1425 | dchan->dirt = (i & 0x1) ? DMA_FROM_DEVICE : DMA_TO_DEVICE; | ||
1426 | dchan->uport = &hsu->port[i/2]; | ||
1427 | dchan->reg = hsu->reg + HSU_DMA_CHANS_REG_OFFSET + | ||
1428 | i * HSU_DMA_CHANS_REG_LENGTH; | ||
1429 | |||
1430 | /* Work around for RX */ | ||
1431 | if (dchan->dirt == DMA_FROM_DEVICE) { | ||
1432 | init_timer(&dchan->rx_timer); | ||
1433 | dchan->rx_timer.function = hsu_dma_rx_timeout; | ||
1434 | dchan->rx_timer.data = (unsigned long)dchan; | ||
1435 | } | ||
1436 | dchan++; | ||
1437 | } | ||
1438 | |||
1439 | phsu = hsu; | ||
1440 | hsu_debugfs_init(hsu); | ||
1441 | return; | ||
1442 | |||
1443 | err_free_region: | ||
1444 | release_mem_region(hsu->paddr, hsu->iolen); | ||
1445 | kfree(hsu); | ||
1446 | return; | ||
1447 | } | ||
1448 | |||
1449 | static void serial_hsu_remove(struct pci_dev *pdev) | ||
1450 | { | ||
1451 | void *priv = pci_get_drvdata(pdev); | ||
1452 | struct uart_hsu_port *up; | ||
1453 | |||
1454 | if (!priv) | ||
1455 | return; | ||
1456 | |||
1457 | /* For port 0/1/2, priv is the address of uart_hsu_port */ | ||
1458 | if (pdev->device != 0x081E) { | ||
1459 | up = priv; | ||
1460 | uart_remove_one_port(&serial_hsu_reg, &up->port); | ||
1461 | } | ||
1462 | |||
1463 | pci_set_drvdata(pdev, NULL); | ||
1464 | free_irq(pdev->irq, priv); | ||
1465 | pci_disable_device(pdev); | ||
1466 | } | ||
1467 | |||
1468 | /* First 3 are UART ports, and the 4th is the DMA */ | ||
1469 | static const struct pci_device_id pci_ids[] __devinitdata = { | ||
1470 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081B) }, | ||
1471 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081C) }, | ||
1472 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081D) }, | ||
1473 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081E) }, | ||
1474 | {}, | ||
1475 | }; | ||
1476 | |||
1477 | static struct pci_driver hsu_pci_driver = { | ||
1478 | .name = "HSU serial", | ||
1479 | .id_table = pci_ids, | ||
1480 | .probe = serial_hsu_probe, | ||
1481 | .remove = __devexit_p(serial_hsu_remove), | ||
1482 | .suspend = serial_hsu_suspend, | ||
1483 | .resume = serial_hsu_resume, | ||
1484 | }; | ||
1485 | |||
1486 | static int __init hsu_pci_init(void) | ||
1487 | { | ||
1488 | int ret; | ||
1489 | |||
1490 | hsu_global_init(); | ||
1491 | |||
1492 | ret = uart_register_driver(&serial_hsu_reg); | ||
1493 | if (ret) | ||
1494 | return ret; | ||
1495 | |||
1496 | return pci_register_driver(&hsu_pci_driver); | ||
1497 | } | ||
1498 | |||
1499 | static void __exit hsu_pci_exit(void) | ||
1500 | { | ||
1501 | pci_unregister_driver(&hsu_pci_driver); | ||
1502 | uart_unregister_driver(&serial_hsu_reg); | ||
1503 | |||
1504 | hsu_debugfs_remove(phsu); | ||
1505 | |||
1506 | kfree(phsu); | ||
1507 | } | ||
1508 | |||
1509 | module_init(hsu_pci_init); | ||
1510 | module_exit(hsu_pci_exit); | ||
1511 | |||
1512 | MODULE_LICENSE("GPL v2"); | ||
1513 | MODULE_ALIAS("platform:medfield-hsu"); | ||