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-rw-r--r--drivers/tty/serial/crisv10.c4573
1 files changed, 4573 insertions, 0 deletions
diff --git a/drivers/tty/serial/crisv10.c b/drivers/tty/serial/crisv10.c
new file mode 100644
index 000000000000..bcc31f2140ac
--- /dev/null
+++ b/drivers/tty/serial/crisv10.c
@@ -0,0 +1,4573 @@
1/*
2 * Serial port driver for the ETRAX 100LX chip
3 *
4 * Copyright (C) 1998-2007 Axis Communications AB
5 *
6 * Many, many authors. Based once upon a time on serial.c for 16x50.
7 *
8 */
9
10static char *serial_version = "$Revision: 1.25 $";
11
12#include <linux/types.h>
13#include <linux/errno.h>
14#include <linux/signal.h>
15#include <linux/sched.h>
16#include <linux/timer.h>
17#include <linux/interrupt.h>
18#include <linux/tty.h>
19#include <linux/tty_flip.h>
20#include <linux/major.h>
21#include <linux/string.h>
22#include <linux/fcntl.h>
23#include <linux/mm.h>
24#include <linux/slab.h>
25#include <linux/init.h>
26#include <linux/kernel.h>
27#include <linux/mutex.h>
28#include <linux/bitops.h>
29#include <linux/seq_file.h>
30#include <linux/delay.h>
31#include <linux/module.h>
32#include <linux/uaccess.h>
33#include <linux/io.h>
34
35#include <asm/irq.h>
36#include <asm/dma.h>
37#include <asm/system.h>
38
39#include <arch/svinto.h>
40
41/* non-arch dependent serial structures are in linux/serial.h */
42#include <linux/serial.h>
43/* while we keep our own stuff (struct e100_serial) in a local .h file */
44#include "crisv10.h"
45#include <asm/fasttimer.h>
46#include <arch/io_interface_mux.h>
47
48#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
49#ifndef CONFIG_ETRAX_FAST_TIMER
50#error "Enable FAST_TIMER to use SERIAL_FAST_TIMER"
51#endif
52#endif
53
54#if defined(CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS) && \
55 (CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS == 0)
56#error "RX_TIMEOUT_TICKS == 0 not allowed, use 1"
57#endif
58
59#if defined(CONFIG_ETRAX_RS485_ON_PA) && defined(CONFIG_ETRAX_RS485_ON_PORT_G)
60#error "Disable either CONFIG_ETRAX_RS485_ON_PA or CONFIG_ETRAX_RS485_ON_PORT_G"
61#endif
62
63/*
64 * All of the compatibilty code so we can compile serial.c against
65 * older kernels is hidden in serial_compat.h
66 */
67#if defined(LOCAL_HEADERS)
68#include "serial_compat.h"
69#endif
70
71struct tty_driver *serial_driver;
72
73/* number of characters left in xmit buffer before we ask for more */
74#define WAKEUP_CHARS 256
75
76//#define SERIAL_DEBUG_INTR
77//#define SERIAL_DEBUG_OPEN
78//#define SERIAL_DEBUG_FLOW
79//#define SERIAL_DEBUG_DATA
80//#define SERIAL_DEBUG_THROTTLE
81//#define SERIAL_DEBUG_IO /* Debug for Extra control and status pins */
82//#define SERIAL_DEBUG_LINE 0 /* What serport we want to debug */
83
84/* Enable this to use serial interrupts to handle when you
85 expect the first received event on the serial port to
86 be an error, break or similar. Used to be able to flash IRMA
87 from eLinux */
88#define SERIAL_HANDLE_EARLY_ERRORS
89
90/* Currently 16 descriptors x 128 bytes = 2048 bytes */
91#define SERIAL_DESCR_BUF_SIZE 256
92
93#define SERIAL_PRESCALE_BASE 3125000 /* 3.125MHz */
94#define DEF_BAUD_BASE SERIAL_PRESCALE_BASE
95
96/* We don't want to load the system with massive fast timer interrupt
97 * on high baudrates so limit it to 250 us (4kHz) */
98#define MIN_FLUSH_TIME_USEC 250
99
100/* Add an x here to log a lot of timer stuff */
101#define TIMERD(x)
102/* Debug details of interrupt handling */
103#define DINTR1(x) /* irq on/off, errors */
104#define DINTR2(x) /* tx and rx */
105/* Debug flip buffer stuff */
106#define DFLIP(x)
107/* Debug flow control and overview of data flow */
108#define DFLOW(x)
109#define DBAUD(x)
110#define DLOG_INT_TRIG(x)
111
112//#define DEBUG_LOG_INCLUDED
113#ifndef DEBUG_LOG_INCLUDED
114#define DEBUG_LOG(line, string, value)
115#else
116struct debug_log_info
117{
118 unsigned long time;
119 unsigned long timer_data;
120// int line;
121 const char *string;
122 int value;
123};
124#define DEBUG_LOG_SIZE 4096
125
126struct debug_log_info debug_log[DEBUG_LOG_SIZE];
127int debug_log_pos = 0;
128
129#define DEBUG_LOG(_line, _string, _value) do { \
130 if ((_line) == SERIAL_DEBUG_LINE) {\
131 debug_log_func(_line, _string, _value); \
132 }\
133}while(0)
134
135void debug_log_func(int line, const char *string, int value)
136{
137 if (debug_log_pos < DEBUG_LOG_SIZE) {
138 debug_log[debug_log_pos].time = jiffies;
139 debug_log[debug_log_pos].timer_data = *R_TIMER_DATA;
140// debug_log[debug_log_pos].line = line;
141 debug_log[debug_log_pos].string = string;
142 debug_log[debug_log_pos].value = value;
143 debug_log_pos++;
144 }
145 /*printk(string, value);*/
146}
147#endif
148
149#ifndef CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS
150/* Default number of timer ticks before flushing rx fifo
151 * When using "little data, low latency applications: use 0
152 * When using "much data applications (PPP)" use ~5
153 */
154#define CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS 5
155#endif
156
157unsigned long timer_data_to_ns(unsigned long timer_data);
158
159static void change_speed(struct e100_serial *info);
160static void rs_throttle(struct tty_struct * tty);
161static void rs_wait_until_sent(struct tty_struct *tty, int timeout);
162static int rs_write(struct tty_struct *tty,
163 const unsigned char *buf, int count);
164#ifdef CONFIG_ETRAX_RS485
165static int e100_write_rs485(struct tty_struct *tty,
166 const unsigned char *buf, int count);
167#endif
168static int get_lsr_info(struct e100_serial *info, unsigned int *value);
169
170
171#define DEF_BAUD 115200 /* 115.2 kbit/s */
172#define STD_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
173#define DEF_RX 0x20 /* or SERIAL_CTRL_W >> 8 */
174/* Default value of tx_ctrl register: has txd(bit 7)=1 (idle) as default */
175#define DEF_TX 0x80 /* or SERIAL_CTRL_B */
176
177/* offsets from R_SERIALx_CTRL */
178
179#define REG_DATA 0
180#define REG_DATA_STATUS32 0 /* this is the 32 bit register R_SERIALx_READ */
181#define REG_TR_DATA 0
182#define REG_STATUS 1
183#define REG_TR_CTRL 1
184#define REG_REC_CTRL 2
185#define REG_BAUD 3
186#define REG_XOFF 4 /* this is a 32 bit register */
187
188/* The bitfields are the same for all serial ports */
189#define SER_RXD_MASK IO_MASK(R_SERIAL0_STATUS, rxd)
190#define SER_DATA_AVAIL_MASK IO_MASK(R_SERIAL0_STATUS, data_avail)
191#define SER_FRAMING_ERR_MASK IO_MASK(R_SERIAL0_STATUS, framing_err)
192#define SER_PAR_ERR_MASK IO_MASK(R_SERIAL0_STATUS, par_err)
193#define SER_OVERRUN_MASK IO_MASK(R_SERIAL0_STATUS, overrun)
194
195#define SER_ERROR_MASK (SER_OVERRUN_MASK | SER_PAR_ERR_MASK | SER_FRAMING_ERR_MASK)
196
197/* Values for info->errorcode */
198#define ERRCODE_SET_BREAK (TTY_BREAK)
199#define ERRCODE_INSERT 0x100
200#define ERRCODE_INSERT_BREAK (ERRCODE_INSERT | TTY_BREAK)
201
202#define FORCE_EOP(info) *R_SET_EOP = 1U << info->iseteop;
203
204/*
205 * General note regarding the use of IO_* macros in this file:
206 *
207 * We will use the bits defined for DMA channel 6 when using various
208 * IO_* macros (e.g. IO_STATE, IO_MASK, IO_EXTRACT) and _assume_ they are
209 * the same for all channels (which of course they are).
210 *
211 * We will also use the bits defined for serial port 0 when writing commands
212 * to the different ports, as these bits too are the same for all ports.
213 */
214
215
216/* Mask for the irqs possibly enabled in R_IRQ_MASK1_RD etc. */
217static const unsigned long e100_ser_int_mask = 0
218#ifdef CONFIG_ETRAX_SERIAL_PORT0
219| IO_MASK(R_IRQ_MASK1_RD, ser0_data) | IO_MASK(R_IRQ_MASK1_RD, ser0_ready)
220#endif
221#ifdef CONFIG_ETRAX_SERIAL_PORT1
222| IO_MASK(R_IRQ_MASK1_RD, ser1_data) | IO_MASK(R_IRQ_MASK1_RD, ser1_ready)
223#endif
224#ifdef CONFIG_ETRAX_SERIAL_PORT2
225| IO_MASK(R_IRQ_MASK1_RD, ser2_data) | IO_MASK(R_IRQ_MASK1_RD, ser2_ready)
226#endif
227#ifdef CONFIG_ETRAX_SERIAL_PORT3
228| IO_MASK(R_IRQ_MASK1_RD, ser3_data) | IO_MASK(R_IRQ_MASK1_RD, ser3_ready)
229#endif
230;
231unsigned long r_alt_ser_baudrate_shadow = 0;
232
233/* this is the data for the four serial ports in the etrax100 */
234/* DMA2(ser2), DMA4(ser3), DMA6(ser0) or DMA8(ser1) */
235/* R_DMA_CHx_CLR_INTR, R_DMA_CHx_FIRST, R_DMA_CHx_CMD */
236
237static struct e100_serial rs_table[] = {
238 { .baud = DEF_BAUD,
239 .ioport = (unsigned char *)R_SERIAL0_CTRL,
240 .irq = 1U << 12, /* uses DMA 6 and 7 */
241 .oclrintradr = R_DMA_CH6_CLR_INTR,
242 .ofirstadr = R_DMA_CH6_FIRST,
243 .ocmdadr = R_DMA_CH6_CMD,
244 .ostatusadr = R_DMA_CH6_STATUS,
245 .iclrintradr = R_DMA_CH7_CLR_INTR,
246 .ifirstadr = R_DMA_CH7_FIRST,
247 .icmdadr = R_DMA_CH7_CMD,
248 .idescradr = R_DMA_CH7_DESCR,
249 .flags = STD_FLAGS,
250 .rx_ctrl = DEF_RX,
251 .tx_ctrl = DEF_TX,
252 .iseteop = 2,
253 .dma_owner = dma_ser0,
254 .io_if = if_serial_0,
255#ifdef CONFIG_ETRAX_SERIAL_PORT0
256 .enabled = 1,
257#ifdef CONFIG_ETRAX_SERIAL_PORT0_DMA6_OUT
258 .dma_out_enabled = 1,
259 .dma_out_nbr = SER0_TX_DMA_NBR,
260 .dma_out_irq_nbr = SER0_DMA_TX_IRQ_NBR,
261 .dma_out_irq_flags = IRQF_DISABLED,
262 .dma_out_irq_description = "serial 0 dma tr",
263#else
264 .dma_out_enabled = 0,
265 .dma_out_nbr = UINT_MAX,
266 .dma_out_irq_nbr = 0,
267 .dma_out_irq_flags = 0,
268 .dma_out_irq_description = NULL,
269#endif
270#ifdef CONFIG_ETRAX_SERIAL_PORT0_DMA7_IN
271 .dma_in_enabled = 1,
272 .dma_in_nbr = SER0_RX_DMA_NBR,
273 .dma_in_irq_nbr = SER0_DMA_RX_IRQ_NBR,
274 .dma_in_irq_flags = IRQF_DISABLED,
275 .dma_in_irq_description = "serial 0 dma rec",
276#else
277 .dma_in_enabled = 0,
278 .dma_in_nbr = UINT_MAX,
279 .dma_in_irq_nbr = 0,
280 .dma_in_irq_flags = 0,
281 .dma_in_irq_description = NULL,
282#endif
283#else
284 .enabled = 0,
285 .io_if_description = NULL,
286 .dma_out_enabled = 0,
287 .dma_in_enabled = 0
288#endif
289
290}, /* ttyS0 */
291#ifndef CONFIG_SVINTO_SIM
292 { .baud = DEF_BAUD,
293 .ioport = (unsigned char *)R_SERIAL1_CTRL,
294 .irq = 1U << 16, /* uses DMA 8 and 9 */
295 .oclrintradr = R_DMA_CH8_CLR_INTR,
296 .ofirstadr = R_DMA_CH8_FIRST,
297 .ocmdadr = R_DMA_CH8_CMD,
298 .ostatusadr = R_DMA_CH8_STATUS,
299 .iclrintradr = R_DMA_CH9_CLR_INTR,
300 .ifirstadr = R_DMA_CH9_FIRST,
301 .icmdadr = R_DMA_CH9_CMD,
302 .idescradr = R_DMA_CH9_DESCR,
303 .flags = STD_FLAGS,
304 .rx_ctrl = DEF_RX,
305 .tx_ctrl = DEF_TX,
306 .iseteop = 3,
307 .dma_owner = dma_ser1,
308 .io_if = if_serial_1,
309#ifdef CONFIG_ETRAX_SERIAL_PORT1
310 .enabled = 1,
311 .io_if_description = "ser1",
312#ifdef CONFIG_ETRAX_SERIAL_PORT1_DMA8_OUT
313 .dma_out_enabled = 1,
314 .dma_out_nbr = SER1_TX_DMA_NBR,
315 .dma_out_irq_nbr = SER1_DMA_TX_IRQ_NBR,
316 .dma_out_irq_flags = IRQF_DISABLED,
317 .dma_out_irq_description = "serial 1 dma tr",
318#else
319 .dma_out_enabled = 0,
320 .dma_out_nbr = UINT_MAX,
321 .dma_out_irq_nbr = 0,
322 .dma_out_irq_flags = 0,
323 .dma_out_irq_description = NULL,
324#endif
325#ifdef CONFIG_ETRAX_SERIAL_PORT1_DMA9_IN
326 .dma_in_enabled = 1,
327 .dma_in_nbr = SER1_RX_DMA_NBR,
328 .dma_in_irq_nbr = SER1_DMA_RX_IRQ_NBR,
329 .dma_in_irq_flags = IRQF_DISABLED,
330 .dma_in_irq_description = "serial 1 dma rec",
331#else
332 .dma_in_enabled = 0,
333 .dma_in_enabled = 0,
334 .dma_in_nbr = UINT_MAX,
335 .dma_in_irq_nbr = 0,
336 .dma_in_irq_flags = 0,
337 .dma_in_irq_description = NULL,
338#endif
339#else
340 .enabled = 0,
341 .io_if_description = NULL,
342 .dma_in_irq_nbr = 0,
343 .dma_out_enabled = 0,
344 .dma_in_enabled = 0
345#endif
346}, /* ttyS1 */
347
348 { .baud = DEF_BAUD,
349 .ioport = (unsigned char *)R_SERIAL2_CTRL,
350 .irq = 1U << 4, /* uses DMA 2 and 3 */
351 .oclrintradr = R_DMA_CH2_CLR_INTR,
352 .ofirstadr = R_DMA_CH2_FIRST,
353 .ocmdadr = R_DMA_CH2_CMD,
354 .ostatusadr = R_DMA_CH2_STATUS,
355 .iclrintradr = R_DMA_CH3_CLR_INTR,
356 .ifirstadr = R_DMA_CH3_FIRST,
357 .icmdadr = R_DMA_CH3_CMD,
358 .idescradr = R_DMA_CH3_DESCR,
359 .flags = STD_FLAGS,
360 .rx_ctrl = DEF_RX,
361 .tx_ctrl = DEF_TX,
362 .iseteop = 0,
363 .dma_owner = dma_ser2,
364 .io_if = if_serial_2,
365#ifdef CONFIG_ETRAX_SERIAL_PORT2
366 .enabled = 1,
367 .io_if_description = "ser2",
368#ifdef CONFIG_ETRAX_SERIAL_PORT2_DMA2_OUT
369 .dma_out_enabled = 1,
370 .dma_out_nbr = SER2_TX_DMA_NBR,
371 .dma_out_irq_nbr = SER2_DMA_TX_IRQ_NBR,
372 .dma_out_irq_flags = IRQF_DISABLED,
373 .dma_out_irq_description = "serial 2 dma tr",
374#else
375 .dma_out_enabled = 0,
376 .dma_out_nbr = UINT_MAX,
377 .dma_out_irq_nbr = 0,
378 .dma_out_irq_flags = 0,
379 .dma_out_irq_description = NULL,
380#endif
381#ifdef CONFIG_ETRAX_SERIAL_PORT2_DMA3_IN
382 .dma_in_enabled = 1,
383 .dma_in_nbr = SER2_RX_DMA_NBR,
384 .dma_in_irq_nbr = SER2_DMA_RX_IRQ_NBR,
385 .dma_in_irq_flags = IRQF_DISABLED,
386 .dma_in_irq_description = "serial 2 dma rec",
387#else
388 .dma_in_enabled = 0,
389 .dma_in_nbr = UINT_MAX,
390 .dma_in_irq_nbr = 0,
391 .dma_in_irq_flags = 0,
392 .dma_in_irq_description = NULL,
393#endif
394#else
395 .enabled = 0,
396 .io_if_description = NULL,
397 .dma_out_enabled = 0,
398 .dma_in_enabled = 0
399#endif
400 }, /* ttyS2 */
401
402 { .baud = DEF_BAUD,
403 .ioport = (unsigned char *)R_SERIAL3_CTRL,
404 .irq = 1U << 8, /* uses DMA 4 and 5 */
405 .oclrintradr = R_DMA_CH4_CLR_INTR,
406 .ofirstadr = R_DMA_CH4_FIRST,
407 .ocmdadr = R_DMA_CH4_CMD,
408 .ostatusadr = R_DMA_CH4_STATUS,
409 .iclrintradr = R_DMA_CH5_CLR_INTR,
410 .ifirstadr = R_DMA_CH5_FIRST,
411 .icmdadr = R_DMA_CH5_CMD,
412 .idescradr = R_DMA_CH5_DESCR,
413 .flags = STD_FLAGS,
414 .rx_ctrl = DEF_RX,
415 .tx_ctrl = DEF_TX,
416 .iseteop = 1,
417 .dma_owner = dma_ser3,
418 .io_if = if_serial_3,
419#ifdef CONFIG_ETRAX_SERIAL_PORT3
420 .enabled = 1,
421 .io_if_description = "ser3",
422#ifdef CONFIG_ETRAX_SERIAL_PORT3_DMA4_OUT
423 .dma_out_enabled = 1,
424 .dma_out_nbr = SER3_TX_DMA_NBR,
425 .dma_out_irq_nbr = SER3_DMA_TX_IRQ_NBR,
426 .dma_out_irq_flags = IRQF_DISABLED,
427 .dma_out_irq_description = "serial 3 dma tr",
428#else
429 .dma_out_enabled = 0,
430 .dma_out_nbr = UINT_MAX,
431 .dma_out_irq_nbr = 0,
432 .dma_out_irq_flags = 0,
433 .dma_out_irq_description = NULL,
434#endif
435#ifdef CONFIG_ETRAX_SERIAL_PORT3_DMA5_IN
436 .dma_in_enabled = 1,
437 .dma_in_nbr = SER3_RX_DMA_NBR,
438 .dma_in_irq_nbr = SER3_DMA_RX_IRQ_NBR,
439 .dma_in_irq_flags = IRQF_DISABLED,
440 .dma_in_irq_description = "serial 3 dma rec",
441#else
442 .dma_in_enabled = 0,
443 .dma_in_nbr = UINT_MAX,
444 .dma_in_irq_nbr = 0,
445 .dma_in_irq_flags = 0,
446 .dma_in_irq_description = NULL
447#endif
448#else
449 .enabled = 0,
450 .io_if_description = NULL,
451 .dma_out_enabled = 0,
452 .dma_in_enabled = 0
453#endif
454 } /* ttyS3 */
455#endif
456};
457
458
459#define NR_PORTS (sizeof(rs_table)/sizeof(struct e100_serial))
460
461#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
462static struct fast_timer fast_timers[NR_PORTS];
463#endif
464
465#ifdef CONFIG_ETRAX_SERIAL_PROC_ENTRY
466#define PROCSTAT(x) x
467struct ser_statistics_type {
468 int overrun_cnt;
469 int early_errors_cnt;
470 int ser_ints_ok_cnt;
471 int errors_cnt;
472 unsigned long int processing_flip;
473 unsigned long processing_flip_still_room;
474 unsigned long int timeout_flush_cnt;
475 int rx_dma_ints;
476 int tx_dma_ints;
477 int rx_tot;
478 int tx_tot;
479};
480
481static struct ser_statistics_type ser_stat[NR_PORTS];
482
483#else
484
485#define PROCSTAT(x)
486
487#endif /* CONFIG_ETRAX_SERIAL_PROC_ENTRY */
488
489/* RS-485 */
490#if defined(CONFIG_ETRAX_RS485)
491#ifdef CONFIG_ETRAX_FAST_TIMER
492static struct fast_timer fast_timers_rs485[NR_PORTS];
493#endif
494#if defined(CONFIG_ETRAX_RS485_ON_PA)
495static int rs485_pa_bit = CONFIG_ETRAX_RS485_ON_PA_BIT;
496#endif
497#if defined(CONFIG_ETRAX_RS485_ON_PORT_G)
498static int rs485_port_g_bit = CONFIG_ETRAX_RS485_ON_PORT_G_BIT;
499#endif
500#endif
501
502/* Info and macros needed for each ports extra control/status signals. */
503#define E100_STRUCT_PORT(line, pinname) \
504 ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \
505 (R_PORT_PA_DATA): ( \
506 (CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \
507 (R_PORT_PB_DATA):&dummy_ser[line]))
508
509#define E100_STRUCT_SHADOW(line, pinname) \
510 ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \
511 (&port_pa_data_shadow): ( \
512 (CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \
513 (&port_pb_data_shadow):&dummy_ser[line]))
514#define E100_STRUCT_MASK(line, pinname) \
515 ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \
516 (1<<CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT): ( \
517 (CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \
518 (1<<CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT):DUMMY_##pinname##_MASK))
519
520#define DUMMY_DTR_MASK 1
521#define DUMMY_RI_MASK 2
522#define DUMMY_DSR_MASK 4
523#define DUMMY_CD_MASK 8
524static unsigned char dummy_ser[NR_PORTS] = {0xFF, 0xFF, 0xFF,0xFF};
525
526/* If not all status pins are used or disabled, use mixed mode */
527#ifdef CONFIG_ETRAX_SERIAL_PORT0
528
529#define SER0_PA_BITSUM (CONFIG_ETRAX_SER0_DTR_ON_PA_BIT+CONFIG_ETRAX_SER0_RI_ON_PA_BIT+CONFIG_ETRAX_SER0_DSR_ON_PA_BIT+CONFIG_ETRAX_SER0_CD_ON_PA_BIT)
530
531#if SER0_PA_BITSUM != -4
532# if CONFIG_ETRAX_SER0_DTR_ON_PA_BIT == -1
533# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
534# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
535# endif
536# endif
537# if CONFIG_ETRAX_SER0_RI_ON_PA_BIT == -1
538# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
539# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
540# endif
541# endif
542# if CONFIG_ETRAX_SER0_DSR_ON_PA_BIT == -1
543# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
544# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
545# endif
546# endif
547# if CONFIG_ETRAX_SER0_CD_ON_PA_BIT == -1
548# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
549# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
550# endif
551# endif
552#endif
553
554#define SER0_PB_BITSUM (CONFIG_ETRAX_SER0_DTR_ON_PB_BIT+CONFIG_ETRAX_SER0_RI_ON_PB_BIT+CONFIG_ETRAX_SER0_DSR_ON_PB_BIT+CONFIG_ETRAX_SER0_CD_ON_PB_BIT)
555
556#if SER0_PB_BITSUM != -4
557# if CONFIG_ETRAX_SER0_DTR_ON_PB_BIT == -1
558# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
559# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
560# endif
561# endif
562# if CONFIG_ETRAX_SER0_RI_ON_PB_BIT == -1
563# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
564# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
565# endif
566# endif
567# if CONFIG_ETRAX_SER0_DSR_ON_PB_BIT == -1
568# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
569# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
570# endif
571# endif
572# if CONFIG_ETRAX_SER0_CD_ON_PB_BIT == -1
573# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
574# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
575# endif
576# endif
577#endif
578
579#endif /* PORT0 */
580
581
582#ifdef CONFIG_ETRAX_SERIAL_PORT1
583
584#define SER1_PA_BITSUM (CONFIG_ETRAX_SER1_DTR_ON_PA_BIT+CONFIG_ETRAX_SER1_RI_ON_PA_BIT+CONFIG_ETRAX_SER1_DSR_ON_PA_BIT+CONFIG_ETRAX_SER1_CD_ON_PA_BIT)
585
586#if SER1_PA_BITSUM != -4
587# if CONFIG_ETRAX_SER1_DTR_ON_PA_BIT == -1
588# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
589# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
590# endif
591# endif
592# if CONFIG_ETRAX_SER1_RI_ON_PA_BIT == -1
593# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
594# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
595# endif
596# endif
597# if CONFIG_ETRAX_SER1_DSR_ON_PA_BIT == -1
598# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
599# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
600# endif
601# endif
602# if CONFIG_ETRAX_SER1_CD_ON_PA_BIT == -1
603# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
604# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
605# endif
606# endif
607#endif
608
609#define SER1_PB_BITSUM (CONFIG_ETRAX_SER1_DTR_ON_PB_BIT+CONFIG_ETRAX_SER1_RI_ON_PB_BIT+CONFIG_ETRAX_SER1_DSR_ON_PB_BIT+CONFIG_ETRAX_SER1_CD_ON_PB_BIT)
610
611#if SER1_PB_BITSUM != -4
612# if CONFIG_ETRAX_SER1_DTR_ON_PB_BIT == -1
613# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
614# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
615# endif
616# endif
617# if CONFIG_ETRAX_SER1_RI_ON_PB_BIT == -1
618# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
619# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
620# endif
621# endif
622# if CONFIG_ETRAX_SER1_DSR_ON_PB_BIT == -1
623# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
624# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
625# endif
626# endif
627# if CONFIG_ETRAX_SER1_CD_ON_PB_BIT == -1
628# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
629# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
630# endif
631# endif
632#endif
633
634#endif /* PORT1 */
635
636#ifdef CONFIG_ETRAX_SERIAL_PORT2
637
638#define SER2_PA_BITSUM (CONFIG_ETRAX_SER2_DTR_ON_PA_BIT+CONFIG_ETRAX_SER2_RI_ON_PA_BIT+CONFIG_ETRAX_SER2_DSR_ON_PA_BIT+CONFIG_ETRAX_SER2_CD_ON_PA_BIT)
639
640#if SER2_PA_BITSUM != -4
641# if CONFIG_ETRAX_SER2_DTR_ON_PA_BIT == -1
642# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
643# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
644# endif
645# endif
646# if CONFIG_ETRAX_SER2_RI_ON_PA_BIT == -1
647# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
648# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
649# endif
650# endif
651# if CONFIG_ETRAX_SER2_DSR_ON_PA_BIT == -1
652# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
653# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
654# endif
655# endif
656# if CONFIG_ETRAX_SER2_CD_ON_PA_BIT == -1
657# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
658# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
659# endif
660# endif
661#endif
662
663#define SER2_PB_BITSUM (CONFIG_ETRAX_SER2_DTR_ON_PB_BIT+CONFIG_ETRAX_SER2_RI_ON_PB_BIT+CONFIG_ETRAX_SER2_DSR_ON_PB_BIT+CONFIG_ETRAX_SER2_CD_ON_PB_BIT)
664
665#if SER2_PB_BITSUM != -4
666# if CONFIG_ETRAX_SER2_DTR_ON_PB_BIT == -1
667# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
668# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
669# endif
670# endif
671# if CONFIG_ETRAX_SER2_RI_ON_PB_BIT == -1
672# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
673# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
674# endif
675# endif
676# if CONFIG_ETRAX_SER2_DSR_ON_PB_BIT == -1
677# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
678# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
679# endif
680# endif
681# if CONFIG_ETRAX_SER2_CD_ON_PB_BIT == -1
682# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
683# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
684# endif
685# endif
686#endif
687
688#endif /* PORT2 */
689
690#ifdef CONFIG_ETRAX_SERIAL_PORT3
691
692#define SER3_PA_BITSUM (CONFIG_ETRAX_SER3_DTR_ON_PA_BIT+CONFIG_ETRAX_SER3_RI_ON_PA_BIT+CONFIG_ETRAX_SER3_DSR_ON_PA_BIT+CONFIG_ETRAX_SER3_CD_ON_PA_BIT)
693
694#if SER3_PA_BITSUM != -4
695# if CONFIG_ETRAX_SER3_DTR_ON_PA_BIT == -1
696# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
697# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
698# endif
699# endif
700# if CONFIG_ETRAX_SER3_RI_ON_PA_BIT == -1
701# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
702# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
703# endif
704# endif
705# if CONFIG_ETRAX_SER3_DSR_ON_PA_BIT == -1
706# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
707# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
708# endif
709# endif
710# if CONFIG_ETRAX_SER3_CD_ON_PA_BIT == -1
711# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
712# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
713# endif
714# endif
715#endif
716
717#define SER3_PB_BITSUM (CONFIG_ETRAX_SER3_DTR_ON_PB_BIT+CONFIG_ETRAX_SER3_RI_ON_PB_BIT+CONFIG_ETRAX_SER3_DSR_ON_PB_BIT+CONFIG_ETRAX_SER3_CD_ON_PB_BIT)
718
719#if SER3_PB_BITSUM != -4
720# if CONFIG_ETRAX_SER3_DTR_ON_PB_BIT == -1
721# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
722# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
723# endif
724# endif
725# if CONFIG_ETRAX_SER3_RI_ON_PB_BIT == -1
726# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
727# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
728# endif
729# endif
730# if CONFIG_ETRAX_SER3_DSR_ON_PB_BIT == -1
731# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
732# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
733# endif
734# endif
735# if CONFIG_ETRAX_SER3_CD_ON_PB_BIT == -1
736# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
737# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
738# endif
739# endif
740#endif
741
742#endif /* PORT3 */
743
744
745#if defined(CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED) || \
746 defined(CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED) || \
747 defined(CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED) || \
748 defined(CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED)
749#define CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED
750#endif
751
752#ifdef CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED
753/* The pins can be mixed on PA and PB */
754#define CONTROL_PINS_PORT_NOT_USED(line) \
755 &dummy_ser[line], &dummy_ser[line], \
756 &dummy_ser[line], &dummy_ser[line], \
757 &dummy_ser[line], &dummy_ser[line], \
758 &dummy_ser[line], &dummy_ser[line], \
759 DUMMY_DTR_MASK, DUMMY_RI_MASK, DUMMY_DSR_MASK, DUMMY_CD_MASK
760
761
762struct control_pins
763{
764 volatile unsigned char *dtr_port;
765 unsigned char *dtr_shadow;
766 volatile unsigned char *ri_port;
767 unsigned char *ri_shadow;
768 volatile unsigned char *dsr_port;
769 unsigned char *dsr_shadow;
770 volatile unsigned char *cd_port;
771 unsigned char *cd_shadow;
772
773 unsigned char dtr_mask;
774 unsigned char ri_mask;
775 unsigned char dsr_mask;
776 unsigned char cd_mask;
777};
778
779static const struct control_pins e100_modem_pins[NR_PORTS] =
780{
781 /* Ser 0 */
782 {
783#ifdef CONFIG_ETRAX_SERIAL_PORT0
784 E100_STRUCT_PORT(0,DTR), E100_STRUCT_SHADOW(0,DTR),
785 E100_STRUCT_PORT(0,RI), E100_STRUCT_SHADOW(0,RI),
786 E100_STRUCT_PORT(0,DSR), E100_STRUCT_SHADOW(0,DSR),
787 E100_STRUCT_PORT(0,CD), E100_STRUCT_SHADOW(0,CD),
788 E100_STRUCT_MASK(0,DTR),
789 E100_STRUCT_MASK(0,RI),
790 E100_STRUCT_MASK(0,DSR),
791 E100_STRUCT_MASK(0,CD)
792#else
793 CONTROL_PINS_PORT_NOT_USED(0)
794#endif
795 },
796
797 /* Ser 1 */
798 {
799#ifdef CONFIG_ETRAX_SERIAL_PORT1
800 E100_STRUCT_PORT(1,DTR), E100_STRUCT_SHADOW(1,DTR),
801 E100_STRUCT_PORT(1,RI), E100_STRUCT_SHADOW(1,RI),
802 E100_STRUCT_PORT(1,DSR), E100_STRUCT_SHADOW(1,DSR),
803 E100_STRUCT_PORT(1,CD), E100_STRUCT_SHADOW(1,CD),
804 E100_STRUCT_MASK(1,DTR),
805 E100_STRUCT_MASK(1,RI),
806 E100_STRUCT_MASK(1,DSR),
807 E100_STRUCT_MASK(1,CD)
808#else
809 CONTROL_PINS_PORT_NOT_USED(1)
810#endif
811 },
812
813 /* Ser 2 */
814 {
815#ifdef CONFIG_ETRAX_SERIAL_PORT2
816 E100_STRUCT_PORT(2,DTR), E100_STRUCT_SHADOW(2,DTR),
817 E100_STRUCT_PORT(2,RI), E100_STRUCT_SHADOW(2,RI),
818 E100_STRUCT_PORT(2,DSR), E100_STRUCT_SHADOW(2,DSR),
819 E100_STRUCT_PORT(2,CD), E100_STRUCT_SHADOW(2,CD),
820 E100_STRUCT_MASK(2,DTR),
821 E100_STRUCT_MASK(2,RI),
822 E100_STRUCT_MASK(2,DSR),
823 E100_STRUCT_MASK(2,CD)
824#else
825 CONTROL_PINS_PORT_NOT_USED(2)
826#endif
827 },
828
829 /* Ser 3 */
830 {
831#ifdef CONFIG_ETRAX_SERIAL_PORT3
832 E100_STRUCT_PORT(3,DTR), E100_STRUCT_SHADOW(3,DTR),
833 E100_STRUCT_PORT(3,RI), E100_STRUCT_SHADOW(3,RI),
834 E100_STRUCT_PORT(3,DSR), E100_STRUCT_SHADOW(3,DSR),
835 E100_STRUCT_PORT(3,CD), E100_STRUCT_SHADOW(3,CD),
836 E100_STRUCT_MASK(3,DTR),
837 E100_STRUCT_MASK(3,RI),
838 E100_STRUCT_MASK(3,DSR),
839 E100_STRUCT_MASK(3,CD)
840#else
841 CONTROL_PINS_PORT_NOT_USED(3)
842#endif
843 }
844};
845#else /* CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED */
846
847/* All pins are on either PA or PB for each serial port */
848#define CONTROL_PINS_PORT_NOT_USED(line) \
849 &dummy_ser[line], &dummy_ser[line], \
850 DUMMY_DTR_MASK, DUMMY_RI_MASK, DUMMY_DSR_MASK, DUMMY_CD_MASK
851
852
853struct control_pins
854{
855 volatile unsigned char *port;
856 unsigned char *shadow;
857
858 unsigned char dtr_mask;
859 unsigned char ri_mask;
860 unsigned char dsr_mask;
861 unsigned char cd_mask;
862};
863
864#define dtr_port port
865#define dtr_shadow shadow
866#define ri_port port
867#define ri_shadow shadow
868#define dsr_port port
869#define dsr_shadow shadow
870#define cd_port port
871#define cd_shadow shadow
872
873static const struct control_pins e100_modem_pins[NR_PORTS] =
874{
875 /* Ser 0 */
876 {
877#ifdef CONFIG_ETRAX_SERIAL_PORT0
878 E100_STRUCT_PORT(0,DTR), E100_STRUCT_SHADOW(0,DTR),
879 E100_STRUCT_MASK(0,DTR),
880 E100_STRUCT_MASK(0,RI),
881 E100_STRUCT_MASK(0,DSR),
882 E100_STRUCT_MASK(0,CD)
883#else
884 CONTROL_PINS_PORT_NOT_USED(0)
885#endif
886 },
887
888 /* Ser 1 */
889 {
890#ifdef CONFIG_ETRAX_SERIAL_PORT1
891 E100_STRUCT_PORT(1,DTR), E100_STRUCT_SHADOW(1,DTR),
892 E100_STRUCT_MASK(1,DTR),
893 E100_STRUCT_MASK(1,RI),
894 E100_STRUCT_MASK(1,DSR),
895 E100_STRUCT_MASK(1,CD)
896#else
897 CONTROL_PINS_PORT_NOT_USED(1)
898#endif
899 },
900
901 /* Ser 2 */
902 {
903#ifdef CONFIG_ETRAX_SERIAL_PORT2
904 E100_STRUCT_PORT(2,DTR), E100_STRUCT_SHADOW(2,DTR),
905 E100_STRUCT_MASK(2,DTR),
906 E100_STRUCT_MASK(2,RI),
907 E100_STRUCT_MASK(2,DSR),
908 E100_STRUCT_MASK(2,CD)
909#else
910 CONTROL_PINS_PORT_NOT_USED(2)
911#endif
912 },
913
914 /* Ser 3 */
915 {
916#ifdef CONFIG_ETRAX_SERIAL_PORT3
917 E100_STRUCT_PORT(3,DTR), E100_STRUCT_SHADOW(3,DTR),
918 E100_STRUCT_MASK(3,DTR),
919 E100_STRUCT_MASK(3,RI),
920 E100_STRUCT_MASK(3,DSR),
921 E100_STRUCT_MASK(3,CD)
922#else
923 CONTROL_PINS_PORT_NOT_USED(3)
924#endif
925 }
926};
927#endif /* !CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED */
928
929#define E100_RTS_MASK 0x20
930#define E100_CTS_MASK 0x40
931
932/* All serial port signals are active low:
933 * active = 0 -> 3.3V to RS-232 driver -> -12V on RS-232 level
934 * inactive = 1 -> 0V to RS-232 driver -> +12V on RS-232 level
935 *
936 * These macros returns the pin value: 0=0V, >=1 = 3.3V on ETRAX chip
937 */
938
939/* Output */
940#define E100_RTS_GET(info) ((info)->rx_ctrl & E100_RTS_MASK)
941/* Input */
942#define E100_CTS_GET(info) ((info)->ioport[REG_STATUS] & E100_CTS_MASK)
943
944/* These are typically PA or PB and 0 means 0V, 1 means 3.3V */
945/* Is an output */
946#define E100_DTR_GET(info) ((*e100_modem_pins[(info)->line].dtr_shadow) & e100_modem_pins[(info)->line].dtr_mask)
947
948/* Normally inputs */
949#define E100_RI_GET(info) ((*e100_modem_pins[(info)->line].ri_port) & e100_modem_pins[(info)->line].ri_mask)
950#define E100_CD_GET(info) ((*e100_modem_pins[(info)->line].cd_port) & e100_modem_pins[(info)->line].cd_mask)
951
952/* Input */
953#define E100_DSR_GET(info) ((*e100_modem_pins[(info)->line].dsr_port) & e100_modem_pins[(info)->line].dsr_mask)
954
955
956/*
957 * tmp_buf is used as a temporary buffer by serial_write. We need to
958 * lock it in case the memcpy_fromfs blocks while swapping in a page,
959 * and some other program tries to do a serial write at the same time.
960 * Since the lock will only come under contention when the system is
961 * swapping and available memory is low, it makes sense to share one
962 * buffer across all the serial ports, since it significantly saves
963 * memory if large numbers of serial ports are open.
964 */
965static unsigned char *tmp_buf;
966static DEFINE_MUTEX(tmp_buf_mutex);
967
968/* Calculate the chartime depending on baudrate, numbor of bits etc. */
969static void update_char_time(struct e100_serial * info)
970{
971 tcflag_t cflags = info->port.tty->termios->c_cflag;
972 int bits;
973
974 /* calc. number of bits / data byte */
975 /* databits + startbit and 1 stopbit */
976 if ((cflags & CSIZE) == CS7)
977 bits = 9;
978 else
979 bits = 10;
980
981 if (cflags & CSTOPB) /* 2 stopbits ? */
982 bits++;
983
984 if (cflags & PARENB) /* parity bit ? */
985 bits++;
986
987 /* calc timeout */
988 info->char_time_usec = ((bits * 1000000) / info->baud) + 1;
989 info->flush_time_usec = 4*info->char_time_usec;
990 if (info->flush_time_usec < MIN_FLUSH_TIME_USEC)
991 info->flush_time_usec = MIN_FLUSH_TIME_USEC;
992
993}
994
995/*
996 * This function maps from the Bxxxx defines in asm/termbits.h into real
997 * baud rates.
998 */
999
1000static int
1001cflag_to_baud(unsigned int cflag)
1002{
1003 static int baud_table[] = {
1004 0, 50, 75, 110, 134, 150, 200, 300, 600, 1200, 1800, 2400,
1005 4800, 9600, 19200, 38400 };
1006
1007 static int ext_baud_table[] = {
1008 0, 57600, 115200, 230400, 460800, 921600, 1843200, 6250000,
1009 0, 0, 0, 0, 0, 0, 0, 0 };
1010
1011 if (cflag & CBAUDEX)
1012 return ext_baud_table[(cflag & CBAUD) & ~CBAUDEX];
1013 else
1014 return baud_table[cflag & CBAUD];
1015}
1016
1017/* and this maps to an etrax100 hardware baud constant */
1018
1019static unsigned char
1020cflag_to_etrax_baud(unsigned int cflag)
1021{
1022 char retval;
1023
1024 static char baud_table[] = {
1025 -1, -1, -1, -1, -1, -1, -1, 0, 1, 2, -1, 3, 4, 5, 6, 7 };
1026
1027 static char ext_baud_table[] = {
1028 -1, 8, 9, 10, 11, 12, 13, 14, -1, -1, -1, -1, -1, -1, -1, -1 };
1029
1030 if (cflag & CBAUDEX)
1031 retval = ext_baud_table[(cflag & CBAUD) & ~CBAUDEX];
1032 else
1033 retval = baud_table[cflag & CBAUD];
1034
1035 if (retval < 0) {
1036 printk(KERN_WARNING "serdriver tried setting invalid baud rate, flags %x.\n", cflag);
1037 retval = 5; /* choose default 9600 instead */
1038 }
1039
1040 return retval | (retval << 4); /* choose same for both TX and RX */
1041}
1042
1043
1044/* Various static support functions */
1045
1046/* Functions to set or clear DTR/RTS on the requested line */
1047/* It is complicated by the fact that RTS is a serial port register, while
1048 * DTR might not be implemented in the HW at all, and if it is, it can be on
1049 * any general port.
1050 */
1051
1052
1053static inline void
1054e100_dtr(struct e100_serial *info, int set)
1055{
1056#ifndef CONFIG_SVINTO_SIM
1057 unsigned char mask = e100_modem_pins[info->line].dtr_mask;
1058
1059#ifdef SERIAL_DEBUG_IO
1060 printk("ser%i dtr %i mask: 0x%02X\n", info->line, set, mask);
1061 printk("ser%i shadow before 0x%02X get: %i\n",
1062 info->line, *e100_modem_pins[info->line].dtr_shadow,
1063 E100_DTR_GET(info));
1064#endif
1065 /* DTR is active low */
1066 {
1067 unsigned long flags;
1068
1069 local_irq_save(flags);
1070 *e100_modem_pins[info->line].dtr_shadow &= ~mask;
1071 *e100_modem_pins[info->line].dtr_shadow |= (set ? 0 : mask);
1072 *e100_modem_pins[info->line].dtr_port = *e100_modem_pins[info->line].dtr_shadow;
1073 local_irq_restore(flags);
1074 }
1075
1076#ifdef SERIAL_DEBUG_IO
1077 printk("ser%i shadow after 0x%02X get: %i\n",
1078 info->line, *e100_modem_pins[info->line].dtr_shadow,
1079 E100_DTR_GET(info));
1080#endif
1081#endif
1082}
1083
1084/* set = 0 means 3.3V on the pin, bitvalue: 0=active, 1=inactive
1085 * 0=0V , 1=3.3V
1086 */
1087static inline void
1088e100_rts(struct e100_serial *info, int set)
1089{
1090#ifndef CONFIG_SVINTO_SIM
1091 unsigned long flags;
1092 local_irq_save(flags);
1093 info->rx_ctrl &= ~E100_RTS_MASK;
1094 info->rx_ctrl |= (set ? 0 : E100_RTS_MASK); /* RTS is active low */
1095 info->ioport[REG_REC_CTRL] = info->rx_ctrl;
1096 local_irq_restore(flags);
1097#ifdef SERIAL_DEBUG_IO
1098 printk("ser%i rts %i\n", info->line, set);
1099#endif
1100#endif
1101}
1102
1103
1104/* If this behaves as a modem, RI and CD is an output */
1105static inline void
1106e100_ri_out(struct e100_serial *info, int set)
1107{
1108#ifndef CONFIG_SVINTO_SIM
1109 /* RI is active low */
1110 {
1111 unsigned char mask = e100_modem_pins[info->line].ri_mask;
1112 unsigned long flags;
1113
1114 local_irq_save(flags);
1115 *e100_modem_pins[info->line].ri_shadow &= ~mask;
1116 *e100_modem_pins[info->line].ri_shadow |= (set ? 0 : mask);
1117 *e100_modem_pins[info->line].ri_port = *e100_modem_pins[info->line].ri_shadow;
1118 local_irq_restore(flags);
1119 }
1120#endif
1121}
1122static inline void
1123e100_cd_out(struct e100_serial *info, int set)
1124{
1125#ifndef CONFIG_SVINTO_SIM
1126 /* CD is active low */
1127 {
1128 unsigned char mask = e100_modem_pins[info->line].cd_mask;
1129 unsigned long flags;
1130
1131 local_irq_save(flags);
1132 *e100_modem_pins[info->line].cd_shadow &= ~mask;
1133 *e100_modem_pins[info->line].cd_shadow |= (set ? 0 : mask);
1134 *e100_modem_pins[info->line].cd_port = *e100_modem_pins[info->line].cd_shadow;
1135 local_irq_restore(flags);
1136 }
1137#endif
1138}
1139
1140static inline void
1141e100_disable_rx(struct e100_serial *info)
1142{
1143#ifndef CONFIG_SVINTO_SIM
1144 /* disable the receiver */
1145 info->ioport[REG_REC_CTRL] =
1146 (info->rx_ctrl &= ~IO_MASK(R_SERIAL0_REC_CTRL, rec_enable));
1147#endif
1148}
1149
1150static inline void
1151e100_enable_rx(struct e100_serial *info)
1152{
1153#ifndef CONFIG_SVINTO_SIM
1154 /* enable the receiver */
1155 info->ioport[REG_REC_CTRL] =
1156 (info->rx_ctrl |= IO_MASK(R_SERIAL0_REC_CTRL, rec_enable));
1157#endif
1158}
1159
1160/* the rx DMA uses both the dma_descr and the dma_eop interrupts */
1161
1162static inline void
1163e100_disable_rxdma_irq(struct e100_serial *info)
1164{
1165#ifdef SERIAL_DEBUG_INTR
1166 printk("rxdma_irq(%d): 0\n",info->line);
1167#endif
1168 DINTR1(DEBUG_LOG(info->line,"IRQ disable_rxdma_irq %i\n", info->line));
1169 *R_IRQ_MASK2_CLR = (info->irq << 2) | (info->irq << 3);
1170}
1171
1172static inline void
1173e100_enable_rxdma_irq(struct e100_serial *info)
1174{
1175#ifdef SERIAL_DEBUG_INTR
1176 printk("rxdma_irq(%d): 1\n",info->line);
1177#endif
1178 DINTR1(DEBUG_LOG(info->line,"IRQ enable_rxdma_irq %i\n", info->line));
1179 *R_IRQ_MASK2_SET = (info->irq << 2) | (info->irq << 3);
1180}
1181
1182/* the tx DMA uses only dma_descr interrupt */
1183
1184static void e100_disable_txdma_irq(struct e100_serial *info)
1185{
1186#ifdef SERIAL_DEBUG_INTR
1187 printk("txdma_irq(%d): 0\n",info->line);
1188#endif
1189 DINTR1(DEBUG_LOG(info->line,"IRQ disable_txdma_irq %i\n", info->line));
1190 *R_IRQ_MASK2_CLR = info->irq;
1191}
1192
1193static void e100_enable_txdma_irq(struct e100_serial *info)
1194{
1195#ifdef SERIAL_DEBUG_INTR
1196 printk("txdma_irq(%d): 1\n",info->line);
1197#endif
1198 DINTR1(DEBUG_LOG(info->line,"IRQ enable_txdma_irq %i\n", info->line));
1199 *R_IRQ_MASK2_SET = info->irq;
1200}
1201
1202static void e100_disable_txdma_channel(struct e100_serial *info)
1203{
1204 unsigned long flags;
1205
1206 /* Disable output DMA channel for the serial port in question
1207 * ( set to something other than serialX)
1208 */
1209 local_irq_save(flags);
1210 DFLOW(DEBUG_LOG(info->line, "disable_txdma_channel %i\n", info->line));
1211 if (info->line == 0) {
1212 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma6)) ==
1213 IO_STATE(R_GEN_CONFIG, dma6, serial0)) {
1214 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma6);
1215 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma6, unused);
1216 }
1217 } else if (info->line == 1) {
1218 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma8)) ==
1219 IO_STATE(R_GEN_CONFIG, dma8, serial1)) {
1220 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma8);
1221 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma8, usb);
1222 }
1223 } else if (info->line == 2) {
1224 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma2)) ==
1225 IO_STATE(R_GEN_CONFIG, dma2, serial2)) {
1226 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma2);
1227 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma2, par0);
1228 }
1229 } else if (info->line == 3) {
1230 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma4)) ==
1231 IO_STATE(R_GEN_CONFIG, dma4, serial3)) {
1232 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma4);
1233 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma4, par1);
1234 }
1235 }
1236 *R_GEN_CONFIG = genconfig_shadow;
1237 local_irq_restore(flags);
1238}
1239
1240
1241static void e100_enable_txdma_channel(struct e100_serial *info)
1242{
1243 unsigned long flags;
1244
1245 local_irq_save(flags);
1246 DFLOW(DEBUG_LOG(info->line, "enable_txdma_channel %i\n", info->line));
1247 /* Enable output DMA channel for the serial port in question */
1248 if (info->line == 0) {
1249 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma6);
1250 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma6, serial0);
1251 } else if (info->line == 1) {
1252 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma8);
1253 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma8, serial1);
1254 } else if (info->line == 2) {
1255 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma2);
1256 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma2, serial2);
1257 } else if (info->line == 3) {
1258 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma4);
1259 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma4, serial3);
1260 }
1261 *R_GEN_CONFIG = genconfig_shadow;
1262 local_irq_restore(flags);
1263}
1264
1265static void e100_disable_rxdma_channel(struct e100_serial *info)
1266{
1267 unsigned long flags;
1268
1269 /* Disable input DMA channel for the serial port in question
1270 * ( set to something other than serialX)
1271 */
1272 local_irq_save(flags);
1273 if (info->line == 0) {
1274 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma7)) ==
1275 IO_STATE(R_GEN_CONFIG, dma7, serial0)) {
1276 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma7);
1277 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma7, unused);
1278 }
1279 } else if (info->line == 1) {
1280 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma9)) ==
1281 IO_STATE(R_GEN_CONFIG, dma9, serial1)) {
1282 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma9);
1283 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma9, usb);
1284 }
1285 } else if (info->line == 2) {
1286 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma3)) ==
1287 IO_STATE(R_GEN_CONFIG, dma3, serial2)) {
1288 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma3);
1289 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma3, par0);
1290 }
1291 } else if (info->line == 3) {
1292 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma5)) ==
1293 IO_STATE(R_GEN_CONFIG, dma5, serial3)) {
1294 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma5);
1295 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma5, par1);
1296 }
1297 }
1298 *R_GEN_CONFIG = genconfig_shadow;
1299 local_irq_restore(flags);
1300}
1301
1302
1303static void e100_enable_rxdma_channel(struct e100_serial *info)
1304{
1305 unsigned long flags;
1306
1307 local_irq_save(flags);
1308 /* Enable input DMA channel for the serial port in question */
1309 if (info->line == 0) {
1310 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma7);
1311 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma7, serial0);
1312 } else if (info->line == 1) {
1313 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma9);
1314 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma9, serial1);
1315 } else if (info->line == 2) {
1316 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma3);
1317 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma3, serial2);
1318 } else if (info->line == 3) {
1319 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma5);
1320 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma5, serial3);
1321 }
1322 *R_GEN_CONFIG = genconfig_shadow;
1323 local_irq_restore(flags);
1324}
1325
1326#ifdef SERIAL_HANDLE_EARLY_ERRORS
1327/* in order to detect and fix errors on the first byte
1328 we have to use the serial interrupts as well. */
1329
1330static inline void
1331e100_disable_serial_data_irq(struct e100_serial *info)
1332{
1333#ifdef SERIAL_DEBUG_INTR
1334 printk("ser_irq(%d): 0\n",info->line);
1335#endif
1336 DINTR1(DEBUG_LOG(info->line,"IRQ disable data_irq %i\n", info->line));
1337 *R_IRQ_MASK1_CLR = (1U << (8+2*info->line));
1338}
1339
1340static inline void
1341e100_enable_serial_data_irq(struct e100_serial *info)
1342{
1343#ifdef SERIAL_DEBUG_INTR
1344 printk("ser_irq(%d): 1\n",info->line);
1345 printk("**** %d = %d\n",
1346 (8+2*info->line),
1347 (1U << (8+2*info->line)));
1348#endif
1349 DINTR1(DEBUG_LOG(info->line,"IRQ enable data_irq %i\n", info->line));
1350 *R_IRQ_MASK1_SET = (1U << (8+2*info->line));
1351}
1352#endif
1353
1354static inline void
1355e100_disable_serial_tx_ready_irq(struct e100_serial *info)
1356{
1357#ifdef SERIAL_DEBUG_INTR
1358 printk("ser_tx_irq(%d): 0\n",info->line);
1359#endif
1360 DINTR1(DEBUG_LOG(info->line,"IRQ disable ready_irq %i\n", info->line));
1361 *R_IRQ_MASK1_CLR = (1U << (8+1+2*info->line));
1362}
1363
1364static inline void
1365e100_enable_serial_tx_ready_irq(struct e100_serial *info)
1366{
1367#ifdef SERIAL_DEBUG_INTR
1368 printk("ser_tx_irq(%d): 1\n",info->line);
1369 printk("**** %d = %d\n",
1370 (8+1+2*info->line),
1371 (1U << (8+1+2*info->line)));
1372#endif
1373 DINTR2(DEBUG_LOG(info->line,"IRQ enable ready_irq %i\n", info->line));
1374 *R_IRQ_MASK1_SET = (1U << (8+1+2*info->line));
1375}
1376
1377static inline void e100_enable_rx_irq(struct e100_serial *info)
1378{
1379 if (info->uses_dma_in)
1380 e100_enable_rxdma_irq(info);
1381 else
1382 e100_enable_serial_data_irq(info);
1383}
1384static inline void e100_disable_rx_irq(struct e100_serial *info)
1385{
1386 if (info->uses_dma_in)
1387 e100_disable_rxdma_irq(info);
1388 else
1389 e100_disable_serial_data_irq(info);
1390}
1391
1392#if defined(CONFIG_ETRAX_RS485)
1393/* Enable RS-485 mode on selected port. This is UGLY. */
1394static int
1395e100_enable_rs485(struct tty_struct *tty, struct serial_rs485 *r)
1396{
1397 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
1398
1399#if defined(CONFIG_ETRAX_RS485_ON_PA)
1400 *R_PORT_PA_DATA = port_pa_data_shadow |= (1 << rs485_pa_bit);
1401#endif
1402#if defined(CONFIG_ETRAX_RS485_ON_PORT_G)
1403 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
1404 rs485_port_g_bit, 1);
1405#endif
1406#if defined(CONFIG_ETRAX_RS485_LTC1387)
1407 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
1408 CONFIG_ETRAX_RS485_LTC1387_DXEN_PORT_G_BIT, 1);
1409 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
1410 CONFIG_ETRAX_RS485_LTC1387_RXEN_PORT_G_BIT, 1);
1411#endif
1412
1413 info->rs485 = *r;
1414
1415 /* Maximum delay before RTS equal to 1000 */
1416 if (info->rs485.delay_rts_before_send >= 1000)
1417 info->rs485.delay_rts_before_send = 1000;
1418
1419/* printk("rts: on send = %i, after = %i, enabled = %i",
1420 info->rs485.rts_on_send,
1421 info->rs485.rts_after_sent,
1422 info->rs485.enabled
1423 );
1424*/
1425 return 0;
1426}
1427
1428static int
1429e100_write_rs485(struct tty_struct *tty,
1430 const unsigned char *buf, int count)
1431{
1432 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
1433 int old_value = (info->rs485.flags) & SER_RS485_ENABLED;
1434
1435 /* rs485 is always implicitly enabled if we're using the ioctl()
1436 * but it doesn't have to be set in the serial_rs485
1437 * (to be backward compatible with old apps)
1438 * So we store, set and restore it.
1439 */
1440 info->rs485.flags |= SER_RS485_ENABLED;
1441 /* rs_write now deals with RS485 if enabled */
1442 count = rs_write(tty, buf, count);
1443 if (!old_value)
1444 info->rs485.flags &= ~(SER_RS485_ENABLED);
1445 return count;
1446}
1447
1448#ifdef CONFIG_ETRAX_FAST_TIMER
1449/* Timer function to toggle RTS when using FAST_TIMER */
1450static void rs485_toggle_rts_timer_function(unsigned long data)
1451{
1452 struct e100_serial *info = (struct e100_serial *)data;
1453
1454 fast_timers_rs485[info->line].function = NULL;
1455 e100_rts(info, (info->rs485.flags & SER_RS485_RTS_AFTER_SEND));
1456#if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
1457 e100_enable_rx(info);
1458 e100_enable_rx_irq(info);
1459#endif
1460}
1461#endif
1462#endif /* CONFIG_ETRAX_RS485 */
1463
1464/*
1465 * ------------------------------------------------------------
1466 * rs_stop() and rs_start()
1467 *
1468 * This routines are called before setting or resetting tty->stopped.
1469 * They enable or disable transmitter using the XOFF registers, as necessary.
1470 * ------------------------------------------------------------
1471 */
1472
1473static void
1474rs_stop(struct tty_struct *tty)
1475{
1476 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
1477 if (info) {
1478 unsigned long flags;
1479 unsigned long xoff;
1480
1481 local_irq_save(flags);
1482 DFLOW(DEBUG_LOG(info->line, "XOFF rs_stop xmit %i\n",
1483 CIRC_CNT(info->xmit.head,
1484 info->xmit.tail,SERIAL_XMIT_SIZE)));
1485
1486 xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char,
1487 STOP_CHAR(info->port.tty));
1488 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, stop);
1489 if (tty->termios->c_iflag & IXON ) {
1490 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable);
1491 }
1492
1493 *((unsigned long *)&info->ioport[REG_XOFF]) = xoff;
1494 local_irq_restore(flags);
1495 }
1496}
1497
1498static void
1499rs_start(struct tty_struct *tty)
1500{
1501 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
1502 if (info) {
1503 unsigned long flags;
1504 unsigned long xoff;
1505
1506 local_irq_save(flags);
1507 DFLOW(DEBUG_LOG(info->line, "XOFF rs_start xmit %i\n",
1508 CIRC_CNT(info->xmit.head,
1509 info->xmit.tail,SERIAL_XMIT_SIZE)));
1510 xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char, STOP_CHAR(tty));
1511 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, enable);
1512 if (tty->termios->c_iflag & IXON ) {
1513 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable);
1514 }
1515
1516 *((unsigned long *)&info->ioport[REG_XOFF]) = xoff;
1517 if (!info->uses_dma_out &&
1518 info->xmit.head != info->xmit.tail && info->xmit.buf)
1519 e100_enable_serial_tx_ready_irq(info);
1520
1521 local_irq_restore(flags);
1522 }
1523}
1524
1525/*
1526 * ----------------------------------------------------------------------
1527 *
1528 * Here starts the interrupt handling routines. All of the following
1529 * subroutines are declared as inline and are folded into
1530 * rs_interrupt(). They were separated out for readability's sake.
1531 *
1532 * Note: rs_interrupt() is a "fast" interrupt, which means that it
1533 * runs with interrupts turned off. People who may want to modify
1534 * rs_interrupt() should try to keep the interrupt handler as fast as
1535 * possible. After you are done making modifications, it is not a bad
1536 * idea to do:
1537 *
1538 * gcc -S -DKERNEL -Wall -Wstrict-prototypes -O6 -fomit-frame-pointer serial.c
1539 *
1540 * and look at the resulting assemble code in serial.s.
1541 *
1542 * - Ted Ts'o (tytso@mit.edu), 7-Mar-93
1543 * -----------------------------------------------------------------------
1544 */
1545
1546/*
1547 * This routine is used by the interrupt handler to schedule
1548 * processing in the software interrupt portion of the driver.
1549 */
1550static void rs_sched_event(struct e100_serial *info, int event)
1551{
1552 if (info->event & (1 << event))
1553 return;
1554 info->event |= 1 << event;
1555 schedule_work(&info->work);
1556}
1557
1558/* The output DMA channel is free - use it to send as many chars as possible
1559 * NOTES:
1560 * We don't pay attention to info->x_char, which means if the TTY wants to
1561 * use XON/XOFF it will set info->x_char but we won't send any X char!
1562 *
1563 * To implement this, we'd just start a DMA send of 1 byte pointing at a
1564 * buffer containing the X char, and skip updating xmit. We'd also have to
1565 * check if the last sent char was the X char when we enter this function
1566 * the next time, to avoid updating xmit with the sent X value.
1567 */
1568
1569static void
1570transmit_chars_dma(struct e100_serial *info)
1571{
1572 unsigned int c, sentl;
1573 struct etrax_dma_descr *descr;
1574
1575#ifdef CONFIG_SVINTO_SIM
1576 /* This will output too little if tail is not 0 always since
1577 * we don't reloop to send the other part. Anyway this SHOULD be a
1578 * no-op - transmit_chars_dma would never really be called during sim
1579 * since rs_write does not write into the xmit buffer then.
1580 */
1581 if (info->xmit.tail)
1582 printk("Error in serial.c:transmit_chars-dma(), tail!=0\n");
1583 if (info->xmit.head != info->xmit.tail) {
1584 SIMCOUT(info->xmit.buf + info->xmit.tail,
1585 CIRC_CNT(info->xmit.head,
1586 info->xmit.tail,
1587 SERIAL_XMIT_SIZE));
1588 info->xmit.head = info->xmit.tail; /* move back head */
1589 info->tr_running = 0;
1590 }
1591 return;
1592#endif
1593 /* acknowledge both dma_descr and dma_eop irq in R_DMA_CHx_CLR_INTR */
1594 *info->oclrintradr =
1595 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
1596 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
1597
1598#ifdef SERIAL_DEBUG_INTR
1599 if (info->line == SERIAL_DEBUG_LINE)
1600 printk("tc\n");
1601#endif
1602 if (!info->tr_running) {
1603 /* weirdo... we shouldn't get here! */
1604 printk(KERN_WARNING "Achtung: transmit_chars_dma with !tr_running\n");
1605 return;
1606 }
1607
1608 descr = &info->tr_descr;
1609
1610 /* first get the amount of bytes sent during the last DMA transfer,
1611 and update xmit accordingly */
1612
1613 /* if the stop bit was not set, all data has been sent */
1614 if (!(descr->status & d_stop)) {
1615 sentl = descr->sw_len;
1616 } else
1617 /* otherwise we find the amount of data sent here */
1618 sentl = descr->hw_len;
1619
1620 DFLOW(DEBUG_LOG(info->line, "TX %i done\n", sentl));
1621
1622 /* update stats */
1623 info->icount.tx += sentl;
1624
1625 /* update xmit buffer */
1626 info->xmit.tail = (info->xmit.tail + sentl) & (SERIAL_XMIT_SIZE - 1);
1627
1628 /* if there is only a few chars left in the buf, wake up the blocked
1629 write if any */
1630 if (CIRC_CNT(info->xmit.head,
1631 info->xmit.tail,
1632 SERIAL_XMIT_SIZE) < WAKEUP_CHARS)
1633 rs_sched_event(info, RS_EVENT_WRITE_WAKEUP);
1634
1635 /* find out the largest amount of consecutive bytes we want to send now */
1636
1637 c = CIRC_CNT_TO_END(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
1638
1639 /* Don't send all in one DMA transfer - divide it so we wake up
1640 * application before all is sent
1641 */
1642
1643 if (c >= 4*WAKEUP_CHARS)
1644 c = c/2;
1645
1646 if (c <= 0) {
1647 /* our job here is done, don't schedule any new DMA transfer */
1648 info->tr_running = 0;
1649
1650#if defined(CONFIG_ETRAX_RS485) && defined(CONFIG_ETRAX_FAST_TIMER)
1651 if (info->rs485.flags & SER_RS485_ENABLED) {
1652 /* Set a short timer to toggle RTS */
1653 start_one_shot_timer(&fast_timers_rs485[info->line],
1654 rs485_toggle_rts_timer_function,
1655 (unsigned long)info,
1656 info->char_time_usec*2,
1657 "RS-485");
1658 }
1659#endif /* RS485 */
1660 return;
1661 }
1662
1663 /* ok we can schedule a dma send of c chars starting at info->xmit.tail */
1664 /* set up the descriptor correctly for output */
1665 DFLOW(DEBUG_LOG(info->line, "TX %i\n", c));
1666 descr->ctrl = d_int | d_eol | d_wait; /* Wait needed for tty_wait_until_sent() */
1667 descr->sw_len = c;
1668 descr->buf = virt_to_phys(info->xmit.buf + info->xmit.tail);
1669 descr->status = 0;
1670
1671 *info->ofirstadr = virt_to_phys(descr); /* write to R_DMAx_FIRST */
1672 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, start);
1673
1674 /* DMA is now running (hopefully) */
1675} /* transmit_chars_dma */
1676
1677static void
1678start_transmit(struct e100_serial *info)
1679{
1680#if 0
1681 if (info->line == SERIAL_DEBUG_LINE)
1682 printk("x\n");
1683#endif
1684
1685 info->tr_descr.sw_len = 0;
1686 info->tr_descr.hw_len = 0;
1687 info->tr_descr.status = 0;
1688 info->tr_running = 1;
1689 if (info->uses_dma_out)
1690 transmit_chars_dma(info);
1691 else
1692 e100_enable_serial_tx_ready_irq(info);
1693} /* start_transmit */
1694
1695#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
1696static int serial_fast_timer_started = 0;
1697static int serial_fast_timer_expired = 0;
1698static void flush_timeout_function(unsigned long data);
1699#define START_FLUSH_FAST_TIMER_TIME(info, string, usec) {\
1700 unsigned long timer_flags; \
1701 local_irq_save(timer_flags); \
1702 if (fast_timers[info->line].function == NULL) { \
1703 serial_fast_timer_started++; \
1704 TIMERD(DEBUG_LOG(info->line, "start_timer %i ", info->line)); \
1705 TIMERD(DEBUG_LOG(info->line, "num started: %i\n", serial_fast_timer_started)); \
1706 start_one_shot_timer(&fast_timers[info->line], \
1707 flush_timeout_function, \
1708 (unsigned long)info, \
1709 (usec), \
1710 string); \
1711 } \
1712 else { \
1713 TIMERD(DEBUG_LOG(info->line, "timer %i already running\n", info->line)); \
1714 } \
1715 local_irq_restore(timer_flags); \
1716}
1717#define START_FLUSH_FAST_TIMER(info, string) START_FLUSH_FAST_TIMER_TIME(info, string, info->flush_time_usec)
1718
1719#else
1720#define START_FLUSH_FAST_TIMER_TIME(info, string, usec)
1721#define START_FLUSH_FAST_TIMER(info, string)
1722#endif
1723
1724static struct etrax_recv_buffer *
1725alloc_recv_buffer(unsigned int size)
1726{
1727 struct etrax_recv_buffer *buffer;
1728
1729 if (!(buffer = kmalloc(sizeof *buffer + size, GFP_ATOMIC)))
1730 return NULL;
1731
1732 buffer->next = NULL;
1733 buffer->length = 0;
1734 buffer->error = TTY_NORMAL;
1735
1736 return buffer;
1737}
1738
1739static void
1740append_recv_buffer(struct e100_serial *info, struct etrax_recv_buffer *buffer)
1741{
1742 unsigned long flags;
1743
1744 local_irq_save(flags);
1745
1746 if (!info->first_recv_buffer)
1747 info->first_recv_buffer = buffer;
1748 else
1749 info->last_recv_buffer->next = buffer;
1750
1751 info->last_recv_buffer = buffer;
1752
1753 info->recv_cnt += buffer->length;
1754 if (info->recv_cnt > info->max_recv_cnt)
1755 info->max_recv_cnt = info->recv_cnt;
1756
1757 local_irq_restore(flags);
1758}
1759
1760static int
1761add_char_and_flag(struct e100_serial *info, unsigned char data, unsigned char flag)
1762{
1763 struct etrax_recv_buffer *buffer;
1764 if (info->uses_dma_in) {
1765 if (!(buffer = alloc_recv_buffer(4)))
1766 return 0;
1767
1768 buffer->length = 1;
1769 buffer->error = flag;
1770 buffer->buffer[0] = data;
1771
1772 append_recv_buffer(info, buffer);
1773
1774 info->icount.rx++;
1775 } else {
1776 struct tty_struct *tty = info->port.tty;
1777 tty_insert_flip_char(tty, data, flag);
1778 info->icount.rx++;
1779 }
1780
1781 return 1;
1782}
1783
1784static unsigned int handle_descr_data(struct e100_serial *info,
1785 struct etrax_dma_descr *descr,
1786 unsigned int recvl)
1787{
1788 struct etrax_recv_buffer *buffer = phys_to_virt(descr->buf) - sizeof *buffer;
1789
1790 if (info->recv_cnt + recvl > 65536) {
1791 printk(KERN_CRIT
1792 "%s: Too much pending incoming serial data! Dropping %u bytes.\n", __func__, recvl);
1793 return 0;
1794 }
1795
1796 buffer->length = recvl;
1797
1798 if (info->errorcode == ERRCODE_SET_BREAK)
1799 buffer->error = TTY_BREAK;
1800 info->errorcode = 0;
1801
1802 append_recv_buffer(info, buffer);
1803
1804 if (!(buffer = alloc_recv_buffer(SERIAL_DESCR_BUF_SIZE)))
1805 panic("%s: Failed to allocate memory for receive buffer!\n", __func__);
1806
1807 descr->buf = virt_to_phys(buffer->buffer);
1808
1809 return recvl;
1810}
1811
1812static unsigned int handle_all_descr_data(struct e100_serial *info)
1813{
1814 struct etrax_dma_descr *descr;
1815 unsigned int recvl;
1816 unsigned int ret = 0;
1817
1818 while (1)
1819 {
1820 descr = &info->rec_descr[info->cur_rec_descr];
1821
1822 if (descr == phys_to_virt(*info->idescradr))
1823 break;
1824
1825 if (++info->cur_rec_descr == SERIAL_RECV_DESCRIPTORS)
1826 info->cur_rec_descr = 0;
1827
1828 /* find out how many bytes were read */
1829
1830 /* if the eop bit was not set, all data has been received */
1831 if (!(descr->status & d_eop)) {
1832 recvl = descr->sw_len;
1833 } else {
1834 /* otherwise we find the amount of data received here */
1835 recvl = descr->hw_len;
1836 }
1837
1838 /* Reset the status information */
1839 descr->status = 0;
1840
1841 DFLOW( DEBUG_LOG(info->line, "RX %lu\n", recvl);
1842 if (info->port.tty->stopped) {
1843 unsigned char *buf = phys_to_virt(descr->buf);
1844 DEBUG_LOG(info->line, "rx 0x%02X\n", buf[0]);
1845 DEBUG_LOG(info->line, "rx 0x%02X\n", buf[1]);
1846 DEBUG_LOG(info->line, "rx 0x%02X\n", buf[2]);
1847 }
1848 );
1849
1850 /* update stats */
1851 info->icount.rx += recvl;
1852
1853 ret += handle_descr_data(info, descr, recvl);
1854 }
1855
1856 return ret;
1857}
1858
1859static void receive_chars_dma(struct e100_serial *info)
1860{
1861 struct tty_struct *tty;
1862 unsigned char rstat;
1863
1864#ifdef CONFIG_SVINTO_SIM
1865 /* No receive in the simulator. Will probably be when the rest of
1866 * the serial interface works, and this piece will just be removed.
1867 */
1868 return;
1869#endif
1870
1871 /* Acknowledge both dma_descr and dma_eop irq in R_DMA_CHx_CLR_INTR */
1872 *info->iclrintradr =
1873 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
1874 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
1875
1876 tty = info->port.tty;
1877 if (!tty) /* Something wrong... */
1878 return;
1879
1880#ifdef SERIAL_HANDLE_EARLY_ERRORS
1881 if (info->uses_dma_in)
1882 e100_enable_serial_data_irq(info);
1883#endif
1884
1885 if (info->errorcode == ERRCODE_INSERT_BREAK)
1886 add_char_and_flag(info, '\0', TTY_BREAK);
1887
1888 handle_all_descr_data(info);
1889
1890 /* Read the status register to detect errors */
1891 rstat = info->ioport[REG_STATUS];
1892 if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect) ) {
1893 DFLOW(DEBUG_LOG(info->line, "XOFF detect stat %x\n", rstat));
1894 }
1895
1896 if (rstat & SER_ERROR_MASK) {
1897 /* If we got an error, we must reset it by reading the
1898 * data_in field
1899 */
1900 unsigned char data = info->ioport[REG_DATA];
1901
1902 PROCSTAT(ser_stat[info->line].errors_cnt++);
1903 DEBUG_LOG(info->line, "#dERR: s d 0x%04X\n",
1904 ((rstat & SER_ERROR_MASK) << 8) | data);
1905
1906 if (rstat & SER_PAR_ERR_MASK)
1907 add_char_and_flag(info, data, TTY_PARITY);
1908 else if (rstat & SER_OVERRUN_MASK)
1909 add_char_and_flag(info, data, TTY_OVERRUN);
1910 else if (rstat & SER_FRAMING_ERR_MASK)
1911 add_char_and_flag(info, data, TTY_FRAME);
1912 }
1913
1914 START_FLUSH_FAST_TIMER(info, "receive_chars");
1915
1916 /* Restart the receiving DMA */
1917 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, restart);
1918}
1919
1920static int start_recv_dma(struct e100_serial *info)
1921{
1922 struct etrax_dma_descr *descr = info->rec_descr;
1923 struct etrax_recv_buffer *buffer;
1924 int i;
1925
1926 /* Set up the receiving descriptors */
1927 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++) {
1928 if (!(buffer = alloc_recv_buffer(SERIAL_DESCR_BUF_SIZE)))
1929 panic("%s: Failed to allocate memory for receive buffer!\n", __func__);
1930
1931 descr[i].ctrl = d_int;
1932 descr[i].buf = virt_to_phys(buffer->buffer);
1933 descr[i].sw_len = SERIAL_DESCR_BUF_SIZE;
1934 descr[i].hw_len = 0;
1935 descr[i].status = 0;
1936 descr[i].next = virt_to_phys(&descr[i+1]);
1937 }
1938
1939 /* Link the last descriptor to the first */
1940 descr[i-1].next = virt_to_phys(&descr[0]);
1941
1942 /* Start with the first descriptor in the list */
1943 info->cur_rec_descr = 0;
1944
1945 /* Start the DMA */
1946 *info->ifirstadr = virt_to_phys(&descr[info->cur_rec_descr]);
1947 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, start);
1948
1949 /* Input DMA should be running now */
1950 return 1;
1951}
1952
1953static void
1954start_receive(struct e100_serial *info)
1955{
1956#ifdef CONFIG_SVINTO_SIM
1957 /* No receive in the simulator. Will probably be when the rest of
1958 * the serial interface works, and this piece will just be removed.
1959 */
1960 return;
1961#endif
1962 if (info->uses_dma_in) {
1963 /* reset the input dma channel to be sure it works */
1964
1965 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
1966 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->icmdadr) ==
1967 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset));
1968
1969 start_recv_dma(info);
1970 }
1971}
1972
1973
1974/* the bits in the MASK2 register are laid out like this:
1975 DMAI_EOP DMAI_DESCR DMAO_EOP DMAO_DESCR
1976 where I is the input channel and O is the output channel for the port.
1977 info->irq is the bit number for the DMAO_DESCR so to check the others we
1978 shift info->irq to the left.
1979*/
1980
1981/* dma output channel interrupt handler
1982 this interrupt is called from DMA2(ser2), DMA4(ser3), DMA6(ser0) or
1983 DMA8(ser1) when they have finished a descriptor with the intr flag set.
1984*/
1985
1986static irqreturn_t
1987tr_interrupt(int irq, void *dev_id)
1988{
1989 struct e100_serial *info;
1990 unsigned long ireg;
1991 int i;
1992 int handled = 0;
1993
1994#ifdef CONFIG_SVINTO_SIM
1995 /* No receive in the simulator. Will probably be when the rest of
1996 * the serial interface works, and this piece will just be removed.
1997 */
1998 {
1999 const char *s = "What? tr_interrupt in simulator??\n";
2000 SIMCOUT(s,strlen(s));
2001 }
2002 return IRQ_HANDLED;
2003#endif
2004
2005 /* find out the line that caused this irq and get it from rs_table */
2006
2007 ireg = *R_IRQ_MASK2_RD; /* get the active irq bits for the dma channels */
2008
2009 for (i = 0; i < NR_PORTS; i++) {
2010 info = rs_table + i;
2011 if (!info->enabled || !info->uses_dma_out)
2012 continue;
2013 /* check for dma_descr (don't need to check for dma_eop in output dma for serial */
2014 if (ireg & info->irq) {
2015 handled = 1;
2016 /* we can send a new dma bunch. make it so. */
2017 DINTR2(DEBUG_LOG(info->line, "tr_interrupt %i\n", i));
2018 /* Read jiffies_usec first,
2019 * we want this time to be as late as possible
2020 */
2021 PROCSTAT(ser_stat[info->line].tx_dma_ints++);
2022 info->last_tx_active_usec = GET_JIFFIES_USEC();
2023 info->last_tx_active = jiffies;
2024 transmit_chars_dma(info);
2025 }
2026
2027 /* FIXME: here we should really check for a change in the
2028 status lines and if so call status_handle(info) */
2029 }
2030 return IRQ_RETVAL(handled);
2031} /* tr_interrupt */
2032
2033/* dma input channel interrupt handler */
2034
2035static irqreturn_t
2036rec_interrupt(int irq, void *dev_id)
2037{
2038 struct e100_serial *info;
2039 unsigned long ireg;
2040 int i;
2041 int handled = 0;
2042
2043#ifdef CONFIG_SVINTO_SIM
2044 /* No receive in the simulator. Will probably be when the rest of
2045 * the serial interface works, and this piece will just be removed.
2046 */
2047 {
2048 const char *s = "What? rec_interrupt in simulator??\n";
2049 SIMCOUT(s,strlen(s));
2050 }
2051 return IRQ_HANDLED;
2052#endif
2053
2054 /* find out the line that caused this irq and get it from rs_table */
2055
2056 ireg = *R_IRQ_MASK2_RD; /* get the active irq bits for the dma channels */
2057
2058 for (i = 0; i < NR_PORTS; i++) {
2059 info = rs_table + i;
2060 if (!info->enabled || !info->uses_dma_in)
2061 continue;
2062 /* check for both dma_eop and dma_descr for the input dma channel */
2063 if (ireg & ((info->irq << 2) | (info->irq << 3))) {
2064 handled = 1;
2065 /* we have received something */
2066 receive_chars_dma(info);
2067 }
2068
2069 /* FIXME: here we should really check for a change in the
2070 status lines and if so call status_handle(info) */
2071 }
2072 return IRQ_RETVAL(handled);
2073} /* rec_interrupt */
2074
2075static int force_eop_if_needed(struct e100_serial *info)
2076{
2077 /* We check data_avail bit to determine if data has
2078 * arrived since last time
2079 */
2080 unsigned char rstat = info->ioport[REG_STATUS];
2081
2082 /* error or datavail? */
2083 if (rstat & SER_ERROR_MASK) {
2084 /* Some error has occurred. If there has been valid data, an
2085 * EOP interrupt will be made automatically. If no data, the
2086 * normal ser_interrupt should be enabled and handle it.
2087 * So do nothing!
2088 */
2089 DEBUG_LOG(info->line, "timeout err: rstat 0x%03X\n",
2090 rstat | (info->line << 8));
2091 return 0;
2092 }
2093
2094 if (rstat & SER_DATA_AVAIL_MASK) {
2095 /* Ok data, no error, count it */
2096 TIMERD(DEBUG_LOG(info->line, "timeout: rstat 0x%03X\n",
2097 rstat | (info->line << 8)));
2098 /* Read data to clear status flags */
2099 (void)info->ioport[REG_DATA];
2100
2101 info->forced_eop = 0;
2102 START_FLUSH_FAST_TIMER(info, "magic");
2103 return 0;
2104 }
2105
2106 /* hit the timeout, force an EOP for the input
2107 * dma channel if we haven't already
2108 */
2109 if (!info->forced_eop) {
2110 info->forced_eop = 1;
2111 PROCSTAT(ser_stat[info->line].timeout_flush_cnt++);
2112 TIMERD(DEBUG_LOG(info->line, "timeout EOP %i\n", info->line));
2113 FORCE_EOP(info);
2114 }
2115
2116 return 1;
2117}
2118
2119static void flush_to_flip_buffer(struct e100_serial *info)
2120{
2121 struct tty_struct *tty;
2122 struct etrax_recv_buffer *buffer;
2123 unsigned long flags;
2124
2125 local_irq_save(flags);
2126 tty = info->port.tty;
2127
2128 if (!tty) {
2129 local_irq_restore(flags);
2130 return;
2131 }
2132
2133 while ((buffer = info->first_recv_buffer) != NULL) {
2134 unsigned int count = buffer->length;
2135
2136 tty_insert_flip_string(tty, buffer->buffer, count);
2137 info->recv_cnt -= count;
2138
2139 if (count == buffer->length) {
2140 info->first_recv_buffer = buffer->next;
2141 kfree(buffer);
2142 } else {
2143 buffer->length -= count;
2144 memmove(buffer->buffer, buffer->buffer + count, buffer->length);
2145 buffer->error = TTY_NORMAL;
2146 }
2147 }
2148
2149 if (!info->first_recv_buffer)
2150 info->last_recv_buffer = NULL;
2151
2152 local_irq_restore(flags);
2153
2154 /* This includes a check for low-latency */
2155 tty_flip_buffer_push(tty);
2156}
2157
2158static void check_flush_timeout(struct e100_serial *info)
2159{
2160 /* Flip what we've got (if we can) */
2161 flush_to_flip_buffer(info);
2162
2163 /* We might need to flip later, but not to fast
2164 * since the system is busy processing input... */
2165 if (info->first_recv_buffer)
2166 START_FLUSH_FAST_TIMER_TIME(info, "flip", 2000);
2167
2168 /* Force eop last, since data might have come while we're processing
2169 * and if we started the slow timer above, we won't start a fast
2170 * below.
2171 */
2172 force_eop_if_needed(info);
2173}
2174
2175#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
2176static void flush_timeout_function(unsigned long data)
2177{
2178 struct e100_serial *info = (struct e100_serial *)data;
2179
2180 fast_timers[info->line].function = NULL;
2181 serial_fast_timer_expired++;
2182 TIMERD(DEBUG_LOG(info->line, "flush_timout %i ", info->line));
2183 TIMERD(DEBUG_LOG(info->line, "num expired: %i\n", serial_fast_timer_expired));
2184 check_flush_timeout(info);
2185}
2186
2187#else
2188
2189/* dma fifo/buffer timeout handler
2190 forces an end-of-packet for the dma input channel if no chars
2191 have been received for CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS/100 s.
2192*/
2193
2194static struct timer_list flush_timer;
2195
2196static void
2197timed_flush_handler(unsigned long ptr)
2198{
2199 struct e100_serial *info;
2200 int i;
2201
2202#ifdef CONFIG_SVINTO_SIM
2203 return;
2204#endif
2205
2206 for (i = 0; i < NR_PORTS; i++) {
2207 info = rs_table + i;
2208 if (info->uses_dma_in)
2209 check_flush_timeout(info);
2210 }
2211
2212 /* restart flush timer */
2213 mod_timer(&flush_timer, jiffies + CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS);
2214}
2215#endif
2216
2217#ifdef SERIAL_HANDLE_EARLY_ERRORS
2218
2219/* If there is an error (ie break) when the DMA is running and
2220 * there are no bytes in the fifo the DMA is stopped and we get no
2221 * eop interrupt. Thus we have to monitor the first bytes on a DMA
2222 * transfer, and if it is without error we can turn the serial
2223 * interrupts off.
2224 */
2225
2226/*
2227BREAK handling on ETRAX 100:
2228ETRAX will generate interrupt although there is no stop bit between the
2229characters.
2230
2231Depending on how long the break sequence is, the end of the breaksequence
2232will look differently:
2233| indicates start/end of a character.
2234
2235B= Break character (0x00) with framing error.
2236E= Error byte with parity error received after B characters.
2237F= "Faked" valid byte received immediately after B characters.
2238V= Valid byte
2239
22401.
2241 B BL ___________________________ V
2242.._|__________|__________| |valid data |
2243
2244Multiple frame errors with data == 0x00 (B),
2245the timing matches up "perfectly" so no extra ending char is detected.
2246The RXD pin is 1 in the last interrupt, in that case
2247we set info->errorcode = ERRCODE_INSERT_BREAK, but we can't really
2248know if another byte will come and this really is case 2. below
2249(e.g F=0xFF or 0xFE)
2250If RXD pin is 0 we can expect another character (see 2. below).
2251
2252
22532.
2254
2255 B B E or F__________________..__ V
2256.._|__________|__________|______ | |valid data
2257 "valid" or
2258 parity error
2259
2260Multiple frame errors with data == 0x00 (B),
2261but the part of the break trigs is interpreted as a start bit (and possibly
2262some 0 bits followed by a number of 1 bits and a stop bit).
2263Depending on parity settings etc. this last character can be either
2264a fake "valid" char (F) or have a parity error (E).
2265
2266If the character is valid it will be put in the buffer,
2267we set info->errorcode = ERRCODE_SET_BREAK so the receive interrupt
2268will set the flags so the tty will handle it,
2269if it's an error byte it will not be put in the buffer
2270and we set info->errorcode = ERRCODE_INSERT_BREAK.
2271
2272To distinguish a V byte in 1. from an F byte in 2. we keep a timestamp
2273of the last faulty char (B) and compares it with the current time:
2274If the time elapsed time is less then 2*char_time_usec we will assume
2275it's a faked F char and not a Valid char and set
2276info->errorcode = ERRCODE_SET_BREAK.
2277
2278Flaws in the above solution:
2279~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2280We use the timer to distinguish a F character from a V character,
2281if a V character is to close after the break we might make the wrong decision.
2282
2283TODO: The break will be delayed until an F or V character is received.
2284
2285*/
2286
2287static
2288struct e100_serial * handle_ser_rx_interrupt_no_dma(struct e100_serial *info)
2289{
2290 unsigned long data_read;
2291 struct tty_struct *tty = info->port.tty;
2292
2293 if (!tty) {
2294 printk("!NO TTY!\n");
2295 return info;
2296 }
2297
2298 /* Read data and status at the same time */
2299 data_read = *((unsigned long *)&info->ioport[REG_DATA_STATUS32]);
2300more_data:
2301 if (data_read & IO_MASK(R_SERIAL0_READ, xoff_detect) ) {
2302 DFLOW(DEBUG_LOG(info->line, "XOFF detect\n", 0));
2303 }
2304 DINTR2(DEBUG_LOG(info->line, "ser_rx %c\n", IO_EXTRACT(R_SERIAL0_READ, data_in, data_read)));
2305
2306 if (data_read & ( IO_MASK(R_SERIAL0_READ, framing_err) |
2307 IO_MASK(R_SERIAL0_READ, par_err) |
2308 IO_MASK(R_SERIAL0_READ, overrun) )) {
2309 /* An error */
2310 info->last_rx_active_usec = GET_JIFFIES_USEC();
2311 info->last_rx_active = jiffies;
2312 DINTR1(DEBUG_LOG(info->line, "ser_rx err stat_data %04X\n", data_read));
2313 DLOG_INT_TRIG(
2314 if (!log_int_trig1_pos) {
2315 log_int_trig1_pos = log_int_pos;
2316 log_int(rdpc(), 0, 0);
2317 }
2318 );
2319
2320
2321 if ( ((data_read & IO_MASK(R_SERIAL0_READ, data_in)) == 0) &&
2322 (data_read & IO_MASK(R_SERIAL0_READ, framing_err)) ) {
2323 /* Most likely a break, but we get interrupts over and
2324 * over again.
2325 */
2326
2327 if (!info->break_detected_cnt) {
2328 DEBUG_LOG(info->line, "#BRK start\n", 0);
2329 }
2330 if (data_read & IO_MASK(R_SERIAL0_READ, rxd)) {
2331 /* The RX pin is high now, so the break
2332 * must be over, but....
2333 * we can't really know if we will get another
2334 * last byte ending the break or not.
2335 * And we don't know if the byte (if any) will
2336 * have an error or look valid.
2337 */
2338 DEBUG_LOG(info->line, "# BL BRK\n", 0);
2339 info->errorcode = ERRCODE_INSERT_BREAK;
2340 }
2341 info->break_detected_cnt++;
2342 } else {
2343 /* The error does not look like a break, but could be
2344 * the end of one
2345 */
2346 if (info->break_detected_cnt) {
2347 DEBUG_LOG(info->line, "EBRK %i\n", info->break_detected_cnt);
2348 info->errorcode = ERRCODE_INSERT_BREAK;
2349 } else {
2350 unsigned char data = IO_EXTRACT(R_SERIAL0_READ,
2351 data_in, data_read);
2352 char flag = TTY_NORMAL;
2353 if (info->errorcode == ERRCODE_INSERT_BREAK) {
2354 struct tty_struct *tty = info->port.tty;
2355 tty_insert_flip_char(tty, 0, flag);
2356 info->icount.rx++;
2357 }
2358
2359 if (data_read & IO_MASK(R_SERIAL0_READ, par_err)) {
2360 info->icount.parity++;
2361 flag = TTY_PARITY;
2362 } else if (data_read & IO_MASK(R_SERIAL0_READ, overrun)) {
2363 info->icount.overrun++;
2364 flag = TTY_OVERRUN;
2365 } else if (data_read & IO_MASK(R_SERIAL0_READ, framing_err)) {
2366 info->icount.frame++;
2367 flag = TTY_FRAME;
2368 }
2369 tty_insert_flip_char(tty, data, flag);
2370 info->errorcode = 0;
2371 }
2372 info->break_detected_cnt = 0;
2373 }
2374 } else if (data_read & IO_MASK(R_SERIAL0_READ, data_avail)) {
2375 /* No error */
2376 DLOG_INT_TRIG(
2377 if (!log_int_trig1_pos) {
2378 if (log_int_pos >= log_int_size) {
2379 log_int_pos = 0;
2380 }
2381 log_int_trig0_pos = log_int_pos;
2382 log_int(rdpc(), 0, 0);
2383 }
2384 );
2385 tty_insert_flip_char(tty,
2386 IO_EXTRACT(R_SERIAL0_READ, data_in, data_read),
2387 TTY_NORMAL);
2388 } else {
2389 DEBUG_LOG(info->line, "ser_rx int but no data_avail %08lX\n", data_read);
2390 }
2391
2392
2393 info->icount.rx++;
2394 data_read = *((unsigned long *)&info->ioport[REG_DATA_STATUS32]);
2395 if (data_read & IO_MASK(R_SERIAL0_READ, data_avail)) {
2396 DEBUG_LOG(info->line, "ser_rx %c in loop\n", IO_EXTRACT(R_SERIAL0_READ, data_in, data_read));
2397 goto more_data;
2398 }
2399
2400 tty_flip_buffer_push(info->port.tty);
2401 return info;
2402}
2403
2404static struct e100_serial* handle_ser_rx_interrupt(struct e100_serial *info)
2405{
2406 unsigned char rstat;
2407
2408#ifdef SERIAL_DEBUG_INTR
2409 printk("Interrupt from serport %d\n", i);
2410#endif
2411/* DEBUG_LOG(info->line, "ser_interrupt stat %03X\n", rstat | (i << 8)); */
2412 if (!info->uses_dma_in) {
2413 return handle_ser_rx_interrupt_no_dma(info);
2414 }
2415 /* DMA is used */
2416 rstat = info->ioport[REG_STATUS];
2417 if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect) ) {
2418 DFLOW(DEBUG_LOG(info->line, "XOFF detect\n", 0));
2419 }
2420
2421 if (rstat & SER_ERROR_MASK) {
2422 unsigned char data;
2423
2424 info->last_rx_active_usec = GET_JIFFIES_USEC();
2425 info->last_rx_active = jiffies;
2426 /* If we got an error, we must reset it by reading the
2427 * data_in field
2428 */
2429 data = info->ioport[REG_DATA];
2430 DINTR1(DEBUG_LOG(info->line, "ser_rx! %c\n", data));
2431 DINTR1(DEBUG_LOG(info->line, "ser_rx err stat %02X\n", rstat));
2432 if (!data && (rstat & SER_FRAMING_ERR_MASK)) {
2433 /* Most likely a break, but we get interrupts over and
2434 * over again.
2435 */
2436
2437 if (!info->break_detected_cnt) {
2438 DEBUG_LOG(info->line, "#BRK start\n", 0);
2439 }
2440 if (rstat & SER_RXD_MASK) {
2441 /* The RX pin is high now, so the break
2442 * must be over, but....
2443 * we can't really know if we will get another
2444 * last byte ending the break or not.
2445 * And we don't know if the byte (if any) will
2446 * have an error or look valid.
2447 */
2448 DEBUG_LOG(info->line, "# BL BRK\n", 0);
2449 info->errorcode = ERRCODE_INSERT_BREAK;
2450 }
2451 info->break_detected_cnt++;
2452 } else {
2453 /* The error does not look like a break, but could be
2454 * the end of one
2455 */
2456 if (info->break_detected_cnt) {
2457 DEBUG_LOG(info->line, "EBRK %i\n", info->break_detected_cnt);
2458 info->errorcode = ERRCODE_INSERT_BREAK;
2459 } else {
2460 if (info->errorcode == ERRCODE_INSERT_BREAK) {
2461 info->icount.brk++;
2462 add_char_and_flag(info, '\0', TTY_BREAK);
2463 }
2464
2465 if (rstat & SER_PAR_ERR_MASK) {
2466 info->icount.parity++;
2467 add_char_and_flag(info, data, TTY_PARITY);
2468 } else if (rstat & SER_OVERRUN_MASK) {
2469 info->icount.overrun++;
2470 add_char_and_flag(info, data, TTY_OVERRUN);
2471 } else if (rstat & SER_FRAMING_ERR_MASK) {
2472 info->icount.frame++;
2473 add_char_and_flag(info, data, TTY_FRAME);
2474 }
2475
2476 info->errorcode = 0;
2477 }
2478 info->break_detected_cnt = 0;
2479 DEBUG_LOG(info->line, "#iERR s d %04X\n",
2480 ((rstat & SER_ERROR_MASK) << 8) | data);
2481 }
2482 PROCSTAT(ser_stat[info->line].early_errors_cnt++);
2483 } else { /* It was a valid byte, now let the DMA do the rest */
2484 unsigned long curr_time_u = GET_JIFFIES_USEC();
2485 unsigned long curr_time = jiffies;
2486
2487 if (info->break_detected_cnt) {
2488 /* Detect if this character is a new valid char or the
2489 * last char in a break sequence: If LSBits are 0 and
2490 * MSBits are high AND the time is close to the
2491 * previous interrupt we should discard it.
2492 */
2493 long elapsed_usec =
2494 (curr_time - info->last_rx_active) * (1000000/HZ) +
2495 curr_time_u - info->last_rx_active_usec;
2496 if (elapsed_usec < 2*info->char_time_usec) {
2497 DEBUG_LOG(info->line, "FBRK %i\n", info->line);
2498 /* Report as BREAK (error) and let
2499 * receive_chars_dma() handle it
2500 */
2501 info->errorcode = ERRCODE_SET_BREAK;
2502 } else {
2503 DEBUG_LOG(info->line, "Not end of BRK (V)%i\n", info->line);
2504 }
2505 DEBUG_LOG(info->line, "num brk %i\n", info->break_detected_cnt);
2506 }
2507
2508#ifdef SERIAL_DEBUG_INTR
2509 printk("** OK, disabling ser_interrupts\n");
2510#endif
2511 e100_disable_serial_data_irq(info);
2512 DINTR2(DEBUG_LOG(info->line, "ser_rx OK %d\n", info->line));
2513 info->break_detected_cnt = 0;
2514
2515 PROCSTAT(ser_stat[info->line].ser_ints_ok_cnt++);
2516 }
2517 /* Restarting the DMA never hurts */
2518 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, restart);
2519 START_FLUSH_FAST_TIMER(info, "ser_int");
2520 return info;
2521} /* handle_ser_rx_interrupt */
2522
2523static void handle_ser_tx_interrupt(struct e100_serial *info)
2524{
2525 unsigned long flags;
2526
2527 if (info->x_char) {
2528 unsigned char rstat;
2529 DFLOW(DEBUG_LOG(info->line, "tx_int: xchar 0x%02X\n", info->x_char));
2530 local_irq_save(flags);
2531 rstat = info->ioport[REG_STATUS];
2532 DFLOW(DEBUG_LOG(info->line, "stat %x\n", rstat));
2533
2534 info->ioport[REG_TR_DATA] = info->x_char;
2535 info->icount.tx++;
2536 info->x_char = 0;
2537 /* We must enable since it is disabled in ser_interrupt */
2538 e100_enable_serial_tx_ready_irq(info);
2539 local_irq_restore(flags);
2540 return;
2541 }
2542 if (info->uses_dma_out) {
2543 unsigned char rstat;
2544 int i;
2545 /* We only use normal tx interrupt when sending x_char */
2546 DFLOW(DEBUG_LOG(info->line, "tx_int: xchar sent\n", 0));
2547 local_irq_save(flags);
2548 rstat = info->ioport[REG_STATUS];
2549 DFLOW(DEBUG_LOG(info->line, "stat %x\n", rstat));
2550 e100_disable_serial_tx_ready_irq(info);
2551 if (info->port.tty->stopped)
2552 rs_stop(info->port.tty);
2553 /* Enable the DMA channel and tell it to continue */
2554 e100_enable_txdma_channel(info);
2555 /* Wait 12 cycles before doing the DMA command */
2556 for(i = 6; i > 0; i--)
2557 nop();
2558
2559 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, continue);
2560 local_irq_restore(flags);
2561 return;
2562 }
2563 /* Normal char-by-char interrupt */
2564 if (info->xmit.head == info->xmit.tail
2565 || info->port.tty->stopped
2566 || info->port.tty->hw_stopped) {
2567 DFLOW(DEBUG_LOG(info->line, "tx_int: stopped %i\n",
2568 info->port.tty->stopped));
2569 e100_disable_serial_tx_ready_irq(info);
2570 info->tr_running = 0;
2571 return;
2572 }
2573 DINTR2(DEBUG_LOG(info->line, "tx_int %c\n", info->xmit.buf[info->xmit.tail]));
2574 /* Send a byte, rs485 timing is critical so turn of ints */
2575 local_irq_save(flags);
2576 info->ioport[REG_TR_DATA] = info->xmit.buf[info->xmit.tail];
2577 info->xmit.tail = (info->xmit.tail + 1) & (SERIAL_XMIT_SIZE-1);
2578 info->icount.tx++;
2579 if (info->xmit.head == info->xmit.tail) {
2580#if defined(CONFIG_ETRAX_RS485) && defined(CONFIG_ETRAX_FAST_TIMER)
2581 if (info->rs485.flags & SER_RS485_ENABLED) {
2582 /* Set a short timer to toggle RTS */
2583 start_one_shot_timer(&fast_timers_rs485[info->line],
2584 rs485_toggle_rts_timer_function,
2585 (unsigned long)info,
2586 info->char_time_usec*2,
2587 "RS-485");
2588 }
2589#endif /* RS485 */
2590 info->last_tx_active_usec = GET_JIFFIES_USEC();
2591 info->last_tx_active = jiffies;
2592 e100_disable_serial_tx_ready_irq(info);
2593 info->tr_running = 0;
2594 DFLOW(DEBUG_LOG(info->line, "tx_int: stop2\n", 0));
2595 } else {
2596 /* We must enable since it is disabled in ser_interrupt */
2597 e100_enable_serial_tx_ready_irq(info);
2598 }
2599 local_irq_restore(flags);
2600
2601 if (CIRC_CNT(info->xmit.head,
2602 info->xmit.tail,
2603 SERIAL_XMIT_SIZE) < WAKEUP_CHARS)
2604 rs_sched_event(info, RS_EVENT_WRITE_WAKEUP);
2605
2606} /* handle_ser_tx_interrupt */
2607
2608/* result of time measurements:
2609 * RX duration 54-60 us when doing something, otherwise 6-9 us
2610 * ser_int duration: just sending: 8-15 us normally, up to 73 us
2611 */
2612static irqreturn_t
2613ser_interrupt(int irq, void *dev_id)
2614{
2615 static volatile int tx_started = 0;
2616 struct e100_serial *info;
2617 int i;
2618 unsigned long flags;
2619 unsigned long irq_mask1_rd;
2620 unsigned long data_mask = (1 << (8+2*0)); /* ser0 data_avail */
2621 int handled = 0;
2622 static volatile unsigned long reentered_ready_mask = 0;
2623
2624 local_irq_save(flags);
2625 irq_mask1_rd = *R_IRQ_MASK1_RD;
2626 /* First handle all rx interrupts with ints disabled */
2627 info = rs_table;
2628 irq_mask1_rd &= e100_ser_int_mask;
2629 for (i = 0; i < NR_PORTS; i++) {
2630 /* Which line caused the data irq? */
2631 if (irq_mask1_rd & data_mask) {
2632 handled = 1;
2633 handle_ser_rx_interrupt(info);
2634 }
2635 info += 1;
2636 data_mask <<= 2;
2637 }
2638 /* Handle tx interrupts with interrupts enabled so we
2639 * can take care of new data interrupts while transmitting
2640 * We protect the tx part with the tx_started flag.
2641 * We disable the tr_ready interrupts we are about to handle and
2642 * unblock the serial interrupt so new serial interrupts may come.
2643 *
2644 * If we get a new interrupt:
2645 * - it migth be due to synchronous serial ports.
2646 * - serial irq will be blocked by general irq handler.
2647 * - async data will be handled above (sync will be ignored).
2648 * - tx_started flag will prevent us from trying to send again and
2649 * we will exit fast - no need to unblock serial irq.
2650 * - Next (sync) serial interrupt handler will be runned with
2651 * disabled interrupt due to restore_flags() at end of function,
2652 * so sync handler will not be preempted or reentered.
2653 */
2654 if (!tx_started) {
2655 unsigned long ready_mask;
2656 unsigned long
2657 tx_started = 1;
2658 /* Only the tr_ready interrupts left */
2659 irq_mask1_rd &= (IO_MASK(R_IRQ_MASK1_RD, ser0_ready) |
2660 IO_MASK(R_IRQ_MASK1_RD, ser1_ready) |
2661 IO_MASK(R_IRQ_MASK1_RD, ser2_ready) |
2662 IO_MASK(R_IRQ_MASK1_RD, ser3_ready));
2663 while (irq_mask1_rd) {
2664 /* Disable those we are about to handle */
2665 *R_IRQ_MASK1_CLR = irq_mask1_rd;
2666 /* Unblock the serial interrupt */
2667 *R_VECT_MASK_SET = IO_STATE(R_VECT_MASK_SET, serial, set);
2668
2669 local_irq_enable();
2670 ready_mask = (1 << (8+1+2*0)); /* ser0 tr_ready */
2671 info = rs_table;
2672 for (i = 0; i < NR_PORTS; i++) {
2673 /* Which line caused the ready irq? */
2674 if (irq_mask1_rd & ready_mask) {
2675 handled = 1;
2676 handle_ser_tx_interrupt(info);
2677 }
2678 info += 1;
2679 ready_mask <<= 2;
2680 }
2681 /* handle_ser_tx_interrupt enables tr_ready interrupts */
2682 local_irq_disable();
2683 /* Handle reentered TX interrupt */
2684 irq_mask1_rd = reentered_ready_mask;
2685 }
2686 local_irq_disable();
2687 tx_started = 0;
2688 } else {
2689 unsigned long ready_mask;
2690 ready_mask = irq_mask1_rd & (IO_MASK(R_IRQ_MASK1_RD, ser0_ready) |
2691 IO_MASK(R_IRQ_MASK1_RD, ser1_ready) |
2692 IO_MASK(R_IRQ_MASK1_RD, ser2_ready) |
2693 IO_MASK(R_IRQ_MASK1_RD, ser3_ready));
2694 if (ready_mask) {
2695 reentered_ready_mask |= ready_mask;
2696 /* Disable those we are about to handle */
2697 *R_IRQ_MASK1_CLR = ready_mask;
2698 DFLOW(DEBUG_LOG(SERIAL_DEBUG_LINE, "ser_int reentered with TX %X\n", ready_mask));
2699 }
2700 }
2701
2702 local_irq_restore(flags);
2703 return IRQ_RETVAL(handled);
2704} /* ser_interrupt */
2705#endif
2706
2707/*
2708 * -------------------------------------------------------------------
2709 * Here ends the serial interrupt routines.
2710 * -------------------------------------------------------------------
2711 */
2712
2713/*
2714 * This routine is used to handle the "bottom half" processing for the
2715 * serial driver, known also the "software interrupt" processing.
2716 * This processing is done at the kernel interrupt level, after the
2717 * rs_interrupt() has returned, BUT WITH INTERRUPTS TURNED ON. This
2718 * is where time-consuming activities which can not be done in the
2719 * interrupt driver proper are done; the interrupt driver schedules
2720 * them using rs_sched_event(), and they get done here.
2721 */
2722static void
2723do_softint(struct work_struct *work)
2724{
2725 struct e100_serial *info;
2726 struct tty_struct *tty;
2727
2728 info = container_of(work, struct e100_serial, work);
2729
2730 tty = info->port.tty;
2731 if (!tty)
2732 return;
2733
2734 if (test_and_clear_bit(RS_EVENT_WRITE_WAKEUP, &info->event))
2735 tty_wakeup(tty);
2736}
2737
2738static int
2739startup(struct e100_serial * info)
2740{
2741 unsigned long flags;
2742 unsigned long xmit_page;
2743 int i;
2744
2745 xmit_page = get_zeroed_page(GFP_KERNEL);
2746 if (!xmit_page)
2747 return -ENOMEM;
2748
2749 local_irq_save(flags);
2750
2751 /* if it was already initialized, skip this */
2752
2753 if (info->flags & ASYNC_INITIALIZED) {
2754 local_irq_restore(flags);
2755 free_page(xmit_page);
2756 return 0;
2757 }
2758
2759 if (info->xmit.buf)
2760 free_page(xmit_page);
2761 else
2762 info->xmit.buf = (unsigned char *) xmit_page;
2763
2764#ifdef SERIAL_DEBUG_OPEN
2765 printk("starting up ttyS%d (xmit_buf 0x%p)...\n", info->line, info->xmit.buf);
2766#endif
2767
2768#ifdef CONFIG_SVINTO_SIM
2769 /* Bits and pieces collected from below. Better to have them
2770 in one ifdef:ed clause than to mix in a lot of ifdefs,
2771 right? */
2772 if (info->port.tty)
2773 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2774
2775 info->xmit.head = info->xmit.tail = 0;
2776 info->first_recv_buffer = info->last_recv_buffer = NULL;
2777 info->recv_cnt = info->max_recv_cnt = 0;
2778
2779 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++)
2780 info->rec_descr[i].buf = NULL;
2781
2782 /* No real action in the simulator, but may set info important
2783 to ioctl. */
2784 change_speed(info);
2785#else
2786
2787 /*
2788 * Clear the FIFO buffers and disable them
2789 * (they will be reenabled in change_speed())
2790 */
2791
2792 /*
2793 * Reset the DMA channels and make sure their interrupts are cleared
2794 */
2795
2796 if (info->dma_in_enabled) {
2797 info->uses_dma_in = 1;
2798 e100_enable_rxdma_channel(info);
2799
2800 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2801
2802 /* Wait until reset cycle is complete */
2803 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->icmdadr) ==
2804 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset));
2805
2806 /* Make sure the irqs are cleared */
2807 *info->iclrintradr =
2808 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
2809 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
2810 } else {
2811 e100_disable_rxdma_channel(info);
2812 }
2813
2814 if (info->dma_out_enabled) {
2815 info->uses_dma_out = 1;
2816 e100_enable_txdma_channel(info);
2817 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2818
2819 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->ocmdadr) ==
2820 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset));
2821
2822 /* Make sure the irqs are cleared */
2823 *info->oclrintradr =
2824 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
2825 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
2826 } else {
2827 e100_disable_txdma_channel(info);
2828 }
2829
2830 if (info->port.tty)
2831 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2832
2833 info->xmit.head = info->xmit.tail = 0;
2834 info->first_recv_buffer = info->last_recv_buffer = NULL;
2835 info->recv_cnt = info->max_recv_cnt = 0;
2836
2837 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++)
2838 info->rec_descr[i].buf = 0;
2839
2840 /*
2841 * and set the speed and other flags of the serial port
2842 * this will start the rx/tx as well
2843 */
2844#ifdef SERIAL_HANDLE_EARLY_ERRORS
2845 e100_enable_serial_data_irq(info);
2846#endif
2847 change_speed(info);
2848
2849 /* dummy read to reset any serial errors */
2850
2851 (void)info->ioport[REG_DATA];
2852
2853 /* enable the interrupts */
2854 if (info->uses_dma_out)
2855 e100_enable_txdma_irq(info);
2856
2857 e100_enable_rx_irq(info);
2858
2859 info->tr_running = 0; /* to be sure we don't lock up the transmitter */
2860
2861 /* setup the dma input descriptor and start dma */
2862
2863 start_receive(info);
2864
2865 /* for safety, make sure the descriptors last result is 0 bytes written */
2866
2867 info->tr_descr.sw_len = 0;
2868 info->tr_descr.hw_len = 0;
2869 info->tr_descr.status = 0;
2870
2871 /* enable RTS/DTR last */
2872
2873 e100_rts(info, 1);
2874 e100_dtr(info, 1);
2875
2876#endif /* CONFIG_SVINTO_SIM */
2877
2878 info->flags |= ASYNC_INITIALIZED;
2879
2880 local_irq_restore(flags);
2881 return 0;
2882}
2883
2884/*
2885 * This routine will shutdown a serial port; interrupts are disabled, and
2886 * DTR is dropped if the hangup on close termio flag is on.
2887 */
2888static void
2889shutdown(struct e100_serial * info)
2890{
2891 unsigned long flags;
2892 struct etrax_dma_descr *descr = info->rec_descr;
2893 struct etrax_recv_buffer *buffer;
2894 int i;
2895
2896#ifndef CONFIG_SVINTO_SIM
2897 /* shut down the transmitter and receiver */
2898 DFLOW(DEBUG_LOG(info->line, "shutdown %i\n", info->line));
2899 e100_disable_rx(info);
2900 info->ioport[REG_TR_CTRL] = (info->tx_ctrl &= ~0x40);
2901
2902 /* disable interrupts, reset dma channels */
2903 if (info->uses_dma_in) {
2904 e100_disable_rxdma_irq(info);
2905 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2906 info->uses_dma_in = 0;
2907 } else {
2908 e100_disable_serial_data_irq(info);
2909 }
2910
2911 if (info->uses_dma_out) {
2912 e100_disable_txdma_irq(info);
2913 info->tr_running = 0;
2914 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2915 info->uses_dma_out = 0;
2916 } else {
2917 e100_disable_serial_tx_ready_irq(info);
2918 info->tr_running = 0;
2919 }
2920
2921#endif /* CONFIG_SVINTO_SIM */
2922
2923 if (!(info->flags & ASYNC_INITIALIZED))
2924 return;
2925
2926#ifdef SERIAL_DEBUG_OPEN
2927 printk("Shutting down serial port %d (irq %d)....\n", info->line,
2928 info->irq);
2929#endif
2930
2931 local_irq_save(flags);
2932
2933 if (info->xmit.buf) {
2934 free_page((unsigned long)info->xmit.buf);
2935 info->xmit.buf = NULL;
2936 }
2937
2938 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++)
2939 if (descr[i].buf) {
2940 buffer = phys_to_virt(descr[i].buf) - sizeof *buffer;
2941 kfree(buffer);
2942 descr[i].buf = 0;
2943 }
2944
2945 if (!info->port.tty || (info->port.tty->termios->c_cflag & HUPCL)) {
2946 /* hang up DTR and RTS if HUPCL is enabled */
2947 e100_dtr(info, 0);
2948 e100_rts(info, 0); /* could check CRTSCTS before doing this */
2949 }
2950
2951 if (info->port.tty)
2952 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2953
2954 info->flags &= ~ASYNC_INITIALIZED;
2955 local_irq_restore(flags);
2956}
2957
2958
2959/* change baud rate and other assorted parameters */
2960
2961static void
2962change_speed(struct e100_serial *info)
2963{
2964 unsigned int cflag;
2965 unsigned long xoff;
2966 unsigned long flags;
2967 /* first some safety checks */
2968
2969 if (!info->port.tty || !info->port.tty->termios)
2970 return;
2971 if (!info->ioport)
2972 return;
2973
2974 cflag = info->port.tty->termios->c_cflag;
2975
2976 /* possibly, the tx/rx should be disabled first to do this safely */
2977
2978 /* change baud-rate and write it to the hardware */
2979 if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST) {
2980 /* Special baudrate */
2981 u32 mask = 0xFF << (info->line*8); /* Each port has 8 bits */
2982 unsigned long alt_source =
2983 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, normal) |
2984 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, normal);
2985 /* R_ALT_SER_BAUDRATE selects the source */
2986 DBAUD(printk("Custom baudrate: baud_base/divisor %lu/%i\n",
2987 (unsigned long)info->baud_base, info->custom_divisor));
2988 if (info->baud_base == SERIAL_PRESCALE_BASE) {
2989 /* 0, 2-65535 (0=65536) */
2990 u16 divisor = info->custom_divisor;
2991 /* R_SERIAL_PRESCALE (upper 16 bits of R_CLOCK_PRESCALE) */
2992 /* baudrate is 3.125MHz/custom_divisor */
2993 alt_source =
2994 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, prescale) |
2995 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, prescale);
2996 alt_source = 0x11;
2997 DBAUD(printk("Writing SERIAL_PRESCALE: divisor %i\n", divisor));
2998 *R_SERIAL_PRESCALE = divisor;
2999 info->baud = SERIAL_PRESCALE_BASE/divisor;
3000 }
3001#ifdef CONFIG_ETRAX_EXTERN_PB6CLK_ENABLED
3002 else if ((info->baud_base==CONFIG_ETRAX_EXTERN_PB6CLK_FREQ/8 &&
3003 info->custom_divisor == 1) ||
3004 (info->baud_base==CONFIG_ETRAX_EXTERN_PB6CLK_FREQ &&
3005 info->custom_divisor == 8)) {
3006 /* ext_clk selected */
3007 alt_source =
3008 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, extern) |
3009 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, extern);
3010 DBAUD(printk("using external baudrate: %lu\n", CONFIG_ETRAX_EXTERN_PB6CLK_FREQ/8));
3011 info->baud = CONFIG_ETRAX_EXTERN_PB6CLK_FREQ/8;
3012 }
3013#endif
3014 else
3015 {
3016 /* Bad baudbase, we don't support using timer0
3017 * for baudrate.
3018 */
3019 printk(KERN_WARNING "Bad baud_base/custom_divisor: %lu/%i\n",
3020 (unsigned long)info->baud_base, info->custom_divisor);
3021 }
3022 r_alt_ser_baudrate_shadow &= ~mask;
3023 r_alt_ser_baudrate_shadow |= (alt_source << (info->line*8));
3024 *R_ALT_SER_BAUDRATE = r_alt_ser_baudrate_shadow;
3025 } else {
3026 /* Normal baudrate */
3027 /* Make sure we use normal baudrate */
3028 u32 mask = 0xFF << (info->line*8); /* Each port has 8 bits */
3029 unsigned long alt_source =
3030 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, normal) |
3031 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, normal);
3032 r_alt_ser_baudrate_shadow &= ~mask;
3033 r_alt_ser_baudrate_shadow |= (alt_source << (info->line*8));
3034#ifndef CONFIG_SVINTO_SIM
3035 *R_ALT_SER_BAUDRATE = r_alt_ser_baudrate_shadow;
3036#endif /* CONFIG_SVINTO_SIM */
3037
3038 info->baud = cflag_to_baud(cflag);
3039#ifndef CONFIG_SVINTO_SIM
3040 info->ioport[REG_BAUD] = cflag_to_etrax_baud(cflag);
3041#endif /* CONFIG_SVINTO_SIM */
3042 }
3043
3044#ifndef CONFIG_SVINTO_SIM
3045 /* start with default settings and then fill in changes */
3046 local_irq_save(flags);
3047 /* 8 bit, no/even parity */
3048 info->rx_ctrl &= ~(IO_MASK(R_SERIAL0_REC_CTRL, rec_bitnr) |
3049 IO_MASK(R_SERIAL0_REC_CTRL, rec_par_en) |
3050 IO_MASK(R_SERIAL0_REC_CTRL, rec_par));
3051
3052 /* 8 bit, no/even parity, 1 stop bit, no cts */
3053 info->tx_ctrl &= ~(IO_MASK(R_SERIAL0_TR_CTRL, tr_bitnr) |
3054 IO_MASK(R_SERIAL0_TR_CTRL, tr_par_en) |
3055 IO_MASK(R_SERIAL0_TR_CTRL, tr_par) |
3056 IO_MASK(R_SERIAL0_TR_CTRL, stop_bits) |
3057 IO_MASK(R_SERIAL0_TR_CTRL, auto_cts));
3058
3059 if ((cflag & CSIZE) == CS7) {
3060 /* set 7 bit mode */
3061 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_bitnr, tr_7bit);
3062 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_bitnr, rec_7bit);
3063 }
3064
3065 if (cflag & CSTOPB) {
3066 /* set 2 stop bit mode */
3067 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, stop_bits, two_bits);
3068 }
3069
3070 if (cflag & PARENB) {
3071 /* enable parity */
3072 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_par_en, enable);
3073 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_par_en, enable);
3074 }
3075
3076 if (cflag & CMSPAR) {
3077 /* enable stick parity, PARODD mean Mark which matches ETRAX */
3078 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_stick_par, stick);
3079 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_stick_par, stick);
3080 }
3081 if (cflag & PARODD) {
3082 /* set odd parity (or Mark if CMSPAR) */
3083 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_par, odd);
3084 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_par, odd);
3085 }
3086
3087 if (cflag & CRTSCTS) {
3088 /* enable automatic CTS handling */
3089 DFLOW(DEBUG_LOG(info->line, "FLOW auto_cts enabled\n", 0));
3090 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, auto_cts, active);
3091 }
3092
3093 /* make sure the tx and rx are enabled */
3094
3095 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_enable, enable);
3096 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_enable, enable);
3097
3098 /* actually write the control regs to the hardware */
3099
3100 info->ioport[REG_TR_CTRL] = info->tx_ctrl;
3101 info->ioport[REG_REC_CTRL] = info->rx_ctrl;
3102 xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char, STOP_CHAR(info->port.tty));
3103 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, enable);
3104 if (info->port.tty->termios->c_iflag & IXON ) {
3105 DFLOW(DEBUG_LOG(info->line, "FLOW XOFF enabled 0x%02X\n",
3106 STOP_CHAR(info->port.tty)));
3107 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable);
3108 }
3109
3110 *((unsigned long *)&info->ioport[REG_XOFF]) = xoff;
3111 local_irq_restore(flags);
3112#endif /* !CONFIG_SVINTO_SIM */
3113
3114 update_char_time(info);
3115
3116} /* change_speed */
3117
3118/* start transmitting chars NOW */
3119
3120static void
3121rs_flush_chars(struct tty_struct *tty)
3122{
3123 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3124 unsigned long flags;
3125
3126 if (info->tr_running ||
3127 info->xmit.head == info->xmit.tail ||
3128 tty->stopped ||
3129 tty->hw_stopped ||
3130 !info->xmit.buf)
3131 return;
3132
3133#ifdef SERIAL_DEBUG_FLOW
3134 printk("rs_flush_chars\n");
3135#endif
3136
3137 /* this protection might not exactly be necessary here */
3138
3139 local_irq_save(flags);
3140 start_transmit(info);
3141 local_irq_restore(flags);
3142}
3143
3144static int rs_raw_write(struct tty_struct *tty,
3145 const unsigned char *buf, int count)
3146{
3147 int c, ret = 0;
3148 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3149 unsigned long flags;
3150
3151 /* first some sanity checks */
3152
3153 if (!tty || !info->xmit.buf || !tmp_buf)
3154 return 0;
3155
3156#ifdef SERIAL_DEBUG_DATA
3157 if (info->line == SERIAL_DEBUG_LINE)
3158 printk("rs_raw_write (%d), status %d\n",
3159 count, info->ioport[REG_STATUS]);
3160#endif
3161
3162#ifdef CONFIG_SVINTO_SIM
3163 /* Really simple. The output is here and now. */
3164 SIMCOUT(buf, count);
3165 return count;
3166#endif
3167 local_save_flags(flags);
3168 DFLOW(DEBUG_LOG(info->line, "write count %i ", count));
3169 DFLOW(DEBUG_LOG(info->line, "ldisc %i\n", tty->ldisc.chars_in_buffer(tty)));
3170
3171
3172 /* The local_irq_disable/restore_flags pairs below are needed
3173 * because the DMA interrupt handler moves the info->xmit values.
3174 * the memcpy needs to be in the critical region unfortunately,
3175 * because we need to read xmit values, memcpy, write xmit values
3176 * in one atomic operation... this could perhaps be avoided by
3177 * more clever design.
3178 */
3179 local_irq_disable();
3180 while (count) {
3181 c = CIRC_SPACE_TO_END(info->xmit.head,
3182 info->xmit.tail,
3183 SERIAL_XMIT_SIZE);
3184
3185 if (count < c)
3186 c = count;
3187 if (c <= 0)
3188 break;
3189
3190 memcpy(info->xmit.buf + info->xmit.head, buf, c);
3191 info->xmit.head = (info->xmit.head + c) &
3192 (SERIAL_XMIT_SIZE-1);
3193 buf += c;
3194 count -= c;
3195 ret += c;
3196 }
3197 local_irq_restore(flags);
3198
3199 /* enable transmitter if not running, unless the tty is stopped
3200 * this does not need IRQ protection since if tr_running == 0
3201 * the IRQ's are not running anyway for this port.
3202 */
3203 DFLOW(DEBUG_LOG(info->line, "write ret %i\n", ret));
3204
3205 if (info->xmit.head != info->xmit.tail &&
3206 !tty->stopped &&
3207 !tty->hw_stopped &&
3208 !info->tr_running) {
3209 start_transmit(info);
3210 }
3211
3212 return ret;
3213} /* raw_raw_write() */
3214
3215static int
3216rs_write(struct tty_struct *tty,
3217 const unsigned char *buf, int count)
3218{
3219#if defined(CONFIG_ETRAX_RS485)
3220 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3221
3222 if (info->rs485.flags & SER_RS485_ENABLED)
3223 {
3224 /* If we are in RS-485 mode, we need to toggle RTS and disable
3225 * the receiver before initiating a DMA transfer
3226 */
3227#ifdef CONFIG_ETRAX_FAST_TIMER
3228 /* Abort any started timer */
3229 fast_timers_rs485[info->line].function = NULL;
3230 del_fast_timer(&fast_timers_rs485[info->line]);
3231#endif
3232 e100_rts(info, (info->rs485.flags & SER_RS485_RTS_ON_SEND));
3233#if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
3234 e100_disable_rx(info);
3235 e100_enable_rx_irq(info);
3236#endif
3237 if ((info->rs485.flags & SER_RS485_RTS_BEFORE_SEND) &&
3238 (info->rs485.delay_rts_before_send > 0))
3239 msleep(info->rs485.delay_rts_before_send);
3240 }
3241#endif /* CONFIG_ETRAX_RS485 */
3242
3243 count = rs_raw_write(tty, buf, count);
3244
3245#if defined(CONFIG_ETRAX_RS485)
3246 if (info->rs485.flags & SER_RS485_ENABLED)
3247 {
3248 unsigned int val;
3249 /* If we are in RS-485 mode the following has to be done:
3250 * wait until DMA is ready
3251 * wait on transmit shift register
3252 * toggle RTS
3253 * enable the receiver
3254 */
3255
3256 /* Sleep until all sent */
3257 tty_wait_until_sent(tty, 0);
3258#ifdef CONFIG_ETRAX_FAST_TIMER
3259 /* Now sleep a little more so that shift register is empty */
3260 schedule_usleep(info->char_time_usec * 2);
3261#endif
3262 /* wait on transmit shift register */
3263 do{
3264 get_lsr_info(info, &val);
3265 }while (!(val & TIOCSER_TEMT));
3266
3267 e100_rts(info, (info->rs485.flags & SER_RS485_RTS_AFTER_SEND));
3268
3269#if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
3270 e100_enable_rx(info);
3271 e100_enable_rxdma_irq(info);
3272#endif
3273 }
3274#endif /* CONFIG_ETRAX_RS485 */
3275
3276 return count;
3277} /* rs_write */
3278
3279
3280/* how much space is available in the xmit buffer? */
3281
3282static int
3283rs_write_room(struct tty_struct *tty)
3284{
3285 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3286
3287 return CIRC_SPACE(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
3288}
3289
3290/* How many chars are in the xmit buffer?
3291 * This does not include any chars in the transmitter FIFO.
3292 * Use wait_until_sent for waiting for FIFO drain.
3293 */
3294
3295static int
3296rs_chars_in_buffer(struct tty_struct *tty)
3297{
3298 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3299
3300 return CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
3301}
3302
3303/* discard everything in the xmit buffer */
3304
3305static void
3306rs_flush_buffer(struct tty_struct *tty)
3307{
3308 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3309 unsigned long flags;
3310
3311 local_irq_save(flags);
3312 info->xmit.head = info->xmit.tail = 0;
3313 local_irq_restore(flags);
3314
3315 tty_wakeup(tty);
3316}
3317
3318/*
3319 * This function is used to send a high-priority XON/XOFF character to
3320 * the device
3321 *
3322 * Since we use DMA we don't check for info->x_char in transmit_chars_dma(),
3323 * but we do it in handle_ser_tx_interrupt().
3324 * We disable DMA channel and enable tx ready interrupt and write the
3325 * character when possible.
3326 */
3327static void rs_send_xchar(struct tty_struct *tty, char ch)
3328{
3329 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3330 unsigned long flags;
3331 local_irq_save(flags);
3332 if (info->uses_dma_out) {
3333 /* Put the DMA on hold and disable the channel */
3334 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, hold);
3335 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->ocmdadr) !=
3336 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, hold));
3337 e100_disable_txdma_channel(info);
3338 }
3339
3340 /* Must make sure transmitter is not stopped before we can transmit */
3341 if (tty->stopped)
3342 rs_start(tty);
3343
3344 /* Enable manual transmit interrupt and send from there */
3345 DFLOW(DEBUG_LOG(info->line, "rs_send_xchar 0x%02X\n", ch));
3346 info->x_char = ch;
3347 e100_enable_serial_tx_ready_irq(info);
3348 local_irq_restore(flags);
3349}
3350
3351/*
3352 * ------------------------------------------------------------
3353 * rs_throttle()
3354 *
3355 * This routine is called by the upper-layer tty layer to signal that
3356 * incoming characters should be throttled.
3357 * ------------------------------------------------------------
3358 */
3359static void
3360rs_throttle(struct tty_struct * tty)
3361{
3362 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3363#ifdef SERIAL_DEBUG_THROTTLE
3364 char buf[64];
3365
3366 printk("throttle %s: %lu....\n", tty_name(tty, buf),
3367 (unsigned long)tty->ldisc.chars_in_buffer(tty));
3368#endif
3369 DFLOW(DEBUG_LOG(info->line,"rs_throttle %lu\n", tty->ldisc.chars_in_buffer(tty)));
3370
3371 /* Do RTS before XOFF since XOFF might take some time */
3372 if (tty->termios->c_cflag & CRTSCTS) {
3373 /* Turn off RTS line */
3374 e100_rts(info, 0);
3375 }
3376 if (I_IXOFF(tty))
3377 rs_send_xchar(tty, STOP_CHAR(tty));
3378
3379}
3380
3381static void
3382rs_unthrottle(struct tty_struct * tty)
3383{
3384 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3385#ifdef SERIAL_DEBUG_THROTTLE
3386 char buf[64];
3387
3388 printk("unthrottle %s: %lu....\n", tty_name(tty, buf),
3389 (unsigned long)tty->ldisc.chars_in_buffer(tty));
3390#endif
3391 DFLOW(DEBUG_LOG(info->line,"rs_unthrottle ldisc %d\n", tty->ldisc.chars_in_buffer(tty)));
3392 DFLOW(DEBUG_LOG(info->line,"rs_unthrottle flip.count: %i\n", tty->flip.count));
3393 /* Do RTS before XOFF since XOFF might take some time */
3394 if (tty->termios->c_cflag & CRTSCTS) {
3395 /* Assert RTS line */
3396 e100_rts(info, 1);
3397 }
3398
3399 if (I_IXOFF(tty)) {
3400 if (info->x_char)
3401 info->x_char = 0;
3402 else
3403 rs_send_xchar(tty, START_CHAR(tty));
3404 }
3405
3406}
3407
3408/*
3409 * ------------------------------------------------------------
3410 * rs_ioctl() and friends
3411 * ------------------------------------------------------------
3412 */
3413
3414static int
3415get_serial_info(struct e100_serial * info,
3416 struct serial_struct * retinfo)
3417{
3418 struct serial_struct tmp;
3419
3420 /* this is all probably wrong, there are a lot of fields
3421 * here that we don't have in e100_serial and maybe we
3422 * should set them to something else than 0.
3423 */
3424
3425 if (!retinfo)
3426 return -EFAULT;
3427 memset(&tmp, 0, sizeof(tmp));
3428 tmp.type = info->type;
3429 tmp.line = info->line;
3430 tmp.port = (int)info->ioport;
3431 tmp.irq = info->irq;
3432 tmp.flags = info->flags;
3433 tmp.baud_base = info->baud_base;
3434 tmp.close_delay = info->close_delay;
3435 tmp.closing_wait = info->closing_wait;
3436 tmp.custom_divisor = info->custom_divisor;
3437 if (copy_to_user(retinfo, &tmp, sizeof(*retinfo)))
3438 return -EFAULT;
3439 return 0;
3440}
3441
3442static int
3443set_serial_info(struct e100_serial *info,
3444 struct serial_struct *new_info)
3445{
3446 struct serial_struct new_serial;
3447 struct e100_serial old_info;
3448 int retval = 0;
3449
3450 if (copy_from_user(&new_serial, new_info, sizeof(new_serial)))
3451 return -EFAULT;
3452
3453 old_info = *info;
3454
3455 if (!capable(CAP_SYS_ADMIN)) {
3456 if ((new_serial.type != info->type) ||
3457 (new_serial.close_delay != info->close_delay) ||
3458 ((new_serial.flags & ~ASYNC_USR_MASK) !=
3459 (info->flags & ~ASYNC_USR_MASK)))
3460 return -EPERM;
3461 info->flags = ((info->flags & ~ASYNC_USR_MASK) |
3462 (new_serial.flags & ASYNC_USR_MASK));
3463 goto check_and_exit;
3464 }
3465
3466 if (info->count > 1)
3467 return -EBUSY;
3468
3469 /*
3470 * OK, past this point, all the error checking has been done.
3471 * At this point, we start making changes.....
3472 */
3473
3474 info->baud_base = new_serial.baud_base;
3475 info->flags = ((info->flags & ~ASYNC_FLAGS) |
3476 (new_serial.flags & ASYNC_FLAGS));
3477 info->custom_divisor = new_serial.custom_divisor;
3478 info->type = new_serial.type;
3479 info->close_delay = new_serial.close_delay;
3480 info->closing_wait = new_serial.closing_wait;
3481 info->port.tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
3482
3483 check_and_exit:
3484 if (info->flags & ASYNC_INITIALIZED) {
3485 change_speed(info);
3486 } else
3487 retval = startup(info);
3488 return retval;
3489}
3490
3491/*
3492 * get_lsr_info - get line status register info
3493 *
3494 * Purpose: Let user call ioctl() to get info when the UART physically
3495 * is emptied. On bus types like RS485, the transmitter must
3496 * release the bus after transmitting. This must be done when
3497 * the transmit shift register is empty, not be done when the
3498 * transmit holding register is empty. This functionality
3499 * allows an RS485 driver to be written in user space.
3500 */
3501static int
3502get_lsr_info(struct e100_serial * info, unsigned int *value)
3503{
3504 unsigned int result = TIOCSER_TEMT;
3505#ifndef CONFIG_SVINTO_SIM
3506 unsigned long curr_time = jiffies;
3507 unsigned long curr_time_usec = GET_JIFFIES_USEC();
3508 unsigned long elapsed_usec =
3509 (curr_time - info->last_tx_active) * 1000000/HZ +
3510 curr_time_usec - info->last_tx_active_usec;
3511
3512 if (info->xmit.head != info->xmit.tail ||
3513 elapsed_usec < 2*info->char_time_usec) {
3514 result = 0;
3515 }
3516#endif
3517
3518 if (copy_to_user(value, &result, sizeof(int)))
3519 return -EFAULT;
3520 return 0;
3521}
3522
3523#ifdef SERIAL_DEBUG_IO
3524struct state_str
3525{
3526 int state;
3527 const char *str;
3528};
3529
3530const struct state_str control_state_str[] = {
3531 {TIOCM_DTR, "DTR" },
3532 {TIOCM_RTS, "RTS"},
3533 {TIOCM_ST, "ST?" },
3534 {TIOCM_SR, "SR?" },
3535 {TIOCM_CTS, "CTS" },
3536 {TIOCM_CD, "CD" },
3537 {TIOCM_RI, "RI" },
3538 {TIOCM_DSR, "DSR" },
3539 {0, NULL }
3540};
3541
3542char *get_control_state_str(int MLines, char *s)
3543{
3544 int i = 0;
3545
3546 s[0]='\0';
3547 while (control_state_str[i].str != NULL) {
3548 if (MLines & control_state_str[i].state) {
3549 if (s[0] != '\0') {
3550 strcat(s, ", ");
3551 }
3552 strcat(s, control_state_str[i].str);
3553 }
3554 i++;
3555 }
3556 return s;
3557}
3558#endif
3559
3560static int
3561rs_break(struct tty_struct *tty, int break_state)
3562{
3563 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3564 unsigned long flags;
3565
3566 if (!info->ioport)
3567 return -EIO;
3568
3569 local_irq_save(flags);
3570 if (break_state == -1) {
3571 /* Go to manual mode and set the txd pin to 0 */
3572 /* Clear bit 7 (txd) and 6 (tr_enable) */
3573 info->tx_ctrl &= 0x3F;
3574 } else {
3575 /* Set bit 7 (txd) and 6 (tr_enable) */
3576 info->tx_ctrl |= (0x80 | 0x40);
3577 }
3578 info->ioport[REG_TR_CTRL] = info->tx_ctrl;
3579 local_irq_restore(flags);
3580 return 0;
3581}
3582
3583static int
3584rs_tiocmset(struct tty_struct *tty, struct file *file,
3585 unsigned int set, unsigned int clear)
3586{
3587 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3588 unsigned long flags;
3589
3590 local_irq_save(flags);
3591
3592 if (clear & TIOCM_RTS)
3593 e100_rts(info, 0);
3594 if (clear & TIOCM_DTR)
3595 e100_dtr(info, 0);
3596 /* Handle FEMALE behaviour */
3597 if (clear & TIOCM_RI)
3598 e100_ri_out(info, 0);
3599 if (clear & TIOCM_CD)
3600 e100_cd_out(info, 0);
3601
3602 if (set & TIOCM_RTS)
3603 e100_rts(info, 1);
3604 if (set & TIOCM_DTR)
3605 e100_dtr(info, 1);
3606 /* Handle FEMALE behaviour */
3607 if (set & TIOCM_RI)
3608 e100_ri_out(info, 1);
3609 if (set & TIOCM_CD)
3610 e100_cd_out(info, 1);
3611
3612 local_irq_restore(flags);
3613 return 0;
3614}
3615
3616static int
3617rs_tiocmget(struct tty_struct *tty, struct file *file)
3618{
3619 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3620 unsigned int result;
3621 unsigned long flags;
3622
3623 local_irq_save(flags);
3624
3625 result =
3626 (!E100_RTS_GET(info) ? TIOCM_RTS : 0)
3627 | (!E100_DTR_GET(info) ? TIOCM_DTR : 0)
3628 | (!E100_RI_GET(info) ? TIOCM_RNG : 0)
3629 | (!E100_DSR_GET(info) ? TIOCM_DSR : 0)
3630 | (!E100_CD_GET(info) ? TIOCM_CAR : 0)
3631 | (!E100_CTS_GET(info) ? TIOCM_CTS : 0);
3632
3633 local_irq_restore(flags);
3634
3635#ifdef SERIAL_DEBUG_IO
3636 printk(KERN_DEBUG "ser%i: modem state: %i 0x%08X\n",
3637 info->line, result, result);
3638 {
3639 char s[100];
3640
3641 get_control_state_str(result, s);
3642 printk(KERN_DEBUG "state: %s\n", s);
3643 }
3644#endif
3645 return result;
3646
3647}
3648
3649
3650static int
3651rs_ioctl(struct tty_struct *tty, struct file * file,
3652 unsigned int cmd, unsigned long arg)
3653{
3654 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
3655
3656 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
3657 (cmd != TIOCSERCONFIG) && (cmd != TIOCSERGWILD) &&
3658 (cmd != TIOCSERSWILD) && (cmd != TIOCSERGSTRUCT)) {
3659 if (tty->flags & (1 << TTY_IO_ERROR))
3660 return -EIO;
3661 }
3662
3663 switch (cmd) {
3664 case TIOCGSERIAL:
3665 return get_serial_info(info,
3666 (struct serial_struct *) arg);
3667 case TIOCSSERIAL:
3668 return set_serial_info(info,
3669 (struct serial_struct *) arg);
3670 case TIOCSERGETLSR: /* Get line status register */
3671 return get_lsr_info(info, (unsigned int *) arg);
3672
3673 case TIOCSERGSTRUCT:
3674 if (copy_to_user((struct e100_serial *) arg,
3675 info, sizeof(struct e100_serial)))
3676 return -EFAULT;
3677 return 0;
3678
3679#if defined(CONFIG_ETRAX_RS485)
3680 case TIOCSERSETRS485:
3681 {
3682 /* In this ioctl we still use the old structure
3683 * rs485_control for backward compatibility
3684 * (if we use serial_rs485, then old user-level code
3685 * wouldn't work anymore...).
3686 * The use of this ioctl is deprecated: use TIOCSRS485
3687 * instead.*/
3688 struct rs485_control rs485ctrl;
3689 struct serial_rs485 rs485data;
3690 printk(KERN_DEBUG "The use of this ioctl is deprecated. Use TIOCSRS485 instead\n");
3691 if (copy_from_user(&rs485ctrl, (struct rs485_control *)arg,
3692 sizeof(rs485ctrl)))
3693 return -EFAULT;
3694
3695 rs485data.delay_rts_before_send = rs485ctrl.delay_rts_before_send;
3696 rs485data.flags = 0;
3697 if (rs485data.delay_rts_before_send != 0)
3698 rs485data.flags |= SER_RS485_RTS_BEFORE_SEND;
3699 else
3700 rs485data.flags &= ~(SER_RS485_RTS_BEFORE_SEND);
3701
3702 if (rs485ctrl.enabled)
3703 rs485data.flags |= SER_RS485_ENABLED;
3704 else
3705 rs485data.flags &= ~(SER_RS485_ENABLED);
3706
3707 if (rs485ctrl.rts_on_send)
3708 rs485data.flags |= SER_RS485_RTS_ON_SEND;
3709 else
3710 rs485data.flags &= ~(SER_RS485_RTS_ON_SEND);
3711
3712 if (rs485ctrl.rts_after_sent)
3713 rs485data.flags |= SER_RS485_RTS_AFTER_SEND;
3714 else
3715 rs485data.flags &= ~(SER_RS485_RTS_AFTER_SEND);
3716
3717 return e100_enable_rs485(tty, &rs485data);
3718 }
3719
3720 case TIOCSRS485:
3721 {
3722 /* This is the new version of TIOCSRS485, with new
3723 * data structure serial_rs485 */
3724 struct serial_rs485 rs485data;
3725 if (copy_from_user(&rs485data, (struct rs485_control *)arg,
3726 sizeof(rs485data)))
3727 return -EFAULT;
3728
3729 return e100_enable_rs485(tty, &rs485data);
3730 }
3731
3732 case TIOCGRS485:
3733 {
3734 struct serial_rs485 *rs485data =
3735 &(((struct e100_serial *)tty->driver_data)->rs485);
3736 /* This is the ioctl to get RS485 data from user-space */
3737 if (copy_to_user((struct serial_rs485 *) arg,
3738 rs485data,
3739 sizeof(struct serial_rs485)))
3740 return -EFAULT;
3741 break;
3742 }
3743
3744 case TIOCSERWRRS485:
3745 {
3746 struct rs485_write rs485wr;
3747 if (copy_from_user(&rs485wr, (struct rs485_write *)arg,
3748 sizeof(rs485wr)))
3749 return -EFAULT;
3750
3751 return e100_write_rs485(tty, rs485wr.outc, rs485wr.outc_size);
3752 }
3753#endif
3754
3755 default:
3756 return -ENOIOCTLCMD;
3757 }
3758 return 0;
3759}
3760
3761static void
3762rs_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
3763{
3764 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3765
3766 change_speed(info);
3767
3768 /* Handle turning off CRTSCTS */
3769 if ((old_termios->c_cflag & CRTSCTS) &&
3770 !(tty->termios->c_cflag & CRTSCTS)) {
3771 tty->hw_stopped = 0;
3772 rs_start(tty);
3773 }
3774
3775}
3776
3777/*
3778 * ------------------------------------------------------------
3779 * rs_close()
3780 *
3781 * This routine is called when the serial port gets closed. First, we
3782 * wait for the last remaining data to be sent. Then, we unlink its
3783 * S structure from the interrupt chain if necessary, and we free
3784 * that IRQ if nothing is left in the chain.
3785 * ------------------------------------------------------------
3786 */
3787static void
3788rs_close(struct tty_struct *tty, struct file * filp)
3789{
3790 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
3791 unsigned long flags;
3792
3793 if (!info)
3794 return;
3795
3796 /* interrupts are disabled for this entire function */
3797
3798 local_irq_save(flags);
3799
3800 if (tty_hung_up_p(filp)) {
3801 local_irq_restore(flags);
3802 return;
3803 }
3804
3805#ifdef SERIAL_DEBUG_OPEN
3806 printk("[%d] rs_close ttyS%d, count = %d\n", current->pid,
3807 info->line, info->count);
3808#endif
3809 if ((tty->count == 1) && (info->count != 1)) {
3810 /*
3811 * Uh, oh. tty->count is 1, which means that the tty
3812 * structure will be freed. Info->count should always
3813 * be one in these conditions. If it's greater than
3814 * one, we've got real problems, since it means the
3815 * serial port won't be shutdown.
3816 */
3817 printk(KERN_CRIT
3818 "rs_close: bad serial port count; tty->count is 1, "
3819 "info->count is %d\n", info->count);
3820 info->count = 1;
3821 }
3822 if (--info->count < 0) {
3823 printk(KERN_CRIT "rs_close: bad serial port count for ttyS%d: %d\n",
3824 info->line, info->count);
3825 info->count = 0;
3826 }
3827 if (info->count) {
3828 local_irq_restore(flags);
3829 return;
3830 }
3831 info->flags |= ASYNC_CLOSING;
3832 /*
3833 * Save the termios structure, since this port may have
3834 * separate termios for callout and dialin.
3835 */
3836 if (info->flags & ASYNC_NORMAL_ACTIVE)
3837 info->normal_termios = *tty->termios;
3838 /*
3839 * Now we wait for the transmit buffer to clear; and we notify
3840 * the line discipline to only process XON/XOFF characters.
3841 */
3842 tty->closing = 1;
3843 if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE)
3844 tty_wait_until_sent(tty, info->closing_wait);
3845 /*
3846 * At this point we stop accepting input. To do this, we
3847 * disable the serial receiver and the DMA receive interrupt.
3848 */
3849#ifdef SERIAL_HANDLE_EARLY_ERRORS
3850 e100_disable_serial_data_irq(info);
3851#endif
3852
3853#ifndef CONFIG_SVINTO_SIM
3854 e100_disable_rx(info);
3855 e100_disable_rx_irq(info);
3856
3857 if (info->flags & ASYNC_INITIALIZED) {
3858 /*
3859 * Before we drop DTR, make sure the UART transmitter
3860 * has completely drained; this is especially
3861 * important as we have a transmit FIFO!
3862 */
3863 rs_wait_until_sent(tty, HZ);
3864 }
3865#endif
3866
3867 shutdown(info);
3868 rs_flush_buffer(tty);
3869 tty_ldisc_flush(tty);
3870 tty->closing = 0;
3871 info->event = 0;
3872 info->port.tty = NULL;
3873 if (info->blocked_open) {
3874 if (info->close_delay)
3875 schedule_timeout_interruptible(info->close_delay);
3876 wake_up_interruptible(&info->open_wait);
3877 }
3878 info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
3879 wake_up_interruptible(&info->close_wait);
3880 local_irq_restore(flags);
3881
3882 /* port closed */
3883
3884#if defined(CONFIG_ETRAX_RS485)
3885 if (info->rs485.flags & SER_RS485_ENABLED) {
3886 info->rs485.flags &= ~(SER_RS485_ENABLED);
3887#if defined(CONFIG_ETRAX_RS485_ON_PA)
3888 *R_PORT_PA_DATA = port_pa_data_shadow &= ~(1 << rs485_pa_bit);
3889#endif
3890#if defined(CONFIG_ETRAX_RS485_ON_PORT_G)
3891 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
3892 rs485_port_g_bit, 0);
3893#endif
3894#if defined(CONFIG_ETRAX_RS485_LTC1387)
3895 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
3896 CONFIG_ETRAX_RS485_LTC1387_DXEN_PORT_G_BIT, 0);
3897 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
3898 CONFIG_ETRAX_RS485_LTC1387_RXEN_PORT_G_BIT, 0);
3899#endif
3900 }
3901#endif
3902
3903 /*
3904 * Release any allocated DMA irq's.
3905 */
3906 if (info->dma_in_enabled) {
3907 free_irq(info->dma_in_irq_nbr, info);
3908 cris_free_dma(info->dma_in_nbr, info->dma_in_irq_description);
3909 info->uses_dma_in = 0;
3910#ifdef SERIAL_DEBUG_OPEN
3911 printk(KERN_DEBUG "DMA irq '%s' freed\n",
3912 info->dma_in_irq_description);
3913#endif
3914 }
3915 if (info->dma_out_enabled) {
3916 free_irq(info->dma_out_irq_nbr, info);
3917 cris_free_dma(info->dma_out_nbr, info->dma_out_irq_description);
3918 info->uses_dma_out = 0;
3919#ifdef SERIAL_DEBUG_OPEN
3920 printk(KERN_DEBUG "DMA irq '%s' freed\n",
3921 info->dma_out_irq_description);
3922#endif
3923 }
3924}
3925
3926/*
3927 * rs_wait_until_sent() --- wait until the transmitter is empty
3928 */
3929static void rs_wait_until_sent(struct tty_struct *tty, int timeout)
3930{
3931 unsigned long orig_jiffies;
3932 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3933 unsigned long curr_time = jiffies;
3934 unsigned long curr_time_usec = GET_JIFFIES_USEC();
3935 long elapsed_usec =
3936 (curr_time - info->last_tx_active) * (1000000/HZ) +
3937 curr_time_usec - info->last_tx_active_usec;
3938
3939 /*
3940 * Check R_DMA_CHx_STATUS bit 0-6=number of available bytes in FIFO
3941 * R_DMA_CHx_HWSW bit 31-16=nbr of bytes left in DMA buffer (0=64k)
3942 */
3943 orig_jiffies = jiffies;
3944 while (info->xmit.head != info->xmit.tail || /* More in send queue */
3945 (*info->ostatusadr & 0x007f) || /* more in FIFO */
3946 (elapsed_usec < 2*info->char_time_usec)) {
3947 schedule_timeout_interruptible(1);
3948 if (signal_pending(current))
3949 break;
3950 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3951 break;
3952 curr_time = jiffies;
3953 curr_time_usec = GET_JIFFIES_USEC();
3954 elapsed_usec =
3955 (curr_time - info->last_tx_active) * (1000000/HZ) +
3956 curr_time_usec - info->last_tx_active_usec;
3957 }
3958 set_current_state(TASK_RUNNING);
3959}
3960
3961/*
3962 * rs_hangup() --- called by tty_hangup() when a hangup is signaled.
3963 */
3964void
3965rs_hangup(struct tty_struct *tty)
3966{
3967 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
3968
3969 rs_flush_buffer(tty);
3970 shutdown(info);
3971 info->event = 0;
3972 info->count = 0;
3973 info->flags &= ~ASYNC_NORMAL_ACTIVE;
3974 info->port.tty = NULL;
3975 wake_up_interruptible(&info->open_wait);
3976}
3977
3978/*
3979 * ------------------------------------------------------------
3980 * rs_open() and friends
3981 * ------------------------------------------------------------
3982 */
3983static int
3984block_til_ready(struct tty_struct *tty, struct file * filp,
3985 struct e100_serial *info)
3986{
3987 DECLARE_WAITQUEUE(wait, current);
3988 unsigned long flags;
3989 int retval;
3990 int do_clocal = 0, extra_count = 0;
3991
3992 /*
3993 * If the device is in the middle of being closed, then block
3994 * until it's done, and then try again.
3995 */
3996 if (tty_hung_up_p(filp) ||
3997 (info->flags & ASYNC_CLOSING)) {
3998 wait_event_interruptible_tty(info->close_wait,
3999 !(info->flags & ASYNC_CLOSING));
4000#ifdef SERIAL_DO_RESTART
4001 if (info->flags & ASYNC_HUP_NOTIFY)
4002 return -EAGAIN;
4003 else
4004 return -ERESTARTSYS;
4005#else
4006 return -EAGAIN;
4007#endif
4008 }
4009
4010 /*
4011 * If non-blocking mode is set, or the port is not enabled,
4012 * then make the check up front and then exit.
4013 */
4014 if ((filp->f_flags & O_NONBLOCK) ||
4015 (tty->flags & (1 << TTY_IO_ERROR))) {
4016 info->flags |= ASYNC_NORMAL_ACTIVE;
4017 return 0;
4018 }
4019
4020 if (tty->termios->c_cflag & CLOCAL) {
4021 do_clocal = 1;
4022 }
4023
4024 /*
4025 * Block waiting for the carrier detect and the line to become
4026 * free (i.e., not in use by the callout). While we are in
4027 * this loop, info->count is dropped by one, so that
4028 * rs_close() knows when to free things. We restore it upon
4029 * exit, either normal or abnormal.
4030 */
4031 retval = 0;
4032 add_wait_queue(&info->open_wait, &wait);
4033#ifdef SERIAL_DEBUG_OPEN
4034 printk("block_til_ready before block: ttyS%d, count = %d\n",
4035 info->line, info->count);
4036#endif
4037 local_irq_save(flags);
4038 if (!tty_hung_up_p(filp)) {
4039 extra_count++;
4040 info->count--;
4041 }
4042 local_irq_restore(flags);
4043 info->blocked_open++;
4044 while (1) {
4045 local_irq_save(flags);
4046 /* assert RTS and DTR */
4047 e100_rts(info, 1);
4048 e100_dtr(info, 1);
4049 local_irq_restore(flags);
4050 set_current_state(TASK_INTERRUPTIBLE);
4051 if (tty_hung_up_p(filp) ||
4052 !(info->flags & ASYNC_INITIALIZED)) {
4053#ifdef SERIAL_DO_RESTART
4054 if (info->flags & ASYNC_HUP_NOTIFY)
4055 retval = -EAGAIN;
4056 else
4057 retval = -ERESTARTSYS;
4058#else
4059 retval = -EAGAIN;
4060#endif
4061 break;
4062 }
4063 if (!(info->flags & ASYNC_CLOSING) && do_clocal)
4064 /* && (do_clocal || DCD_IS_ASSERTED) */
4065 break;
4066 if (signal_pending(current)) {
4067 retval = -ERESTARTSYS;
4068 break;
4069 }
4070#ifdef SERIAL_DEBUG_OPEN
4071 printk("block_til_ready blocking: ttyS%d, count = %d\n",
4072 info->line, info->count);
4073#endif
4074 tty_unlock();
4075 schedule();
4076 tty_lock();
4077 }
4078 set_current_state(TASK_RUNNING);
4079 remove_wait_queue(&info->open_wait, &wait);
4080 if (extra_count)
4081 info->count++;
4082 info->blocked_open--;
4083#ifdef SERIAL_DEBUG_OPEN
4084 printk("block_til_ready after blocking: ttyS%d, count = %d\n",
4085 info->line, info->count);
4086#endif
4087 if (retval)
4088 return retval;
4089 info->flags |= ASYNC_NORMAL_ACTIVE;
4090 return 0;
4091}
4092
4093static void
4094deinit_port(struct e100_serial *info)
4095{
4096 if (info->dma_out_enabled) {
4097 cris_free_dma(info->dma_out_nbr, info->dma_out_irq_description);
4098 free_irq(info->dma_out_irq_nbr, info);
4099 }
4100 if (info->dma_in_enabled) {
4101 cris_free_dma(info->dma_in_nbr, info->dma_in_irq_description);
4102 free_irq(info->dma_in_irq_nbr, info);
4103 }
4104}
4105
4106/*
4107 * This routine is called whenever a serial port is opened.
4108 * It performs the serial-specific initialization for the tty structure.
4109 */
4110static int
4111rs_open(struct tty_struct *tty, struct file * filp)
4112{
4113 struct e100_serial *info;
4114 int retval, line;
4115 unsigned long page;
4116 int allocated_resources = 0;
4117
4118 /* find which port we want to open */
4119 line = tty->index;
4120
4121 if (line < 0 || line >= NR_PORTS)
4122 return -ENODEV;
4123
4124 /* find the corresponding e100_serial struct in the table */
4125 info = rs_table + line;
4126
4127 /* don't allow the opening of ports that are not enabled in the HW config */
4128 if (!info->enabled)
4129 return -ENODEV;
4130
4131#ifdef SERIAL_DEBUG_OPEN
4132 printk("[%d] rs_open %s, count = %d\n", current->pid, tty->name,
4133 info->count);
4134#endif
4135
4136 info->count++;
4137 tty->driver_data = info;
4138 info->port.tty = tty;
4139
4140 info->port.tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
4141
4142 if (!tmp_buf) {
4143 page = get_zeroed_page(GFP_KERNEL);
4144 if (!page) {
4145 return -ENOMEM;
4146 }
4147 if (tmp_buf)
4148 free_page(page);
4149 else
4150 tmp_buf = (unsigned char *) page;
4151 }
4152
4153 /*
4154 * If the port is in the middle of closing, bail out now
4155 */
4156 if (tty_hung_up_p(filp) ||
4157 (info->flags & ASYNC_CLOSING)) {
4158 wait_event_interruptible_tty(info->close_wait,
4159 !(info->flags & ASYNC_CLOSING));
4160#ifdef SERIAL_DO_RESTART
4161 return ((info->flags & ASYNC_HUP_NOTIFY) ?
4162 -EAGAIN : -ERESTARTSYS);
4163#else
4164 return -EAGAIN;
4165#endif
4166 }
4167
4168 /*
4169 * If DMA is enabled try to allocate the irq's.
4170 */
4171 if (info->count == 1) {
4172 allocated_resources = 1;
4173 if (info->dma_in_enabled) {
4174 if (request_irq(info->dma_in_irq_nbr,
4175 rec_interrupt,
4176 info->dma_in_irq_flags,
4177 info->dma_in_irq_description,
4178 info)) {
4179 printk(KERN_WARNING "DMA irq '%s' busy; "
4180 "falling back to non-DMA mode\n",
4181 info->dma_in_irq_description);
4182 /* Make sure we never try to use DMA in */
4183 /* for the port again. */
4184 info->dma_in_enabled = 0;
4185 } else if (cris_request_dma(info->dma_in_nbr,
4186 info->dma_in_irq_description,
4187 DMA_VERBOSE_ON_ERROR,
4188 info->dma_owner)) {
4189 free_irq(info->dma_in_irq_nbr, info);
4190 printk(KERN_WARNING "DMA '%s' busy; "
4191 "falling back to non-DMA mode\n",
4192 info->dma_in_irq_description);
4193 /* Make sure we never try to use DMA in */
4194 /* for the port again. */
4195 info->dma_in_enabled = 0;
4196 }
4197#ifdef SERIAL_DEBUG_OPEN
4198 else
4199 printk(KERN_DEBUG "DMA irq '%s' allocated\n",
4200 info->dma_in_irq_description);
4201#endif
4202 }
4203 if (info->dma_out_enabled) {
4204 if (request_irq(info->dma_out_irq_nbr,
4205 tr_interrupt,
4206 info->dma_out_irq_flags,
4207 info->dma_out_irq_description,
4208 info)) {
4209 printk(KERN_WARNING "DMA irq '%s' busy; "
4210 "falling back to non-DMA mode\n",
4211 info->dma_out_irq_description);
4212 /* Make sure we never try to use DMA out */
4213 /* for the port again. */
4214 info->dma_out_enabled = 0;
4215 } else if (cris_request_dma(info->dma_out_nbr,
4216 info->dma_out_irq_description,
4217 DMA_VERBOSE_ON_ERROR,
4218 info->dma_owner)) {
4219 free_irq(info->dma_out_irq_nbr, info);
4220 printk(KERN_WARNING "DMA '%s' busy; "
4221 "falling back to non-DMA mode\n",
4222 info->dma_out_irq_description);
4223 /* Make sure we never try to use DMA out */
4224 /* for the port again. */
4225 info->dma_out_enabled = 0;
4226 }
4227#ifdef SERIAL_DEBUG_OPEN
4228 else
4229 printk(KERN_DEBUG "DMA irq '%s' allocated\n",
4230 info->dma_out_irq_description);
4231#endif
4232 }
4233 }
4234
4235 /*
4236 * Start up the serial port
4237 */
4238
4239 retval = startup(info);
4240 if (retval) {
4241 if (allocated_resources)
4242 deinit_port(info);
4243
4244 /* FIXME Decrease count info->count here too? */
4245 return retval;
4246 }
4247
4248
4249 retval = block_til_ready(tty, filp, info);
4250 if (retval) {
4251#ifdef SERIAL_DEBUG_OPEN
4252 printk("rs_open returning after block_til_ready with %d\n",
4253 retval);
4254#endif
4255 if (allocated_resources)
4256 deinit_port(info);
4257
4258 return retval;
4259 }
4260
4261 if ((info->count == 1) && (info->flags & ASYNC_SPLIT_TERMIOS)) {
4262 *tty->termios = info->normal_termios;
4263 change_speed(info);
4264 }
4265
4266#ifdef SERIAL_DEBUG_OPEN
4267 printk("rs_open ttyS%d successful...\n", info->line);
4268#endif
4269 DLOG_INT_TRIG( log_int_pos = 0);
4270
4271 DFLIP( if (info->line == SERIAL_DEBUG_LINE) {
4272 info->icount.rx = 0;
4273 } );
4274
4275 return 0;
4276}
4277
4278#ifdef CONFIG_PROC_FS
4279/*
4280 * /proc fs routines....
4281 */
4282
4283static void seq_line_info(struct seq_file *m, struct e100_serial *info)
4284{
4285 unsigned long tmp;
4286
4287 seq_printf(m, "%d: uart:E100 port:%lX irq:%d",
4288 info->line, (unsigned long)info->ioport, info->irq);
4289
4290 if (!info->ioport || (info->type == PORT_UNKNOWN)) {
4291 seq_printf(m, "\n");
4292 return;
4293 }
4294
4295 seq_printf(m, " baud:%d", info->baud);
4296 seq_printf(m, " tx:%lu rx:%lu",
4297 (unsigned long)info->icount.tx,
4298 (unsigned long)info->icount.rx);
4299 tmp = CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
4300 if (tmp)
4301 seq_printf(m, " tx_pend:%lu/%lu",
4302 (unsigned long)tmp,
4303 (unsigned long)SERIAL_XMIT_SIZE);
4304
4305 seq_printf(m, " rx_pend:%lu/%lu",
4306 (unsigned long)info->recv_cnt,
4307 (unsigned long)info->max_recv_cnt);
4308
4309#if 1
4310 if (info->port.tty) {
4311 if (info->port.tty->stopped)
4312 seq_printf(m, " stopped:%i",
4313 (int)info->port.tty->stopped);
4314 if (info->port.tty->hw_stopped)
4315 seq_printf(m, " hw_stopped:%i",
4316 (int)info->port.tty->hw_stopped);
4317 }
4318
4319 {
4320 unsigned char rstat = info->ioport[REG_STATUS];
4321 if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect))
4322 seq_printf(m, " xoff_detect:1");
4323 }
4324
4325#endif
4326
4327 if (info->icount.frame)
4328 seq_printf(m, " fe:%lu", (unsigned long)info->icount.frame);
4329
4330 if (info->icount.parity)
4331 seq_printf(m, " pe:%lu", (unsigned long)info->icount.parity);
4332
4333 if (info->icount.brk)
4334 seq_printf(m, " brk:%lu", (unsigned long)info->icount.brk);
4335
4336 if (info->icount.overrun)
4337 seq_printf(m, " oe:%lu", (unsigned long)info->icount.overrun);
4338
4339 /*
4340 * Last thing is the RS-232 status lines
4341 */
4342 if (!E100_RTS_GET(info))
4343 seq_puts(m, "|RTS");
4344 if (!E100_CTS_GET(info))
4345 seq_puts(m, "|CTS");
4346 if (!E100_DTR_GET(info))
4347 seq_puts(m, "|DTR");
4348 if (!E100_DSR_GET(info))
4349 seq_puts(m, "|DSR");
4350 if (!E100_CD_GET(info))
4351 seq_puts(m, "|CD");
4352 if (!E100_RI_GET(info))
4353 seq_puts(m, "|RI");
4354 seq_puts(m, "\n");
4355}
4356
4357
4358static int crisv10_proc_show(struct seq_file *m, void *v)
4359{
4360 int i;
4361
4362 seq_printf(m, "serinfo:1.0 driver:%s\n", serial_version);
4363
4364 for (i = 0; i < NR_PORTS; i++) {
4365 if (!rs_table[i].enabled)
4366 continue;
4367 seq_line_info(m, &rs_table[i]);
4368 }
4369#ifdef DEBUG_LOG_INCLUDED
4370 for (i = 0; i < debug_log_pos; i++) {
4371 seq_printf(m, "%-4i %lu.%lu ",
4372 i, debug_log[i].time,
4373 timer_data_to_ns(debug_log[i].timer_data));
4374 seq_printf(m, debug_log[i].string, debug_log[i].value);
4375 }
4376 seq_printf(m, "debug_log %i/%i\n", i, DEBUG_LOG_SIZE);
4377 debug_log_pos = 0;
4378#endif
4379 return 0;
4380}
4381
4382static int crisv10_proc_open(struct inode *inode, struct file *file)
4383{
4384 return single_open(file, crisv10_proc_show, NULL);
4385}
4386
4387static const struct file_operations crisv10_proc_fops = {
4388 .owner = THIS_MODULE,
4389 .open = crisv10_proc_open,
4390 .read = seq_read,
4391 .llseek = seq_lseek,
4392 .release = single_release,
4393};
4394#endif
4395
4396
4397/* Finally, routines used to initialize the serial driver. */
4398
4399static void show_serial_version(void)
4400{
4401 printk(KERN_INFO
4402 "ETRAX 100LX serial-driver %s, "
4403 "(c) 2000-2004 Axis Communications AB\r\n",
4404 &serial_version[11]); /* "$Revision: x.yy" */
4405}
4406
4407/* rs_init inits the driver at boot (using the module_init chain) */
4408
4409static const struct tty_operations rs_ops = {
4410 .open = rs_open,
4411 .close = rs_close,
4412 .write = rs_write,
4413 .flush_chars = rs_flush_chars,
4414 .write_room = rs_write_room,
4415 .chars_in_buffer = rs_chars_in_buffer,
4416 .flush_buffer = rs_flush_buffer,
4417 .ioctl = rs_ioctl,
4418 .throttle = rs_throttle,
4419 .unthrottle = rs_unthrottle,
4420 .set_termios = rs_set_termios,
4421 .stop = rs_stop,
4422 .start = rs_start,
4423 .hangup = rs_hangup,
4424 .break_ctl = rs_break,
4425 .send_xchar = rs_send_xchar,
4426 .wait_until_sent = rs_wait_until_sent,
4427 .tiocmget = rs_tiocmget,
4428 .tiocmset = rs_tiocmset,
4429#ifdef CONFIG_PROC_FS
4430 .proc_fops = &crisv10_proc_fops,
4431#endif
4432};
4433
4434static int __init rs_init(void)
4435{
4436 int i;
4437 struct e100_serial *info;
4438 struct tty_driver *driver = alloc_tty_driver(NR_PORTS);
4439
4440 if (!driver)
4441 return -ENOMEM;
4442
4443 show_serial_version();
4444
4445 /* Setup the timed flush handler system */
4446
4447#if !defined(CONFIG_ETRAX_SERIAL_FAST_TIMER)
4448 setup_timer(&flush_timer, timed_flush_handler, 0);
4449 mod_timer(&flush_timer, jiffies + 5);
4450#endif
4451
4452#if defined(CONFIG_ETRAX_RS485)
4453#if defined(CONFIG_ETRAX_RS485_ON_PA)
4454 if (cris_io_interface_allocate_pins(if_ser0, 'a', rs485_pa_bit,
4455 rs485_pa_bit)) {
4456 printk(KERN_CRIT "ETRAX100LX serial: Could not allocate "
4457 "RS485 pin\n");
4458 put_tty_driver(driver);
4459 return -EBUSY;
4460 }
4461#endif
4462#if defined(CONFIG_ETRAX_RS485_ON_PORT_G)
4463 if (cris_io_interface_allocate_pins(if_ser0, 'g', rs485_pa_bit,
4464 rs485_port_g_bit)) {
4465 printk(KERN_CRIT "ETRAX100LX serial: Could not allocate "
4466 "RS485 pin\n");
4467 put_tty_driver(driver);
4468 return -EBUSY;
4469 }
4470#endif
4471#endif
4472
4473 /* Initialize the tty_driver structure */
4474
4475 driver->driver_name = "serial";
4476 driver->name = "ttyS";
4477 driver->major = TTY_MAJOR;
4478 driver->minor_start = 64;
4479 driver->type = TTY_DRIVER_TYPE_SERIAL;
4480 driver->subtype = SERIAL_TYPE_NORMAL;
4481 driver->init_termios = tty_std_termios;
4482 driver->init_termios.c_cflag =
4483 B115200 | CS8 | CREAD | HUPCL | CLOCAL; /* is normally B9600 default... */
4484 driver->init_termios.c_ispeed = 115200;
4485 driver->init_termios.c_ospeed = 115200;
4486 driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
4487
4488 tty_set_operations(driver, &rs_ops);
4489 serial_driver = driver;
4490 if (tty_register_driver(driver))
4491 panic("Couldn't register serial driver\n");
4492 /* do some initializing for the separate ports */
4493
4494 for (i = 0, info = rs_table; i < NR_PORTS; i++,info++) {
4495 if (info->enabled) {
4496 if (cris_request_io_interface(info->io_if,
4497 info->io_if_description)) {
4498 printk(KERN_CRIT "ETRAX100LX async serial: "
4499 "Could not allocate IO pins for "
4500 "%s, port %d\n",
4501 info->io_if_description, i);
4502 info->enabled = 0;
4503 }
4504 }
4505 info->uses_dma_in = 0;
4506 info->uses_dma_out = 0;
4507 info->line = i;
4508 info->port.tty = NULL;
4509 info->type = PORT_ETRAX;
4510 info->tr_running = 0;
4511 info->forced_eop = 0;
4512 info->baud_base = DEF_BAUD_BASE;
4513 info->custom_divisor = 0;
4514 info->flags = 0;
4515 info->close_delay = 5*HZ/10;
4516 info->closing_wait = 30*HZ;
4517 info->x_char = 0;
4518 info->event = 0;
4519 info->count = 0;
4520 info->blocked_open = 0;
4521 info->normal_termios = driver->init_termios;
4522 init_waitqueue_head(&info->open_wait);
4523 init_waitqueue_head(&info->close_wait);
4524 info->xmit.buf = NULL;
4525 info->xmit.tail = info->xmit.head = 0;
4526 info->first_recv_buffer = info->last_recv_buffer = NULL;
4527 info->recv_cnt = info->max_recv_cnt = 0;
4528 info->last_tx_active_usec = 0;
4529 info->last_tx_active = 0;
4530
4531#if defined(CONFIG_ETRAX_RS485)
4532 /* Set sane defaults */
4533 info->rs485.flags &= ~(SER_RS485_RTS_ON_SEND);
4534 info->rs485.flags |= SER_RS485_RTS_AFTER_SEND;
4535 info->rs485.flags &= ~(SER_RS485_RTS_BEFORE_SEND);
4536 info->rs485.delay_rts_before_send = 0;
4537 info->rs485.flags &= ~(SER_RS485_ENABLED);
4538#endif
4539 INIT_WORK(&info->work, do_softint);
4540
4541 if (info->enabled) {
4542 printk(KERN_INFO "%s%d at %p is a builtin UART with DMA\n",
4543 serial_driver->name, info->line, info->ioport);
4544 }
4545 }
4546#ifdef CONFIG_ETRAX_FAST_TIMER
4547#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
4548 memset(fast_timers, 0, sizeof(fast_timers));
4549#endif
4550#ifdef CONFIG_ETRAX_RS485
4551 memset(fast_timers_rs485, 0, sizeof(fast_timers_rs485));
4552#endif
4553 fast_timer_init();
4554#endif
4555
4556#ifndef CONFIG_SVINTO_SIM
4557#ifndef CONFIG_ETRAX_KGDB
4558 /* Not needed in simulator. May only complicate stuff. */
4559 /* hook the irq's for DMA channel 6 and 7, serial output and input, and some more... */
4560
4561 if (request_irq(SERIAL_IRQ_NBR, ser_interrupt,
4562 IRQF_SHARED | IRQF_DISABLED, "serial ", driver))
4563 panic("%s: Failed to request irq8", __func__);
4564
4565#endif
4566#endif /* CONFIG_SVINTO_SIM */
4567
4568 return 0;
4569}
4570
4571/* this makes sure that rs_init is called during kernel boot */
4572
4573module_init(rs_init);
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