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Diffstat (limited to 'drivers/tty/serial/8250/m32r_sio.c')
-rw-r--r--drivers/tty/serial/8250/m32r_sio.c1191
1 files changed, 1191 insertions, 0 deletions
diff --git a/drivers/tty/serial/8250/m32r_sio.c b/drivers/tty/serial/8250/m32r_sio.c
new file mode 100644
index 000000000000..94a6792bf97b
--- /dev/null
+++ b/drivers/tty/serial/8250/m32r_sio.c
@@ -0,0 +1,1191 @@
1/*
2 * m32r_sio.c
3 *
4 * Driver for M32R serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 * Based on drivers/serial/8250.c.
8 *
9 * Copyright (C) 2001 Russell King.
10 * Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 */
17
18/*
19 * A note about mapbase / membase
20 *
21 * mapbase is the physical address of the IO port. Currently, we don't
22 * support this very well, and it may well be dropped from this driver
23 * in future. As such, mapbase should be NULL.
24 *
25 * membase is an 'ioremapped' cookie. This is compatible with the old
26 * serial.c driver, and is currently the preferred form.
27 */
28
29#if defined(CONFIG_SERIAL_M32R_SIO_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
30#define SUPPORT_SYSRQ
31#endif
32
33#include <linux/module.h>
34#include <linux/tty.h>
35#include <linux/tty_flip.h>
36#include <linux/ioport.h>
37#include <linux/init.h>
38#include <linux/console.h>
39#include <linux/sysrq.h>
40#include <linux/serial.h>
41#include <linux/serialP.h>
42#include <linux/delay.h>
43
44#include <asm/m32r.h>
45#include <asm/io.h>
46#include <asm/irq.h>
47
48#define PORT_M32R_BASE PORT_M32R_SIO
49#define PORT_INDEX(x) (x - PORT_M32R_BASE + 1)
50#define BAUD_RATE 115200
51
52#include <linux/serial_core.h>
53#include "m32r_sio.h"
54#include "m32r_sio_reg.h"
55
56/*
57 * Debugging.
58 */
59#if 0
60#define DEBUG_AUTOCONF(fmt...) printk(fmt)
61#else
62#define DEBUG_AUTOCONF(fmt...) do { } while (0)
63#endif
64
65#if 0
66#define DEBUG_INTR(fmt...) printk(fmt)
67#else
68#define DEBUG_INTR(fmt...) do { } while (0)
69#endif
70
71#define PASS_LIMIT 256
72
73/*
74 * We default to IRQ0 for the "no irq" hack. Some
75 * machine types want others as well - they're free
76 * to redefine this in their header file.
77 */
78#define is_real_interrupt(irq) ((irq) != 0)
79
80#define BASE_BAUD 115200
81
82/* Standard COM flags */
83#define STD_COM_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST)
84
85/*
86 * SERIAL_PORT_DFNS tells us about built-in ports that have no
87 * standard enumeration mechanism. Platforms that can find all
88 * serial ports via mechanisms like ACPI or PCI need not supply it.
89 */
90#if defined(CONFIG_PLAT_USRV)
91
92#define SERIAL_PORT_DFNS \
93 /* UART CLK PORT IRQ FLAGS */ \
94 { 0, BASE_BAUD, 0x3F8, PLD_IRQ_UART0, STD_COM_FLAGS }, /* ttyS0 */ \
95 { 0, BASE_BAUD, 0x2F8, PLD_IRQ_UART1, STD_COM_FLAGS }, /* ttyS1 */
96
97#else /* !CONFIG_PLAT_USRV */
98
99#if defined(CONFIG_SERIAL_M32R_PLDSIO)
100#define SERIAL_PORT_DFNS \
101 { 0, BASE_BAUD, ((unsigned long)PLD_ESIO0CR), PLD_IRQ_SIO0_RCV, \
102 STD_COM_FLAGS }, /* ttyS0 */
103#else
104#define SERIAL_PORT_DFNS \
105 { 0, BASE_BAUD, M32R_SIO_OFFSET, M32R_IRQ_SIO0_R, \
106 STD_COM_FLAGS }, /* ttyS0 */
107#endif
108
109#endif /* !CONFIG_PLAT_USRV */
110
111static struct old_serial_port old_serial_port[] = {
112 SERIAL_PORT_DFNS
113};
114
115#define UART_NR ARRAY_SIZE(old_serial_port)
116
117struct uart_sio_port {
118 struct uart_port port;
119 struct timer_list timer; /* "no irq" timer */
120 struct list_head list; /* ports on this IRQ */
121 unsigned short rev;
122 unsigned char acr;
123 unsigned char ier;
124 unsigned char lcr;
125 unsigned char mcr_mask; /* mask of user bits */
126 unsigned char mcr_force; /* mask of forced bits */
127 unsigned char lsr_break_flag;
128
129 /*
130 * We provide a per-port pm hook.
131 */
132 void (*pm)(struct uart_port *port,
133 unsigned int state, unsigned int old);
134};
135
136struct irq_info {
137 spinlock_t lock;
138 struct list_head *head;
139};
140
141static struct irq_info irq_lists[NR_IRQS];
142
143/*
144 * Here we define the default xmit fifo size used for each type of UART.
145 */
146static const struct serial_uart_config uart_config[] = {
147 [PORT_UNKNOWN] = {
148 .name = "unknown",
149 .dfl_xmit_fifo_size = 1,
150 .flags = 0,
151 },
152 [PORT_INDEX(PORT_M32R_SIO)] = {
153 .name = "M32RSIO",
154 .dfl_xmit_fifo_size = 1,
155 .flags = 0,
156 },
157};
158
159#ifdef CONFIG_SERIAL_M32R_PLDSIO
160
161#define __sio_in(x) inw((unsigned long)(x))
162#define __sio_out(v,x) outw((v),(unsigned long)(x))
163
164static inline void sio_set_baud_rate(unsigned long baud)
165{
166 unsigned short sbaud;
167 sbaud = (boot_cpu_data.bus_clock / (baud * 4))-1;
168 __sio_out(sbaud, PLD_ESIO0BAUR);
169}
170
171static void sio_reset(void)
172{
173 unsigned short tmp;
174
175 tmp = __sio_in(PLD_ESIO0RXB);
176 tmp = __sio_in(PLD_ESIO0RXB);
177 tmp = __sio_in(PLD_ESIO0CR);
178 sio_set_baud_rate(BAUD_RATE);
179 __sio_out(0x0300, PLD_ESIO0CR);
180 __sio_out(0x0003, PLD_ESIO0CR);
181}
182
183static void sio_init(void)
184{
185 unsigned short tmp;
186
187 tmp = __sio_in(PLD_ESIO0RXB);
188 tmp = __sio_in(PLD_ESIO0RXB);
189 tmp = __sio_in(PLD_ESIO0CR);
190 __sio_out(0x0300, PLD_ESIO0CR);
191 __sio_out(0x0003, PLD_ESIO0CR);
192}
193
194static void sio_error(int *status)
195{
196 printk("SIO0 error[%04x]\n", *status);
197 do {
198 sio_init();
199 } while ((*status = __sio_in(PLD_ESIO0CR)) != 3);
200}
201
202#else /* not CONFIG_SERIAL_M32R_PLDSIO */
203
204#define __sio_in(x) inl(x)
205#define __sio_out(v,x) outl((v),(x))
206
207static inline void sio_set_baud_rate(unsigned long baud)
208{
209 unsigned long i, j;
210
211 i = boot_cpu_data.bus_clock / (baud * 16);
212 j = (boot_cpu_data.bus_clock - (i * baud * 16)) / baud;
213 i -= 1;
214 j = (j + 1) >> 1;
215
216 __sio_out(i, M32R_SIO0_BAUR_PORTL);
217 __sio_out(j, M32R_SIO0_RBAUR_PORTL);
218}
219
220static void sio_reset(void)
221{
222 __sio_out(0x00000300, M32R_SIO0_CR_PORTL); /* init status */
223 __sio_out(0x00000800, M32R_SIO0_MOD1_PORTL); /* 8bit */
224 __sio_out(0x00000080, M32R_SIO0_MOD0_PORTL); /* 1stop non */
225 sio_set_baud_rate(BAUD_RATE);
226 __sio_out(0x00000000, M32R_SIO0_TRCR_PORTL);
227 __sio_out(0x00000003, M32R_SIO0_CR_PORTL); /* RXCEN */
228}
229
230static void sio_init(void)
231{
232 unsigned int tmp;
233
234 tmp = __sio_in(M32R_SIO0_RXB_PORTL);
235 tmp = __sio_in(M32R_SIO0_RXB_PORTL);
236 tmp = __sio_in(M32R_SIO0_STS_PORTL);
237 __sio_out(0x00000003, M32R_SIO0_CR_PORTL);
238}
239
240static void sio_error(int *status)
241{
242 printk("SIO0 error[%04x]\n", *status);
243 do {
244 sio_init();
245 } while ((*status = __sio_in(M32R_SIO0_CR_PORTL)) != 3);
246}
247
248#endif /* CONFIG_SERIAL_M32R_PLDSIO */
249
250static unsigned int sio_in(struct uart_sio_port *up, int offset)
251{
252 return __sio_in(up->port.iobase + offset);
253}
254
255static void sio_out(struct uart_sio_port *up, int offset, int value)
256{
257 __sio_out(value, up->port.iobase + offset);
258}
259
260static unsigned int serial_in(struct uart_sio_port *up, int offset)
261{
262 if (!offset)
263 return 0;
264
265 return __sio_in(offset);
266}
267
268static void serial_out(struct uart_sio_port *up, int offset, int value)
269{
270 if (!offset)
271 return;
272
273 __sio_out(value, offset);
274}
275
276static void m32r_sio_stop_tx(struct uart_port *port)
277{
278 struct uart_sio_port *up = (struct uart_sio_port *)port;
279
280 if (up->ier & UART_IER_THRI) {
281 up->ier &= ~UART_IER_THRI;
282 serial_out(up, UART_IER, up->ier);
283 }
284}
285
286static void m32r_sio_start_tx(struct uart_port *port)
287{
288#ifdef CONFIG_SERIAL_M32R_PLDSIO
289 struct uart_sio_port *up = (struct uart_sio_port *)port;
290 struct circ_buf *xmit = &up->port.state->xmit;
291
292 if (!(up->ier & UART_IER_THRI)) {
293 up->ier |= UART_IER_THRI;
294 serial_out(up, UART_IER, up->ier);
295 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
296 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
297 up->port.icount.tx++;
298 }
299 while((serial_in(up, UART_LSR) & UART_EMPTY) != UART_EMPTY);
300#else
301 struct uart_sio_port *up = (struct uart_sio_port *)port;
302
303 if (!(up->ier & UART_IER_THRI)) {
304 up->ier |= UART_IER_THRI;
305 serial_out(up, UART_IER, up->ier);
306 }
307#endif
308}
309
310static void m32r_sio_stop_rx(struct uart_port *port)
311{
312 struct uart_sio_port *up = (struct uart_sio_port *)port;
313
314 up->ier &= ~UART_IER_RLSI;
315 up->port.read_status_mask &= ~UART_LSR_DR;
316 serial_out(up, UART_IER, up->ier);
317}
318
319static void m32r_sio_enable_ms(struct uart_port *port)
320{
321 struct uart_sio_port *up = (struct uart_sio_port *)port;
322
323 up->ier |= UART_IER_MSI;
324 serial_out(up, UART_IER, up->ier);
325}
326
327static void receive_chars(struct uart_sio_port *up, int *status)
328{
329 struct tty_struct *tty = up->port.state->port.tty;
330 unsigned char ch;
331 unsigned char flag;
332 int max_count = 256;
333
334 do {
335 ch = sio_in(up, SIORXB);
336 flag = TTY_NORMAL;
337 up->port.icount.rx++;
338
339 if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
340 UART_LSR_FE | UART_LSR_OE))) {
341 /*
342 * For statistics only
343 */
344 if (*status & UART_LSR_BI) {
345 *status &= ~(UART_LSR_FE | UART_LSR_PE);
346 up->port.icount.brk++;
347 /*
348 * We do the SysRQ and SAK checking
349 * here because otherwise the break
350 * may get masked by ignore_status_mask
351 * or read_status_mask.
352 */
353 if (uart_handle_break(&up->port))
354 goto ignore_char;
355 } else if (*status & UART_LSR_PE)
356 up->port.icount.parity++;
357 else if (*status & UART_LSR_FE)
358 up->port.icount.frame++;
359 if (*status & UART_LSR_OE)
360 up->port.icount.overrun++;
361
362 /*
363 * Mask off conditions which should be ingored.
364 */
365 *status &= up->port.read_status_mask;
366
367 if (up->port.line == up->port.cons->index) {
368 /* Recover the break flag from console xmit */
369 *status |= up->lsr_break_flag;
370 up->lsr_break_flag = 0;
371 }
372
373 if (*status & UART_LSR_BI) {
374 DEBUG_INTR("handling break....");
375 flag = TTY_BREAK;
376 } else if (*status & UART_LSR_PE)
377 flag = TTY_PARITY;
378 else if (*status & UART_LSR_FE)
379 flag = TTY_FRAME;
380 }
381 if (uart_handle_sysrq_char(&up->port, ch))
382 goto ignore_char;
383 if ((*status & up->port.ignore_status_mask) == 0)
384 tty_insert_flip_char(tty, ch, flag);
385
386 if (*status & UART_LSR_OE) {
387 /*
388 * Overrun is special, since it's reported
389 * immediately, and doesn't affect the current
390 * character.
391 */
392 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
393 }
394 ignore_char:
395 *status = serial_in(up, UART_LSR);
396 } while ((*status & UART_LSR_DR) && (max_count-- > 0));
397 tty_flip_buffer_push(tty);
398}
399
400static void transmit_chars(struct uart_sio_port *up)
401{
402 struct circ_buf *xmit = &up->port.state->xmit;
403 int count;
404
405 if (up->port.x_char) {
406#ifndef CONFIG_SERIAL_M32R_PLDSIO /* XXX */
407 serial_out(up, UART_TX, up->port.x_char);
408#endif
409 up->port.icount.tx++;
410 up->port.x_char = 0;
411 return;
412 }
413 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
414 m32r_sio_stop_tx(&up->port);
415 return;
416 }
417
418 count = up->port.fifosize;
419 do {
420 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
421 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
422 up->port.icount.tx++;
423 if (uart_circ_empty(xmit))
424 break;
425 while (!(serial_in(up, UART_LSR) & UART_LSR_THRE));
426
427 } while (--count > 0);
428
429 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
430 uart_write_wakeup(&up->port);
431
432 DEBUG_INTR("THRE...");
433
434 if (uart_circ_empty(xmit))
435 m32r_sio_stop_tx(&up->port);
436}
437
438/*
439 * This handles the interrupt from one port.
440 */
441static inline void m32r_sio_handle_port(struct uart_sio_port *up,
442 unsigned int status)
443{
444 DEBUG_INTR("status = %x...", status);
445
446 if (status & 0x04)
447 receive_chars(up, &status);
448 if (status & 0x01)
449 transmit_chars(up);
450}
451
452/*
453 * This is the serial driver's interrupt routine.
454 *
455 * Arjan thinks the old way was overly complex, so it got simplified.
456 * Alan disagrees, saying that need the complexity to handle the weird
457 * nature of ISA shared interrupts. (This is a special exception.)
458 *
459 * In order to handle ISA shared interrupts properly, we need to check
460 * that all ports have been serviced, and therefore the ISA interrupt
461 * line has been de-asserted.
462 *
463 * This means we need to loop through all ports. checking that they
464 * don't have an interrupt pending.
465 */
466static irqreturn_t m32r_sio_interrupt(int irq, void *dev_id)
467{
468 struct irq_info *i = dev_id;
469 struct list_head *l, *end = NULL;
470 int pass_counter = 0;
471
472 DEBUG_INTR("m32r_sio_interrupt(%d)...", irq);
473
474#ifdef CONFIG_SERIAL_M32R_PLDSIO
475// if (irq == PLD_IRQ_SIO0_SND)
476// irq = PLD_IRQ_SIO0_RCV;
477#else
478 if (irq == M32R_IRQ_SIO0_S)
479 irq = M32R_IRQ_SIO0_R;
480#endif
481
482 spin_lock(&i->lock);
483
484 l = i->head;
485 do {
486 struct uart_sio_port *up;
487 unsigned int sts;
488
489 up = list_entry(l, struct uart_sio_port, list);
490
491 sts = sio_in(up, SIOSTS);
492 if (sts & 0x5) {
493 spin_lock(&up->port.lock);
494 m32r_sio_handle_port(up, sts);
495 spin_unlock(&up->port.lock);
496
497 end = NULL;
498 } else if (end == NULL)
499 end = l;
500
501 l = l->next;
502
503 if (l == i->head && pass_counter++ > PASS_LIMIT) {
504 if (sts & 0xe0)
505 sio_error(&sts);
506 break;
507 }
508 } while (l != end);
509
510 spin_unlock(&i->lock);
511
512 DEBUG_INTR("end.\n");
513
514 return IRQ_HANDLED;
515}
516
517/*
518 * To support ISA shared interrupts, we need to have one interrupt
519 * handler that ensures that the IRQ line has been deasserted
520 * before returning. Failing to do this will result in the IRQ
521 * line being stuck active, and, since ISA irqs are edge triggered,
522 * no more IRQs will be seen.
523 */
524static void serial_do_unlink(struct irq_info *i, struct uart_sio_port *up)
525{
526 spin_lock_irq(&i->lock);
527
528 if (!list_empty(i->head)) {
529 if (i->head == &up->list)
530 i->head = i->head->next;
531 list_del(&up->list);
532 } else {
533 BUG_ON(i->head != &up->list);
534 i->head = NULL;
535 }
536
537 spin_unlock_irq(&i->lock);
538}
539
540static int serial_link_irq_chain(struct uart_sio_port *up)
541{
542 struct irq_info *i = irq_lists + up->port.irq;
543 int ret, irq_flags = 0;
544
545 spin_lock_irq(&i->lock);
546
547 if (i->head) {
548 list_add(&up->list, i->head);
549 spin_unlock_irq(&i->lock);
550
551 ret = 0;
552 } else {
553 INIT_LIST_HEAD(&up->list);
554 i->head = &up->list;
555 spin_unlock_irq(&i->lock);
556
557 ret = request_irq(up->port.irq, m32r_sio_interrupt,
558 irq_flags, "SIO0-RX", i);
559 ret |= request_irq(up->port.irq + 1, m32r_sio_interrupt,
560 irq_flags, "SIO0-TX", i);
561 if (ret < 0)
562 serial_do_unlink(i, up);
563 }
564
565 return ret;
566}
567
568static void serial_unlink_irq_chain(struct uart_sio_port *up)
569{
570 struct irq_info *i = irq_lists + up->port.irq;
571
572 BUG_ON(i->head == NULL);
573
574 if (list_empty(i->head)) {
575 free_irq(up->port.irq, i);
576 free_irq(up->port.irq + 1, i);
577 }
578
579 serial_do_unlink(i, up);
580}
581
582/*
583 * This function is used to handle ports that do not have an interrupt.
584 */
585static void m32r_sio_timeout(unsigned long data)
586{
587 struct uart_sio_port *up = (struct uart_sio_port *)data;
588 unsigned int timeout;
589 unsigned int sts;
590
591 sts = sio_in(up, SIOSTS);
592 if (sts & 0x5) {
593 spin_lock(&up->port.lock);
594 m32r_sio_handle_port(up, sts);
595 spin_unlock(&up->port.lock);
596 }
597
598 timeout = up->port.timeout;
599 timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
600 mod_timer(&up->timer, jiffies + timeout);
601}
602
603static unsigned int m32r_sio_tx_empty(struct uart_port *port)
604{
605 struct uart_sio_port *up = (struct uart_sio_port *)port;
606 unsigned long flags;
607 unsigned int ret;
608
609 spin_lock_irqsave(&up->port.lock, flags);
610 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
611 spin_unlock_irqrestore(&up->port.lock, flags);
612
613 return ret;
614}
615
616static unsigned int m32r_sio_get_mctrl(struct uart_port *port)
617{
618 return 0;
619}
620
621static void m32r_sio_set_mctrl(struct uart_port *port, unsigned int mctrl)
622{
623
624}
625
626static void m32r_sio_break_ctl(struct uart_port *port, int break_state)
627{
628
629}
630
631static int m32r_sio_startup(struct uart_port *port)
632{
633 struct uart_sio_port *up = (struct uart_sio_port *)port;
634 int retval;
635
636 sio_init();
637
638 /*
639 * If the "interrupt" for this port doesn't correspond with any
640 * hardware interrupt, we use a timer-based system. The original
641 * driver used to do this with IRQ0.
642 */
643 if (!is_real_interrupt(up->port.irq)) {
644 unsigned int timeout = up->port.timeout;
645
646 timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
647
648 up->timer.data = (unsigned long)up;
649 mod_timer(&up->timer, jiffies + timeout);
650 } else {
651 retval = serial_link_irq_chain(up);
652 if (retval)
653 return retval;
654 }
655
656 /*
657 * Finally, enable interrupts. Note: Modem status interrupts
658 * are set via set_termios(), which will be occurring imminently
659 * anyway, so we don't enable them here.
660 * - M32R_SIO: 0x0c
661 * - M32R_PLDSIO: 0x04
662 */
663 up->ier = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI;
664 sio_out(up, SIOTRCR, up->ier);
665
666 /*
667 * And clear the interrupt registers again for luck.
668 */
669 sio_reset();
670
671 return 0;
672}
673
674static void m32r_sio_shutdown(struct uart_port *port)
675{
676 struct uart_sio_port *up = (struct uart_sio_port *)port;
677
678 /*
679 * Disable interrupts from this port
680 */
681 up->ier = 0;
682 sio_out(up, SIOTRCR, 0);
683
684 /*
685 * Disable break condition and FIFOs
686 */
687
688 sio_init();
689
690 if (!is_real_interrupt(up->port.irq))
691 del_timer_sync(&up->timer);
692 else
693 serial_unlink_irq_chain(up);
694}
695
696static unsigned int m32r_sio_get_divisor(struct uart_port *port,
697 unsigned int baud)
698{
699 return uart_get_divisor(port, baud);
700}
701
702static void m32r_sio_set_termios(struct uart_port *port,
703 struct ktermios *termios, struct ktermios *old)
704{
705 struct uart_sio_port *up = (struct uart_sio_port *)port;
706 unsigned char cval = 0;
707 unsigned long flags;
708 unsigned int baud, quot;
709
710 switch (termios->c_cflag & CSIZE) {
711 case CS5:
712 cval = UART_LCR_WLEN5;
713 break;
714 case CS6:
715 cval = UART_LCR_WLEN6;
716 break;
717 case CS7:
718 cval = UART_LCR_WLEN7;
719 break;
720 default:
721 case CS8:
722 cval = UART_LCR_WLEN8;
723 break;
724 }
725
726 if (termios->c_cflag & CSTOPB)
727 cval |= UART_LCR_STOP;
728 if (termios->c_cflag & PARENB)
729 cval |= UART_LCR_PARITY;
730 if (!(termios->c_cflag & PARODD))
731 cval |= UART_LCR_EPAR;
732#ifdef CMSPAR
733 if (termios->c_cflag & CMSPAR)
734 cval |= UART_LCR_SPAR;
735#endif
736
737 /*
738 * Ask the core to calculate the divisor for us.
739 */
740#ifdef CONFIG_SERIAL_M32R_PLDSIO
741 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/4);
742#else
743 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
744#endif
745 quot = m32r_sio_get_divisor(port, baud);
746
747 /*
748 * Ok, we're now changing the port state. Do it with
749 * interrupts disabled.
750 */
751 spin_lock_irqsave(&up->port.lock, flags);
752
753 sio_set_baud_rate(baud);
754
755 /*
756 * Update the per-port timeout.
757 */
758 uart_update_timeout(port, termios->c_cflag, baud);
759
760 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
761 if (termios->c_iflag & INPCK)
762 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
763 if (termios->c_iflag & (BRKINT | PARMRK))
764 up->port.read_status_mask |= UART_LSR_BI;
765
766 /*
767 * Characteres to ignore
768 */
769 up->port.ignore_status_mask = 0;
770 if (termios->c_iflag & IGNPAR)
771 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
772 if (termios->c_iflag & IGNBRK) {
773 up->port.ignore_status_mask |= UART_LSR_BI;
774 /*
775 * If we're ignoring parity and break indicators,
776 * ignore overruns too (for real raw support).
777 */
778 if (termios->c_iflag & IGNPAR)
779 up->port.ignore_status_mask |= UART_LSR_OE;
780 }
781
782 /*
783 * ignore all characters if CREAD is not set
784 */
785 if ((termios->c_cflag & CREAD) == 0)
786 up->port.ignore_status_mask |= UART_LSR_DR;
787
788 /*
789 * CTS flow control flag and modem status interrupts
790 */
791 up->ier &= ~UART_IER_MSI;
792 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
793 up->ier |= UART_IER_MSI;
794
795 serial_out(up, UART_IER, up->ier);
796
797 up->lcr = cval; /* Save LCR */
798 spin_unlock_irqrestore(&up->port.lock, flags);
799}
800
801static void m32r_sio_pm(struct uart_port *port, unsigned int state,
802 unsigned int oldstate)
803{
804 struct uart_sio_port *up = (struct uart_sio_port *)port;
805
806 if (up->pm)
807 up->pm(port, state, oldstate);
808}
809
810/*
811 * Resource handling. This is complicated by the fact that resources
812 * depend on the port type. Maybe we should be claiming the standard
813 * 8250 ports, and then trying to get other resources as necessary?
814 */
815static int
816m32r_sio_request_std_resource(struct uart_sio_port *up, struct resource **res)
817{
818 unsigned int size = 8 << up->port.regshift;
819#ifndef CONFIG_SERIAL_M32R_PLDSIO
820 unsigned long start;
821#endif
822 int ret = 0;
823
824 switch (up->port.iotype) {
825 case UPIO_MEM:
826 if (up->port.mapbase) {
827#ifdef CONFIG_SERIAL_M32R_PLDSIO
828 *res = request_mem_region(up->port.mapbase, size, "serial");
829#else
830 start = up->port.mapbase;
831 *res = request_mem_region(start, size, "serial");
832#endif
833 if (!*res)
834 ret = -EBUSY;
835 }
836 break;
837
838 case UPIO_PORT:
839 *res = request_region(up->port.iobase, size, "serial");
840 if (!*res)
841 ret = -EBUSY;
842 break;
843 }
844 return ret;
845}
846
847static void m32r_sio_release_port(struct uart_port *port)
848{
849 struct uart_sio_port *up = (struct uart_sio_port *)port;
850 unsigned long start, offset = 0, size = 0;
851
852 size <<= up->port.regshift;
853
854 switch (up->port.iotype) {
855 case UPIO_MEM:
856 if (up->port.mapbase) {
857 /*
858 * Unmap the area.
859 */
860 iounmap(up->port.membase);
861 up->port.membase = NULL;
862
863 start = up->port.mapbase;
864
865 if (size)
866 release_mem_region(start + offset, size);
867 release_mem_region(start, 8 << up->port.regshift);
868 }
869 break;
870
871 case UPIO_PORT:
872 start = up->port.iobase;
873
874 if (size)
875 release_region(start + offset, size);
876 release_region(start + offset, 8 << up->port.regshift);
877 break;
878
879 default:
880 break;
881 }
882}
883
884static int m32r_sio_request_port(struct uart_port *port)
885{
886 struct uart_sio_port *up = (struct uart_sio_port *)port;
887 struct resource *res = NULL;
888 int ret = 0;
889
890 ret = m32r_sio_request_std_resource(up, &res);
891
892 /*
893 * If we have a mapbase, then request that as well.
894 */
895 if (ret == 0 && up->port.flags & UPF_IOREMAP) {
896 int size = resource_size(res);
897
898 up->port.membase = ioremap(up->port.mapbase, size);
899 if (!up->port.membase)
900 ret = -ENOMEM;
901 }
902
903 if (ret < 0) {
904 if (res)
905 release_resource(res);
906 }
907
908 return ret;
909}
910
911static void m32r_sio_config_port(struct uart_port *port, int unused)
912{
913 struct uart_sio_port *up = (struct uart_sio_port *)port;
914 unsigned long flags;
915
916 spin_lock_irqsave(&up->port.lock, flags);
917
918 up->port.type = (PORT_M32R_SIO - PORT_M32R_BASE + 1);
919 up->port.fifosize = uart_config[up->port.type].dfl_xmit_fifo_size;
920
921 spin_unlock_irqrestore(&up->port.lock, flags);
922}
923
924static int
925m32r_sio_verify_port(struct uart_port *port, struct serial_struct *ser)
926{
927 if (ser->irq >= nr_irqs || ser->irq < 0 ||
928 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
929 ser->type >= ARRAY_SIZE(uart_config))
930 return -EINVAL;
931 return 0;
932}
933
934static const char *
935m32r_sio_type(struct uart_port *port)
936{
937 int type = port->type;
938
939 if (type >= ARRAY_SIZE(uart_config))
940 type = 0;
941 return uart_config[type].name;
942}
943
944static struct uart_ops m32r_sio_pops = {
945 .tx_empty = m32r_sio_tx_empty,
946 .set_mctrl = m32r_sio_set_mctrl,
947 .get_mctrl = m32r_sio_get_mctrl,
948 .stop_tx = m32r_sio_stop_tx,
949 .start_tx = m32r_sio_start_tx,
950 .stop_rx = m32r_sio_stop_rx,
951 .enable_ms = m32r_sio_enable_ms,
952 .break_ctl = m32r_sio_break_ctl,
953 .startup = m32r_sio_startup,
954 .shutdown = m32r_sio_shutdown,
955 .set_termios = m32r_sio_set_termios,
956 .pm = m32r_sio_pm,
957 .type = m32r_sio_type,
958 .release_port = m32r_sio_release_port,
959 .request_port = m32r_sio_request_port,
960 .config_port = m32r_sio_config_port,
961 .verify_port = m32r_sio_verify_port,
962};
963
964static struct uart_sio_port m32r_sio_ports[UART_NR];
965
966static void __init m32r_sio_init_ports(void)
967{
968 struct uart_sio_port *up;
969 static int first = 1;
970 int i;
971
972 if (!first)
973 return;
974 first = 0;
975
976 for (i = 0, up = m32r_sio_ports; i < ARRAY_SIZE(old_serial_port);
977 i++, up++) {
978 up->port.iobase = old_serial_port[i].port;
979 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
980 up->port.uartclk = old_serial_port[i].baud_base * 16;
981 up->port.flags = old_serial_port[i].flags;
982 up->port.membase = old_serial_port[i].iomem_base;
983 up->port.iotype = old_serial_port[i].io_type;
984 up->port.regshift = old_serial_port[i].iomem_reg_shift;
985 up->port.ops = &m32r_sio_pops;
986 }
987}
988
989static void __init m32r_sio_register_ports(struct uart_driver *drv)
990{
991 int i;
992
993 m32r_sio_init_ports();
994
995 for (i = 0; i < UART_NR; i++) {
996 struct uart_sio_port *up = &m32r_sio_ports[i];
997
998 up->port.line = i;
999 up->port.ops = &m32r_sio_pops;
1000 init_timer(&up->timer);
1001 up->timer.function = m32r_sio_timeout;
1002
1003 up->mcr_mask = ~0;
1004 up->mcr_force = 0;
1005
1006 uart_add_one_port(drv, &up->port);
1007 }
1008}
1009
1010#ifdef CONFIG_SERIAL_M32R_SIO_CONSOLE
1011
1012/*
1013 * Wait for transmitter & holding register to empty
1014 */
1015static inline void wait_for_xmitr(struct uart_sio_port *up)
1016{
1017 unsigned int status, tmout = 10000;
1018
1019 /* Wait up to 10ms for the character(s) to be sent. */
1020 do {
1021 status = sio_in(up, SIOSTS);
1022
1023 if (--tmout == 0)
1024 break;
1025 udelay(1);
1026 } while ((status & UART_EMPTY) != UART_EMPTY);
1027
1028 /* Wait up to 1s for flow control if necessary */
1029 if (up->port.flags & UPF_CONS_FLOW) {
1030 tmout = 1000000;
1031 while (--tmout)
1032 udelay(1);
1033 }
1034}
1035
1036static void m32r_sio_console_putchar(struct uart_port *port, int ch)
1037{
1038 struct uart_sio_port *up = (struct uart_sio_port *)port;
1039
1040 wait_for_xmitr(up);
1041 sio_out(up, SIOTXB, ch);
1042}
1043
1044/*
1045 * Print a string to the serial port trying not to disturb
1046 * any possible real use of the port...
1047 *
1048 * The console_lock must be held when we get here.
1049 */
1050static void m32r_sio_console_write(struct console *co, const char *s,
1051 unsigned int count)
1052{
1053 struct uart_sio_port *up = &m32r_sio_ports[co->index];
1054 unsigned int ier;
1055
1056 /*
1057 * First save the UER then disable the interrupts
1058 */
1059 ier = sio_in(up, SIOTRCR);
1060 sio_out(up, SIOTRCR, 0);
1061
1062 uart_console_write(&up->port, s, count, m32r_sio_console_putchar);
1063
1064 /*
1065 * Finally, wait for transmitter to become empty
1066 * and restore the IER
1067 */
1068 wait_for_xmitr(up);
1069 sio_out(up, SIOTRCR, ier);
1070}
1071
1072static int __init m32r_sio_console_setup(struct console *co, char *options)
1073{
1074 struct uart_port *port;
1075 int baud = 9600;
1076 int bits = 8;
1077 int parity = 'n';
1078 int flow = 'n';
1079
1080 /*
1081 * Check whether an invalid uart number has been specified, and
1082 * if so, search for the first available port that does have
1083 * console support.
1084 */
1085 if (co->index >= UART_NR)
1086 co->index = 0;
1087 port = &m32r_sio_ports[co->index].port;
1088
1089 /*
1090 * Temporary fix.
1091 */
1092 spin_lock_init(&port->lock);
1093
1094 if (options)
1095 uart_parse_options(options, &baud, &parity, &bits, &flow);
1096
1097 return uart_set_options(port, co, baud, parity, bits, flow);
1098}
1099
1100static struct uart_driver m32r_sio_reg;
1101static struct console m32r_sio_console = {
1102 .name = "ttyS",
1103 .write = m32r_sio_console_write,
1104 .device = uart_console_device,
1105 .setup = m32r_sio_console_setup,
1106 .flags = CON_PRINTBUFFER,
1107 .index = -1,
1108 .data = &m32r_sio_reg,
1109};
1110
1111static int __init m32r_sio_console_init(void)
1112{
1113 sio_reset();
1114 sio_init();
1115 m32r_sio_init_ports();
1116 register_console(&m32r_sio_console);
1117 return 0;
1118}
1119console_initcall(m32r_sio_console_init);
1120
1121#define M32R_SIO_CONSOLE &m32r_sio_console
1122#else
1123#define M32R_SIO_CONSOLE NULL
1124#endif
1125
1126static struct uart_driver m32r_sio_reg = {
1127 .owner = THIS_MODULE,
1128 .driver_name = "sio",
1129 .dev_name = "ttyS",
1130 .major = TTY_MAJOR,
1131 .minor = 64,
1132 .nr = UART_NR,
1133 .cons = M32R_SIO_CONSOLE,
1134};
1135
1136/**
1137 * m32r_sio_suspend_port - suspend one serial port
1138 * @line: serial line number
1139 *
1140 * Suspend one serial port.
1141 */
1142void m32r_sio_suspend_port(int line)
1143{
1144 uart_suspend_port(&m32r_sio_reg, &m32r_sio_ports[line].port);
1145}
1146
1147/**
1148 * m32r_sio_resume_port - resume one serial port
1149 * @line: serial line number
1150 *
1151 * Resume one serial port.
1152 */
1153void m32r_sio_resume_port(int line)
1154{
1155 uart_resume_port(&m32r_sio_reg, &m32r_sio_ports[line].port);
1156}
1157
1158static int __init m32r_sio_init(void)
1159{
1160 int ret, i;
1161
1162 printk(KERN_INFO "Serial: M32R SIO driver\n");
1163
1164 for (i = 0; i < nr_irqs; i++)
1165 spin_lock_init(&irq_lists[i].lock);
1166
1167 ret = uart_register_driver(&m32r_sio_reg);
1168 if (ret >= 0)
1169 m32r_sio_register_ports(&m32r_sio_reg);
1170
1171 return ret;
1172}
1173
1174static void __exit m32r_sio_exit(void)
1175{
1176 int i;
1177
1178 for (i = 0; i < UART_NR; i++)
1179 uart_remove_one_port(&m32r_sio_reg, &m32r_sio_ports[i].port);
1180
1181 uart_unregister_driver(&m32r_sio_reg);
1182}
1183
1184module_init(m32r_sio_init);
1185module_exit(m32r_sio_exit);
1186
1187EXPORT_SYMBOL(m32r_sio_suspend_port);
1188EXPORT_SYMBOL(m32r_sio_resume_port);
1189
1190MODULE_LICENSE("GPL");
1191MODULE_DESCRIPTION("Generic M32R SIO serial driver");
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-31 05:19:01 -0400