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-rw-r--r--drivers/tty/serial/8250.c3377
1 files changed, 3377 insertions, 0 deletions
diff --git a/drivers/tty/serial/8250.c b/drivers/tty/serial/8250.c
new file mode 100644
index 000000000000..b25e6e490530
--- /dev/null
+++ b/drivers/tty/serial/8250.c
@@ -0,0 +1,3377 @@
1/*
2 * linux/drivers/char/8250.c
3 *
4 * Driver for 8250/16550-type serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * A note about mapbase / membase
16 *
17 * mapbase is the physical address of the IO port.
18 * membase is an 'ioremapped' cookie.
19 */
20
21#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
22#define SUPPORT_SYSRQ
23#endif
24
25#include <linux/module.h>
26#include <linux/moduleparam.h>
27#include <linux/ioport.h>
28#include <linux/init.h>
29#include <linux/console.h>
30#include <linux/sysrq.h>
31#include <linux/delay.h>
32#include <linux/platform_device.h>
33#include <linux/tty.h>
34#include <linux/ratelimit.h>
35#include <linux/tty_flip.h>
36#include <linux/serial_reg.h>
37#include <linux/serial_core.h>
38#include <linux/serial.h>
39#include <linux/serial_8250.h>
40#include <linux/nmi.h>
41#include <linux/mutex.h>
42#include <linux/slab.h>
43
44#include <asm/io.h>
45#include <asm/irq.h>
46
47#include "8250.h"
48
49#ifdef CONFIG_SPARC
50#include "suncore.h"
51#endif
52
53/*
54 * Configuration:
55 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
56 * is unsafe when used on edge-triggered interrupts.
57 */
58static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
59
60static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
61
62static struct uart_driver serial8250_reg;
63
64static int serial_index(struct uart_port *port)
65{
66 return (serial8250_reg.minor - 64) + port->line;
67}
68
69static unsigned int skip_txen_test; /* force skip of txen test at init time */
70
71/*
72 * Debugging.
73 */
74#if 0
75#define DEBUG_AUTOCONF(fmt...) printk(fmt)
76#else
77#define DEBUG_AUTOCONF(fmt...) do { } while (0)
78#endif
79
80#if 0
81#define DEBUG_INTR(fmt...) printk(fmt)
82#else
83#define DEBUG_INTR(fmt...) do { } while (0)
84#endif
85
86#define PASS_LIMIT 256
87
88#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
89
90
91/*
92 * We default to IRQ0 for the "no irq" hack. Some
93 * machine types want others as well - they're free
94 * to redefine this in their header file.
95 */
96#define is_real_interrupt(irq) ((irq) != 0)
97
98#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
99#define CONFIG_SERIAL_DETECT_IRQ 1
100#endif
101#ifdef CONFIG_SERIAL_8250_MANY_PORTS
102#define CONFIG_SERIAL_MANY_PORTS 1
103#endif
104
105/*
106 * HUB6 is always on. This will be removed once the header
107 * files have been cleaned.
108 */
109#define CONFIG_HUB6 1
110
111#include <asm/serial.h>
112/*
113 * SERIAL_PORT_DFNS tells us about built-in ports that have no
114 * standard enumeration mechanism. Platforms that can find all
115 * serial ports via mechanisms like ACPI or PCI need not supply it.
116 */
117#ifndef SERIAL_PORT_DFNS
118#define SERIAL_PORT_DFNS
119#endif
120
121static const struct old_serial_port old_serial_port[] = {
122 SERIAL_PORT_DFNS /* defined in asm/serial.h */
123};
124
125#define UART_NR CONFIG_SERIAL_8250_NR_UARTS
126
127#ifdef CONFIG_SERIAL_8250_RSA
128
129#define PORT_RSA_MAX 4
130static unsigned long probe_rsa[PORT_RSA_MAX];
131static unsigned int probe_rsa_count;
132#endif /* CONFIG_SERIAL_8250_RSA */
133
134struct uart_8250_port {
135 struct uart_port port;
136 struct timer_list timer; /* "no irq" timer */
137 struct list_head list; /* ports on this IRQ */
138 unsigned short capabilities; /* port capabilities */
139 unsigned short bugs; /* port bugs */
140 unsigned int tx_loadsz; /* transmit fifo load size */
141 unsigned char acr;
142 unsigned char ier;
143 unsigned char lcr;
144 unsigned char mcr;
145 unsigned char mcr_mask; /* mask of user bits */
146 unsigned char mcr_force; /* mask of forced bits */
147 unsigned char cur_iotype; /* Running I/O type */
148
149 /*
150 * Some bits in registers are cleared on a read, so they must
151 * be saved whenever the register is read but the bits will not
152 * be immediately processed.
153 */
154#define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS
155 unsigned char lsr_saved_flags;
156#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
157 unsigned char msr_saved_flags;
158};
159
160struct irq_info {
161 struct hlist_node node;
162 int irq;
163 spinlock_t lock; /* Protects list not the hash */
164 struct list_head *head;
165};
166
167#define NR_IRQ_HASH 32 /* Can be adjusted later */
168static struct hlist_head irq_lists[NR_IRQ_HASH];
169static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
170
171/*
172 * Here we define the default xmit fifo size used for each type of UART.
173 */
174static const struct serial8250_config uart_config[] = {
175 [PORT_UNKNOWN] = {
176 .name = "unknown",
177 .fifo_size = 1,
178 .tx_loadsz = 1,
179 },
180 [PORT_8250] = {
181 .name = "8250",
182 .fifo_size = 1,
183 .tx_loadsz = 1,
184 },
185 [PORT_16450] = {
186 .name = "16450",
187 .fifo_size = 1,
188 .tx_loadsz = 1,
189 },
190 [PORT_16550] = {
191 .name = "16550",
192 .fifo_size = 1,
193 .tx_loadsz = 1,
194 },
195 [PORT_16550A] = {
196 .name = "16550A",
197 .fifo_size = 16,
198 .tx_loadsz = 16,
199 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
200 .flags = UART_CAP_FIFO,
201 },
202 [PORT_CIRRUS] = {
203 .name = "Cirrus",
204 .fifo_size = 1,
205 .tx_loadsz = 1,
206 },
207 [PORT_16650] = {
208 .name = "ST16650",
209 .fifo_size = 1,
210 .tx_loadsz = 1,
211 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
212 },
213 [PORT_16650V2] = {
214 .name = "ST16650V2",
215 .fifo_size = 32,
216 .tx_loadsz = 16,
217 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
218 UART_FCR_T_TRIG_00,
219 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
220 },
221 [PORT_16750] = {
222 .name = "TI16750",
223 .fifo_size = 64,
224 .tx_loadsz = 64,
225 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
226 UART_FCR7_64BYTE,
227 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
228 },
229 [PORT_STARTECH] = {
230 .name = "Startech",
231 .fifo_size = 1,
232 .tx_loadsz = 1,
233 },
234 [PORT_16C950] = {
235 .name = "16C950/954",
236 .fifo_size = 128,
237 .tx_loadsz = 128,
238 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
239 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
240 },
241 [PORT_16654] = {
242 .name = "ST16654",
243 .fifo_size = 64,
244 .tx_loadsz = 32,
245 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
246 UART_FCR_T_TRIG_10,
247 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
248 },
249 [PORT_16850] = {
250 .name = "XR16850",
251 .fifo_size = 128,
252 .tx_loadsz = 128,
253 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
254 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
255 },
256 [PORT_RSA] = {
257 .name = "RSA",
258 .fifo_size = 2048,
259 .tx_loadsz = 2048,
260 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
261 .flags = UART_CAP_FIFO,
262 },
263 [PORT_NS16550A] = {
264 .name = "NS16550A",
265 .fifo_size = 16,
266 .tx_loadsz = 16,
267 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
268 .flags = UART_CAP_FIFO | UART_NATSEMI,
269 },
270 [PORT_XSCALE] = {
271 .name = "XScale",
272 .fifo_size = 32,
273 .tx_loadsz = 32,
274 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
275 .flags = UART_CAP_FIFO | UART_CAP_UUE,
276 },
277 [PORT_RM9000] = {
278 .name = "RM9000",
279 .fifo_size = 16,
280 .tx_loadsz = 16,
281 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
282 .flags = UART_CAP_FIFO,
283 },
284 [PORT_OCTEON] = {
285 .name = "OCTEON",
286 .fifo_size = 64,
287 .tx_loadsz = 64,
288 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
289 .flags = UART_CAP_FIFO,
290 },
291 [PORT_AR7] = {
292 .name = "AR7",
293 .fifo_size = 16,
294 .tx_loadsz = 16,
295 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
296 .flags = UART_CAP_FIFO | UART_CAP_AFE,
297 },
298 [PORT_U6_16550A] = {
299 .name = "U6_16550A",
300 .fifo_size = 64,
301 .tx_loadsz = 64,
302 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
303 .flags = UART_CAP_FIFO | UART_CAP_AFE,
304 },
305};
306
307#if defined(CONFIG_MIPS_ALCHEMY)
308
309/* Au1x00 UART hardware has a weird register layout */
310static const u8 au_io_in_map[] = {
311 [UART_RX] = 0,
312 [UART_IER] = 2,
313 [UART_IIR] = 3,
314 [UART_LCR] = 5,
315 [UART_MCR] = 6,
316 [UART_LSR] = 7,
317 [UART_MSR] = 8,
318};
319
320static const u8 au_io_out_map[] = {
321 [UART_TX] = 1,
322 [UART_IER] = 2,
323 [UART_FCR] = 4,
324 [UART_LCR] = 5,
325 [UART_MCR] = 6,
326};
327
328/* sane hardware needs no mapping */
329static inline int map_8250_in_reg(struct uart_port *p, int offset)
330{
331 if (p->iotype != UPIO_AU)
332 return offset;
333 return au_io_in_map[offset];
334}
335
336static inline int map_8250_out_reg(struct uart_port *p, int offset)
337{
338 if (p->iotype != UPIO_AU)
339 return offset;
340 return au_io_out_map[offset];
341}
342
343#elif defined(CONFIG_SERIAL_8250_RM9K)
344
345static const u8
346 regmap_in[8] = {
347 [UART_RX] = 0x00,
348 [UART_IER] = 0x0c,
349 [UART_IIR] = 0x14,
350 [UART_LCR] = 0x1c,
351 [UART_MCR] = 0x20,
352 [UART_LSR] = 0x24,
353 [UART_MSR] = 0x28,
354 [UART_SCR] = 0x2c
355 },
356 regmap_out[8] = {
357 [UART_TX] = 0x04,
358 [UART_IER] = 0x0c,
359 [UART_FCR] = 0x18,
360 [UART_LCR] = 0x1c,
361 [UART_MCR] = 0x20,
362 [UART_LSR] = 0x24,
363 [UART_MSR] = 0x28,
364 [UART_SCR] = 0x2c
365 };
366
367static inline int map_8250_in_reg(struct uart_port *p, int offset)
368{
369 if (p->iotype != UPIO_RM9000)
370 return offset;
371 return regmap_in[offset];
372}
373
374static inline int map_8250_out_reg(struct uart_port *p, int offset)
375{
376 if (p->iotype != UPIO_RM9000)
377 return offset;
378 return regmap_out[offset];
379}
380
381#else
382
383/* sane hardware needs no mapping */
384#define map_8250_in_reg(up, offset) (offset)
385#define map_8250_out_reg(up, offset) (offset)
386
387#endif
388
389static unsigned int hub6_serial_in(struct uart_port *p, int offset)
390{
391 offset = map_8250_in_reg(p, offset) << p->regshift;
392 outb(p->hub6 - 1 + offset, p->iobase);
393 return inb(p->iobase + 1);
394}
395
396static void hub6_serial_out(struct uart_port *p, int offset, int value)
397{
398 offset = map_8250_out_reg(p, offset) << p->regshift;
399 outb(p->hub6 - 1 + offset, p->iobase);
400 outb(value, p->iobase + 1);
401}
402
403static unsigned int mem_serial_in(struct uart_port *p, int offset)
404{
405 offset = map_8250_in_reg(p, offset) << p->regshift;
406 return readb(p->membase + offset);
407}
408
409static void mem_serial_out(struct uart_port *p, int offset, int value)
410{
411 offset = map_8250_out_reg(p, offset) << p->regshift;
412 writeb(value, p->membase + offset);
413}
414
415static void mem32_serial_out(struct uart_port *p, int offset, int value)
416{
417 offset = map_8250_out_reg(p, offset) << p->regshift;
418 writel(value, p->membase + offset);
419}
420
421static unsigned int mem32_serial_in(struct uart_port *p, int offset)
422{
423 offset = map_8250_in_reg(p, offset) << p->regshift;
424 return readl(p->membase + offset);
425}
426
427static unsigned int au_serial_in(struct uart_port *p, int offset)
428{
429 offset = map_8250_in_reg(p, offset) << p->regshift;
430 return __raw_readl(p->membase + offset);
431}
432
433static void au_serial_out(struct uart_port *p, int offset, int value)
434{
435 offset = map_8250_out_reg(p, offset) << p->regshift;
436 __raw_writel(value, p->membase + offset);
437}
438
439static unsigned int tsi_serial_in(struct uart_port *p, int offset)
440{
441 unsigned int tmp;
442 offset = map_8250_in_reg(p, offset) << p->regshift;
443 if (offset == UART_IIR) {
444 tmp = readl(p->membase + (UART_IIR & ~3));
445 return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */
446 } else
447 return readb(p->membase + offset);
448}
449
450static void tsi_serial_out(struct uart_port *p, int offset, int value)
451{
452 offset = map_8250_out_reg(p, offset) << p->regshift;
453 if (!((offset == UART_IER) && (value & UART_IER_UUE)))
454 writeb(value, p->membase + offset);
455}
456
457/* Save the LCR value so it can be re-written when a Busy Detect IRQ occurs. */
458static inline void dwapb_save_out_value(struct uart_port *p, int offset,
459 int value)
460{
461 struct uart_8250_port *up =
462 container_of(p, struct uart_8250_port, port);
463
464 if (offset == UART_LCR)
465 up->lcr = value;
466}
467
468/* Read the IER to ensure any interrupt is cleared before returning from ISR. */
469static inline void dwapb_check_clear_ier(struct uart_port *p, int offset)
470{
471 if (offset == UART_TX || offset == UART_IER)
472 p->serial_in(p, UART_IER);
473}
474
475static void dwapb_serial_out(struct uart_port *p, int offset, int value)
476{
477 int save_offset = offset;
478 offset = map_8250_out_reg(p, offset) << p->regshift;
479 dwapb_save_out_value(p, save_offset, value);
480 writeb(value, p->membase + offset);
481 dwapb_check_clear_ier(p, save_offset);
482}
483
484static void dwapb32_serial_out(struct uart_port *p, int offset, int value)
485{
486 int save_offset = offset;
487 offset = map_8250_out_reg(p, offset) << p->regshift;
488 dwapb_save_out_value(p, save_offset, value);
489 writel(value, p->membase + offset);
490 dwapb_check_clear_ier(p, save_offset);
491}
492
493static unsigned int io_serial_in(struct uart_port *p, int offset)
494{
495 offset = map_8250_in_reg(p, offset) << p->regshift;
496 return inb(p->iobase + offset);
497}
498
499static void io_serial_out(struct uart_port *p, int offset, int value)
500{
501 offset = map_8250_out_reg(p, offset) << p->regshift;
502 outb(value, p->iobase + offset);
503}
504
505static void set_io_from_upio(struct uart_port *p)
506{
507 struct uart_8250_port *up =
508 container_of(p, struct uart_8250_port, port);
509 switch (p->iotype) {
510 case UPIO_HUB6:
511 p->serial_in = hub6_serial_in;
512 p->serial_out = hub6_serial_out;
513 break;
514
515 case UPIO_MEM:
516 p->serial_in = mem_serial_in;
517 p->serial_out = mem_serial_out;
518 break;
519
520 case UPIO_RM9000:
521 case UPIO_MEM32:
522 p->serial_in = mem32_serial_in;
523 p->serial_out = mem32_serial_out;
524 break;
525
526 case UPIO_AU:
527 p->serial_in = au_serial_in;
528 p->serial_out = au_serial_out;
529 break;
530
531 case UPIO_TSI:
532 p->serial_in = tsi_serial_in;
533 p->serial_out = tsi_serial_out;
534 break;
535
536 case UPIO_DWAPB:
537 p->serial_in = mem_serial_in;
538 p->serial_out = dwapb_serial_out;
539 break;
540
541 case UPIO_DWAPB32:
542 p->serial_in = mem32_serial_in;
543 p->serial_out = dwapb32_serial_out;
544 break;
545
546 default:
547 p->serial_in = io_serial_in;
548 p->serial_out = io_serial_out;
549 break;
550 }
551 /* Remember loaded iotype */
552 up->cur_iotype = p->iotype;
553}
554
555static void
556serial_out_sync(struct uart_8250_port *up, int offset, int value)
557{
558 struct uart_port *p = &up->port;
559 switch (p->iotype) {
560 case UPIO_MEM:
561 case UPIO_MEM32:
562 case UPIO_AU:
563 case UPIO_DWAPB:
564 case UPIO_DWAPB32:
565 p->serial_out(p, offset, value);
566 p->serial_in(p, UART_LCR); /* safe, no side-effects */
567 break;
568 default:
569 p->serial_out(p, offset, value);
570 }
571}
572
573#define serial_in(up, offset) \
574 (up->port.serial_in(&(up)->port, (offset)))
575#define serial_out(up, offset, value) \
576 (up->port.serial_out(&(up)->port, (offset), (value)))
577/*
578 * We used to support using pause I/O for certain machines. We
579 * haven't supported this for a while, but just in case it's badly
580 * needed for certain old 386 machines, I've left these #define's
581 * in....
582 */
583#define serial_inp(up, offset) serial_in(up, offset)
584#define serial_outp(up, offset, value) serial_out(up, offset, value)
585
586/* Uart divisor latch read */
587static inline int _serial_dl_read(struct uart_8250_port *up)
588{
589 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
590}
591
592/* Uart divisor latch write */
593static inline void _serial_dl_write(struct uart_8250_port *up, int value)
594{
595 serial_outp(up, UART_DLL, value & 0xff);
596 serial_outp(up, UART_DLM, value >> 8 & 0xff);
597}
598
599#if defined(CONFIG_MIPS_ALCHEMY)
600/* Au1x00 haven't got a standard divisor latch */
601static int serial_dl_read(struct uart_8250_port *up)
602{
603 if (up->port.iotype == UPIO_AU)
604 return __raw_readl(up->port.membase + 0x28);
605 else
606 return _serial_dl_read(up);
607}
608
609static void serial_dl_write(struct uart_8250_port *up, int value)
610{
611 if (up->port.iotype == UPIO_AU)
612 __raw_writel(value, up->port.membase + 0x28);
613 else
614 _serial_dl_write(up, value);
615}
616#elif defined(CONFIG_SERIAL_8250_RM9K)
617static int serial_dl_read(struct uart_8250_port *up)
618{
619 return (up->port.iotype == UPIO_RM9000) ?
620 (((__raw_readl(up->port.membase + 0x10) << 8) |
621 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
622 _serial_dl_read(up);
623}
624
625static void serial_dl_write(struct uart_8250_port *up, int value)
626{
627 if (up->port.iotype == UPIO_RM9000) {
628 __raw_writel(value, up->port.membase + 0x08);
629 __raw_writel(value >> 8, up->port.membase + 0x10);
630 } else {
631 _serial_dl_write(up, value);
632 }
633}
634#else
635#define serial_dl_read(up) _serial_dl_read(up)
636#define serial_dl_write(up, value) _serial_dl_write(up, value)
637#endif
638
639/*
640 * For the 16C950
641 */
642static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
643{
644 serial_out(up, UART_SCR, offset);
645 serial_out(up, UART_ICR, value);
646}
647
648static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
649{
650 unsigned int value;
651
652 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
653 serial_out(up, UART_SCR, offset);
654 value = serial_in(up, UART_ICR);
655 serial_icr_write(up, UART_ACR, up->acr);
656
657 return value;
658}
659
660/*
661 * FIFO support.
662 */
663static void serial8250_clear_fifos(struct uart_8250_port *p)
664{
665 if (p->capabilities & UART_CAP_FIFO) {
666 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
667 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
668 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
669 serial_outp(p, UART_FCR, 0);
670 }
671}
672
673/*
674 * IER sleep support. UARTs which have EFRs need the "extended
675 * capability" bit enabled. Note that on XR16C850s, we need to
676 * reset LCR to write to IER.
677 */
678static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
679{
680 if (p->capabilities & UART_CAP_SLEEP) {
681 if (p->capabilities & UART_CAP_EFR) {
682 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
683 serial_outp(p, UART_EFR, UART_EFR_ECB);
684 serial_outp(p, UART_LCR, 0);
685 }
686 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
687 if (p->capabilities & UART_CAP_EFR) {
688 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
689 serial_outp(p, UART_EFR, 0);
690 serial_outp(p, UART_LCR, 0);
691 }
692 }
693}
694
695#ifdef CONFIG_SERIAL_8250_RSA
696/*
697 * Attempts to turn on the RSA FIFO. Returns zero on failure.
698 * We set the port uart clock rate if we succeed.
699 */
700static int __enable_rsa(struct uart_8250_port *up)
701{
702 unsigned char mode;
703 int result;
704
705 mode = serial_inp(up, UART_RSA_MSR);
706 result = mode & UART_RSA_MSR_FIFO;
707
708 if (!result) {
709 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
710 mode = serial_inp(up, UART_RSA_MSR);
711 result = mode & UART_RSA_MSR_FIFO;
712 }
713
714 if (result)
715 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
716
717 return result;
718}
719
720static void enable_rsa(struct uart_8250_port *up)
721{
722 if (up->port.type == PORT_RSA) {
723 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
724 spin_lock_irq(&up->port.lock);
725 __enable_rsa(up);
726 spin_unlock_irq(&up->port.lock);
727 }
728 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
729 serial_outp(up, UART_RSA_FRR, 0);
730 }
731}
732
733/*
734 * Attempts to turn off the RSA FIFO. Returns zero on failure.
735 * It is unknown why interrupts were disabled in here. However,
736 * the caller is expected to preserve this behaviour by grabbing
737 * the spinlock before calling this function.
738 */
739static void disable_rsa(struct uart_8250_port *up)
740{
741 unsigned char mode;
742 int result;
743
744 if (up->port.type == PORT_RSA &&
745 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
746 spin_lock_irq(&up->port.lock);
747
748 mode = serial_inp(up, UART_RSA_MSR);
749 result = !(mode & UART_RSA_MSR_FIFO);
750
751 if (!result) {
752 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
753 mode = serial_inp(up, UART_RSA_MSR);
754 result = !(mode & UART_RSA_MSR_FIFO);
755 }
756
757 if (result)
758 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
759 spin_unlock_irq(&up->port.lock);
760 }
761}
762#endif /* CONFIG_SERIAL_8250_RSA */
763
764/*
765 * This is a quickie test to see how big the FIFO is.
766 * It doesn't work at all the time, more's the pity.
767 */
768static int size_fifo(struct uart_8250_port *up)
769{
770 unsigned char old_fcr, old_mcr, old_lcr;
771 unsigned short old_dl;
772 int count;
773
774 old_lcr = serial_inp(up, UART_LCR);
775 serial_outp(up, UART_LCR, 0);
776 old_fcr = serial_inp(up, UART_FCR);
777 old_mcr = serial_inp(up, UART_MCR);
778 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
779 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
780 serial_outp(up, UART_MCR, UART_MCR_LOOP);
781 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
782 old_dl = serial_dl_read(up);
783 serial_dl_write(up, 0x0001);
784 serial_outp(up, UART_LCR, 0x03);
785 for (count = 0; count < 256; count++)
786 serial_outp(up, UART_TX, count);
787 mdelay(20);/* FIXME - schedule_timeout */
788 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
789 (count < 256); count++)
790 serial_inp(up, UART_RX);
791 serial_outp(up, UART_FCR, old_fcr);
792 serial_outp(up, UART_MCR, old_mcr);
793 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
794 serial_dl_write(up, old_dl);
795 serial_outp(up, UART_LCR, old_lcr);
796
797 return count;
798}
799
800/*
801 * Read UART ID using the divisor method - set DLL and DLM to zero
802 * and the revision will be in DLL and device type in DLM. We
803 * preserve the device state across this.
804 */
805static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
806{
807 unsigned char old_dll, old_dlm, old_lcr;
808 unsigned int id;
809
810 old_lcr = serial_inp(p, UART_LCR);
811 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_A);
812
813 old_dll = serial_inp(p, UART_DLL);
814 old_dlm = serial_inp(p, UART_DLM);
815
816 serial_outp(p, UART_DLL, 0);
817 serial_outp(p, UART_DLM, 0);
818
819 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
820
821 serial_outp(p, UART_DLL, old_dll);
822 serial_outp(p, UART_DLM, old_dlm);
823 serial_outp(p, UART_LCR, old_lcr);
824
825 return id;
826}
827
828/*
829 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
830 * When this function is called we know it is at least a StarTech
831 * 16650 V2, but it might be one of several StarTech UARTs, or one of
832 * its clones. (We treat the broken original StarTech 16650 V1 as a
833 * 16550, and why not? Startech doesn't seem to even acknowledge its
834 * existence.)
835 *
836 * What evil have men's minds wrought...
837 */
838static void autoconfig_has_efr(struct uart_8250_port *up)
839{
840 unsigned int id1, id2, id3, rev;
841
842 /*
843 * Everything with an EFR has SLEEP
844 */
845 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
846
847 /*
848 * First we check to see if it's an Oxford Semiconductor UART.
849 *
850 * If we have to do this here because some non-National
851 * Semiconductor clone chips lock up if you try writing to the
852 * LSR register (which serial_icr_read does)
853 */
854
855 /*
856 * Check for Oxford Semiconductor 16C950.
857 *
858 * EFR [4] must be set else this test fails.
859 *
860 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
861 * claims that it's needed for 952 dual UART's (which are not
862 * recommended for new designs).
863 */
864 up->acr = 0;
865 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
866 serial_out(up, UART_EFR, UART_EFR_ECB);
867 serial_out(up, UART_LCR, 0x00);
868 id1 = serial_icr_read(up, UART_ID1);
869 id2 = serial_icr_read(up, UART_ID2);
870 id3 = serial_icr_read(up, UART_ID3);
871 rev = serial_icr_read(up, UART_REV);
872
873 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
874
875 if (id1 == 0x16 && id2 == 0xC9 &&
876 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
877 up->port.type = PORT_16C950;
878
879 /*
880 * Enable work around for the Oxford Semiconductor 952 rev B
881 * chip which causes it to seriously miscalculate baud rates
882 * when DLL is 0.
883 */
884 if (id3 == 0x52 && rev == 0x01)
885 up->bugs |= UART_BUG_QUOT;
886 return;
887 }
888
889 /*
890 * We check for a XR16C850 by setting DLL and DLM to 0, and then
891 * reading back DLL and DLM. The chip type depends on the DLM
892 * value read back:
893 * 0x10 - XR16C850 and the DLL contains the chip revision.
894 * 0x12 - XR16C2850.
895 * 0x14 - XR16C854.
896 */
897 id1 = autoconfig_read_divisor_id(up);
898 DEBUG_AUTOCONF("850id=%04x ", id1);
899
900 id2 = id1 >> 8;
901 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
902 up->port.type = PORT_16850;
903 return;
904 }
905
906 /*
907 * It wasn't an XR16C850.
908 *
909 * We distinguish between the '654 and the '650 by counting
910 * how many bytes are in the FIFO. I'm using this for now,
911 * since that's the technique that was sent to me in the
912 * serial driver update, but I'm not convinced this works.
913 * I've had problems doing this in the past. -TYT
914 */
915 if (size_fifo(up) == 64)
916 up->port.type = PORT_16654;
917 else
918 up->port.type = PORT_16650V2;
919}
920
921/*
922 * We detected a chip without a FIFO. Only two fall into
923 * this category - the original 8250 and the 16450. The
924 * 16450 has a scratch register (accessible with LCR=0)
925 */
926static void autoconfig_8250(struct uart_8250_port *up)
927{
928 unsigned char scratch, status1, status2;
929
930 up->port.type = PORT_8250;
931
932 scratch = serial_in(up, UART_SCR);
933 serial_outp(up, UART_SCR, 0xa5);
934 status1 = serial_in(up, UART_SCR);
935 serial_outp(up, UART_SCR, 0x5a);
936 status2 = serial_in(up, UART_SCR);
937 serial_outp(up, UART_SCR, scratch);
938
939 if (status1 == 0xa5 && status2 == 0x5a)
940 up->port.type = PORT_16450;
941}
942
943static int broken_efr(struct uart_8250_port *up)
944{
945 /*
946 * Exar ST16C2550 "A2" devices incorrectly detect as
947 * having an EFR, and report an ID of 0x0201. See
948 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
949 */
950 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
951 return 1;
952
953 return 0;
954}
955
956/*
957 * We know that the chip has FIFOs. Does it have an EFR? The
958 * EFR is located in the same register position as the IIR and
959 * we know the top two bits of the IIR are currently set. The
960 * EFR should contain zero. Try to read the EFR.
961 */
962static void autoconfig_16550a(struct uart_8250_port *up)
963{
964 unsigned char status1, status2;
965 unsigned int iersave;
966
967 up->port.type = PORT_16550A;
968 up->capabilities |= UART_CAP_FIFO;
969
970 /*
971 * Check for presence of the EFR when DLAB is set.
972 * Only ST16C650V1 UARTs pass this test.
973 */
974 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
975 if (serial_in(up, UART_EFR) == 0) {
976 serial_outp(up, UART_EFR, 0xA8);
977 if (serial_in(up, UART_EFR) != 0) {
978 DEBUG_AUTOCONF("EFRv1 ");
979 up->port.type = PORT_16650;
980 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
981 } else {
982 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
983 }
984 serial_outp(up, UART_EFR, 0);
985 return;
986 }
987
988 /*
989 * Maybe it requires 0xbf to be written to the LCR.
990 * (other ST16C650V2 UARTs, TI16C752A, etc)
991 */
992 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
993 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
994 DEBUG_AUTOCONF("EFRv2 ");
995 autoconfig_has_efr(up);
996 return;
997 }
998
999 /*
1000 * Check for a National Semiconductor SuperIO chip.
1001 * Attempt to switch to bank 2, read the value of the LOOP bit
1002 * from EXCR1. Switch back to bank 0, change it in MCR. Then
1003 * switch back to bank 2, read it from EXCR1 again and check
1004 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1005 */
1006 serial_outp(up, UART_LCR, 0);
1007 status1 = serial_in(up, UART_MCR);
1008 serial_outp(up, UART_LCR, 0xE0);
1009 status2 = serial_in(up, 0x02); /* EXCR1 */
1010
1011 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
1012 serial_outp(up, UART_LCR, 0);
1013 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
1014 serial_outp(up, UART_LCR, 0xE0);
1015 status2 = serial_in(up, 0x02); /* EXCR1 */
1016 serial_outp(up, UART_LCR, 0);
1017 serial_outp(up, UART_MCR, status1);
1018
1019 if ((status2 ^ status1) & UART_MCR_LOOP) {
1020 unsigned short quot;
1021
1022 serial_outp(up, UART_LCR, 0xE0);
1023
1024 quot = serial_dl_read(up);
1025 quot <<= 3;
1026
1027 status1 = serial_in(up, 0x04); /* EXCR2 */
1028 status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
1029 status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
1030 serial_outp(up, 0x04, status1);
1031
1032 serial_dl_write(up, quot);
1033
1034 serial_outp(up, UART_LCR, 0);
1035
1036 up->port.uartclk = 921600*16;
1037 up->port.type = PORT_NS16550A;
1038 up->capabilities |= UART_NATSEMI;
1039 return;
1040 }
1041 }
1042
1043 /*
1044 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1045 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1046 * Try setting it with and without DLAB set. Cheap clones
1047 * set bit 5 without DLAB set.
1048 */
1049 serial_outp(up, UART_LCR, 0);
1050 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1051 status1 = serial_in(up, UART_IIR) >> 5;
1052 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1053 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
1054 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1055 status2 = serial_in(up, UART_IIR) >> 5;
1056 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1057 serial_outp(up, UART_LCR, 0);
1058
1059 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1060
1061 if (status1 == 6 && status2 == 7) {
1062 up->port.type = PORT_16750;
1063 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1064 return;
1065 }
1066
1067 /*
1068 * Try writing and reading the UART_IER_UUE bit (b6).
1069 * If it works, this is probably one of the Xscale platform's
1070 * internal UARTs.
1071 * We're going to explicitly set the UUE bit to 0 before
1072 * trying to write and read a 1 just to make sure it's not
1073 * already a 1 and maybe locked there before we even start start.
1074 */
1075 iersave = serial_in(up, UART_IER);
1076 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
1077 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1078 /*
1079 * OK it's in a known zero state, try writing and reading
1080 * without disturbing the current state of the other bits.
1081 */
1082 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
1083 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1084 /*
1085 * It's an Xscale.
1086 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1087 */
1088 DEBUG_AUTOCONF("Xscale ");
1089 up->port.type = PORT_XSCALE;
1090 up->capabilities |= UART_CAP_UUE;
1091 return;
1092 }
1093 } else {
1094 /*
1095 * If we got here we couldn't force the IER_UUE bit to 0.
1096 * Log it and continue.
1097 */
1098 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1099 }
1100 serial_outp(up, UART_IER, iersave);
1101
1102 /*
1103 * We distinguish between 16550A and U6 16550A by counting
1104 * how many bytes are in the FIFO.
1105 */
1106 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1107 up->port.type = PORT_U6_16550A;
1108 up->capabilities |= UART_CAP_AFE;
1109 }
1110}
1111
1112/*
1113 * This routine is called by rs_init() to initialize a specific serial
1114 * port. It determines what type of UART chip this serial port is
1115 * using: 8250, 16450, 16550, 16550A. The important question is
1116 * whether or not this UART is a 16550A or not, since this will
1117 * determine whether or not we can use its FIFO features or not.
1118 */
1119static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1120{
1121 unsigned char status1, scratch, scratch2, scratch3;
1122 unsigned char save_lcr, save_mcr;
1123 unsigned long flags;
1124
1125 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
1126 return;
1127
1128 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1129 serial_index(&up->port), up->port.iobase, up->port.membase);
1130
1131 /*
1132 * We really do need global IRQs disabled here - we're going to
1133 * be frobbing the chips IRQ enable register to see if it exists.
1134 */
1135 spin_lock_irqsave(&up->port.lock, flags);
1136
1137 up->capabilities = 0;
1138 up->bugs = 0;
1139
1140 if (!(up->port.flags & UPF_BUGGY_UART)) {
1141 /*
1142 * Do a simple existence test first; if we fail this,
1143 * there's no point trying anything else.
1144 *
1145 * 0x80 is used as a nonsense port to prevent against
1146 * false positives due to ISA bus float. The
1147 * assumption is that 0x80 is a non-existent port;
1148 * which should be safe since include/asm/io.h also
1149 * makes this assumption.
1150 *
1151 * Note: this is safe as long as MCR bit 4 is clear
1152 * and the device is in "PC" mode.
1153 */
1154 scratch = serial_inp(up, UART_IER);
1155 serial_outp(up, UART_IER, 0);
1156#ifdef __i386__
1157 outb(0xff, 0x080);
1158#endif
1159 /*
1160 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1161 * 16C754B) allow only to modify them if an EFR bit is set.
1162 */
1163 scratch2 = serial_inp(up, UART_IER) & 0x0f;
1164 serial_outp(up, UART_IER, 0x0F);
1165#ifdef __i386__
1166 outb(0, 0x080);
1167#endif
1168 scratch3 = serial_inp(up, UART_IER) & 0x0f;
1169 serial_outp(up, UART_IER, scratch);
1170 if (scratch2 != 0 || scratch3 != 0x0F) {
1171 /*
1172 * We failed; there's nothing here
1173 */
1174 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1175 scratch2, scratch3);
1176 goto out;
1177 }
1178 }
1179
1180 save_mcr = serial_in(up, UART_MCR);
1181 save_lcr = serial_in(up, UART_LCR);
1182
1183 /*
1184 * Check to see if a UART is really there. Certain broken
1185 * internal modems based on the Rockwell chipset fail this
1186 * test, because they apparently don't implement the loopback
1187 * test mode. So this test is skipped on the COM 1 through
1188 * COM 4 ports. This *should* be safe, since no board
1189 * manufacturer would be stupid enough to design a board
1190 * that conflicts with COM 1-4 --- we hope!
1191 */
1192 if (!(up->port.flags & UPF_SKIP_TEST)) {
1193 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1194 status1 = serial_inp(up, UART_MSR) & 0xF0;
1195 serial_outp(up, UART_MCR, save_mcr);
1196 if (status1 != 0x90) {
1197 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1198 status1);
1199 goto out;
1200 }
1201 }
1202
1203 /*
1204 * We're pretty sure there's a port here. Lets find out what
1205 * type of port it is. The IIR top two bits allows us to find
1206 * out if it's 8250 or 16450, 16550, 16550A or later. This
1207 * determines what we test for next.
1208 *
1209 * We also initialise the EFR (if any) to zero for later. The
1210 * EFR occupies the same register location as the FCR and IIR.
1211 */
1212 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1213 serial_outp(up, UART_EFR, 0);
1214 serial_outp(up, UART_LCR, 0);
1215
1216 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1217 scratch = serial_in(up, UART_IIR) >> 6;
1218
1219 DEBUG_AUTOCONF("iir=%d ", scratch);
1220
1221 switch (scratch) {
1222 case 0:
1223 autoconfig_8250(up);
1224 break;
1225 case 1:
1226 up->port.type = PORT_UNKNOWN;
1227 break;
1228 case 2:
1229 up->port.type = PORT_16550;
1230 break;
1231 case 3:
1232 autoconfig_16550a(up);
1233 break;
1234 }
1235
1236#ifdef CONFIG_SERIAL_8250_RSA
1237 /*
1238 * Only probe for RSA ports if we got the region.
1239 */
1240 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1241 int i;
1242
1243 for (i = 0 ; i < probe_rsa_count; ++i) {
1244 if (probe_rsa[i] == up->port.iobase &&
1245 __enable_rsa(up)) {
1246 up->port.type = PORT_RSA;
1247 break;
1248 }
1249 }
1250 }
1251#endif
1252
1253 serial_outp(up, UART_LCR, save_lcr);
1254
1255 if (up->capabilities != uart_config[up->port.type].flags) {
1256 printk(KERN_WARNING
1257 "ttyS%d: detected caps %08x should be %08x\n",
1258 serial_index(&up->port), up->capabilities,
1259 uart_config[up->port.type].flags);
1260 }
1261
1262 up->port.fifosize = uart_config[up->port.type].fifo_size;
1263 up->capabilities = uart_config[up->port.type].flags;
1264 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1265
1266 if (up->port.type == PORT_UNKNOWN)
1267 goto out;
1268
1269 /*
1270 * Reset the UART.
1271 */
1272#ifdef CONFIG_SERIAL_8250_RSA
1273 if (up->port.type == PORT_RSA)
1274 serial_outp(up, UART_RSA_FRR, 0);
1275#endif
1276 serial_outp(up, UART_MCR, save_mcr);
1277 serial8250_clear_fifos(up);
1278 serial_in(up, UART_RX);
1279 if (up->capabilities & UART_CAP_UUE)
1280 serial_outp(up, UART_IER, UART_IER_UUE);
1281 else
1282 serial_outp(up, UART_IER, 0);
1283
1284 out:
1285 spin_unlock_irqrestore(&up->port.lock, flags);
1286 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1287}
1288
1289static void autoconfig_irq(struct uart_8250_port *up)
1290{
1291 unsigned char save_mcr, save_ier;
1292 unsigned char save_ICP = 0;
1293 unsigned int ICP = 0;
1294 unsigned long irqs;
1295 int irq;
1296
1297 if (up->port.flags & UPF_FOURPORT) {
1298 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1299 save_ICP = inb_p(ICP);
1300 outb_p(0x80, ICP);
1301 (void) inb_p(ICP);
1302 }
1303
1304 /* forget possible initially masked and pending IRQ */
1305 probe_irq_off(probe_irq_on());
1306 save_mcr = serial_inp(up, UART_MCR);
1307 save_ier = serial_inp(up, UART_IER);
1308 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1309
1310 irqs = probe_irq_on();
1311 serial_outp(up, UART_MCR, 0);
1312 udelay(10);
1313 if (up->port.flags & UPF_FOURPORT) {
1314 serial_outp(up, UART_MCR,
1315 UART_MCR_DTR | UART_MCR_RTS);
1316 } else {
1317 serial_outp(up, UART_MCR,
1318 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1319 }
1320 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1321 (void)serial_inp(up, UART_LSR);
1322 (void)serial_inp(up, UART_RX);
1323 (void)serial_inp(up, UART_IIR);
1324 (void)serial_inp(up, UART_MSR);
1325 serial_outp(up, UART_TX, 0xFF);
1326 udelay(20);
1327 irq = probe_irq_off(irqs);
1328
1329 serial_outp(up, UART_MCR, save_mcr);
1330 serial_outp(up, UART_IER, save_ier);
1331
1332 if (up->port.flags & UPF_FOURPORT)
1333 outb_p(save_ICP, ICP);
1334
1335 up->port.irq = (irq > 0) ? irq : 0;
1336}
1337
1338static inline void __stop_tx(struct uart_8250_port *p)
1339{
1340 if (p->ier & UART_IER_THRI) {
1341 p->ier &= ~UART_IER_THRI;
1342 serial_out(p, UART_IER, p->ier);
1343 }
1344}
1345
1346static void serial8250_stop_tx(struct uart_port *port)
1347{
1348 struct uart_8250_port *up =
1349 container_of(port, struct uart_8250_port, port);
1350
1351 __stop_tx(up);
1352
1353 /*
1354 * We really want to stop the transmitter from sending.
1355 */
1356 if (up->port.type == PORT_16C950) {
1357 up->acr |= UART_ACR_TXDIS;
1358 serial_icr_write(up, UART_ACR, up->acr);
1359 }
1360}
1361
1362static void transmit_chars(struct uart_8250_port *up);
1363
1364static void serial8250_start_tx(struct uart_port *port)
1365{
1366 struct uart_8250_port *up =
1367 container_of(port, struct uart_8250_port, port);
1368
1369 if (!(up->ier & UART_IER_THRI)) {
1370 up->ier |= UART_IER_THRI;
1371 serial_out(up, UART_IER, up->ier);
1372
1373 if (up->bugs & UART_BUG_TXEN) {
1374 unsigned char lsr;
1375 lsr = serial_in(up, UART_LSR);
1376 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1377 if ((up->port.type == PORT_RM9000) ?
1378 (lsr & UART_LSR_THRE) :
1379 (lsr & UART_LSR_TEMT))
1380 transmit_chars(up);
1381 }
1382 }
1383
1384 /*
1385 * Re-enable the transmitter if we disabled it.
1386 */
1387 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1388 up->acr &= ~UART_ACR_TXDIS;
1389 serial_icr_write(up, UART_ACR, up->acr);
1390 }
1391}
1392
1393static void serial8250_stop_rx(struct uart_port *port)
1394{
1395 struct uart_8250_port *up =
1396 container_of(port, struct uart_8250_port, port);
1397
1398 up->ier &= ~UART_IER_RLSI;
1399 up->port.read_status_mask &= ~UART_LSR_DR;
1400 serial_out(up, UART_IER, up->ier);
1401}
1402
1403static void serial8250_enable_ms(struct uart_port *port)
1404{
1405 struct uart_8250_port *up =
1406 container_of(port, struct uart_8250_port, port);
1407
1408 /* no MSR capabilities */
1409 if (up->bugs & UART_BUG_NOMSR)
1410 return;
1411
1412 up->ier |= UART_IER_MSI;
1413 serial_out(up, UART_IER, up->ier);
1414}
1415
1416static void
1417receive_chars(struct uart_8250_port *up, unsigned int *status)
1418{
1419 struct tty_struct *tty = up->port.state->port.tty;
1420 unsigned char ch, lsr = *status;
1421 int max_count = 256;
1422 char flag;
1423
1424 do {
1425 if (likely(lsr & UART_LSR_DR))
1426 ch = serial_inp(up, UART_RX);
1427 else
1428 /*
1429 * Intel 82571 has a Serial Over Lan device that will
1430 * set UART_LSR_BI without setting UART_LSR_DR when
1431 * it receives a break. To avoid reading from the
1432 * receive buffer without UART_LSR_DR bit set, we
1433 * just force the read character to be 0
1434 */
1435 ch = 0;
1436
1437 flag = TTY_NORMAL;
1438 up->port.icount.rx++;
1439
1440 lsr |= up->lsr_saved_flags;
1441 up->lsr_saved_flags = 0;
1442
1443 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1444 /*
1445 * For statistics only
1446 */
1447 if (lsr & UART_LSR_BI) {
1448 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1449 up->port.icount.brk++;
1450 /*
1451 * We do the SysRQ and SAK checking
1452 * here because otherwise the break
1453 * may get masked by ignore_status_mask
1454 * or read_status_mask.
1455 */
1456 if (uart_handle_break(&up->port))
1457 goto ignore_char;
1458 } else if (lsr & UART_LSR_PE)
1459 up->port.icount.parity++;
1460 else if (lsr & UART_LSR_FE)
1461 up->port.icount.frame++;
1462 if (lsr & UART_LSR_OE)
1463 up->port.icount.overrun++;
1464
1465 /*
1466 * Mask off conditions which should be ignored.
1467 */
1468 lsr &= up->port.read_status_mask;
1469
1470 if (lsr & UART_LSR_BI) {
1471 DEBUG_INTR("handling break....");
1472 flag = TTY_BREAK;
1473 } else if (lsr & UART_LSR_PE)
1474 flag = TTY_PARITY;
1475 else if (lsr & UART_LSR_FE)
1476 flag = TTY_FRAME;
1477 }
1478 if (uart_handle_sysrq_char(&up->port, ch))
1479 goto ignore_char;
1480
1481 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1482
1483ignore_char:
1484 lsr = serial_inp(up, UART_LSR);
1485 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1486 spin_unlock(&up->port.lock);
1487 tty_flip_buffer_push(tty);
1488 spin_lock(&up->port.lock);
1489 *status = lsr;
1490}
1491
1492static void transmit_chars(struct uart_8250_port *up)
1493{
1494 struct circ_buf *xmit = &up->port.state->xmit;
1495 int count;
1496
1497 if (up->port.x_char) {
1498 serial_outp(up, UART_TX, up->port.x_char);
1499 up->port.icount.tx++;
1500 up->port.x_char = 0;
1501 return;
1502 }
1503 if (uart_tx_stopped(&up->port)) {
1504 serial8250_stop_tx(&up->port);
1505 return;
1506 }
1507 if (uart_circ_empty(xmit)) {
1508 __stop_tx(up);
1509 return;
1510 }
1511
1512 count = up->tx_loadsz;
1513 do {
1514 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1515 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1516 up->port.icount.tx++;
1517 if (uart_circ_empty(xmit))
1518 break;
1519 } while (--count > 0);
1520
1521 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1522 uart_write_wakeup(&up->port);
1523
1524 DEBUG_INTR("THRE...");
1525
1526 if (uart_circ_empty(xmit))
1527 __stop_tx(up);
1528}
1529
1530static unsigned int check_modem_status(struct uart_8250_port *up)
1531{
1532 unsigned int status = serial_in(up, UART_MSR);
1533
1534 status |= up->msr_saved_flags;
1535 up->msr_saved_flags = 0;
1536 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1537 up->port.state != NULL) {
1538 if (status & UART_MSR_TERI)
1539 up->port.icount.rng++;
1540 if (status & UART_MSR_DDSR)
1541 up->port.icount.dsr++;
1542 if (status & UART_MSR_DDCD)
1543 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1544 if (status & UART_MSR_DCTS)
1545 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1546
1547 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
1548 }
1549
1550 return status;
1551}
1552
1553/*
1554 * This handles the interrupt from one port.
1555 */
1556static void serial8250_handle_port(struct uart_8250_port *up)
1557{
1558 unsigned int status;
1559 unsigned long flags;
1560
1561 spin_lock_irqsave(&up->port.lock, flags);
1562
1563 status = serial_inp(up, UART_LSR);
1564
1565 DEBUG_INTR("status = %x...", status);
1566
1567 if (status & (UART_LSR_DR | UART_LSR_BI))
1568 receive_chars(up, &status);
1569 check_modem_status(up);
1570 if (status & UART_LSR_THRE)
1571 transmit_chars(up);
1572
1573 spin_unlock_irqrestore(&up->port.lock, flags);
1574}
1575
1576/*
1577 * This is the serial driver's interrupt routine.
1578 *
1579 * Arjan thinks the old way was overly complex, so it got simplified.
1580 * Alan disagrees, saying that need the complexity to handle the weird
1581 * nature of ISA shared interrupts. (This is a special exception.)
1582 *
1583 * In order to handle ISA shared interrupts properly, we need to check
1584 * that all ports have been serviced, and therefore the ISA interrupt
1585 * line has been de-asserted.
1586 *
1587 * This means we need to loop through all ports. checking that they
1588 * don't have an interrupt pending.
1589 */
1590static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1591{
1592 struct irq_info *i = dev_id;
1593 struct list_head *l, *end = NULL;
1594 int pass_counter = 0, handled = 0;
1595
1596 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1597
1598 spin_lock(&i->lock);
1599
1600 l = i->head;
1601 do {
1602 struct uart_8250_port *up;
1603 unsigned int iir;
1604
1605 up = list_entry(l, struct uart_8250_port, list);
1606
1607 iir = serial_in(up, UART_IIR);
1608 if (!(iir & UART_IIR_NO_INT)) {
1609 serial8250_handle_port(up);
1610
1611 handled = 1;
1612
1613 end = NULL;
1614 } else if ((up->port.iotype == UPIO_DWAPB ||
1615 up->port.iotype == UPIO_DWAPB32) &&
1616 (iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
1617 /* The DesignWare APB UART has an Busy Detect (0x07)
1618 * interrupt meaning an LCR write attempt occured while the
1619 * UART was busy. The interrupt must be cleared by reading
1620 * the UART status register (USR) and the LCR re-written. */
1621 unsigned int status;
1622 status = *(volatile u32 *)up->port.private_data;
1623 serial_out(up, UART_LCR, up->lcr);
1624
1625 handled = 1;
1626
1627 end = NULL;
1628 } else if (end == NULL)
1629 end = l;
1630
1631 l = l->next;
1632
1633 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1634 /* If we hit this, we're dead. */
1635 printk_ratelimited(KERN_ERR
1636 "serial8250: too much work for irq%d\n", irq);
1637 break;
1638 }
1639 } while (l != end);
1640
1641 spin_unlock(&i->lock);
1642
1643 DEBUG_INTR("end.\n");
1644
1645 return IRQ_RETVAL(handled);
1646}
1647
1648/*
1649 * To support ISA shared interrupts, we need to have one interrupt
1650 * handler that ensures that the IRQ line has been deasserted
1651 * before returning. Failing to do this will result in the IRQ
1652 * line being stuck active, and, since ISA irqs are edge triggered,
1653 * no more IRQs will be seen.
1654 */
1655static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1656{
1657 spin_lock_irq(&i->lock);
1658
1659 if (!list_empty(i->head)) {
1660 if (i->head == &up->list)
1661 i->head = i->head->next;
1662 list_del(&up->list);
1663 } else {
1664 BUG_ON(i->head != &up->list);
1665 i->head = NULL;
1666 }
1667 spin_unlock_irq(&i->lock);
1668 /* List empty so throw away the hash node */
1669 if (i->head == NULL) {
1670 hlist_del(&i->node);
1671 kfree(i);
1672 }
1673}
1674
1675static int serial_link_irq_chain(struct uart_8250_port *up)
1676{
1677 struct hlist_head *h;
1678 struct hlist_node *n;
1679 struct irq_info *i;
1680 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1681
1682 mutex_lock(&hash_mutex);
1683
1684 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1685
1686 hlist_for_each(n, h) {
1687 i = hlist_entry(n, struct irq_info, node);
1688 if (i->irq == up->port.irq)
1689 break;
1690 }
1691
1692 if (n == NULL) {
1693 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1694 if (i == NULL) {
1695 mutex_unlock(&hash_mutex);
1696 return -ENOMEM;
1697 }
1698 spin_lock_init(&i->lock);
1699 i->irq = up->port.irq;
1700 hlist_add_head(&i->node, h);
1701 }
1702 mutex_unlock(&hash_mutex);
1703
1704 spin_lock_irq(&i->lock);
1705
1706 if (i->head) {
1707 list_add(&up->list, i->head);
1708 spin_unlock_irq(&i->lock);
1709
1710 ret = 0;
1711 } else {
1712 INIT_LIST_HEAD(&up->list);
1713 i->head = &up->list;
1714 spin_unlock_irq(&i->lock);
1715 irq_flags |= up->port.irqflags;
1716 ret = request_irq(up->port.irq, serial8250_interrupt,
1717 irq_flags, "serial", i);
1718 if (ret < 0)
1719 serial_do_unlink(i, up);
1720 }
1721
1722 return ret;
1723}
1724
1725static void serial_unlink_irq_chain(struct uart_8250_port *up)
1726{
1727 struct irq_info *i;
1728 struct hlist_node *n;
1729 struct hlist_head *h;
1730
1731 mutex_lock(&hash_mutex);
1732
1733 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1734
1735 hlist_for_each(n, h) {
1736 i = hlist_entry(n, struct irq_info, node);
1737 if (i->irq == up->port.irq)
1738 break;
1739 }
1740
1741 BUG_ON(n == NULL);
1742 BUG_ON(i->head == NULL);
1743
1744 if (list_empty(i->head))
1745 free_irq(up->port.irq, i);
1746
1747 serial_do_unlink(i, up);
1748 mutex_unlock(&hash_mutex);
1749}
1750
1751/*
1752 * This function is used to handle ports that do not have an
1753 * interrupt. This doesn't work very well for 16450's, but gives
1754 * barely passable results for a 16550A. (Although at the expense
1755 * of much CPU overhead).
1756 */
1757static void serial8250_timeout(unsigned long data)
1758{
1759 struct uart_8250_port *up = (struct uart_8250_port *)data;
1760 unsigned int iir;
1761
1762 iir = serial_in(up, UART_IIR);
1763 if (!(iir & UART_IIR_NO_INT))
1764 serial8250_handle_port(up);
1765 mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
1766}
1767
1768static void serial8250_backup_timeout(unsigned long data)
1769{
1770 struct uart_8250_port *up = (struct uart_8250_port *)data;
1771 unsigned int iir, ier = 0, lsr;
1772 unsigned long flags;
1773
1774 /*
1775 * Must disable interrupts or else we risk racing with the interrupt
1776 * based handler.
1777 */
1778 if (is_real_interrupt(up->port.irq)) {
1779 ier = serial_in(up, UART_IER);
1780 serial_out(up, UART_IER, 0);
1781 }
1782
1783 iir = serial_in(up, UART_IIR);
1784
1785 /*
1786 * This should be a safe test for anyone who doesn't trust the
1787 * IIR bits on their UART, but it's specifically designed for
1788 * the "Diva" UART used on the management processor on many HP
1789 * ia64 and parisc boxes.
1790 */
1791 spin_lock_irqsave(&up->port.lock, flags);
1792 lsr = serial_in(up, UART_LSR);
1793 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1794 spin_unlock_irqrestore(&up->port.lock, flags);
1795 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1796 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
1797 (lsr & UART_LSR_THRE)) {
1798 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1799 iir |= UART_IIR_THRI;
1800 }
1801
1802 if (!(iir & UART_IIR_NO_INT))
1803 serial8250_handle_port(up);
1804
1805 if (is_real_interrupt(up->port.irq))
1806 serial_out(up, UART_IER, ier);
1807
1808 /* Standard timer interval plus 0.2s to keep the port running */
1809 mod_timer(&up->timer,
1810 jiffies + uart_poll_timeout(&up->port) + HZ / 5);
1811}
1812
1813static unsigned int serial8250_tx_empty(struct uart_port *port)
1814{
1815 struct uart_8250_port *up =
1816 container_of(port, struct uart_8250_port, port);
1817 unsigned long flags;
1818 unsigned int lsr;
1819
1820 spin_lock_irqsave(&up->port.lock, flags);
1821 lsr = serial_in(up, UART_LSR);
1822 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1823 spin_unlock_irqrestore(&up->port.lock, flags);
1824
1825 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1826}
1827
1828static unsigned int serial8250_get_mctrl(struct uart_port *port)
1829{
1830 struct uart_8250_port *up =
1831 container_of(port, struct uart_8250_port, port);
1832 unsigned int status;
1833 unsigned int ret;
1834
1835 status = check_modem_status(up);
1836
1837 ret = 0;
1838 if (status & UART_MSR_DCD)
1839 ret |= TIOCM_CAR;
1840 if (status & UART_MSR_RI)
1841 ret |= TIOCM_RNG;
1842 if (status & UART_MSR_DSR)
1843 ret |= TIOCM_DSR;
1844 if (status & UART_MSR_CTS)
1845 ret |= TIOCM_CTS;
1846 return ret;
1847}
1848
1849static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1850{
1851 struct uart_8250_port *up =
1852 container_of(port, struct uart_8250_port, port);
1853 unsigned char mcr = 0;
1854
1855 if (mctrl & TIOCM_RTS)
1856 mcr |= UART_MCR_RTS;
1857 if (mctrl & TIOCM_DTR)
1858 mcr |= UART_MCR_DTR;
1859 if (mctrl & TIOCM_OUT1)
1860 mcr |= UART_MCR_OUT1;
1861 if (mctrl & TIOCM_OUT2)
1862 mcr |= UART_MCR_OUT2;
1863 if (mctrl & TIOCM_LOOP)
1864 mcr |= UART_MCR_LOOP;
1865
1866 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1867
1868 serial_out(up, UART_MCR, mcr);
1869}
1870
1871static void serial8250_break_ctl(struct uart_port *port, int break_state)
1872{
1873 struct uart_8250_port *up =
1874 container_of(port, struct uart_8250_port, port);
1875 unsigned long flags;
1876
1877 spin_lock_irqsave(&up->port.lock, flags);
1878 if (break_state == -1)
1879 up->lcr |= UART_LCR_SBC;
1880 else
1881 up->lcr &= ~UART_LCR_SBC;
1882 serial_out(up, UART_LCR, up->lcr);
1883 spin_unlock_irqrestore(&up->port.lock, flags);
1884}
1885
1886/*
1887 * Wait for transmitter & holding register to empty
1888 */
1889static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1890{
1891 unsigned int status, tmout = 10000;
1892
1893 /* Wait up to 10ms for the character(s) to be sent. */
1894 for (;;) {
1895 status = serial_in(up, UART_LSR);
1896
1897 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1898
1899 if ((status & bits) == bits)
1900 break;
1901 if (--tmout == 0)
1902 break;
1903 udelay(1);
1904 }
1905
1906 /* Wait up to 1s for flow control if necessary */
1907 if (up->port.flags & UPF_CONS_FLOW) {
1908 unsigned int tmout;
1909 for (tmout = 1000000; tmout; tmout--) {
1910 unsigned int msr = serial_in(up, UART_MSR);
1911 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1912 if (msr & UART_MSR_CTS)
1913 break;
1914 udelay(1);
1915 touch_nmi_watchdog();
1916 }
1917 }
1918}
1919
1920#ifdef CONFIG_CONSOLE_POLL
1921/*
1922 * Console polling routines for writing and reading from the uart while
1923 * in an interrupt or debug context.
1924 */
1925
1926static int serial8250_get_poll_char(struct uart_port *port)
1927{
1928 struct uart_8250_port *up =
1929 container_of(port, struct uart_8250_port, port);
1930 unsigned char lsr = serial_inp(up, UART_LSR);
1931
1932 if (!(lsr & UART_LSR_DR))
1933 return NO_POLL_CHAR;
1934
1935 return serial_inp(up, UART_RX);
1936}
1937
1938
1939static void serial8250_put_poll_char(struct uart_port *port,
1940 unsigned char c)
1941{
1942 unsigned int ier;
1943 struct uart_8250_port *up =
1944 container_of(port, struct uart_8250_port, port);
1945
1946 /*
1947 * First save the IER then disable the interrupts
1948 */
1949 ier = serial_in(up, UART_IER);
1950 if (up->capabilities & UART_CAP_UUE)
1951 serial_out(up, UART_IER, UART_IER_UUE);
1952 else
1953 serial_out(up, UART_IER, 0);
1954
1955 wait_for_xmitr(up, BOTH_EMPTY);
1956 /*
1957 * Send the character out.
1958 * If a LF, also do CR...
1959 */
1960 serial_out(up, UART_TX, c);
1961 if (c == 10) {
1962 wait_for_xmitr(up, BOTH_EMPTY);
1963 serial_out(up, UART_TX, 13);
1964 }
1965
1966 /*
1967 * Finally, wait for transmitter to become empty
1968 * and restore the IER
1969 */
1970 wait_for_xmitr(up, BOTH_EMPTY);
1971 serial_out(up, UART_IER, ier);
1972}
1973
1974#endif /* CONFIG_CONSOLE_POLL */
1975
1976static int serial8250_startup(struct uart_port *port)
1977{
1978 struct uart_8250_port *up =
1979 container_of(port, struct uart_8250_port, port);
1980 unsigned long flags;
1981 unsigned char lsr, iir;
1982 int retval;
1983
1984 up->port.fifosize = uart_config[up->port.type].fifo_size;
1985 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1986 up->capabilities = uart_config[up->port.type].flags;
1987 up->mcr = 0;
1988
1989 if (up->port.iotype != up->cur_iotype)
1990 set_io_from_upio(port);
1991
1992 if (up->port.type == PORT_16C950) {
1993 /* Wake up and initialize UART */
1994 up->acr = 0;
1995 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1996 serial_outp(up, UART_EFR, UART_EFR_ECB);
1997 serial_outp(up, UART_IER, 0);
1998 serial_outp(up, UART_LCR, 0);
1999 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2000 serial_outp(up, UART_LCR, 0xBF);
2001 serial_outp(up, UART_EFR, UART_EFR_ECB);
2002 serial_outp(up, UART_LCR, 0);
2003 }
2004
2005#ifdef CONFIG_SERIAL_8250_RSA
2006 /*
2007 * If this is an RSA port, see if we can kick it up to the
2008 * higher speed clock.
2009 */
2010 enable_rsa(up);
2011#endif
2012
2013 /*
2014 * Clear the FIFO buffers and disable them.
2015 * (they will be reenabled in set_termios())
2016 */
2017 serial8250_clear_fifos(up);
2018
2019 /*
2020 * Clear the interrupt registers.
2021 */
2022 (void) serial_inp(up, UART_LSR);
2023 (void) serial_inp(up, UART_RX);
2024 (void) serial_inp(up, UART_IIR);
2025 (void) serial_inp(up, UART_MSR);
2026
2027 /*
2028 * At this point, there's no way the LSR could still be 0xff;
2029 * if it is, then bail out, because there's likely no UART
2030 * here.
2031 */
2032 if (!(up->port.flags & UPF_BUGGY_UART) &&
2033 (serial_inp(up, UART_LSR) == 0xff)) {
2034 printk(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
2035 serial_index(&up->port));
2036 return -ENODEV;
2037 }
2038
2039 /*
2040 * For a XR16C850, we need to set the trigger levels
2041 */
2042 if (up->port.type == PORT_16850) {
2043 unsigned char fctr;
2044
2045 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
2046
2047 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2048 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2049 serial_outp(up, UART_TRG, UART_TRG_96);
2050 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2051 serial_outp(up, UART_TRG, UART_TRG_96);
2052
2053 serial_outp(up, UART_LCR, 0);
2054 }
2055
2056 if (is_real_interrupt(up->port.irq)) {
2057 unsigned char iir1;
2058 /*
2059 * Test for UARTs that do not reassert THRE when the
2060 * transmitter is idle and the interrupt has already
2061 * been cleared. Real 16550s should always reassert
2062 * this interrupt whenever the transmitter is idle and
2063 * the interrupt is enabled. Delays are necessary to
2064 * allow register changes to become visible.
2065 */
2066 spin_lock_irqsave(&up->port.lock, flags);
2067 if (up->port.irqflags & IRQF_SHARED)
2068 disable_irq_nosync(up->port.irq);
2069
2070 wait_for_xmitr(up, UART_LSR_THRE);
2071 serial_out_sync(up, UART_IER, UART_IER_THRI);
2072 udelay(1); /* allow THRE to set */
2073 iir1 = serial_in(up, UART_IIR);
2074 serial_out(up, UART_IER, 0);
2075 serial_out_sync(up, UART_IER, UART_IER_THRI);
2076 udelay(1); /* allow a working UART time to re-assert THRE */
2077 iir = serial_in(up, UART_IIR);
2078 serial_out(up, UART_IER, 0);
2079
2080 if (up->port.irqflags & IRQF_SHARED)
2081 enable_irq(up->port.irq);
2082 spin_unlock_irqrestore(&up->port.lock, flags);
2083
2084 /*
2085 * If the interrupt is not reasserted, setup a timer to
2086 * kick the UART on a regular basis.
2087 */
2088 if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) {
2089 up->bugs |= UART_BUG_THRE;
2090 pr_debug("ttyS%d - using backup timer\n",
2091 serial_index(port));
2092 }
2093 }
2094
2095 /*
2096 * The above check will only give an accurate result the first time
2097 * the port is opened so this value needs to be preserved.
2098 */
2099 if (up->bugs & UART_BUG_THRE) {
2100 up->timer.function = serial8250_backup_timeout;
2101 up->timer.data = (unsigned long)up;
2102 mod_timer(&up->timer, jiffies +
2103 uart_poll_timeout(port) + HZ / 5);
2104 }
2105
2106 /*
2107 * If the "interrupt" for this port doesn't correspond with any
2108 * hardware interrupt, we use a timer-based system. The original
2109 * driver used to do this with IRQ0.
2110 */
2111 if (!is_real_interrupt(up->port.irq)) {
2112 up->timer.data = (unsigned long)up;
2113 mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
2114 } else {
2115 retval = serial_link_irq_chain(up);
2116 if (retval)
2117 return retval;
2118 }
2119
2120 /*
2121 * Now, initialize the UART
2122 */
2123 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
2124
2125 spin_lock_irqsave(&up->port.lock, flags);
2126 if (up->port.flags & UPF_FOURPORT) {
2127 if (!is_real_interrupt(up->port.irq))
2128 up->port.mctrl |= TIOCM_OUT1;
2129 } else
2130 /*
2131 * Most PC uarts need OUT2 raised to enable interrupts.
2132 */
2133 if (is_real_interrupt(up->port.irq))
2134 up->port.mctrl |= TIOCM_OUT2;
2135
2136 serial8250_set_mctrl(&up->port, up->port.mctrl);
2137
2138 /* Serial over Lan (SoL) hack:
2139 Intel 8257x Gigabit ethernet chips have a
2140 16550 emulation, to be used for Serial Over Lan.
2141 Those chips take a longer time than a normal
2142 serial device to signalize that a transmission
2143 data was queued. Due to that, the above test generally
2144 fails. One solution would be to delay the reading of
2145 iir. However, this is not reliable, since the timeout
2146 is variable. So, let's just don't test if we receive
2147 TX irq. This way, we'll never enable UART_BUG_TXEN.
2148 */
2149 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
2150 goto dont_test_tx_en;
2151
2152 /*
2153 * Do a quick test to see if we receive an
2154 * interrupt when we enable the TX irq.
2155 */
2156 serial_outp(up, UART_IER, UART_IER_THRI);
2157 lsr = serial_in(up, UART_LSR);
2158 iir = serial_in(up, UART_IIR);
2159 serial_outp(up, UART_IER, 0);
2160
2161 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2162 if (!(up->bugs & UART_BUG_TXEN)) {
2163 up->bugs |= UART_BUG_TXEN;
2164 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2165 serial_index(port));
2166 }
2167 } else {
2168 up->bugs &= ~UART_BUG_TXEN;
2169 }
2170
2171dont_test_tx_en:
2172 spin_unlock_irqrestore(&up->port.lock, flags);
2173
2174 /*
2175 * Clear the interrupt registers again for luck, and clear the
2176 * saved flags to avoid getting false values from polling
2177 * routines or the previous session.
2178 */
2179 serial_inp(up, UART_LSR);
2180 serial_inp(up, UART_RX);
2181 serial_inp(up, UART_IIR);
2182 serial_inp(up, UART_MSR);
2183 up->lsr_saved_flags = 0;
2184 up->msr_saved_flags = 0;
2185
2186 /*
2187 * Finally, enable interrupts. Note: Modem status interrupts
2188 * are set via set_termios(), which will be occurring imminently
2189 * anyway, so we don't enable them here.
2190 */
2191 up->ier = UART_IER_RLSI | UART_IER_RDI;
2192 serial_outp(up, UART_IER, up->ier);
2193
2194 if (up->port.flags & UPF_FOURPORT) {
2195 unsigned int icp;
2196 /*
2197 * Enable interrupts on the AST Fourport board
2198 */
2199 icp = (up->port.iobase & 0xfe0) | 0x01f;
2200 outb_p(0x80, icp);
2201 (void) inb_p(icp);
2202 }
2203
2204 return 0;
2205}
2206
2207static void serial8250_shutdown(struct uart_port *port)
2208{
2209 struct uart_8250_port *up =
2210 container_of(port, struct uart_8250_port, port);
2211 unsigned long flags;
2212
2213 /*
2214 * Disable interrupts from this port
2215 */
2216 up->ier = 0;
2217 serial_outp(up, UART_IER, 0);
2218
2219 spin_lock_irqsave(&up->port.lock, flags);
2220 if (up->port.flags & UPF_FOURPORT) {
2221 /* reset interrupts on the AST Fourport board */
2222 inb((up->port.iobase & 0xfe0) | 0x1f);
2223 up->port.mctrl |= TIOCM_OUT1;
2224 } else
2225 up->port.mctrl &= ~TIOCM_OUT2;
2226
2227 serial8250_set_mctrl(&up->port, up->port.mctrl);
2228 spin_unlock_irqrestore(&up->port.lock, flags);
2229
2230 /*
2231 * Disable break condition and FIFOs
2232 */
2233 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
2234 serial8250_clear_fifos(up);
2235
2236#ifdef CONFIG_SERIAL_8250_RSA
2237 /*
2238 * Reset the RSA board back to 115kbps compat mode.
2239 */
2240 disable_rsa(up);
2241#endif
2242
2243 /*
2244 * Read data port to reset things, and then unlink from
2245 * the IRQ chain.
2246 */
2247 (void) serial_in(up, UART_RX);
2248
2249 del_timer_sync(&up->timer);
2250 up->timer.function = serial8250_timeout;
2251 if (is_real_interrupt(up->port.irq))
2252 serial_unlink_irq_chain(up);
2253}
2254
2255static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2256{
2257 unsigned int quot;
2258
2259 /*
2260 * Handle magic divisors for baud rates above baud_base on
2261 * SMSC SuperIO chips.
2262 */
2263 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2264 baud == (port->uartclk/4))
2265 quot = 0x8001;
2266 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2267 baud == (port->uartclk/8))
2268 quot = 0x8002;
2269 else
2270 quot = uart_get_divisor(port, baud);
2271
2272 return quot;
2273}
2274
2275void
2276serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2277 struct ktermios *old)
2278{
2279 struct uart_8250_port *up =
2280 container_of(port, struct uart_8250_port, port);
2281 unsigned char cval, fcr = 0;
2282 unsigned long flags;
2283 unsigned int baud, quot;
2284
2285 switch (termios->c_cflag & CSIZE) {
2286 case CS5:
2287 cval = UART_LCR_WLEN5;
2288 break;
2289 case CS6:
2290 cval = UART_LCR_WLEN6;
2291 break;
2292 case CS7:
2293 cval = UART_LCR_WLEN7;
2294 break;
2295 default:
2296 case CS8:
2297 cval = UART_LCR_WLEN8;
2298 break;
2299 }
2300
2301 if (termios->c_cflag & CSTOPB)
2302 cval |= UART_LCR_STOP;
2303 if (termios->c_cflag & PARENB)
2304 cval |= UART_LCR_PARITY;
2305 if (!(termios->c_cflag & PARODD))
2306 cval |= UART_LCR_EPAR;
2307#ifdef CMSPAR
2308 if (termios->c_cflag & CMSPAR)
2309 cval |= UART_LCR_SPAR;
2310#endif
2311
2312 /*
2313 * Ask the core to calculate the divisor for us.
2314 */
2315 baud = uart_get_baud_rate(port, termios, old,
2316 port->uartclk / 16 / 0xffff,
2317 port->uartclk / 16);
2318 quot = serial8250_get_divisor(port, baud);
2319
2320 /*
2321 * Oxford Semi 952 rev B workaround
2322 */
2323 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2324 quot++;
2325
2326 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2327 if (baud < 2400)
2328 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
2329 else
2330 fcr = uart_config[up->port.type].fcr;
2331 }
2332
2333 /*
2334 * MCR-based auto flow control. When AFE is enabled, RTS will be
2335 * deasserted when the receive FIFO contains more characters than
2336 * the trigger, or the MCR RTS bit is cleared. In the case where
2337 * the remote UART is not using CTS auto flow control, we must
2338 * have sufficient FIFO entries for the latency of the remote
2339 * UART to respond. IOW, at least 32 bytes of FIFO.
2340 */
2341 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2342 up->mcr &= ~UART_MCR_AFE;
2343 if (termios->c_cflag & CRTSCTS)
2344 up->mcr |= UART_MCR_AFE;
2345 }
2346
2347 /*
2348 * Ok, we're now changing the port state. Do it with
2349 * interrupts disabled.
2350 */
2351 spin_lock_irqsave(&up->port.lock, flags);
2352
2353 /*
2354 * Update the per-port timeout.
2355 */
2356 uart_update_timeout(port, termios->c_cflag, baud);
2357
2358 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2359 if (termios->c_iflag & INPCK)
2360 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2361 if (termios->c_iflag & (BRKINT | PARMRK))
2362 up->port.read_status_mask |= UART_LSR_BI;
2363
2364 /*
2365 * Characteres to ignore
2366 */
2367 up->port.ignore_status_mask = 0;
2368 if (termios->c_iflag & IGNPAR)
2369 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2370 if (termios->c_iflag & IGNBRK) {
2371 up->port.ignore_status_mask |= UART_LSR_BI;
2372 /*
2373 * If we're ignoring parity and break indicators,
2374 * ignore overruns too (for real raw support).
2375 */
2376 if (termios->c_iflag & IGNPAR)
2377 up->port.ignore_status_mask |= UART_LSR_OE;
2378 }
2379
2380 /*
2381 * ignore all characters if CREAD is not set
2382 */
2383 if ((termios->c_cflag & CREAD) == 0)
2384 up->port.ignore_status_mask |= UART_LSR_DR;
2385
2386 /*
2387 * CTS flow control flag and modem status interrupts
2388 */
2389 up->ier &= ~UART_IER_MSI;
2390 if (!(up->bugs & UART_BUG_NOMSR) &&
2391 UART_ENABLE_MS(&up->port, termios->c_cflag))
2392 up->ier |= UART_IER_MSI;
2393 if (up->capabilities & UART_CAP_UUE)
2394 up->ier |= UART_IER_UUE | UART_IER_RTOIE;
2395
2396 serial_out(up, UART_IER, up->ier);
2397
2398 if (up->capabilities & UART_CAP_EFR) {
2399 unsigned char efr = 0;
2400 /*
2401 * TI16C752/Startech hardware flow control. FIXME:
2402 * - TI16C752 requires control thresholds to be set.
2403 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2404 */
2405 if (termios->c_cflag & CRTSCTS)
2406 efr |= UART_EFR_CTS;
2407
2408 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
2409 serial_outp(up, UART_EFR, efr);
2410 }
2411
2412#ifdef CONFIG_ARCH_OMAP
2413 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2414 if (cpu_is_omap1510() && is_omap_port(up)) {
2415 if (baud == 115200) {
2416 quot = 1;
2417 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2418 } else
2419 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2420 }
2421#endif
2422
2423 if (up->capabilities & UART_NATSEMI) {
2424 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2425 serial_outp(up, UART_LCR, 0xe0);
2426 } else {
2427 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2428 }
2429
2430 serial_dl_write(up, quot);
2431
2432 /*
2433 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2434 * is written without DLAB set, this mode will be disabled.
2435 */
2436 if (up->port.type == PORT_16750)
2437 serial_outp(up, UART_FCR, fcr);
2438
2439 serial_outp(up, UART_LCR, cval); /* reset DLAB */
2440 up->lcr = cval; /* Save LCR */
2441 if (up->port.type != PORT_16750) {
2442 if (fcr & UART_FCR_ENABLE_FIFO) {
2443 /* emulated UARTs (Lucent Venus 167x) need two steps */
2444 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2445 }
2446 serial_outp(up, UART_FCR, fcr); /* set fcr */
2447 }
2448 serial8250_set_mctrl(&up->port, up->port.mctrl);
2449 spin_unlock_irqrestore(&up->port.lock, flags);
2450 /* Don't rewrite B0 */
2451 if (tty_termios_baud_rate(termios))
2452 tty_termios_encode_baud_rate(termios, baud, baud);
2453}
2454EXPORT_SYMBOL(serial8250_do_set_termios);
2455
2456static void
2457serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2458 struct ktermios *old)
2459{
2460 if (port->set_termios)
2461 port->set_termios(port, termios, old);
2462 else
2463 serial8250_do_set_termios(port, termios, old);
2464}
2465
2466static void
2467serial8250_set_ldisc(struct uart_port *port, int new)
2468{
2469 if (new == N_PPS) {
2470 port->flags |= UPF_HARDPPS_CD;
2471 serial8250_enable_ms(port);
2472 } else
2473 port->flags &= ~UPF_HARDPPS_CD;
2474}
2475
2476
2477void serial8250_do_pm(struct uart_port *port, unsigned int state,
2478 unsigned int oldstate)
2479{
2480 struct uart_8250_port *p =
2481 container_of(port, struct uart_8250_port, port);
2482
2483 serial8250_set_sleep(p, state != 0);
2484}
2485EXPORT_SYMBOL(serial8250_do_pm);
2486
2487static void
2488serial8250_pm(struct uart_port *port, unsigned int state,
2489 unsigned int oldstate)
2490{
2491 if (port->pm)
2492 port->pm(port, state, oldstate);
2493 else
2494 serial8250_do_pm(port, state, oldstate);
2495}
2496
2497static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2498{
2499 if (pt->port.iotype == UPIO_AU)
2500 return 0x1000;
2501#ifdef CONFIG_ARCH_OMAP
2502 if (is_omap_port(pt))
2503 return 0x16 << pt->port.regshift;
2504#endif
2505 return 8 << pt->port.regshift;
2506}
2507
2508/*
2509 * Resource handling.
2510 */
2511static int serial8250_request_std_resource(struct uart_8250_port *up)
2512{
2513 unsigned int size = serial8250_port_size(up);
2514 int ret = 0;
2515
2516 switch (up->port.iotype) {
2517 case UPIO_AU:
2518 case UPIO_TSI:
2519 case UPIO_MEM32:
2520 case UPIO_MEM:
2521 case UPIO_DWAPB:
2522 case UPIO_DWAPB32:
2523 if (!up->port.mapbase)
2524 break;
2525
2526 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2527 ret = -EBUSY;
2528 break;
2529 }
2530
2531 if (up->port.flags & UPF_IOREMAP) {
2532 up->port.membase = ioremap_nocache(up->port.mapbase,
2533 size);
2534 if (!up->port.membase) {
2535 release_mem_region(up->port.mapbase, size);
2536 ret = -ENOMEM;
2537 }
2538 }
2539 break;
2540
2541 case UPIO_HUB6:
2542 case UPIO_PORT:
2543 if (!request_region(up->port.iobase, size, "serial"))
2544 ret = -EBUSY;
2545 break;
2546 }
2547 return ret;
2548}
2549
2550static void serial8250_release_std_resource(struct uart_8250_port *up)
2551{
2552 unsigned int size = serial8250_port_size(up);
2553
2554 switch (up->port.iotype) {
2555 case UPIO_AU:
2556 case UPIO_TSI:
2557 case UPIO_MEM32:
2558 case UPIO_MEM:
2559 case UPIO_DWAPB:
2560 case UPIO_DWAPB32:
2561 if (!up->port.mapbase)
2562 break;
2563
2564 if (up->port.flags & UPF_IOREMAP) {
2565 iounmap(up->port.membase);
2566 up->port.membase = NULL;
2567 }
2568
2569 release_mem_region(up->port.mapbase, size);
2570 break;
2571
2572 case UPIO_HUB6:
2573 case UPIO_PORT:
2574 release_region(up->port.iobase, size);
2575 break;
2576 }
2577}
2578
2579static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2580{
2581 unsigned long start = UART_RSA_BASE << up->port.regshift;
2582 unsigned int size = 8 << up->port.regshift;
2583 int ret = -EINVAL;
2584
2585 switch (up->port.iotype) {
2586 case UPIO_HUB6:
2587 case UPIO_PORT:
2588 start += up->port.iobase;
2589 if (request_region(start, size, "serial-rsa"))
2590 ret = 0;
2591 else
2592 ret = -EBUSY;
2593 break;
2594 }
2595
2596 return ret;
2597}
2598
2599static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2600{
2601 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2602 unsigned int size = 8 << up->port.regshift;
2603
2604 switch (up->port.iotype) {
2605 case UPIO_HUB6:
2606 case UPIO_PORT:
2607 release_region(up->port.iobase + offset, size);
2608 break;
2609 }
2610}
2611
2612static void serial8250_release_port(struct uart_port *port)
2613{
2614 struct uart_8250_port *up =
2615 container_of(port, struct uart_8250_port, port);
2616
2617 serial8250_release_std_resource(up);
2618 if (up->port.type == PORT_RSA)
2619 serial8250_release_rsa_resource(up);
2620}
2621
2622static int serial8250_request_port(struct uart_port *port)
2623{
2624 struct uart_8250_port *up =
2625 container_of(port, struct uart_8250_port, port);
2626 int ret = 0;
2627
2628 ret = serial8250_request_std_resource(up);
2629 if (ret == 0 && up->port.type == PORT_RSA) {
2630 ret = serial8250_request_rsa_resource(up);
2631 if (ret < 0)
2632 serial8250_release_std_resource(up);
2633 }
2634
2635 return ret;
2636}
2637
2638static void serial8250_config_port(struct uart_port *port, int flags)
2639{
2640 struct uart_8250_port *up =
2641 container_of(port, struct uart_8250_port, port);
2642 int probeflags = PROBE_ANY;
2643 int ret;
2644
2645 /*
2646 * Find the region that we can probe for. This in turn
2647 * tells us whether we can probe for the type of port.
2648 */
2649 ret = serial8250_request_std_resource(up);
2650 if (ret < 0)
2651 return;
2652
2653 ret = serial8250_request_rsa_resource(up);
2654 if (ret < 0)
2655 probeflags &= ~PROBE_RSA;
2656
2657 if (up->port.iotype != up->cur_iotype)
2658 set_io_from_upio(port);
2659
2660 if (flags & UART_CONFIG_TYPE)
2661 autoconfig(up, probeflags);
2662
2663 /* if access method is AU, it is a 16550 with a quirk */
2664 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
2665 up->bugs |= UART_BUG_NOMSR;
2666
2667 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2668 autoconfig_irq(up);
2669
2670 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2671 serial8250_release_rsa_resource(up);
2672 if (up->port.type == PORT_UNKNOWN)
2673 serial8250_release_std_resource(up);
2674}
2675
2676static int
2677serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2678{
2679 if (ser->irq >= nr_irqs || ser->irq < 0 ||
2680 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2681 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2682 ser->type == PORT_STARTECH)
2683 return -EINVAL;
2684 return 0;
2685}
2686
2687static const char *
2688serial8250_type(struct uart_port *port)
2689{
2690 int type = port->type;
2691
2692 if (type >= ARRAY_SIZE(uart_config))
2693 type = 0;
2694 return uart_config[type].name;
2695}
2696
2697static struct uart_ops serial8250_pops = {
2698 .tx_empty = serial8250_tx_empty,
2699 .set_mctrl = serial8250_set_mctrl,
2700 .get_mctrl = serial8250_get_mctrl,
2701 .stop_tx = serial8250_stop_tx,
2702 .start_tx = serial8250_start_tx,
2703 .stop_rx = serial8250_stop_rx,
2704 .enable_ms = serial8250_enable_ms,
2705 .break_ctl = serial8250_break_ctl,
2706 .startup = serial8250_startup,
2707 .shutdown = serial8250_shutdown,
2708 .set_termios = serial8250_set_termios,
2709 .set_ldisc = serial8250_set_ldisc,
2710 .pm = serial8250_pm,
2711 .type = serial8250_type,
2712 .release_port = serial8250_release_port,
2713 .request_port = serial8250_request_port,
2714 .config_port = serial8250_config_port,
2715 .verify_port = serial8250_verify_port,
2716#ifdef CONFIG_CONSOLE_POLL
2717 .poll_get_char = serial8250_get_poll_char,
2718 .poll_put_char = serial8250_put_poll_char,
2719#endif
2720};
2721
2722static struct uart_8250_port serial8250_ports[UART_NR];
2723
2724static void (*serial8250_isa_config)(int port, struct uart_port *up,
2725 unsigned short *capabilities);
2726
2727void serial8250_set_isa_configurator(
2728 void (*v)(int port, struct uart_port *up, unsigned short *capabilities))
2729{
2730 serial8250_isa_config = v;
2731}
2732EXPORT_SYMBOL(serial8250_set_isa_configurator);
2733
2734static void __init serial8250_isa_init_ports(void)
2735{
2736 struct uart_8250_port *up;
2737 static int first = 1;
2738 int i, irqflag = 0;
2739
2740 if (!first)
2741 return;
2742 first = 0;
2743
2744 for (i = 0; i < nr_uarts; i++) {
2745 struct uart_8250_port *up = &serial8250_ports[i];
2746
2747 up->port.line = i;
2748 spin_lock_init(&up->port.lock);
2749
2750 init_timer(&up->timer);
2751 up->timer.function = serial8250_timeout;
2752
2753 /*
2754 * ALPHA_KLUDGE_MCR needs to be killed.
2755 */
2756 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2757 up->mcr_force = ALPHA_KLUDGE_MCR;
2758
2759 up->port.ops = &serial8250_pops;
2760 }
2761
2762 if (share_irqs)
2763 irqflag = IRQF_SHARED;
2764
2765 for (i = 0, up = serial8250_ports;
2766 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2767 i++, up++) {
2768 up->port.iobase = old_serial_port[i].port;
2769 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2770 up->port.irqflags = old_serial_port[i].irqflags;
2771 up->port.uartclk = old_serial_port[i].baud_base * 16;
2772 up->port.flags = old_serial_port[i].flags;
2773 up->port.hub6 = old_serial_port[i].hub6;
2774 up->port.membase = old_serial_port[i].iomem_base;
2775 up->port.iotype = old_serial_port[i].io_type;
2776 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2777 set_io_from_upio(&up->port);
2778 up->port.irqflags |= irqflag;
2779 if (serial8250_isa_config != NULL)
2780 serial8250_isa_config(i, &up->port, &up->capabilities);
2781
2782 }
2783}
2784
2785static void
2786serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2787{
2788 up->port.type = type;
2789 up->port.fifosize = uart_config[type].fifo_size;
2790 up->capabilities = uart_config[type].flags;
2791 up->tx_loadsz = uart_config[type].tx_loadsz;
2792}
2793
2794static void __init
2795serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2796{
2797 int i;
2798
2799 for (i = 0; i < nr_uarts; i++) {
2800 struct uart_8250_port *up = &serial8250_ports[i];
2801 up->cur_iotype = 0xFF;
2802 }
2803
2804 serial8250_isa_init_ports();
2805
2806 for (i = 0; i < nr_uarts; i++) {
2807 struct uart_8250_port *up = &serial8250_ports[i];
2808
2809 up->port.dev = dev;
2810
2811 if (up->port.flags & UPF_FIXED_TYPE)
2812 serial8250_init_fixed_type_port(up, up->port.type);
2813
2814 uart_add_one_port(drv, &up->port);
2815 }
2816}
2817
2818#ifdef CONFIG_SERIAL_8250_CONSOLE
2819
2820static void serial8250_console_putchar(struct uart_port *port, int ch)
2821{
2822 struct uart_8250_port *up =
2823 container_of(port, struct uart_8250_port, port);
2824
2825 wait_for_xmitr(up, UART_LSR_THRE);
2826 serial_out(up, UART_TX, ch);
2827}
2828
2829/*
2830 * Print a string to the serial port trying not to disturb
2831 * any possible real use of the port...
2832 *
2833 * The console_lock must be held when we get here.
2834 */
2835static void
2836serial8250_console_write(struct console *co, const char *s, unsigned int count)
2837{
2838 struct uart_8250_port *up = &serial8250_ports[co->index];
2839 unsigned long flags;
2840 unsigned int ier;
2841 int locked = 1;
2842
2843 touch_nmi_watchdog();
2844
2845 local_irq_save(flags);
2846 if (up->port.sysrq) {
2847 /* serial8250_handle_port() already took the lock */
2848 locked = 0;
2849 } else if (oops_in_progress) {
2850 locked = spin_trylock(&up->port.lock);
2851 } else
2852 spin_lock(&up->port.lock);
2853
2854 /*
2855 * First save the IER then disable the interrupts
2856 */
2857 ier = serial_in(up, UART_IER);
2858
2859 if (up->capabilities & UART_CAP_UUE)
2860 serial_out(up, UART_IER, UART_IER_UUE);
2861 else
2862 serial_out(up, UART_IER, 0);
2863
2864 uart_console_write(&up->port, s, count, serial8250_console_putchar);
2865
2866 /*
2867 * Finally, wait for transmitter to become empty
2868 * and restore the IER
2869 */
2870 wait_for_xmitr(up, BOTH_EMPTY);
2871 serial_out(up, UART_IER, ier);
2872
2873 /*
2874 * The receive handling will happen properly because the
2875 * receive ready bit will still be set; it is not cleared
2876 * on read. However, modem control will not, we must
2877 * call it if we have saved something in the saved flags
2878 * while processing with interrupts off.
2879 */
2880 if (up->msr_saved_flags)
2881 check_modem_status(up);
2882
2883 if (locked)
2884 spin_unlock(&up->port.lock);
2885 local_irq_restore(flags);
2886}
2887
2888static int __init serial8250_console_setup(struct console *co, char *options)
2889{
2890 struct uart_port *port;
2891 int baud = 9600;
2892 int bits = 8;
2893 int parity = 'n';
2894 int flow = 'n';
2895
2896 /*
2897 * Check whether an invalid uart number has been specified, and
2898 * if so, search for the first available port that does have
2899 * console support.
2900 */
2901 if (co->index >= nr_uarts)
2902 co->index = 0;
2903 port = &serial8250_ports[co->index].port;
2904 if (!port->iobase && !port->membase)
2905 return -ENODEV;
2906
2907 if (options)
2908 uart_parse_options(options, &baud, &parity, &bits, &flow);
2909
2910 return uart_set_options(port, co, baud, parity, bits, flow);
2911}
2912
2913static int serial8250_console_early_setup(void)
2914{
2915 return serial8250_find_port_for_earlycon();
2916}
2917
2918static struct console serial8250_console = {
2919 .name = "ttyS",
2920 .write = serial8250_console_write,
2921 .device = uart_console_device,
2922 .setup = serial8250_console_setup,
2923 .early_setup = serial8250_console_early_setup,
2924 .flags = CON_PRINTBUFFER | CON_ANYTIME,
2925 .index = -1,
2926 .data = &serial8250_reg,
2927};
2928
2929static int __init serial8250_console_init(void)
2930{
2931 if (nr_uarts > UART_NR)
2932 nr_uarts = UART_NR;
2933
2934 serial8250_isa_init_ports();
2935 register_console(&serial8250_console);
2936 return 0;
2937}
2938console_initcall(serial8250_console_init);
2939
2940int serial8250_find_port(struct uart_port *p)
2941{
2942 int line;
2943 struct uart_port *port;
2944
2945 for (line = 0; line < nr_uarts; line++) {
2946 port = &serial8250_ports[line].port;
2947 if (uart_match_port(p, port))
2948 return line;
2949 }
2950 return -ENODEV;
2951}
2952
2953#define SERIAL8250_CONSOLE &serial8250_console
2954#else
2955#define SERIAL8250_CONSOLE NULL
2956#endif
2957
2958static struct uart_driver serial8250_reg = {
2959 .owner = THIS_MODULE,
2960 .driver_name = "serial",
2961 .dev_name = "ttyS",
2962 .major = TTY_MAJOR,
2963 .minor = 64,
2964 .cons = SERIAL8250_CONSOLE,
2965};
2966
2967/*
2968 * early_serial_setup - early registration for 8250 ports
2969 *
2970 * Setup an 8250 port structure prior to console initialisation. Use
2971 * after console initialisation will cause undefined behaviour.
2972 */
2973int __init early_serial_setup(struct uart_port *port)
2974{
2975 struct uart_port *p;
2976
2977 if (port->line >= ARRAY_SIZE(serial8250_ports))
2978 return -ENODEV;
2979
2980 serial8250_isa_init_ports();
2981 p = &serial8250_ports[port->line].port;
2982 p->iobase = port->iobase;
2983 p->membase = port->membase;
2984 p->irq = port->irq;
2985 p->irqflags = port->irqflags;
2986 p->uartclk = port->uartclk;
2987 p->fifosize = port->fifosize;
2988 p->regshift = port->regshift;
2989 p->iotype = port->iotype;
2990 p->flags = port->flags;
2991 p->mapbase = port->mapbase;
2992 p->private_data = port->private_data;
2993 p->type = port->type;
2994 p->line = port->line;
2995
2996 set_io_from_upio(p);
2997 if (port->serial_in)
2998 p->serial_in = port->serial_in;
2999 if (port->serial_out)
3000 p->serial_out = port->serial_out;
3001
3002 return 0;
3003}
3004
3005/**
3006 * serial8250_suspend_port - suspend one serial port
3007 * @line: serial line number
3008 *
3009 * Suspend one serial port.
3010 */
3011void serial8250_suspend_port(int line)
3012{
3013 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
3014}
3015
3016/**
3017 * serial8250_resume_port - resume one serial port
3018 * @line: serial line number
3019 *
3020 * Resume one serial port.
3021 */
3022void serial8250_resume_port(int line)
3023{
3024 struct uart_8250_port *up = &serial8250_ports[line];
3025
3026 if (up->capabilities & UART_NATSEMI) {
3027 unsigned char tmp;
3028
3029 /* Ensure it's still in high speed mode */
3030 serial_outp(up, UART_LCR, 0xE0);
3031
3032 tmp = serial_in(up, 0x04); /* EXCR2 */
3033 tmp &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
3034 tmp |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
3035 serial_outp(up, 0x04, tmp);
3036
3037 serial_outp(up, UART_LCR, 0);
3038 }
3039 uart_resume_port(&serial8250_reg, &up->port);
3040}
3041
3042/*
3043 * Register a set of serial devices attached to a platform device. The
3044 * list is terminated with a zero flags entry, which means we expect
3045 * all entries to have at least UPF_BOOT_AUTOCONF set.
3046 */
3047static int __devinit serial8250_probe(struct platform_device *dev)
3048{
3049 struct plat_serial8250_port *p = dev->dev.platform_data;
3050 struct uart_port port;
3051 int ret, i, irqflag = 0;
3052
3053 memset(&port, 0, sizeof(struct uart_port));
3054
3055 if (share_irqs)
3056 irqflag = IRQF_SHARED;
3057
3058 for (i = 0; p && p->flags != 0; p++, i++) {
3059 port.iobase = p->iobase;
3060 port.membase = p->membase;
3061 port.irq = p->irq;
3062 port.irqflags = p->irqflags;
3063 port.uartclk = p->uartclk;
3064 port.regshift = p->regshift;
3065 port.iotype = p->iotype;
3066 port.flags = p->flags;
3067 port.mapbase = p->mapbase;
3068 port.hub6 = p->hub6;
3069 port.private_data = p->private_data;
3070 port.type = p->type;
3071 port.serial_in = p->serial_in;
3072 port.serial_out = p->serial_out;
3073 port.set_termios = p->set_termios;
3074 port.pm = p->pm;
3075 port.dev = &dev->dev;
3076 port.irqflags |= irqflag;
3077 ret = serial8250_register_port(&port);
3078 if (ret < 0) {
3079 dev_err(&dev->dev, "unable to register port at index %d "
3080 "(IO%lx MEM%llx IRQ%d): %d\n", i,
3081 p->iobase, (unsigned long long)p->mapbase,
3082 p->irq, ret);
3083 }
3084 }
3085 return 0;
3086}
3087
3088/*
3089 * Remove serial ports registered against a platform device.
3090 */
3091static int __devexit serial8250_remove(struct platform_device *dev)
3092{
3093 int i;
3094
3095 for (i = 0; i < nr_uarts; i++) {
3096 struct uart_8250_port *up = &serial8250_ports[i];
3097
3098 if (up->port.dev == &dev->dev)
3099 serial8250_unregister_port(i);
3100 }
3101 return 0;
3102}
3103
3104static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
3105{
3106 int i;
3107
3108 for (i = 0; i < UART_NR; i++) {
3109 struct uart_8250_port *up = &serial8250_ports[i];
3110
3111 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3112 uart_suspend_port(&serial8250_reg, &up->port);
3113 }
3114
3115 return 0;
3116}
3117
3118static int serial8250_resume(struct platform_device *dev)
3119{
3120 int i;
3121
3122 for (i = 0; i < UART_NR; i++) {
3123 struct uart_8250_port *up = &serial8250_ports[i];
3124
3125 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3126 serial8250_resume_port(i);
3127 }
3128
3129 return 0;
3130}
3131
3132static struct platform_driver serial8250_isa_driver = {
3133 .probe = serial8250_probe,
3134 .remove = __devexit_p(serial8250_remove),
3135 .suspend = serial8250_suspend,
3136 .resume = serial8250_resume,
3137 .driver = {
3138 .name = "serial8250",
3139 .owner = THIS_MODULE,
3140 },
3141};
3142
3143/*
3144 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3145 * in the table in include/asm/serial.h
3146 */
3147static struct platform_device *serial8250_isa_devs;
3148
3149/*
3150 * serial8250_register_port and serial8250_unregister_port allows for
3151 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3152 * modems and PCI multiport cards.
3153 */
3154static DEFINE_MUTEX(serial_mutex);
3155
3156static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3157{
3158 int i;
3159
3160 /*
3161 * First, find a port entry which matches.
3162 */
3163 for (i = 0; i < nr_uarts; i++)
3164 if (uart_match_port(&serial8250_ports[i].port, port))
3165 return &serial8250_ports[i];
3166
3167 /*
3168 * We didn't find a matching entry, so look for the first
3169 * free entry. We look for one which hasn't been previously
3170 * used (indicated by zero iobase).
3171 */
3172 for (i = 0; i < nr_uarts; i++)
3173 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3174 serial8250_ports[i].port.iobase == 0)
3175 return &serial8250_ports[i];
3176
3177 /*
3178 * That also failed. Last resort is to find any entry which
3179 * doesn't have a real port associated with it.
3180 */
3181 for (i = 0; i < nr_uarts; i++)
3182 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3183 return &serial8250_ports[i];
3184
3185 return NULL;
3186}
3187
3188/**
3189 * serial8250_register_port - register a serial port
3190 * @port: serial port template
3191 *
3192 * Configure the serial port specified by the request. If the
3193 * port exists and is in use, it is hung up and unregistered
3194 * first.
3195 *
3196 * The port is then probed and if necessary the IRQ is autodetected
3197 * If this fails an error is returned.
3198 *
3199 * On success the port is ready to use and the line number is returned.
3200 */
3201int serial8250_register_port(struct uart_port *port)
3202{
3203 struct uart_8250_port *uart;
3204 int ret = -ENOSPC;
3205
3206 if (port->uartclk == 0)
3207 return -EINVAL;
3208
3209 mutex_lock(&serial_mutex);
3210
3211 uart = serial8250_find_match_or_unused(port);
3212 if (uart) {
3213 uart_remove_one_port(&serial8250_reg, &uart->port);
3214
3215 uart->port.iobase = port->iobase;
3216 uart->port.membase = port->membase;
3217 uart->port.irq = port->irq;
3218 uart->port.irqflags = port->irqflags;
3219 uart->port.uartclk = port->uartclk;
3220 uart->port.fifosize = port->fifosize;
3221 uart->port.regshift = port->regshift;
3222 uart->port.iotype = port->iotype;
3223 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
3224 uart->port.mapbase = port->mapbase;
3225 uart->port.private_data = port->private_data;
3226 if (port->dev)
3227 uart->port.dev = port->dev;
3228
3229 if (port->flags & UPF_FIXED_TYPE)
3230 serial8250_init_fixed_type_port(uart, port->type);
3231
3232 set_io_from_upio(&uart->port);
3233 /* Possibly override default I/O functions. */
3234 if (port->serial_in)
3235 uart->port.serial_in = port->serial_in;
3236 if (port->serial_out)
3237 uart->port.serial_out = port->serial_out;
3238 /* Possibly override set_termios call */
3239 if (port->set_termios)
3240 uart->port.set_termios = port->set_termios;
3241 if (port->pm)
3242 uart->port.pm = port->pm;
3243
3244 if (serial8250_isa_config != NULL)
3245 serial8250_isa_config(0, &uart->port,
3246 &uart->capabilities);
3247
3248 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3249 if (ret == 0)
3250 ret = uart->port.line;
3251 }
3252 mutex_unlock(&serial_mutex);
3253
3254 return ret;
3255}
3256EXPORT_SYMBOL(serial8250_register_port);
3257
3258/**
3259 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3260 * @line: serial line number
3261 *
3262 * Remove one serial port. This may not be called from interrupt
3263 * context. We hand the port back to the our control.
3264 */
3265void serial8250_unregister_port(int line)
3266{
3267 struct uart_8250_port *uart = &serial8250_ports[line];
3268
3269 mutex_lock(&serial_mutex);
3270 uart_remove_one_port(&serial8250_reg, &uart->port);
3271 if (serial8250_isa_devs) {
3272 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3273 uart->port.type = PORT_UNKNOWN;
3274 uart->port.dev = &serial8250_isa_devs->dev;
3275 uart_add_one_port(&serial8250_reg, &uart->port);
3276 } else {
3277 uart->port.dev = NULL;
3278 }
3279 mutex_unlock(&serial_mutex);
3280}
3281EXPORT_SYMBOL(serial8250_unregister_port);
3282
3283static int __init serial8250_init(void)
3284{
3285 int ret;
3286
3287 if (nr_uarts > UART_NR)
3288 nr_uarts = UART_NR;
3289
3290 printk(KERN_INFO "Serial: 8250/16550 driver, "
3291 "%d ports, IRQ sharing %sabled\n", nr_uarts,
3292 share_irqs ? "en" : "dis");
3293
3294#ifdef CONFIG_SPARC
3295 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3296#else
3297 serial8250_reg.nr = UART_NR;
3298 ret = uart_register_driver(&serial8250_reg);
3299#endif
3300 if (ret)
3301 goto out;
3302
3303 serial8250_isa_devs = platform_device_alloc("serial8250",
3304 PLAT8250_DEV_LEGACY);
3305 if (!serial8250_isa_devs) {
3306 ret = -ENOMEM;
3307 goto unreg_uart_drv;
3308 }
3309
3310 ret = platform_device_add(serial8250_isa_devs);
3311 if (ret)
3312 goto put_dev;
3313
3314 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3315
3316 ret = platform_driver_register(&serial8250_isa_driver);
3317 if (ret == 0)
3318 goto out;
3319
3320 platform_device_del(serial8250_isa_devs);
3321put_dev:
3322 platform_device_put(serial8250_isa_devs);
3323unreg_uart_drv:
3324#ifdef CONFIG_SPARC
3325 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3326#else
3327 uart_unregister_driver(&serial8250_reg);
3328#endif
3329out:
3330 return ret;
3331}
3332
3333static void __exit serial8250_exit(void)
3334{
3335 struct platform_device *isa_dev = serial8250_isa_devs;
3336
3337 /*
3338 * This tells serial8250_unregister_port() not to re-register
3339 * the ports (thereby making serial8250_isa_driver permanently
3340 * in use.)
3341 */
3342 serial8250_isa_devs = NULL;
3343
3344 platform_driver_unregister(&serial8250_isa_driver);
3345 platform_device_unregister(isa_dev);
3346
3347#ifdef CONFIG_SPARC
3348 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3349#else
3350 uart_unregister_driver(&serial8250_reg);
3351#endif
3352}
3353
3354module_init(serial8250_init);
3355module_exit(serial8250_exit);
3356
3357EXPORT_SYMBOL(serial8250_suspend_port);
3358EXPORT_SYMBOL(serial8250_resume_port);
3359
3360MODULE_LICENSE("GPL");
3361MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
3362
3363module_param(share_irqs, uint, 0644);
3364MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3365 " (unsafe)");
3366
3367module_param(nr_uarts, uint, 0644);
3368MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3369
3370module_param(skip_txen_test, uint, 0644);
3371MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3372
3373#ifdef CONFIG_SERIAL_8250_RSA
3374module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3375MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3376#endif
3377MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-26 03:53:19 -0500