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Diffstat (limited to 'drivers/thermal/samsung/exynos_tmu_data.c')
-rw-r--r--drivers/thermal/samsung/exynos_tmu_data.c268
1 files changed, 268 insertions, 0 deletions
diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
new file mode 100644
index 000000000000..073c292baa53
--- /dev/null
+++ b/drivers/thermal/samsung/exynos_tmu_data.c
@@ -0,0 +1,268 @@
1/*
2 * exynos_tmu_data.c - Samsung EXYNOS tmu data file
3 *
4 * Copyright (C) 2013 Samsung Electronics
5 * Amit Daniel Kachhap <amit.daniel@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 */
22
23#include "exynos_thermal_common.h"
24#include "exynos_tmu.h"
25#include "exynos_tmu_data.h"
26
27#if defined(CONFIG_CPU_EXYNOS4210)
28static const struct exynos_tmu_registers exynos4210_tmu_registers = {
29 .triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
30 .triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
31 .triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
32 .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
33 .buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
34 .buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
35 .buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
36 .buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
37 .core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
38 .tmu_status = EXYNOS_TMU_REG_STATUS,
39 .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
40 .threshold_temp = EXYNOS4210_TMU_REG_THRESHOLD_TEMP,
41 .threshold_th0 = EXYNOS4210_TMU_REG_TRIG_LEVEL0,
42 .tmu_inten = EXYNOS_TMU_REG_INTEN,
43 .inten_rise_mask = EXYNOS4210_TMU_TRIG_LEVEL_MASK,
44 .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
45 .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
46 .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
47 .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
48 .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
49 .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
50};
51
52struct exynos_tmu_init_data const exynos4210_default_tmu_data = {
53 .tmu_data = {
54 {
55 .threshold = 80,
56 .trigger_levels[0] = 5,
57 .trigger_levels[1] = 20,
58 .trigger_levels[2] = 30,
59 .trigger_enable[0] = true,
60 .trigger_enable[1] = true,
61 .trigger_enable[2] = true,
62 .trigger_enable[3] = false,
63 .trigger_type[0] = THROTTLE_ACTIVE,
64 .trigger_type[1] = THROTTLE_ACTIVE,
65 .trigger_type[2] = SW_TRIP,
66 .max_trigger_level = 4,
67 .gain = 15,
68 .reference_voltage = 7,
69 .cal_type = TYPE_ONE_POINT_TRIMMING,
70 .min_efuse_value = 40,
71 .max_efuse_value = 100,
72 .first_point_trim = 25,
73 .second_point_trim = 85,
74 .default_temp_offset = 50,
75 .freq_tab[0] = {
76 .freq_clip_max = 800 * 1000,
77 .temp_level = 85,
78 },
79 .freq_tab[1] = {
80 .freq_clip_max = 200 * 1000,
81 .temp_level = 100,
82 },
83 .freq_tab_count = 2,
84 .type = SOC_ARCH_EXYNOS4210,
85 .registers = &exynos4210_tmu_registers,
86 .features = TMU_SUPPORT_READY_STATUS,
87 },
88 },
89 .tmu_count = 1,
90};
91#endif
92
93#if defined(CONFIG_SOC_EXYNOS4412) || defined(CONFIG_SOC_EXYNOS5250)
94static const struct exynos_tmu_registers exynos4412_tmu_registers = {
95 .triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
96 .triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
97 .triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
98 .triminfo_ctrl = EXYNOS_TMU_TRIMINFO_CON,
99 .triminfo_reload_shift = EXYNOS_TRIMINFO_RELOAD_SHIFT,
100 .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
101 .test_mux_addr_shift = EXYNOS4412_MUX_ADDR_SHIFT,
102 .buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
103 .buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
104 .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
105 .therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
106 .therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
107 .buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
108 .buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
109 .core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
110 .tmu_status = EXYNOS_TMU_REG_STATUS,
111 .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
112 .threshold_th0 = EXYNOS_THD_TEMP_RISE,
113 .threshold_th1 = EXYNOS_THD_TEMP_FALL,
114 .tmu_inten = EXYNOS_TMU_REG_INTEN,
115 .inten_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
116 .inten_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
117 .inten_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
118 .inten_fall_shift = EXYNOS_TMU_FALL_INT_SHIFT,
119 .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
120 .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
121 .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
122 .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
123 .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
124 .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
125 .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
126 .emul_con = EXYNOS_EMUL_CON,
127 .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
128 .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
129 .emul_time_mask = EXYNOS_EMUL_TIME_MASK,
130};
131
132#define EXYNOS4412_TMU_DATA \
133 .threshold_falling = 10, \
134 .trigger_levels[0] = 85, \
135 .trigger_levels[1] = 103, \
136 .trigger_levels[2] = 110, \
137 .trigger_levels[3] = 120, \
138 .trigger_enable[0] = true, \
139 .trigger_enable[1] = true, \
140 .trigger_enable[2] = true, \
141 .trigger_enable[3] = false, \
142 .trigger_type[0] = THROTTLE_ACTIVE, \
143 .trigger_type[1] = THROTTLE_ACTIVE, \
144 .trigger_type[2] = SW_TRIP, \
145 .trigger_type[3] = HW_TRIP, \
146 .max_trigger_level = 4, \
147 .gain = 8, \
148 .reference_voltage = 16, \
149 .noise_cancel_mode = 4, \
150 .cal_type = TYPE_ONE_POINT_TRIMMING, \
151 .efuse_value = 55, \
152 .min_efuse_value = 40, \
153 .max_efuse_value = 100, \
154 .first_point_trim = 25, \
155 .second_point_trim = 85, \
156 .default_temp_offset = 50, \
157 .freq_tab[0] = { \
158 .freq_clip_max = 800 * 1000, \
159 .temp_level = 85, \
160 }, \
161 .freq_tab[1] = { \
162 .freq_clip_max = 200 * 1000, \
163 .temp_level = 103, \
164 }, \
165 .freq_tab_count = 2, \
166 .registers = &exynos4412_tmu_registers, \
167 .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
168 TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
169 TMU_SUPPORT_EMUL_TIME)
170#endif
171
172#if defined(CONFIG_SOC_EXYNOS4412)
173struct exynos_tmu_init_data const exynos4412_default_tmu_data = {
174 .tmu_data = {
175 {
176 EXYNOS4412_TMU_DATA,
177 .type = SOC_ARCH_EXYNOS4412,
178 .test_mux = EXYNOS4412_MUX_ADDR_VALUE,
179 },
180 },
181 .tmu_count = 1,
182};
183#endif
184
185#if defined(CONFIG_SOC_EXYNOS5250)
186struct exynos_tmu_init_data const exynos5250_default_tmu_data = {
187 .tmu_data = {
188 {
189 EXYNOS4412_TMU_DATA,
190 .type = SOC_ARCH_EXYNOS5250,
191 },
192 },
193 .tmu_count = 1,
194};
195#endif
196
197#if defined(CONFIG_SOC_EXYNOS5440)
198static const struct exynos_tmu_registers exynos5440_tmu_registers = {
199 .triminfo_data = EXYNOS5440_TMU_S0_7_TRIM,
200 .triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
201 .triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
202 .tmu_ctrl = EXYNOS5440_TMU_S0_7_CTRL,
203 .buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
204 .buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
205 .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
206 .therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
207 .therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
208 .buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
209 .buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
210 .calib_mode_shift = EXYNOS_TMU_CALIB_MODE_SHIFT,
211 .calib_mode_mask = EXYNOS_TMU_CALIB_MODE_MASK,
212 .core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
213 .tmu_status = EXYNOS5440_TMU_S0_7_STATUS,
214 .tmu_cur_temp = EXYNOS5440_TMU_S0_7_TEMP,
215 .threshold_th0 = EXYNOS5440_TMU_S0_7_TH0,
216 .threshold_th1 = EXYNOS5440_TMU_S0_7_TH1,
217 .threshold_th2 = EXYNOS5440_TMU_S0_7_TH2,
218 .threshold_th3_l0_shift = EXYNOS5440_TMU_TH_RISE4_SHIFT,
219 .tmu_inten = EXYNOS5440_TMU_S0_7_IRQEN,
220 .inten_rise_mask = EXYNOS5440_TMU_RISE_INT_MASK,
221 .inten_rise_shift = EXYNOS5440_TMU_RISE_INT_SHIFT,
222 .inten_fall_mask = EXYNOS5440_TMU_FALL_INT_MASK,
223 .inten_fall_shift = EXYNOS5440_TMU_FALL_INT_SHIFT,
224 .inten_rise0_shift = EXYNOS5440_TMU_INTEN_RISE0_SHIFT,
225 .inten_rise1_shift = EXYNOS5440_TMU_INTEN_RISE1_SHIFT,
226 .inten_rise2_shift = EXYNOS5440_TMU_INTEN_RISE2_SHIFT,
227 .inten_rise3_shift = EXYNOS5440_TMU_INTEN_RISE3_SHIFT,
228 .inten_fall0_shift = EXYNOS5440_TMU_INTEN_FALL0_SHIFT,
229 .tmu_intstat = EXYNOS5440_TMU_S0_7_IRQ,
230 .tmu_intclear = EXYNOS5440_TMU_S0_7_IRQ,
231 .tmu_irqstatus = EXYNOS5440_TMU_IRQ_STATUS,
232 .emul_con = EXYNOS5440_TMU_S0_7_DEBUG,
233 .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
234 .tmu_pmin = EXYNOS5440_TMU_PMIN,
235};
236
237#define EXYNOS5440_TMU_DATA \
238 .trigger_levels[0] = 100, \
239 .trigger_levels[4] = 105, \
240 .trigger_enable[0] = 1, \
241 .trigger_type[0] = SW_TRIP, \
242 .trigger_type[4] = HW_TRIP, \
243 .max_trigger_level = 5, \
244 .gain = 5, \
245 .reference_voltage = 16, \
246 .noise_cancel_mode = 4, \
247 .cal_type = TYPE_ONE_POINT_TRIMMING, \
248 .cal_mode = 0, \
249 .efuse_value = 0x5b2d, \
250 .min_efuse_value = 16, \
251 .max_efuse_value = 76, \
252 .first_point_trim = 25, \
253 .second_point_trim = 70, \
254 .default_temp_offset = 25, \
255 .type = SOC_ARCH_EXYNOS5440, \
256 .registers = &exynos5440_tmu_registers, \
257 .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
258 TMU_SUPPORT_MULTI_INST | TMU_SUPPORT_SHARED_MEMORY),
259
260struct exynos_tmu_init_data const exynos5440_default_tmu_data = {
261 .tmu_data = {
262 { EXYNOS5440_TMU_DATA } ,
263 { EXYNOS5440_TMU_DATA } ,
264 { EXYNOS5440_TMU_DATA } ,
265 },
266 .tmu_count = 3,
267};
268#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-28 11:37:16 -0500