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path: root/drivers/thermal/exynos_thermal.c
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Diffstat (limited to 'drivers/thermal/exynos_thermal.c')
-rw-r--r--drivers/thermal/exynos_thermal.c351
1 files changed, 224 insertions, 127 deletions
diff --git a/drivers/thermal/exynos_thermal.c b/drivers/thermal/exynos_thermal.c
index 556d15b4b029..c9a33dd5e4d8 100644
--- a/drivers/thermal/exynos_thermal.c
+++ b/drivers/thermal/exynos_thermal.c
@@ -33,44 +33,83 @@
33#include <linux/kobject.h> 33#include <linux/kobject.h>
34#include <linux/io.h> 34#include <linux/io.h>
35#include <linux/mutex.h> 35#include <linux/mutex.h>
36
37#include <linux/platform_data/exynos_thermal.h> 36#include <linux/platform_data/exynos_thermal.h>
38 37#include <linux/of.h>
39#define EXYNOS4_TMU_REG_TRIMINFO 0x0 38
40#define EXYNOS4_TMU_REG_CONTROL 0x20 39#include <plat/cpu.h>
41#define EXYNOS4_TMU_REG_STATUS 0x28 40
42#define EXYNOS4_TMU_REG_CURRENT_TEMP 0x40 41/* Exynos generic registers */
43#define EXYNOS4_TMU_REG_THRESHOLD_TEMP 0x44 42#define EXYNOS_TMU_REG_TRIMINFO 0x0
44#define EXYNOS4_TMU_REG_TRIG_LEVEL0 0x50 43#define EXYNOS_TMU_REG_CONTROL 0x20
45#define EXYNOS4_TMU_REG_TRIG_LEVEL1 0x54 44#define EXYNOS_TMU_REG_STATUS 0x28
46#define EXYNOS4_TMU_REG_TRIG_LEVEL2 0x58 45#define EXYNOS_TMU_REG_CURRENT_TEMP 0x40
47#define EXYNOS4_TMU_REG_TRIG_LEVEL3 0x5C 46#define EXYNOS_TMU_REG_INTEN 0x70
48#define EXYNOS4_TMU_REG_PAST_TEMP0 0x60 47#define EXYNOS_TMU_REG_INTSTAT 0x74
49#define EXYNOS4_TMU_REG_PAST_TEMP1 0x64 48#define EXYNOS_TMU_REG_INTCLEAR 0x78
50#define EXYNOS4_TMU_REG_PAST_TEMP2 0x68 49
51#define EXYNOS4_TMU_REG_PAST_TEMP3 0x6C 50#define EXYNOS_TMU_TRIM_TEMP_MASK 0xff
52#define EXYNOS4_TMU_REG_INTEN 0x70 51#define EXYNOS_TMU_GAIN_SHIFT 8
53#define EXYNOS4_TMU_REG_INTSTAT 0x74 52#define EXYNOS_TMU_REF_VOLTAGE_SHIFT 24
54#define EXYNOS4_TMU_REG_INTCLEAR 0x78 53#define EXYNOS_TMU_CORE_ON 3
55 54#define EXYNOS_TMU_CORE_OFF 2
56#define EXYNOS4_TMU_GAIN_SHIFT 8 55#define EXYNOS_TMU_DEF_CODE_TO_TEMP_OFFSET 50
57#define EXYNOS4_TMU_REF_VOLTAGE_SHIFT 24 56
58 57/* Exynos4210 specific registers */
59#define EXYNOS4_TMU_TRIM_TEMP_MASK 0xff 58#define EXYNOS4210_TMU_REG_THRESHOLD_TEMP 0x44
60#define EXYNOS4_TMU_CORE_ON 3 59#define EXYNOS4210_TMU_REG_TRIG_LEVEL0 0x50
61#define EXYNOS4_TMU_CORE_OFF 2 60#define EXYNOS4210_TMU_REG_TRIG_LEVEL1 0x54
62#define EXYNOS4_TMU_DEF_CODE_TO_TEMP_OFFSET 50 61#define EXYNOS4210_TMU_REG_TRIG_LEVEL2 0x58
63#define EXYNOS4_TMU_TRIG_LEVEL0_MASK 0x1 62#define EXYNOS4210_TMU_REG_TRIG_LEVEL3 0x5C
64#define EXYNOS4_TMU_TRIG_LEVEL1_MASK 0x10 63#define EXYNOS4210_TMU_REG_PAST_TEMP0 0x60
65#define EXYNOS4_TMU_TRIG_LEVEL2_MASK 0x100 64#define EXYNOS4210_TMU_REG_PAST_TEMP1 0x64
66#define EXYNOS4_TMU_TRIG_LEVEL3_MASK 0x1000 65#define EXYNOS4210_TMU_REG_PAST_TEMP2 0x68
67#define EXYNOS4_TMU_INTCLEAR_VAL 0x1111 66#define EXYNOS4210_TMU_REG_PAST_TEMP3 0x6C
68 67
69struct exynos4_tmu_data { 68#define EXYNOS4210_TMU_TRIG_LEVEL0_MASK 0x1
70 struct exynos4_tmu_platform_data *pdata; 69#define EXYNOS4210_TMU_TRIG_LEVEL1_MASK 0x10
70#define EXYNOS4210_TMU_TRIG_LEVEL2_MASK 0x100
71#define EXYNOS4210_TMU_TRIG_LEVEL3_MASK 0x1000
72#define EXYNOS4210_TMU_INTCLEAR_VAL 0x1111
73
74/* Exynos5250 and Exynos4412 specific registers */
75#define EXYNOS_TMU_TRIMINFO_CON 0x14
76#define EXYNOS_THD_TEMP_RISE 0x50
77#define EXYNOS_THD_TEMP_FALL 0x54
78#define EXYNOS_EMUL_CON 0x80
79
80#define EXYNOS_TRIMINFO_RELOAD 0x1
81#define EXYNOS_TMU_CLEAR_RISE_INT 0x111
82#define EXYNOS_TMU_CLEAR_FALL_INT (0x111 << 16)
83#define EXYNOS_MUX_ADDR_VALUE 6
84#define EXYNOS_MUX_ADDR_SHIFT 20
85#define EXYNOS_TMU_TRIP_MODE_SHIFT 13
86
87#define EFUSE_MIN_VALUE 40
88#define EFUSE_MAX_VALUE 100
89
90/* In-kernel thermal framework related macros & definations */
91#define SENSOR_NAME_LEN 16
92#define MAX_TRIP_COUNT 8
93#define MAX_COOLING_DEVICE 4
94
95#define ACTIVE_INTERVAL 500
96#define IDLE_INTERVAL 10000
97
98/* CPU Zone information */
99#define PANIC_ZONE 4
100#define WARN_ZONE 3
101#define MONITOR_ZONE 2
102#define SAFE_ZONE 1
103
104#define GET_ZONE(trip) (trip + 2)
105#define GET_TRIP(zone) (zone - 2)
106
107struct exynos_tmu_data {
108 struct exynos_tmu_platform_data *pdata;
71 struct resource *mem; 109 struct resource *mem;
72 void __iomem *base; 110 void __iomem *base;
73 int irq; 111 int irq;
112 enum soc_type soc;
74 struct work_struct irq_work; 113 struct work_struct irq_work;
75 struct mutex lock; 114 struct mutex lock;
76 struct clk *clk; 115 struct clk *clk;
@@ -81,16 +120,17 @@ struct exynos4_tmu_data {
81 * TMU treats temperature as a mapped temperature code. 120 * TMU treats temperature as a mapped temperature code.
82 * The temperature is converted differently depending on the calibration type. 121 * The temperature is converted differently depending on the calibration type.
83 */ 122 */
84static int temp_to_code(struct exynos4_tmu_data *data, u8 temp) 123static int temp_to_code(struct exynos_tmu_data *data, u8 temp)
85{ 124{
86 struct exynos4_tmu_platform_data *pdata = data->pdata; 125 struct exynos_tmu_platform_data *pdata = data->pdata;
87 int temp_code; 126 int temp_code;
88 127
89 /* temp should range between 25 and 125 */ 128 if (data->soc == SOC_ARCH_EXYNOS4210)
90 if (temp < 25 || temp > 125) { 129 /* temp should range between 25 and 125 */
91 temp_code = -EINVAL; 130 if (temp < 25 || temp > 125) {
92 goto out; 131 temp_code = -EINVAL;
93 } 132 goto out;
133 }
94 134
95 switch (pdata->cal_type) { 135 switch (pdata->cal_type) {
96 case TYPE_TWO_POINT_TRIMMING: 136 case TYPE_TWO_POINT_TRIMMING:
@@ -102,7 +142,7 @@ static int temp_to_code(struct exynos4_tmu_data *data, u8 temp)
102 temp_code = temp + data->temp_error1 - 25; 142 temp_code = temp + data->temp_error1 - 25;
103 break; 143 break;
104 default: 144 default:
105 temp_code = temp + EXYNOS4_TMU_DEF_CODE_TO_TEMP_OFFSET; 145 temp_code = temp + EXYNOS_TMU_DEF_CODE_TO_TEMP_OFFSET;
106 break; 146 break;
107 } 147 }
108out: 148out:
@@ -113,16 +153,17 @@ out:
113 * Calculate a temperature value from a temperature code. 153 * Calculate a temperature value from a temperature code.
114 * The unit of the temperature is degree Celsius. 154 * The unit of the temperature is degree Celsius.
115 */ 155 */
116static int code_to_temp(struct exynos4_tmu_data *data, u8 temp_code) 156static int code_to_temp(struct exynos_tmu_data *data, u8 temp_code)
117{ 157{
118 struct exynos4_tmu_platform_data *pdata = data->pdata; 158 struct exynos_tmu_platform_data *pdata = data->pdata;
119 int temp; 159 int temp;
120 160
121 /* temp_code should range between 75 and 175 */ 161 if (data->soc == SOC_ARCH_EXYNOS4210)
122 if (temp_code < 75 || temp_code > 175) { 162 /* temp_code should range between 75 and 175 */
123 temp = -ENODATA; 163 if (temp_code < 75 || temp_code > 175) {
124 goto out; 164 temp = -ENODATA;
125 } 165 goto out;
166 }
126 167
127 switch (pdata->cal_type) { 168 switch (pdata->cal_type) {
128 case TYPE_TWO_POINT_TRIMMING: 169 case TYPE_TWO_POINT_TRIMMING:
@@ -133,54 +174,92 @@ static int code_to_temp(struct exynos4_tmu_data *data, u8 temp_code)
133 temp = temp_code - data->temp_error1 + 25; 174 temp = temp_code - data->temp_error1 + 25;
134 break; 175 break;
135 default: 176 default:
136 temp = temp_code - EXYNOS4_TMU_DEF_CODE_TO_TEMP_OFFSET; 177 temp = temp_code - EXYNOS_TMU_DEF_CODE_TO_TEMP_OFFSET;
137 break; 178 break;
138 } 179 }
139out: 180out:
140 return temp; 181 return temp;
141} 182}
142 183
143static int exynos4_tmu_initialize(struct platform_device *pdev) 184static int exynos_tmu_initialize(struct platform_device *pdev)
144{ 185{
145 struct exynos4_tmu_data *data = platform_get_drvdata(pdev); 186 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
146 struct exynos4_tmu_platform_data *pdata = data->pdata; 187 struct exynos_tmu_platform_data *pdata = data->pdata;
147 unsigned int status, trim_info; 188 unsigned int status, trim_info, rising_threshold;
148 int ret = 0, threshold_code; 189 int ret = 0, threshold_code;
149 190
150 mutex_lock(&data->lock); 191 mutex_lock(&data->lock);
151 clk_enable(data->clk); 192 clk_enable(data->clk);
152 193
153 status = readb(data->base + EXYNOS4_TMU_REG_STATUS); 194 status = readb(data->base + EXYNOS_TMU_REG_STATUS);
154 if (!status) { 195 if (!status) {
155 ret = -EBUSY; 196 ret = -EBUSY;
156 goto out; 197 goto out;
157 } 198 }
158 199
200 if (data->soc == SOC_ARCH_EXYNOS) {
201 __raw_writel(EXYNOS_TRIMINFO_RELOAD,
202 data->base + EXYNOS_TMU_TRIMINFO_CON);
203 }
159 /* Save trimming info in order to perform calibration */ 204 /* Save trimming info in order to perform calibration */
160 trim_info = readl(data->base + EXYNOS4_TMU_REG_TRIMINFO); 205 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
161 data->temp_error1 = trim_info & EXYNOS4_TMU_TRIM_TEMP_MASK; 206 data->temp_error1 = trim_info & EXYNOS_TMU_TRIM_TEMP_MASK;
162 data->temp_error2 = ((trim_info >> 8) & EXYNOS4_TMU_TRIM_TEMP_MASK); 207 data->temp_error2 = ((trim_info >> 8) & EXYNOS_TMU_TRIM_TEMP_MASK);
163 208
164 /* Write temperature code for threshold */ 209 if ((EFUSE_MIN_VALUE > data->temp_error1) ||
165 threshold_code = temp_to_code(data, pdata->threshold); 210 (data->temp_error1 > EFUSE_MAX_VALUE) ||
166 if (threshold_code < 0) { 211 (data->temp_error2 != 0))
167 ret = threshold_code; 212 data->temp_error1 = pdata->efuse_value;
168 goto out; 213
214 if (data->soc == SOC_ARCH_EXYNOS4210) {
215 /* Write temperature code for threshold */
216 threshold_code = temp_to_code(data, pdata->threshold);
217 if (threshold_code < 0) {
218 ret = threshold_code;
219 goto out;
220 }
221 writeb(threshold_code,
222 data->base + EXYNOS4210_TMU_REG_THRESHOLD_TEMP);
223
224 writeb(pdata->trigger_levels[0],
225 data->base + EXYNOS4210_TMU_REG_TRIG_LEVEL0);
226 writeb(pdata->trigger_levels[1],
227 data->base + EXYNOS4210_TMU_REG_TRIG_LEVEL1);
228 writeb(pdata->trigger_levels[2],
229 data->base + EXYNOS4210_TMU_REG_TRIG_LEVEL2);
230 writeb(pdata->trigger_levels[3],
231 data->base + EXYNOS4210_TMU_REG_TRIG_LEVEL3);
232
233 writel(EXYNOS4210_TMU_INTCLEAR_VAL,
234 data->base + EXYNOS_TMU_REG_INTCLEAR);
235 } else if (data->soc == SOC_ARCH_EXYNOS) {
236 /* Write temperature code for threshold */
237 threshold_code = temp_to_code(data, pdata->trigger_levels[0]);
238 if (threshold_code < 0) {
239 ret = threshold_code;
240 goto out;
241 }
242 rising_threshold = threshold_code;
243 threshold_code = temp_to_code(data, pdata->trigger_levels[1]);
244 if (threshold_code < 0) {
245 ret = threshold_code;
246 goto out;
247 }
248 rising_threshold |= (threshold_code << 8);
249 threshold_code = temp_to_code(data, pdata->trigger_levels[2]);
250 if (threshold_code < 0) {
251 ret = threshold_code;
252 goto out;
253 }
254 rising_threshold |= (threshold_code << 16);
255
256 writel(rising_threshold,
257 data->base + EXYNOS_THD_TEMP_RISE);
258 writel(0, data->base + EXYNOS_THD_TEMP_FALL);
259
260 writel(EXYNOS_TMU_CLEAR_RISE_INT|EXYNOS_TMU_CLEAR_FALL_INT,
261 data->base + EXYNOS_TMU_REG_INTCLEAR);
169 } 262 }
170 writeb(threshold_code,
171 data->base + EXYNOS4_TMU_REG_THRESHOLD_TEMP);
172
173 writeb(pdata->trigger_levels[0],
174 data->base + EXYNOS4_TMU_REG_TRIG_LEVEL0);
175 writeb(pdata->trigger_levels[1],
176 data->base + EXYNOS4_TMU_REG_TRIG_LEVEL1);
177 writeb(pdata->trigger_levels[2],
178 data->base + EXYNOS4_TMU_REG_TRIG_LEVEL2);
179 writeb(pdata->trigger_levels[3],
180 data->base + EXYNOS4_TMU_REG_TRIG_LEVEL3);
181
182 writel(EXYNOS4_TMU_INTCLEAR_VAL,
183 data->base + EXYNOS4_TMU_REG_INTCLEAR);
184out: 263out:
185 clk_disable(data->clk); 264 clk_disable(data->clk);
186 mutex_unlock(&data->lock); 265 mutex_unlock(&data->lock);
@@ -188,35 +267,41 @@ out:
188 return ret; 267 return ret;
189} 268}
190 269
191static void exynos4_tmu_control(struct platform_device *pdev, bool on) 270static void exynos_tmu_control(struct platform_device *pdev, bool on)
192{ 271{
193 struct exynos4_tmu_data *data = platform_get_drvdata(pdev); 272 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
194 struct exynos4_tmu_platform_data *pdata = data->pdata; 273 struct exynos_tmu_platform_data *pdata = data->pdata;
195 unsigned int con, interrupt_en; 274 unsigned int con, interrupt_en;
196 275
197 mutex_lock(&data->lock); 276 mutex_lock(&data->lock);
198 clk_enable(data->clk); 277 clk_enable(data->clk);
199 278
200 con = pdata->reference_voltage << EXYNOS4_TMU_REF_VOLTAGE_SHIFT | 279 con = pdata->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT |
201 pdata->gain << EXYNOS4_TMU_GAIN_SHIFT; 280 pdata->gain << EXYNOS_TMU_GAIN_SHIFT;
281
282 if (data->soc == SOC_ARCH_EXYNOS) {
283 con |= pdata->noise_cancel_mode << EXYNOS_TMU_TRIP_MODE_SHIFT;
284 con |= (EXYNOS_MUX_ADDR_VALUE << EXYNOS_MUX_ADDR_SHIFT);
285 }
286
202 if (on) { 287 if (on) {
203 con |= EXYNOS4_TMU_CORE_ON; 288 con |= EXYNOS_TMU_CORE_ON;
204 interrupt_en = pdata->trigger_level3_en << 12 | 289 interrupt_en = pdata->trigger_level3_en << 12 |
205 pdata->trigger_level2_en << 8 | 290 pdata->trigger_level2_en << 8 |
206 pdata->trigger_level1_en << 4 | 291 pdata->trigger_level1_en << 4 |
207 pdata->trigger_level0_en; 292 pdata->trigger_level0_en;
208 } else { 293 } else {
209 con |= EXYNOS4_TMU_CORE_OFF; 294 con |= EXYNOS_TMU_CORE_OFF;
210 interrupt_en = 0; /* Disable all interrupts */ 295 interrupt_en = 0; /* Disable all interrupts */
211 } 296 }
212 writel(interrupt_en, data->base + EXYNOS4_TMU_REG_INTEN); 297 writel(interrupt_en, data->base + EXYNOS_TMU_REG_INTEN);
213 writel(con, data->base + EXYNOS4_TMU_REG_CONTROL); 298 writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
214 299
215 clk_disable(data->clk); 300 clk_disable(data->clk);
216 mutex_unlock(&data->lock); 301 mutex_unlock(&data->lock);
217} 302}
218 303
219static int exynos4_tmu_read(struct exynos4_tmu_data *data) 304static int exynos_tmu_read(struct exynos_tmu_data *data)
220{ 305{
221 u8 temp_code; 306 u8 temp_code;
222 int temp; 307 int temp;
@@ -224,7 +309,7 @@ static int exynos4_tmu_read(struct exynos4_tmu_data *data)
224 mutex_lock(&data->lock); 309 mutex_lock(&data->lock);
225 clk_enable(data->clk); 310 clk_enable(data->clk);
226 311
227 temp_code = readb(data->base + EXYNOS4_TMU_REG_CURRENT_TEMP); 312 temp_code = readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP);
228 temp = code_to_temp(data, temp_code); 313 temp = code_to_temp(data, temp_code);
229 314
230 clk_disable(data->clk); 315 clk_disable(data->clk);
@@ -233,25 +318,30 @@ static int exynos4_tmu_read(struct exynos4_tmu_data *data)
233 return temp; 318 return temp;
234} 319}
235 320
236static void exynos4_tmu_work(struct work_struct *work) 321static void exynos_tmu_work(struct work_struct *work)
237{ 322{
238 struct exynos4_tmu_data *data = container_of(work, 323 struct exynos_tmu_data *data = container_of(work,
239 struct exynos4_tmu_data, irq_work); 324 struct exynos_tmu_data, irq_work);
240 325
241 mutex_lock(&data->lock); 326 mutex_lock(&data->lock);
242 clk_enable(data->clk); 327 clk_enable(data->clk);
243 328
244 writel(EXYNOS4_TMU_INTCLEAR_VAL, data->base + EXYNOS4_TMU_REG_INTCLEAR);
245 329
246 enable_irq(data->irq); 330 if (data->soc == SOC_ARCH_EXYNOS)
331 writel(EXYNOS_TMU_CLEAR_RISE_INT,
332 data->base + EXYNOS_TMU_REG_INTCLEAR);
333 else
334 writel(EXYNOS4210_TMU_INTCLEAR_VAL,
335 data->base + EXYNOS_TMU_REG_INTCLEAR);
247 336
248 clk_disable(data->clk); 337 clk_disable(data->clk);
249 mutex_unlock(&data->lock); 338 mutex_unlock(&data->lock);
339 enable_irq(data->irq);
250} 340}
251 341
252static irqreturn_t exynos4_tmu_irq(int irq, void *id) 342static irqreturn_t exynos_tmu_irq(int irq, void *id)
253{ 343{
254 struct exynos4_tmu_data *data = id; 344 struct exynos_tmu_data *data = id;
255 345
256 disable_irq_nosync(irq); 346 disable_irq_nosync(irq);
257 schedule_work(&data->irq_work); 347 schedule_work(&data->irq_work);
@@ -259,18 +349,17 @@ static irqreturn_t exynos4_tmu_irq(int irq, void *id)
259 return IRQ_HANDLED; 349 return IRQ_HANDLED;
260} 350}
261 351
262static int __devinit exynos4_tmu_probe(struct platform_device *pdev) 352static int __devinit exynos_tmu_probe(struct platform_device *pdev)
263{ 353{
264 struct exynos4_tmu_data *data; 354 struct exynos_tmu_data *data;
265 struct exynos4_tmu_platform_data *pdata = pdev->dev.platform_data; 355 struct exynos_tmu_platform_data *pdata = pdev->dev.platform_data;
266 int ret; 356 int ret;
267 357
268 if (!pdata) { 358 if (!pdata) {
269 dev_err(&pdev->dev, "No platform init data supplied.\n"); 359 dev_err(&pdev->dev, "No platform init data supplied.\n");
270 return -ENODEV; 360 return -ENODEV;
271 } 361 }
272 362 data = kzalloc(sizeof(struct exynos_tmu_data), GFP_KERNEL);
273 data = kzalloc(sizeof(struct exynos4_tmu_data), GFP_KERNEL);
274 if (!data) { 363 if (!data) {
275 dev_err(&pdev->dev, "Failed to allocate driver structure\n"); 364 dev_err(&pdev->dev, "Failed to allocate driver structure\n");
276 return -ENOMEM; 365 return -ENOMEM;
@@ -283,7 +372,7 @@ static int __devinit exynos4_tmu_probe(struct platform_device *pdev)
283 goto err_free; 372 goto err_free;
284 } 373 }
285 374
286 INIT_WORK(&data->irq_work, exynos4_tmu_work); 375 INIT_WORK(&data->irq_work, exynos_tmu_work);
287 376
288 data->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 377 data->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
289 if (!data->mem) { 378 if (!data->mem) {
@@ -307,9 +396,8 @@ static int __devinit exynos4_tmu_probe(struct platform_device *pdev)
307 goto err_mem_region; 396 goto err_mem_region;
308 } 397 }
309 398
310 ret = request_irq(data->irq, exynos4_tmu_irq, 399 ret = request_irq(data->irq, exynos_tmu_irq,
311 IRQF_TRIGGER_RISING, 400 IRQF_TRIGGER_RISING, "exynos-tmu", data);
312 "exynos4-tmu", data);
313 if (ret) { 401 if (ret) {
314 dev_err(&pdev->dev, "Failed to request irq: %d\n", data->irq); 402 dev_err(&pdev->dev, "Failed to request irq: %d\n", data->irq);
315 goto err_io_remap; 403 goto err_io_remap;
@@ -322,17 +410,26 @@ static int __devinit exynos4_tmu_probe(struct platform_device *pdev)
322 goto err_irq; 410 goto err_irq;
323 } 411 }
324 412
413 if (pdata->type == SOC_ARCH_EXYNOS ||
414 pdata->type == SOC_ARCH_EXYNOS4210)
415 data->soc = pdata->type;
416 else {
417 ret = -EINVAL;
418 dev_err(&pdev->dev, "Platform not supported\n");
419 goto err_clk;
420 }
421
325 data->pdata = pdata; 422 data->pdata = pdata;
326 platform_set_drvdata(pdev, data); 423 platform_set_drvdata(pdev, data);
327 mutex_init(&data->lock); 424 mutex_init(&data->lock);
328 425
329 ret = exynos4_tmu_initialize(pdev); 426 ret = exynos_tmu_initialize(pdev);
330 if (ret) { 427 if (ret) {
331 dev_err(&pdev->dev, "Failed to initialize TMU\n"); 428 dev_err(&pdev->dev, "Failed to initialize TMU\n");
332 goto err_clk; 429 goto err_clk;
333 } 430 }
334 431
335 exynos4_tmu_control(pdev, true); 432 exynos_tmu_control(pdev, true);
336 433
337 return 0; 434 return 0;
338err_clk: 435err_clk:
@@ -350,11 +447,11 @@ err_free:
350 return ret; 447 return ret;
351} 448}
352 449
353static int __devexit exynos4_tmu_remove(struct platform_device *pdev) 450static int __devexit exynos_tmu_remove(struct platform_device *pdev)
354{ 451{
355 struct exynos4_tmu_data *data = platform_get_drvdata(pdev); 452 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
356 453
357 exynos4_tmu_control(pdev, false); 454 exynos_tmu_control(pdev, false);
358 455
359 clk_put(data->clk); 456 clk_put(data->clk);
360 457
@@ -371,43 +468,43 @@ static int __devexit exynos4_tmu_remove(struct platform_device *pdev)
371} 468}
372 469
373#ifdef CONFIG_PM_SLEEP 470#ifdef CONFIG_PM_SLEEP
374static int exynos4_tmu_suspend(struct device *dev) 471static int exynos_tmu_suspend(struct device *dev)
375{ 472{
376 exynos4_tmu_control(to_platform_device(dev), false); 473 exynos_tmu_control(to_platform_device(dev), false);
377 474
378 return 0; 475 return 0;
379} 476}
380 477
381static int exynos4_tmu_resume(struct device *dev) 478static int exynos_tmu_resume(struct device *dev)
382{ 479{
383 struct platform_device *pdev = to_platform_device(dev); 480 struct platform_device *pdev = to_platform_device(dev);
384 481
385 exynos4_tmu_initialize(pdev); 482 exynos_tmu_initialize(pdev);
386 exynos4_tmu_control(pdev, true); 483 exynos_tmu_control(pdev, true);
387 484
388 return 0; 485 return 0;
389} 486}
390 487
391static SIMPLE_DEV_PM_OPS(exynos4_tmu_pm, 488static SIMPLE_DEV_PM_OPS(exynos_tmu_pm,
392 exynos4_tmu_suspend, exynos4_tmu_resume); 489 exynos_tmu_suspend, exynos_tmu_resume);
393#define EXYNOS4_TMU_PM (&exynos4_tmu_pm) 490#define EXYNOS_TMU_PM (&exynos_tmu_pm)
394#else 491#else
395#define EXYNOS4_TMU_PM NULL 492#define EXYNOS_TMU_PM NULL
396#endif 493#endif
397 494
398static struct platform_driver exynos4_tmu_driver = { 495static struct platform_driver exynos_tmu_driver = {
399 .driver = { 496 .driver = {
400 .name = "exynos4-tmu", 497 .name = "exynos-tmu",
401 .owner = THIS_MODULE, 498 .owner = THIS_MODULE,
402 .pm = EXYNOS4_TMU_PM, 499 .pm = EXYNOS_TMU_PM,
403 }, 500 },
404 .probe = exynos4_tmu_probe, 501 .probe = exynos_tmu_probe,
405 .remove = __devexit_p(exynos4_tmu_remove), 502 .remove = __devexit_p(exynos_tmu_remove),
406}; 503};
407 504
408module_platform_driver(exynos4_tmu_driver); 505module_platform_driver(exynos_tmu_driver);
409 506
410MODULE_DESCRIPTION("EXYNOS4 TMU Driver"); 507MODULE_DESCRIPTION("EXYNOS TMU Driver");
411MODULE_AUTHOR("Donggeun Kim <dg77.kim@samsung.com>"); 508MODULE_AUTHOR("Donggeun Kim <dg77.kim@samsung.com>");
412MODULE_LICENSE("GPL"); 509MODULE_LICENSE("GPL");
413MODULE_ALIAS("platform:exynos4-tmu"); 510MODULE_ALIAS("platform:exynos-tmu");
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-22 17:17:04 -0500