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-rw-r--r--drivers/ssb/Kconfig15
-rw-r--r--drivers/ssb/Makefile2
-rw-r--r--drivers/ssb/driver_chipcommon.c10
-rw-r--r--drivers/ssb/driver_gige.c294
-rw-r--r--drivers/ssb/driver_mipscore.c1
-rw-r--r--drivers/ssb/driver_pcicore.c160
-rw-r--r--drivers/ssb/embedded.c90
-rw-r--r--drivers/ssb/main.c71
-rw-r--r--drivers/ssb/pci.c141
-rw-r--r--drivers/ssb/pcmcia.c550
-rw-r--r--drivers/ssb/sprom.c133
-rw-r--r--drivers/ssb/ssb_private.h19
12 files changed, 1249 insertions, 237 deletions
diff --git a/drivers/ssb/Kconfig b/drivers/ssb/Kconfig
index adea792fb675..0f7cce2560d1 100644
--- a/drivers/ssb/Kconfig
+++ b/drivers/ssb/Kconfig
@@ -20,6 +20,10 @@ config SSB
20 20
21 If unsure, say N. 21 If unsure, say N.
22 22
23# Common SPROM support routines
24config SSB_SPROM
25 bool
26
23config SSB_PCIHOST_POSSIBLE 27config SSB_PCIHOST_POSSIBLE
24 bool 28 bool
25 depends on SSB && (PCI = y || PCI = SSB) 29 depends on SSB && (PCI = y || PCI = SSB)
@@ -28,6 +32,7 @@ config SSB_PCIHOST_POSSIBLE
28config SSB_PCIHOST 32config SSB_PCIHOST
29 bool "Support for SSB on PCI-bus host" 33 bool "Support for SSB on PCI-bus host"
30 depends on SSB_PCIHOST_POSSIBLE 34 depends on SSB_PCIHOST_POSSIBLE
35 select SSB_SPROM
31 default y 36 default y
32 help 37 help
33 Support for a Sonics Silicon Backplane on top 38 Support for a Sonics Silicon Backplane on top
@@ -48,6 +53,7 @@ config SSB_PCMCIAHOST_POSSIBLE
48config SSB_PCMCIAHOST 53config SSB_PCMCIAHOST
49 bool "Support for SSB on PCMCIA-bus host (EXPERIMENTAL)" 54 bool "Support for SSB on PCMCIA-bus host (EXPERIMENTAL)"
50 depends on SSB_PCMCIAHOST_POSSIBLE 55 depends on SSB_PCMCIAHOST_POSSIBLE
56 select SSB_SPROM
51 help 57 help
52 Support for a Sonics Silicon Backplane on top 58 Support for a Sonics Silicon Backplane on top
53 of a PCMCIA device. 59 of a PCMCIA device.
@@ -125,4 +131,13 @@ config SSB_DRIVER_EXTIF
125 131
126 If unsure, say N 132 If unsure, say N
127 133
134config SSB_DRIVER_GIGE
135 bool "SSB Broadcom Gigabit Ethernet driver"
136 depends on SSB_PCIHOST_POSSIBLE && SSB_EMBEDDED && MIPS
137 help
138 Driver for the Sonics Silicon Backplane attached
139 Broadcom Gigabit Ethernet.
140
141 If unsure, say N
142
128endmenu 143endmenu
diff --git a/drivers/ssb/Makefile b/drivers/ssb/Makefile
index de94c2eb7a37..6f255e9c5af9 100644
--- a/drivers/ssb/Makefile
+++ b/drivers/ssb/Makefile
@@ -1,6 +1,7 @@
1# core 1# core
2ssb-y += main.o scan.o 2ssb-y += main.o scan.o
3ssb-$(CONFIG_SSB_EMBEDDED) += embedded.o 3ssb-$(CONFIG_SSB_EMBEDDED) += embedded.o
4ssb-$(CONFIG_SSB_SPROM) += sprom.o
4 5
5# host support 6# host support
6ssb-$(CONFIG_SSB_PCIHOST) += pci.o pcihost_wrapper.o 7ssb-$(CONFIG_SSB_PCIHOST) += pci.o pcihost_wrapper.o
@@ -11,6 +12,7 @@ ssb-y += driver_chipcommon.o
11ssb-$(CONFIG_SSB_DRIVER_MIPS) += driver_mipscore.o 12ssb-$(CONFIG_SSB_DRIVER_MIPS) += driver_mipscore.o
12ssb-$(CONFIG_SSB_DRIVER_EXTIF) += driver_extif.o 13ssb-$(CONFIG_SSB_DRIVER_EXTIF) += driver_extif.o
13ssb-$(CONFIG_SSB_DRIVER_PCICORE) += driver_pcicore.o 14ssb-$(CONFIG_SSB_DRIVER_PCICORE) += driver_pcicore.o
15ssb-$(CONFIG_SSB_DRIVER_GIGE) += driver_gige.o
14 16
15# b43 pci-ssb-bridge driver 17# b43 pci-ssb-bridge driver
16# Not strictly a part of SSB, but kept here for convenience 18# Not strictly a part of SSB, but kept here for convenience
diff --git a/drivers/ssb/driver_chipcommon.c b/drivers/ssb/driver_chipcommon.c
index e586321a473a..45b672a69003 100644
--- a/drivers/ssb/driver_chipcommon.c
+++ b/drivers/ssb/driver_chipcommon.c
@@ -353,6 +353,16 @@ void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
353 chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks); 353 chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
354} 354}
355 355
356void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value)
357{
358 chipco_write32_masked(cc, SSB_CHIPCO_IRQMASK, mask, value);
359}
360
361u32 ssb_chipco_irq_status(struct ssb_chipcommon *cc, u32 mask)
362{
363 return chipco_read32(cc, SSB_CHIPCO_IRQSTAT) & mask;
364}
365
356u32 ssb_chipco_gpio_in(struct ssb_chipcommon *cc, u32 mask) 366u32 ssb_chipco_gpio_in(struct ssb_chipcommon *cc, u32 mask)
357{ 367{
358 return chipco_read32(cc, SSB_CHIPCO_GPIOIN) & mask; 368 return chipco_read32(cc, SSB_CHIPCO_GPIOIN) & mask;
diff --git a/drivers/ssb/driver_gige.c b/drivers/ssb/driver_gige.c
new file mode 100644
index 000000000000..172f90407b93
--- /dev/null
+++ b/drivers/ssb/driver_gige.c
@@ -0,0 +1,294 @@
1/*
2 * Sonics Silicon Backplane
3 * Broadcom Gigabit Ethernet core driver
4 *
5 * Copyright 2008, Broadcom Corporation
6 * Copyright 2008, Michael Buesch <mb@bu3sch.de>
7 *
8 * Licensed under the GNU/GPL. See COPYING for details.
9 */
10
11#include <linux/ssb/ssb.h>
12#include <linux/ssb/ssb_driver_gige.h>
13#include <linux/pci.h>
14#include <linux/pci_regs.h>
15
16
17/*
18MODULE_DESCRIPTION("SSB Broadcom Gigabit Ethernet driver");
19MODULE_AUTHOR("Michael Buesch");
20MODULE_LICENSE("GPL");
21*/
22
23static const struct ssb_device_id ssb_gige_tbl[] = {
24 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_ETHERNET_GBIT, SSB_ANY_REV),
25 SSB_DEVTABLE_END
26};
27/* MODULE_DEVICE_TABLE(ssb, ssb_gige_tbl); */
28
29
30static inline u8 gige_read8(struct ssb_gige *dev, u16 offset)
31{
32 return ssb_read8(dev->dev, offset);
33}
34
35static inline u16 gige_read16(struct ssb_gige *dev, u16 offset)
36{
37 return ssb_read16(dev->dev, offset);
38}
39
40static inline u32 gige_read32(struct ssb_gige *dev, u16 offset)
41{
42 return ssb_read32(dev->dev, offset);
43}
44
45static inline void gige_write8(struct ssb_gige *dev,
46 u16 offset, u8 value)
47{
48 ssb_write8(dev->dev, offset, value);
49}
50
51static inline void gige_write16(struct ssb_gige *dev,
52 u16 offset, u16 value)
53{
54 ssb_write16(dev->dev, offset, value);
55}
56
57static inline void gige_write32(struct ssb_gige *dev,
58 u16 offset, u32 value)
59{
60 ssb_write32(dev->dev, offset, value);
61}
62
63static inline
64u8 gige_pcicfg_read8(struct ssb_gige *dev, unsigned int offset)
65{
66 BUG_ON(offset >= 256);
67 return gige_read8(dev, SSB_GIGE_PCICFG + offset);
68}
69
70static inline
71u16 gige_pcicfg_read16(struct ssb_gige *dev, unsigned int offset)
72{
73 BUG_ON(offset >= 256);
74 return gige_read16(dev, SSB_GIGE_PCICFG + offset);
75}
76
77static inline
78u32 gige_pcicfg_read32(struct ssb_gige *dev, unsigned int offset)
79{
80 BUG_ON(offset >= 256);
81 return gige_read32(dev, SSB_GIGE_PCICFG + offset);
82}
83
84static inline
85void gige_pcicfg_write8(struct ssb_gige *dev,
86 unsigned int offset, u8 value)
87{
88 BUG_ON(offset >= 256);
89 gige_write8(dev, SSB_GIGE_PCICFG + offset, value);
90}
91
92static inline
93void gige_pcicfg_write16(struct ssb_gige *dev,
94 unsigned int offset, u16 value)
95{
96 BUG_ON(offset >= 256);
97 gige_write16(dev, SSB_GIGE_PCICFG + offset, value);
98}
99
100static inline
101void gige_pcicfg_write32(struct ssb_gige *dev,
102 unsigned int offset, u32 value)
103{
104 BUG_ON(offset >= 256);
105 gige_write32(dev, SSB_GIGE_PCICFG + offset, value);
106}
107
108static int ssb_gige_pci_read_config(struct pci_bus *bus, unsigned int devfn,
109 int reg, int size, u32 *val)
110{
111 struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
112 unsigned long flags;
113
114 if ((PCI_SLOT(devfn) > 0) || (PCI_FUNC(devfn) > 0))
115 return PCIBIOS_DEVICE_NOT_FOUND;
116 if (reg >= 256)
117 return PCIBIOS_DEVICE_NOT_FOUND;
118
119 spin_lock_irqsave(&dev->lock, flags);
120 switch (size) {
121 case 1:
122 *val = gige_pcicfg_read8(dev, reg);
123 break;
124 case 2:
125 *val = gige_pcicfg_read16(dev, reg);
126 break;
127 case 4:
128 *val = gige_pcicfg_read32(dev, reg);
129 break;
130 default:
131 WARN_ON(1);
132 }
133 spin_unlock_irqrestore(&dev->lock, flags);
134
135 return PCIBIOS_SUCCESSFUL;
136}
137
138static int ssb_gige_pci_write_config(struct pci_bus *bus, unsigned int devfn,
139 int reg, int size, u32 val)
140{
141 struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
142 unsigned long flags;
143
144 if ((PCI_SLOT(devfn) > 0) || (PCI_FUNC(devfn) > 0))
145 return PCIBIOS_DEVICE_NOT_FOUND;
146 if (reg >= 256)
147 return PCIBIOS_DEVICE_NOT_FOUND;
148
149 spin_lock_irqsave(&dev->lock, flags);
150 switch (size) {
151 case 1:
152 gige_pcicfg_write8(dev, reg, val);
153 break;
154 case 2:
155 gige_pcicfg_write16(dev, reg, val);
156 break;
157 case 4:
158 gige_pcicfg_write32(dev, reg, val);
159 break;
160 default:
161 WARN_ON(1);
162 }
163 spin_unlock_irqrestore(&dev->lock, flags);
164
165 return PCIBIOS_SUCCESSFUL;
166}
167
168static int ssb_gige_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
169{
170 struct ssb_gige *dev;
171 u32 base, tmslow, tmshigh;
172
173 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
174 if (!dev)
175 return -ENOMEM;
176 dev->dev = sdev;
177
178 spin_lock_init(&dev->lock);
179 dev->pci_controller.pci_ops = &dev->pci_ops;
180 dev->pci_controller.io_resource = &dev->io_resource;
181 dev->pci_controller.mem_resource = &dev->mem_resource;
182 dev->pci_controller.io_map_base = 0x800;
183 dev->pci_ops.read = ssb_gige_pci_read_config;
184 dev->pci_ops.write = ssb_gige_pci_write_config;
185
186 dev->io_resource.name = SSB_GIGE_IO_RES_NAME;
187 dev->io_resource.start = 0x800;
188 dev->io_resource.end = 0x8FF;
189 dev->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED;
190
191 if (!ssb_device_is_enabled(sdev))
192 ssb_device_enable(sdev, 0);
193
194 /* Setup BAR0. This is a 64k MMIO region. */
195 base = ssb_admatch_base(ssb_read32(sdev, SSB_ADMATCH1));
196 gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_0, base);
197 gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_1, 0);
198
199 dev->mem_resource.name = SSB_GIGE_MEM_RES_NAME;
200 dev->mem_resource.start = base;
201 dev->mem_resource.end = base + 0x10000 - 1;
202 dev->mem_resource.flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
203
204 /* Enable the memory region. */
205 gige_pcicfg_write16(dev, PCI_COMMAND,
206 gige_pcicfg_read16(dev, PCI_COMMAND)
207 | PCI_COMMAND_MEMORY);
208
209 /* Write flushing is controlled by the Flush Status Control register.
210 * We want to flush every register write with a timeout and we want
211 * to disable the IRQ mask while flushing to avoid concurrency.
212 * Note that automatic write flushing does _not_ work from
213 * an IRQ handler. The driver must flush manually by reading a register.
214 */
215 gige_write32(dev, SSB_GIGE_SHIM_FLUSHSTAT, 0x00000068);
216
217 /* Check if we have an RGMII or GMII PHY-bus.
218 * On RGMII do not bypass the DLLs */
219 tmslow = ssb_read32(sdev, SSB_TMSLOW);
220 tmshigh = ssb_read32(sdev, SSB_TMSHIGH);
221 if (tmshigh & SSB_GIGE_TMSHIGH_RGMII) {
222 tmslow &= ~SSB_GIGE_TMSLOW_TXBYPASS;
223 tmslow &= ~SSB_GIGE_TMSLOW_RXBYPASS;
224 dev->has_rgmii = 1;
225 } else {
226 tmslow |= SSB_GIGE_TMSLOW_TXBYPASS;
227 tmslow |= SSB_GIGE_TMSLOW_RXBYPASS;
228 dev->has_rgmii = 0;
229 }
230 tmslow |= SSB_GIGE_TMSLOW_DLLEN;
231 ssb_write32(sdev, SSB_TMSLOW, tmslow);
232
233 ssb_set_drvdata(sdev, dev);
234 register_pci_controller(&dev->pci_controller);
235
236 return 0;
237}
238
239bool pdev_is_ssb_gige_core(struct pci_dev *pdev)
240{
241 if (!pdev->resource[0].name)
242 return 0;
243 return (strcmp(pdev->resource[0].name, SSB_GIGE_MEM_RES_NAME) == 0);
244}
245EXPORT_SYMBOL(pdev_is_ssb_gige_core);
246
247int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
248 struct pci_dev *pdev)
249{
250 struct ssb_gige *dev = ssb_get_drvdata(sdev);
251 struct resource *res;
252
253 if (pdev->bus->ops != &dev->pci_ops) {
254 /* The PCI device is not on this SSB GigE bridge device. */
255 return -ENODEV;
256 }
257
258 /* Fixup the PCI resources. */
259 res = &(pdev->resource[0]);
260 res->flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
261 res->name = dev->mem_resource.name;
262 res->start = dev->mem_resource.start;
263 res->end = dev->mem_resource.end;
264
265 /* Fixup interrupt lines. */
266 pdev->irq = ssb_mips_irq(sdev) + 2;
267 pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, pdev->irq);
268
269 return 0;
270}
271
272int ssb_gige_map_irq(struct ssb_device *sdev,
273 const struct pci_dev *pdev)
274{
275 struct ssb_gige *dev = ssb_get_drvdata(sdev);
276
277 if (pdev->bus->ops != &dev->pci_ops) {
278 /* The PCI device is not on this SSB GigE bridge device. */
279 return -ENODEV;
280 }
281
282 return ssb_mips_irq(sdev) + 2;
283}
284
285static struct ssb_driver ssb_gige_driver = {
286 .name = "BCM-GigE",
287 .id_table = ssb_gige_tbl,
288 .probe = ssb_gige_probe,
289};
290
291int ssb_gige_init(void)
292{
293 return ssb_driver_register(&ssb_gige_driver);
294}
diff --git a/drivers/ssb/driver_mipscore.c b/drivers/ssb/driver_mipscore.c
index 3d3dd32bf3ab..e3fad3123ecb 100644
--- a/drivers/ssb/driver_mipscore.c
+++ b/drivers/ssb/driver_mipscore.c
@@ -209,6 +209,7 @@ void ssb_mipscore_init(struct ssb_mipscore *mcore)
209 /* fallthrough */ 209 /* fallthrough */
210 case SSB_DEV_PCI: 210 case SSB_DEV_PCI:
211 case SSB_DEV_ETHERNET: 211 case SSB_DEV_ETHERNET:
212 case SSB_DEV_ETHERNET_GBIT:
212 case SSB_DEV_80211: 213 case SSB_DEV_80211:
213 case SSB_DEV_USB20_HOST: 214 case SSB_DEV_USB20_HOST:
214 /* These devices get their own IRQ line if available, the rest goes on IRQ0 */ 215 /* These devices get their own IRQ line if available, the rest goes on IRQ0 */
diff --git a/drivers/ssb/driver_pcicore.c b/drivers/ssb/driver_pcicore.c
index 74b9a8aea52b..33a7d5620474 100644
--- a/drivers/ssb/driver_pcicore.c
+++ b/drivers/ssb/driver_pcicore.c
@@ -60,77 +60,6 @@ static DEFINE_SPINLOCK(cfgspace_lock);
60/* Core to access the external PCI config space. Can only have one. */ 60/* Core to access the external PCI config space. Can only have one. */
61static struct ssb_pcicore *extpci_core; 61static struct ssb_pcicore *extpci_core;
62 62
63static u32 ssb_pcicore_pcibus_iobase = 0x100;
64static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA;
65
66int pcibios_plat_dev_init(struct pci_dev *d)
67{
68 struct resource *res;
69 int pos, size;
70 u32 *base;
71
72 ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
73 pci_name(d));
74
75 /* Fix up resource bases */
76 for (pos = 0; pos < 6; pos++) {
77 res = &d->resource[pos];
78 if (res->flags & IORESOURCE_IO)
79 base = &ssb_pcicore_pcibus_iobase;
80 else
81 base = &ssb_pcicore_pcibus_membase;
82 res->flags |= IORESOURCE_PCI_FIXED;
83 if (res->end) {
84 size = res->end - res->start + 1;
85 if (*base & (size - 1))
86 *base = (*base + size) & ~(size - 1);
87 res->start = *base;
88 res->end = res->start + size - 1;
89 *base += size;
90 pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
91 }
92 /* Fix up PCI bridge BAR0 only */
93 if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
94 break;
95 }
96 /* Fix up interrupt lines */
97 d->irq = ssb_mips_irq(extpci_core->dev) + 2;
98 pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
99
100 return 0;
101}
102
103static void __init ssb_fixup_pcibridge(struct pci_dev *dev)
104{
105 u8 lat;
106
107 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
108 return;
109
110 ssb_printk(KERN_INFO "PCI: Fixing up bridge %s\n", pci_name(dev));
111
112 /* Enable PCI bridge bus mastering and memory space */
113 pci_set_master(dev);
114 if (pcibios_enable_device(dev, ~0) < 0) {
115 ssb_printk(KERN_ERR "PCI: SSB bridge enable failed\n");
116 return;
117 }
118
119 /* Enable PCI bridge BAR1 prefetch and burst */
120 pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
121
122 /* Make sure our latency is high enough to handle the devices behind us */
123 lat = 168;
124 ssb_printk(KERN_INFO "PCI: Fixing latency timer of device %s to %u\n",
125 pci_name(dev), lat);
126 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
127}
128DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_fixup_pcibridge);
129
130int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
131{
132 return ssb_mips_irq(extpci_core->dev) + 2;
133}
134 63
135static u32 get_cfgspace_addr(struct ssb_pcicore *pc, 64static u32 get_cfgspace_addr(struct ssb_pcicore *pc,
136 unsigned int bus, unsigned int dev, 65 unsigned int bus, unsigned int dev,
@@ -320,6 +249,95 @@ static struct pci_controller ssb_pcicore_controller = {
320 .mem_offset = 0x24000000, 249 .mem_offset = 0x24000000,
321}; 250};
322 251
252static u32 ssb_pcicore_pcibus_iobase = 0x100;
253static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA;
254
255/* This function is called when doing a pci_enable_device().
256 * We must first check if the device is a device on the PCI-core bridge. */
257int ssb_pcicore_plat_dev_init(struct pci_dev *d)
258{
259 struct resource *res;
260 int pos, size;
261 u32 *base;
262
263 if (d->bus->ops != &ssb_pcicore_pciops) {
264 /* This is not a device on the PCI-core bridge. */
265 return -ENODEV;
266 }
267
268 ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
269 pci_name(d));
270
271 /* Fix up resource bases */
272 for (pos = 0; pos < 6; pos++) {
273 res = &d->resource[pos];
274 if (res->flags & IORESOURCE_IO)
275 base = &ssb_pcicore_pcibus_iobase;
276 else
277 base = &ssb_pcicore_pcibus_membase;
278 res->flags |= IORESOURCE_PCI_FIXED;
279 if (res->end) {
280 size = res->end - res->start + 1;
281 if (*base & (size - 1))
282 *base = (*base + size) & ~(size - 1);
283 res->start = *base;
284 res->end = res->start + size - 1;
285 *base += size;
286 pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
287 }
288 /* Fix up PCI bridge BAR0 only */
289 if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
290 break;
291 }
292 /* Fix up interrupt lines */
293 d->irq = ssb_mips_irq(extpci_core->dev) + 2;
294 pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
295
296 return 0;
297}
298
299/* Early PCI fixup for a device on the PCI-core bridge. */
300static void ssb_pcicore_fixup_pcibridge(struct pci_dev *dev)
301{
302 u8 lat;
303
304 if (dev->bus->ops != &ssb_pcicore_pciops) {
305 /* This is not a device on the PCI-core bridge. */
306 return;
307 }
308 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
309 return;
310
311 ssb_printk(KERN_INFO "PCI: Fixing up bridge %s\n", pci_name(dev));
312
313 /* Enable PCI bridge bus mastering and memory space */
314 pci_set_master(dev);
315 if (pcibios_enable_device(dev, ~0) < 0) {
316 ssb_printk(KERN_ERR "PCI: SSB bridge enable failed\n");
317 return;
318 }
319
320 /* Enable PCI bridge BAR1 prefetch and burst */
321 pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
322
323 /* Make sure our latency is high enough to handle the devices behind us */
324 lat = 168;
325 ssb_printk(KERN_INFO "PCI: Fixing latency timer of device %s to %u\n",
326 pci_name(dev), lat);
327 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
328}
329DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_pcicore_fixup_pcibridge);
330
331/* PCI device IRQ mapping. */
332int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
333{
334 if (dev->bus->ops != &ssb_pcicore_pciops) {
335 /* This is not a device on the PCI-core bridge. */
336 return -ENODEV;
337 }
338 return ssb_mips_irq(extpci_core->dev) + 2;
339}
340
323static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc) 341static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
324{ 342{
325 u32 val; 343 u32 val;
diff --git a/drivers/ssb/embedded.c b/drivers/ssb/embedded.c
index d3ade821555c..7dc3a6b41397 100644
--- a/drivers/ssb/embedded.c
+++ b/drivers/ssb/embedded.c
@@ -10,6 +10,9 @@
10 10
11#include <linux/ssb/ssb.h> 11#include <linux/ssb/ssb.h>
12#include <linux/ssb/ssb_embedded.h> 12#include <linux/ssb/ssb_embedded.h>
13#include <linux/ssb/ssb_driver_pci.h>
14#include <linux/ssb/ssb_driver_gige.h>
15#include <linux/pci.h>
13 16
14#include "ssb_private.h" 17#include "ssb_private.h"
15 18
@@ -130,3 +133,90 @@ u32 ssb_gpio_polarity(struct ssb_bus *bus, u32 mask, u32 value)
130 return res; 133 return res;
131} 134}
132EXPORT_SYMBOL(ssb_gpio_polarity); 135EXPORT_SYMBOL(ssb_gpio_polarity);
136
137#ifdef CONFIG_SSB_DRIVER_GIGE
138static int gige_pci_init_callback(struct ssb_bus *bus, unsigned long data)
139{
140 struct pci_dev *pdev = (struct pci_dev *)data;
141 struct ssb_device *dev;
142 unsigned int i;
143 int res;
144
145 for (i = 0; i < bus->nr_devices; i++) {
146 dev = &(bus->devices[i]);
147 if (dev->id.coreid != SSB_DEV_ETHERNET_GBIT)
148 continue;
149 if (!dev->dev ||
150 !dev->dev->driver ||
151 !device_is_registered(dev->dev))
152 continue;
153 res = ssb_gige_pcibios_plat_dev_init(dev, pdev);
154 if (res >= 0)
155 return res;
156 }
157
158 return -ENODEV;
159}
160#endif /* CONFIG_SSB_DRIVER_GIGE */
161
162int ssb_pcibios_plat_dev_init(struct pci_dev *dev)
163{
164 int err;
165
166 err = ssb_pcicore_plat_dev_init(dev);
167 if (!err)
168 return 0;
169#ifdef CONFIG_SSB_DRIVER_GIGE
170 err = ssb_for_each_bus_call((unsigned long)dev, gige_pci_init_callback);
171 if (err >= 0)
172 return err;
173#endif
174 /* This is not a PCI device on any SSB device. */
175
176 return -ENODEV;
177}
178
179#ifdef CONFIG_SSB_DRIVER_GIGE
180static int gige_map_irq_callback(struct ssb_bus *bus, unsigned long data)
181{
182 const struct pci_dev *pdev = (const struct pci_dev *)data;
183 struct ssb_device *dev;
184 unsigned int i;
185 int res;
186
187 for (i = 0; i < bus->nr_devices; i++) {
188 dev = &(bus->devices[i]);
189 if (dev->id.coreid != SSB_DEV_ETHERNET_GBIT)
190 continue;
191 if (!dev->dev ||
192 !dev->dev->driver ||
193 !device_is_registered(dev->dev))
194 continue;
195 res = ssb_gige_map_irq(dev, pdev);
196 if (res >= 0)
197 return res;
198 }
199
200 return -ENODEV;
201}
202#endif /* CONFIG_SSB_DRIVER_GIGE */
203
204int ssb_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
205{
206 int res;
207
208 /* Check if this PCI device is a device on a SSB bus or device
209 * and return the IRQ number for it. */
210
211 res = ssb_pcicore_pcibios_map_irq(dev, slot, pin);
212 if (res >= 0)
213 return res;
214#ifdef CONFIG_SSB_DRIVER_GIGE
215 res = ssb_for_each_bus_call((unsigned long)dev, gige_map_irq_callback);
216 if (res >= 0)
217 return res;
218#endif
219 /* This is not a PCI device on any SSB device. */
220
221 return -ENODEV;
222}
diff --git a/drivers/ssb/main.c b/drivers/ssb/main.c
index bedb2b4ee9d2..e12371916444 100644
--- a/drivers/ssb/main.c
+++ b/drivers/ssb/main.c
@@ -14,6 +14,7 @@
14#include <linux/io.h> 14#include <linux/io.h>
15#include <linux/ssb/ssb.h> 15#include <linux/ssb/ssb.h>
16#include <linux/ssb/ssb_regs.h> 16#include <linux/ssb/ssb_regs.h>
17#include <linux/ssb/ssb_driver_gige.h>
17#include <linux/dma-mapping.h> 18#include <linux/dma-mapping.h>
18#include <linux/pci.h> 19#include <linux/pci.h>
19 20
@@ -68,6 +69,44 @@ found:
68} 69}
69#endif /* CONFIG_SSB_PCIHOST */ 70#endif /* CONFIG_SSB_PCIHOST */
70 71
72#ifdef CONFIG_SSB_PCMCIAHOST
73struct ssb_bus *ssb_pcmcia_dev_to_bus(struct pcmcia_device *pdev)
74{
75 struct ssb_bus *bus;
76
77 ssb_buses_lock();
78 list_for_each_entry(bus, &buses, list) {
79 if (bus->bustype == SSB_BUSTYPE_PCMCIA &&
80 bus->host_pcmcia == pdev)
81 goto found;
82 }
83 bus = NULL;
84found:
85 ssb_buses_unlock();
86
87 return bus;
88}
89#endif /* CONFIG_SSB_PCMCIAHOST */
90
91int ssb_for_each_bus_call(unsigned long data,
92 int (*func)(struct ssb_bus *bus, unsigned long data))
93{
94 struct ssb_bus *bus;
95 int res;
96
97 ssb_buses_lock();
98 list_for_each_entry(bus, &buses, list) {
99 res = func(bus, data);
100 if (res >= 0) {
101 ssb_buses_unlock();
102 return res;
103 }
104 }
105 ssb_buses_unlock();
106
107 return -ENODEV;
108}
109
71static struct ssb_device *ssb_device_get(struct ssb_device *dev) 110static struct ssb_device *ssb_device_get(struct ssb_device *dev)
72{ 111{
73 if (dev) 112 if (dev)
@@ -378,7 +417,7 @@ void ssb_bus_unregister(struct ssb_bus *bus)
378 list_del(&bus->list); 417 list_del(&bus->list);
379 ssb_buses_unlock(); 418 ssb_buses_unlock();
380 419
381 /* ssb_pcmcia_exit(bus); */ 420 ssb_pcmcia_exit(bus);
382 ssb_pci_exit(bus); 421 ssb_pci_exit(bus);
383 ssb_iounmap(bus); 422 ssb_iounmap(bus);
384} 423}
@@ -505,6 +544,14 @@ error:
505 return err; 544 return err;
506} 545}
507 546
547static u8 ssb_ssb_read8(struct ssb_device *dev, u16 offset)
548{
549 struct ssb_bus *bus = dev->bus;
550
551 offset += dev->core_index * SSB_CORE_SIZE;
552 return readb(bus->mmio + offset);
553}
554
508static u16 ssb_ssb_read16(struct ssb_device *dev, u16 offset) 555static u16 ssb_ssb_read16(struct ssb_device *dev, u16 offset)
509{ 556{
510 struct ssb_bus *bus = dev->bus; 557 struct ssb_bus *bus = dev->bus;
@@ -521,6 +568,14 @@ static u32 ssb_ssb_read32(struct ssb_device *dev, u16 offset)
521 return readl(bus->mmio + offset); 568 return readl(bus->mmio + offset);
522} 569}
523 570
571static void ssb_ssb_write8(struct ssb_device *dev, u16 offset, u8 value)
572{
573 struct ssb_bus *bus = dev->bus;
574
575 offset += dev->core_index * SSB_CORE_SIZE;
576 writeb(value, bus->mmio + offset);
577}
578
524static void ssb_ssb_write16(struct ssb_device *dev, u16 offset, u16 value) 579static void ssb_ssb_write16(struct ssb_device *dev, u16 offset, u16 value)
525{ 580{
526 struct ssb_bus *bus = dev->bus; 581 struct ssb_bus *bus = dev->bus;
@@ -539,8 +594,10 @@ static void ssb_ssb_write32(struct ssb_device *dev, u16 offset, u32 value)
539 594
540/* Ops for the plain SSB bus without a host-device (no PCI or PCMCIA). */ 595/* Ops for the plain SSB bus without a host-device (no PCI or PCMCIA). */
541static const struct ssb_bus_ops ssb_ssb_ops = { 596static const struct ssb_bus_ops ssb_ssb_ops = {
597 .read8 = ssb_ssb_read8,
542 .read16 = ssb_ssb_read16, 598 .read16 = ssb_ssb_read16,
543 .read32 = ssb_ssb_read32, 599 .read32 = ssb_ssb_read32,
600 .write8 = ssb_ssb_write8,
544 .write16 = ssb_ssb_write16, 601 .write16 = ssb_ssb_write16,
545 .write32 = ssb_ssb_write32, 602 .write32 = ssb_ssb_write32,
546}; 603};
@@ -625,7 +682,7 @@ out:
625err_dequeue: 682err_dequeue:
626 list_del(&bus->list); 683 list_del(&bus->list);
627err_pcmcia_exit: 684err_pcmcia_exit:
628/* ssb_pcmcia_exit(bus); */ 685 ssb_pcmcia_exit(bus);
629err_pci_exit: 686err_pci_exit:
630 ssb_pci_exit(bus); 687 ssb_pci_exit(bus);
631err_unmap: 688err_unmap:
@@ -1153,7 +1210,14 @@ static int __init ssb_modinit(void)
1153 err = b43_pci_ssb_bridge_init(); 1210 err = b43_pci_ssb_bridge_init();
1154 if (err) { 1211 if (err) {
1155 ssb_printk(KERN_ERR "Broadcom 43xx PCI-SSB-bridge " 1212 ssb_printk(KERN_ERR "Broadcom 43xx PCI-SSB-bridge "
1156 "initialization failed"); 1213 "initialization failed\n");
1214 /* don't fail SSB init because of this */
1215 err = 0;
1216 }
1217 err = ssb_gige_init();
1218 if (err) {
1219 ssb_printk(KERN_ERR "SSB Broadcom Gigabit Ethernet "
1220 "driver initialization failed\n");
1157 /* don't fail SSB init because of this */ 1221 /* don't fail SSB init because of this */
1158 err = 0; 1222 err = 0;
1159 } 1223 }
@@ -1167,6 +1231,7 @@ fs_initcall(ssb_modinit);
1167 1231
1168static void __exit ssb_modexit(void) 1232static void __exit ssb_modexit(void)
1169{ 1233{
1234 ssb_gige_exit();
1170 b43_pci_ssb_bridge_exit(); 1235 b43_pci_ssb_bridge_exit();
1171 bus_unregister(&ssb_bustype); 1236 bus_unregister(&ssb_bustype);
1172} 1237}
diff --git a/drivers/ssb/pci.c b/drivers/ssb/pci.c
index b434df75047f..f1514b33cfae 100644
--- a/drivers/ssb/pci.c
+++ b/drivers/ssb/pci.c
@@ -227,7 +227,7 @@ static u8 ssb_sprom_crc(const u16 *sprom, u16 size)
227 return crc; 227 return crc;
228} 228}
229 229
230static int sprom_check_crc(const u16 *sprom, u16 size) 230static int sprom_check_crc(const u16 *sprom, size_t size)
231{ 231{
232 u8 crc; 232 u8 crc;
233 u8 expected_crc; 233 u8 expected_crc;
@@ -242,12 +242,14 @@ static int sprom_check_crc(const u16 *sprom, u16 size)
242 return 0; 242 return 0;
243} 243}
244 244
245static void sprom_do_read(struct ssb_bus *bus, u16 *sprom) 245static int sprom_do_read(struct ssb_bus *bus, u16 *sprom)
246{ 246{
247 int i; 247 int i;
248 248
249 for (i = 0; i < bus->sprom_size; i++) 249 for (i = 0; i < bus->sprom_size; i++)
250 sprom[i] = ioread16(bus->mmio + SSB_SPROM_BASE + (i * 2)); 250 sprom[i] = ioread16(bus->mmio + SSB_SPROM_BASE + (i * 2));
251
252 return 0;
251} 253}
252 254
253static int sprom_do_write(struct ssb_bus *bus, const u16 *sprom) 255static int sprom_do_write(struct ssb_bus *bus, const u16 *sprom)
@@ -572,6 +574,19 @@ static inline int ssb_pci_assert_buspower(struct ssb_bus *bus)
572} 574}
573#endif /* DEBUG */ 575#endif /* DEBUG */
574 576
577static u8 ssb_pci_read8(struct ssb_device *dev, u16 offset)
578{
579 struct ssb_bus *bus = dev->bus;
580
581 if (unlikely(ssb_pci_assert_buspower(bus)))
582 return 0xFF;
583 if (unlikely(bus->mapped_device != dev)) {
584 if (unlikely(ssb_pci_switch_core(bus, dev)))
585 return 0xFF;
586 }
587 return ioread8(bus->mmio + offset);
588}
589
575static u16 ssb_pci_read16(struct ssb_device *dev, u16 offset) 590static u16 ssb_pci_read16(struct ssb_device *dev, u16 offset)
576{ 591{
577 struct ssb_bus *bus = dev->bus; 592 struct ssb_bus *bus = dev->bus;
@@ -598,6 +613,19 @@ static u32 ssb_pci_read32(struct ssb_device *dev, u16 offset)
598 return ioread32(bus->mmio + offset); 613 return ioread32(bus->mmio + offset);
599} 614}
600 615
616static void ssb_pci_write8(struct ssb_device *dev, u16 offset, u8 value)
617{
618 struct ssb_bus *bus = dev->bus;
619
620 if (unlikely(ssb_pci_assert_buspower(bus)))
621 return;
622 if (unlikely(bus->mapped_device != dev)) {
623 if (unlikely(ssb_pci_switch_core(bus, dev)))
624 return;
625 }
626 iowrite8(value, bus->mmio + offset);
627}
628
601static void ssb_pci_write16(struct ssb_device *dev, u16 offset, u16 value) 629static void ssb_pci_write16(struct ssb_device *dev, u16 offset, u16 value)
602{ 630{
603 struct ssb_bus *bus = dev->bus; 631 struct ssb_bus *bus = dev->bus;
@@ -626,77 +654,26 @@ static void ssb_pci_write32(struct ssb_device *dev, u16 offset, u32 value)
626 654
627/* Not "static", as it's used in main.c */ 655/* Not "static", as it's used in main.c */
628const struct ssb_bus_ops ssb_pci_ops = { 656const struct ssb_bus_ops ssb_pci_ops = {
657 .read8 = ssb_pci_read8,
629 .read16 = ssb_pci_read16, 658 .read16 = ssb_pci_read16,
630 .read32 = ssb_pci_read32, 659 .read32 = ssb_pci_read32,
660 .write8 = ssb_pci_write8,
631 .write16 = ssb_pci_write16, 661 .write16 = ssb_pci_write16,
632 .write32 = ssb_pci_write32, 662 .write32 = ssb_pci_write32,
633}; 663};
634 664
635static int sprom2hex(const u16 *sprom, char *buf, size_t buf_len, u16 size)
636{
637 int i, pos = 0;
638
639 for (i = 0; i < size; i++)
640 pos += snprintf(buf + pos, buf_len - pos - 1,
641 "%04X", swab16(sprom[i]) & 0xFFFF);
642 pos += snprintf(buf + pos, buf_len - pos - 1, "\n");
643
644 return pos + 1;
645}
646
647static int hex2sprom(u16 *sprom, const char *dump, size_t len, u16 size)
648{
649 char tmp[5] = { 0 };
650 int cnt = 0;
651 unsigned long parsed;
652
653 if (len < size * 2)
654 return -EINVAL;
655
656 while (cnt < size) {
657 memcpy(tmp, dump, 4);
658 dump += 4;
659 parsed = simple_strtoul(tmp, NULL, 16);
660 sprom[cnt++] = swab16((u16)parsed);
661 }
662
663 return 0;
664}
665
666static ssize_t ssb_pci_attr_sprom_show(struct device *pcidev, 665static ssize_t ssb_pci_attr_sprom_show(struct device *pcidev,
667 struct device_attribute *attr, 666 struct device_attribute *attr,
668 char *buf) 667 char *buf)
669{ 668{
670 struct pci_dev *pdev = container_of(pcidev, struct pci_dev, dev); 669 struct pci_dev *pdev = container_of(pcidev, struct pci_dev, dev);
671 struct ssb_bus *bus; 670 struct ssb_bus *bus;
672 u16 *sprom;
673 int err = -ENODEV;
674 ssize_t count = 0;
675 671
676 bus = ssb_pci_dev_to_bus(pdev); 672 bus = ssb_pci_dev_to_bus(pdev);
677 if (!bus) 673 if (!bus)
678 goto out; 674 return -ENODEV;
679 err = -ENOMEM;
680 sprom = kcalloc(bus->sprom_size, sizeof(u16), GFP_KERNEL);
681 if (!sprom)
682 goto out;
683
684 /* Use interruptible locking, as the SPROM write might
685 * be holding the lock for several seconds. So allow userspace
686 * to cancel operation. */
687 err = -ERESTARTSYS;
688 if (mutex_lock_interruptible(&bus->pci_sprom_mutex))
689 goto out_kfree;
690 sprom_do_read(bus, sprom);
691 mutex_unlock(&bus->pci_sprom_mutex);
692
693 count = sprom2hex(sprom, buf, PAGE_SIZE, bus->sprom_size);
694 err = 0;
695 675
696out_kfree: 676 return ssb_attr_sprom_show(bus, buf, sprom_do_read);
697 kfree(sprom);
698out:
699 return err ? err : count;
700} 677}
701 678
702static ssize_t ssb_pci_attr_sprom_store(struct device *pcidev, 679static ssize_t ssb_pci_attr_sprom_store(struct device *pcidev,
@@ -705,55 +682,13 @@ static ssize_t ssb_pci_attr_sprom_store(struct device *pcidev,
705{ 682{
706 struct pci_dev *pdev = container_of(pcidev, struct pci_dev, dev); 683 struct pci_dev *pdev = container_of(pcidev, struct pci_dev, dev);
707 struct ssb_bus *bus; 684 struct ssb_bus *bus;
708 u16 *sprom;
709 int res = 0, err = -ENODEV;
710 685
711 bus = ssb_pci_dev_to_bus(pdev); 686 bus = ssb_pci_dev_to_bus(pdev);
712 if (!bus) 687 if (!bus)
713 goto out; 688 return -ENODEV;
714 err = -ENOMEM;
715 sprom = kcalloc(bus->sprom_size, sizeof(u16), GFP_KERNEL);
716 if (!sprom)
717 goto out;
718 err = hex2sprom(sprom, buf, count, bus->sprom_size);
719 if (err) {
720 err = -EINVAL;
721 goto out_kfree;
722 }
723 err = sprom_check_crc(sprom, bus->sprom_size);
724 if (err) {
725 err = -EINVAL;
726 goto out_kfree;
727 }
728 689
729 /* Use interruptible locking, as the SPROM write might 690 return ssb_attr_sprom_store(bus, buf, count,
730 * be holding the lock for several seconds. So allow userspace 691 sprom_check_crc, sprom_do_write);
731 * to cancel operation. */
732 err = -ERESTARTSYS;
733 if (mutex_lock_interruptible(&bus->pci_sprom_mutex))
734 goto out_kfree;
735 err = ssb_devices_freeze(bus);
736 if (err == -EOPNOTSUPP) {
737 ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze devices. "
738 "No suspend support. Is CONFIG_PM enabled?\n");
739 goto out_unlock;
740 }
741 if (err) {
742 ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze all devices\n");
743 goto out_unlock;
744 }
745 res = sprom_do_write(bus, sprom);
746 err = ssb_devices_thaw(bus);
747 if (err)
748 ssb_printk(KERN_ERR PFX "SPROM write: Could not thaw all devices\n");
749out_unlock:
750 mutex_unlock(&bus->pci_sprom_mutex);
751out_kfree:
752 kfree(sprom);
753out:
754 if (res)
755 return res;
756 return err ? err : count;
757} 692}
758 693
759static DEVICE_ATTR(ssb_sprom, 0600, 694static DEVICE_ATTR(ssb_sprom, 0600,
@@ -780,7 +715,7 @@ int ssb_pci_init(struct ssb_bus *bus)
780 return 0; 715 return 0;
781 716
782 pdev = bus->host_pci; 717 pdev = bus->host_pci;
783 mutex_init(&bus->pci_sprom_mutex); 718 mutex_init(&bus->sprom_mutex);
784 err = device_create_file(&pdev->dev, &dev_attr_ssb_sprom); 719 err = device_create_file(&pdev->dev, &dev_attr_ssb_sprom);
785 if (err) 720 if (err)
786 goto out; 721 goto out;
diff --git a/drivers/ssb/pcmcia.c b/drivers/ssb/pcmcia.c
index 46816cda8b98..cd49f7c65531 100644
--- a/drivers/ssb/pcmcia.c
+++ b/drivers/ssb/pcmcia.c
@@ -3,7 +3,7 @@
3 * PCMCIA-Hostbus related functions 3 * PCMCIA-Hostbus related functions
4 * 4 *
5 * Copyright 2006 Johannes Berg <johannes@sipsolutions.net> 5 * Copyright 2006 Johannes Berg <johannes@sipsolutions.net>
6 * Copyright 2007 Michael Buesch <mb@bu3sch.de> 6 * Copyright 2007-2008 Michael Buesch <mb@bu3sch.de>
7 * 7 *
8 * Licensed under the GNU/GPL. See COPYING for details. 8 * Licensed under the GNU/GPL. See COPYING for details.
9 */ 9 */
@@ -11,6 +11,7 @@
11#include <linux/ssb/ssb.h> 11#include <linux/ssb/ssb.h>
12#include <linux/delay.h> 12#include <linux/delay.h>
13#include <linux/io.h> 13#include <linux/io.h>
14#include <linux/etherdevice.h>
14 15
15#include <pcmcia/cs_types.h> 16#include <pcmcia/cs_types.h>
16#include <pcmcia/cs.h> 17#include <pcmcia/cs.h>
@@ -26,59 +27,132 @@
26#define SSB_VERBOSE_PCMCIACORESWITCH_DEBUG 0 27#define SSB_VERBOSE_PCMCIACORESWITCH_DEBUG 0
27 28
28 29
30/* PCMCIA configuration registers */
31#define SSB_PCMCIA_CORECTL 0x00
32#define SSB_PCMCIA_CORECTL_RESET 0x80 /* Core reset */
33#define SSB_PCMCIA_CORECTL_IRQEN 0x04 /* IRQ enable */
34#define SSB_PCMCIA_CORECTL_FUNCEN 0x01 /* Function enable */
35#define SSB_PCMCIA_CORECTL2 0x80
36#define SSB_PCMCIA_ADDRESS0 0x2E
37#define SSB_PCMCIA_ADDRESS1 0x30
38#define SSB_PCMCIA_ADDRESS2 0x32
39#define SSB_PCMCIA_MEMSEG 0x34
40#define SSB_PCMCIA_SPROMCTL 0x36
41#define SSB_PCMCIA_SPROMCTL_IDLE 0
42#define SSB_PCMCIA_SPROMCTL_WRITE 1
43#define SSB_PCMCIA_SPROMCTL_READ 2
44#define SSB_PCMCIA_SPROMCTL_WRITEEN 4
45#define SSB_PCMCIA_SPROMCTL_WRITEDIS 7
46#define SSB_PCMCIA_SPROMCTL_DONE 8
47#define SSB_PCMCIA_SPROM_DATALO 0x38
48#define SSB_PCMCIA_SPROM_DATAHI 0x3A
49#define SSB_PCMCIA_SPROM_ADDRLO 0x3C
50#define SSB_PCMCIA_SPROM_ADDRHI 0x3E
51
52/* Hardware invariants CIS tuples */
53#define SSB_PCMCIA_CIS 0x80
54#define SSB_PCMCIA_CIS_ID 0x01
55#define SSB_PCMCIA_CIS_BOARDREV 0x02
56#define SSB_PCMCIA_CIS_PA 0x03
57#define SSB_PCMCIA_CIS_PA_PA0B0_LO 0
58#define SSB_PCMCIA_CIS_PA_PA0B0_HI 1
59#define SSB_PCMCIA_CIS_PA_PA0B1_LO 2
60#define SSB_PCMCIA_CIS_PA_PA0B1_HI 3
61#define SSB_PCMCIA_CIS_PA_PA0B2_LO 4
62#define SSB_PCMCIA_CIS_PA_PA0B2_HI 5
63#define SSB_PCMCIA_CIS_PA_ITSSI 6
64#define SSB_PCMCIA_CIS_PA_MAXPOW 7
65#define SSB_PCMCIA_CIS_OEMNAME 0x04
66#define SSB_PCMCIA_CIS_CCODE 0x05
67#define SSB_PCMCIA_CIS_ANTENNA 0x06
68#define SSB_PCMCIA_CIS_ANTGAIN 0x07
69#define SSB_PCMCIA_CIS_BFLAGS 0x08
70#define SSB_PCMCIA_CIS_LEDS 0x09
71
72/* PCMCIA SPROM size. */
73#define SSB_PCMCIA_SPROM_SIZE 256
74#define SSB_PCMCIA_SPROM_SIZE_BYTES (SSB_PCMCIA_SPROM_SIZE * sizeof(u16))
75
76
77/* Write to a PCMCIA configuration register. */
78static int ssb_pcmcia_cfg_write(struct ssb_bus *bus, u8 offset, u8 value)
79{
80 conf_reg_t reg;
81 int res;
82
83 memset(&reg, 0, sizeof(reg));
84 reg.Offset = offset;
85 reg.Action = CS_WRITE;
86 reg.Value = value;
87 res = pcmcia_access_configuration_register(bus->host_pcmcia, &reg);
88 if (unlikely(res != CS_SUCCESS))
89 return -EBUSY;
90
91 return 0;
92}
93
94/* Read from a PCMCIA configuration register. */
95static int ssb_pcmcia_cfg_read(struct ssb_bus *bus, u8 offset, u8 *value)
96{
97 conf_reg_t reg;
98 int res;
99
100 memset(&reg, 0, sizeof(reg));
101 reg.Offset = offset;
102 reg.Action = CS_READ;
103 res = pcmcia_access_configuration_register(bus->host_pcmcia, &reg);
104 if (unlikely(res != CS_SUCCESS))
105 return -EBUSY;
106 *value = reg.Value;
107
108 return 0;
109}
110
29int ssb_pcmcia_switch_coreidx(struct ssb_bus *bus, 111int ssb_pcmcia_switch_coreidx(struct ssb_bus *bus,
30 u8 coreidx) 112 u8 coreidx)
31{ 113{
32 struct pcmcia_device *pdev = bus->host_pcmcia;
33 int err; 114 int err;
34 int attempts = 0; 115 int attempts = 0;
35 u32 cur_core; 116 u32 cur_core;
36 conf_reg_t reg;
37 u32 addr; 117 u32 addr;
38 u32 read_addr; 118 u32 read_addr;
119 u8 val;
39 120
40 addr = (coreidx * SSB_CORE_SIZE) + SSB_ENUM_BASE; 121 addr = (coreidx * SSB_CORE_SIZE) + SSB_ENUM_BASE;
41 while (1) { 122 while (1) {
42 reg.Action = CS_WRITE; 123 err = ssb_pcmcia_cfg_write(bus, SSB_PCMCIA_ADDRESS0,
43 reg.Offset = 0x2E; 124 (addr & 0x0000F000) >> 12);
44 reg.Value = (addr & 0x0000F000) >> 12; 125 if (err)
45 err = pcmcia_access_configuration_register(pdev, &reg);
46 if (err != CS_SUCCESS)
47 goto error; 126 goto error;
48 reg.Offset = 0x30; 127 err = ssb_pcmcia_cfg_write(bus, SSB_PCMCIA_ADDRESS1,
49 reg.Value = (addr & 0x00FF0000) >> 16; 128 (addr & 0x00FF0000) >> 16);
50 err = pcmcia_access_configuration_register(pdev, &reg); 129 if (err)
51 if (err != CS_SUCCESS)
52 goto error; 130 goto error;
53 reg.Offset = 0x32; 131 err = ssb_pcmcia_cfg_write(bus, SSB_PCMCIA_ADDRESS2,
54 reg.Value = (addr & 0xFF000000) >> 24; 132 (addr & 0xFF000000) >> 24);
55 err = pcmcia_access_configuration_register(pdev, &reg); 133 if (err)
56 if (err != CS_SUCCESS)
57 goto error; 134 goto error;
58 135
59 read_addr = 0; 136 read_addr = 0;
60 137
61 reg.Action = CS_READ; 138 err = ssb_pcmcia_cfg_read(bus, SSB_PCMCIA_ADDRESS0, &val);
62 reg.Offset = 0x2E; 139 if (err)
63 err = pcmcia_access_configuration_register(pdev, &reg);
64 if (err != CS_SUCCESS)
65 goto error; 140 goto error;
66 read_addr |= ((u32)(reg.Value & 0x0F)) << 12; 141 read_addr |= ((u32)(val & 0x0F)) << 12;
67 reg.Offset = 0x30; 142 err = ssb_pcmcia_cfg_read(bus, SSB_PCMCIA_ADDRESS1, &val);
68 err = pcmcia_access_configuration_register(pdev, &reg); 143 if (err)
69 if (err != CS_SUCCESS)
70 goto error; 144 goto error;
71 read_addr |= ((u32)reg.Value) << 16; 145 read_addr |= ((u32)val) << 16;
72 reg.Offset = 0x32; 146 err = ssb_pcmcia_cfg_read(bus, SSB_PCMCIA_ADDRESS2, &val);
73 err = pcmcia_access_configuration_register(pdev, &reg); 147 if (err)
74 if (err != CS_SUCCESS)
75 goto error; 148 goto error;
76 read_addr |= ((u32)reg.Value) << 24; 149 read_addr |= ((u32)val) << 24;
77 150
78 cur_core = (read_addr - SSB_ENUM_BASE) / SSB_CORE_SIZE; 151 cur_core = (read_addr - SSB_ENUM_BASE) / SSB_CORE_SIZE;
79 if (cur_core == coreidx) 152 if (cur_core == coreidx)
80 break; 153 break;
81 154
155 err = -ETIMEDOUT;
82 if (attempts++ > SSB_BAR0_MAX_RETRIES) 156 if (attempts++ > SSB_BAR0_MAX_RETRIES)
83 goto error; 157 goto error;
84 udelay(10); 158 udelay(10);
@@ -87,7 +161,7 @@ int ssb_pcmcia_switch_coreidx(struct ssb_bus *bus,
87 return 0; 161 return 0;
88error: 162error:
89 ssb_printk(KERN_ERR PFX "Failed to switch to core %u\n", coreidx); 163 ssb_printk(KERN_ERR PFX "Failed to switch to core %u\n", coreidx);
90 return -ENODEV; 164 return err;
91} 165}
92 166
93int ssb_pcmcia_switch_core(struct ssb_bus *bus, 167int ssb_pcmcia_switch_core(struct ssb_bus *bus,
@@ -112,27 +186,21 @@ int ssb_pcmcia_switch_core(struct ssb_bus *bus,
112int ssb_pcmcia_switch_segment(struct ssb_bus *bus, u8 seg) 186int ssb_pcmcia_switch_segment(struct ssb_bus *bus, u8 seg)
113{ 187{
114 int attempts = 0; 188 int attempts = 0;
115 conf_reg_t reg; 189 int err;
116 int res; 190 u8 val;
117 191
118 SSB_WARN_ON((seg != 0) && (seg != 1)); 192 SSB_WARN_ON((seg != 0) && (seg != 1));
119 reg.Offset = 0x34;
120 reg.Function = 0;
121 while (1) { 193 while (1) {
122 reg.Action = CS_WRITE; 194 err = ssb_pcmcia_cfg_write(bus, SSB_PCMCIA_MEMSEG, seg);
123 reg.Value = seg; 195 if (err)
124 res = pcmcia_access_configuration_register(bus->host_pcmcia, &reg);
125 if (unlikely(res != CS_SUCCESS))
126 goto error; 196 goto error;
127 reg.Value = 0xFF; 197 err = ssb_pcmcia_cfg_read(bus, SSB_PCMCIA_MEMSEG, &val);
128 reg.Action = CS_READ; 198 if (err)
129 res = pcmcia_access_configuration_register(bus->host_pcmcia, &reg);
130 if (unlikely(res != CS_SUCCESS))
131 goto error; 199 goto error;
132 200 if (val == seg)
133 if (reg.Value == seg)
134 break; 201 break;
135 202
203 err = -ETIMEDOUT;
136 if (unlikely(attempts++ > SSB_BAR0_MAX_RETRIES)) 204 if (unlikely(attempts++ > SSB_BAR0_MAX_RETRIES))
137 goto error; 205 goto error;
138 udelay(10); 206 udelay(10);
@@ -142,7 +210,7 @@ int ssb_pcmcia_switch_segment(struct ssb_bus *bus, u8 seg)
142 return 0; 210 return 0;
143error: 211error:
144 ssb_printk(KERN_ERR PFX "Failed to switch pcmcia segment\n"); 212 ssb_printk(KERN_ERR PFX "Failed to switch pcmcia segment\n");
145 return -ENODEV; 213 return err;
146} 214}
147 215
148static int select_core_and_segment(struct ssb_device *dev, 216static int select_core_and_segment(struct ssb_device *dev,
@@ -172,6 +240,22 @@ static int select_core_and_segment(struct ssb_device *dev,
172 return 0; 240 return 0;
173} 241}
174 242
243static u8 ssb_pcmcia_read8(struct ssb_device *dev, u16 offset)
244{
245 struct ssb_bus *bus = dev->bus;
246 unsigned long flags;
247 int err;
248 u8 value = 0xFF;
249
250 spin_lock_irqsave(&bus->bar_lock, flags);
251 err = select_core_and_segment(dev, &offset);
252 if (likely(!err))
253 value = readb(bus->mmio + offset);
254 spin_unlock_irqrestore(&bus->bar_lock, flags);
255
256 return value;
257}
258
175static u16 ssb_pcmcia_read16(struct ssb_device *dev, u16 offset) 259static u16 ssb_pcmcia_read16(struct ssb_device *dev, u16 offset)
176{ 260{
177 struct ssb_bus *bus = dev->bus; 261 struct ssb_bus *bus = dev->bus;
@@ -206,6 +290,20 @@ static u32 ssb_pcmcia_read32(struct ssb_device *dev, u16 offset)
206 return (lo | (hi << 16)); 290 return (lo | (hi << 16));
207} 291}
208 292
293static void ssb_pcmcia_write8(struct ssb_device *dev, u16 offset, u8 value)
294{
295 struct ssb_bus *bus = dev->bus;
296 unsigned long flags;
297 int err;
298
299 spin_lock_irqsave(&bus->bar_lock, flags);
300 err = select_core_and_segment(dev, &offset);
301 if (likely(!err))
302 writeb(value, bus->mmio + offset);
303 mmiowb();
304 spin_unlock_irqrestore(&bus->bar_lock, flags);
305}
306
209static void ssb_pcmcia_write16(struct ssb_device *dev, u16 offset, u16 value) 307static void ssb_pcmcia_write16(struct ssb_device *dev, u16 offset, u16 value)
210{ 308{
211 struct ssb_bus *bus = dev->bus; 309 struct ssb_bus *bus = dev->bus;
@@ -238,24 +336,352 @@ static void ssb_pcmcia_write32(struct ssb_device *dev, u16 offset, u32 value)
238 336
239/* Not "static", as it's used in main.c */ 337/* Not "static", as it's used in main.c */
240const struct ssb_bus_ops ssb_pcmcia_ops = { 338const struct ssb_bus_ops ssb_pcmcia_ops = {
339 .read8 = ssb_pcmcia_read8,
241 .read16 = ssb_pcmcia_read16, 340 .read16 = ssb_pcmcia_read16,
242 .read32 = ssb_pcmcia_read32, 341 .read32 = ssb_pcmcia_read32,
342 .write8 = ssb_pcmcia_write8,
243 .write16 = ssb_pcmcia_write16, 343 .write16 = ssb_pcmcia_write16,
244 .write32 = ssb_pcmcia_write32, 344 .write32 = ssb_pcmcia_write32,
245}; 345};
246 346
247#include <linux/etherdevice.h> 347static int ssb_pcmcia_sprom_command(struct ssb_bus *bus, u8 command)
348{
349 unsigned int i;
350 int err;
351 u8 value;
352
353 err = ssb_pcmcia_cfg_write(bus, SSB_PCMCIA_SPROMCTL, command);
354 if (err)
355 return err;
356 for (i = 0; i < 1000; i++) {
357 err = ssb_pcmcia_cfg_read(bus, SSB_PCMCIA_SPROMCTL, &value);
358 if (err)
359 return err;
360 if (value & SSB_PCMCIA_SPROMCTL_DONE)
361 return 0;
362 udelay(10);
363 }
364
365 return -ETIMEDOUT;
366}
367
368/* offset is the 16bit word offset */
369static int ssb_pcmcia_sprom_read(struct ssb_bus *bus, u16 offset, u16 *value)
370{
371 int err;
372 u8 lo, hi;
373
374 offset *= 2; /* Make byte offset */
375
376 err = ssb_pcmcia_cfg_write(bus, SSB_PCMCIA_SPROM_ADDRLO,
377 (offset & 0x00FF));
378 if (err)
379 return err;
380 err = ssb_pcmcia_cfg_write(bus, SSB_PCMCIA_SPROM_ADDRHI,
381 (offset & 0xFF00) >> 8);
382 if (err)
383 return err;
384 err = ssb_pcmcia_sprom_command(bus, SSB_PCMCIA_SPROMCTL_READ);
385 if (err)
386 return err;
387 err = ssb_pcmcia_cfg_read(bus, SSB_PCMCIA_SPROM_DATALO, &lo);
388 if (err)
389 return err;
390 err = ssb_pcmcia_cfg_read(bus, SSB_PCMCIA_SPROM_DATAHI, &hi);
391 if (err)
392 return err;
393 *value = (lo | (((u16)hi) << 8));
394
395 return 0;
396}
397
398/* offset is the 16bit word offset */
399static int ssb_pcmcia_sprom_write(struct ssb_bus *bus, u16 offset, u16 value)
400{
401 int err;
402
403 offset *= 2; /* Make byte offset */
404
405 err = ssb_pcmcia_cfg_write(bus, SSB_PCMCIA_SPROM_ADDRLO,
406 (offset & 0x00FF));
407 if (err)
408 return err;
409 err = ssb_pcmcia_cfg_write(bus, SSB_PCMCIA_SPROM_ADDRHI,
410 (offset & 0xFF00) >> 8);
411 if (err)
412 return err;
413 err = ssb_pcmcia_cfg_write(bus, SSB_PCMCIA_SPROM_DATALO,
414 (value & 0x00FF));
415 if (err)
416 return err;
417 err = ssb_pcmcia_cfg_write(bus, SSB_PCMCIA_SPROM_DATAHI,
418 (value & 0xFF00) >> 8);
419 if (err)
420 return err;
421 err = ssb_pcmcia_sprom_command(bus, SSB_PCMCIA_SPROMCTL_WRITE);
422 if (err)
423 return err;
424 msleep(20);
425
426 return 0;
427}
428
429/* Read the SPROM image. bufsize is in 16bit words. */
430static int ssb_pcmcia_sprom_read_all(struct ssb_bus *bus, u16 *sprom)
431{
432 int err, i;
433
434 for (i = 0; i < SSB_PCMCIA_SPROM_SIZE; i++) {
435 err = ssb_pcmcia_sprom_read(bus, i, &sprom[i]);
436 if (err)
437 return err;
438 }
439
440 return 0;
441}
442
443/* Write the SPROM image. size is in 16bit words. */
444static int ssb_pcmcia_sprom_write_all(struct ssb_bus *bus, const u16 *sprom)
445{
446 int i, err;
447 bool failed = 0;
448 size_t size = SSB_PCMCIA_SPROM_SIZE;
449
450 ssb_printk(KERN_NOTICE PFX
451 "Writing SPROM. Do NOT turn off the power! "
452 "Please stand by...\n");
453 err = ssb_pcmcia_sprom_command(bus, SSB_PCMCIA_SPROMCTL_WRITEEN);
454 if (err) {
455 ssb_printk(KERN_NOTICE PFX
456 "Could not enable SPROM write access.\n");
457 return -EBUSY;
458 }
459 ssb_printk(KERN_NOTICE PFX "[ 0%%");
460 msleep(500);
461 for (i = 0; i < size; i++) {
462 if (i == size / 4)
463 ssb_printk("25%%");
464 else if (i == size / 2)
465 ssb_printk("50%%");
466 else if (i == (size * 3) / 4)
467 ssb_printk("75%%");
468 else if (i % 2)
469 ssb_printk(".");
470 err = ssb_pcmcia_sprom_write(bus, i, sprom[i]);
471 if (err) {
472 ssb_printk("\n" KERN_NOTICE PFX
473 "Failed to write to SPROM.\n");
474 failed = 1;
475 break;
476 }
477 }
478 err = ssb_pcmcia_sprom_command(bus, SSB_PCMCIA_SPROMCTL_WRITEDIS);
479 if (err) {
480 ssb_printk("\n" KERN_NOTICE PFX
481 "Could not disable SPROM write access.\n");
482 failed = 1;
483 }
484 msleep(500);
485 if (!failed) {
486 ssb_printk("100%% ]\n");
487 ssb_printk(KERN_NOTICE PFX "SPROM written.\n");
488 }
489
490 return failed ? -EBUSY : 0;
491}
492
493static int ssb_pcmcia_sprom_check_crc(const u16 *sprom, size_t size)
494{
495 //TODO
496 return 0;
497}
498
499#define GOTO_ERROR_ON(condition, description) do { \
500 if (unlikely(condition)) { \
501 error_description = description; \
502 goto error; \
503 } \
504 } while (0)
505
248int ssb_pcmcia_get_invariants(struct ssb_bus *bus, 506int ssb_pcmcia_get_invariants(struct ssb_bus *bus,
249 struct ssb_init_invariants *iv) 507 struct ssb_init_invariants *iv)
250{ 508{
251 //TODO 509 tuple_t tuple;
252 random_ether_addr(iv->sprom.il0mac); 510 int res;
511 unsigned char buf[32];
512 struct ssb_sprom *sprom = &iv->sprom;
513 struct ssb_boardinfo *bi = &iv->boardinfo;
514 const char *error_description;
515
516 memset(sprom, 0xFF, sizeof(*sprom));
517 sprom->revision = 1;
518 sprom->boardflags_lo = 0;
519 sprom->boardflags_hi = 0;
520
521 /* First fetch the MAC address. */
522 memset(&tuple, 0, sizeof(tuple));
523 tuple.DesiredTuple = CISTPL_FUNCE;
524 tuple.TupleData = buf;
525 tuple.TupleDataMax = sizeof(buf);
526 res = pcmcia_get_first_tuple(bus->host_pcmcia, &tuple);
527 GOTO_ERROR_ON(res != CS_SUCCESS, "MAC first tpl");
528 res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
529 GOTO_ERROR_ON(res != CS_SUCCESS, "MAC first tpl data");
530 while (1) {
531 GOTO_ERROR_ON(tuple.TupleDataLen < 1, "MAC tpl < 1");
532 if (tuple.TupleData[0] == CISTPL_FUNCE_LAN_NODE_ID)
533 break;
534 res = pcmcia_get_next_tuple(bus->host_pcmcia, &tuple);
535 GOTO_ERROR_ON(res != CS_SUCCESS, "MAC next tpl");
536 res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
537 GOTO_ERROR_ON(res != CS_SUCCESS, "MAC next tpl data");
538 }
539 GOTO_ERROR_ON(tuple.TupleDataLen != ETH_ALEN + 2, "MAC tpl size");
540 memcpy(sprom->il0mac, &tuple.TupleData[2], ETH_ALEN);
541
542 /* Fetch the vendor specific tuples. */
543 memset(&tuple, 0, sizeof(tuple));
544 tuple.DesiredTuple = SSB_PCMCIA_CIS;
545 tuple.TupleData = buf;
546 tuple.TupleDataMax = sizeof(buf);
547 res = pcmcia_get_first_tuple(bus->host_pcmcia, &tuple);
548 GOTO_ERROR_ON(res != CS_SUCCESS, "VEN first tpl");
549 res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
550 GOTO_ERROR_ON(res != CS_SUCCESS, "VEN first tpl data");
551 while (1) {
552 GOTO_ERROR_ON(tuple.TupleDataLen < 1, "VEN tpl < 1");
553 switch (tuple.TupleData[0]) {
554 case SSB_PCMCIA_CIS_ID:
555 GOTO_ERROR_ON((tuple.TupleDataLen != 5) &&
556 (tuple.TupleDataLen != 7),
557 "id tpl size");
558 bi->vendor = tuple.TupleData[1] |
559 ((u16)tuple.TupleData[2] << 8);
560 break;
561 case SSB_PCMCIA_CIS_BOARDREV:
562 GOTO_ERROR_ON(tuple.TupleDataLen != 2,
563 "boardrev tpl size");
564 sprom->board_rev = tuple.TupleData[1];
565 break;
566 case SSB_PCMCIA_CIS_PA:
567 GOTO_ERROR_ON(tuple.TupleDataLen != 9,
568 "pa tpl size");
569 sprom->pa0b0 = tuple.TupleData[1] |
570 ((u16)tuple.TupleData[2] << 8);
571 sprom->pa0b1 = tuple.TupleData[3] |
572 ((u16)tuple.TupleData[4] << 8);
573 sprom->pa0b2 = tuple.TupleData[5] |
574 ((u16)tuple.TupleData[6] << 8);
575 sprom->itssi_a = tuple.TupleData[7];
576 sprom->itssi_bg = tuple.TupleData[7];
577 sprom->maxpwr_a = tuple.TupleData[8];
578 sprom->maxpwr_bg = tuple.TupleData[8];
579 break;
580 case SSB_PCMCIA_CIS_OEMNAME:
581 /* We ignore this. */
582 break;
583 case SSB_PCMCIA_CIS_CCODE:
584 GOTO_ERROR_ON(tuple.TupleDataLen != 2,
585 "ccode tpl size");
586 sprom->country_code = tuple.TupleData[1];
587 break;
588 case SSB_PCMCIA_CIS_ANTENNA:
589 GOTO_ERROR_ON(tuple.TupleDataLen != 2,
590 "ant tpl size");
591 sprom->ant_available_a = tuple.TupleData[1];
592 sprom->ant_available_bg = tuple.TupleData[1];
593 break;
594 case SSB_PCMCIA_CIS_ANTGAIN:
595 GOTO_ERROR_ON(tuple.TupleDataLen != 2,
596 "antg tpl size");
597 sprom->antenna_gain.ghz24.a0 = tuple.TupleData[1];
598 sprom->antenna_gain.ghz24.a1 = tuple.TupleData[1];
599 sprom->antenna_gain.ghz24.a2 = tuple.TupleData[1];
600 sprom->antenna_gain.ghz24.a3 = tuple.TupleData[1];
601 sprom->antenna_gain.ghz5.a0 = tuple.TupleData[1];
602 sprom->antenna_gain.ghz5.a1 = tuple.TupleData[1];
603 sprom->antenna_gain.ghz5.a2 = tuple.TupleData[1];
604 sprom->antenna_gain.ghz5.a3 = tuple.TupleData[1];
605 break;
606 case SSB_PCMCIA_CIS_BFLAGS:
607 GOTO_ERROR_ON(tuple.TupleDataLen != 3,
608 "bfl tpl size");
609 sprom->boardflags_lo = tuple.TupleData[1] |
610 ((u16)tuple.TupleData[2] << 8);
611 break;
612 case SSB_PCMCIA_CIS_LEDS:
613 GOTO_ERROR_ON(tuple.TupleDataLen != 5,
614 "leds tpl size");
615 sprom->gpio0 = tuple.TupleData[1];
616 sprom->gpio1 = tuple.TupleData[2];
617 sprom->gpio2 = tuple.TupleData[3];
618 sprom->gpio3 = tuple.TupleData[4];
619 break;
620 }
621 res = pcmcia_get_next_tuple(bus->host_pcmcia, &tuple);
622 if (res == CS_NO_MORE_ITEMS)
623 break;
624 GOTO_ERROR_ON(res != CS_SUCCESS, "VEN next tpl");
625 res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
626 GOTO_ERROR_ON(res != CS_SUCCESS, "VEN next tpl data");
627 }
628
253 return 0; 629 return 0;
630error:
631 ssb_printk(KERN_ERR PFX
632 "PCMCIA: Failed to fetch device invariants: %s\n",
633 error_description);
634 return -ENODEV;
635}
636
637static ssize_t ssb_pcmcia_attr_sprom_show(struct device *pcmciadev,
638 struct device_attribute *attr,
639 char *buf)
640{
641 struct pcmcia_device *pdev =
642 container_of(pcmciadev, struct pcmcia_device, dev);
643 struct ssb_bus *bus;
644
645 bus = ssb_pcmcia_dev_to_bus(pdev);
646 if (!bus)
647 return -ENODEV;
648
649 return ssb_attr_sprom_show(bus, buf,
650 ssb_pcmcia_sprom_read_all);
651}
652
653static ssize_t ssb_pcmcia_attr_sprom_store(struct device *pcmciadev,
654 struct device_attribute *attr,
655 const char *buf, size_t count)
656{
657 struct pcmcia_device *pdev =
658 container_of(pcmciadev, struct pcmcia_device, dev);
659 struct ssb_bus *bus;
660
661 bus = ssb_pcmcia_dev_to_bus(pdev);
662 if (!bus)
663 return -ENODEV;
664
665 return ssb_attr_sprom_store(bus, buf, count,
666 ssb_pcmcia_sprom_check_crc,
667 ssb_pcmcia_sprom_write_all);
668}
669
670static DEVICE_ATTR(ssb_sprom, 0600,
671 ssb_pcmcia_attr_sprom_show,
672 ssb_pcmcia_attr_sprom_store);
673
674void ssb_pcmcia_exit(struct ssb_bus *bus)
675{
676 if (bus->bustype != SSB_BUSTYPE_PCMCIA)
677 return;
678
679 device_remove_file(&bus->host_pcmcia->dev, &dev_attr_ssb_sprom);
254} 680}
255 681
256int ssb_pcmcia_init(struct ssb_bus *bus) 682int ssb_pcmcia_init(struct ssb_bus *bus)
257{ 683{
258 conf_reg_t reg; 684 u8 val, offset;
259 int err; 685 int err;
260 686
261 if (bus->bustype != SSB_BUSTYPE_PCMCIA) 687 if (bus->bustype != SSB_BUSTYPE_PCMCIA)
@@ -266,22 +692,26 @@ int ssb_pcmcia_init(struct ssb_bus *bus)
266 ssb_pcmcia_switch_segment(bus, 0); 692 ssb_pcmcia_switch_segment(bus, 0);
267 693
268 /* Init IRQ routing */ 694 /* Init IRQ routing */
269 reg.Action = CS_READ;
270 reg.Function = 0;
271 if (bus->chip_id == 0x4306) 695 if (bus->chip_id == 0x4306)
272 reg.Offset = 0x00; 696 offset = SSB_PCMCIA_CORECTL;
273 else 697 else
274 reg.Offset = 0x80; 698 offset = SSB_PCMCIA_CORECTL2;
275 err = pcmcia_access_configuration_register(bus->host_pcmcia, &reg); 699 err = ssb_pcmcia_cfg_read(bus, offset, &val);
276 if (err != CS_SUCCESS) 700 if (err)
277 goto error; 701 goto error;
278 reg.Action = CS_WRITE; 702 val |= SSB_PCMCIA_CORECTL_IRQEN | SSB_PCMCIA_CORECTL_FUNCEN;
279 reg.Value |= 0x04 | 0x01; 703 err = ssb_pcmcia_cfg_write(bus, offset, val);
280 err = pcmcia_access_configuration_register(bus->host_pcmcia, &reg); 704 if (err)
281 if (err != CS_SUCCESS) 705 goto error;
706
707 bus->sprom_size = SSB_PCMCIA_SPROM_SIZE;
708 mutex_init(&bus->sprom_mutex);
709 err = device_create_file(&bus->host_pcmcia->dev, &dev_attr_ssb_sprom);
710 if (err)
282 goto error; 711 goto error;
283 712
284 return 0; 713 return 0;
285error: 714error:
286 return -ENODEV; 715 ssb_printk(KERN_ERR PFX "Failed to initialize PCMCIA host device\n");
716 return err;
287} 717}
diff --git a/drivers/ssb/sprom.c b/drivers/ssb/sprom.c
new file mode 100644
index 000000000000..3668edb39315
--- /dev/null
+++ b/drivers/ssb/sprom.c
@@ -0,0 +1,133 @@
1/*
2 * Sonics Silicon Backplane
3 * Common SPROM support routines
4 *
5 * Copyright (C) 2005-2008 Michael Buesch <mb@bu3sch.de>
6 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
7 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
8 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 * Copyright (C) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10 *
11 * Licensed under the GNU/GPL. See COPYING for details.
12 */
13
14#include "ssb_private.h"
15
16
17static int sprom2hex(const u16 *sprom, char *buf, size_t buf_len,
18 size_t sprom_size_words)
19{
20 int i, pos = 0;
21
22 for (i = 0; i < sprom_size_words; i++)
23 pos += snprintf(buf + pos, buf_len - pos - 1,
24 "%04X", swab16(sprom[i]) & 0xFFFF);
25 pos += snprintf(buf + pos, buf_len - pos - 1, "\n");
26
27 return pos + 1;
28}
29
30static int hex2sprom(u16 *sprom, const char *dump, size_t len,
31 size_t sprom_size_words)
32{
33 char tmp[5] = { 0 };
34 int cnt = 0;
35 unsigned long parsed;
36
37 if (len < sprom_size_words * 2)
38 return -EINVAL;
39
40 while (cnt < sprom_size_words) {
41 memcpy(tmp, dump, 4);
42 dump += 4;
43 parsed = simple_strtoul(tmp, NULL, 16);
44 sprom[cnt++] = swab16((u16)parsed);
45 }
46
47 return 0;
48}
49
50/* Common sprom device-attribute show-handler */
51ssize_t ssb_attr_sprom_show(struct ssb_bus *bus, char *buf,
52 int (*sprom_read)(struct ssb_bus *bus, u16 *sprom))
53{
54 u16 *sprom;
55 int err = -ENOMEM;
56 ssize_t count = 0;
57 size_t sprom_size_words = bus->sprom_size;
58
59 sprom = kcalloc(sprom_size_words, sizeof(u16), GFP_KERNEL);
60 if (!sprom)
61 goto out;
62
63 /* Use interruptible locking, as the SPROM write might
64 * be holding the lock for several seconds. So allow userspace
65 * to cancel operation. */
66 err = -ERESTARTSYS;
67 if (mutex_lock_interruptible(&bus->sprom_mutex))
68 goto out_kfree;
69 err = sprom_read(bus, sprom);
70 mutex_unlock(&bus->sprom_mutex);
71
72 if (!err)
73 count = sprom2hex(sprom, buf, PAGE_SIZE, sprom_size_words);
74
75out_kfree:
76 kfree(sprom);
77out:
78 return err ? err : count;
79}
80
81/* Common sprom device-attribute store-handler */
82ssize_t ssb_attr_sprom_store(struct ssb_bus *bus,
83 const char *buf, size_t count,
84 int (*sprom_check_crc)(const u16 *sprom, size_t size),
85 int (*sprom_write)(struct ssb_bus *bus, const u16 *sprom))
86{
87 u16 *sprom;
88 int res = 0, err = -ENOMEM;
89 size_t sprom_size_words = bus->sprom_size;
90
91 sprom = kcalloc(bus->sprom_size, sizeof(u16), GFP_KERNEL);
92 if (!sprom)
93 goto out;
94 err = hex2sprom(sprom, buf, count, sprom_size_words);
95 if (err) {
96 err = -EINVAL;
97 goto out_kfree;
98 }
99 err = sprom_check_crc(sprom, sprom_size_words);
100 if (err) {
101 err = -EINVAL;
102 goto out_kfree;
103 }
104
105 /* Use interruptible locking, as the SPROM write might
106 * be holding the lock for several seconds. So allow userspace
107 * to cancel operation. */
108 err = -ERESTARTSYS;
109 if (mutex_lock_interruptible(&bus->sprom_mutex))
110 goto out_kfree;
111 err = ssb_devices_freeze(bus);
112 if (err == -EOPNOTSUPP) {
113 ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze devices. "
114 "No suspend support. Is CONFIG_PM enabled?\n");
115 goto out_unlock;
116 }
117 if (err) {
118 ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze all devices\n");
119 goto out_unlock;
120 }
121 res = sprom_write(bus, sprom);
122 err = ssb_devices_thaw(bus);
123 if (err)
124 ssb_printk(KERN_ERR PFX "SPROM write: Could not thaw all devices\n");
125out_unlock:
126 mutex_unlock(&bus->sprom_mutex);
127out_kfree:
128 kfree(sprom);
129out:
130 if (res)
131 return res;
132 return err ? err : count;
133}
diff --git a/drivers/ssb/ssb_private.h b/drivers/ssb/ssb_private.h
index 21eca2b5118b..a83bf7a4d80b 100644
--- a/drivers/ssb/ssb_private.h
+++ b/drivers/ssb/ssb_private.h
@@ -81,6 +81,7 @@ extern int ssb_pcmcia_switch_segment(struct ssb_bus *bus,
81 u8 seg); 81 u8 seg);
82extern int ssb_pcmcia_get_invariants(struct ssb_bus *bus, 82extern int ssb_pcmcia_get_invariants(struct ssb_bus *bus,
83 struct ssb_init_invariants *iv); 83 struct ssb_init_invariants *iv);
84extern void ssb_pcmcia_exit(struct ssb_bus *bus);
84extern int ssb_pcmcia_init(struct ssb_bus *bus); 85extern int ssb_pcmcia_init(struct ssb_bus *bus);
85extern const struct ssb_bus_ops ssb_pcmcia_ops; 86extern const struct ssb_bus_ops ssb_pcmcia_ops;
86#else /* CONFIG_SSB_PCMCIAHOST */ 87#else /* CONFIG_SSB_PCMCIAHOST */
@@ -99,6 +100,9 @@ static inline int ssb_pcmcia_switch_segment(struct ssb_bus *bus,
99{ 100{
100 return 0; 101 return 0;
101} 102}
103static inline void ssb_pcmcia_exit(struct ssb_bus *bus)
104{
105}
102static inline int ssb_pcmcia_init(struct ssb_bus *bus) 106static inline int ssb_pcmcia_init(struct ssb_bus *bus)
103{ 107{
104 return 0; 108 return 0;
@@ -113,11 +117,26 @@ extern int ssb_bus_scan(struct ssb_bus *bus,
113extern void ssb_iounmap(struct ssb_bus *ssb); 117extern void ssb_iounmap(struct ssb_bus *ssb);
114 118
115 119
120/* sprom.c */
121extern
122ssize_t ssb_attr_sprom_show(struct ssb_bus *bus, char *buf,
123 int (*sprom_read)(struct ssb_bus *bus, u16 *sprom));
124extern
125ssize_t ssb_attr_sprom_store(struct ssb_bus *bus,
126 const char *buf, size_t count,
127 int (*sprom_check_crc)(const u16 *sprom, size_t size),
128 int (*sprom_write)(struct ssb_bus *bus, const u16 *sprom));
129
130
116/* core.c */ 131/* core.c */
117extern u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m); 132extern u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m);
118extern int ssb_devices_freeze(struct ssb_bus *bus); 133extern int ssb_devices_freeze(struct ssb_bus *bus);
119extern int ssb_devices_thaw(struct ssb_bus *bus); 134extern int ssb_devices_thaw(struct ssb_bus *bus);
120extern struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev); 135extern struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev);
136int ssb_for_each_bus_call(unsigned long data,
137 int (*func)(struct ssb_bus *bus, unsigned long data));
138extern struct ssb_bus *ssb_pcmcia_dev_to_bus(struct pcmcia_device *pdev);
139
121 140
122/* b43_pci_bridge.c */ 141/* b43_pci_bridge.c */
123#ifdef CONFIG_SSB_B43_PCI_BRIDGE 142#ifdef CONFIG_SSB_B43_PCI_BRIDGE
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-26 09:54:42 -0500