1 files changed, 103 insertions, 26 deletions

diff --git a/drivers/ssb/main.c b/drivers/ssb/main.c
index 7892ac163522..f8a13f863217 100644
--- a/drivers/ssb/main.c
+++ b/drivers/ssb/main.c
@@ -20,7 +20,6 @@
 #include <linux/mmc/sdio_func.h>
 #include <linux/slab.h>
 
-#include <pcmcia/cs.h>
 #include <pcmcia/cistpl.h>
 #include <pcmcia/ds.h>
 
@@ -384,6 +383,35 @@ static int ssb_device_uevent(struct device *dev, struct kobj_uevent_env *env)
                              ssb_dev->id.revision);
 }
 
+#define ssb_config_attr(attrib, field, format_string) \
+static ssize_t \
+attrib##_show(struct device *dev, struct device_attribute *attr, char *buf) \
+{ \
+        return sprintf(buf, format_string, dev_to_ssb_dev(dev)->field); \
+}
+
+ssb_config_attr(core_num, core_index, "%u\n")
+ssb_config_attr(coreid, id.coreid, "0x%04x\n")
+ssb_config_attr(vendor, id.vendor, "0x%04x\n")
+ssb_config_attr(revision, id.revision, "%u\n")
+ssb_config_attr(irq, irq, "%u\n")
+static ssize_t
+name_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+        return sprintf(buf, "%s\n",
+                       ssb_core_name(dev_to_ssb_dev(dev)->id.coreid));
+}
+
+static struct device_attribute ssb_device_attrs[] = {
+        __ATTR_RO(name),
+        __ATTR_RO(core_num),
+        __ATTR_RO(coreid),
+        __ATTR_RO(vendor),
+        __ATTR_RO(revision),
+        __ATTR_RO(irq),
+        __ATTR_NULL,
+};
+
 static struct bus_type ssb_bustype = {
         .name           = "ssb",
         .match          = ssb_bus_match,
@@ -393,6 +421,7 @@ static struct bus_type ssb_bustype = {
         .suspend        = ssb_device_suspend,
         .resume         = ssb_device_resume,
         .uevent         = ssb_device_uevent,
+        .dev_attrs      = ssb_device_attrs,
 };
 
 static void ssb_buses_lock(void)
@@ -1088,23 +1117,22 @@ static u32 ssb_tmslow_reject_bitmask(struct ssb_device *dev)
 {
         u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV;
 
-        /* The REJECT bit changed position in TMSLOW between
-         * Backplane revisions. */
+        /* The REJECT bit seems to be different for Backplane rev 2.3 */
         switch (rev) {
         case SSB_IDLOW_SSBREV_22:
-                return SSB_TMSLOW_REJECT_22;
+        case SSB_IDLOW_SSBREV_24:
+        case SSB_IDLOW_SSBREV_26:
+                return SSB_TMSLOW_REJECT;
         case SSB_IDLOW_SSBREV_23:
                 return SSB_TMSLOW_REJECT_23;
-        case SSB_IDLOW_SSBREV_24:     /* TODO - find the proper REJECT bits */
-        case SSB_IDLOW_SSBREV_25:     /* same here */
-        case SSB_IDLOW_SSBREV_26:     /* same here */
+        case SSB_IDLOW_SSBREV_25:     /* TODO - find the proper REJECT bit */
         case SSB_IDLOW_SSBREV_27:     /* same here */
-                return SSB_TMSLOW_REJECT_23;    /* this is a guess */
+                return SSB_TMSLOW_REJECT;       /* this is a guess */
         default:
                 printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
                 WARN_ON(1);
         }
-        return (SSB_TMSLOW_REJECT_22 | SSB_TMSLOW_REJECT_23);
+        return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
 }
 
 int ssb_device_is_enabled(struct ssb_device *dev)
@@ -1163,10 +1191,10 @@ void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags)
 }
 EXPORT_SYMBOL(ssb_device_enable);
 
-/* Wait for a bit in a register to get set or unset.
+/* Wait for bitmask in a register to get set or cleared.
  * timeout is in units of ten-microseconds */
-static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask,
-                        int timeout, int set)
+static int ssb_wait_bits(struct ssb_device *dev, u16 reg, u32 bitmask,
+                         int timeout, int set)
 {
         int i;
         u32 val;
@@ -1174,7 +1202,7 @@ static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask,
         for (i = 0; i < timeout; i++) {
                 val = ssb_read32(dev, reg);
                 if (set) {
-                        if (val & bitmask)
+                        if ((val & bitmask) == bitmask)
                                 return 0;
                 } else {
                         if (!(val & bitmask))
@@ -1191,20 +1219,38 @@ static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask,
 
 void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
 {
-        u32 reject;
+        u32 reject, val;
 
         if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
                 return;
 
         reject = ssb_tmslow_reject_bitmask(dev);
-        ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
-        ssb_wait_bit(dev, SSB_TMSLOW, reject, 1000, 1);
-        ssb_wait_bit(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
-        ssb_write32(dev, SSB_TMSLOW,
-                    SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
-                    reject | SSB_TMSLOW_RESET |
-                    core_specific_flags);
-        ssb_flush_tmslow(dev);
+
+        if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_CLOCK) {
+                ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
+                ssb_wait_bits(dev, SSB_TMSLOW, reject, 1000, 1);
+                ssb_wait_bits(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
+
+                if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
+                        val = ssb_read32(dev, SSB_IMSTATE);
+                        val |= SSB_IMSTATE_REJECT;
+                        ssb_write32(dev, SSB_IMSTATE, val);
+                        ssb_wait_bits(dev, SSB_IMSTATE, SSB_IMSTATE_BUSY, 1000,
+                                      0);
+                }
+
+                ssb_write32(dev, SSB_TMSLOW,
+                        SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
+                        reject | SSB_TMSLOW_RESET |
+                        core_specific_flags);
+                ssb_flush_tmslow(dev);
+
+                if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
+                        val = ssb_read32(dev, SSB_IMSTATE);
+                        val &= ~SSB_IMSTATE_REJECT;
+                        ssb_write32(dev, SSB_IMSTATE, val);
+                }
+        }
 
         ssb_write32(dev, SSB_TMSLOW,
                     reject | SSB_TMSLOW_RESET |
@@ -1262,20 +1308,20 @@ EXPORT_SYMBOL(ssb_bus_may_powerdown);
 
 int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl)
 {
-        struct ssb_chipcommon *cc;
         int err;
         enum ssb_clkmode mode;
 
         err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
         if (err)
                 goto error;
-        cc = &bus->chipco;
-        mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
-        ssb_chipco_set_clockmode(cc, mode);
 
 #ifdef CONFIG_SSB_DEBUG
         bus->powered_up = 1;
 #endif
+
+        mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
+        ssb_chipco_set_clockmode(&bus->chipco, mode);
+
         return 0;
 error:
         ssb_printk(KERN_ERR PFX "Bus powerup failed\n");
@@ -1283,6 +1329,37 @@ error:
 }
 EXPORT_SYMBOL(ssb_bus_powerup);
 
+static void ssb_broadcast_value(struct ssb_device *dev,
+                                u32 address, u32 data)
+{
+#ifdef CONFIG_SSB_DRIVER_PCICORE
+        /* This is used for both, PCI and ChipCommon core, so be careful. */
+        BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
+        BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
+#endif
+
+        ssb_write32(dev, SSB_CHIPCO_BCAST_ADDR, address);
+        ssb_read32(dev, SSB_CHIPCO_BCAST_ADDR); /* flush */
+        ssb_write32(dev, SSB_CHIPCO_BCAST_DATA, data);
+        ssb_read32(dev, SSB_CHIPCO_BCAST_DATA); /* flush */
+}
+
+void ssb_commit_settings(struct ssb_bus *bus)
+{
+        struct ssb_device *dev;
+
+#ifdef CONFIG_SSB_DRIVER_PCICORE
+        dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
+#else
+        dev = bus->chipco.dev;
+#endif
+        if (WARN_ON(!dev))
+                return;
+        /* This forces an update of the cached registers. */
+        ssb_broadcast_value(dev, 0xFD8, 0);
+}
+EXPORT_SYMBOL(ssb_commit_settings);
+
 u32 ssb_admatch_base(u32 adm)
 {
         u32 base = 0;