aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/spi
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/spi')
-rw-r--r--drivers/spi/Kconfig6
-rw-r--r--drivers/spi/Makefile1
-rw-r--r--drivers/spi/omap2_mcspi.c1081
3 files changed, 1088 insertions, 0 deletions
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 22feb3c8de55..5ac498bbf2b6 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -142,6 +142,12 @@ config SPI_OMAP_UWIRE
142 help 142 help
143 This hooks up to the MicroWire controller on OMAP1 chips. 143 This hooks up to the MicroWire controller on OMAP1 chips.
144 144
145config SPI_OMAP24XX
146 tristate "McSPI driver for OMAP24xx"
147 depends on SPI_MASTER && ARCH_OMAP24XX
148 help
149 SPI master controller for OMAP24xx Multichannel SPI
150 (McSPI) modules.
145 151
146config SPI_PXA2XX 152config SPI_PXA2XX
147 tristate "PXA2xx SSP SPI master" 153 tristate "PXA2xx SSP SPI master"
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 9c95db2b6bbd..be69667e0871 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_SPI_IMX) += spi_imx.o
20obj-$(CONFIG_SPI_LM70_LLP) += spi_lm70llp.o 20obj-$(CONFIG_SPI_LM70_LLP) += spi_lm70llp.o
21obj-$(CONFIG_SPI_PXA2XX) += pxa2xx_spi.o 21obj-$(CONFIG_SPI_PXA2XX) += pxa2xx_spi.o
22obj-$(CONFIG_SPI_OMAP_UWIRE) += omap_uwire.o 22obj-$(CONFIG_SPI_OMAP_UWIRE) += omap_uwire.o
23obj-$(CONFIG_SPI_OMAP24XX) += omap2_mcspi.o
23obj-$(CONFIG_SPI_MPC52xx_PSC) += mpc52xx_psc_spi.o 24obj-$(CONFIG_SPI_MPC52xx_PSC) += mpc52xx_psc_spi.o
24obj-$(CONFIG_SPI_MPC83xx) += spi_mpc83xx.o 25obj-$(CONFIG_SPI_MPC83xx) += spi_mpc83xx.o
25obj-$(CONFIG_SPI_S3C24XX_GPIO) += spi_s3c24xx_gpio.o 26obj-$(CONFIG_SPI_S3C24XX_GPIO) += spi_s3c24xx_gpio.o
diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c
new file mode 100644
index 000000000000..6b357cdb9ea3
--- /dev/null
+++ b/drivers/spi/omap2_mcspi.c
@@ -0,0 +1,1081 @@
1/*
2 * OMAP2 McSPI controller driver
3 *
4 * Copyright (C) 2005, 2006 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
6 * Juha Yrjölä <juha.yrjola@nokia.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24#include <linux/kernel.h>
25#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <linux/module.h>
28#include <linux/device.h>
29#include <linux/delay.h>
30#include <linux/dma-mapping.h>
31#include <linux/platform_device.h>
32#include <linux/err.h>
33#include <linux/clk.h>
34#include <linux/io.h>
35
36#include <linux/spi/spi.h>
37
38#include <asm/arch/dma.h>
39#include <asm/arch/clock.h>
40
41
42#define OMAP2_MCSPI_MAX_FREQ 48000000
43
44#define OMAP2_MCSPI_REVISION 0x00
45#define OMAP2_MCSPI_SYSCONFIG 0x10
46#define OMAP2_MCSPI_SYSSTATUS 0x14
47#define OMAP2_MCSPI_IRQSTATUS 0x18
48#define OMAP2_MCSPI_IRQENABLE 0x1c
49#define OMAP2_MCSPI_WAKEUPENABLE 0x20
50#define OMAP2_MCSPI_SYST 0x24
51#define OMAP2_MCSPI_MODULCTRL 0x28
52
53/* per-channel banks, 0x14 bytes each, first is: */
54#define OMAP2_MCSPI_CHCONF0 0x2c
55#define OMAP2_MCSPI_CHSTAT0 0x30
56#define OMAP2_MCSPI_CHCTRL0 0x34
57#define OMAP2_MCSPI_TX0 0x38
58#define OMAP2_MCSPI_RX0 0x3c
59
60/* per-register bitmasks: */
61
62#define OMAP2_MCSPI_SYSCONFIG_AUTOIDLE (1 << 0)
63#define OMAP2_MCSPI_SYSCONFIG_SOFTRESET (1 << 1)
64
65#define OMAP2_MCSPI_SYSSTATUS_RESETDONE (1 << 0)
66
67#define OMAP2_MCSPI_MODULCTRL_SINGLE (1 << 0)
68#define OMAP2_MCSPI_MODULCTRL_MS (1 << 2)
69#define OMAP2_MCSPI_MODULCTRL_STEST (1 << 3)
70
71#define OMAP2_MCSPI_CHCONF_PHA (1 << 0)
72#define OMAP2_MCSPI_CHCONF_POL (1 << 1)
73#define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
74#define OMAP2_MCSPI_CHCONF_EPOL (1 << 6)
75#define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7)
76#define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY (0x01 << 12)
77#define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY (0x02 << 12)
78#define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
79#define OMAP2_MCSPI_CHCONF_DMAW (1 << 14)
80#define OMAP2_MCSPI_CHCONF_DMAR (1 << 15)
81#define OMAP2_MCSPI_CHCONF_DPE0 (1 << 16)
82#define OMAP2_MCSPI_CHCONF_DPE1 (1 << 17)
83#define OMAP2_MCSPI_CHCONF_IS (1 << 18)
84#define OMAP2_MCSPI_CHCONF_TURBO (1 << 19)
85#define OMAP2_MCSPI_CHCONF_FORCE (1 << 20)
86
87#define OMAP2_MCSPI_CHSTAT_RXS (1 << 0)
88#define OMAP2_MCSPI_CHSTAT_TXS (1 << 1)
89#define OMAP2_MCSPI_CHSTAT_EOT (1 << 2)
90
91#define OMAP2_MCSPI_CHCTRL_EN (1 << 0)
92
93
94/* We have 2 DMA channels per CS, one for RX and one for TX */
95struct omap2_mcspi_dma {
96 int dma_tx_channel;
97 int dma_rx_channel;
98
99 int dma_tx_sync_dev;
100 int dma_rx_sync_dev;
101
102 struct completion dma_tx_completion;
103 struct completion dma_rx_completion;
104};
105
106/* use PIO for small transfers, avoiding DMA setup/teardown overhead and
107 * cache operations; better heuristics consider wordsize and bitrate.
108 */
109#define DMA_MIN_BYTES 8
110
111
112struct omap2_mcspi {
113 struct work_struct work;
114 /* lock protects queue and registers */
115 spinlock_t lock;
116 struct list_head msg_queue;
117 struct spi_master *master;
118 struct clk *ick;
119 struct clk *fck;
120 /* Virtual base address of the controller */
121 void __iomem *base;
122 /* SPI1 has 4 channels, while SPI2 has 2 */
123 struct omap2_mcspi_dma *dma_channels;
124};
125
126struct omap2_mcspi_cs {
127 void __iomem *base;
128 int word_len;
129};
130
131static struct workqueue_struct *omap2_mcspi_wq;
132
133#define MOD_REG_BIT(val, mask, set) do { \
134 if (set) \
135 val |= mask; \
136 else \
137 val &= ~mask; \
138} while (0)
139
140static inline void mcspi_write_reg(struct spi_master *master,
141 int idx, u32 val)
142{
143 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
144
145 __raw_writel(val, mcspi->base + idx);
146}
147
148static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
149{
150 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
151
152 return __raw_readl(mcspi->base + idx);
153}
154
155static inline void mcspi_write_cs_reg(const struct spi_device *spi,
156 int idx, u32 val)
157{
158 struct omap2_mcspi_cs *cs = spi->controller_state;
159
160 __raw_writel(val, cs->base + idx);
161}
162
163static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
164{
165 struct omap2_mcspi_cs *cs = spi->controller_state;
166
167 return __raw_readl(cs->base + idx);
168}
169
170static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
171 int is_read, int enable)
172{
173 u32 l, rw;
174
175 l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
176
177 if (is_read) /* 1 is read, 0 write */
178 rw = OMAP2_MCSPI_CHCONF_DMAR;
179 else
180 rw = OMAP2_MCSPI_CHCONF_DMAW;
181
182 MOD_REG_BIT(l, rw, enable);
183 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, l);
184}
185
186static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
187{
188 u32 l;
189
190 l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0;
191 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l);
192}
193
194static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
195{
196 u32 l;
197
198 l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
199 MOD_REG_BIT(l, OMAP2_MCSPI_CHCONF_FORCE, cs_active);
200 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, l);
201}
202
203static void omap2_mcspi_set_master_mode(struct spi_master *master)
204{
205 u32 l;
206
207 /* setup when switching from (reset default) slave mode
208 * to single-channel master mode
209 */
210 l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
211 MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_STEST, 0);
212 MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_MS, 0);
213 MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_SINGLE, 1);
214 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
215}
216
217static unsigned
218omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
219{
220 struct omap2_mcspi *mcspi;
221 struct omap2_mcspi_cs *cs = spi->controller_state;
222 struct omap2_mcspi_dma *mcspi_dma;
223 unsigned int count, c;
224 unsigned long base, tx_reg, rx_reg;
225 int word_len, data_type, element_count;
226 u8 * rx;
227 const u8 * tx;
228
229 mcspi = spi_master_get_devdata(spi->master);
230 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
231
232 count = xfer->len;
233 c = count;
234 word_len = cs->word_len;
235
236 base = (unsigned long) io_v2p(cs->base);
237 tx_reg = base + OMAP2_MCSPI_TX0;
238 rx_reg = base + OMAP2_MCSPI_RX0;
239 rx = xfer->rx_buf;
240 tx = xfer->tx_buf;
241
242 if (word_len <= 8) {
243 data_type = OMAP_DMA_DATA_TYPE_S8;
244 element_count = count;
245 } else if (word_len <= 16) {
246 data_type = OMAP_DMA_DATA_TYPE_S16;
247 element_count = count >> 1;
248 } else /* word_len <= 32 */ {
249 data_type = OMAP_DMA_DATA_TYPE_S32;
250 element_count = count >> 2;
251 }
252
253 if (tx != NULL) {
254 omap_set_dma_transfer_params(mcspi_dma->dma_tx_channel,
255 data_type, element_count, 1,
256 OMAP_DMA_SYNC_ELEMENT,
257 mcspi_dma->dma_tx_sync_dev, 0);
258
259 omap_set_dma_dest_params(mcspi_dma->dma_tx_channel, 0,
260 OMAP_DMA_AMODE_CONSTANT,
261 tx_reg, 0, 0);
262
263 omap_set_dma_src_params(mcspi_dma->dma_tx_channel, 0,
264 OMAP_DMA_AMODE_POST_INC,
265 xfer->tx_dma, 0, 0);
266 }
267
268 if (rx != NULL) {
269 omap_set_dma_transfer_params(mcspi_dma->dma_rx_channel,
270 data_type, element_count, 1,
271 OMAP_DMA_SYNC_ELEMENT,
272 mcspi_dma->dma_rx_sync_dev, 1);
273
274 omap_set_dma_src_params(mcspi_dma->dma_rx_channel, 0,
275 OMAP_DMA_AMODE_CONSTANT,
276 rx_reg, 0, 0);
277
278 omap_set_dma_dest_params(mcspi_dma->dma_rx_channel, 0,
279 OMAP_DMA_AMODE_POST_INC,
280 xfer->rx_dma, 0, 0);
281 }
282
283 if (tx != NULL) {
284 omap_start_dma(mcspi_dma->dma_tx_channel);
285 omap2_mcspi_set_dma_req(spi, 0, 1);
286 }
287
288 if (rx != NULL) {
289 omap_start_dma(mcspi_dma->dma_rx_channel);
290 omap2_mcspi_set_dma_req(spi, 1, 1);
291 }
292
293 if (tx != NULL) {
294 wait_for_completion(&mcspi_dma->dma_tx_completion);
295 dma_unmap_single(NULL, xfer->tx_dma, count, DMA_TO_DEVICE);
296 }
297
298 if (rx != NULL) {
299 wait_for_completion(&mcspi_dma->dma_rx_completion);
300 dma_unmap_single(NULL, xfer->rx_dma, count, DMA_FROM_DEVICE);
301 }
302 return count;
303}
304
305static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
306{
307 unsigned long timeout;
308
309 timeout = jiffies + msecs_to_jiffies(1000);
310 while (!(__raw_readl(reg) & bit)) {
311 if (time_after(jiffies, timeout))
312 return -1;
313 cpu_relax();
314 }
315 return 0;
316}
317
318static unsigned
319omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
320{
321 struct omap2_mcspi *mcspi;
322 struct omap2_mcspi_cs *cs = spi->controller_state;
323 unsigned int count, c;
324 u32 l;
325 void __iomem *base = cs->base;
326 void __iomem *tx_reg;
327 void __iomem *rx_reg;
328 void __iomem *chstat_reg;
329 int word_len;
330
331 mcspi = spi_master_get_devdata(spi->master);
332 count = xfer->len;
333 c = count;
334 word_len = cs->word_len;
335
336 l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
337 l &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
338
339 /* We store the pre-calculated register addresses on stack to speed
340 * up the transfer loop. */
341 tx_reg = base + OMAP2_MCSPI_TX0;
342 rx_reg = base + OMAP2_MCSPI_RX0;
343 chstat_reg = base + OMAP2_MCSPI_CHSTAT0;
344
345 if (word_len <= 8) {
346 u8 *rx;
347 const u8 *tx;
348
349 rx = xfer->rx_buf;
350 tx = xfer->tx_buf;
351
352 do {
353 if (tx != NULL) {
354 if (mcspi_wait_for_reg_bit(chstat_reg,
355 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
356 dev_err(&spi->dev, "TXS timed out\n");
357 goto out;
358 }
359#ifdef VERBOSE
360 dev_dbg(&spi->dev, "write-%d %02x\n",
361 word_len, *tx);
362#endif
363 __raw_writel(*tx++, tx_reg);
364 }
365 if (rx != NULL) {
366 if (mcspi_wait_for_reg_bit(chstat_reg,
367 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
368 dev_err(&spi->dev, "RXS timed out\n");
369 goto out;
370 }
371 /* prevent last RX_ONLY read from triggering
372 * more word i/o: switch to rx+tx
373 */
374 if (c == 0 && tx == NULL)
375 mcspi_write_cs_reg(spi,
376 OMAP2_MCSPI_CHCONF0, l);
377 *rx++ = __raw_readl(rx_reg);
378#ifdef VERBOSE
379 dev_dbg(&spi->dev, "read-%d %02x\n",
380 word_len, *(rx - 1));
381#endif
382 }
383 c -= 1;
384 } while (c);
385 } else if (word_len <= 16) {
386 u16 *rx;
387 const u16 *tx;
388
389 rx = xfer->rx_buf;
390 tx = xfer->tx_buf;
391 do {
392 if (tx != NULL) {
393 if (mcspi_wait_for_reg_bit(chstat_reg,
394 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
395 dev_err(&spi->dev, "TXS timed out\n");
396 goto out;
397 }
398#ifdef VERBOSE
399 dev_dbg(&spi->dev, "write-%d %04x\n",
400 word_len, *tx);
401#endif
402 __raw_writel(*tx++, tx_reg);
403 }
404 if (rx != NULL) {
405 if (mcspi_wait_for_reg_bit(chstat_reg,
406 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
407 dev_err(&spi->dev, "RXS timed out\n");
408 goto out;
409 }
410 /* prevent last RX_ONLY read from triggering
411 * more word i/o: switch to rx+tx
412 */
413 if (c == 0 && tx == NULL)
414 mcspi_write_cs_reg(spi,
415 OMAP2_MCSPI_CHCONF0, l);
416 *rx++ = __raw_readl(rx_reg);
417#ifdef VERBOSE
418 dev_dbg(&spi->dev, "read-%d %04x\n",
419 word_len, *(rx - 1));
420#endif
421 }
422 c -= 2;
423 } while (c);
424 } else if (word_len <= 32) {
425 u32 *rx;
426 const u32 *tx;
427
428 rx = xfer->rx_buf;
429 tx = xfer->tx_buf;
430 do {
431 if (tx != NULL) {
432 if (mcspi_wait_for_reg_bit(chstat_reg,
433 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
434 dev_err(&spi->dev, "TXS timed out\n");
435 goto out;
436 }
437#ifdef VERBOSE
438 dev_dbg(&spi->dev, "write-%d %04x\n",
439 word_len, *tx);
440#endif
441 __raw_writel(*tx++, tx_reg);
442 }
443 if (rx != NULL) {
444 if (mcspi_wait_for_reg_bit(chstat_reg,
445 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
446 dev_err(&spi->dev, "RXS timed out\n");
447 goto out;
448 }
449 /* prevent last RX_ONLY read from triggering
450 * more word i/o: switch to rx+tx
451 */
452 if (c == 0 && tx == NULL)
453 mcspi_write_cs_reg(spi,
454 OMAP2_MCSPI_CHCONF0, l);
455 *rx++ = __raw_readl(rx_reg);
456#ifdef VERBOSE
457 dev_dbg(&spi->dev, "read-%d %04x\n",
458 word_len, *(rx - 1));
459#endif
460 }
461 c -= 4;
462 } while (c);
463 }
464
465 /* for TX_ONLY mode, be sure all words have shifted out */
466 if (xfer->rx_buf == NULL) {
467 if (mcspi_wait_for_reg_bit(chstat_reg,
468 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
469 dev_err(&spi->dev, "TXS timed out\n");
470 } else if (mcspi_wait_for_reg_bit(chstat_reg,
471 OMAP2_MCSPI_CHSTAT_EOT) < 0)
472 dev_err(&spi->dev, "EOT timed out\n");
473 }
474out:
475 return count - c;
476}
477
478/* called only when no transfer is active to this device */
479static int omap2_mcspi_setup_transfer(struct spi_device *spi,
480 struct spi_transfer *t)
481{
482 struct omap2_mcspi_cs *cs = spi->controller_state;
483 struct omap2_mcspi *mcspi;
484 u32 l = 0, div = 0;
485 u8 word_len = spi->bits_per_word;
486
487 mcspi = spi_master_get_devdata(spi->master);
488
489 if (t != NULL && t->bits_per_word)
490 word_len = t->bits_per_word;
491
492 cs->word_len = word_len;
493
494 if (spi->max_speed_hz) {
495 while (div <= 15 && (OMAP2_MCSPI_MAX_FREQ / (1 << div))
496 > spi->max_speed_hz)
497 div++;
498 } else
499 div = 15;
500
501 l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
502
503 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
504 * REVISIT: this controller could support SPI_3WIRE mode.
505 */
506 l &= ~(OMAP2_MCSPI_CHCONF_IS|OMAP2_MCSPI_CHCONF_DPE1);
507 l |= OMAP2_MCSPI_CHCONF_DPE0;
508
509 /* wordlength */
510 l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
511 l |= (word_len - 1) << 7;
512
513 /* set chipselect polarity; manage with FORCE */
514 if (!(spi->mode & SPI_CS_HIGH))
515 l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */
516 else
517 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
518
519 /* set clock divisor */
520 l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
521 l |= div << 2;
522
523 /* set SPI mode 0..3 */
524 if (spi->mode & SPI_CPOL)
525 l |= OMAP2_MCSPI_CHCONF_POL;
526 else
527 l &= ~OMAP2_MCSPI_CHCONF_POL;
528 if (spi->mode & SPI_CPHA)
529 l |= OMAP2_MCSPI_CHCONF_PHA;
530 else
531 l &= ~OMAP2_MCSPI_CHCONF_PHA;
532
533 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, l);
534
535 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
536 OMAP2_MCSPI_MAX_FREQ / (1 << div),
537 (spi->mode & SPI_CPHA) ? "trailing" : "leading",
538 (spi->mode & SPI_CPOL) ? "inverted" : "normal");
539
540 return 0;
541}
542
543static void omap2_mcspi_dma_rx_callback(int lch, u16 ch_status, void *data)
544{
545 struct spi_device *spi = data;
546 struct omap2_mcspi *mcspi;
547 struct omap2_mcspi_dma *mcspi_dma;
548
549 mcspi = spi_master_get_devdata(spi->master);
550 mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
551
552 complete(&mcspi_dma->dma_rx_completion);
553
554 /* We must disable the DMA RX request */
555 omap2_mcspi_set_dma_req(spi, 1, 0);
556}
557
558static void omap2_mcspi_dma_tx_callback(int lch, u16 ch_status, void *data)
559{
560 struct spi_device *spi = data;
561 struct omap2_mcspi *mcspi;
562 struct omap2_mcspi_dma *mcspi_dma;
563
564 mcspi = spi_master_get_devdata(spi->master);
565 mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
566
567 complete(&mcspi_dma->dma_tx_completion);
568
569 /* We must disable the DMA TX request */
570 omap2_mcspi_set_dma_req(spi, 0, 0);
571}
572
573static int omap2_mcspi_request_dma(struct spi_device *spi)
574{
575 struct spi_master *master = spi->master;
576 struct omap2_mcspi *mcspi;
577 struct omap2_mcspi_dma *mcspi_dma;
578
579 mcspi = spi_master_get_devdata(master);
580 mcspi_dma = mcspi->dma_channels + spi->chip_select;
581
582 if (omap_request_dma(mcspi_dma->dma_rx_sync_dev, "McSPI RX",
583 omap2_mcspi_dma_rx_callback, spi,
584 &mcspi_dma->dma_rx_channel)) {
585 dev_err(&spi->dev, "no RX DMA channel for McSPI\n");
586 return -EAGAIN;
587 }
588
589 if (omap_request_dma(mcspi_dma->dma_tx_sync_dev, "McSPI TX",
590 omap2_mcspi_dma_tx_callback, spi,
591 &mcspi_dma->dma_tx_channel)) {
592 omap_free_dma(mcspi_dma->dma_rx_channel);
593 mcspi_dma->dma_rx_channel = -1;
594 dev_err(&spi->dev, "no TX DMA channel for McSPI\n");
595 return -EAGAIN;
596 }
597
598 init_completion(&mcspi_dma->dma_rx_completion);
599 init_completion(&mcspi_dma->dma_tx_completion);
600
601 return 0;
602}
603
604/* the spi->mode bits understood by this driver: */
605#define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH)
606
607static int omap2_mcspi_setup(struct spi_device *spi)
608{
609 int ret;
610 struct omap2_mcspi *mcspi;
611 struct omap2_mcspi_dma *mcspi_dma;
612 struct omap2_mcspi_cs *cs = spi->controller_state;
613
614 if (spi->mode & ~MODEBITS) {
615 dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
616 spi->mode & ~MODEBITS);
617 return -EINVAL;
618 }
619
620 if (spi->bits_per_word == 0)
621 spi->bits_per_word = 8;
622 else if (spi->bits_per_word < 4 || spi->bits_per_word > 32) {
623 dev_dbg(&spi->dev, "setup: unsupported %d bit words\n",
624 spi->bits_per_word);
625 return -EINVAL;
626 }
627
628 mcspi = spi_master_get_devdata(spi->master);
629 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
630
631 if (!cs) {
632 cs = kzalloc(sizeof *cs, GFP_KERNEL);
633 if (!cs)
634 return -ENOMEM;
635 cs->base = mcspi->base + spi->chip_select * 0x14;
636 spi->controller_state = cs;
637 }
638
639 if (mcspi_dma->dma_rx_channel == -1
640 || mcspi_dma->dma_tx_channel == -1) {
641 ret = omap2_mcspi_request_dma(spi);
642 if (ret < 0)
643 return ret;
644 }
645
646 clk_enable(mcspi->ick);
647 clk_enable(mcspi->fck);
648 ret = omap2_mcspi_setup_transfer(spi, NULL);
649 clk_disable(mcspi->fck);
650 clk_disable(mcspi->ick);
651
652 return ret;
653}
654
655static void omap2_mcspi_cleanup(struct spi_device *spi)
656{
657 struct omap2_mcspi *mcspi;
658 struct omap2_mcspi_dma *mcspi_dma;
659
660 mcspi = spi_master_get_devdata(spi->master);
661 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
662
663 kfree(spi->controller_state);
664
665 if (mcspi_dma->dma_rx_channel != -1) {
666 omap_free_dma(mcspi_dma->dma_rx_channel);
667 mcspi_dma->dma_rx_channel = -1;
668 }
669 if (mcspi_dma->dma_tx_channel != -1) {
670 omap_free_dma(mcspi_dma->dma_tx_channel);
671 mcspi_dma->dma_tx_channel = -1;
672 }
673}
674
675static void omap2_mcspi_work(struct work_struct *work)
676{
677 struct omap2_mcspi *mcspi;
678
679 mcspi = container_of(work, struct omap2_mcspi, work);
680 spin_lock_irq(&mcspi->lock);
681
682 clk_enable(mcspi->ick);
683 clk_enable(mcspi->fck);
684
685 /* We only enable one channel at a time -- the one whose message is
686 * at the head of the queue -- although this controller would gladly
687 * arbitrate among multiple channels. This corresponds to "single
688 * channel" master mode. As a side effect, we need to manage the
689 * chipselect with the FORCE bit ... CS != channel enable.
690 */
691 while (!list_empty(&mcspi->msg_queue)) {
692 struct spi_message *m;
693 struct spi_device *spi;
694 struct spi_transfer *t = NULL;
695 int cs_active = 0;
696 struct omap2_mcspi_device_config *conf;
697 struct omap2_mcspi_cs *cs;
698 int par_override = 0;
699 int status = 0;
700 u32 chconf;
701
702 m = container_of(mcspi->msg_queue.next, struct spi_message,
703 queue);
704
705 list_del_init(&m->queue);
706 spin_unlock_irq(&mcspi->lock);
707
708 spi = m->spi;
709 conf = spi->controller_data;
710 cs = spi->controller_state;
711
712 omap2_mcspi_set_enable(spi, 1);
713 list_for_each_entry(t, &m->transfers, transfer_list) {
714 if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
715 status = -EINVAL;
716 break;
717 }
718 if (par_override || t->speed_hz || t->bits_per_word) {
719 par_override = 1;
720 status = omap2_mcspi_setup_transfer(spi, t);
721 if (status < 0)
722 break;
723 if (!t->speed_hz && !t->bits_per_word)
724 par_override = 0;
725 }
726
727 if (!cs_active) {
728 omap2_mcspi_force_cs(spi, 1);
729 cs_active = 1;
730 }
731
732 chconf = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
733 chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
734 if (t->tx_buf == NULL)
735 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
736 else if (t->rx_buf == NULL)
737 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
738 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, chconf);
739
740 if (t->len) {
741 unsigned count;
742
743 /* RX_ONLY mode needs dummy data in TX reg */
744 if (t->tx_buf == NULL)
745 __raw_writel(0, cs->base
746 + OMAP2_MCSPI_TX0);
747
748 if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)
749 count = omap2_mcspi_txrx_dma(spi, t);
750 else
751 count = omap2_mcspi_txrx_pio(spi, t);
752 m->actual_length += count;
753
754 if (count != t->len) {
755 status = -EIO;
756 break;
757 }
758 }
759
760 if (t->delay_usecs)
761 udelay(t->delay_usecs);
762
763 /* ignore the "leave it on after last xfer" hint */
764 if (t->cs_change) {
765 omap2_mcspi_force_cs(spi, 0);
766 cs_active = 0;
767 }
768 }
769
770 /* Restore defaults if they were overriden */
771 if (par_override) {
772 par_override = 0;
773 status = omap2_mcspi_setup_transfer(spi, NULL);
774 }
775
776 if (cs_active)
777 omap2_mcspi_force_cs(spi, 0);
778
779 omap2_mcspi_set_enable(spi, 0);
780
781 m->status = status;
782 m->complete(m->context);
783
784 spin_lock_irq(&mcspi->lock);
785 }
786
787 clk_disable(mcspi->fck);
788 clk_disable(mcspi->ick);
789
790 spin_unlock_irq(&mcspi->lock);
791}
792
793static int omap2_mcspi_transfer(struct spi_device *spi, struct spi_message *m)
794{
795 struct omap2_mcspi *mcspi;
796 unsigned long flags;
797 struct spi_transfer *t;
798
799 m->actual_length = 0;
800 m->status = 0;
801
802 /* reject invalid messages and transfers */
803 if (list_empty(&m->transfers) || !m->complete)
804 return -EINVAL;
805 list_for_each_entry(t, &m->transfers, transfer_list) {
806 const void *tx_buf = t->tx_buf;
807 void *rx_buf = t->rx_buf;
808 unsigned len = t->len;
809
810 if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ
811 || (len && !(rx_buf || tx_buf))
812 || (t->bits_per_word &&
813 ( t->bits_per_word < 4
814 || t->bits_per_word > 32))) {
815 dev_dbg(&spi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
816 t->speed_hz,
817 len,
818 tx_buf ? "tx" : "",
819 rx_buf ? "rx" : "",
820 t->bits_per_word);
821 return -EINVAL;
822 }
823 if (t->speed_hz && t->speed_hz < OMAP2_MCSPI_MAX_FREQ/(1<<16)) {
824 dev_dbg(&spi->dev, "%d Hz max exceeds %d\n",
825 t->speed_hz,
826 OMAP2_MCSPI_MAX_FREQ/(1<<16));
827 return -EINVAL;
828 }
829
830 if (m->is_dma_mapped || len < DMA_MIN_BYTES)
831 continue;
832
833 /* Do DMA mapping "early" for better error reporting and
834 * dcache use. Note that if dma_unmap_single() ever starts
835 * to do real work on ARM, we'd need to clean up mappings
836 * for previous transfers on *ALL* exits of this loop...
837 */
838 if (tx_buf != NULL) {
839 t->tx_dma = dma_map_single(&spi->dev, (void *) tx_buf,
840 len, DMA_TO_DEVICE);
841 if (dma_mapping_error(t->tx_dma)) {
842 dev_dbg(&spi->dev, "dma %cX %d bytes error\n",
843 'T', len);
844 return -EINVAL;
845 }
846 }
847 if (rx_buf != NULL) {
848 t->rx_dma = dma_map_single(&spi->dev, rx_buf, t->len,
849 DMA_FROM_DEVICE);
850 if (dma_mapping_error(t->rx_dma)) {
851 dev_dbg(&spi->dev, "dma %cX %d bytes error\n",
852 'R', len);
853 if (tx_buf != NULL)
854 dma_unmap_single(NULL, t->tx_dma,
855 len, DMA_TO_DEVICE);
856 return -EINVAL;
857 }
858 }
859 }
860
861 mcspi = spi_master_get_devdata(spi->master);
862
863 spin_lock_irqsave(&mcspi->lock, flags);
864 list_add_tail(&m->queue, &mcspi->msg_queue);
865 queue_work(omap2_mcspi_wq, &mcspi->work);
866 spin_unlock_irqrestore(&mcspi->lock, flags);
867
868 return 0;
869}
870
871static int __init omap2_mcspi_reset(struct omap2_mcspi *mcspi)
872{
873 struct spi_master *master = mcspi->master;
874 u32 tmp;
875
876 clk_enable(mcspi->ick);
877 clk_enable(mcspi->fck);
878
879 mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG,
880 OMAP2_MCSPI_SYSCONFIG_SOFTRESET);
881 do {
882 tmp = mcspi_read_reg(master, OMAP2_MCSPI_SYSSTATUS);
883 } while (!(tmp & OMAP2_MCSPI_SYSSTATUS_RESETDONE));
884
885 mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG,
886 /* (3 << 8) | (2 << 3) | */
887 OMAP2_MCSPI_SYSCONFIG_AUTOIDLE);
888
889 omap2_mcspi_set_master_mode(master);
890
891 clk_disable(mcspi->fck);
892 clk_disable(mcspi->ick);
893 return 0;
894}
895
896static u8 __initdata spi1_rxdma_id [] = {
897 OMAP24XX_DMA_SPI1_RX0,
898 OMAP24XX_DMA_SPI1_RX1,
899 OMAP24XX_DMA_SPI1_RX2,
900 OMAP24XX_DMA_SPI1_RX3,
901};
902
903static u8 __initdata spi1_txdma_id [] = {
904 OMAP24XX_DMA_SPI1_TX0,
905 OMAP24XX_DMA_SPI1_TX1,
906 OMAP24XX_DMA_SPI1_TX2,
907 OMAP24XX_DMA_SPI1_TX3,
908};
909
910static u8 __initdata spi2_rxdma_id[] = {
911 OMAP24XX_DMA_SPI2_RX0,
912 OMAP24XX_DMA_SPI2_RX1,
913};
914
915static u8 __initdata spi2_txdma_id[] = {
916 OMAP24XX_DMA_SPI2_TX0,
917 OMAP24XX_DMA_SPI2_TX1,
918};
919
920static int __init omap2_mcspi_probe(struct platform_device *pdev)
921{
922 struct spi_master *master;
923 struct omap2_mcspi *mcspi;
924 struct resource *r;
925 int status = 0, i;
926 const u8 *rxdma_id, *txdma_id;
927 unsigned num_chipselect;
928
929 switch (pdev->id) {
930 case 1:
931 rxdma_id = spi1_rxdma_id;
932 txdma_id = spi1_txdma_id;
933 num_chipselect = 4;
934 break;
935 case 2:
936 rxdma_id = spi2_rxdma_id;
937 txdma_id = spi2_txdma_id;
938 num_chipselect = 2;
939 break;
940 /* REVISIT omap2430 has a third McSPI ... */
941 default:
942 return -EINVAL;
943 }
944
945 master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
946 if (master == NULL) {
947 dev_dbg(&pdev->dev, "master allocation failed\n");
948 return -ENOMEM;
949 }
950
951 if (pdev->id != -1)
952 master->bus_num = pdev->id;
953
954 master->setup = omap2_mcspi_setup;
955 master->transfer = omap2_mcspi_transfer;
956 master->cleanup = omap2_mcspi_cleanup;
957 master->num_chipselect = num_chipselect;
958
959 dev_set_drvdata(&pdev->dev, master);
960
961 mcspi = spi_master_get_devdata(master);
962 mcspi->master = master;
963
964 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
965 if (r == NULL) {
966 status = -ENODEV;
967 goto err1;
968 }
969 if (!request_mem_region(r->start, (r->end - r->start) + 1,
970 pdev->dev.bus_id)) {
971 status = -EBUSY;
972 goto err1;
973 }
974
975 mcspi->base = (void __iomem *) io_p2v(r->start);
976
977 INIT_WORK(&mcspi->work, omap2_mcspi_work);
978
979 spin_lock_init(&mcspi->lock);
980 INIT_LIST_HEAD(&mcspi->msg_queue);
981
982 mcspi->ick = clk_get(&pdev->dev, "mcspi_ick");
983 if (IS_ERR(mcspi->ick)) {
984 dev_dbg(&pdev->dev, "can't get mcspi_ick\n");
985 status = PTR_ERR(mcspi->ick);
986 goto err1a;
987 }
988 mcspi->fck = clk_get(&pdev->dev, "mcspi_fck");
989 if (IS_ERR(mcspi->fck)) {
990 dev_dbg(&pdev->dev, "can't get mcspi_fck\n");
991 status = PTR_ERR(mcspi->fck);
992 goto err2;
993 }
994
995 mcspi->dma_channels = kcalloc(master->num_chipselect,
996 sizeof(struct omap2_mcspi_dma),
997 GFP_KERNEL);
998
999 if (mcspi->dma_channels == NULL)
1000 goto err3;
1001
1002 for (i = 0; i < num_chipselect; i++) {
1003 mcspi->dma_channels[i].dma_rx_channel = -1;
1004 mcspi->dma_channels[i].dma_rx_sync_dev = rxdma_id[i];
1005 mcspi->dma_channels[i].dma_tx_channel = -1;
1006 mcspi->dma_channels[i].dma_tx_sync_dev = txdma_id[i];
1007 }
1008
1009 if (omap2_mcspi_reset(mcspi) < 0)
1010 goto err4;
1011
1012 status = spi_register_master(master);
1013 if (status < 0)
1014 goto err4;
1015
1016 return status;
1017
1018err4:
1019 kfree(mcspi->dma_channels);
1020err3:
1021 clk_put(mcspi->fck);
1022err2:
1023 clk_put(mcspi->ick);
1024err1a:
1025 release_mem_region(r->start, (r->end - r->start) + 1);
1026err1:
1027 spi_master_put(master);
1028 return status;
1029}
1030
1031static int __exit omap2_mcspi_remove(struct platform_device *pdev)
1032{
1033 struct spi_master *master;
1034 struct omap2_mcspi *mcspi;
1035 struct omap2_mcspi_dma *dma_channels;
1036 struct resource *r;
1037
1038 master = dev_get_drvdata(&pdev->dev);
1039 mcspi = spi_master_get_devdata(master);
1040 dma_channels = mcspi->dma_channels;
1041
1042 clk_put(mcspi->fck);
1043 clk_put(mcspi->ick);
1044
1045 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1046 release_mem_region(r->start, (r->end - r->start) + 1);
1047
1048 spi_unregister_master(master);
1049 kfree(dma_channels);
1050
1051 return 0;
1052}
1053
1054static struct platform_driver omap2_mcspi_driver = {
1055 .driver = {
1056 .name = "omap2_mcspi",
1057 .owner = THIS_MODULE,
1058 },
1059 .remove = __exit_p(omap2_mcspi_remove),
1060};
1061
1062
1063static int __init omap2_mcspi_init(void)
1064{
1065 omap2_mcspi_wq = create_singlethread_workqueue(
1066 omap2_mcspi_driver.driver.name);
1067 if (omap2_mcspi_wq == NULL)
1068 return -1;
1069 return platform_driver_probe(&omap2_mcspi_driver, omap2_mcspi_probe);
1070}
1071subsys_initcall(omap2_mcspi_init);
1072
1073static void __exit omap2_mcspi_exit(void)
1074{
1075 platform_driver_unregister(&omap2_mcspi_driver);
1076
1077 destroy_workqueue(omap2_mcspi_wq);
1078}
1079module_exit(omap2_mcspi_exit);
1080
1081MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-08 06:43:33 -0500