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-rw-r--r--drivers/spi/Kconfig17
-rw-r--r--drivers/spi/Makefile1
-rw-r--r--drivers/spi/spi-au1550.c2
-rw-r--r--drivers/spi/spi-bcm53xx.c299
-rw-r--r--drivers/spi/spi-bcm53xx.h72
-rw-r--r--drivers/spi/spi-cadence.c1
-rw-r--r--drivers/spi/spi-clps711x.c34
-rw-r--r--drivers/spi/spi-davinci.c108
-rw-r--r--drivers/spi/spi-dw-mid.c65
-rw-r--r--drivers/spi/spi-dw-pci.c69
-rw-r--r--drivers/spi/spi-dw.c78
-rw-r--r--drivers/spi/spi-dw.h11
-rw-r--r--drivers/spi/spi-ep93xx.c1
-rw-r--r--drivers/spi/spi-fsl-cpm.c14
-rw-r--r--drivers/spi/spi-fsl-dspi.c22
-rw-r--r--drivers/spi/spi-fsl-espi.c27
-rw-r--r--drivers/spi/spi-fsl-lib.c6
-rw-r--r--drivers/spi/spi-fsl-spi.c32
-rw-r--r--drivers/spi/spi-imx.c286
-rw-r--r--drivers/spi/spi-mxs.c4
-rw-r--r--drivers/spi/spi-omap-100k.c4
-rw-r--r--drivers/spi/spi-omap2-mcspi.c3
-rw-r--r--drivers/spi/spi-orion.c121
-rw-r--r--drivers/spi/spi-pl022.c2
-rw-r--r--drivers/spi/spi-pxa2xx.c1
-rw-r--r--drivers/spi/spi-rockchip.c24
-rw-r--r--drivers/spi/spi-rspi.c94
-rw-r--r--drivers/spi/spi-sh-msiof.c71
-rw-r--r--drivers/spi/spi-sirf.c5
-rw-r--r--drivers/spi/spi-tegra114.c9
-rw-r--r--drivers/spi/spi-tegra20-sflash.c3
-rw-r--r--drivers/spi/spi-txx9.c2
-rw-r--r--drivers/spi/spi-xtensa-xtfpga.c1
-rw-r--r--drivers/spi/spi.c46
34 files changed, 1181 insertions, 354 deletions
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 62e2242ad7e0..c4f19887987b 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -69,6 +69,7 @@ config SPI_ATH79
69 69
70config SPI_ATMEL 70config SPI_ATMEL
71 tristate "Atmel SPI Controller" 71 tristate "Atmel SPI Controller"
72 depends on HAS_DMA
72 depends on (ARCH_AT91 || AVR32 || COMPILE_TEST) 73 depends on (ARCH_AT91 || AVR32 || COMPILE_TEST)
73 help 74 help
74 This selects a driver for the Atmel SPI Controller, present on 75 This selects a driver for the Atmel SPI Controller, present on
@@ -112,6 +113,14 @@ config SPI_AU1550
112 If you say yes to this option, support will be included for the 113 If you say yes to this option, support will be included for the
113 PSC SPI controller found on Au1550, Au1200 and Au1300 series. 114 PSC SPI controller found on Au1550, Au1200 and Au1300 series.
114 115
116config SPI_BCM53XX
117 tristate "Broadcom BCM53xx SPI controller"
118 depends on ARCH_BCM_5301X
119 depends on BCMA_POSSIBLE
120 select BCMA
121 help
122 Enable support for the SPI controller on Broadcom BCM53xx ARM SoCs.
123
115config SPI_BCM63XX 124config SPI_BCM63XX
116 tristate "Broadcom BCM63xx SPI controller" 125 tristate "Broadcom BCM63xx SPI controller"
117 depends on BCM63XX 126 depends on BCM63XX
@@ -185,6 +194,7 @@ config SPI_EFM32
185 194
186config SPI_EP93XX 195config SPI_EP93XX
187 tristate "Cirrus Logic EP93xx SPI controller" 196 tristate "Cirrus Logic EP93xx SPI controller"
197 depends on HAS_DMA
188 depends on ARCH_EP93XX || COMPILE_TEST 198 depends on ARCH_EP93XX || COMPILE_TEST
189 help 199 help
190 This enables using the Cirrus EP93xx SPI controller in master 200 This enables using the Cirrus EP93xx SPI controller in master
@@ -314,6 +324,7 @@ config SPI_OMAP_UWIRE
314 324
315config SPI_OMAP24XX 325config SPI_OMAP24XX
316 tristate "McSPI driver for OMAP" 326 tristate "McSPI driver for OMAP"
327 depends on HAS_DMA
317 depends on ARM || ARM64 || AVR32 || HEXAGON || MIPS || SUPERH 328 depends on ARM || ARM64 || AVR32 || HEXAGON || MIPS || SUPERH
318 depends on ARCH_OMAP2PLUS || COMPILE_TEST 329 depends on ARCH_OMAP2PLUS || COMPILE_TEST
319 help 330 help
@@ -500,7 +511,7 @@ config SPI_MXS
500config SPI_TEGRA114 511config SPI_TEGRA114
501 tristate "NVIDIA Tegra114 SPI Controller" 512 tristate "NVIDIA Tegra114 SPI Controller"
502 depends on (ARCH_TEGRA && TEGRA20_APB_DMA) || COMPILE_TEST 513 depends on (ARCH_TEGRA && TEGRA20_APB_DMA) || COMPILE_TEST
503 depends on RESET_CONTROLLER 514 depends on RESET_CONTROLLER && HAS_DMA
504 help 515 help
505 SPI driver for NVIDIA Tegra114 SPI Controller interface. This controller 516 SPI driver for NVIDIA Tegra114 SPI Controller interface. This controller
506 is different than the older SoCs SPI controller and also register interface 517 is different than the older SoCs SPI controller and also register interface
@@ -518,7 +529,7 @@ config SPI_TEGRA20_SFLASH
518config SPI_TEGRA20_SLINK 529config SPI_TEGRA20_SLINK
519 tristate "Nvidia Tegra20/Tegra30 SLINK Controller" 530 tristate "Nvidia Tegra20/Tegra30 SLINK Controller"
520 depends on (ARCH_TEGRA && TEGRA20_APB_DMA) || COMPILE_TEST 531 depends on (ARCH_TEGRA && TEGRA20_APB_DMA) || COMPILE_TEST
521 depends on RESET_CONTROLLER 532 depends on RESET_CONTROLLER && HAS_DMA
522 help 533 help
523 SPI driver for Nvidia Tegra20/Tegra30 SLINK Controller interface. 534 SPI driver for Nvidia Tegra20/Tegra30 SLINK Controller interface.
524 535
@@ -591,7 +602,7 @@ config SPI_DW_PCI
591 depends on SPI_DESIGNWARE && PCI 602 depends on SPI_DESIGNWARE && PCI
592 603
593config SPI_DW_MID_DMA 604config SPI_DW_MID_DMA
594 bool "DMA support for DW SPI controller on Intel Moorestown platform" 605 bool "DMA support for DW SPI controller on Intel MID platform"
595 depends on SPI_DW_PCI && INTEL_MID_DMAC 606 depends on SPI_DW_PCI && INTEL_MID_DMAC
596 607
597config SPI_DW_MMIO 608config SPI_DW_MMIO
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 762da0741148..78f24ca36fcf 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_SPI_ATMEL) += spi-atmel.o
15obj-$(CONFIG_SPI_ATH79) += spi-ath79.o 15obj-$(CONFIG_SPI_ATH79) += spi-ath79.o
16obj-$(CONFIG_SPI_AU1550) += spi-au1550.o 16obj-$(CONFIG_SPI_AU1550) += spi-au1550.o
17obj-$(CONFIG_SPI_BCM2835) += spi-bcm2835.o 17obj-$(CONFIG_SPI_BCM2835) += spi-bcm2835.o
18obj-$(CONFIG_SPI_BCM53XX) += spi-bcm53xx.o
18obj-$(CONFIG_SPI_BCM63XX) += spi-bcm63xx.o 19obj-$(CONFIG_SPI_BCM63XX) += spi-bcm63xx.o
19obj-$(CONFIG_SPI_BCM63XX_HSSPI) += spi-bcm63xx-hsspi.o 20obj-$(CONFIG_SPI_BCM63XX_HSSPI) += spi-bcm63xx-hsspi.o
20obj-$(CONFIG_SPI_BFIN5XX) += spi-bfin5xx.o 21obj-$(CONFIG_SPI_BFIN5XX) += spi-bfin5xx.o
diff --git a/drivers/spi/spi-au1550.c b/drivers/spi/spi-au1550.c
index 40c3d43c9292..f40b34cdf2fc 100644
--- a/drivers/spi/spi-au1550.c
+++ b/drivers/spi/spi-au1550.c
@@ -945,7 +945,7 @@ static int au1550_spi_remove(struct platform_device *pdev)
945 spi_bitbang_stop(&hw->bitbang); 945 spi_bitbang_stop(&hw->bitbang);
946 free_irq(hw->irq, hw); 946 free_irq(hw->irq, hw);
947 iounmap((void __iomem *)hw->regs); 947 iounmap((void __iomem *)hw->regs);
948 release_mem_region(r->start, sizeof(psc_spi_t)); 948 release_mem_region(hw->ioarea->start, sizeof(psc_spi_t));
949 949
950 if (hw->usedma) { 950 if (hw->usedma) {
951 au1550_spi_dma_rxtmp_free(hw); 951 au1550_spi_dma_rxtmp_free(hw);
diff --git a/drivers/spi/spi-bcm53xx.c b/drivers/spi/spi-bcm53xx.c
new file mode 100644
index 000000000000..17b34cbadc03
--- /dev/null
+++ b/drivers/spi/spi-bcm53xx.c
@@ -0,0 +1,299 @@
1#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
2
3#include <linux/kernel.h>
4#include <linux/module.h>
5#include <linux/slab.h>
6#include <linux/delay.h>
7#include <linux/bcma/bcma.h>
8#include <linux/spi/spi.h>
9
10#include "spi-bcm53xx.h"
11
12#define BCM53XXSPI_MAX_SPI_BAUD 13500000 /* 216 MHz? */
13
14/* The longest observed required wait was 19 ms */
15#define BCM53XXSPI_SPE_TIMEOUT_MS 80
16
17struct bcm53xxspi {
18 struct bcma_device *core;
19 struct spi_master *master;
20
21 size_t read_offset;
22};
23
24static inline u32 bcm53xxspi_read(struct bcm53xxspi *b53spi, u16 offset)
25{
26 return bcma_read32(b53spi->core, offset);
27}
28
29static inline void bcm53xxspi_write(struct bcm53xxspi *b53spi, u16 offset,
30 u32 value)
31{
32 bcma_write32(b53spi->core, offset, value);
33}
34
35static inline unsigned int bcm53xxspi_calc_timeout(size_t len)
36{
37 /* Do some magic calculation based on length and buad. Add 10% and 1. */
38 return (len * 9000 / BCM53XXSPI_MAX_SPI_BAUD * 110 / 100) + 1;
39}
40
41static int bcm53xxspi_wait(struct bcm53xxspi *b53spi, unsigned int timeout_ms)
42{
43 unsigned long deadline;
44 u32 tmp;
45
46 /* SPE bit has to be 0 before we read MSPI STATUS */
47 deadline = jiffies + BCM53XXSPI_SPE_TIMEOUT_MS * HZ / 1000;
48 do {
49 tmp = bcm53xxspi_read(b53spi, B53SPI_MSPI_SPCR2);
50 if (!(tmp & B53SPI_MSPI_SPCR2_SPE))
51 break;
52 udelay(5);
53 } while (!time_after_eq(jiffies, deadline));
54
55 if (tmp & B53SPI_MSPI_SPCR2_SPE)
56 goto spi_timeout;
57
58 /* Check status */
59 deadline = jiffies + timeout_ms * HZ / 1000;
60 do {
61 tmp = bcm53xxspi_read(b53spi, B53SPI_MSPI_MSPI_STATUS);
62 if (tmp & B53SPI_MSPI_MSPI_STATUS_SPIF) {
63 bcm53xxspi_write(b53spi, B53SPI_MSPI_MSPI_STATUS, 0);
64 return 0;
65 }
66
67 cpu_relax();
68 udelay(100);
69 } while (!time_after_eq(jiffies, deadline));
70
71spi_timeout:
72 bcm53xxspi_write(b53spi, B53SPI_MSPI_MSPI_STATUS, 0);
73
74 pr_err("Timeout waiting for SPI to be ready!\n");
75
76 return -EBUSY;
77}
78
79static void bcm53xxspi_buf_write(struct bcm53xxspi *b53spi, u8 *w_buf,
80 size_t len, bool cont)
81{
82 u32 tmp;
83 int i;
84
85 for (i = 0; i < len; i++) {
86 /* Transmit Register File MSB */
87 bcm53xxspi_write(b53spi, B53SPI_MSPI_TXRAM + 4 * (i * 2),
88 (unsigned int)w_buf[i]);
89 }
90
91 for (i = 0; i < len; i++) {
92 tmp = B53SPI_CDRAM_CONT | B53SPI_CDRAM_PCS_DISABLE_ALL |
93 B53SPI_CDRAM_PCS_DSCK;
94 if (!cont && i == len - 1)
95 tmp &= ~B53SPI_CDRAM_CONT;
96 tmp &= ~0x1;
97 /* Command Register File */
98 bcm53xxspi_write(b53spi, B53SPI_MSPI_CDRAM + 4 * i, tmp);
99 }
100
101 /* Set queue pointers */
102 bcm53xxspi_write(b53spi, B53SPI_MSPI_NEWQP, 0);
103 bcm53xxspi_write(b53spi, B53SPI_MSPI_ENDQP, len - 1);
104
105 if (cont)
106 bcm53xxspi_write(b53spi, B53SPI_MSPI_WRITE_LOCK, 1);
107
108 /* Start SPI transfer */
109 tmp = bcm53xxspi_read(b53spi, B53SPI_MSPI_SPCR2);
110 tmp |= B53SPI_MSPI_SPCR2_SPE;
111 if (cont)
112 tmp |= B53SPI_MSPI_SPCR2_CONT_AFTER_CMD;
113 bcm53xxspi_write(b53spi, B53SPI_MSPI_SPCR2, tmp);
114
115 /* Wait for SPI to finish */
116 bcm53xxspi_wait(b53spi, bcm53xxspi_calc_timeout(len));
117
118 if (!cont)
119 bcm53xxspi_write(b53spi, B53SPI_MSPI_WRITE_LOCK, 0);
120
121 b53spi->read_offset = len;
122}
123
124static void bcm53xxspi_buf_read(struct bcm53xxspi *b53spi, u8 *r_buf,
125 size_t len, bool cont)
126{
127 u32 tmp;
128 int i;
129
130 for (i = 0; i < b53spi->read_offset + len; i++) {
131 tmp = B53SPI_CDRAM_CONT | B53SPI_CDRAM_PCS_DISABLE_ALL |
132 B53SPI_CDRAM_PCS_DSCK;
133 if (!cont && i == b53spi->read_offset + len - 1)
134 tmp &= ~B53SPI_CDRAM_CONT;
135 tmp &= ~0x1;
136 /* Command Register File */
137 bcm53xxspi_write(b53spi, B53SPI_MSPI_CDRAM + 4 * i, tmp);
138 }
139
140 /* Set queue pointers */
141 bcm53xxspi_write(b53spi, B53SPI_MSPI_NEWQP, 0);
142 bcm53xxspi_write(b53spi, B53SPI_MSPI_ENDQP,
143 b53spi->read_offset + len - 1);
144
145 if (cont)
146 bcm53xxspi_write(b53spi, B53SPI_MSPI_WRITE_LOCK, 1);
147
148 /* Start SPI transfer */
149 tmp = bcm53xxspi_read(b53spi, B53SPI_MSPI_SPCR2);
150 tmp |= B53SPI_MSPI_SPCR2_SPE;
151 if (cont)
152 tmp |= B53SPI_MSPI_SPCR2_CONT_AFTER_CMD;
153 bcm53xxspi_write(b53spi, B53SPI_MSPI_SPCR2, tmp);
154
155 /* Wait for SPI to finish */
156 bcm53xxspi_wait(b53spi, bcm53xxspi_calc_timeout(len));
157
158 if (!cont)
159 bcm53xxspi_write(b53spi, B53SPI_MSPI_WRITE_LOCK, 0);
160
161 for (i = 0; i < len; ++i) {
162 int offset = b53spi->read_offset + i;
163
164 /* Data stored in the transmit register file LSB */
165 r_buf[i] = (u8)bcm53xxspi_read(b53spi, B53SPI_MSPI_RXRAM + 4 * (1 + offset * 2));
166 }
167
168 b53spi->read_offset = 0;
169}
170
171static int bcm53xxspi_transfer_one(struct spi_master *master,
172 struct spi_device *spi,
173 struct spi_transfer *t)
174{
175 struct bcm53xxspi *b53spi = spi_master_get_devdata(master);
176 u8 *buf;
177 size_t left;
178
179 if (t->tx_buf) {
180 buf = (u8 *)t->tx_buf;
181 left = t->len;
182 while (left) {
183 size_t to_write = min_t(size_t, 16, left);
184 bool cont = left - to_write > 0;
185
186 bcm53xxspi_buf_write(b53spi, buf, to_write, cont);
187 left -= to_write;
188 buf += to_write;
189 }
190 }
191
192 if (t->rx_buf) {
193 buf = (u8 *)t->rx_buf;
194 left = t->len;
195 while (left) {
196 size_t to_read = min_t(size_t, 16 - b53spi->read_offset,
197 left);
198 bool cont = left - to_read > 0;
199
200 bcm53xxspi_buf_read(b53spi, buf, to_read, cont);
201 left -= to_read;
202 buf += to_read;
203 }
204 }
205
206 return 0;
207}
208
209/**************************************************
210 * BCMA
211 **************************************************/
212
213static struct spi_board_info bcm53xx_info = {
214 .modalias = "bcm53xxspiflash",
215};
216
217static const struct bcma_device_id bcm53xxspi_bcma_tbl[] = {
218 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_NS_QSPI, BCMA_ANY_REV, BCMA_ANY_CLASS),
219 BCMA_CORETABLE_END
220};
221MODULE_DEVICE_TABLE(bcma, bcm53xxspi_bcma_tbl);
222
223static int bcm53xxspi_bcma_probe(struct bcma_device *core)
224{
225 struct bcm53xxspi *b53spi;
226 struct spi_master *master;
227 int err;
228
229 if (core->bus->drv_cc.core->id.rev != 42) {
230 pr_err("SPI on SoC with unsupported ChipCommon rev\n");
231 return -ENOTSUPP;
232 }
233
234 master = spi_alloc_master(&core->dev, sizeof(*b53spi));
235 if (!master)
236 return -ENOMEM;
237
238 b53spi = spi_master_get_devdata(master);
239 b53spi->master = master;
240 b53spi->core = core;
241
242 master->transfer_one = bcm53xxspi_transfer_one;
243
244 bcma_set_drvdata(core, b53spi);
245
246 err = devm_spi_register_master(&core->dev, master);
247 if (err) {
248 spi_master_put(master);
249 bcma_set_drvdata(core, NULL);
250 goto out;
251 }
252
253 /* Broadcom SoCs (at least with the CC rev 42) use SPI for flash only */
254 spi_new_device(master, &bcm53xx_info);
255
256out:
257 return err;
258}
259
260static void bcm53xxspi_bcma_remove(struct bcma_device *core)
261{
262 struct bcm53xxspi *b53spi = bcma_get_drvdata(core);
263
264 spi_unregister_master(b53spi->master);
265}
266
267static struct bcma_driver bcm53xxspi_bcma_driver = {
268 .name = KBUILD_MODNAME,
269 .id_table = bcm53xxspi_bcma_tbl,
270 .probe = bcm53xxspi_bcma_probe,
271 .remove = bcm53xxspi_bcma_remove,
272};
273
274/**************************************************
275 * Init & exit
276 **************************************************/
277
278static int __init bcm53xxspi_module_init(void)
279{
280 int err = 0;
281
282 err = bcma_driver_register(&bcm53xxspi_bcma_driver);
283 if (err)
284 pr_err("Failed to register bcma driver: %d\n", err);
285
286 return err;
287}
288
289static void __exit bcm53xxspi_module_exit(void)
290{
291 bcma_driver_unregister(&bcm53xxspi_bcma_driver);
292}
293
294module_init(bcm53xxspi_module_init);
295module_exit(bcm53xxspi_module_exit);
296
297MODULE_DESCRIPTION("Broadcom BCM53xx SPI Controller driver");
298MODULE_AUTHOR("Rafał Miłecki <zajec5@gmail.com>");
299MODULE_LICENSE("GPL");
diff --git a/drivers/spi/spi-bcm53xx.h b/drivers/spi/spi-bcm53xx.h
new file mode 100644
index 000000000000..73575dfe6916
--- /dev/null
+++ b/drivers/spi/spi-bcm53xx.h
@@ -0,0 +1,72 @@
1#ifndef SPI_BCM53XX_H
2#define SPI_BCM53XX_H
3
4#define B53SPI_BSPI_REVISION_ID 0x000
5#define B53SPI_BSPI_SCRATCH 0x004
6#define B53SPI_BSPI_MAST_N_BOOT_CTRL 0x008
7#define B53SPI_BSPI_BUSY_STATUS 0x00c
8#define B53SPI_BSPI_INTR_STATUS 0x010
9#define B53SPI_BSPI_B0_STATUS 0x014
10#define B53SPI_BSPI_B0_CTRL 0x018
11#define B53SPI_BSPI_B1_STATUS 0x01c
12#define B53SPI_BSPI_B1_CTRL 0x020
13#define B53SPI_BSPI_STRAP_OVERRIDE_CTRL 0x024
14#define B53SPI_BSPI_FLEX_MODE_ENABLE 0x028
15#define B53SPI_BSPI_BITS_PER_CYCLE 0x02c
16#define B53SPI_BSPI_BITS_PER_PHASE 0x030
17#define B53SPI_BSPI_CMD_AND_MODE_BYTE 0x034
18#define B53SPI_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE 0x038
19#define B53SPI_BSPI_BSPI_XOR_VALUE 0x03c
20#define B53SPI_BSPI_BSPI_XOR_ENABLE 0x040
21#define B53SPI_BSPI_BSPI_PIO_MODE_ENABLE 0x044
22#define B53SPI_BSPI_BSPI_PIO_IODIR 0x048
23#define B53SPI_BSPI_BSPI_PIO_DATA 0x04c
24
25/* RAF */
26#define B53SPI_RAF_START_ADDR 0x100
27#define B53SPI_RAF_NUM_WORDS 0x104
28#define B53SPI_RAF_CTRL 0x108
29#define B53SPI_RAF_FULLNESS 0x10c
30#define B53SPI_RAF_WATERMARK 0x110
31#define B53SPI_RAF_STATUS 0x114
32#define B53SPI_RAF_READ_DATA 0x118
33#define B53SPI_RAF_WORD_CNT 0x11c
34#define B53SPI_RAF_CURR_ADDR 0x120
35
36/* MSPI */
37#define B53SPI_MSPI_SPCR0_LSB 0x200
38#define B53SPI_MSPI_SPCR0_MSB 0x204
39#define B53SPI_MSPI_SPCR1_LSB 0x208
40#define B53SPI_MSPI_SPCR1_MSB 0x20c
41#define B53SPI_MSPI_NEWQP 0x210
42#define B53SPI_MSPI_ENDQP 0x214
43#define B53SPI_MSPI_SPCR2 0x218
44#define B53SPI_MSPI_SPCR2_SPE 0x00000040
45#define B53SPI_MSPI_SPCR2_CONT_AFTER_CMD 0x00000080
46#define B53SPI_MSPI_MSPI_STATUS 0x220
47#define B53SPI_MSPI_MSPI_STATUS_SPIF 0x00000001
48#define B53SPI_MSPI_CPTQP 0x224
49#define B53SPI_MSPI_TXRAM 0x240 /* 32 registers, up to 0x2b8 */
50#define B53SPI_MSPI_RXRAM 0x2c0 /* 32 registers, up to 0x33c */
51#define B53SPI_MSPI_CDRAM 0x340 /* 16 registers, up to 0x37c */
52#define B53SPI_CDRAM_PCS_PCS0 0x00000001
53#define B53SPI_CDRAM_PCS_PCS1 0x00000002
54#define B53SPI_CDRAM_PCS_PCS2 0x00000004
55#define B53SPI_CDRAM_PCS_PCS3 0x00000008
56#define B53SPI_CDRAM_PCS_DISABLE_ALL 0x0000000f
57#define B53SPI_CDRAM_PCS_DSCK 0x00000010
58#define B53SPI_CDRAM_BITSE 0x00000040
59#define B53SPI_CDRAM_CONT 0x00000080
60#define B53SPI_MSPI_WRITE_LOCK 0x380
61#define B53SPI_MSPI_DISABLE_FLUSH_GEN 0x384
62
63/* Interrupt */
64#define B53SPI_INTR_RAF_LR_FULLNESS_REACHED 0x3a0
65#define B53SPI_INTR_RAF_LR_TRUNCATED 0x3a4
66#define B53SPI_INTR_RAF_LR_IMPATIENT 0x3a8
67#define B53SPI_INTR_RAF_LR_SESSION_DONE 0x3ac
68#define B53SPI_INTR_RAF_LR_OVERREAD 0x3b0
69#define B53SPI_INTR_MSPI_DONE 0x3b4
70#define B53SPI_INTR_MSPI_HALT_SET_TRANSACTION_DONE 0x3b8
71
72#endif /* SPI_BCM53XX_H */
diff --git a/drivers/spi/spi-cadence.c b/drivers/spi/spi-cadence.c
index 562ff83debd9..7b811e38c7ad 100644
--- a/drivers/spi/spi-cadence.c
+++ b/drivers/spi/spi-cadence.c
@@ -677,7 +677,6 @@ static struct platform_driver cdns_spi_driver = {
677 .remove = cdns_spi_remove, 677 .remove = cdns_spi_remove,
678 .driver = { 678 .driver = {
679 .name = CDNS_SPI_NAME, 679 .name = CDNS_SPI_NAME,
680 .owner = THIS_MODULE,
681 .of_match_table = cdns_spi_of_match, 680 .of_match_table = cdns_spi_of_match,
682 .pm = &cdns_spi_dev_pm_ops, 681 .pm = &cdns_spi_dev_pm_ops,
683 }, 682 },
diff --git a/drivers/spi/spi-clps711x.c b/drivers/spi/spi-clps711x.c
index ce538dad526b..181cf2262006 100644
--- a/drivers/spi/spi-clps711x.c
+++ b/drivers/spi/spi-clps711x.c
@@ -30,7 +30,6 @@
30struct spi_clps711x_data { 30struct spi_clps711x_data {
31 void __iomem *syncio; 31 void __iomem *syncio;
32 struct regmap *syscon; 32 struct regmap *syscon;
33 struct regmap *syscon1;
34 struct clk *spi_clk; 33 struct clk *spi_clk;
35 34
36 u8 *tx_buf; 35 u8 *tx_buf;
@@ -47,27 +46,6 @@ static int spi_clps711x_setup(struct spi_device *spi)
47 return 0; 46 return 0;
48} 47}
49 48
50static void spi_clps711x_setup_xfer(struct spi_device *spi,
51 struct spi_transfer *xfer)
52{
53 struct spi_master *master = spi->master;
54 struct spi_clps711x_data *hw = spi_master_get_devdata(master);
55
56 /* Setup SPI frequency divider */
57 if (xfer->speed_hz >= master->max_speed_hz)
58 regmap_update_bits(hw->syscon1, SYSCON_OFFSET,
59 SYSCON1_ADCKSEL_MASK, SYSCON1_ADCKSEL(3));
60 else if (xfer->speed_hz >= (master->max_speed_hz / 2))
61 regmap_update_bits(hw->syscon1, SYSCON_OFFSET,
62 SYSCON1_ADCKSEL_MASK, SYSCON1_ADCKSEL(2));
63 else if (xfer->speed_hz >= (master->max_speed_hz / 8))
64 regmap_update_bits(hw->syscon1, SYSCON_OFFSET,
65 SYSCON1_ADCKSEL_MASK, SYSCON1_ADCKSEL(1));
66 else
67 regmap_update_bits(hw->syscon1, SYSCON_OFFSET,
68 SYSCON1_ADCKSEL_MASK, SYSCON1_ADCKSEL(0));
69}
70
71static int spi_clps711x_prepare_message(struct spi_master *master, 49static int spi_clps711x_prepare_message(struct spi_master *master,
72 struct spi_message *msg) 50 struct spi_message *msg)
73{ 51{
@@ -87,7 +65,7 @@ static int spi_clps711x_transfer_one(struct spi_master *master,
87 struct spi_clps711x_data *hw = spi_master_get_devdata(master); 65 struct spi_clps711x_data *hw = spi_master_get_devdata(master);
88 u8 data; 66 u8 data;
89 67
90 spi_clps711x_setup_xfer(spi, xfer); 68 clk_set_rate(hw->spi_clk, xfer->speed_hz ? : spi->max_speed_hz);
91 69
92 hw->len = xfer->len; 70 hw->len = xfer->len;
93 hw->bpw = xfer->bits_per_word; 71 hw->bpw = xfer->bits_per_word;
@@ -176,13 +154,11 @@ static int spi_clps711x_probe(struct platform_device *pdev)
176 } 154 }
177 } 155 }
178 156
179 hw->spi_clk = devm_clk_get(&pdev->dev, "spi"); 157 hw->spi_clk = devm_clk_get(&pdev->dev, NULL);
180 if (IS_ERR(hw->spi_clk)) { 158 if (IS_ERR(hw->spi_clk)) {
181 dev_err(&pdev->dev, "Can't get clocks\n");
182 ret = PTR_ERR(hw->spi_clk); 159 ret = PTR_ERR(hw->spi_clk);
183 goto err_out; 160 goto err_out;
184 } 161 }
185 master->max_speed_hz = clk_get_rate(hw->spi_clk);
186 162
187 hw->syscon = syscon_regmap_lookup_by_pdevname("syscon.3"); 163 hw->syscon = syscon_regmap_lookup_by_pdevname("syscon.3");
188 if (IS_ERR(hw->syscon)) { 164 if (IS_ERR(hw->syscon)) {
@@ -190,12 +166,6 @@ static int spi_clps711x_probe(struct platform_device *pdev)
190 goto err_out; 166 goto err_out;
191 } 167 }
192 168
193 hw->syscon1 = syscon_regmap_lookup_by_pdevname("syscon.1");
194 if (IS_ERR(hw->syscon1)) {
195 ret = PTR_ERR(hw->syscon1);
196 goto err_out;
197 }
198
199 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 169 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
200 hw->syncio = devm_ioremap_resource(&pdev->dev, res); 170 hw->syncio = devm_ioremap_resource(&pdev->dev, res);
201 if (IS_ERR(hw->syncio)) { 171 if (IS_ERR(hw->syncio)) {
diff --git a/drivers/spi/spi-davinci.c b/drivers/spi/spi-davinci.c
index 276a3884fb3c..63700ab7bd9f 100644
--- a/drivers/spi/spi-davinci.c
+++ b/drivers/spi/spi-davinci.c
@@ -65,6 +65,7 @@
65 65
66/* SPIDAT1 (upper 16 bit defines) */ 66/* SPIDAT1 (upper 16 bit defines) */
67#define SPIDAT1_CSHOLD_MASK BIT(12) 67#define SPIDAT1_CSHOLD_MASK BIT(12)
68#define SPIDAT1_WDEL BIT(10)
68 69
69/* SPIGCR1 */ 70/* SPIGCR1 */
70#define SPIGCR1_CLKMOD_MASK BIT(1) 71#define SPIGCR1_CLKMOD_MASK BIT(1)
@@ -167,8 +168,10 @@ static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *dspi)
167static u32 davinci_spi_tx_buf_u8(struct davinci_spi *dspi) 168static u32 davinci_spi_tx_buf_u8(struct davinci_spi *dspi)
168{ 169{
169 u32 data = 0; 170 u32 data = 0;
171
170 if (dspi->tx) { 172 if (dspi->tx) {
171 const u8 *tx = dspi->tx; 173 const u8 *tx = dspi->tx;
174
172 data = *tx++; 175 data = *tx++;
173 dspi->tx = tx; 176 dspi->tx = tx;
174 } 177 }
@@ -178,8 +181,10 @@ static u32 davinci_spi_tx_buf_u8(struct davinci_spi *dspi)
178static u32 davinci_spi_tx_buf_u16(struct davinci_spi *dspi) 181static u32 davinci_spi_tx_buf_u16(struct davinci_spi *dspi)
179{ 182{
180 u32 data = 0; 183 u32 data = 0;
184
181 if (dspi->tx) { 185 if (dspi->tx) {
182 const u16 *tx = dspi->tx; 186 const u16 *tx = dspi->tx;
187
183 data = *tx++; 188 data = *tx++;
184 dspi->tx = tx; 189 dspi->tx = tx;
185 } 190 }
@@ -209,6 +214,7 @@ static void davinci_spi_chipselect(struct spi_device *spi, int value)
209{ 214{
210 struct davinci_spi *dspi; 215 struct davinci_spi *dspi;
211 struct davinci_spi_platform_data *pdata; 216 struct davinci_spi_platform_data *pdata;
217 struct davinci_spi_config *spicfg = spi->controller_data;
212 u8 chip_sel = spi->chip_select; 218 u8 chip_sel = spi->chip_select;
213 u16 spidat1 = CS_DEFAULT; 219 u16 spidat1 = CS_DEFAULT;
214 bool gpio_chipsel = false; 220 bool gpio_chipsel = false;
@@ -223,6 +229,10 @@ static void davinci_spi_chipselect(struct spi_device *spi, int value)
223 gpio = spi->cs_gpio; 229 gpio = spi->cs_gpio;
224 } 230 }
225 231
232 /* program delay transfers if tx_delay is non zero */
233 if (spicfg->wdelay)
234 spidat1 |= SPIDAT1_WDEL;
235
226 /* 236 /*
227 * Board specific chip select logic decides the polarity and cs 237 * Board specific chip select logic decides the polarity and cs
228 * line for the controller 238 * line for the controller
@@ -237,9 +247,9 @@ static void davinci_spi_chipselect(struct spi_device *spi, int value)
237 spidat1 |= SPIDAT1_CSHOLD_MASK; 247 spidat1 |= SPIDAT1_CSHOLD_MASK;
238 spidat1 &= ~(0x1 << chip_sel); 248 spidat1 &= ~(0x1 << chip_sel);
239 } 249 }
240
241 iowrite16(spidat1, dspi->base + SPIDAT1 + 2);
242 } 250 }
251
252 iowrite16(spidat1, dspi->base + SPIDAT1 + 2);
243} 253}
244 254
245/** 255/**
@@ -285,7 +295,7 @@ static int davinci_spi_setup_transfer(struct spi_device *spi,
285 int prescale; 295 int prescale;
286 296
287 dspi = spi_master_get_devdata(spi->master); 297 dspi = spi_master_get_devdata(spi->master);
288 spicfg = (struct davinci_spi_config *)spi->controller_data; 298 spicfg = spi->controller_data;
289 if (!spicfg) 299 if (!spicfg)
290 spicfg = &davinci_spi_default_cfg; 300 spicfg = &davinci_spi_default_cfg;
291 301
@@ -333,6 +343,14 @@ static int davinci_spi_setup_transfer(struct spi_device *spi,
333 spifmt |= SPIFMT_PHASE_MASK; 343 spifmt |= SPIFMT_PHASE_MASK;
334 344
335 /* 345 /*
346 * Assume wdelay is used only on SPI peripherals that has this field
347 * in SPIFMTn register and when it's configured from board file or DT.
348 */
349 if (spicfg->wdelay)
350 spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT)
351 & SPIFMT_WDELAY_MASK);
352
353 /*
336 * Version 1 hardware supports two basic SPI modes: 354 * Version 1 hardware supports two basic SPI modes:
337 * - Standard SPI mode uses 4 pins, with chipselect 355 * - Standard SPI mode uses 4 pins, with chipselect
338 * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS) 356 * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS)
@@ -349,9 +367,6 @@ static int davinci_spi_setup_transfer(struct spi_device *spi,
349 367
350 u32 delay = 0; 368 u32 delay = 0;
351 369
352 spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT)
353 & SPIFMT_WDELAY_MASK);
354
355 if (spicfg->odd_parity) 370 if (spicfg->odd_parity)
356 spifmt |= SPIFMT_ODD_PARITY_MASK; 371 spifmt |= SPIFMT_ODD_PARITY_MASK;
357 372
@@ -383,6 +398,26 @@ static int davinci_spi_setup_transfer(struct spi_device *spi,
383 return 0; 398 return 0;
384} 399}
385 400
401static int davinci_spi_of_setup(struct spi_device *spi)
402{
403 struct davinci_spi_config *spicfg = spi->controller_data;
404 struct device_node *np = spi->dev.of_node;
405 u32 prop;
406
407 if (spicfg == NULL && np) {
408 spicfg = kzalloc(sizeof(*spicfg), GFP_KERNEL);
409 if (!spicfg)
410 return -ENOMEM;
411 *spicfg = davinci_spi_default_cfg;
412 /* override with dt configured values */
413 if (!of_property_read_u32(np, "ti,spi-wdelay", &prop))
414 spicfg->wdelay = (u8)prop;
415 spi->controller_data = spicfg;
416 }
417
418 return 0;
419}
420
386/** 421/**
387 * davinci_spi_setup - This functions will set default transfer method 422 * davinci_spi_setup - This functions will set default transfer method
388 * @spi: spi device on which data transfer to be done 423 * @spi: spi device on which data transfer to be done
@@ -397,36 +432,33 @@ static int davinci_spi_setup(struct spi_device *spi)
397 struct spi_master *master = spi->master; 432 struct spi_master *master = spi->master;
398 struct device_node *np = spi->dev.of_node; 433 struct device_node *np = spi->dev.of_node;
399 bool internal_cs = true; 434 bool internal_cs = true;
400 unsigned long flags = GPIOF_DIR_OUT;
401 435
402 dspi = spi_master_get_devdata(spi->master); 436 dspi = spi_master_get_devdata(spi->master);
403 pdata = &dspi->pdata; 437 pdata = &dspi->pdata;
404 438
405 flags |= (spi->mode & SPI_CS_HIGH) ? GPIOF_INIT_LOW : GPIOF_INIT_HIGH;
406
407 if (!(spi->mode & SPI_NO_CS)) { 439 if (!(spi->mode & SPI_NO_CS)) {
408 if (np && (master->cs_gpios != NULL) && (spi->cs_gpio >= 0)) { 440 if (np && (master->cs_gpios != NULL) && (spi->cs_gpio >= 0)) {
409 retval = gpio_request_one(spi->cs_gpio, 441 retval = gpio_direction_output(
410 flags, dev_name(&spi->dev)); 442 spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
411 internal_cs = false; 443 internal_cs = false;
412 } else if (pdata->chip_sel && 444 } else if (pdata->chip_sel &&
413 spi->chip_select < pdata->num_chipselect && 445 spi->chip_select < pdata->num_chipselect &&
414 pdata->chip_sel[spi->chip_select] != SPI_INTERN_CS) { 446 pdata->chip_sel[spi->chip_select] != SPI_INTERN_CS) {
415 spi->cs_gpio = pdata->chip_sel[spi->chip_select]; 447 spi->cs_gpio = pdata->chip_sel[spi->chip_select];
416 retval = gpio_request_one(spi->cs_gpio, 448 retval = gpio_direction_output(
417 flags, dev_name(&spi->dev)); 449 spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
418 internal_cs = false; 450 internal_cs = false;
419 } 451 }
420 }
421 452
422 if (retval) { 453 if (retval) {
423 dev_err(&spi->dev, "GPIO %d setup failed (%d)\n", 454 dev_err(&spi->dev, "GPIO %d setup failed (%d)\n",
424 spi->cs_gpio, retval); 455 spi->cs_gpio, retval);
425 return retval; 456 return retval;
426 } 457 }
427 458
428 if (internal_cs) 459 if (internal_cs)
429 set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select); 460 set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select);
461 }
430 462
431 if (spi->mode & SPI_READY) 463 if (spi->mode & SPI_READY)
432 set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK); 464 set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK);
@@ -436,13 +468,16 @@ static int davinci_spi_setup(struct spi_device *spi)
436 else 468 else
437 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK); 469 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);
438 470
439 return retval; 471 return davinci_spi_of_setup(spi);
440} 472}
441 473
442static void davinci_spi_cleanup(struct spi_device *spi) 474static void davinci_spi_cleanup(struct spi_device *spi)
443{ 475{
444 if (spi->cs_gpio >= 0) 476 struct davinci_spi_config *spicfg = spi->controller_data;
445 gpio_free(spi->cs_gpio); 477
478 spi->controller_data = NULL;
479 if (spi->dev.of_node)
480 kfree(spicfg);
446} 481}
447 482
448static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status) 483static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status)
@@ -967,6 +1002,27 @@ static int davinci_spi_probe(struct platform_device *pdev)
967 if (dspi->version == SPI_VERSION_2) 1002 if (dspi->version == SPI_VERSION_2)
968 dspi->bitbang.flags |= SPI_READY; 1003 dspi->bitbang.flags |= SPI_READY;
969 1004
1005 if (pdev->dev.of_node) {
1006 int i;
1007
1008 for (i = 0; i < pdata->num_chipselect; i++) {
1009 int cs_gpio = of_get_named_gpio(pdev->dev.of_node,
1010 "cs-gpios", i);
1011
1012 if (cs_gpio == -EPROBE_DEFER) {
1013 ret = cs_gpio;
1014 goto free_clk;
1015 }
1016
1017 if (gpio_is_valid(cs_gpio)) {
1018 ret = devm_gpio_request(&pdev->dev, cs_gpio,
1019 dev_name(&pdev->dev));
1020 if (ret)
1021 goto free_clk;
1022 }
1023 }
1024 }
1025
970 r = platform_get_resource(pdev, IORESOURCE_DMA, 0); 1026 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
971 if (r) 1027 if (r)
972 dma_rx_chan = r->start; 1028 dma_rx_chan = r->start;
@@ -985,8 +1041,8 @@ static int davinci_spi_probe(struct platform_device *pdev)
985 goto free_clk; 1041 goto free_clk;
986 1042
987 dev_info(&pdev->dev, "DMA: supported\n"); 1043 dev_info(&pdev->dev, "DMA: supported\n");
988 dev_info(&pdev->dev, "DMA: RX channel: %pa, TX channel: %pa, " 1044 dev_info(&pdev->dev, "DMA: RX channel: %pa, TX channel: %pa, event queue: %d\n",
989 "event queue: %d\n", &dma_rx_chan, &dma_tx_chan, 1045 &dma_rx_chan, &dma_tx_chan,
990 pdata->dma_event_q); 1046 pdata->dma_event_q);
991 } 1047 }
992 1048
diff --git a/drivers/spi/spi-dw-mid.c b/drivers/spi/spi-dw-mid.c
index 6d207afec8cb..46c6d58e1fda 100644
--- a/drivers/spi/spi-dw-mid.c
+++ b/drivers/spi/spi-dw-mid.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Special handling for DW core on Intel MID platform 2 * Special handling for DW core on Intel MID platform
3 * 3 *
4 * Copyright (c) 2009, Intel Corporation. 4 * Copyright (c) 2009, 2014 Intel Corporation.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License, 7 * under the terms and conditions of the GNU General Public License,
@@ -11,10 +11,6 @@
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details. 13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 */ 14 */
19 15
20#include <linux/dma-mapping.h> 16#include <linux/dma-mapping.h>
@@ -39,22 +35,25 @@ static bool mid_spi_dma_chan_filter(struct dma_chan *chan, void *param)
39{ 35{
40 struct dw_spi *dws = param; 36 struct dw_spi *dws = param;
41 37
42 return dws->dmac && (&dws->dmac->dev == chan->device->dev); 38 return dws->dma_dev == chan->device->dev;
43} 39}
44 40
45static int mid_spi_dma_init(struct dw_spi *dws) 41static int mid_spi_dma_init(struct dw_spi *dws)
46{ 42{
47 struct mid_dma *dw_dma = dws->dma_priv; 43 struct mid_dma *dw_dma = dws->dma_priv;
44 struct pci_dev *dma_dev;
48 struct intel_mid_dma_slave *rxs, *txs; 45 struct intel_mid_dma_slave *rxs, *txs;
49 dma_cap_mask_t mask; 46 dma_cap_mask_t mask;
50 47
51 /* 48 /*
52 * Get pci device for DMA controller, currently it could only 49 * Get pci device for DMA controller, currently it could only
53 * be the DMA controller of either Moorestown or Medfield 50 * be the DMA controller of Medfield
54 */ 51 */
55 dws->dmac = pci_get_device(PCI_VENDOR_ID_INTEL, 0x0813, NULL); 52 dma_dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x0827, NULL);
56 if (!dws->dmac) 53 if (!dma_dev)
57 dws->dmac = pci_get_device(PCI_VENDOR_ID_INTEL, 0x0827, NULL); 54 return -ENODEV;
55
56 dws->dma_dev = &dma_dev->dev;
58 57
59 dma_cap_zero(mask); 58 dma_cap_zero(mask);
60 dma_cap_set(DMA_SLAVE, mask); 59 dma_cap_set(DMA_SLAVE, mask);
@@ -83,13 +82,18 @@ static int mid_spi_dma_init(struct dw_spi *dws)
83free_rxchan: 82free_rxchan:
84 dma_release_channel(dws->rxchan); 83 dma_release_channel(dws->rxchan);
85err_exit: 84err_exit:
86 return -1; 85 return -EBUSY;
87
88} 86}
89 87
90static void mid_spi_dma_exit(struct dw_spi *dws) 88static void mid_spi_dma_exit(struct dw_spi *dws)
91{ 89{
90 if (!dws->dma_inited)
91 return;
92
93 dmaengine_terminate_all(dws->txchan);
92 dma_release_channel(dws->txchan); 94 dma_release_channel(dws->txchan);
95
96 dmaengine_terminate_all(dws->rxchan);
93 dma_release_channel(dws->rxchan); 97 dma_release_channel(dws->rxchan);
94} 98}
95 99
@@ -109,8 +113,7 @@ static void dw_spi_dma_done(void *arg)
109 113
110static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change) 114static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change)
111{ 115{
112 struct dma_async_tx_descriptor *txdesc = NULL, *rxdesc = NULL; 116 struct dma_async_tx_descriptor *txdesc, *rxdesc;
113 struct dma_chan *txchan, *rxchan;
114 struct dma_slave_config txconf, rxconf; 117 struct dma_slave_config txconf, rxconf;
115 u16 dma_ctrl = 0; 118 u16 dma_ctrl = 0;
116 119
@@ -120,37 +123,34 @@ static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change)
120 dw_writew(dws, DW_SPI_DMARDLR, 0xf); 123 dw_writew(dws, DW_SPI_DMARDLR, 0xf);
121 dw_writew(dws, DW_SPI_DMATDLR, 0x10); 124 dw_writew(dws, DW_SPI_DMATDLR, 0x10);
122 if (dws->tx_dma) 125 if (dws->tx_dma)
123 dma_ctrl |= 0x2; 126 dma_ctrl |= SPI_DMA_TDMAE;
124 if (dws->rx_dma) 127 if (dws->rx_dma)
125 dma_ctrl |= 0x1; 128 dma_ctrl |= SPI_DMA_RDMAE;
126 dw_writew(dws, DW_SPI_DMACR, dma_ctrl); 129 dw_writew(dws, DW_SPI_DMACR, dma_ctrl);
127 spi_enable_chip(dws, 1); 130 spi_enable_chip(dws, 1);
128 } 131 }
129 132
130 dws->dma_chan_done = 0; 133 dws->dma_chan_done = 0;
131 txchan = dws->txchan;
132 rxchan = dws->rxchan;
133 134
134 /* 2. Prepare the TX dma transfer */ 135 /* 2. Prepare the TX dma transfer */
135 txconf.direction = DMA_MEM_TO_DEV; 136 txconf.direction = DMA_MEM_TO_DEV;
136 txconf.dst_addr = dws->dma_addr; 137 txconf.dst_addr = dws->dma_addr;
137 txconf.dst_maxburst = LNW_DMA_MSIZE_16; 138 txconf.dst_maxburst = LNW_DMA_MSIZE_16;
138 txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 139 txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
139 txconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 140 txconf.dst_addr_width = dws->dma_width;
140 txconf.device_fc = false; 141 txconf.device_fc = false;
141 142
142 txchan->device->device_control(txchan, DMA_SLAVE_CONFIG, 143 dmaengine_slave_config(dws->txchan, &txconf);
143 (unsigned long) &txconf);
144 144
145 memset(&dws->tx_sgl, 0, sizeof(dws->tx_sgl)); 145 memset(&dws->tx_sgl, 0, sizeof(dws->tx_sgl));
146 dws->tx_sgl.dma_address = dws->tx_dma; 146 dws->tx_sgl.dma_address = dws->tx_dma;
147 dws->tx_sgl.length = dws->len; 147 dws->tx_sgl.length = dws->len;
148 148
149 txdesc = dmaengine_prep_slave_sg(txchan, 149 txdesc = dmaengine_prep_slave_sg(dws->txchan,
150 &dws->tx_sgl, 150 &dws->tx_sgl,
151 1, 151 1,
152 DMA_MEM_TO_DEV, 152 DMA_MEM_TO_DEV,
153 DMA_PREP_INTERRUPT); 153 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
154 txdesc->callback = dw_spi_dma_done; 154 txdesc->callback = dw_spi_dma_done;
155 txdesc->callback_param = dws; 155 txdesc->callback_param = dws;
156 156
@@ -159,27 +159,30 @@ static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change)
159 rxconf.src_addr = dws->dma_addr; 159 rxconf.src_addr = dws->dma_addr;
160 rxconf.src_maxburst = LNW_DMA_MSIZE_16; 160 rxconf.src_maxburst = LNW_DMA_MSIZE_16;
161 rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 161 rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
162 rxconf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 162 rxconf.src_addr_width = dws->dma_width;
163 rxconf.device_fc = false; 163 rxconf.device_fc = false;
164 164
165 rxchan->device->device_control(rxchan, DMA_SLAVE_CONFIG, 165 dmaengine_slave_config(dws->rxchan, &rxconf);
166 (unsigned long) &rxconf);
167 166
168 memset(&dws->rx_sgl, 0, sizeof(dws->rx_sgl)); 167 memset(&dws->rx_sgl, 0, sizeof(dws->rx_sgl));
169 dws->rx_sgl.dma_address = dws->rx_dma; 168 dws->rx_sgl.dma_address = dws->rx_dma;
170 dws->rx_sgl.length = dws->len; 169 dws->rx_sgl.length = dws->len;
171 170
172 rxdesc = dmaengine_prep_slave_sg(rxchan, 171 rxdesc = dmaengine_prep_slave_sg(dws->rxchan,
173 &dws->rx_sgl, 172 &dws->rx_sgl,
174 1, 173 1,
175 DMA_DEV_TO_MEM, 174 DMA_DEV_TO_MEM,
176 DMA_PREP_INTERRUPT); 175 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
177 rxdesc->callback = dw_spi_dma_done; 176 rxdesc->callback = dw_spi_dma_done;
178 rxdesc->callback_param = dws; 177 rxdesc->callback_param = dws;
179 178
180 /* rx must be started before tx due to spi instinct */ 179 /* rx must be started before tx due to spi instinct */
181 rxdesc->tx_submit(rxdesc); 180 dmaengine_submit(rxdesc);
182 txdesc->tx_submit(txdesc); 181 dma_async_issue_pending(dws->rxchan);
182
183 dmaengine_submit(txdesc);
184 dma_async_issue_pending(dws->txchan);
185
183 return 0; 186 return 0;
184} 187}
185 188
@@ -190,7 +193,7 @@ static struct dw_spi_dma_ops mid_dma_ops = {
190}; 193};
191#endif 194#endif
192 195
193/* Some specific info for SPI0 controller on Moorestown */ 196/* Some specific info for SPI0 controller on Intel MID */
194 197
195/* HW info for MRST CLk Control Unit, one 32b reg */ 198/* HW info for MRST CLk Control Unit, one 32b reg */
196#define MRST_SPI_CLK_BASE 100000000 /* 100m */ 199#define MRST_SPI_CLK_BASE 100000000 /* 100m */
diff --git a/drivers/spi/spi-dw-pci.c b/drivers/spi/spi-dw-pci.c
index 3f3dc1226edf..ba68da12cdf0 100644
--- a/drivers/spi/spi-dw-pci.c
+++ b/drivers/spi/spi-dw-pci.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * PCI interface driver for DW SPI Core 2 * PCI interface driver for DW SPI Core
3 * 3 *
4 * Copyright (c) 2009, Intel Corporation. 4 * Copyright (c) 2009, 2014 Intel Corporation.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License, 7 * under the terms and conditions of the GNU General Public License,
@@ -11,10 +11,6 @@
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details. 13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 */ 14 */
19 15
20#include <linux/interrupt.h> 16#include <linux/interrupt.h>
@@ -32,17 +28,22 @@ struct dw_spi_pci {
32 struct dw_spi dws; 28 struct dw_spi dws;
33}; 29};
34 30
35static int spi_pci_probe(struct pci_dev *pdev, 31struct spi_pci_desc {
36 const struct pci_device_id *ent) 32 int (*setup)(struct dw_spi *);
33};
34
35static struct spi_pci_desc spi_pci_mid_desc = {
36 .setup = dw_spi_mid_init,
37};
38
39static int spi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
37{ 40{
38 struct dw_spi_pci *dwpci; 41 struct dw_spi_pci *dwpci;
39 struct dw_spi *dws; 42 struct dw_spi *dws;
43 struct spi_pci_desc *desc = (struct spi_pci_desc *)ent->driver_data;
40 int pci_bar = 0; 44 int pci_bar = 0;
41 int ret; 45 int ret;
42 46
43 dev_info(&pdev->dev, "found PCI SPI controller(ID: %04x:%04x)\n",
44 pdev->vendor, pdev->device);
45
46 ret = pcim_enable_device(pdev); 47 ret = pcim_enable_device(pdev);
47 if (ret) 48 if (ret)
48 return ret; 49 return ret;
@@ -58,20 +59,22 @@ static int spi_pci_probe(struct pci_dev *pdev,
58 /* Get basic io resource and map it */ 59 /* Get basic io resource and map it */
59 dws->paddr = pci_resource_start(pdev, pci_bar); 60 dws->paddr = pci_resource_start(pdev, pci_bar);
60 61
61 ret = pcim_iomap_regions(pdev, 1, dev_name(&pdev->dev)); 62 ret = pcim_iomap_regions(pdev, 1 << pci_bar, pci_name(pdev));
62 if (ret) 63 if (ret)
63 return ret; 64 return ret;
64 65
66 dws->regs = pcim_iomap_table(pdev)[pci_bar];
67
65 dws->bus_num = 0; 68 dws->bus_num = 0;
66 dws->num_cs = 4; 69 dws->num_cs = 4;
67 dws->irq = pdev->irq; 70 dws->irq = pdev->irq;
68 71
69 /* 72 /*
70 * Specific handling for Intel MID paltforms, like dma setup, 73 * Specific handling for paltforms, like dma setup,
71 * clock rate, FIFO depth. 74 * clock rate, FIFO depth.
72 */ 75 */
73 if (pdev->device == 0x0800) { 76 if (desc && desc->setup) {
74 ret = dw_spi_mid_init(dws); 77 ret = desc->setup(dws);
75 if (ret) 78 if (ret)
76 return ret; 79 return ret;
77 } 80 }
@@ -83,6 +86,9 @@ static int spi_pci_probe(struct pci_dev *pdev,
83 /* PCI hook and SPI hook use the same drv data */ 86 /* PCI hook and SPI hook use the same drv data */
84 pci_set_drvdata(pdev, dwpci); 87 pci_set_drvdata(pdev, dwpci);
85 88
89 dev_info(&pdev->dev, "found PCI SPI controller(ID: %04x:%04x)\n",
90 pdev->vendor, pdev->device);
91
86 return 0; 92 return 0;
87} 93}
88 94
@@ -93,41 +99,29 @@ static void spi_pci_remove(struct pci_dev *pdev)
93 dw_spi_remove_host(&dwpci->dws); 99 dw_spi_remove_host(&dwpci->dws);
94} 100}
95 101
96#ifdef CONFIG_PM 102#ifdef CONFIG_PM_SLEEP
97static int spi_suspend(struct pci_dev *pdev, pm_message_t state) 103static int spi_suspend(struct device *dev)
98{ 104{
105 struct pci_dev *pdev = to_pci_dev(dev);
99 struct dw_spi_pci *dwpci = pci_get_drvdata(pdev); 106 struct dw_spi_pci *dwpci = pci_get_drvdata(pdev);
100 int ret;
101 107
102 ret = dw_spi_suspend_host(&dwpci->dws); 108 return dw_spi_suspend_host(&dwpci->dws);
103 if (ret)
104 return ret;
105 pci_save_state(pdev);
106 pci_disable_device(pdev);
107 pci_set_power_state(pdev, pci_choose_state(pdev, state));
108 return ret;
109} 109}
110 110
111static int spi_resume(struct pci_dev *pdev) 111static int spi_resume(struct device *dev)
112{ 112{
113 struct pci_dev *pdev = to_pci_dev(dev);
113 struct dw_spi_pci *dwpci = pci_get_drvdata(pdev); 114 struct dw_spi_pci *dwpci = pci_get_drvdata(pdev);
114 int ret;
115 115
116 pci_set_power_state(pdev, PCI_D0);
117 pci_restore_state(pdev);
118 ret = pci_enable_device(pdev);
119 if (ret)
120 return ret;
121 return dw_spi_resume_host(&dwpci->dws); 116 return dw_spi_resume_host(&dwpci->dws);
122} 117}
123#else
124#define spi_suspend NULL
125#define spi_resume NULL
126#endif 118#endif
127 119
120static SIMPLE_DEV_PM_OPS(dw_spi_pm_ops, spi_suspend, spi_resume);
121
128static const struct pci_device_id pci_ids[] = { 122static const struct pci_device_id pci_ids[] = {
129 /* Intel MID platform SPI controller 0 */ 123 /* Intel MID platform SPI controller 0 */
130 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0800) }, 124 { PCI_VDEVICE(INTEL, 0x0800), (kernel_ulong_t)&spi_pci_mid_desc},
131 {}, 125 {},
132}; 126};
133 127
@@ -136,8 +130,9 @@ static struct pci_driver dw_spi_driver = {
136 .id_table = pci_ids, 130 .id_table = pci_ids,
137 .probe = spi_pci_probe, 131 .probe = spi_pci_probe,
138 .remove = spi_pci_remove, 132 .remove = spi_pci_remove,
139 .suspend = spi_suspend, 133 .driver = {
140 .resume = spi_resume, 134 .pm = &dw_spi_pm_ops,
135 },
141}; 136};
142 137
143module_pci_driver(dw_spi_driver); 138module_pci_driver(dw_spi_driver);
diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c
index 29f33143b795..729215885250 100644
--- a/drivers/spi/spi-dw.c
+++ b/drivers/spi/spi-dw.c
@@ -11,10 +11,6 @@
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details. 13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 */ 14 */
19 15
20#include <linux/dma-mapping.h> 16#include <linux/dma-mapping.h>
@@ -59,22 +55,20 @@ struct chip_data {
59 55
60#ifdef CONFIG_DEBUG_FS 56#ifdef CONFIG_DEBUG_FS
61#define SPI_REGS_BUFSIZE 1024 57#define SPI_REGS_BUFSIZE 1024
62static ssize_t spi_show_regs(struct file *file, char __user *user_buf, 58static ssize_t dw_spi_show_regs(struct file *file, char __user *user_buf,
63 size_t count, loff_t *ppos) 59 size_t count, loff_t *ppos)
64{ 60{
65 struct dw_spi *dws; 61 struct dw_spi *dws = file->private_data;
66 char *buf; 62 char *buf;
67 u32 len = 0; 63 u32 len = 0;
68 ssize_t ret; 64 ssize_t ret;
69 65
70 dws = file->private_data;
71
72 buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL); 66 buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
73 if (!buf) 67 if (!buf)
74 return 0; 68 return 0;
75 69
76 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, 70 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
77 "MRST SPI0 registers:\n"); 71 "%s registers:\n", dev_name(&dws->master->dev));
78 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, 72 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
79 "=================================\n"); 73 "=================================\n");
80 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, 74 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
@@ -110,42 +104,41 @@ static ssize_t spi_show_regs(struct file *file, char __user *user_buf,
110 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, 104 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
111 "=================================\n"); 105 "=================================\n");
112 106
113 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); 107 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
114 kfree(buf); 108 kfree(buf);
115 return ret; 109 return ret;
116} 110}
117 111
118static const struct file_operations mrst_spi_regs_ops = { 112static const struct file_operations dw_spi_regs_ops = {
119 .owner = THIS_MODULE, 113 .owner = THIS_MODULE,
120 .open = simple_open, 114 .open = simple_open,
121 .read = spi_show_regs, 115 .read = dw_spi_show_regs,
122 .llseek = default_llseek, 116 .llseek = default_llseek,
123}; 117};
124 118
125static int mrst_spi_debugfs_init(struct dw_spi *dws) 119static int dw_spi_debugfs_init(struct dw_spi *dws)
126{ 120{
127 dws->debugfs = debugfs_create_dir("mrst_spi", NULL); 121 dws->debugfs = debugfs_create_dir("dw_spi", NULL);
128 if (!dws->debugfs) 122 if (!dws->debugfs)
129 return -ENOMEM; 123 return -ENOMEM;
130 124
131 debugfs_create_file("registers", S_IFREG | S_IRUGO, 125 debugfs_create_file("registers", S_IFREG | S_IRUGO,
132 dws->debugfs, (void *)dws, &mrst_spi_regs_ops); 126 dws->debugfs, (void *)dws, &dw_spi_regs_ops);
133 return 0; 127 return 0;
134} 128}
135 129
136static void mrst_spi_debugfs_remove(struct dw_spi *dws) 130static void dw_spi_debugfs_remove(struct dw_spi *dws)
137{ 131{
138 if (dws->debugfs) 132 debugfs_remove_recursive(dws->debugfs);
139 debugfs_remove_recursive(dws->debugfs);
140} 133}
141 134
142#else 135#else
143static inline int mrst_spi_debugfs_init(struct dw_spi *dws) 136static inline int dw_spi_debugfs_init(struct dw_spi *dws)
144{ 137{
145 return 0; 138 return 0;
146} 139}
147 140
148static inline void mrst_spi_debugfs_remove(struct dw_spi *dws) 141static inline void dw_spi_debugfs_remove(struct dw_spi *dws)
149{ 142{
150} 143}
151#endif /* CONFIG_DEBUG_FS */ 144#endif /* CONFIG_DEBUG_FS */
@@ -177,7 +170,7 @@ static inline u32 rx_max(struct dw_spi *dws)
177{ 170{
178 u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes; 171 u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes;
179 172
180 return min(rx_left, (u32)dw_readw(dws, DW_SPI_RXFLR)); 173 return min_t(u32, rx_left, dw_readw(dws, DW_SPI_RXFLR));
181} 174}
182 175
183static void dw_writer(struct dw_spi *dws) 176static void dw_writer(struct dw_spi *dws)
@@ -228,8 +221,9 @@ static void *next_transfer(struct dw_spi *dws)
228 struct spi_transfer, 221 struct spi_transfer,
229 transfer_list); 222 transfer_list);
230 return RUNNING_STATE; 223 return RUNNING_STATE;
231 } else 224 }
232 return DONE_STATE; 225
226 return DONE_STATE;
233} 227}
234 228
235/* 229/*
@@ -271,7 +265,7 @@ static void giveback(struct dw_spi *dws)
271 transfer_list); 265 transfer_list);
272 266
273 if (!last_transfer->cs_change) 267 if (!last_transfer->cs_change)
274 spi_chip_sel(dws, dws->cur_msg->spi, 0); 268 spi_chip_sel(dws, msg->spi, 0);
275 269
276 spi_finalize_current_message(dws->master); 270 spi_finalize_current_message(dws->master);
277} 271}
@@ -396,7 +390,7 @@ static void pump_transfers(unsigned long data)
396 goto early_exit; 390 goto early_exit;
397 } 391 }
398 392
399 /* Delay if requested at end of transfer*/ 393 /* Delay if requested at end of transfer */
400 if (message->state == RUNNING_STATE) { 394 if (message->state == RUNNING_STATE) {
401 previous = list_entry(transfer->transfer_list.prev, 395 previous = list_entry(transfer->transfer_list.prev,
402 struct spi_transfer, 396 struct spi_transfer,
@@ -471,10 +465,12 @@ static void pump_transfers(unsigned long data)
471 */ 465 */
472 if (!dws->dma_mapped && !chip->poll_mode) { 466 if (!dws->dma_mapped && !chip->poll_mode) {
473 int templen = dws->len / dws->n_bytes; 467 int templen = dws->len / dws->n_bytes;
468
474 txint_level = dws->fifo_len / 2; 469 txint_level = dws->fifo_len / 2;
475 txint_level = (templen > txint_level) ? txint_level : templen; 470 txint_level = (templen > txint_level) ? txint_level : templen;
476 471
477 imask |= SPI_INT_TXEI | SPI_INT_TXOI | SPI_INT_RXUI | SPI_INT_RXOI; 472 imask |= SPI_INT_TXEI | SPI_INT_TXOI |
473 SPI_INT_RXUI | SPI_INT_RXOI;
478 dws->transfer_handler = interrupt_transfer; 474 dws->transfer_handler = interrupt_transfer;
479 } 475 }
480 476
@@ -515,7 +511,6 @@ static void pump_transfers(unsigned long data)
515 511
516early_exit: 512early_exit:
517 giveback(dws); 513 giveback(dws);
518 return;
519} 514}
520 515
521static int dw_spi_transfer_one_message(struct spi_master *master, 516static int dw_spi_transfer_one_message(struct spi_master *master,
@@ -524,7 +519,7 @@ static int dw_spi_transfer_one_message(struct spi_master *master,
524 struct dw_spi *dws = spi_master_get_devdata(master); 519 struct dw_spi *dws = spi_master_get_devdata(master);
525 520
526 dws->cur_msg = msg; 521 dws->cur_msg = msg;
527 /* Initial message state*/ 522 /* Initial message state */
528 dws->cur_msg->state = START_STATE; 523 dws->cur_msg->state = START_STATE;
529 dws->cur_transfer = list_entry(dws->cur_msg->transfers.next, 524 dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,
530 struct spi_transfer, 525 struct spi_transfer,
@@ -547,8 +542,7 @@ static int dw_spi_setup(struct spi_device *spi)
547 /* Only alloc on first setup */ 542 /* Only alloc on first setup */
548 chip = spi_get_ctldata(spi); 543 chip = spi_get_ctldata(spi);
549 if (!chip) { 544 if (!chip) {
550 chip = devm_kzalloc(&spi->dev, sizeof(struct chip_data), 545 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
551 GFP_KERNEL);
552 if (!chip) 546 if (!chip)
553 return -ENOMEM; 547 return -ENOMEM;
554 spi_set_ctldata(spi, chip); 548 spi_set_ctldata(spi, chip);
@@ -596,6 +590,9 @@ static int dw_spi_setup(struct spi_device *spi)
596 | (spi->mode << SPI_MODE_OFFSET) 590 | (spi->mode << SPI_MODE_OFFSET)
597 | (chip->tmode << SPI_TMOD_OFFSET); 591 | (chip->tmode << SPI_TMOD_OFFSET);
598 592
593 if (spi->mode & SPI_LOOP)
594 chip->cr0 |= 1 << SPI_SRL_OFFSET;
595
599 if (gpio_is_valid(spi->cs_gpio)) { 596 if (gpio_is_valid(spi->cs_gpio)) {
600 ret = gpio_direction_output(spi->cs_gpio, 597 ret = gpio_direction_output(spi->cs_gpio,
601 !(spi->mode & SPI_CS_HIGH)); 598 !(spi->mode & SPI_CS_HIGH));
@@ -606,6 +603,14 @@ static int dw_spi_setup(struct spi_device *spi)
606 return 0; 603 return 0;
607} 604}
608 605
606static void dw_spi_cleanup(struct spi_device *spi)
607{
608 struct chip_data *chip = spi_get_ctldata(spi);
609
610 kfree(chip);
611 spi_set_ctldata(spi, NULL);
612}
613
609/* Restart the controller, disable all interrupts, clean rx fifo */ 614/* Restart the controller, disable all interrupts, clean rx fifo */
610static void spi_hw_init(struct dw_spi *dws) 615static void spi_hw_init(struct dw_spi *dws)
611{ 616{
@@ -619,6 +624,7 @@ static void spi_hw_init(struct dw_spi *dws)
619 */ 624 */
620 if (!dws->fifo_len) { 625 if (!dws->fifo_len) {
621 u32 fifo; 626 u32 fifo;
627
622 for (fifo = 2; fifo <= 257; fifo++) { 628 for (fifo = 2; fifo <= 257; fifo++) {
623 dw_writew(dws, DW_SPI_TXFLTR, fifo); 629 dw_writew(dws, DW_SPI_TXFLTR, fifo);
624 if (fifo != dw_readw(dws, DW_SPI_TXFLTR)) 630 if (fifo != dw_readw(dws, DW_SPI_TXFLTR))
@@ -646,8 +652,7 @@ int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
646 dws->prev_chip = NULL; 652 dws->prev_chip = NULL;
647 dws->dma_inited = 0; 653 dws->dma_inited = 0;
648 dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60); 654 dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60);
649 snprintf(dws->name, sizeof(dws->name), "dw_spi%d", 655 snprintf(dws->name, sizeof(dws->name), "dw_spi%d", dws->bus_num);
650 dws->bus_num);
651 656
652 ret = devm_request_irq(dev, dws->irq, dw_spi_irq, IRQF_SHARED, 657 ret = devm_request_irq(dev, dws->irq, dw_spi_irq, IRQF_SHARED,
653 dws->name, dws); 658 dws->name, dws);
@@ -656,11 +661,12 @@ int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
656 goto err_free_master; 661 goto err_free_master;
657 } 662 }
658 663
659 master->mode_bits = SPI_CPOL | SPI_CPHA; 664 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
660 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16); 665 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
661 master->bus_num = dws->bus_num; 666 master->bus_num = dws->bus_num;
662 master->num_chipselect = dws->num_cs; 667 master->num_chipselect = dws->num_cs;
663 master->setup = dw_spi_setup; 668 master->setup = dw_spi_setup;
669 master->cleanup = dw_spi_cleanup;
664 master->transfer_one_message = dw_spi_transfer_one_message; 670 master->transfer_one_message = dw_spi_transfer_one_message;
665 master->max_speed_hz = dws->max_freq; 671 master->max_speed_hz = dws->max_freq;
666 672
@@ -684,7 +690,7 @@ int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
684 goto err_dma_exit; 690 goto err_dma_exit;
685 } 691 }
686 692
687 mrst_spi_debugfs_init(dws); 693 dw_spi_debugfs_init(dws);
688 return 0; 694 return 0;
689 695
690err_dma_exit: 696err_dma_exit:
@@ -701,7 +707,7 @@ void dw_spi_remove_host(struct dw_spi *dws)
701{ 707{
702 if (!dws) 708 if (!dws)
703 return; 709 return;
704 mrst_spi_debugfs_remove(dws); 710 dw_spi_debugfs_remove(dws);
705 711
706 if (dws->dma_ops && dws->dma_ops->dma_exit) 712 if (dws->dma_ops && dws->dma_ops->dma_exit)
707 dws->dma_ops->dma_exit(dws); 713 dws->dma_ops->dma_exit(dws);
diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
index 6d2acad34f64..83a103a76481 100644
--- a/drivers/spi/spi-dw.h
+++ b/drivers/spi/spi-dw.h
@@ -74,6 +74,10 @@
74#define SPI_INT_RXFI (1 << 4) 74#define SPI_INT_RXFI (1 << 4)
75#define SPI_INT_MSTI (1 << 5) 75#define SPI_INT_MSTI (1 << 5)
76 76
77/* Bit fields in DMACR */
78#define SPI_DMA_RDMAE (1 << 0)
79#define SPI_DMA_TDMAE (1 << 1)
80
77/* TX RX interrupt level threshold, max can be 256 */ 81/* TX RX interrupt level threshold, max can be 256 */
78#define SPI_INT_THRESHOLD 32 82#define SPI_INT_THRESHOLD 32
79 83
@@ -140,7 +144,6 @@ struct dw_spi {
140 dma_addr_t dma_addr; /* phy address of the Data register */ 144 dma_addr_t dma_addr; /* phy address of the Data register */
141 struct dw_spi_dma_ops *dma_ops; 145 struct dw_spi_dma_ops *dma_ops;
142 void *dma_priv; /* platform relate info */ 146 void *dma_priv; /* platform relate info */
143 struct pci_dev *dmac;
144 147
145 /* Bus interface info */ 148 /* Bus interface info */
146 void *priv; 149 void *priv;
@@ -217,11 +220,11 @@ static inline void spi_umask_intr(struct dw_spi *dws, u32 mask)
217 * Each SPI slave device to work with dw_api controller should 220 * Each SPI slave device to work with dw_api controller should
218 * has such a structure claiming its working mode (PIO/DMA etc), 221 * has such a structure claiming its working mode (PIO/DMA etc),
219 * which can be save in the "controller_data" member of the 222 * which can be save in the "controller_data" member of the
220 * struct spi_device 223 * struct spi_device.
221 */ 224 */
222struct dw_spi_chip { 225struct dw_spi_chip {
223 u8 poll_mode; /* 0 for contoller polling mode */ 226 u8 poll_mode; /* 1 for controller polling mode */
224 u8 type; /* SPI/SSP/Micrwire */ 227 u8 type; /* SPI/SSP/MicroWire */
225 u8 enable_dma; 228 u8 enable_dma;
226 void (*cs_control)(u32 command); 229 void (*cs_control)(u32 command);
227}; 230};
diff --git a/drivers/spi/spi-ep93xx.c b/drivers/spi/spi-ep93xx.c
index 2f675d32df0e..bf9728773247 100644
--- a/drivers/spi/spi-ep93xx.c
+++ b/drivers/spi/spi-ep93xx.c
@@ -266,6 +266,7 @@ static int ep93xx_spi_setup(struct spi_device *spi)
266 266
267 if (chip->ops && chip->ops->setup) { 267 if (chip->ops && chip->ops->setup) {
268 int ret = chip->ops->setup(spi); 268 int ret = chip->ops->setup(spi);
269
269 if (ret) { 270 if (ret) {
270 kfree(chip); 271 kfree(chip);
271 return ret; 272 return ret;
diff --git a/drivers/spi/spi-fsl-cpm.c b/drivers/spi/spi-fsl-cpm.c
index 54b06376f03c..c5dd20beee22 100644
--- a/drivers/spi/spi-fsl-cpm.c
+++ b/drivers/spi/spi-fsl-cpm.c
@@ -15,17 +15,17 @@
15 * Free Software Foundation; either version 2 of the License, or (at your 15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version. 16 * option) any later version.
17 */ 17 */
18#include <linux/types.h>
19#include <linux/kernel.h>
20#include <linux/spi/spi.h>
21#include <linux/fsl_devices.h>
22#include <linux/dma-mapping.h>
23#include <linux/of_address.h>
24#include <asm/cpm.h> 18#include <asm/cpm.h>
25#include <asm/qe.h> 19#include <asm/qe.h>
20#include <linux/dma-mapping.h>
21#include <linux/fsl_devices.h>
22#include <linux/kernel.h>
23#include <linux/of_address.h>
24#include <linux/spi/spi.h>
25#include <linux/types.h>
26 26
27#include "spi-fsl-lib.h"
28#include "spi-fsl-cpm.h" 27#include "spi-fsl-cpm.h"
28#include "spi-fsl-lib.h"
29#include "spi-fsl-spi.h" 29#include "spi-fsl-spi.h"
30 30
31/* CPM1 and CPM2 are mutually exclusive. */ 31/* CPM1 and CPM2 are mutually exclusive. */
diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c
index 5021ddf03f60..448216025ce8 100644
--- a/drivers/spi/spi-fsl-dspi.c
+++ b/drivers/spi/spi-fsl-dspi.c
@@ -13,22 +13,22 @@
13 * 13 *
14 */ 14 */
15 15
16#include <linux/clk.h>
17#include <linux/delay.h>
18#include <linux/err.h>
19#include <linux/errno.h>
20#include <linux/interrupt.h>
21#include <linux/io.h>
16#include <linux/kernel.h> 22#include <linux/kernel.h>
17#include <linux/module.h> 23#include <linux/module.h>
18#include <linux/interrupt.h> 24#include <linux/of.h>
19#include <linux/errno.h> 25#include <linux/of_device.h>
20#include <linux/platform_device.h> 26#include <linux/platform_device.h>
27#include <linux/pm_runtime.h>
21#include <linux/regmap.h> 28#include <linux/regmap.h>
22#include <linux/sched.h> 29#include <linux/sched.h>
23#include <linux/delay.h>
24#include <linux/io.h>
25#include <linux/clk.h>
26#include <linux/err.h>
27#include <linux/spi/spi.h> 30#include <linux/spi/spi.h>
28#include <linux/spi/spi_bitbang.h> 31#include <linux/spi/spi_bitbang.h>
29#include <linux/pm_runtime.h>
30#include <linux/of.h>
31#include <linux/of_device.h>
32 32
33#define DRIVER_NAME "fsl-dspi" 33#define DRIVER_NAME "fsl-dspi"
34 34
@@ -493,9 +493,6 @@ static int dspi_probe(struct platform_device *pdev)
493 } 493 }
494 494
495 dspi_regmap_config.lock_arg = dspi; 495 dspi_regmap_config.lock_arg = dspi;
496 dspi_regmap_config.val_format_endian =
497 of_property_read_bool(np, "big-endian")
498 ? REGMAP_ENDIAN_BIG : REGMAP_ENDIAN_DEFAULT;
499 dspi->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "dspi", base, 496 dspi->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "dspi", base,
500 &dspi_regmap_config); 497 &dspi_regmap_config);
501 if (IS_ERR(dspi->regmap)) { 498 if (IS_ERR(dspi->regmap)) {
@@ -535,7 +532,6 @@ static int dspi_probe(struct platform_device *pdev)
535 goto out_clk_put; 532 goto out_clk_put;
536 } 533 }
537 534
538 pr_info(KERN_INFO "Freescale DSPI master initialized\n");
539 return ret; 535 return ret;
540 536
541out_clk_put: 537out_clk_put:
diff --git a/drivers/spi/spi-fsl-espi.c b/drivers/spi/spi-fsl-espi.c
index 8ebd724e4c59..a7f94b6a9e70 100644
--- a/drivers/spi/spi-fsl-espi.c
+++ b/drivers/spi/spi-fsl-espi.c
@@ -8,19 +8,19 @@
8 * Free Software Foundation; either version 2 of the License, or (at your 8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11#include <linux/module.h>
12#include <linux/delay.h> 11#include <linux/delay.h>
13#include <linux/irq.h> 12#include <linux/err.h>
14#include <linux/spi/spi.h>
15#include <linux/platform_device.h>
16#include <linux/fsl_devices.h> 13#include <linux/fsl_devices.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/module.h>
17#include <linux/mm.h> 17#include <linux/mm.h>
18#include <linux/of.h> 18#include <linux/of.h>
19#include <linux/of_address.h> 19#include <linux/of_address.h>
20#include <linux/of_irq.h> 20#include <linux/of_irq.h>
21#include <linux/of_platform.h> 21#include <linux/of_platform.h>
22#include <linux/interrupt.h> 22#include <linux/platform_device.h>
23#include <linux/err.h> 23#include <linux/spi/spi.h>
24#include <sysdev/fsl_soc.h> 24#include <sysdev/fsl_soc.h>
25 25
26#include "spi-fsl-lib.h" 26#include "spi-fsl-lib.h"
@@ -452,16 +452,16 @@ static int fsl_espi_setup(struct spi_device *spi)
452 int retval; 452 int retval;
453 u32 hw_mode; 453 u32 hw_mode;
454 u32 loop_mode; 454 u32 loop_mode;
455 struct spi_mpc8xxx_cs *cs = spi->controller_state; 455 struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
456 456
457 if (!spi->max_speed_hz) 457 if (!spi->max_speed_hz)
458 return -EINVAL; 458 return -EINVAL;
459 459
460 if (!cs) { 460 if (!cs) {
461 cs = devm_kzalloc(&spi->dev, sizeof(*cs), GFP_KERNEL); 461 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
462 if (!cs) 462 if (!cs)
463 return -ENOMEM; 463 return -ENOMEM;
464 spi->controller_state = cs; 464 spi_set_ctldata(spi, cs);
465 } 465 }
466 466
467 mpc8xxx_spi = spi_master_get_devdata(spi->master); 467 mpc8xxx_spi = spi_master_get_devdata(spi->master);
@@ -496,6 +496,14 @@ static int fsl_espi_setup(struct spi_device *spi)
496 return 0; 496 return 0;
497} 497}
498 498
499static void fsl_espi_cleanup(struct spi_device *spi)
500{
501 struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
502
503 kfree(cs);
504 spi_set_ctldata(spi, NULL);
505}
506
499void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events) 507void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
500{ 508{
501 struct fsl_espi_reg *reg_base = mspi->reg_base; 509 struct fsl_espi_reg *reg_base = mspi->reg_base;
@@ -605,6 +613,7 @@ static struct spi_master * fsl_espi_probe(struct device *dev,
605 613
606 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); 614 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
607 master->setup = fsl_espi_setup; 615 master->setup = fsl_espi_setup;
616 master->cleanup = fsl_espi_cleanup;
608 617
609 mpc8xxx_spi = spi_master_get_devdata(master); 618 mpc8xxx_spi = spi_master_get_devdata(master);
610 mpc8xxx_spi->spi_do_one_msg = fsl_espi_do_one_msg; 619 mpc8xxx_spi->spi_do_one_msg = fsl_espi_do_one_msg;
diff --git a/drivers/spi/spi-fsl-lib.c b/drivers/spi/spi-fsl-lib.c
index e0b773fc29cb..5ddb5b098e4e 100644
--- a/drivers/spi/spi-fsl-lib.c
+++ b/drivers/spi/spi-fsl-lib.c
@@ -16,10 +16,10 @@
16 * Free Software Foundation; either version 2 of the License, or (at your 16 * Free Software Foundation; either version 2 of the License, or (at your
17 * option) any later version. 17 * option) any later version.
18 */ 18 */
19#include <linux/kernel.h>
20#include <linux/interrupt.h>
21#include <linux/fsl_devices.h>
22#include <linux/dma-mapping.h> 19#include <linux/dma-mapping.h>
20#include <linux/fsl_devices.h>
21#include <linux/interrupt.h>
22#include <linux/kernel.h>
23#include <linux/mm.h> 23#include <linux/mm.h>
24#include <linux/of_platform.h> 24#include <linux/of_platform.h>
25#include <linux/spi/spi.h> 25#include <linux/spi/spi.h>
diff --git a/drivers/spi/spi-fsl-spi.c b/drivers/spi/spi-fsl-spi.c
index 9452f6740997..ed792880c9d6 100644
--- a/drivers/spi/spi-fsl-spi.c
+++ b/drivers/spi/spi-fsl-spi.c
@@ -19,25 +19,25 @@
19 * Free Software Foundation; either version 2 of the License, or (at your 19 * Free Software Foundation; either version 2 of the License, or (at your
20 * option) any later version. 20 * option) any later version.
21 */ 21 */
22#include <linux/module.h>
23#include <linux/types.h>
24#include <linux/kernel.h>
25#include <linux/interrupt.h>
26#include <linux/delay.h> 22#include <linux/delay.h>
27#include <linux/irq.h>
28#include <linux/spi/spi.h>
29#include <linux/spi/spi_bitbang.h>
30#include <linux/platform_device.h>
31#include <linux/fsl_devices.h>
32#include <linux/dma-mapping.h> 23#include <linux/dma-mapping.h>
24#include <linux/fsl_devices.h>
25#include <linux/gpio.h>
26#include <linux/interrupt.h>
27#include <linux/irq.h>
28#include <linux/kernel.h>
33#include <linux/mm.h> 29#include <linux/mm.h>
30#include <linux/module.h>
34#include <linux/mutex.h> 31#include <linux/mutex.h>
35#include <linux/of.h> 32#include <linux/of.h>
36#include <linux/of_platform.h>
37#include <linux/of_address.h> 33#include <linux/of_address.h>
38#include <linux/of_irq.h> 34#include <linux/of_irq.h>
39#include <linux/gpio.h>
40#include <linux/of_gpio.h> 35#include <linux/of_gpio.h>
36#include <linux/of_platform.h>
37#include <linux/platform_device.h>
38#include <linux/spi/spi.h>
39#include <linux/spi/spi_bitbang.h>
40#include <linux/types.h>
41 41
42#include "spi-fsl-lib.h" 42#include "spi-fsl-lib.h"
43#include "spi-fsl-cpm.h" 43#include "spi-fsl-cpm.h"
@@ -425,16 +425,16 @@ static int fsl_spi_setup(struct spi_device *spi)
425 struct fsl_spi_reg *reg_base; 425 struct fsl_spi_reg *reg_base;
426 int retval; 426 int retval;
427 u32 hw_mode; 427 u32 hw_mode;
428 struct spi_mpc8xxx_cs *cs = spi->controller_state; 428 struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
429 429
430 if (!spi->max_speed_hz) 430 if (!spi->max_speed_hz)
431 return -EINVAL; 431 return -EINVAL;
432 432
433 if (!cs) { 433 if (!cs) {
434 cs = devm_kzalloc(&spi->dev, sizeof(*cs), GFP_KERNEL); 434 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
435 if (!cs) 435 if (!cs)
436 return -ENOMEM; 436 return -ENOMEM;
437 spi->controller_state = cs; 437 spi_set_ctldata(spi, cs);
438 } 438 }
439 mpc8xxx_spi = spi_master_get_devdata(spi->master); 439 mpc8xxx_spi = spi_master_get_devdata(spi->master);
440 440
@@ -496,9 +496,13 @@ static int fsl_spi_setup(struct spi_device *spi)
496static void fsl_spi_cleanup(struct spi_device *spi) 496static void fsl_spi_cleanup(struct spi_device *spi)
497{ 497{
498 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); 498 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
499 struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
499 500
500 if (mpc8xxx_spi->type == TYPE_GRLIB && gpio_is_valid(spi->cs_gpio)) 501 if (mpc8xxx_spi->type == TYPE_GRLIB && gpio_is_valid(spi->cs_gpio))
501 gpio_free(spi->cs_gpio); 502 gpio_free(spi->cs_gpio);
503
504 kfree(cs);
505 spi_set_ctldata(spi, NULL);
502} 506}
503 507
504static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events) 508static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
index 5daff2054ae4..3637847b5370 100644
--- a/drivers/spi/spi-imx.c
+++ b/drivers/spi/spi-imx.c
@@ -21,6 +21,8 @@
21#include <linux/clk.h> 21#include <linux/clk.h>
22#include <linux/completion.h> 22#include <linux/completion.h>
23#include <linux/delay.h> 23#include <linux/delay.h>
24#include <linux/dmaengine.h>
25#include <linux/dma-mapping.h>
24#include <linux/err.h> 26#include <linux/err.h>
25#include <linux/gpio.h> 27#include <linux/gpio.h>
26#include <linux/interrupt.h> 28#include <linux/interrupt.h>
@@ -37,6 +39,7 @@
37#include <linux/of_device.h> 39#include <linux/of_device.h>
38#include <linux/of_gpio.h> 40#include <linux/of_gpio.h>
39 41
42#include <linux/platform_data/dma-imx.h>
40#include <linux/platform_data/spi-imx.h> 43#include <linux/platform_data/spi-imx.h>
41 44
42#define DRIVER_NAME "spi_imx" 45#define DRIVER_NAME "spi_imx"
@@ -51,6 +54,9 @@
51#define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */ 54#define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */
52#define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */ 55#define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */
53 56
57/* The maximum bytes that a sdma BD can transfer.*/
58#define MAX_SDMA_BD_BYTES (1 << 15)
59#define IMX_DMA_TIMEOUT (msecs_to_jiffies(3000))
54struct spi_imx_config { 60struct spi_imx_config {
55 unsigned int speed_hz; 61 unsigned int speed_hz;
56 unsigned int bpw; 62 unsigned int bpw;
@@ -95,6 +101,16 @@ struct spi_imx_data {
95 const void *tx_buf; 101 const void *tx_buf;
96 unsigned int txfifo; /* number of words pushed in tx FIFO */ 102 unsigned int txfifo; /* number of words pushed in tx FIFO */
97 103
104 /* DMA */
105 unsigned int dma_is_inited;
106 unsigned int dma_finished;
107 bool usedma;
108 u32 rx_wml;
109 u32 tx_wml;
110 u32 rxt_wml;
111 struct completion dma_rx_completion;
112 struct completion dma_tx_completion;
113
98 const struct spi_imx_devtype_data *devtype_data; 114 const struct spi_imx_devtype_data *devtype_data;
99 int chipselect[0]; 115 int chipselect[0];
100}; 116};
@@ -181,9 +197,21 @@ static unsigned int spi_imx_clkdiv_2(unsigned int fin,
181 return 7; 197 return 7;
182} 198}
183 199
200static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi,
201 struct spi_transfer *transfer)
202{
203 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
204
205 if (spi_imx->dma_is_inited && (transfer->len > spi_imx->rx_wml)
206 && (transfer->len > spi_imx->tx_wml))
207 return true;
208 return false;
209}
210
184#define MX51_ECSPI_CTRL 0x08 211#define MX51_ECSPI_CTRL 0x08
185#define MX51_ECSPI_CTRL_ENABLE (1 << 0) 212#define MX51_ECSPI_CTRL_ENABLE (1 << 0)
186#define MX51_ECSPI_CTRL_XCH (1 << 2) 213#define MX51_ECSPI_CTRL_XCH (1 << 2)
214#define MX51_ECSPI_CTRL_SMC (1 << 3)
187#define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4) 215#define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4)
188#define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8 216#define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8
189#define MX51_ECSPI_CTRL_PREDIV_OFFSET 12 217#define MX51_ECSPI_CTRL_PREDIV_OFFSET 12
@@ -201,6 +229,18 @@ static unsigned int spi_imx_clkdiv_2(unsigned int fin,
201#define MX51_ECSPI_INT_TEEN (1 << 0) 229#define MX51_ECSPI_INT_TEEN (1 << 0)
202#define MX51_ECSPI_INT_RREN (1 << 3) 230#define MX51_ECSPI_INT_RREN (1 << 3)
203 231
232#define MX51_ECSPI_DMA 0x14
233#define MX51_ECSPI_DMA_TX_WML_OFFSET 0
234#define MX51_ECSPI_DMA_TX_WML_MASK 0x3F
235#define MX51_ECSPI_DMA_RX_WML_OFFSET 16
236#define MX51_ECSPI_DMA_RX_WML_MASK (0x3F << 16)
237#define MX51_ECSPI_DMA_RXT_WML_OFFSET 24
238#define MX51_ECSPI_DMA_RXT_WML_MASK (0x3F << 24)
239
240#define MX51_ECSPI_DMA_TEDEN_OFFSET 7
241#define MX51_ECSPI_DMA_RXDEN_OFFSET 23
242#define MX51_ECSPI_DMA_RXTDEN_OFFSET 31
243
204#define MX51_ECSPI_STAT 0x18 244#define MX51_ECSPI_STAT 0x18
205#define MX51_ECSPI_STAT_RR (1 << 3) 245#define MX51_ECSPI_STAT_RR (1 << 3)
206 246
@@ -257,17 +297,22 @@ static void __maybe_unused mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int
257 297
258static void __maybe_unused mx51_ecspi_trigger(struct spi_imx_data *spi_imx) 298static void __maybe_unused mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
259{ 299{
260 u32 reg; 300 u32 reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
261 301
262 reg = readl(spi_imx->base + MX51_ECSPI_CTRL); 302 if (!spi_imx->usedma)
263 reg |= MX51_ECSPI_CTRL_XCH; 303 reg |= MX51_ECSPI_CTRL_XCH;
304 else if (!spi_imx->dma_finished)
305 reg |= MX51_ECSPI_CTRL_SMC;
306 else
307 reg &= ~MX51_ECSPI_CTRL_SMC;
264 writel(reg, spi_imx->base + MX51_ECSPI_CTRL); 308 writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
265} 309}
266 310
267static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx, 311static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx,
268 struct spi_imx_config *config) 312 struct spi_imx_config *config)
269{ 313{
270 u32 ctrl = MX51_ECSPI_CTRL_ENABLE, cfg = 0; 314 u32 ctrl = MX51_ECSPI_CTRL_ENABLE, cfg = 0, dma = 0;
315 u32 tx_wml_cfg, rx_wml_cfg, rxt_wml_cfg;
271 u32 clk = config->speed_hz, delay; 316 u32 clk = config->speed_hz, delay;
272 317
273 /* 318 /*
@@ -319,6 +364,30 @@ static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx,
319 else /* SCLK is _very_ slow */ 364 else /* SCLK is _very_ slow */
320 usleep_range(delay, delay + 10); 365 usleep_range(delay, delay + 10);
321 366
367 /*
368 * Configure the DMA register: setup the watermark
369 * and enable DMA request.
370 */
371 if (spi_imx->dma_is_inited) {
372 dma = readl(spi_imx->base + MX51_ECSPI_DMA);
373
374 spi_imx->tx_wml = spi_imx_get_fifosize(spi_imx) / 2;
375 spi_imx->rx_wml = spi_imx_get_fifosize(spi_imx) / 2;
376 spi_imx->rxt_wml = spi_imx_get_fifosize(spi_imx) / 2;
377 rx_wml_cfg = spi_imx->rx_wml << MX51_ECSPI_DMA_RX_WML_OFFSET;
378 tx_wml_cfg = spi_imx->tx_wml << MX51_ECSPI_DMA_TX_WML_OFFSET;
379 rxt_wml_cfg = spi_imx->rxt_wml << MX51_ECSPI_DMA_RXT_WML_OFFSET;
380 dma = (dma & ~MX51_ECSPI_DMA_TX_WML_MASK
381 & ~MX51_ECSPI_DMA_RX_WML_MASK
382 & ~MX51_ECSPI_DMA_RXT_WML_MASK)
383 | rx_wml_cfg | tx_wml_cfg | rxt_wml_cfg
384 |(1 << MX51_ECSPI_DMA_TEDEN_OFFSET)
385 |(1 << MX51_ECSPI_DMA_RXDEN_OFFSET)
386 |(1 << MX51_ECSPI_DMA_RXTDEN_OFFSET);
387
388 writel(dma, spi_imx->base + MX51_ECSPI_DMA);
389 }
390
322 return 0; 391 return 0;
323} 392}
324 393
@@ -730,7 +799,186 @@ static int spi_imx_setupxfer(struct spi_device *spi,
730 return 0; 799 return 0;
731} 800}
732 801
733static int spi_imx_transfer(struct spi_device *spi, 802static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx)
803{
804 struct spi_master *master = spi_imx->bitbang.master;
805
806 if (master->dma_rx) {
807 dma_release_channel(master->dma_rx);
808 master->dma_rx = NULL;
809 }
810
811 if (master->dma_tx) {
812 dma_release_channel(master->dma_tx);
813 master->dma_tx = NULL;
814 }
815
816 spi_imx->dma_is_inited = 0;
817}
818
819static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx,
820 struct spi_master *master,
821 const struct resource *res)
822{
823 struct dma_slave_config slave_config = {};
824 int ret;
825
826 /* Prepare for TX DMA: */
827 master->dma_tx = dma_request_slave_channel(dev, "tx");
828 if (!master->dma_tx) {
829 dev_err(dev, "cannot get the TX DMA channel!\n");
830 ret = -EINVAL;
831 goto err;
832 }
833
834 slave_config.direction = DMA_MEM_TO_DEV;
835 slave_config.dst_addr = res->start + MXC_CSPITXDATA;
836 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
837 slave_config.dst_maxburst = spi_imx_get_fifosize(spi_imx) / 2;
838 ret = dmaengine_slave_config(master->dma_tx, &slave_config);
839 if (ret) {
840 dev_err(dev, "error in TX dma configuration.\n");
841 goto err;
842 }
843
844 /* Prepare for RX : */
845 master->dma_rx = dma_request_slave_channel(dev, "rx");
846 if (!master->dma_rx) {
847 dev_dbg(dev, "cannot get the DMA channel.\n");
848 ret = -EINVAL;
849 goto err;
850 }
851
852 slave_config.direction = DMA_DEV_TO_MEM;
853 slave_config.src_addr = res->start + MXC_CSPIRXDATA;
854 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
855 slave_config.src_maxburst = spi_imx_get_fifosize(spi_imx) / 2;
856 ret = dmaengine_slave_config(master->dma_rx, &slave_config);
857 if (ret) {
858 dev_err(dev, "error in RX dma configuration.\n");
859 goto err;
860 }
861
862 init_completion(&spi_imx->dma_rx_completion);
863 init_completion(&spi_imx->dma_tx_completion);
864 master->can_dma = spi_imx_can_dma;
865 master->max_dma_len = MAX_SDMA_BD_BYTES;
866 spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX |
867 SPI_MASTER_MUST_TX;
868 spi_imx->dma_is_inited = 1;
869
870 return 0;
871err:
872 spi_imx_sdma_exit(spi_imx);
873 return ret;
874}
875
876static void spi_imx_dma_rx_callback(void *cookie)
877{
878 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
879
880 complete(&spi_imx->dma_rx_completion);
881}
882
883static void spi_imx_dma_tx_callback(void *cookie)
884{
885 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
886
887 complete(&spi_imx->dma_tx_completion);
888}
889
890static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx,
891 struct spi_transfer *transfer)
892{
893 struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL;
894 int ret;
895 u32 dma;
896 int left;
897 struct spi_master *master = spi_imx->bitbang.master;
898 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
899
900 if (tx) {
901 desc_tx = dmaengine_prep_slave_sg(master->dma_tx,
902 tx->sgl, tx->nents, DMA_TO_DEVICE,
903 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
904 if (!desc_tx)
905 goto no_dma;
906
907 desc_tx->callback = spi_imx_dma_tx_callback;
908 desc_tx->callback_param = (void *)spi_imx;
909 dmaengine_submit(desc_tx);
910 }
911
912 if (rx) {
913 desc_rx = dmaengine_prep_slave_sg(master->dma_rx,
914 rx->sgl, rx->nents, DMA_FROM_DEVICE,
915 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
916 if (!desc_rx)
917 goto no_dma;
918
919 desc_rx->callback = spi_imx_dma_rx_callback;
920 desc_rx->callback_param = (void *)spi_imx;
921 dmaengine_submit(desc_rx);
922 }
923
924 reinit_completion(&spi_imx->dma_rx_completion);
925 reinit_completion(&spi_imx->dma_tx_completion);
926
927 /* Trigger the cspi module. */
928 spi_imx->dma_finished = 0;
929
930 dma = readl(spi_imx->base + MX51_ECSPI_DMA);
931 dma = dma & (~MX51_ECSPI_DMA_RXT_WML_MASK);
932 /* Change RX_DMA_LENGTH trigger dma fetch tail data */
933 left = transfer->len % spi_imx->rxt_wml;
934 if (left)
935 writel(dma | (left << MX51_ECSPI_DMA_RXT_WML_OFFSET),
936 spi_imx->base + MX51_ECSPI_DMA);
937 spi_imx->devtype_data->trigger(spi_imx);
938
939 dma_async_issue_pending(master->dma_tx);
940 dma_async_issue_pending(master->dma_rx);
941 /* Wait SDMA to finish the data transfer.*/
942 ret = wait_for_completion_timeout(&spi_imx->dma_tx_completion,
943 IMX_DMA_TIMEOUT);
944 if (!ret) {
945 pr_warn("%s %s: I/O Error in DMA TX\n",
946 dev_driver_string(&master->dev),
947 dev_name(&master->dev));
948 dmaengine_terminate_all(master->dma_tx);
949 } else {
950 ret = wait_for_completion_timeout(&spi_imx->dma_rx_completion,
951 IMX_DMA_TIMEOUT);
952 if (!ret) {
953 pr_warn("%s %s: I/O Error in DMA RX\n",
954 dev_driver_string(&master->dev),
955 dev_name(&master->dev));
956 spi_imx->devtype_data->reset(spi_imx);
957 dmaengine_terminate_all(master->dma_rx);
958 }
959 writel(dma |
960 spi_imx->rxt_wml << MX51_ECSPI_DMA_RXT_WML_OFFSET,
961 spi_imx->base + MX51_ECSPI_DMA);
962 }
963
964 spi_imx->dma_finished = 1;
965 spi_imx->devtype_data->trigger(spi_imx);
966
967 if (!ret)
968 ret = -ETIMEDOUT;
969 else if (ret > 0)
970 ret = transfer->len;
971
972 return ret;
973
974no_dma:
975 pr_warn_once("%s %s: DMA not available, falling back to PIO\n",
976 dev_driver_string(&master->dev),
977 dev_name(&master->dev));
978 return -EAGAIN;
979}
980
981static int spi_imx_pio_transfer(struct spi_device *spi,
734 struct spi_transfer *transfer) 982 struct spi_transfer *transfer)
735{ 983{
736 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); 984 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
@@ -751,6 +999,24 @@ static int spi_imx_transfer(struct spi_device *spi,
751 return transfer->len; 999 return transfer->len;
752} 1000}
753 1001
1002static int spi_imx_transfer(struct spi_device *spi,
1003 struct spi_transfer *transfer)
1004{
1005 int ret;
1006 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1007
1008 if (spi_imx->bitbang.master->can_dma &&
1009 spi_imx_can_dma(spi_imx->bitbang.master, spi, transfer)) {
1010 spi_imx->usedma = true;
1011 ret = spi_imx_dma_transfer(spi_imx, transfer);
1012 if (ret != -EAGAIN)
1013 return ret;
1014 }
1015 spi_imx->usedma = false;
1016
1017 return spi_imx_pio_transfer(spi, transfer);
1018}
1019
754static int spi_imx_setup(struct spi_device *spi) 1020static int spi_imx_setup(struct spi_device *spi)
755{ 1021{
756 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); 1022 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
@@ -911,6 +1177,13 @@ static int spi_imx_probe(struct platform_device *pdev)
911 goto out_put_per; 1177 goto out_put_per;
912 1178
913 spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per); 1179 spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
1180 /*
1181 * Only validated on i.mx6 now, can remove the constrain if validated on
1182 * other chips.
1183 */
1184 if (spi_imx->devtype_data == &imx51_ecspi_devtype_data
1185 && spi_imx_sdma_init(&pdev->dev, spi_imx, master, res))
1186 dev_err(&pdev->dev, "dma setup error,use pio instead\n");
914 1187
915 spi_imx->devtype_data->reset(spi_imx); 1188 spi_imx->devtype_data->reset(spi_imx);
916 1189
@@ -949,6 +1222,7 @@ static int spi_imx_remove(struct platform_device *pdev)
949 writel(0, spi_imx->base + MXC_CSPICTRL); 1222 writel(0, spi_imx->base + MXC_CSPICTRL);
950 clk_unprepare(spi_imx->clk_ipg); 1223 clk_unprepare(spi_imx->clk_ipg);
951 clk_unprepare(spi_imx->clk_per); 1224 clk_unprepare(spi_imx->clk_per);
1225 spi_imx_sdma_exit(spi_imx);
952 spi_master_put(master); 1226 spi_master_put(master);
953 1227
954 return 0; 1228 return 0;
diff --git a/drivers/spi/spi-mxs.c b/drivers/spi/spi-mxs.c
index 74f2ba0ccf71..51460878af04 100644
--- a/drivers/spi/spi-mxs.c
+++ b/drivers/spi/spi-mxs.c
@@ -154,12 +154,14 @@ static int mxs_ssp_wait(struct mxs_spi *spi, int offset, int mask, bool set)
154static void mxs_ssp_dma_irq_callback(void *param) 154static void mxs_ssp_dma_irq_callback(void *param)
155{ 155{
156 struct mxs_spi *spi = param; 156 struct mxs_spi *spi = param;
157
157 complete(&spi->c); 158 complete(&spi->c);
158} 159}
159 160
160static irqreturn_t mxs_ssp_irq_handler(int irq, void *dev_id) 161static irqreturn_t mxs_ssp_irq_handler(int irq, void *dev_id)
161{ 162{
162 struct mxs_ssp *ssp = dev_id; 163 struct mxs_ssp *ssp = dev_id;
164
163 dev_err(ssp->dev, "%s[%i] CTRL1=%08x STATUS=%08x\n", 165 dev_err(ssp->dev, "%s[%i] CTRL1=%08x STATUS=%08x\n",
164 __func__, __LINE__, 166 __func__, __LINE__,
165 readl(ssp->base + HW_SSP_CTRL1(ssp)), 167 readl(ssp->base + HW_SSP_CTRL1(ssp)),
@@ -189,7 +191,7 @@ static int mxs_spi_txrx_dma(struct mxs_spi *spi,
189 if (!len) 191 if (!len)
190 return -EINVAL; 192 return -EINVAL;
191 193
192 dma_xfer = kzalloc(sizeof(*dma_xfer) * sgs, GFP_KERNEL); 194 dma_xfer = kcalloc(sgs, sizeof(*dma_xfer), GFP_KERNEL);
193 if (!dma_xfer) 195 if (!dma_xfer)
194 return -ENOMEM; 196 return -ENOMEM;
195 197
diff --git a/drivers/spi/spi-omap-100k.c b/drivers/spi/spi-omap-100k.c
index 5e91858f6f01..fb522765ce5a 100644
--- a/drivers/spi/spi-omap-100k.c
+++ b/drivers/spi/spi-omap-100k.c
@@ -70,10 +70,6 @@
70#define SPI_STATUS_WE (1UL << 1) 70#define SPI_STATUS_WE (1UL << 1)
71#define SPI_STATUS_RD (1UL << 0) 71#define SPI_STATUS_RD (1UL << 0)
72 72
73#define WRITE 0
74#define READ 1
75
76
77/* use PIO for small transfers, avoiding DMA setup/teardown overhead and 73/* use PIO for small transfers, avoiding DMA setup/teardown overhead and
78 * cache operations; better heuristics consider wordsize and bitrate. 74 * cache operations; better heuristics consider wordsize and bitrate.
79 */ 75 */
diff --git a/drivers/spi/spi-omap2-mcspi.c b/drivers/spi/spi-omap2-mcspi.c
index 68441fa448de..352eed7463ac 100644
--- a/drivers/spi/spi-omap2-mcspi.c
+++ b/drivers/spi/spi-omap2-mcspi.c
@@ -329,7 +329,8 @@ static void omap2_mcspi_set_fifo(const struct spi_device *spi,
329disable_fifo: 329disable_fifo:
330 if (t->rx_buf != NULL) 330 if (t->rx_buf != NULL)
331 chconf &= ~OMAP2_MCSPI_CHCONF_FFER; 331 chconf &= ~OMAP2_MCSPI_CHCONF_FFER;
332 else 332
333 if (t->tx_buf != NULL)
333 chconf &= ~OMAP2_MCSPI_CHCONF_FFET; 334 chconf &= ~OMAP2_MCSPI_CHCONF_FFET;
334 335
335 mcspi_write_chconf0(spi, chconf); 336 mcspi_write_chconf0(spi, chconf);
diff --git a/drivers/spi/spi-orion.c b/drivers/spi/spi-orion.c
index c4675fa8b645..835cdda6f4f5 100644
--- a/drivers/spi/spi-orion.c
+++ b/drivers/spi/spi-orion.c
@@ -18,6 +18,7 @@
18#include <linux/module.h> 18#include <linux/module.h>
19#include <linux/pm_runtime.h> 19#include <linux/pm_runtime.h>
20#include <linux/of.h> 20#include <linux/of.h>
21#include <linux/of_device.h>
21#include <linux/clk.h> 22#include <linux/clk.h>
22#include <linux/sizes.h> 23#include <linux/sizes.h>
23#include <asm/unaligned.h> 24#include <asm/unaligned.h>
@@ -40,13 +41,27 @@
40#define ORION_SPI_MODE_CPHA (1 << 12) 41#define ORION_SPI_MODE_CPHA (1 << 12)
41#define ORION_SPI_IF_8_16_BIT_MODE (1 << 5) 42#define ORION_SPI_IF_8_16_BIT_MODE (1 << 5)
42#define ORION_SPI_CLK_PRESCALE_MASK 0x1F 43#define ORION_SPI_CLK_PRESCALE_MASK 0x1F
44#define ARMADA_SPI_CLK_PRESCALE_MASK 0xDF
43#define ORION_SPI_MODE_MASK (ORION_SPI_MODE_CPOL | \ 45#define ORION_SPI_MODE_MASK (ORION_SPI_MODE_CPOL | \
44 ORION_SPI_MODE_CPHA) 46 ORION_SPI_MODE_CPHA)
45 47
48enum orion_spi_type {
49 ORION_SPI,
50 ARMADA_SPI,
51};
52
53struct orion_spi_dev {
54 enum orion_spi_type typ;
55 unsigned int min_divisor;
56 unsigned int max_divisor;
57 u32 prescale_mask;
58};
59
46struct orion_spi { 60struct orion_spi {
47 struct spi_master *master; 61 struct spi_master *master;
48 void __iomem *base; 62 void __iomem *base;
49 struct clk *clk; 63 struct clk *clk;
64 const struct orion_spi_dev *devdata;
50}; 65};
51 66
52static inline void __iomem *spi_reg(struct orion_spi *orion_spi, u32 reg) 67static inline void __iomem *spi_reg(struct orion_spi *orion_spi, u32 reg)
@@ -83,30 +98,66 @@ static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
83 u32 prescale; 98 u32 prescale;
84 u32 reg; 99 u32 reg;
85 struct orion_spi *orion_spi; 100 struct orion_spi *orion_spi;
101 const struct orion_spi_dev *devdata;
86 102
87 orion_spi = spi_master_get_devdata(spi->master); 103 orion_spi = spi_master_get_devdata(spi->master);
104 devdata = orion_spi->devdata;
88 105
89 tclk_hz = clk_get_rate(orion_spi->clk); 106 tclk_hz = clk_get_rate(orion_spi->clk);
90 107
91 /* 108 if (devdata->typ == ARMADA_SPI) {
92 * the supported rates are: 4,6,8...30 109 unsigned int clk, spr, sppr, sppr2, err;
93 * round up as we look for equal or less speed 110 unsigned int best_spr, best_sppr, best_err;
94 */
95 rate = DIV_ROUND_UP(tclk_hz, speed);
96 rate = roundup(rate, 2);
97 111
98 /* check if requested speed is too small */ 112 best_err = speed;
99 if (rate > 30) 113 best_spr = 0;
100 return -EINVAL; 114 best_sppr = 0;
101 115
102 if (rate < 4) 116 /* Iterate over the valid range looking for best fit */
103 rate = 4; 117 for (sppr = 0; sppr < 8; sppr++) {
118 sppr2 = 0x1 << sppr;
119
120 spr = tclk_hz / sppr2;
121 spr = DIV_ROUND_UP(spr, speed);
122 if ((spr == 0) || (spr > 15))
123 continue;
124
125 clk = tclk_hz / (spr * sppr2);
126 err = speed - clk;
127
128 if (err < best_err) {
129 best_spr = spr;
130 best_sppr = sppr;
131 best_err = err;
132 }
133 }
104 134
105 /* Convert the rate to SPI clock divisor value. */ 135 if ((best_sppr == 0) && (best_spr == 0))
106 prescale = 0x10 + rate/2; 136 return -EINVAL;
137
138 prescale = ((best_sppr & 0x6) << 5) |
139 ((best_sppr & 0x1) << 4) | best_spr;
140 } else {
141 /*
142 * the supported rates are: 4,6,8...30
143 * round up as we look for equal or less speed
144 */
145 rate = DIV_ROUND_UP(tclk_hz, speed);
146 rate = roundup(rate, 2);
147
148 /* check if requested speed is too small */
149 if (rate > 30)
150 return -EINVAL;
151
152 if (rate < 4)
153 rate = 4;
154
155 /* Convert the rate to SPI clock divisor value. */
156 prescale = 0x10 + rate/2;
157 }
107 158
108 reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); 159 reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
109 reg = ((reg & ~ORION_SPI_CLK_PRESCALE_MASK) | prescale); 160 reg = ((reg & ~devdata->prescale_mask) | prescale);
110 writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); 161 writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
111 162
112 return 0; 163 return 0;
@@ -179,8 +230,8 @@ static inline int orion_spi_wait_till_ready(struct orion_spi *orion_spi)
179 for (i = 0; i < ORION_SPI_WAIT_RDY_MAX_LOOP; i++) { 230 for (i = 0; i < ORION_SPI_WAIT_RDY_MAX_LOOP; i++) {
180 if (readl(spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG))) 231 if (readl(spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG)))
181 return 1; 232 return 1;
182 else 233
183 udelay(1); 234 udelay(1);
184 } 235 }
185 236
186 return -1; 237 return -1;
@@ -342,8 +393,31 @@ static int orion_spi_reset(struct orion_spi *orion_spi)
342 return 0; 393 return 0;
343} 394}
344 395
396static const struct orion_spi_dev orion_spi_dev_data = {
397 .typ = ORION_SPI,
398 .min_divisor = 4,
399 .max_divisor = 30,
400 .prescale_mask = ORION_SPI_CLK_PRESCALE_MASK,
401};
402
403static const struct orion_spi_dev armada_spi_dev_data = {
404 .typ = ARMADA_SPI,
405 .min_divisor = 1,
406 .max_divisor = 1920,
407 .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
408};
409
410static const struct of_device_id orion_spi_of_match_table[] = {
411 { .compatible = "marvell,orion-spi", .data = &orion_spi_dev_data, },
412 { .compatible = "marvell,armada-370-spi", .data = &armada_spi_dev_data, },
413 {}
414};
415MODULE_DEVICE_TABLE(of, orion_spi_of_match_table);
416
345static int orion_spi_probe(struct platform_device *pdev) 417static int orion_spi_probe(struct platform_device *pdev)
346{ 418{
419 const struct of_device_id *of_id;
420 const struct orion_spi_dev *devdata;
347 struct spi_master *master; 421 struct spi_master *master;
348 struct orion_spi *spi; 422 struct orion_spi *spi;
349 struct resource *r; 423 struct resource *r;
@@ -360,6 +434,7 @@ static int orion_spi_probe(struct platform_device *pdev)
360 master->bus_num = pdev->id; 434 master->bus_num = pdev->id;
361 if (pdev->dev.of_node) { 435 if (pdev->dev.of_node) {
362 u32 cell_index; 436 u32 cell_index;
437
363 if (!of_property_read_u32(pdev->dev.of_node, "cell-index", 438 if (!of_property_read_u32(pdev->dev.of_node, "cell-index",
364 &cell_index)) 439 &cell_index))
365 master->bus_num = cell_index; 440 master->bus_num = cell_index;
@@ -378,6 +453,10 @@ static int orion_spi_probe(struct platform_device *pdev)
378 spi = spi_master_get_devdata(master); 453 spi = spi_master_get_devdata(master);
379 spi->master = master; 454 spi->master = master;
380 455
456 of_id = of_match_device(orion_spi_of_match_table, &pdev->dev);
457 devdata = of_id->data;
458 spi->devdata = devdata;
459
381 spi->clk = devm_clk_get(&pdev->dev, NULL); 460 spi->clk = devm_clk_get(&pdev->dev, NULL);
382 if (IS_ERR(spi->clk)) { 461 if (IS_ERR(spi->clk)) {
383 status = PTR_ERR(spi->clk); 462 status = PTR_ERR(spi->clk);
@@ -389,8 +468,8 @@ static int orion_spi_probe(struct platform_device *pdev)
389 goto out; 468 goto out;
390 469
391 tclk_hz = clk_get_rate(spi->clk); 470 tclk_hz = clk_get_rate(spi->clk);
392 master->max_speed_hz = DIV_ROUND_UP(tclk_hz, 4); 471 master->max_speed_hz = DIV_ROUND_UP(tclk_hz, devdata->min_divisor);
393 master->min_speed_hz = DIV_ROUND_UP(tclk_hz, 30); 472 master->min_speed_hz = DIV_ROUND_UP(tclk_hz, devdata->max_divisor);
394 473
395 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 474 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
396 spi->base = devm_ioremap_resource(&pdev->dev, r); 475 spi->base = devm_ioremap_resource(&pdev->dev, r);
@@ -469,12 +548,6 @@ static const struct dev_pm_ops orion_spi_pm_ops = {
469 NULL) 548 NULL)
470}; 549};
471 550
472static const struct of_device_id orion_spi_of_match_table[] = {
473 { .compatible = "marvell,orion-spi", },
474 {}
475};
476MODULE_DEVICE_TABLE(of, orion_spi_of_match_table);
477
478static struct platform_driver orion_spi_driver = { 551static struct platform_driver orion_spi_driver = {
479 .driver = { 552 .driver = {
480 .name = DRIVER_NAME, 553 .name = DRIVER_NAME,
diff --git a/drivers/spi/spi-pl022.c b/drivers/spi/spi-pl022.c
index 1189cfd96477..f1f0a587e4fc 100644
--- a/drivers/spi/spi-pl022.c
+++ b/drivers/spi/spi-pl022.c
@@ -2136,7 +2136,7 @@ static int pl022_probe(struct amba_device *adev, const struct amba_id *id)
2136 cs_gpio); 2136 cs_gpio);
2137 else if (gpio_direction_output(cs_gpio, 1)) 2137 else if (gpio_direction_output(cs_gpio, 1))
2138 dev_err(&adev->dev, 2138 dev_err(&adev->dev,
2139 "could set gpio %d as output\n", 2139 "could not set gpio %d as output\n",
2140 cs_gpio); 2140 cs_gpio);
2141 } 2141 }
2142 } 2142 }
diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c
index fe792106bdc5..46f45ca2c694 100644
--- a/drivers/spi/spi-pxa2xx.c
+++ b/drivers/spi/spi-pxa2xx.c
@@ -1074,6 +1074,7 @@ static struct acpi_device_id pxa2xx_spi_acpi_match[] = {
1074 { "INT3430", 0 }, 1074 { "INT3430", 0 },
1075 { "INT3431", 0 }, 1075 { "INT3431", 0 },
1076 { "80860F0E", 0 }, 1076 { "80860F0E", 0 },
1077 { "8086228E", 0 },
1077 { }, 1078 { },
1078}; 1079};
1079MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match); 1080MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match);
diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c
index c0743604b906..f96ea8a38d64 100644
--- a/drivers/spi/spi-rockchip.c
+++ b/drivers/spi/spi-rockchip.c
@@ -220,7 +220,7 @@ static inline void wait_for_idle(struct rockchip_spi *rs)
220 do { 220 do {
221 if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY)) 221 if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY))
222 return; 222 return;
223 } while (time_before(jiffies, timeout)); 223 } while (!time_after(jiffies, timeout));
224 224
225 dev_warn(rs->dev, "spi controller is in busy state!\n"); 225 dev_warn(rs->dev, "spi controller is in busy state!\n");
226} 226}
@@ -415,7 +415,7 @@ static void rockchip_spi_dma_txcb(void *data)
415 spin_unlock_irqrestore(&rs->lock, flags); 415 spin_unlock_irqrestore(&rs->lock, flags);
416} 416}
417 417
418static int rockchip_spi_dma_transfer(struct rockchip_spi *rs) 418static void rockchip_spi_prepare_dma(struct rockchip_spi *rs)
419{ 419{
420 unsigned long flags; 420 unsigned long flags;
421 struct dma_slave_config rxconf, txconf; 421 struct dma_slave_config rxconf, txconf;
@@ -474,8 +474,6 @@ static int rockchip_spi_dma_transfer(struct rockchip_spi *rs)
474 dmaengine_submit(txdesc); 474 dmaengine_submit(txdesc);
475 dma_async_issue_pending(rs->dma_tx.ch); 475 dma_async_issue_pending(rs->dma_tx.ch);
476 } 476 }
477
478 return 1;
479} 477}
480 478
481static void rockchip_spi_config(struct rockchip_spi *rs) 479static void rockchip_spi_config(struct rockchip_spi *rs)
@@ -499,7 +497,7 @@ static void rockchip_spi_config(struct rockchip_spi *rs)
499 } 497 }
500 498
501 /* div doesn't support odd number */ 499 /* div doesn't support odd number */
502 div = rs->max_freq / rs->speed; 500 div = max_t(u32, rs->max_freq / rs->speed, 1);
503 div = (div + 1) & 0xfffe; 501 div = (div + 1) & 0xfffe;
504 502
505 spi_enable_chip(rs, 0); 503 spi_enable_chip(rs, 0);
@@ -529,7 +527,8 @@ static int rockchip_spi_transfer_one(
529 int ret = 0; 527 int ret = 0;
530 struct rockchip_spi *rs = spi_master_get_devdata(master); 528 struct rockchip_spi *rs = spi_master_get_devdata(master);
531 529
532 WARN_ON((readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY)); 530 WARN_ON(readl_relaxed(rs->regs + ROCKCHIP_SPI_SSIENR) &&
531 (readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY));
533 532
534 if (!xfer->tx_buf && !xfer->rx_buf) { 533 if (!xfer->tx_buf && !xfer->rx_buf) {
535 dev_err(rs->dev, "No buffer for transfer\n"); 534 dev_err(rs->dev, "No buffer for transfer\n");
@@ -556,16 +555,17 @@ static int rockchip_spi_transfer_one(
556 else if (rs->rx) 555 else if (rs->rx)
557 rs->tmode = CR0_XFM_RO; 556 rs->tmode = CR0_XFM_RO;
558 557
559 if (master->can_dma && master->can_dma(master, spi, xfer)) 558 /* we need prepare dma before spi was enabled */
559 if (master->can_dma && master->can_dma(master, spi, xfer)) {
560 rs->use_dma = 1; 560 rs->use_dma = 1;
561 else 561 rockchip_spi_prepare_dma(rs);
562 } else {
562 rs->use_dma = 0; 563 rs->use_dma = 0;
564 }
563 565
564 rockchip_spi_config(rs); 566 rockchip_spi_config(rs);
565 567
566 if (rs->use_dma) 568 if (!rs->use_dma)
567 ret = rockchip_spi_dma_transfer(rs);
568 else
569 ret = rockchip_spi_pio_transfer(rs); 569 ret = rockchip_spi_pio_transfer(rs);
570 570
571 return ret; 571 return ret;
@@ -678,7 +678,7 @@ static int rockchip_spi_probe(struct platform_device *pdev)
678 rs->dma_tx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_TXDR); 678 rs->dma_tx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_TXDR);
679 rs->dma_rx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_RXDR); 679 rs->dma_rx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_RXDR);
680 rs->dma_tx.direction = DMA_MEM_TO_DEV; 680 rs->dma_tx.direction = DMA_MEM_TO_DEV;
681 rs->dma_tx.direction = DMA_DEV_TO_MEM; 681 rs->dma_rx.direction = DMA_DEV_TO_MEM;
682 682
683 master->can_dma = rockchip_spi_can_dma; 683 master->can_dma = rockchip_spi_can_dma;
684 master->dma_tx = rs->dma_tx.ch; 684 master->dma_tx = rs->dma_tx.ch;
diff --git a/drivers/spi/spi-rspi.c b/drivers/spi/spi-rspi.c
index c850dfdfa9e3..ad87a98f8f68 100644
--- a/drivers/spi/spi-rspi.c
+++ b/drivers/spi/spi-rspi.c
@@ -472,25 +472,52 @@ static int rspi_dma_transfer(struct rspi_data *rspi, struct sg_table *tx,
472 dma_cookie_t cookie; 472 dma_cookie_t cookie;
473 int ret; 473 int ret;
474 474
475 if (tx) { 475 /* First prepare and submit the DMA request(s), as this may fail */
476 desc_tx = dmaengine_prep_slave_sg(rspi->master->dma_tx,
477 tx->sgl, tx->nents, DMA_TO_DEVICE,
478 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
479 if (!desc_tx)
480 goto no_dma;
481
482 irq_mask |= SPCR_SPTIE;
483 }
484 if (rx) { 476 if (rx) {
485 desc_rx = dmaengine_prep_slave_sg(rspi->master->dma_rx, 477 desc_rx = dmaengine_prep_slave_sg(rspi->master->dma_rx,
486 rx->sgl, rx->nents, DMA_FROM_DEVICE, 478 rx->sgl, rx->nents, DMA_FROM_DEVICE,
487 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 479 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
488 if (!desc_rx) 480 if (!desc_rx) {
489 goto no_dma; 481 ret = -EAGAIN;
482 goto no_dma_rx;
483 }
484
485 desc_rx->callback = rspi_dma_complete;
486 desc_rx->callback_param = rspi;
487 cookie = dmaengine_submit(desc_rx);
488 if (dma_submit_error(cookie)) {
489 ret = cookie;
490 goto no_dma_rx;
491 }
490 492
491 irq_mask |= SPCR_SPRIE; 493 irq_mask |= SPCR_SPRIE;
492 } 494 }
493 495
496 if (tx) {
497 desc_tx = dmaengine_prep_slave_sg(rspi->master->dma_tx,
498 tx->sgl, tx->nents, DMA_TO_DEVICE,
499 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
500 if (!desc_tx) {
501 ret = -EAGAIN;
502 goto no_dma_tx;
503 }
504
505 if (rx) {
506 /* No callback */
507 desc_tx->callback = NULL;
508 } else {
509 desc_tx->callback = rspi_dma_complete;
510 desc_tx->callback_param = rspi;
511 }
512 cookie = dmaengine_submit(desc_tx);
513 if (dma_submit_error(cookie)) {
514 ret = cookie;
515 goto no_dma_tx;
516 }
517
518 irq_mask |= SPCR_SPTIE;
519 }
520
494 /* 521 /*
495 * DMAC needs SPxIE, but if SPxIE is set, the IRQ routine will be 522 * DMAC needs SPxIE, but if SPxIE is set, the IRQ routine will be
496 * called. So, this driver disables the IRQ while DMA transfer. 523 * called. So, this driver disables the IRQ while DMA transfer.
@@ -503,34 +530,24 @@ static int rspi_dma_transfer(struct rspi_data *rspi, struct sg_table *tx,
503 rspi_enable_irq(rspi, irq_mask); 530 rspi_enable_irq(rspi, irq_mask);
504 rspi->dma_callbacked = 0; 531 rspi->dma_callbacked = 0;
505 532
506 if (rx) { 533 /* Now start DMA */
507 desc_rx->callback = rspi_dma_complete; 534 if (rx)
508 desc_rx->callback_param = rspi;
509 cookie = dmaengine_submit(desc_rx);
510 if (dma_submit_error(cookie))
511 return cookie;
512 dma_async_issue_pending(rspi->master->dma_rx); 535 dma_async_issue_pending(rspi->master->dma_rx);
513 } 536 if (tx)
514 if (tx) {
515 if (rx) {
516 /* No callback */
517 desc_tx->callback = NULL;
518 } else {
519 desc_tx->callback = rspi_dma_complete;
520 desc_tx->callback_param = rspi;
521 }
522 cookie = dmaengine_submit(desc_tx);
523 if (dma_submit_error(cookie))
524 return cookie;
525 dma_async_issue_pending(rspi->master->dma_tx); 537 dma_async_issue_pending(rspi->master->dma_tx);
526 }
527 538
528 ret = wait_event_interruptible_timeout(rspi->wait, 539 ret = wait_event_interruptible_timeout(rspi->wait,
529 rspi->dma_callbacked, HZ); 540 rspi->dma_callbacked, HZ);
530 if (ret > 0 && rspi->dma_callbacked) 541 if (ret > 0 && rspi->dma_callbacked)
531 ret = 0; 542 ret = 0;
532 else if (!ret) 543 else if (!ret) {
544 dev_err(&rspi->master->dev, "DMA timeout\n");
533 ret = -ETIMEDOUT; 545 ret = -ETIMEDOUT;
546 if (tx)
547 dmaengine_terminate_all(rspi->master->dma_tx);
548 if (rx)
549 dmaengine_terminate_all(rspi->master->dma_rx);
550 }
534 551
535 rspi_disable_irq(rspi, irq_mask); 552 rspi_disable_irq(rspi, irq_mask);
536 553
@@ -541,11 +558,16 @@ static int rspi_dma_transfer(struct rspi_data *rspi, struct sg_table *tx,
541 558
542 return ret; 559 return ret;
543 560
544no_dma: 561no_dma_tx:
545 pr_warn_once("%s %s: DMA not available, falling back to PIO\n", 562 if (rx)
546 dev_driver_string(&rspi->master->dev), 563 dmaengine_terminate_all(rspi->master->dma_rx);
547 dev_name(&rspi->master->dev)); 564no_dma_rx:
548 return -EAGAIN; 565 if (ret == -EAGAIN) {
566 pr_warn_once("%s %s: DMA not available, falling back to PIO\n",
567 dev_driver_string(&rspi->master->dev),
568 dev_name(&rspi->master->dev));
569 }
570 return ret;
549} 571}
550 572
551static void rspi_receive_init(const struct rspi_data *rspi) 573static void rspi_receive_init(const struct rspi_data *rspi)
diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c
index 2a4354dcd661..543075b80f16 100644
--- a/drivers/spi/spi-sh-msiof.c
+++ b/drivers/spi/spi-sh-msiof.c
@@ -636,48 +636,38 @@ static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx,
636 dma_cookie_t cookie; 636 dma_cookie_t cookie;
637 int ret; 637 int ret;
638 638
639 if (tx) { 639 /* First prepare and submit the DMA request(s), as this may fail */
640 ier_bits |= IER_TDREQE | IER_TDMAE;
641 dma_sync_single_for_device(p->master->dma_tx->device->dev,
642 p->tx_dma_addr, len, DMA_TO_DEVICE);
643 desc_tx = dmaengine_prep_slave_single(p->master->dma_tx,
644 p->tx_dma_addr, len, DMA_TO_DEVICE,
645 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
646 if (!desc_tx)
647 return -EAGAIN;
648 }
649
650 if (rx) { 640 if (rx) {
651 ier_bits |= IER_RDREQE | IER_RDMAE; 641 ier_bits |= IER_RDREQE | IER_RDMAE;
652 desc_rx = dmaengine_prep_slave_single(p->master->dma_rx, 642 desc_rx = dmaengine_prep_slave_single(p->master->dma_rx,
653 p->rx_dma_addr, len, DMA_FROM_DEVICE, 643 p->rx_dma_addr, len, DMA_FROM_DEVICE,
654 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 644 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
655 if (!desc_rx) 645 if (!desc_rx) {
656 return -EAGAIN; 646 ret = -EAGAIN;
657 } 647 goto no_dma_rx;
658 648 }
659 /* 1 stage FIFO watermarks for DMA */
660 sh_msiof_write(p, FCTR, FCTR_TFWM_1 | FCTR_RFWM_1);
661
662 /* setup msiof transfer mode registers (32-bit words) */
663 sh_msiof_spi_set_mode_regs(p, tx, rx, 32, len / 4);
664
665 sh_msiof_write(p, IER, ier_bits);
666
667 reinit_completion(&p->done);
668 649
669 if (rx) {
670 desc_rx->callback = sh_msiof_dma_complete; 650 desc_rx->callback = sh_msiof_dma_complete;
671 desc_rx->callback_param = p; 651 desc_rx->callback_param = p;
672 cookie = dmaengine_submit(desc_rx); 652 cookie = dmaengine_submit(desc_rx);
673 if (dma_submit_error(cookie)) { 653 if (dma_submit_error(cookie)) {
674 ret = cookie; 654 ret = cookie;
675 goto stop_ier; 655 goto no_dma_rx;
676 } 656 }
677 dma_async_issue_pending(p->master->dma_rx);
678 } 657 }
679 658
680 if (tx) { 659 if (tx) {
660 ier_bits |= IER_TDREQE | IER_TDMAE;
661 dma_sync_single_for_device(p->master->dma_tx->device->dev,
662 p->tx_dma_addr, len, DMA_TO_DEVICE);
663 desc_tx = dmaengine_prep_slave_single(p->master->dma_tx,
664 p->tx_dma_addr, len, DMA_TO_DEVICE,
665 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
666 if (!desc_tx) {
667 ret = -EAGAIN;
668 goto no_dma_tx;
669 }
670
681 if (rx) { 671 if (rx) {
682 /* No callback */ 672 /* No callback */
683 desc_tx->callback = NULL; 673 desc_tx->callback = NULL;
@@ -688,15 +678,30 @@ static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx,
688 cookie = dmaengine_submit(desc_tx); 678 cookie = dmaengine_submit(desc_tx);
689 if (dma_submit_error(cookie)) { 679 if (dma_submit_error(cookie)) {
690 ret = cookie; 680 ret = cookie;
691 goto stop_rx; 681 goto no_dma_tx;
692 } 682 }
693 dma_async_issue_pending(p->master->dma_tx);
694 } 683 }
695 684
685 /* 1 stage FIFO watermarks for DMA */
686 sh_msiof_write(p, FCTR, FCTR_TFWM_1 | FCTR_RFWM_1);
687
688 /* setup msiof transfer mode registers (32-bit words) */
689 sh_msiof_spi_set_mode_regs(p, tx, rx, 32, len / 4);
690
691 sh_msiof_write(p, IER, ier_bits);
692
693 reinit_completion(&p->done);
694
695 /* Now start DMA */
696 if (rx)
697 dma_async_issue_pending(p->master->dma_rx);
698 if (tx)
699 dma_async_issue_pending(p->master->dma_tx);
700
696 ret = sh_msiof_spi_start(p, rx); 701 ret = sh_msiof_spi_start(p, rx);
697 if (ret) { 702 if (ret) {
698 dev_err(&p->pdev->dev, "failed to start hardware\n"); 703 dev_err(&p->pdev->dev, "failed to start hardware\n");
699 goto stop_tx; 704 goto stop_dma;
700 } 705 }
701 706
702 /* wait for tx fifo to be emptied / rx fifo to be filled */ 707 /* wait for tx fifo to be emptied / rx fifo to be filled */
@@ -726,14 +731,14 @@ static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx,
726stop_reset: 731stop_reset:
727 sh_msiof_reset_str(p); 732 sh_msiof_reset_str(p);
728 sh_msiof_spi_stop(p, rx); 733 sh_msiof_spi_stop(p, rx);
729stop_tx: 734stop_dma:
730 if (tx) 735 if (tx)
731 dmaengine_terminate_all(p->master->dma_tx); 736 dmaengine_terminate_all(p->master->dma_tx);
732stop_rx: 737no_dma_tx:
733 if (rx) 738 if (rx)
734 dmaengine_terminate_all(p->master->dma_rx); 739 dmaengine_terminate_all(p->master->dma_rx);
735stop_ier:
736 sh_msiof_write(p, IER, 0); 740 sh_msiof_write(p, IER, 0);
741no_dma_rx:
737 return ret; 742 return ret;
738} 743}
739 744
diff --git a/drivers/spi/spi-sirf.c b/drivers/spi/spi-sirf.c
index 95ac276eaafe..6f0602fd7401 100644
--- a/drivers/spi/spi-sirf.c
+++ b/drivers/spi/spi-sirf.c
@@ -312,6 +312,8 @@ static int spi_sirfsoc_cmd_transfer(struct spi_device *spi,
312 u32 cmd; 312 u32 cmd;
313 313
314 sspi = spi_master_get_devdata(spi->master); 314 sspi = spi_master_get_devdata(spi->master);
315 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
316 writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
315 memcpy(&cmd, sspi->tx, t->len); 317 memcpy(&cmd, sspi->tx, t->len);
316 if (sspi->word_width == 1 && !(spi->mode & SPI_LSB_FIRST)) 318 if (sspi->word_width == 1 && !(spi->mode & SPI_LSB_FIRST))
317 cmd = cpu_to_be32(cmd) >> 319 cmd = cpu_to_be32(cmd) >>
@@ -438,7 +440,8 @@ static void spi_sirfsoc_pio_transfer(struct spi_device *spi,
438 sspi->tx_word(sspi); 440 sspi->tx_word(sspi);
439 writel(SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN | 441 writel(SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN |
440 SIRFSOC_SPI_TX_UFLOW_INT_EN | 442 SIRFSOC_SPI_TX_UFLOW_INT_EN |
441 SIRFSOC_SPI_RX_OFLOW_INT_EN, 443 SIRFSOC_SPI_RX_OFLOW_INT_EN |
444 SIRFSOC_SPI_RX_IO_DMA_INT_EN,
442 sspi->base + SIRFSOC_SPI_INT_EN); 445 sspi->base + SIRFSOC_SPI_INT_EN);
443 writel(SIRFSOC_SPI_RX_EN | SIRFSOC_SPI_TX_EN, 446 writel(SIRFSOC_SPI_RX_EN | SIRFSOC_SPI_TX_EN,
444 sspi->base + SIRFSOC_SPI_TX_RX_EN); 447 sspi->base + SIRFSOC_SPI_TX_RX_EN);
diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c
index e4a85ada861d..795bcbc0131b 100644
--- a/drivers/spi/spi-tegra114.c
+++ b/drivers/spi/spi-tegra114.c
@@ -302,6 +302,7 @@ static unsigned tegra_spi_fill_tx_fifo_from_client_txbuf(
302 max_n_32bit = DIV_ROUND_UP(nbytes, 4); 302 max_n_32bit = DIV_ROUND_UP(nbytes, 4);
303 for (count = 0; count < max_n_32bit; count++) { 303 for (count = 0; count < max_n_32bit; count++) {
304 u32 x = 0; 304 u32 x = 0;
305
305 for (i = 0; (i < 4) && nbytes; i++, nbytes--) 306 for (i = 0; (i < 4) && nbytes; i++, nbytes--)
306 x |= (u32)(*tx_buf++) << (i * 8); 307 x |= (u32)(*tx_buf++) << (i * 8);
307 tegra_spi_writel(tspi, x, SPI_TX_FIFO); 308 tegra_spi_writel(tspi, x, SPI_TX_FIFO);
@@ -312,6 +313,7 @@ static unsigned tegra_spi_fill_tx_fifo_from_client_txbuf(
312 nbytes = written_words * tspi->bytes_per_word; 313 nbytes = written_words * tspi->bytes_per_word;
313 for (count = 0; count < max_n_32bit; count++) { 314 for (count = 0; count < max_n_32bit; count++) {
314 u32 x = 0; 315 u32 x = 0;
316
315 for (i = 0; nbytes && (i < tspi->bytes_per_word); 317 for (i = 0; nbytes && (i < tspi->bytes_per_word);
316 i++, nbytes--) 318 i++, nbytes--)
317 x |= (u32)(*tx_buf++) << (i * 8); 319 x |= (u32)(*tx_buf++) << (i * 8);
@@ -338,6 +340,7 @@ static unsigned int tegra_spi_read_rx_fifo_to_client_rxbuf(
338 len = tspi->curr_dma_words * tspi->bytes_per_word; 340 len = tspi->curr_dma_words * tspi->bytes_per_word;
339 for (count = 0; count < rx_full_count; count++) { 341 for (count = 0; count < rx_full_count; count++) {
340 u32 x = tegra_spi_readl(tspi, SPI_RX_FIFO); 342 u32 x = tegra_spi_readl(tspi, SPI_RX_FIFO);
343
341 for (i = 0; len && (i < 4); i++, len--) 344 for (i = 0; len && (i < 4); i++, len--)
342 *rx_buf++ = (x >> i*8) & 0xFF; 345 *rx_buf++ = (x >> i*8) & 0xFF;
343 } 346 }
@@ -345,8 +348,10 @@ static unsigned int tegra_spi_read_rx_fifo_to_client_rxbuf(
345 read_words += tspi->curr_dma_words; 348 read_words += tspi->curr_dma_words;
346 } else { 349 } else {
347 u32 rx_mask = ((u32)1 << t->bits_per_word) - 1; 350 u32 rx_mask = ((u32)1 << t->bits_per_word) - 1;
351
348 for (count = 0; count < rx_full_count; count++) { 352 for (count = 0; count < rx_full_count; count++) {
349 u32 x = tegra_spi_readl(tspi, SPI_RX_FIFO) & rx_mask; 353 u32 x = tegra_spi_readl(tspi, SPI_RX_FIFO) & rx_mask;
354
350 for (i = 0; (i < tspi->bytes_per_word); i++) 355 for (i = 0; (i < tspi->bytes_per_word); i++)
351 *rx_buf++ = (x >> (i*8)) & 0xFF; 356 *rx_buf++ = (x >> (i*8)) & 0xFF;
352 } 357 }
@@ -365,6 +370,7 @@ static void tegra_spi_copy_client_txbuf_to_spi_txbuf(
365 370
366 if (tspi->is_packed) { 371 if (tspi->is_packed) {
367 unsigned len = tspi->curr_dma_words * tspi->bytes_per_word; 372 unsigned len = tspi->curr_dma_words * tspi->bytes_per_word;
373
368 memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len); 374 memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len);
369 } else { 375 } else {
370 unsigned int i; 376 unsigned int i;
@@ -374,6 +380,7 @@ static void tegra_spi_copy_client_txbuf_to_spi_txbuf(
374 380
375 for (count = 0; count < tspi->curr_dma_words; count++) { 381 for (count = 0; count < tspi->curr_dma_words; count++) {
376 u32 x = 0; 382 u32 x = 0;
383
377 for (i = 0; consume && (i < tspi->bytes_per_word); 384 for (i = 0; consume && (i < tspi->bytes_per_word);
378 i++, consume--) 385 i++, consume--)
379 x |= (u32)(*tx_buf++) << (i * 8); 386 x |= (u32)(*tx_buf++) << (i * 8);
@@ -396,6 +403,7 @@ static void tegra_spi_copy_spi_rxbuf_to_client_rxbuf(
396 403
397 if (tspi->is_packed) { 404 if (tspi->is_packed) {
398 unsigned len = tspi->curr_dma_words * tspi->bytes_per_word; 405 unsigned len = tspi->curr_dma_words * tspi->bytes_per_word;
406
399 memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_dma_buf, len); 407 memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_dma_buf, len);
400 } else { 408 } else {
401 unsigned int i; 409 unsigned int i;
@@ -405,6 +413,7 @@ static void tegra_spi_copy_spi_rxbuf_to_client_rxbuf(
405 413
406 for (count = 0; count < tspi->curr_dma_words; count++) { 414 for (count = 0; count < tspi->curr_dma_words; count++) {
407 u32 x = tspi->rx_dma_buf[count] & rx_mask; 415 u32 x = tspi->rx_dma_buf[count] & rx_mask;
416
408 for (i = 0; (i < tspi->bytes_per_word); i++) 417 for (i = 0; (i < tspi->bytes_per_word); i++)
409 *rx_buf++ = (x >> (i*8)) & 0xFF; 418 *rx_buf++ = (x >> (i*8)) & 0xFF;
410 } 419 }
diff --git a/drivers/spi/spi-tegra20-sflash.c b/drivers/spi/spi-tegra20-sflash.c
index 3548ce25c08f..cd66fe7b78a9 100644
--- a/drivers/spi/spi-tegra20-sflash.c
+++ b/drivers/spi/spi-tegra20-sflash.c
@@ -99,7 +99,7 @@
99#define SPI_TX_TRIG_MASK (0x3 << 16) 99#define SPI_TX_TRIG_MASK (0x3 << 16)
100#define SPI_TX_TRIG_1W (0x0 << 16) 100#define SPI_TX_TRIG_1W (0x0 << 16)
101#define SPI_TX_TRIG_4W (0x1 << 16) 101#define SPI_TX_TRIG_4W (0x1 << 16)
102#define SPI_DMA_BLK_COUNT(count) (((count) - 1) & 0xFFFF); 102#define SPI_DMA_BLK_COUNT(count) (((count) - 1) & 0xFFFF)
103 103
104#define SPI_TX_FIFO 0x10 104#define SPI_TX_FIFO 0x10
105#define SPI_RX_FIFO 0x20 105#define SPI_RX_FIFO 0x20
@@ -221,6 +221,7 @@ static int tegra_sflash_read_rx_fifo_to_client_rxbuf(
221 while (!(status & SPI_RXF_EMPTY)) { 221 while (!(status & SPI_RXF_EMPTY)) {
222 int i; 222 int i;
223 u32 x = tegra_sflash_readl(tsd, SPI_RX_FIFO); 223 u32 x = tegra_sflash_readl(tsd, SPI_RX_FIFO);
224
224 for (i = 0; (i < tsd->bytes_per_word); i++) 225 for (i = 0; (i < tsd->bytes_per_word); i++)
225 *rx_buf++ = (x >> (i*8)) & 0xFF; 226 *rx_buf++ = (x >> (i*8)) & 0xFF;
226 read_words++; 227 read_words++;
diff --git a/drivers/spi/spi-txx9.c b/drivers/spi/spi-txx9.c
index 5f183baa91a9..2501a8373e89 100644
--- a/drivers/spi/spi-txx9.c
+++ b/drivers/spi/spi-txx9.c
@@ -97,6 +97,7 @@ static void txx9spi_cs_func(struct spi_device *spi, struct txx9spi *c,
97 int on, unsigned int cs_delay) 97 int on, unsigned int cs_delay)
98{ 98{
99 int val = (spi->mode & SPI_CS_HIGH) ? on : !on; 99 int val = (spi->mode & SPI_CS_HIGH) ? on : !on;
100
100 if (on) { 101 if (on) {
101 /* deselect the chip with cs_change hint in last transfer */ 102 /* deselect the chip with cs_change hint in last transfer */
102 if (c->last_chipselect >= 0) 103 if (c->last_chipselect >= 0)
@@ -188,6 +189,7 @@ static void txx9spi_work_one(struct txx9spi *c, struct spi_message *m)
188 if (prev_speed_hz != speed_hz 189 if (prev_speed_hz != speed_hz
189 || prev_bits_per_word != bits_per_word) { 190 || prev_bits_per_word != bits_per_word) {
190 int n = DIV_ROUND_UP(c->baseclk, speed_hz) - 1; 191 int n = DIV_ROUND_UP(c->baseclk, speed_hz) - 1;
192
191 n = clamp(n, SPI_MIN_DIVIDER, SPI_MAX_DIVIDER); 193 n = clamp(n, SPI_MIN_DIVIDER, SPI_MAX_DIVIDER);
192 /* enter config mode */ 194 /* enter config mode */
193 txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR, 195 txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR,
diff --git a/drivers/spi/spi-xtensa-xtfpga.c b/drivers/spi/spi-xtensa-xtfpga.c
index 41e158187f9d..0dc5df5233a9 100644
--- a/drivers/spi/spi-xtensa-xtfpga.c
+++ b/drivers/spi/spi-xtensa-xtfpga.c
@@ -46,6 +46,7 @@ static inline unsigned int xtfpga_spi_read32(const struct xtfpga_spi *spi,
46static inline void xtfpga_spi_wait_busy(struct xtfpga_spi *xspi) 46static inline void xtfpga_spi_wait_busy(struct xtfpga_spi *xspi)
47{ 47{
48 unsigned i; 48 unsigned i;
49
49 for (i = 0; xtfpga_spi_read32(xspi, XTFPGA_SPI_BUSY) && 50 for (i = 0; xtfpga_spi_read32(xspi, XTFPGA_SPI_BUSY) &&
50 i < BUSY_WAIT_US; ++i) 51 i < BUSY_WAIT_US; ++i)
51 udelay(1); 52 udelay(1);
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index e0531baf2782..e19512ffc40e 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -552,6 +552,9 @@ int spi_register_board_info(struct spi_board_info const *info, unsigned n)
552 struct boardinfo *bi; 552 struct boardinfo *bi;
553 int i; 553 int i;
554 554
555 if (!n)
556 return -EINVAL;
557
555 bi = kzalloc(n * sizeof(*bi), GFP_KERNEL); 558 bi = kzalloc(n * sizeof(*bi), GFP_KERNEL);
556 if (!bi) 559 if (!bi)
557 return -ENOMEM; 560 return -ENOMEM;
@@ -789,27 +792,35 @@ static int spi_transfer_one_message(struct spi_master *master,
789 list_for_each_entry(xfer, &msg->transfers, transfer_list) { 792 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
790 trace_spi_transfer_start(msg, xfer); 793 trace_spi_transfer_start(msg, xfer);
791 794
792 reinit_completion(&master->xfer_completion); 795 if (xfer->tx_buf || xfer->rx_buf) {
796 reinit_completion(&master->xfer_completion);
793 797
794 ret = master->transfer_one(master, msg->spi, xfer); 798 ret = master->transfer_one(master, msg->spi, xfer);
795 if (ret < 0) { 799 if (ret < 0) {
796 dev_err(&msg->spi->dev, 800 dev_err(&msg->spi->dev,
797 "SPI transfer failed: %d\n", ret); 801 "SPI transfer failed: %d\n", ret);
798 goto out; 802 goto out;
799 } 803 }
800 804
801 if (ret > 0) { 805 if (ret > 0) {
802 ret = 0; 806 ret = 0;
803 ms = xfer->len * 8 * 1000 / xfer->speed_hz; 807 ms = xfer->len * 8 * 1000 / xfer->speed_hz;
804 ms += ms + 100; /* some tolerance */ 808 ms += ms + 100; /* some tolerance */
805 809
806 ms = wait_for_completion_timeout(&master->xfer_completion, 810 ms = wait_for_completion_timeout(&master->xfer_completion,
807 msecs_to_jiffies(ms)); 811 msecs_to_jiffies(ms));
808 } 812 }
809 813
810 if (ms == 0) { 814 if (ms == 0) {
811 dev_err(&msg->spi->dev, "SPI transfer timed out\n"); 815 dev_err(&msg->spi->dev,
812 msg->status = -ETIMEDOUT; 816 "SPI transfer timed out\n");
817 msg->status = -ETIMEDOUT;
818 }
819 } else {
820 if (xfer->len)
821 dev_err(&msg->spi->dev,
822 "Bufferless transfer has length %u\n",
823 xfer->len);
813 } 824 }
814 825
815 trace_spi_transfer_stop(msg, xfer); 826 trace_spi_transfer_stop(msg, xfer);
@@ -848,6 +859,7 @@ out:
848 859
849/** 860/**
850 * spi_finalize_current_transfer - report completion of a transfer 861 * spi_finalize_current_transfer - report completion of a transfer
862 * @master: the master reporting completion
851 * 863 *
852 * Called by SPI drivers using the core transfer_one_message() 864 * Called by SPI drivers using the core transfer_one_message()
853 * implementation to notify it that the current interrupt driven 865 * implementation to notify it that the current interrupt driven
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-13 13:21:01 -0500