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-rw-r--r--drivers/spi/Kconfig55
-rw-r--r--drivers/spi/Makefile5
-rw-r--r--drivers/spi/spi-altera.c7
-rw-r--r--drivers/spi/spi-ath79.c1
-rw-r--r--drivers/spi/spi-atmel.c34
-rw-r--r--drivers/spi/spi-au1550.c30
-rw-r--r--drivers/spi/spi-bcm2835.c1
-rw-r--r--drivers/spi/spi-bcm63xx-hsspi.c8
-rw-r--r--drivers/spi/spi-bcm63xx.c6
-rw-r--r--drivers/spi/spi-bfin-sport.c1
-rw-r--r--drivers/spi/spi-bfin-v3.c3
-rw-r--r--drivers/spi/spi-bfin5xx.c8
-rw-r--r--drivers/spi/spi-bitbang.c5
-rw-r--r--drivers/spi/spi-butterfly.c3
-rw-r--r--drivers/spi/spi-clps711x.c227
-rw-r--r--drivers/spi/spi-coldfire-qspi.c112
-rw-r--r--drivers/spi/spi-davinci.c14
-rw-r--r--drivers/spi/spi-dw-mmio.c2
-rw-r--r--drivers/spi/spi-dw.c17
-rw-r--r--drivers/spi/spi-efm32.c46
-rw-r--r--drivers/spi/spi-ep93xx.c21
-rw-r--r--drivers/spi/spi-falcon.c5
-rw-r--r--drivers/spi/spi-fsl-dspi.c94
-rw-r--r--drivers/spi/spi-fsl-espi.c5
-rw-r--r--drivers/spi/spi-fsl-lib.c14
-rw-r--r--drivers/spi/spi-fsl-spi.c30
-rw-r--r--drivers/spi/spi-gpio.c8
-rw-r--r--drivers/spi/spi-imx.c7
-rw-r--r--drivers/spi/spi-mpc512x-psc.c17
-rw-r--r--drivers/spi/spi-mpc52xx-psc.c1
-rw-r--r--drivers/spi/spi-mpc52xx.c17
-rw-r--r--drivers/spi/spi-mxs.c7
-rw-r--r--drivers/spi/spi-nuc900.c28
-rw-r--r--drivers/spi/spi-oc-tiny.c3
-rw-r--r--drivers/spi/spi-octeon.c80
-rw-r--r--drivers/spi/spi-omap-100k.c52
-rw-r--r--drivers/spi/spi-omap-uwire.c34
-rw-r--r--drivers/spi/spi-omap2-mcspi.c91
-rw-r--r--drivers/spi/spi-orion.c80
-rw-r--r--drivers/spi/spi-pl022.c80
-rw-r--r--drivers/spi/spi-ppc4xx.c1
-rw-r--r--drivers/spi/spi-pxa2xx-dma.c1
-rw-r--r--drivers/spi/spi-pxa2xx-pxadma.c1
-rw-r--r--drivers/spi/spi-pxa2xx.c3
-rw-r--r--drivers/spi/spi-qup.c779
-rw-r--r--drivers/spi/spi-rspi.c842
-rw-r--r--drivers/spi/spi-s3c24xx.c19
-rw-r--r--drivers/spi/spi-s3c64xx.c424
-rw-r--r--drivers/spi/spi-sc18is602.c29
-rw-r--r--drivers/spi/spi-sh-hspi.c43
-rw-r--r--drivers/spi/spi-sh-msiof.c385
-rw-r--r--drivers/spi/spi-sh-sci.c8
-rw-r--r--drivers/spi/spi-sirf.c116
-rw-r--r--drivers/spi/spi-sun4i.c478
-rw-r--r--drivers/spi/spi-sun6i.c484
-rw-r--r--drivers/spi/spi-tegra114.c27
-rw-r--r--drivers/spi/spi-tegra20-sflash.c26
-rw-r--r--drivers/spi/spi-tegra20-slink.c20
-rw-r--r--drivers/spi/spi-ti-qspi.c5
-rw-r--r--drivers/spi/spi-ti-ssp.c378
-rw-r--r--drivers/spi/spi-topcliff-pch.c47
-rw-r--r--drivers/spi/spi-txx9.c25
-rw-r--r--drivers/spi/spi-xcomm.c13
-rw-r--r--drivers/spi/spi-xilinx.c27
-rw-r--r--drivers/spi/spi-xtensa-xtfpga.c170
-rw-r--r--drivers/spi/spi.c247
-rw-r--r--drivers/spi/spidev.c23
67 files changed, 3638 insertions, 2242 deletions
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 581ee2a8856b..60f2b41c7310 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -150,7 +150,7 @@ config SPI_BUTTERFLY
150 150
151config SPI_CLPS711X 151config SPI_CLPS711X
152 tristate "CLPS711X host SPI controller" 152 tristate "CLPS711X host SPI controller"
153 depends on ARCH_CLPS711X 153 depends on ARCH_CLPS711X || COMPILE_TEST
154 help 154 help
155 This enables dedicated general purpose SPI/Microwire1-compatible 155 This enables dedicated general purpose SPI/Microwire1-compatible
156 master mode interface (SSI1) for CLPS711X-based CPUs. 156 master mode interface (SSI1) for CLPS711X-based CPUs.
@@ -212,7 +212,6 @@ config SPI_IMX
212 tristate "Freescale i.MX SPI controllers" 212 tristate "Freescale i.MX SPI controllers"
213 depends on ARCH_MXC || COMPILE_TEST 213 depends on ARCH_MXC || COMPILE_TEST
214 select SPI_BITBANG 214 select SPI_BITBANG
215 default m if IMX_HAVE_PLATFORM_SPI_IMX
216 help 215 help
217 This enables using the Freescale i.MX SPI controllers in master 216 This enables using the Freescale i.MX SPI controllers in master
218 mode. 217 mode.
@@ -270,6 +269,7 @@ config SPI_FSL_SPI
270config SPI_FSL_DSPI 269config SPI_FSL_DSPI
271 tristate "Freescale DSPI controller" 270 tristate "Freescale DSPI controller"
272 select SPI_BITBANG 271 select SPI_BITBANG
272 select REGMAP_MMIO
273 depends on SOC_VF610 || COMPILE_TEST 273 depends on SOC_VF610 || COMPILE_TEST
274 help 274 help
275 This enables support for the Freescale DSPI controller in master 275 This enables support for the Freescale DSPI controller in master
@@ -307,7 +307,7 @@ config SPI_OMAP_UWIRE
307 307
308config SPI_OMAP24XX 308config SPI_OMAP24XX
309 tristate "McSPI driver for OMAP" 309 tristate "McSPI driver for OMAP"
310 depends on ARM || ARM64 || AVR32 || HEXAGON || MIPS || SH 310 depends on ARM || ARM64 || AVR32 || HEXAGON || MIPS || SUPERH
311 depends on ARCH_OMAP2PLUS || COMPILE_TEST 311 depends on ARCH_OMAP2PLUS || COMPILE_TEST
312 help 312 help
313 SPI master controller for OMAP24XX and later Multichannel SPI 313 SPI master controller for OMAP24XX and later Multichannel SPI
@@ -381,6 +381,19 @@ config SPI_RSPI
381 help 381 help
382 SPI driver for Renesas RSPI and QSPI blocks. 382 SPI driver for Renesas RSPI and QSPI blocks.
383 383
384config SPI_QUP
385 tristate "Qualcomm SPI controller with QUP interface"
386 depends on ARCH_QCOM || (ARM && COMPILE_TEST)
387 help
388 Qualcomm Universal Peripheral (QUP) core is an AHB slave that
389 provides a common data path (an output FIFO and an input FIFO)
390 for serial peripheral interface (SPI) mini-core. SPI in master
391 mode supports up to 50MHz, up to four chip selects, programmable
392 data path from 4 bits to 32 bits and numerous protocol variants.
393
394 This driver can also be built as a module. If so, the module
395 will be called spi_qup.
396
384config SPI_S3C24XX 397config SPI_S3C24XX
385 tristate "Samsung S3C24XX series SPI" 398 tristate "Samsung S3C24XX series SPI"
386 depends on ARCH_S3C24XX 399 depends on ARCH_S3C24XX
@@ -416,7 +429,6 @@ config SPI_SH_MSIOF
416 tristate "SuperH MSIOF SPI controller" 429 tristate "SuperH MSIOF SPI controller"
417 depends on HAVE_CLK 430 depends on HAVE_CLK
418 depends on SUPERH || ARCH_SHMOBILE || COMPILE_TEST 431 depends on SUPERH || ARCH_SHMOBILE || COMPILE_TEST
419 select SPI_BITBANG
420 help 432 help
421 SPI driver for SuperH and SH Mobile MSIOF blocks. 433 SPI driver for SuperH and SH Mobile MSIOF blocks.
422 434
@@ -446,6 +458,19 @@ config SPI_SIRF
446 help 458 help
447 SPI driver for CSR SiRFprimaII SoCs 459 SPI driver for CSR SiRFprimaII SoCs
448 460
461config SPI_SUN4I
462 tristate "Allwinner A10 SoCs SPI controller"
463 depends on ARCH_SUNXI || COMPILE_TEST
464 help
465 SPI driver for Allwinner sun4i, sun5i and sun7i SoCs
466
467config SPI_SUN6I
468 tristate "Allwinner A31 SPI controller"
469 depends on ARCH_SUNXI || COMPILE_TEST
470 depends on RESET_CONTROLLER
471 help
472 This enables using the SPI controller on the Allwinner A31 SoCs.
473
449config SPI_MXS 474config SPI_MXS
450 tristate "Freescale MXS SPI controller" 475 tristate "Freescale MXS SPI controller"
451 depends on ARCH_MXS 476 depends on ARCH_MXS
@@ -478,13 +503,6 @@ config SPI_TEGRA20_SLINK
478 help 503 help
479 SPI driver for Nvidia Tegra20/Tegra30 SLINK Controller interface. 504 SPI driver for Nvidia Tegra20/Tegra30 SLINK Controller interface.
480 505
481config SPI_TI_SSP
482 tristate "TI Sequencer Serial Port - SPI Support"
483 depends on MFD_TI_SSP
484 help
485 This selects an SPI master implementation using a TI sequencer
486 serial port.
487
488config SPI_TOPCLIFF_PCH 506config SPI_TOPCLIFF_PCH
489 tristate "Intel EG20T PCH/LAPIS Semicon IOH(ML7213/ML7223/ML7831) SPI" 507 tristate "Intel EG20T PCH/LAPIS Semicon IOH(ML7213/ML7223/ML7831) SPI"
490 depends on PCI 508 depends on PCI
@@ -520,6 +538,19 @@ config SPI_XILINX
520 538
521 Or for the DS570, see "XPS Serial Peripheral Interface (SPI) (v2.00b)" 539 Or for the DS570, see "XPS Serial Peripheral Interface (SPI) (v2.00b)"
522 540
541config SPI_XTENSA_XTFPGA
542 tristate "Xtensa SPI controller for xtfpga"
543 depends on (XTENSA && XTENSA_PLATFORM_XTFPGA) || COMPILE_TEST
544 select SPI_BITBANG
545 help
546 SPI driver for xtfpga SPI master controller.
547
548 This simple SPI master controller is built into xtfpga bitstreams
549 and is used to control daughterboard audio codec. It always transfers
550 16 bit words in SPI mode 0, automatically asserting CS on transfer
551 start and deasserting on end.
552
553
523config SPI_NUC900 554config SPI_NUC900
524 tristate "Nuvoton NUC900 series SPI" 555 tristate "Nuvoton NUC900 series SPI"
525 depends on ARCH_W90X900 556 depends on ARCH_W90X900
@@ -546,7 +577,7 @@ config SPI_DW_MID_DMA
546 577
547config SPI_DW_MMIO 578config SPI_DW_MMIO
548 tristate "Memory-mapped io interface driver for DW SPI core" 579 tristate "Memory-mapped io interface driver for DW SPI core"
549 depends on SPI_DESIGNWARE && HAVE_CLK 580 depends on SPI_DESIGNWARE
550 581
551# 582#
552# There are lots of SPI device types, with sensors and memory 583# There are lots of SPI device types, with sensors and memory
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 95af48d2d360..bd792669e563 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -59,6 +59,7 @@ spi-pxa2xx-platform-$(CONFIG_SPI_PXA2XX_PXADMA) += spi-pxa2xx-pxadma.o
59spi-pxa2xx-platform-$(CONFIG_SPI_PXA2XX_DMA) += spi-pxa2xx-dma.o 59spi-pxa2xx-platform-$(CONFIG_SPI_PXA2XX_DMA) += spi-pxa2xx-dma.o
60obj-$(CONFIG_SPI_PXA2XX) += spi-pxa2xx-platform.o 60obj-$(CONFIG_SPI_PXA2XX) += spi-pxa2xx-platform.o
61obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa2xx-pci.o 61obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa2xx-pci.o
62obj-$(CONFIG_SPI_QUP) += spi-qup.o
62obj-$(CONFIG_SPI_RSPI) += spi-rspi.o 63obj-$(CONFIG_SPI_RSPI) += spi-rspi.o
63obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o 64obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o
64spi-s3c24xx-hw-y := spi-s3c24xx.o 65spi-s3c24xx-hw-y := spi-s3c24xx.o
@@ -70,12 +71,14 @@ obj-$(CONFIG_SPI_SH_HSPI) += spi-sh-hspi.o
70obj-$(CONFIG_SPI_SH_MSIOF) += spi-sh-msiof.o 71obj-$(CONFIG_SPI_SH_MSIOF) += spi-sh-msiof.o
71obj-$(CONFIG_SPI_SH_SCI) += spi-sh-sci.o 72obj-$(CONFIG_SPI_SH_SCI) += spi-sh-sci.o
72obj-$(CONFIG_SPI_SIRF) += spi-sirf.o 73obj-$(CONFIG_SPI_SIRF) += spi-sirf.o
74obj-$(CONFIG_SPI_SUN4I) += spi-sun4i.o
75obj-$(CONFIG_SPI_SUN6I) += spi-sun6i.o
73obj-$(CONFIG_SPI_TEGRA114) += spi-tegra114.o 76obj-$(CONFIG_SPI_TEGRA114) += spi-tegra114.o
74obj-$(CONFIG_SPI_TEGRA20_SFLASH) += spi-tegra20-sflash.o 77obj-$(CONFIG_SPI_TEGRA20_SFLASH) += spi-tegra20-sflash.o
75obj-$(CONFIG_SPI_TEGRA20_SLINK) += spi-tegra20-slink.o 78obj-$(CONFIG_SPI_TEGRA20_SLINK) += spi-tegra20-slink.o
76obj-$(CONFIG_SPI_TI_SSP) += spi-ti-ssp.o
77obj-$(CONFIG_SPI_TLE62X0) += spi-tle62x0.o 79obj-$(CONFIG_SPI_TLE62X0) += spi-tle62x0.o
78obj-$(CONFIG_SPI_TOPCLIFF_PCH) += spi-topcliff-pch.o 80obj-$(CONFIG_SPI_TOPCLIFF_PCH) += spi-topcliff-pch.o
79obj-$(CONFIG_SPI_TXX9) += spi-txx9.o 81obj-$(CONFIG_SPI_TXX9) += spi-txx9.o
80obj-$(CONFIG_SPI_XCOMM) += spi-xcomm.o 82obj-$(CONFIG_SPI_XCOMM) += spi-xcomm.o
81obj-$(CONFIG_SPI_XILINX) += spi-xilinx.o 83obj-$(CONFIG_SPI_XILINX) += spi-xilinx.o
84obj-$(CONFIG_SPI_XTENSA_XTFPGA) += spi-xtensa-xtfpga.o
diff --git a/drivers/spi/spi-altera.c b/drivers/spi/spi-altera.c
index 5d7deaf62867..5b5709a5c957 100644
--- a/drivers/spi/spi-altera.c
+++ b/drivers/spi/spi-altera.c
@@ -13,7 +13,6 @@
13 * published by the Free Software Foundation. 13 * published by the Free Software Foundation.
14 */ 14 */
15 15
16#include <linux/init.h>
17#include <linux/interrupt.h> 16#include <linux/interrupt.h>
18#include <linux/errno.h> 17#include <linux/errno.h>
19#include <linux/module.h> 18#include <linux/module.h>
@@ -200,7 +199,6 @@ static irqreturn_t altera_spi_irq(int irq, void *dev)
200 199
201static int altera_spi_probe(struct platform_device *pdev) 200static int altera_spi_probe(struct platform_device *pdev)
202{ 201{
203 struct altera_spi_platform_data *platp = dev_get_platdata(&pdev->dev);
204 struct altera_spi *hw; 202 struct altera_spi *hw;
205 struct spi_master *master; 203 struct spi_master *master;
206 struct resource *res; 204 struct resource *res;
@@ -214,6 +212,8 @@ static int altera_spi_probe(struct platform_device *pdev)
214 master->bus_num = pdev->id; 212 master->bus_num = pdev->id;
215 master->num_chipselect = 16; 213 master->num_chipselect = 16;
216 master->mode_bits = SPI_CS_HIGH; 214 master->mode_bits = SPI_CS_HIGH;
215 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 16);
216 master->dev.of_node = pdev->dev.of_node;
217 217
218 hw = spi_master_get_devdata(master); 218 hw = spi_master_get_devdata(master);
219 platform_set_drvdata(pdev, hw); 219 platform_set_drvdata(pdev, hw);
@@ -245,9 +245,6 @@ static int altera_spi_probe(struct platform_device *pdev)
245 if (err) 245 if (err)
246 goto exit; 246 goto exit;
247 } 247 }
248 /* find platform data */
249 if (!platp)
250 hw->bitbang.master->dev.of_node = pdev->dev.of_node;
251 248
252 /* register our spi controller */ 249 /* register our spi controller */
253 err = spi_bitbang_start(&hw->bitbang); 250 err = spi_bitbang_start(&hw->bitbang);
diff --git a/drivers/spi/spi-ath79.c b/drivers/spi/spi-ath79.c
index c3b2fb9b6713..3898b0b9ee77 100644
--- a/drivers/spi/spi-ath79.c
+++ b/drivers/spi/spi-ath79.c
@@ -14,7 +14,6 @@
14 14
15#include <linux/kernel.h> 15#include <linux/kernel.h>
16#include <linux/module.h> 16#include <linux/module.h>
17#include <linux/init.h>
18#include <linux/delay.h> 17#include <linux/delay.h>
19#include <linux/spinlock.h> 18#include <linux/spinlock.h>
20#include <linux/workqueue.h> 19#include <linux/workqueue.h>
diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
index 5d7b07f08326..8005f9869481 100644
--- a/drivers/spi/spi-atmel.c
+++ b/drivers/spi/spi-atmel.c
@@ -9,7 +9,6 @@
9 */ 9 */
10 10
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/clk.h> 12#include <linux/clk.h>
14#include <linux/module.h> 13#include <linux/module.h>
15#include <linux/platform_device.h> 14#include <linux/platform_device.h>
@@ -26,6 +25,7 @@
26 25
27#include <linux/io.h> 26#include <linux/io.h>
28#include <linux/gpio.h> 27#include <linux/gpio.h>
28#include <linux/pinctrl/consumer.h>
29 29
30/* SPI register offsets */ 30/* SPI register offsets */
31#define SPI_CR 0x0000 31#define SPI_CR 0x0000
@@ -993,13 +993,6 @@ static int atmel_spi_setup(struct spi_device *spi)
993 993
994 as = spi_master_get_devdata(spi->master); 994 as = spi_master_get_devdata(spi->master);
995 995
996 if (spi->chip_select > spi->master->num_chipselect) {
997 dev_dbg(&spi->dev,
998 "setup: invalid chipselect %u (%u defined)\n",
999 spi->chip_select, spi->master->num_chipselect);
1000 return -EINVAL;
1001 }
1002
1003 /* see notes above re chipselect */ 996 /* see notes above re chipselect */
1004 if (!atmel_spi_is_v2(as) 997 if (!atmel_spi_is_v2(as)
1005 && spi->chip_select == 0 998 && spi->chip_select == 0
@@ -1087,14 +1080,6 @@ static int atmel_spi_one_transfer(struct spi_master *master,
1087 } 1080 }
1088 } 1081 }
1089 1082
1090 if (xfer->bits_per_word > 8) {
1091 if (xfer->len % 2) {
1092 dev_dbg(&spi->dev,
1093 "buffer len should be 16 bits aligned\n");
1094 return -EINVAL;
1095 }
1096 }
1097
1098 /* 1083 /*
1099 * DMA map early, for performance (empties dcache ASAP) and 1084 * DMA map early, for performance (empties dcache ASAP) and
1100 * better fault reporting. 1085 * better fault reporting.
@@ -1221,9 +1206,6 @@ static int atmel_spi_transfer_one_message(struct spi_master *master,
1221 dev_dbg(&spi->dev, "new message %p submitted for %s\n", 1206 dev_dbg(&spi->dev, "new message %p submitted for %s\n",
1222 msg, dev_name(&spi->dev)); 1207 msg, dev_name(&spi->dev));
1223 1208
1224 if (unlikely(list_empty(&msg->transfers)))
1225 return -EINVAL;
1226
1227 atmel_spi_lock(as); 1209 atmel_spi_lock(as);
1228 cs_activate(as, spi); 1210 cs_activate(as, spi);
1229 1211
@@ -1244,10 +1226,10 @@ static int atmel_spi_transfer_one_message(struct spi_master *master,
1244 1226
1245 list_for_each_entry(xfer, &msg->transfers, transfer_list) { 1227 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1246 dev_dbg(&spi->dev, 1228 dev_dbg(&spi->dev,
1247 " xfer %p: len %u tx %p/%08x rx %p/%08x\n", 1229 " xfer %p: len %u tx %p/%pad rx %p/%pad\n",
1248 xfer, xfer->len, 1230 xfer, xfer->len,
1249 xfer->tx_buf, xfer->tx_dma, 1231 xfer->tx_buf, &xfer->tx_dma,
1250 xfer->rx_buf, xfer->rx_dma); 1232 xfer->rx_buf, &xfer->rx_dma);
1251 } 1233 }
1252 1234
1253msg_done: 1235msg_done:
@@ -1303,6 +1285,9 @@ static int atmel_spi_probe(struct platform_device *pdev)
1303 struct spi_master *master; 1285 struct spi_master *master;
1304 struct atmel_spi *as; 1286 struct atmel_spi *as;
1305 1287
1288 /* Select default pin state */
1289 pinctrl_pm_select_default_state(&pdev->dev);
1290
1306 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1291 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1307 if (!regs) 1292 if (!regs)
1308 return -ENXIO; 1293 return -ENXIO;
@@ -1465,6 +1450,9 @@ static int atmel_spi_suspend(struct device *dev)
1465 } 1450 }
1466 1451
1467 clk_disable_unprepare(as->clk); 1452 clk_disable_unprepare(as->clk);
1453
1454 pinctrl_pm_select_sleep_state(dev);
1455
1468 return 0; 1456 return 0;
1469} 1457}
1470 1458
@@ -1474,6 +1462,8 @@ static int atmel_spi_resume(struct device *dev)
1474 struct atmel_spi *as = spi_master_get_devdata(master); 1462 struct atmel_spi *as = spi_master_get_devdata(master);
1475 int ret; 1463 int ret;
1476 1464
1465 pinctrl_pm_select_default_state(dev);
1466
1477 clk_prepare_enable(as->clk); 1467 clk_prepare_enable(as->clk);
1478 1468
1479 /* Start the queue running */ 1469 /* Start the queue running */
diff --git a/drivers/spi/spi-au1550.c b/drivers/spi/spi-au1550.c
index c4141c92bcff..aafb812d7ea6 100644
--- a/drivers/spi/spi-au1550.c
+++ b/drivers/spi/spi-au1550.c
@@ -55,8 +55,6 @@ struct au1550_spi {
55 55
56 volatile psc_spi_t __iomem *regs; 56 volatile psc_spi_t __iomem *regs;
57 int irq; 57 int irq;
58 unsigned freq_max;
59 unsigned freq_min;
60 58
61 unsigned len; 59 unsigned len;
62 unsigned tx_count; 60 unsigned tx_count;
@@ -248,11 +246,8 @@ static int au1550_spi_setupxfer(struct spi_device *spi, struct spi_transfer *t)
248 hz = t->speed_hz; 246 hz = t->speed_hz;
249 } 247 }
250 248
251 if (hz > spi->max_speed_hz || hz > hw->freq_max || hz < hw->freq_min) { 249 if (!hz)
252 dev_err(&spi->dev, "setupxfer: clock rate=%d out of range\n",
253 hz);
254 return -EINVAL; 250 return -EINVAL;
255 }
256 251
257 au1550_spi_bits_handlers_set(hw, spi->bits_per_word); 252 au1550_spi_bits_handlers_set(hw, spi->bits_per_word);
258 253
@@ -287,23 +282,6 @@ static int au1550_spi_setupxfer(struct spi_device *spi, struct spi_transfer *t)
287 return 0; 282 return 0;
288} 283}
289 284
290static int au1550_spi_setup(struct spi_device *spi)
291{
292 struct au1550_spi *hw = spi_master_get_devdata(spi->master);
293
294 if (spi->max_speed_hz == 0)
295 spi->max_speed_hz = hw->freq_max;
296 if (spi->max_speed_hz > hw->freq_max
297 || spi->max_speed_hz < hw->freq_min)
298 return -EINVAL;
299 /*
300 * NOTE: cannot change speed and other hw settings immediately,
301 * otherwise sharing of spi bus is not possible,
302 * so do not call setupxfer(spi, NULL) here
303 */
304 return 0;
305}
306
307/* 285/*
308 * for dma spi transfers, we have to setup rx channel, otherwise there is 286 * for dma spi transfers, we have to setup rx channel, otherwise there is
309 * no reliable way how to recognize that spi transfer is done 287 * no reliable way how to recognize that spi transfer is done
@@ -838,7 +816,6 @@ static int au1550_spi_probe(struct platform_device *pdev)
838 hw->bitbang.master = hw->master; 816 hw->bitbang.master = hw->master;
839 hw->bitbang.setup_transfer = au1550_spi_setupxfer; 817 hw->bitbang.setup_transfer = au1550_spi_setupxfer;
840 hw->bitbang.chipselect = au1550_spi_chipsel; 818 hw->bitbang.chipselect = au1550_spi_chipsel;
841 hw->bitbang.master->setup = au1550_spi_setup;
842 hw->bitbang.txrx_bufs = au1550_spi_txrx_bufs; 819 hw->bitbang.txrx_bufs = au1550_spi_txrx_bufs;
843 820
844 if (hw->usedma) { 821 if (hw->usedma) {
@@ -909,8 +886,9 @@ static int au1550_spi_probe(struct platform_device *pdev)
909 { 886 {
910 int min_div = (2 << 0) * (2 * (4 + 1)); 887 int min_div = (2 << 0) * (2 * (4 + 1));
911 int max_div = (2 << 3) * (2 * (63 + 1)); 888 int max_div = (2 << 3) * (2 * (63 + 1));
912 hw->freq_max = hw->pdata->mainclk_hz / min_div; 889 master->max_speed_hz = hw->pdata->mainclk_hz / min_div;
913 hw->freq_min = hw->pdata->mainclk_hz / (max_div + 1) + 1; 890 master->min_speed_hz =
891 hw->pdata->mainclk_hz / (max_div + 1) + 1;
914 } 892 }
915 893
916 au1550_spi_setup_psc_as_spi(hw); 894 au1550_spi_setup_psc_as_spi(hw);
diff --git a/drivers/spi/spi-bcm2835.c b/drivers/spi/spi-bcm2835.c
index 8a89dd1f2654..69167456ec1e 100644
--- a/drivers/spi/spi-bcm2835.c
+++ b/drivers/spi/spi-bcm2835.c
@@ -315,7 +315,6 @@ static int bcm2835_spi_probe(struct platform_device *pdev)
315 315
316 master->mode_bits = BCM2835_SPI_MODE_BITS; 316 master->mode_bits = BCM2835_SPI_MODE_BITS;
317 master->bits_per_word_mask = SPI_BPW_MASK(8); 317 master->bits_per_word_mask = SPI_BPW_MASK(8);
318 master->bus_num = -1;
319 master->num_chipselect = 3; 318 master->num_chipselect = 3;
320 master->transfer_one_message = bcm2835_spi_transfer_one; 319 master->transfer_one_message = bcm2835_spi_transfer_one;
321 master->dev.of_node = pdev->dev.of_node; 320 master->dev.of_node = pdev->dev.of_node;
diff --git a/drivers/spi/spi-bcm63xx-hsspi.c b/drivers/spi/spi-bcm63xx-hsspi.c
index b528f9fc8bc0..5a211e98383b 100644
--- a/drivers/spi/spi-bcm63xx-hsspi.c
+++ b/drivers/spi/spi-bcm63xx-hsspi.c
@@ -180,7 +180,7 @@ static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t)
180 while (pending > 0) { 180 while (pending > 0) {
181 int curr_step = min_t(int, step_size, pending); 181 int curr_step = min_t(int, step_size, pending);
182 182
183 init_completion(&bs->done); 183 reinit_completion(&bs->done);
184 if (tx) { 184 if (tx) {
185 memcpy_toio(bs->fifo + HSSPI_OPCODE_LEN, tx, curr_step); 185 memcpy_toio(bs->fifo + HSSPI_OPCODE_LEN, tx, curr_step);
186 tx += curr_step; 186 tx += curr_step;
@@ -369,6 +369,7 @@ static int bcm63xx_hsspi_probe(struct platform_device *pdev)
369 bs->fifo = (u8 __iomem *)(bs->regs + HSSPI_FIFO_REG(0)); 369 bs->fifo = (u8 __iomem *)(bs->regs + HSSPI_FIFO_REG(0));
370 370
371 mutex_init(&bs->bus_mutex); 371 mutex_init(&bs->bus_mutex);
372 init_completion(&bs->done);
372 373
373 master->bus_num = HSSPI_BUS_NUM; 374 master->bus_num = HSSPI_BUS_NUM;
374 master->num_chipselect = 8; 375 master->num_chipselect = 8;
@@ -453,9 +454,8 @@ static int bcm63xx_hsspi_resume(struct device *dev)
453} 454}
454#endif 455#endif
455 456
456static const struct dev_pm_ops bcm63xx_hsspi_pm_ops = { 457static SIMPLE_DEV_PM_OPS(bcm63xx_hsspi_pm_ops, bcm63xx_hsspi_suspend,
457 SET_SYSTEM_SLEEP_PM_OPS(bcm63xx_hsspi_suspend, bcm63xx_hsspi_resume) 458 bcm63xx_hsspi_resume);
458};
459 459
460static struct platform_driver bcm63xx_hsspi_driver = { 460static struct platform_driver bcm63xx_hsspi_driver = {
461 .driver = { 461 .driver = {
diff --git a/drivers/spi/spi-bcm63xx.c b/drivers/spi/spi-bcm63xx.c
index 77286aef2adf..0250fa721cea 100644
--- a/drivers/spi/spi-bcm63xx.c
+++ b/drivers/spi/spi-bcm63xx.c
@@ -20,7 +20,6 @@
20 */ 20 */
21 21
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/init.h>
24#include <linux/clk.h> 23#include <linux/clk.h>
25#include <linux/io.h> 24#include <linux/io.h>
26#include <linux/module.h> 25#include <linux/module.h>
@@ -35,8 +34,6 @@
35 34
36#include <bcm63xx_dev_spi.h> 35#include <bcm63xx_dev_spi.h>
37 36
38#define PFX KBUILD_MODNAME
39
40#define BCM63XX_SPI_MAX_PREPEND 15 37#define BCM63XX_SPI_MAX_PREPEND 15
41 38
42struct bcm63xx_spi { 39struct bcm63xx_spi {
@@ -169,7 +166,7 @@ static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *first,
169 transfer_list); 166 transfer_list);
170 } 167 }
171 168
172 init_completion(&bs->done); 169 reinit_completion(&bs->done);
173 170
174 /* Fill in the Message control register */ 171 /* Fill in the Message control register */
175 msg_ctl = (len << SPI_BYTE_CNT_SHIFT); 172 msg_ctl = (len << SPI_BYTE_CNT_SHIFT);
@@ -353,6 +350,7 @@ static int bcm63xx_spi_probe(struct platform_device *pdev)
353 } 350 }
354 351
355 bs = spi_master_get_devdata(master); 352 bs = spi_master_get_devdata(master);
353 init_completion(&bs->done);
356 354
357 platform_set_drvdata(pdev, master); 355 platform_set_drvdata(pdev, master);
358 bs->pdev = pdev; 356 bs->pdev = pdev;
diff --git a/drivers/spi/spi-bfin-sport.c b/drivers/spi/spi-bfin-sport.c
index 38941e5920b5..f515c5e9db57 100644
--- a/drivers/spi/spi-bfin-sport.c
+++ b/drivers/spi/spi-bfin-sport.c
@@ -8,7 +8,6 @@
8 * Licensed under the GPL-2 or later. 8 * Licensed under the GPL-2 or later.
9 */ 9 */
10 10
11#include <linux/init.h>
12#include <linux/module.h> 11#include <linux/module.h>
13#include <linux/delay.h> 12#include <linux/delay.h>
14#include <linux/device.h> 13#include <linux/device.h>
diff --git a/drivers/spi/spi-bfin-v3.c b/drivers/spi/spi-bfin-v3.c
index 8f8598834b30..4089d0e0d84e 100644
--- a/drivers/spi/spi-bfin-v3.c
+++ b/drivers/spi/spi-bfin-v3.c
@@ -822,7 +822,8 @@ static int bfin_spi_probe(struct platform_device *pdev)
822 master->cleanup = bfin_spi_cleanup; 822 master->cleanup = bfin_spi_cleanup;
823 master->setup = bfin_spi_setup; 823 master->setup = bfin_spi_setup;
824 master->transfer_one_message = bfin_spi_transfer_one_message; 824 master->transfer_one_message = bfin_spi_transfer_one_message;
825 master->bits_per_word_mask = BIT(32 - 1) | BIT(16 - 1) | BIT(8 - 1); 825 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
826 SPI_BPW_MASK(8);
826 827
827 drv_data = spi_master_get_devdata(master); 828 drv_data = spi_master_get_devdata(master);
828 drv_data->master = master; 829 drv_data->master = master;
diff --git a/drivers/spi/spi-bfin5xx.c b/drivers/spi/spi-bfin5xx.c
index f0f195af75d4..55e57c3eb9bd 100644
--- a/drivers/spi/spi-bfin5xx.c
+++ b/drivers/spi/spi-bfin5xx.c
@@ -350,7 +350,6 @@ static void *bfin_spi_next_transfer(struct bfin_spi_master_data *drv_data)
350static void bfin_spi_giveback(struct bfin_spi_master_data *drv_data) 350static void bfin_spi_giveback(struct bfin_spi_master_data *drv_data)
351{ 351{
352 struct bfin_spi_slave_data *chip = drv_data->cur_chip; 352 struct bfin_spi_slave_data *chip = drv_data->cur_chip;
353 struct spi_transfer *last_transfer;
354 unsigned long flags; 353 unsigned long flags;
355 struct spi_message *msg; 354 struct spi_message *msg;
356 355
@@ -362,9 +361,6 @@ static void bfin_spi_giveback(struct bfin_spi_master_data *drv_data)
362 queue_work(drv_data->workqueue, &drv_data->pump_messages); 361 queue_work(drv_data->workqueue, &drv_data->pump_messages);
363 spin_unlock_irqrestore(&drv_data->lock, flags); 362 spin_unlock_irqrestore(&drv_data->lock, flags);
364 363
365 last_transfer = list_entry(msg->transfers.prev,
366 struct spi_transfer, transfer_list);
367
368 msg->state = NULL; 364 msg->state = NULL;
369 365
370 if (!drv_data->cs_change) 366 if (!drv_data->cs_change)
@@ -1030,10 +1026,6 @@ static int bfin_spi_setup(struct spi_device *spi)
1030 } 1026 }
1031 1027
1032 /* translate common spi framework into our register */ 1028 /* translate common spi framework into our register */
1033 if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) {
1034 dev_err(&spi->dev, "unsupported spi modes detected\n");
1035 goto error;
1036 }
1037 if (spi->mode & SPI_CPOL) 1029 if (spi->mode & SPI_CPOL)
1038 chip->ctl_reg |= BIT_CTL_CPOL; 1030 chip->ctl_reg |= BIT_CTL_CPOL;
1039 if (spi->mode & SPI_CPHA) 1031 if (spi->mode & SPI_CPHA)
diff --git a/drivers/spi/spi-bitbang.c b/drivers/spi/spi-bitbang.c
index bd222f6b677d..dc7d2c2d643e 100644
--- a/drivers/spi/spi-bitbang.c
+++ b/drivers/spi/spi-bitbang.c
@@ -16,7 +16,6 @@
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */ 17 */
18 18
19#include <linux/init.h>
20#include <linux/spinlock.h> 19#include <linux/spinlock.h>
21#include <linux/workqueue.h> 20#include <linux/workqueue.h>
22#include <linux/interrupt.h> 21#include <linux/interrupt.h>
@@ -467,11 +466,9 @@ EXPORT_SYMBOL_GPL(spi_bitbang_start);
467/** 466/**
468 * spi_bitbang_stop - stops the task providing spi communication 467 * spi_bitbang_stop - stops the task providing spi communication
469 */ 468 */
470int spi_bitbang_stop(struct spi_bitbang *bitbang) 469void spi_bitbang_stop(struct spi_bitbang *bitbang)
471{ 470{
472 spi_unregister_master(bitbang->master); 471 spi_unregister_master(bitbang->master);
473
474 return 0;
475} 472}
476EXPORT_SYMBOL_GPL(spi_bitbang_stop); 473EXPORT_SYMBOL_GPL(spi_bitbang_stop);
477 474
diff --git a/drivers/spi/spi-butterfly.c b/drivers/spi/spi-butterfly.c
index 8081f96bd1d5..ee4f91ccd8fd 100644
--- a/drivers/spi/spi-butterfly.c
+++ b/drivers/spi/spi-butterfly.c
@@ -309,7 +309,6 @@ done:
309static void butterfly_detach(struct parport *p) 309static void butterfly_detach(struct parport *p)
310{ 310{
311 struct butterfly *pp; 311 struct butterfly *pp;
312 int status;
313 312
314 /* FIXME this global is ugly ... but, how to quickly get from 313 /* FIXME this global is ugly ... but, how to quickly get from
315 * the parport to the "struct butterfly" associated with it? 314 * the parport to the "struct butterfly" associated with it?
@@ -321,7 +320,7 @@ static void butterfly_detach(struct parport *p)
321 butterfly = NULL; 320 butterfly = NULL;
322 321
323 /* stop() unregisters child devices too */ 322 /* stop() unregisters child devices too */
324 status = spi_bitbang_stop(&pp->bitbang); 323 spi_bitbang_stop(&pp->bitbang);
325 324
326 /* turn off VCC */ 325 /* turn off VCC */
327 parport_write_data(pp->port, 0); 326 parport_write_data(pp->port, 0);
diff --git a/drivers/spi/spi-clps711x.c b/drivers/spi/spi-clps711x.c
index 374ba4a48a9e..4cd62f636547 100644
--- a/drivers/spi/spi-clps711x.c
+++ b/drivers/spi/spi-clps711x.c
@@ -11,158 +11,125 @@
11 11
12#include <linux/io.h> 12#include <linux/io.h>
13#include <linux/clk.h> 13#include <linux/clk.h>
14#include <linux/init.h>
15#include <linux/gpio.h> 14#include <linux/gpio.h>
16#include <linux/delay.h> 15#include <linux/delay.h>
17#include <linux/module.h> 16#include <linux/module.h>
18#include <linux/interrupt.h> 17#include <linux/interrupt.h>
19#include <linux/platform_device.h> 18#include <linux/platform_device.h>
19#include <linux/regmap.h>
20#include <linux/mfd/syscon.h>
21#include <linux/mfd/syscon/clps711x.h>
20#include <linux/spi/spi.h> 22#include <linux/spi/spi.h>
21#include <linux/platform_data/spi-clps711x.h> 23#include <linux/platform_data/spi-clps711x.h>
22 24
23#include <mach/hardware.h>
24
25#define DRIVER_NAME "spi-clps711x" 25#define DRIVER_NAME "spi-clps711x"
26 26
27struct spi_clps711x_data { 27#define SYNCIO_FRMLEN(x) ((x) << 8)
28 struct completion done; 28#define SYNCIO_TXFRMEN (1 << 14)
29 29
30struct spi_clps711x_data {
31 void __iomem *syncio;
32 struct regmap *syscon;
33 struct regmap *syscon1;
30 struct clk *spi_clk; 34 struct clk *spi_clk;
31 u32 max_speed_hz;
32 35
33 u8 *tx_buf; 36 u8 *tx_buf;
34 u8 *rx_buf; 37 u8 *rx_buf;
35 int count; 38 unsigned int bpw;
36 int len; 39 int len;
37
38 int chipselect[0];
39}; 40};
40 41
41static int spi_clps711x_setup(struct spi_device *spi) 42static int spi_clps711x_setup(struct spi_device *spi)
42{ 43{
43 struct spi_clps711x_data *hw = spi_master_get_devdata(spi->master);
44
45 /* We are expect that SPI-device is not selected */ 44 /* We are expect that SPI-device is not selected */
46 gpio_direction_output(hw->chipselect[spi->chip_select], 45 gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
47 !(spi->mode & SPI_CS_HIGH));
48 46
49 return 0; 47 return 0;
50} 48}
51 49
52static void spi_clps711x_setup_mode(struct spi_device *spi) 50static void spi_clps711x_setup_xfer(struct spi_device *spi,
53{ 51 struct spi_transfer *xfer)
54 /* Setup edge for transfer */
55 if (spi->mode & SPI_CPHA)
56 clps_writew(clps_readw(SYSCON3) | SYSCON3_ADCCKNSEN, SYSCON3);
57 else
58 clps_writew(clps_readw(SYSCON3) & ~SYSCON3_ADCCKNSEN, SYSCON3);
59}
60
61static int spi_clps711x_setup_xfer(struct spi_device *spi,
62 struct spi_transfer *xfer)
63{ 52{
64 u32 speed = xfer->speed_hz ? : spi->max_speed_hz; 53 struct spi_master *master = spi->master;
65 u8 bpw = xfer->bits_per_word; 54 struct spi_clps711x_data *hw = spi_master_get_devdata(master);
66 struct spi_clps711x_data *hw = spi_master_get_devdata(spi->master);
67
68 if (bpw != 8) {
69 dev_err(&spi->dev, "Unsupported master bus width %i\n", bpw);
70 return -EINVAL;
71 }
72 55
73 /* Setup SPI frequency divider */ 56 /* Setup SPI frequency divider */
74 if (!speed || (speed >= hw->max_speed_hz)) 57 if (xfer->speed_hz >= master->max_speed_hz)
75 clps_writel((clps_readl(SYSCON1) & ~SYSCON1_ADCKSEL_MASK) | 58 regmap_update_bits(hw->syscon1, SYSCON_OFFSET,
76 SYSCON1_ADCKSEL(3), SYSCON1); 59 SYSCON1_ADCKSEL_MASK, SYSCON1_ADCKSEL(3));
77 else if (speed >= (hw->max_speed_hz / 2)) 60 else if (xfer->speed_hz >= (master->max_speed_hz / 2))
78 clps_writel((clps_readl(SYSCON1) & ~SYSCON1_ADCKSEL_MASK) | 61 regmap_update_bits(hw->syscon1, SYSCON_OFFSET,
79 SYSCON1_ADCKSEL(2), SYSCON1); 62 SYSCON1_ADCKSEL_MASK, SYSCON1_ADCKSEL(2));
80 else if (speed >= (hw->max_speed_hz / 8)) 63 else if (xfer->speed_hz >= (master->max_speed_hz / 8))
81 clps_writel((clps_readl(SYSCON1) & ~SYSCON1_ADCKSEL_MASK) | 64 regmap_update_bits(hw->syscon1, SYSCON_OFFSET,
82 SYSCON1_ADCKSEL(1), SYSCON1); 65 SYSCON1_ADCKSEL_MASK, SYSCON1_ADCKSEL(1));
83 else 66 else
84 clps_writel((clps_readl(SYSCON1) & ~SYSCON1_ADCKSEL_MASK) | 67 regmap_update_bits(hw->syscon1, SYSCON_OFFSET,
85 SYSCON1_ADCKSEL(0), SYSCON1); 68 SYSCON1_ADCKSEL_MASK, SYSCON1_ADCKSEL(0));
86
87 return 0;
88} 69}
89 70
90static int spi_clps711x_transfer_one_message(struct spi_master *master, 71static int spi_clps711x_prepare_message(struct spi_master *master,
91 struct spi_message *msg) 72 struct spi_message *msg)
92{ 73{
93 struct spi_clps711x_data *hw = spi_master_get_devdata(master); 74 struct spi_clps711x_data *hw = spi_master_get_devdata(master);
94 struct spi_transfer *xfer; 75 struct spi_device *spi = msg->spi;
95 int status = 0, cs = hw->chipselect[msg->spi->chip_select];
96 u32 data;
97
98 spi_clps711x_setup_mode(msg->spi);
99
100 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
101 if (spi_clps711x_setup_xfer(msg->spi, xfer)) {
102 status = -EINVAL;
103 goto out_xfr;
104 }
105 76
106 gpio_set_value(cs, !!(msg->spi->mode & SPI_CS_HIGH)); 77 /* Setup mode for transfer */
107 78 return regmap_update_bits(hw->syscon, SYSCON_OFFSET, SYSCON3_ADCCKNSEN,
108 reinit_completion(&hw->done); 79 (spi->mode & SPI_CPHA) ?
109 80 SYSCON3_ADCCKNSEN : 0);
110 hw->count = 0; 81}
111 hw->len = xfer->len;
112 hw->tx_buf = (u8 *)xfer->tx_buf;
113 hw->rx_buf = (u8 *)xfer->rx_buf;
114
115 /* Initiate transfer */
116 data = hw->tx_buf ? hw->tx_buf[hw->count] : 0;
117 clps_writel(data | SYNCIO_FRMLEN(8) | SYNCIO_TXFRMEN, SYNCIO);
118
119 wait_for_completion(&hw->done);
120 82
121 if (xfer->delay_usecs) 83static int spi_clps711x_transfer_one(struct spi_master *master,
122 udelay(xfer->delay_usecs); 84 struct spi_device *spi,
85 struct spi_transfer *xfer)
86{
87 struct spi_clps711x_data *hw = spi_master_get_devdata(master);
88 u8 data;
123 89
124 if (xfer->cs_change || 90 spi_clps711x_setup_xfer(spi, xfer);
125 list_is_last(&xfer->transfer_list, &msg->transfers))
126 gpio_set_value(cs, !(msg->spi->mode & SPI_CS_HIGH));
127 91
128 msg->actual_length += xfer->len; 92 hw->len = xfer->len;
129 } 93 hw->bpw = xfer->bits_per_word;
94 hw->tx_buf = (u8 *)xfer->tx_buf;
95 hw->rx_buf = (u8 *)xfer->rx_buf;
130 96
131out_xfr: 97 /* Initiate transfer */
132 msg->status = status; 98 data = hw->tx_buf ? *hw->tx_buf++ : 0;
133 spi_finalize_current_message(master); 99 writel(data | SYNCIO_FRMLEN(hw->bpw) | SYNCIO_TXFRMEN, hw->syncio);
134 100
135 return 0; 101 return 1;
136} 102}
137 103
138static irqreturn_t spi_clps711x_isr(int irq, void *dev_id) 104static irqreturn_t spi_clps711x_isr(int irq, void *dev_id)
139{ 105{
140 struct spi_clps711x_data *hw = (struct spi_clps711x_data *)dev_id; 106 struct spi_master *master = dev_id;
141 u32 data; 107 struct spi_clps711x_data *hw = spi_master_get_devdata(master);
108 u8 data;
142 109
143 /* Handle RX */ 110 /* Handle RX */
144 data = clps_readb(SYNCIO); 111 data = readb(hw->syncio);
145 if (hw->rx_buf) 112 if (hw->rx_buf)
146 hw->rx_buf[hw->count] = (u8)data; 113 *hw->rx_buf++ = data;
147
148 hw->count++;
149 114
150 /* Handle TX */ 115 /* Handle TX */
151 if (hw->count < hw->len) { 116 if (--hw->len > 0) {
152 data = hw->tx_buf ? hw->tx_buf[hw->count] : 0; 117 data = hw->tx_buf ? *hw->tx_buf++ : 0;
153 clps_writel(data | SYNCIO_FRMLEN(8) | SYNCIO_TXFRMEN, SYNCIO); 118 writel(data | SYNCIO_FRMLEN(hw->bpw) | SYNCIO_TXFRMEN,
119 hw->syncio);
154 } else 120 } else
155 complete(&hw->done); 121 spi_finalize_current_transfer(master);
156 122
157 return IRQ_HANDLED; 123 return IRQ_HANDLED;
158} 124}
159 125
160static int spi_clps711x_probe(struct platform_device *pdev) 126static int spi_clps711x_probe(struct platform_device *pdev)
161{ 127{
162 int i, ret;
163 struct spi_master *master;
164 struct spi_clps711x_data *hw; 128 struct spi_clps711x_data *hw;
165 struct spi_clps711x_pdata *pdata = dev_get_platdata(&pdev->dev); 129 struct spi_clps711x_pdata *pdata = dev_get_platdata(&pdev->dev);
130 struct spi_master *master;
131 struct resource *res;
132 int i, irq, ret;
166 133
167 if (!pdata) { 134 if (!pdata) {
168 dev_err(&pdev->dev, "No platform data supplied\n"); 135 dev_err(&pdev->dev, "No platform data supplied\n");
@@ -174,33 +141,37 @@ static int spi_clps711x_probe(struct platform_device *pdev)
174 return -EINVAL; 141 return -EINVAL;
175 } 142 }
176 143
177 master = spi_alloc_master(&pdev->dev, 144 irq = platform_get_irq(pdev, 0);
178 sizeof(struct spi_clps711x_data) + 145 if (irq < 0)
179 sizeof(int) * pdata->num_chipselect); 146 return irq;
180 if (!master) { 147
181 dev_err(&pdev->dev, "SPI allocating memory error\n"); 148 master = spi_alloc_master(&pdev->dev, sizeof(*hw));
149 if (!master)
182 return -ENOMEM; 150 return -ENOMEM;
151
152 master->cs_gpios = devm_kzalloc(&pdev->dev, sizeof(int) *
153 pdata->num_chipselect, GFP_KERNEL);
154 if (!master->cs_gpios) {
155 ret = -ENOMEM;
156 goto err_out;
183 } 157 }
184 158
185 master->bus_num = pdev->id; 159 master->bus_num = pdev->id;
186 master->mode_bits = SPI_CPHA | SPI_CS_HIGH; 160 master->mode_bits = SPI_CPHA | SPI_CS_HIGH;
187 master->bits_per_word_mask = SPI_BPW_MASK(8); 161 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 8);
188 master->num_chipselect = pdata->num_chipselect; 162 master->num_chipselect = pdata->num_chipselect;
189 master->setup = spi_clps711x_setup; 163 master->setup = spi_clps711x_setup;
190 master->transfer_one_message = spi_clps711x_transfer_one_message; 164 master->prepare_message = spi_clps711x_prepare_message;
165 master->transfer_one = spi_clps711x_transfer_one;
191 166
192 hw = spi_master_get_devdata(master); 167 hw = spi_master_get_devdata(master);
193 168
194 for (i = 0; i < master->num_chipselect; i++) { 169 for (i = 0; i < master->num_chipselect; i++) {
195 hw->chipselect[i] = pdata->chipselect[i]; 170 master->cs_gpios[i] = pdata->chipselect[i];
196 if (!gpio_is_valid(hw->chipselect[i])) { 171 ret = devm_gpio_request(&pdev->dev, master->cs_gpios[i],
197 dev_err(&pdev->dev, "Invalid CS GPIO %i\n", i); 172 DRIVER_NAME);
198 ret = -EINVAL; 173 if (ret) {
199 goto err_out;
200 }
201 if (devm_gpio_request(&pdev->dev, hw->chipselect[i], NULL)) {
202 dev_err(&pdev->dev, "Can't get CS GPIO %i\n", i); 174 dev_err(&pdev->dev, "Can't get CS GPIO %i\n", i);
203 ret = -EINVAL;
204 goto err_out; 175 goto err_out;
205 } 176 }
206 } 177 }
@@ -211,29 +182,45 @@ static int spi_clps711x_probe(struct platform_device *pdev)
211 ret = PTR_ERR(hw->spi_clk); 182 ret = PTR_ERR(hw->spi_clk);
212 goto err_out; 183 goto err_out;
213 } 184 }
214 hw->max_speed_hz = clk_get_rate(hw->spi_clk); 185 master->max_speed_hz = clk_get_rate(hw->spi_clk);
215 186
216 init_completion(&hw->done);
217 platform_set_drvdata(pdev, master); 187 platform_set_drvdata(pdev, master);
218 188
189 hw->syscon = syscon_regmap_lookup_by_pdevname("syscon.3");
190 if (IS_ERR(hw->syscon)) {
191 ret = PTR_ERR(hw->syscon);
192 goto err_out;
193 }
194
195 hw->syscon1 = syscon_regmap_lookup_by_pdevname("syscon.1");
196 if (IS_ERR(hw->syscon1)) {
197 ret = PTR_ERR(hw->syscon1);
198 goto err_out;
199 }
200
201 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
202 hw->syncio = devm_ioremap_resource(&pdev->dev, res);
203 if (IS_ERR(hw->syncio)) {
204 ret = PTR_ERR(hw->syncio);
205 goto err_out;
206 }
207
219 /* Disable extended mode due hardware problems */ 208 /* Disable extended mode due hardware problems */
220 clps_writew(clps_readw(SYSCON3) & ~SYSCON3_ADCCON, SYSCON3); 209 regmap_update_bits(hw->syscon, SYSCON_OFFSET, SYSCON3_ADCCON, 0);
221 210
222 /* Clear possible pending interrupt */ 211 /* Clear possible pending interrupt */
223 clps_readl(SYNCIO); 212 readl(hw->syncio);
224 213
225 ret = devm_request_irq(&pdev->dev, IRQ_SSEOTI, spi_clps711x_isr, 0, 214 ret = devm_request_irq(&pdev->dev, irq, spi_clps711x_isr, 0,
226 dev_name(&pdev->dev), hw); 215 dev_name(&pdev->dev), master);
227 if (ret) { 216 if (ret)
228 dev_err(&pdev->dev, "Can't request IRQ\n");
229 goto err_out; 217 goto err_out;
230 }
231 218
232 ret = devm_spi_register_master(&pdev->dev, master); 219 ret = devm_spi_register_master(&pdev->dev, master);
233 if (!ret) { 220 if (!ret) {
234 dev_info(&pdev->dev, 221 dev_info(&pdev->dev,
235 "SPI bus driver initialized. Master clock %u Hz\n", 222 "SPI bus driver initialized. Master clock %u Hz\n",
236 hw->max_speed_hz); 223 master->max_speed_hz);
237 return 0; 224 return 0;
238 } 225 }
239 226
diff --git a/drivers/spi/spi-coldfire-qspi.c b/drivers/spi/spi-coldfire-qspi.c
index 28ae470397a9..e2fa628e55e7 100644
--- a/drivers/spi/spi-coldfire-qspi.c
+++ b/drivers/spi/spi-coldfire-qspi.c
@@ -77,8 +77,6 @@ struct mcfqspi {
77 struct mcfqspi_cs_control *cs_control; 77 struct mcfqspi_cs_control *cs_control;
78 78
79 wait_queue_head_t waitq; 79 wait_queue_head_t waitq;
80
81 struct device *dev;
82}; 80};
83 81
84static void mcfqspi_wr_qmr(struct mcfqspi *mcfqspi, u16 val) 82static void mcfqspi_wr_qmr(struct mcfqspi *mcfqspi, u16 val)
@@ -135,13 +133,13 @@ static void mcfqspi_cs_deselect(struct mcfqspi *mcfqspi, u8 chip_select,
135 133
136static int mcfqspi_cs_setup(struct mcfqspi *mcfqspi) 134static int mcfqspi_cs_setup(struct mcfqspi *mcfqspi)
137{ 135{
138 return (mcfqspi->cs_control && mcfqspi->cs_control->setup) ? 136 return (mcfqspi->cs_control->setup) ?
139 mcfqspi->cs_control->setup(mcfqspi->cs_control) : 0; 137 mcfqspi->cs_control->setup(mcfqspi->cs_control) : 0;
140} 138}
141 139
142static void mcfqspi_cs_teardown(struct mcfqspi *mcfqspi) 140static void mcfqspi_cs_teardown(struct mcfqspi *mcfqspi)
143{ 141{
144 if (mcfqspi->cs_control && mcfqspi->cs_control->teardown) 142 if (mcfqspi->cs_control->teardown)
145 mcfqspi->cs_control->teardown(mcfqspi->cs_control); 143 mcfqspi->cs_control->teardown(mcfqspi->cs_control);
146} 144}
147 145
@@ -300,68 +298,45 @@ static void mcfqspi_transfer_msg16(struct mcfqspi *mcfqspi, unsigned count,
300 } 298 }
301} 299}
302 300
303static int mcfqspi_transfer_one_message(struct spi_master *master, 301static void mcfqspi_set_cs(struct spi_device *spi, bool enable)
304 struct spi_message *msg)
305{ 302{
306 struct mcfqspi *mcfqspi = spi_master_get_devdata(master); 303 struct mcfqspi *mcfqspi = spi_master_get_devdata(spi->master);
307 struct spi_device *spi = msg->spi; 304 bool cs_high = spi->mode & SPI_CS_HIGH;
308 struct spi_transfer *t;
309 int status = 0;
310
311 list_for_each_entry(t, &msg->transfers, transfer_list) {
312 bool cs_high = spi->mode & SPI_CS_HIGH;
313 u16 qmr = MCFQSPI_QMR_MSTR;
314
315 qmr |= t->bits_per_word << 10;
316 if (spi->mode & SPI_CPHA)
317 qmr |= MCFQSPI_QMR_CPHA;
318 if (spi->mode & SPI_CPOL)
319 qmr |= MCFQSPI_QMR_CPOL;
320 if (t->speed_hz)
321 qmr |= mcfqspi_qmr_baud(t->speed_hz);
322 else
323 qmr |= mcfqspi_qmr_baud(spi->max_speed_hz);
324 mcfqspi_wr_qmr(mcfqspi, qmr);
325 305
306 if (enable)
326 mcfqspi_cs_select(mcfqspi, spi->chip_select, cs_high); 307 mcfqspi_cs_select(mcfqspi, spi->chip_select, cs_high);
308 else
309 mcfqspi_cs_deselect(mcfqspi, spi->chip_select, cs_high);
310}
327 311
328 mcfqspi_wr_qir(mcfqspi, MCFQSPI_QIR_SPIFE); 312static int mcfqspi_transfer_one(struct spi_master *master,
329 if (t->bits_per_word == 8) 313 struct spi_device *spi,
330 mcfqspi_transfer_msg8(mcfqspi, t->len, t->tx_buf, 314 struct spi_transfer *t)
331 t->rx_buf); 315{
332 else 316 struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
333 mcfqspi_transfer_msg16(mcfqspi, t->len / 2, t->tx_buf, 317 u16 qmr = MCFQSPI_QMR_MSTR;
334 t->rx_buf); 318
335 mcfqspi_wr_qir(mcfqspi, 0); 319 qmr |= t->bits_per_word << 10;
336 320 if (spi->mode & SPI_CPHA)
337 if (t->delay_usecs) 321 qmr |= MCFQSPI_QMR_CPHA;
338 udelay(t->delay_usecs); 322 if (spi->mode & SPI_CPOL)
339 if (t->cs_change) { 323 qmr |= MCFQSPI_QMR_CPOL;
340 if (!list_is_last(&t->transfer_list, &msg->transfers)) 324 qmr |= mcfqspi_qmr_baud(t->speed_hz);
341 mcfqspi_cs_deselect(mcfqspi, spi->chip_select, 325 mcfqspi_wr_qmr(mcfqspi, qmr);
342 cs_high); 326
343 } else { 327 mcfqspi_wr_qir(mcfqspi, MCFQSPI_QIR_SPIFE);
344 if (list_is_last(&t->transfer_list, &msg->transfers)) 328 if (t->bits_per_word == 8)
345 mcfqspi_cs_deselect(mcfqspi, spi->chip_select, 329 mcfqspi_transfer_msg8(mcfqspi, t->len, t->tx_buf, t->rx_buf);
346 cs_high); 330 else
347 } 331 mcfqspi_transfer_msg16(mcfqspi, t->len / 2, t->tx_buf,
348 msg->actual_length += t->len; 332 t->rx_buf);
349 } 333 mcfqspi_wr_qir(mcfqspi, 0);
350 msg->status = status;
351 spi_finalize_current_message(master);
352
353 return status;
354 334
335 return 0;
355} 336}
356 337
357static int mcfqspi_setup(struct spi_device *spi) 338static int mcfqspi_setup(struct spi_device *spi)
358{ 339{
359 if (spi->chip_select >= spi->master->num_chipselect) {
360 dev_dbg(&spi->dev, "%d chip select is out of range\n",
361 spi->chip_select);
362 return -EINVAL;
363 }
364
365 mcfqspi_cs_deselect(spi_master_get_devdata(spi->master), 340 mcfqspi_cs_deselect(spi_master_get_devdata(spi->master),
366 spi->chip_select, spi->mode & SPI_CS_HIGH); 341 spi->chip_select, spi->mode & SPI_CS_HIGH);
367 342
@@ -388,6 +363,11 @@ static int mcfqspi_probe(struct platform_device *pdev)
388 return -ENOENT; 363 return -ENOENT;
389 } 364 }
390 365
366 if (!pdata->cs_control) {
367 dev_dbg(&pdev->dev, "pdata->cs_control is NULL\n");
368 return -EINVAL;
369 }
370
391 master = spi_alloc_master(&pdev->dev, sizeof(*mcfqspi)); 371 master = spi_alloc_master(&pdev->dev, sizeof(*mcfqspi));
392 if (master == NULL) { 372 if (master == NULL) {
393 dev_dbg(&pdev->dev, "spi_alloc_master failed\n"); 373 dev_dbg(&pdev->dev, "spi_alloc_master failed\n");
@@ -436,12 +416,12 @@ static int mcfqspi_probe(struct platform_device *pdev)
436 } 416 }
437 417
438 init_waitqueue_head(&mcfqspi->waitq); 418 init_waitqueue_head(&mcfqspi->waitq);
439 mcfqspi->dev = &pdev->dev;
440 419
441 master->mode_bits = SPI_CS_HIGH | SPI_CPOL | SPI_CPHA; 420 master->mode_bits = SPI_CS_HIGH | SPI_CPOL | SPI_CPHA;
442 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16); 421 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16);
443 master->setup = mcfqspi_setup; 422 master->setup = mcfqspi_setup;
444 master->transfer_one_message = mcfqspi_transfer_one_message; 423 master->set_cs = mcfqspi_set_cs;
424 master->transfer_one = mcfqspi_transfer_one;
445 master->auto_runtime_pm = true; 425 master->auto_runtime_pm = true;
446 426
447 platform_set_drvdata(pdev, master); 427 platform_set_drvdata(pdev, master);
@@ -451,7 +431,7 @@ static int mcfqspi_probe(struct platform_device *pdev)
451 dev_dbg(&pdev->dev, "spi_register_master failed\n"); 431 dev_dbg(&pdev->dev, "spi_register_master failed\n");
452 goto fail2; 432 goto fail2;
453 } 433 }
454 pm_runtime_enable(mcfqspi->dev); 434 pm_runtime_enable(&pdev->dev);
455 435
456 dev_info(&pdev->dev, "Coldfire QSPI bus driver\n"); 436 dev_info(&pdev->dev, "Coldfire QSPI bus driver\n");
457 437
@@ -473,9 +453,8 @@ static int mcfqspi_remove(struct platform_device *pdev)
473{ 453{
474 struct spi_master *master = platform_get_drvdata(pdev); 454 struct spi_master *master = platform_get_drvdata(pdev);
475 struct mcfqspi *mcfqspi = spi_master_get_devdata(master); 455 struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
476 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
477 456
478 pm_runtime_disable(mcfqspi->dev); 457 pm_runtime_disable(&pdev->dev);
479 /* disable the hardware (set the baud rate to 0) */ 458 /* disable the hardware (set the baud rate to 0) */
480 mcfqspi_wr_qmr(mcfqspi, MCFQSPI_QMR_MSTR); 459 mcfqspi_wr_qmr(mcfqspi, MCFQSPI_QMR_MSTR);
481 460
@@ -490,8 +469,11 @@ static int mcfqspi_suspend(struct device *dev)
490{ 469{
491 struct spi_master *master = dev_get_drvdata(dev); 470 struct spi_master *master = dev_get_drvdata(dev);
492 struct mcfqspi *mcfqspi = spi_master_get_devdata(master); 471 struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
472 int ret;
493 473
494 spi_master_suspend(master); 474 ret = spi_master_suspend(master);
475 if (ret)
476 return ret;
495 477
496 clk_disable(mcfqspi->clk); 478 clk_disable(mcfqspi->clk);
497 479
@@ -503,11 +485,9 @@ static int mcfqspi_resume(struct device *dev)
503 struct spi_master *master = dev_get_drvdata(dev); 485 struct spi_master *master = dev_get_drvdata(dev);
504 struct mcfqspi *mcfqspi = spi_master_get_devdata(master); 486 struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
505 487
506 spi_master_resume(master);
507
508 clk_enable(mcfqspi->clk); 488 clk_enable(mcfqspi->clk);
509 489
510 return 0; 490 return spi_master_resume(master);
511} 491}
512#endif 492#endif
513 493
diff --git a/drivers/spi/spi-davinci.c b/drivers/spi/spi-davinci.c
index 5e7389faa2a0..50f750989258 100644
--- a/drivers/spi/spi-davinci.c
+++ b/drivers/spi/spi-davinci.c
@@ -802,8 +802,7 @@ static int spi_davinci_get_pdata(struct platform_device *pdev,
802 pdata = &dspi->pdata; 802 pdata = &dspi->pdata;
803 803
804 pdata->version = SPI_VERSION_1; 804 pdata->version = SPI_VERSION_1;
805 match = of_match_device(of_match_ptr(davinci_spi_of_match), 805 match = of_match_device(davinci_spi_of_match, &pdev->dev);
806 &pdev->dev);
807 if (!match) 806 if (!match)
808 return -ENODEV; 807 return -ENODEV;
809 808
@@ -824,7 +823,6 @@ static int spi_davinci_get_pdata(struct platform_device *pdev,
824 return 0; 823 return 0;
825} 824}
826#else 825#else
827#define davinci_spi_of_match NULL
828static struct davinci_spi_platform_data 826static struct davinci_spi_platform_data
829 *spi_davinci_get_pdata(struct platform_device *pdev, 827 *spi_davinci_get_pdata(struct platform_device *pdev,
830 struct davinci_spi *dspi) 828 struct davinci_spi *dspi)
@@ -864,10 +862,6 @@ static int davinci_spi_probe(struct platform_device *pdev)
864 platform_set_drvdata(pdev, master); 862 platform_set_drvdata(pdev, master);
865 863
866 dspi = spi_master_get_devdata(master); 864 dspi = spi_master_get_devdata(master);
867 if (dspi == NULL) {
868 ret = -ENOENT;
869 goto free_master;
870 }
871 865
872 if (dev_get_platdata(&pdev->dev)) { 866 if (dev_get_platdata(&pdev->dev)) {
873 pdata = dev_get_platdata(&pdev->dev); 867 pdata = dev_get_platdata(&pdev->dev);
@@ -908,10 +902,6 @@ static int davinci_spi_probe(struct platform_device *pdev)
908 goto free_master; 902 goto free_master;
909 903
910 dspi->bitbang.master = master; 904 dspi->bitbang.master = master;
911 if (dspi->bitbang.master == NULL) {
912 ret = -ENODEV;
913 goto free_master;
914 }
915 905
916 dspi->clk = devm_clk_get(&pdev->dev, NULL); 906 dspi->clk = devm_clk_get(&pdev->dev, NULL);
917 if (IS_ERR(dspi->clk)) { 907 if (IS_ERR(dspi->clk)) {
@@ -1040,7 +1030,7 @@ static struct platform_driver davinci_spi_driver = {
1040 .driver = { 1030 .driver = {
1041 .name = "spi_davinci", 1031 .name = "spi_davinci",
1042 .owner = THIS_MODULE, 1032 .owner = THIS_MODULE,
1043 .of_match_table = davinci_spi_of_match, 1033 .of_match_table = of_match_ptr(davinci_spi_of_match),
1044 }, 1034 },
1045 .probe = davinci_spi_probe, 1035 .probe = davinci_spi_probe,
1046 .remove = davinci_spi_remove, 1036 .remove = davinci_spi_remove,
diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c
index 9af56cdf1540..1492f5ee9aaa 100644
--- a/drivers/spi/spi-dw-mmio.c
+++ b/drivers/spi/spi-dw-mmio.c
@@ -66,7 +66,7 @@ static int dw_spi_mmio_probe(struct platform_device *pdev)
66 if (ret) 66 if (ret)
67 return ret; 67 return ret;
68 68
69 dws->bus_num = 0; 69 dws->bus_num = pdev->id;
70 dws->num_cs = 4; 70 dws->num_cs = 4;
71 dws->max_freq = clk_get_rate(dwsmmio->clk); 71 dws->max_freq = clk_get_rate(dwsmmio->clk);
72 72
diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c
index bf98d63d92b3..712ac5629cd4 100644
--- a/drivers/spi/spi-dw.c
+++ b/drivers/spi/spi-dw.c
@@ -276,8 +276,7 @@ static void giveback(struct dw_spi *dws)
276 queue_work(dws->workqueue, &dws->pump_messages); 276 queue_work(dws->workqueue, &dws->pump_messages);
277 spin_unlock_irqrestore(&dws->lock, flags); 277 spin_unlock_irqrestore(&dws->lock, flags);
278 278
279 last_transfer = list_entry(msg->transfers.prev, 279 last_transfer = list_last_entry(&msg->transfers, struct spi_transfer,
280 struct spi_transfer,
281 transfer_list); 280 transfer_list);
282 281
283 if (!last_transfer->cs_change && dws->cs_control) 282 if (!last_transfer->cs_change && dws->cs_control)
@@ -439,12 +438,6 @@ static void pump_transfers(unsigned long data)
439 438
440 if (transfer->speed_hz != speed) { 439 if (transfer->speed_hz != speed) {
441 speed = transfer->speed_hz; 440 speed = transfer->speed_hz;
442 if (speed > dws->max_freq) {
443 printk(KERN_ERR "MRST SPI0: unsupported"
444 "freq: %dHz\n", speed);
445 message->status = -EIO;
446 goto early_exit;
447 }
448 441
449 /* clk_div doesn't support odd number */ 442 /* clk_div doesn't support odd number */
450 clk_div = dws->max_freq / speed; 443 clk_div = dws->max_freq / speed;
@@ -671,12 +664,6 @@ static int dw_spi_setup(struct spi_device *spi)
671 return 0; 664 return 0;
672} 665}
673 666
674static void dw_spi_cleanup(struct spi_device *spi)
675{
676 struct chip_data *chip = spi_get_ctldata(spi);
677 kfree(chip);
678}
679
680static int init_queue(struct dw_spi *dws) 667static int init_queue(struct dw_spi *dws)
681{ 668{
682 INIT_LIST_HEAD(&dws->queue); 669 INIT_LIST_HEAD(&dws->queue);
@@ -806,9 +793,9 @@ int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
806 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16); 793 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
807 master->bus_num = dws->bus_num; 794 master->bus_num = dws->bus_num;
808 master->num_chipselect = dws->num_cs; 795 master->num_chipselect = dws->num_cs;
809 master->cleanup = dw_spi_cleanup;
810 master->setup = dw_spi_setup; 796 master->setup = dw_spi_setup;
811 master->transfer = dw_spi_transfer; 797 master->transfer = dw_spi_transfer;
798 master->max_speed_hz = dws->max_freq;
812 799
813 /* Basic HW init */ 800 /* Basic HW init */
814 spi_hw_init(dws); 801 spi_hw_init(dws);
diff --git a/drivers/spi/spi-efm32.c b/drivers/spi/spi-efm32.c
index d4d3cc534792..be44a3eeb5e8 100644
--- a/drivers/spi/spi-efm32.c
+++ b/drivers/spi/spi-efm32.c
@@ -198,7 +198,7 @@ static int efm32_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
198 198
199 efm32_spi_filltx(ddata); 199 efm32_spi_filltx(ddata);
200 200
201 init_completion(&ddata->done); 201 reinit_completion(&ddata->done);
202 202
203 efm32_spi_write32(ddata, REG_IF_TXBL | REG_IF_RXDATAV, REG_IEN); 203 efm32_spi_write32(ddata, REG_IF_TXBL | REG_IF_RXDATAV, REG_IEN);
204 204
@@ -287,17 +287,17 @@ static u32 efm32_spi_get_configured_location(struct efm32_spi_ddata *ddata)
287 return (reg & REG_ROUTE_LOCATION__MASK) >> __ffs(REG_ROUTE_LOCATION__MASK); 287 return (reg & REG_ROUTE_LOCATION__MASK) >> __ffs(REG_ROUTE_LOCATION__MASK);
288} 288}
289 289
290static int efm32_spi_probe_dt(struct platform_device *pdev, 290static void efm32_spi_probe_dt(struct platform_device *pdev,
291 struct spi_master *master, struct efm32_spi_ddata *ddata) 291 struct spi_master *master, struct efm32_spi_ddata *ddata)
292{ 292{
293 struct device_node *np = pdev->dev.of_node; 293 struct device_node *np = pdev->dev.of_node;
294 u32 location; 294 u32 location;
295 int ret; 295 int ret;
296 296
297 if (!np) 297 ret = of_property_read_u32(np, "efm32,location", &location);
298 return 1; 298 if (ret)
299 299 /* fall back to old and (wrongly) generic property "location" */
300 ret = of_property_read_u32(np, "location", &location); 300 ret = of_property_read_u32(np, "location", &location);
301 if (!ret) { 301 if (!ret) {
302 dev_dbg(&pdev->dev, "using location %u\n", location); 302 dev_dbg(&pdev->dev, "using location %u\n", location);
303 } else { 303 } else {
@@ -308,11 +308,6 @@ static int efm32_spi_probe_dt(struct platform_device *pdev,
308 } 308 }
309 309
310 ddata->pdata.location = location; 310 ddata->pdata.location = location;
311
312 /* spi core takes care about the bus number using an alias */
313 master->bus_num = -1;
314
315 return 0;
316} 311}
317 312
318static int efm32_spi_probe(struct platform_device *pdev) 313static int efm32_spi_probe(struct platform_device *pdev)
@@ -322,9 +317,14 @@ static int efm32_spi_probe(struct platform_device *pdev)
322 int ret; 317 int ret;
323 struct spi_master *master; 318 struct spi_master *master;
324 struct device_node *np = pdev->dev.of_node; 319 struct device_node *np = pdev->dev.of_node;
325 unsigned int num_cs, i; 320 int num_cs, i;
321
322 if (!np)
323 return -EINVAL;
326 324
327 num_cs = of_gpio_named_count(np, "cs-gpios"); 325 num_cs = of_gpio_named_count(np, "cs-gpios");
326 if (num_cs < 0)
327 return num_cs;
328 328
329 master = spi_alloc_master(&pdev->dev, 329 master = spi_alloc_master(&pdev->dev,
330 sizeof(*ddata) + num_cs * sizeof(unsigned)); 330 sizeof(*ddata) + num_cs * sizeof(unsigned));
@@ -349,6 +349,7 @@ static int efm32_spi_probe(struct platform_device *pdev)
349 ddata->bitbang.txrx_bufs = efm32_spi_txrx_bufs; 349 ddata->bitbang.txrx_bufs = efm32_spi_txrx_bufs;
350 350
351 spin_lock_init(&ddata->lock); 351 spin_lock_init(&ddata->lock);
352 init_completion(&ddata->done);
352 353
353 ddata->clk = devm_clk_get(&pdev->dev, NULL); 354 ddata->clk = devm_clk_get(&pdev->dev, NULL);
354 if (IS_ERR(ddata->clk)) { 355 if (IS_ERR(ddata->clk)) {
@@ -415,23 +416,7 @@ static int efm32_spi_probe(struct platform_device *pdev)
415 goto err; 416 goto err;
416 } 417 }
417 418
418 ret = efm32_spi_probe_dt(pdev, master, ddata); 419 efm32_spi_probe_dt(pdev, master, ddata);
419 if (ret > 0) {
420 /* not created by device tree */
421 const struct efm32_spi_pdata *pdata =
422 dev_get_platdata(&pdev->dev);
423
424 if (pdata)
425 ddata->pdata = *pdata;
426 else
427 ddata->pdata.location =
428 efm32_spi_get_configured_location(ddata);
429
430 master->bus_num = pdev->id;
431
432 } else if (ret < 0) {
433 goto err_disable_clk;
434 }
435 420
436 efm32_spi_write32(ddata, 0, REG_IEN); 421 efm32_spi_write32(ddata, 0, REG_IEN);
437 efm32_spi_write32(ddata, REG_ROUTE_TXPEN | REG_ROUTE_RXPEN | 422 efm32_spi_write32(ddata, REG_ROUTE_TXPEN | REG_ROUTE_RXPEN |
@@ -487,6 +472,9 @@ static int efm32_spi_remove(struct platform_device *pdev)
487 472
488static const struct of_device_id efm32_spi_dt_ids[] = { 473static const struct of_device_id efm32_spi_dt_ids[] = {
489 { 474 {
475 .compatible = "energymicro,efm32-spi",
476 }, {
477 /* doesn't follow the "vendor,device" scheme, don't use */
490 .compatible = "efm32,spi", 478 .compatible = "efm32,spi",
491 }, { 479 }, {
492 /* sentinel */ 480 /* sentinel */
diff --git a/drivers/spi/spi-ep93xx.c b/drivers/spi/spi-ep93xx.c
index 1bfaed6e4073..2f675d32df0e 100644
--- a/drivers/spi/spi-ep93xx.c
+++ b/drivers/spi/spi-ep93xx.c
@@ -73,8 +73,6 @@
73 * @clk: clock for the controller 73 * @clk: clock for the controller
74 * @regs_base: pointer to ioremap()'d registers 74 * @regs_base: pointer to ioremap()'d registers
75 * @sspdr_phys: physical address of the SSPDR register 75 * @sspdr_phys: physical address of the SSPDR register
76 * @min_rate: minimum clock rate (in Hz) supported by the controller
77 * @max_rate: maximum clock rate (in Hz) supported by the controller
78 * @wait: wait here until given transfer is completed 76 * @wait: wait here until given transfer is completed
79 * @current_msg: message that is currently processed (or %NULL if none) 77 * @current_msg: message that is currently processed (or %NULL if none)
80 * @tx: current byte in transfer to transmit 78 * @tx: current byte in transfer to transmit
@@ -95,8 +93,6 @@ struct ep93xx_spi {
95 struct clk *clk; 93 struct clk *clk;
96 void __iomem *regs_base; 94 void __iomem *regs_base;
97 unsigned long sspdr_phys; 95 unsigned long sspdr_phys;
98 unsigned long min_rate;
99 unsigned long max_rate;
100 struct completion wait; 96 struct completion wait;
101 struct spi_message *current_msg; 97 struct spi_message *current_msg;
102 size_t tx; 98 size_t tx;
@@ -199,9 +195,9 @@ static void ep93xx_spi_disable_interrupts(const struct ep93xx_spi *espi)
199 * @div_scr: pointer to return the scr divider 195 * @div_scr: pointer to return the scr divider
200 */ 196 */
201static int ep93xx_spi_calc_divisors(const struct ep93xx_spi *espi, 197static int ep93xx_spi_calc_divisors(const struct ep93xx_spi *espi,
202 unsigned long rate, 198 u32 rate, u8 *div_cpsr, u8 *div_scr)
203 u8 *div_cpsr, u8 *div_scr)
204{ 199{
200 struct spi_master *master = platform_get_drvdata(espi->pdev);
205 unsigned long spi_clk_rate = clk_get_rate(espi->clk); 201 unsigned long spi_clk_rate = clk_get_rate(espi->clk);
206 int cpsr, scr; 202 int cpsr, scr;
207 203
@@ -210,7 +206,7 @@ static int ep93xx_spi_calc_divisors(const struct ep93xx_spi *espi,
210 * controller. Note that minimum value is already checked in 206 * controller. Note that minimum value is already checked in
211 * ep93xx_spi_transfer_one_message(). 207 * ep93xx_spi_transfer_one_message().
212 */ 208 */
213 rate = clamp(rate, espi->min_rate, espi->max_rate); 209 rate = clamp(rate, master->min_speed_hz, master->max_speed_hz);
214 210
215 /* 211 /*
216 * Calculate divisors so that we can get speed according the 212 * Calculate divisors so that we can get speed according the
@@ -735,13 +731,6 @@ static int ep93xx_spi_transfer_one_message(struct spi_master *master,
735 struct spi_message *msg) 731 struct spi_message *msg)
736{ 732{
737 struct ep93xx_spi *espi = spi_master_get_devdata(master); 733 struct ep93xx_spi *espi = spi_master_get_devdata(master);
738 struct spi_transfer *t;
739
740 /* first validate each transfer */
741 list_for_each_entry(t, &msg->transfers, transfer_list) {
742 if (t->speed_hz < espi->min_rate)
743 return -EINVAL;
744 }
745 734
746 msg->state = NULL; 735 msg->state = NULL;
747 msg->status = 0; 736 msg->status = 0;
@@ -917,8 +906,8 @@ static int ep93xx_spi_probe(struct platform_device *pdev)
917 * Calculate maximum and minimum supported clock rates 906 * Calculate maximum and minimum supported clock rates
918 * for the controller. 907 * for the controller.
919 */ 908 */
920 espi->max_rate = clk_get_rate(espi->clk) / 2; 909 master->max_speed_hz = clk_get_rate(espi->clk) / 2;
921 espi->min_rate = clk_get_rate(espi->clk) / (254 * 256); 910 master->min_speed_hz = clk_get_rate(espi->clk) / (254 * 256);
922 espi->pdev = pdev; 911 espi->pdev = pdev;
923 912
924 espi->sspdr_phys = res->start + SSPDR; 913 espi->sspdr_phys = res->start + SSPDR;
diff --git a/drivers/spi/spi-falcon.c b/drivers/spi/spi-falcon.c
index dd5bd468e962..09965f069a1c 100644
--- a/drivers/spi/spi-falcon.c
+++ b/drivers/spi/spi-falcon.c
@@ -312,9 +312,6 @@ static int falcon_sflash_setup(struct spi_device *spi)
312 unsigned int i; 312 unsigned int i;
313 unsigned long flags; 313 unsigned long flags;
314 314
315 if (spi->chip_select > 0)
316 return -ENODEV;
317
318 spin_lock_irqsave(&ebu_lock, flags); 315 spin_lock_irqsave(&ebu_lock, flags);
319 316
320 if (spi->max_speed_hz >= CLOCK_100M) { 317 if (spi->max_speed_hz >= CLOCK_100M) {
@@ -422,9 +419,7 @@ static int falcon_sflash_probe(struct platform_device *pdev)
422 priv->master = master; 419 priv->master = master;
423 420
424 master->mode_bits = SPI_MODE_3; 421 master->mode_bits = SPI_MODE_3;
425 master->num_chipselect = 1;
426 master->flags = SPI_MASTER_HALF_DUPLEX; 422 master->flags = SPI_MASTER_HALF_DUPLEX;
427 master->bus_num = -1;
428 master->setup = falcon_sflash_setup; 423 master->setup = falcon_sflash_setup;
429 master->prepare_transfer_hardware = falcon_sflash_prepare_xfer; 424 master->prepare_transfer_hardware = falcon_sflash_prepare_xfer;
430 master->transfer_one_message = falcon_sflash_xfer_one; 425 master->transfer_one_message = falcon_sflash_xfer_one;
diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c
index a25392065d9b..d565eeee3bd8 100644
--- a/drivers/spi/spi-fsl-dspi.c
+++ b/drivers/spi/spi-fsl-dspi.c
@@ -18,6 +18,7 @@
18#include <linux/interrupt.h> 18#include <linux/interrupt.h>
19#include <linux/errno.h> 19#include <linux/errno.h>
20#include <linux/platform_device.h> 20#include <linux/platform_device.h>
21#include <linux/regmap.h>
21#include <linux/sched.h> 22#include <linux/sched.h>
22#include <linux/delay.h> 23#include <linux/delay.h>
23#include <linux/io.h> 24#include <linux/io.h>
@@ -108,11 +109,11 @@ struct fsl_dspi {
108 struct spi_bitbang bitbang; 109 struct spi_bitbang bitbang;
109 struct platform_device *pdev; 110 struct platform_device *pdev;
110 111
111 void __iomem *base; 112 struct regmap *regmap;
112 int irq; 113 int irq;
113 struct clk *clk; 114 struct clk *clk;
114 115
115 struct spi_transfer *cur_transfer; 116 struct spi_transfer *cur_transfer;
116 struct chip_data *cur_chip; 117 struct chip_data *cur_chip;
117 size_t len; 118 size_t len;
118 void *tx; 119 void *tx;
@@ -123,24 +124,17 @@ struct fsl_dspi {
123 u8 cs; 124 u8 cs;
124 u16 void_write_data; 125 u16 void_write_data;
125 126
126 wait_queue_head_t waitq; 127 wait_queue_head_t waitq;
127 u32 waitflags; 128 u32 waitflags;
128}; 129};
129 130
130static inline int is_double_byte_mode(struct fsl_dspi *dspi) 131static inline int is_double_byte_mode(struct fsl_dspi *dspi)
131{ 132{
132 return ((readl(dspi->base + SPI_CTAR(dspi->cs)) & SPI_FRAME_BITS_MASK) 133 unsigned int val;
133 == SPI_FRAME_BITS(8)) ? 0 : 1;
134}
135 134
136static void set_bit_mode(struct fsl_dspi *dspi, unsigned char bits) 135 regmap_read(dspi->regmap, SPI_CTAR(dspi->cs), &val);
137{
138 u32 temp;
139 136
140 temp = readl(dspi->base + SPI_CTAR(dspi->cs)); 137 return ((val & SPI_FRAME_BITS_MASK) == SPI_FRAME_BITS(8)) ? 0 : 1;
141 temp &= ~SPI_FRAME_BITS_MASK;
142 temp |= SPI_FRAME_BITS(bits);
143 writel(temp, dspi->base + SPI_CTAR(dspi->cs));
144} 138}
145 139
146static void hz_to_spi_baud(char *pbr, char *br, int speed_hz, 140static void hz_to_spi_baud(char *pbr, char *br, int speed_hz,
@@ -188,7 +182,8 @@ static int dspi_transfer_write(struct fsl_dspi *dspi)
188 */ 182 */
189 if (tx_word && (dspi->len == 1)) { 183 if (tx_word && (dspi->len == 1)) {
190 dspi->dataflags |= TRAN_STATE_WORD_ODD_NUM; 184 dspi->dataflags |= TRAN_STATE_WORD_ODD_NUM;
191 set_bit_mode(dspi, 8); 185 regmap_update_bits(dspi->regmap, SPI_CTAR(dspi->cs),
186 SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(8));
192 tx_word = 0; 187 tx_word = 0;
193 } 188 }
194 189
@@ -238,7 +233,8 @@ static int dspi_transfer_write(struct fsl_dspi *dspi)
238 dspi_pushr |= SPI_PUSHR_CTCNT; /* clear counter */ 233 dspi_pushr |= SPI_PUSHR_CTCNT; /* clear counter */
239 } 234 }
240 235
241 writel(dspi_pushr, dspi->base + SPI_PUSHR); 236 regmap_write(dspi->regmap, SPI_PUSHR, dspi_pushr);
237
242 tx_count++; 238 tx_count++;
243 } 239 }
244 240
@@ -253,17 +249,23 @@ static int dspi_transfer_read(struct fsl_dspi *dspi)
253 while ((dspi->rx < dspi->rx_end) 249 while ((dspi->rx < dspi->rx_end)
254 && (rx_count < DSPI_FIFO_SIZE)) { 250 && (rx_count < DSPI_FIFO_SIZE)) {
255 if (rx_word) { 251 if (rx_word) {
252 unsigned int val;
253
256 if ((dspi->rx_end - dspi->rx) == 1) 254 if ((dspi->rx_end - dspi->rx) == 1)
257 break; 255 break;
258 256
259 d = SPI_POPR_RXDATA(readl(dspi->base + SPI_POPR)); 257 regmap_read(dspi->regmap, SPI_POPR, &val);
258 d = SPI_POPR_RXDATA(val);
260 259
261 if (!(dspi->dataflags & TRAN_STATE_RX_VOID)) 260 if (!(dspi->dataflags & TRAN_STATE_RX_VOID))
262 *(u16 *)dspi->rx = d; 261 *(u16 *)dspi->rx = d;
263 dspi->rx += 2; 262 dspi->rx += 2;
264 263
265 } else { 264 } else {
266 d = SPI_POPR_RXDATA(readl(dspi->base + SPI_POPR)); 265 unsigned int val;
266
267 regmap_read(dspi->regmap, SPI_POPR, &val);
268 d = SPI_POPR_RXDATA(val);
267 if (!(dspi->dataflags & TRAN_STATE_RX_VOID)) 269 if (!(dspi->dataflags & TRAN_STATE_RX_VOID))
268 *(u8 *)dspi->rx = d; 270 *(u8 *)dspi->rx = d;
269 dspi->rx++; 271 dspi->rx++;
@@ -295,13 +297,13 @@ static int dspi_txrx_transfer(struct spi_device *spi, struct spi_transfer *t)
295 if (!dspi->tx) 297 if (!dspi->tx)
296 dspi->dataflags |= TRAN_STATE_TX_VOID; 298 dspi->dataflags |= TRAN_STATE_TX_VOID;
297 299
298 writel(dspi->cur_chip->mcr_val, dspi->base + SPI_MCR); 300 regmap_write(dspi->regmap, SPI_MCR, dspi->cur_chip->mcr_val);
299 writel(dspi->cur_chip->ctar_val, dspi->base + SPI_CTAR(dspi->cs)); 301 regmap_write(dspi->regmap, SPI_CTAR(dspi->cs), dspi->cur_chip->ctar_val);
300 writel(SPI_RSER_EOQFE, dspi->base + SPI_RSER); 302 regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_EOQFE);
301 303
302 if (t->speed_hz) 304 if (t->speed_hz)
303 writel(dspi->cur_chip->ctar_val, 305 regmap_write(dspi->regmap, SPI_CTAR(dspi->cs),
304 dspi->base + SPI_CTAR(dspi->cs)); 306 dspi->cur_chip->ctar_val);
305 307
306 dspi_transfer_write(dspi); 308 dspi_transfer_write(dspi);
307 309
@@ -315,7 +317,9 @@ static int dspi_txrx_transfer(struct spi_device *spi, struct spi_transfer *t)
315static void dspi_chipselect(struct spi_device *spi, int value) 317static void dspi_chipselect(struct spi_device *spi, int value)
316{ 318{
317 struct fsl_dspi *dspi = spi_master_get_devdata(spi->master); 319 struct fsl_dspi *dspi = spi_master_get_devdata(spi->master);
318 u32 pushr = readl(dspi->base + SPI_PUSHR); 320 unsigned int pushr;
321
322 regmap_read(dspi->regmap, SPI_PUSHR, &pushr);
319 323
320 switch (value) { 324 switch (value) {
321 case BITBANG_CS_ACTIVE: 325 case BITBANG_CS_ACTIVE:
@@ -326,7 +330,7 @@ static void dspi_chipselect(struct spi_device *spi, int value)
326 break; 330 break;
327 } 331 }
328 332
329 writel(pushr, dspi->base + SPI_PUSHR); 333 regmap_write(dspi->regmap, SPI_PUSHR, pushr);
330} 334}
331 335
332static int dspi_setup_transfer(struct spi_device *spi, struct spi_transfer *t) 336static int dspi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
@@ -338,7 +342,8 @@ static int dspi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
338 /* Only alloc on first setup */ 342 /* Only alloc on first setup */
339 chip = spi_get_ctldata(spi); 343 chip = spi_get_ctldata(spi);
340 if (chip == NULL) { 344 if (chip == NULL) {
341 chip = kcalloc(1, sizeof(struct chip_data), GFP_KERNEL); 345 chip = devm_kzalloc(&spi->dev, sizeof(struct chip_data),
346 GFP_KERNEL);
342 if (!chip) 347 if (!chip)
343 return -ENOMEM; 348 return -ENOMEM;
344 } 349 }
@@ -349,7 +354,6 @@ static int dspi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
349 fmsz = spi->bits_per_word - 1; 354 fmsz = spi->bits_per_word - 1;
350 } else { 355 } else {
351 pr_err("Invalid wordsize\n"); 356 pr_err("Invalid wordsize\n");
352 kfree(chip);
353 return -ENODEV; 357 return -ENODEV;
354 } 358 }
355 359
@@ -382,13 +386,15 @@ static irqreturn_t dspi_interrupt(int irq, void *dev_id)
382{ 386{
383 struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id; 387 struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id;
384 388
385 writel(SPI_SR_EOQF, dspi->base + SPI_SR); 389 regmap_write(dspi->regmap, SPI_SR, SPI_SR_EOQF);
386 390
387 dspi_transfer_read(dspi); 391 dspi_transfer_read(dspi);
388 392
389 if (!dspi->len) { 393 if (!dspi->len) {
390 if (dspi->dataflags & TRAN_STATE_WORD_ODD_NUM) 394 if (dspi->dataflags & TRAN_STATE_WORD_ODD_NUM)
391 set_bit_mode(dspi, 16); 395 regmap_update_bits(dspi->regmap, SPI_CTAR(dspi->cs),
396 SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(16));
397
392 dspi->waitflags = 1; 398 dspi->waitflags = 1;
393 wake_up_interruptible(&dspi->waitq); 399 wake_up_interruptible(&dspi->waitq);
394 } else { 400 } else {
@@ -430,8 +436,13 @@ static int dspi_resume(struct device *dev)
430} 436}
431#endif /* CONFIG_PM_SLEEP */ 437#endif /* CONFIG_PM_SLEEP */
432 438
433static const struct dev_pm_ops dspi_pm = { 439static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume);
434 SET_SYSTEM_SLEEP_PM_OPS(dspi_suspend, dspi_resume) 440
441static struct regmap_config dspi_regmap_config = {
442 .reg_bits = 32,
443 .val_bits = 32,
444 .reg_stride = 4,
445 .max_register = 0x88,
435}; 446};
436 447
437static int dspi_probe(struct platform_device *pdev) 448static int dspi_probe(struct platform_device *pdev)
@@ -440,6 +451,7 @@ static int dspi_probe(struct platform_device *pdev)
440 struct spi_master *master; 451 struct spi_master *master;
441 struct fsl_dspi *dspi; 452 struct fsl_dspi *dspi;
442 struct resource *res; 453 struct resource *res;
454 void __iomem *base;
443 int ret = 0, cs_num, bus_num; 455 int ret = 0, cs_num, bus_num;
444 456
445 master = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi)); 457 master = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi));
@@ -474,12 +486,24 @@ static int dspi_probe(struct platform_device *pdev)
474 master->bus_num = bus_num; 486 master->bus_num = bus_num;
475 487
476 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 488 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
477 dspi->base = devm_ioremap_resource(&pdev->dev, res); 489 base = devm_ioremap_resource(&pdev->dev, res);
478 if (IS_ERR(dspi->base)) { 490 if (IS_ERR(base)) {
479 ret = PTR_ERR(dspi->base); 491 ret = PTR_ERR(base);
480 goto out_master_put; 492 goto out_master_put;
481 } 493 }
482 494
495 dspi_regmap_config.lock_arg = dspi;
496 dspi_regmap_config.val_format_endian =
497 of_property_read_bool(np, "big-endian")
498 ? REGMAP_ENDIAN_BIG : REGMAP_ENDIAN_DEFAULT;
499 dspi->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "dspi", base,
500 &dspi_regmap_config);
501 if (IS_ERR(dspi->regmap)) {
502 dev_err(&pdev->dev, "failed to init regmap: %ld\n",
503 PTR_ERR(dspi->regmap));
504 return PTR_ERR(dspi->regmap);
505 }
506
483 dspi->irq = platform_get_irq(pdev, 0); 507 dspi->irq = platform_get_irq(pdev, 0);
484 if (dspi->irq < 0) { 508 if (dspi->irq < 0) {
485 dev_err(&pdev->dev, "can't get platform irq\n"); 509 dev_err(&pdev->dev, "can't get platform irq\n");
diff --git a/drivers/spi/spi-fsl-espi.c b/drivers/spi/spi-fsl-espi.c
index e8e3d34bab07..e767f5831b9c 100644
--- a/drivers/spi/spi-fsl-espi.c
+++ b/drivers/spi/spi-fsl-espi.c
@@ -219,13 +219,8 @@ static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t)
219 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); 219 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
220 struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base; 220 struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base;
221 unsigned int len = t->len; 221 unsigned int len = t->len;
222 u8 bits_per_word;
223 int ret; 222 int ret;
224 223
225 bits_per_word = spi->bits_per_word;
226 if (t->bits_per_word)
227 bits_per_word = t->bits_per_word;
228
229 mpc8xxx_spi->len = t->len; 224 mpc8xxx_spi->len = t->len;
230 len = roundup(len, 4) / 4; 225 len = roundup(len, 4) / 4;
231 226
diff --git a/drivers/spi/spi-fsl-lib.c b/drivers/spi/spi-fsl-lib.c
index 0b75f26158ab..e5d45fca3551 100644
--- a/drivers/spi/spi-fsl-lib.c
+++ b/drivers/spi/spi-fsl-lib.c
@@ -200,7 +200,7 @@ int of_mpc8xxx_spi_probe(struct platform_device *ofdev)
200 const void *prop; 200 const void *prop;
201 int ret = -ENOMEM; 201 int ret = -ENOMEM;
202 202
203 pinfo = kzalloc(sizeof(*pinfo), GFP_KERNEL); 203 pinfo = devm_kzalloc(&ofdev->dev, sizeof(*pinfo), GFP_KERNEL);
204 if (!pinfo) 204 if (!pinfo)
205 return -ENOMEM; 205 return -ENOMEM;
206 206
@@ -215,15 +215,13 @@ int of_mpc8xxx_spi_probe(struct platform_device *ofdev)
215 pdata->sysclk = get_brgfreq(); 215 pdata->sysclk = get_brgfreq();
216 if (pdata->sysclk == -1) { 216 if (pdata->sysclk == -1) {
217 pdata->sysclk = fsl_get_sys_freq(); 217 pdata->sysclk = fsl_get_sys_freq();
218 if (pdata->sysclk == -1) { 218 if (pdata->sysclk == -1)
219 ret = -ENODEV; 219 return -ENODEV;
220 goto err;
221 }
222 } 220 }
223#else 221#else
224 ret = of_property_read_u32(np, "clock-frequency", &pdata->sysclk); 222 ret = of_property_read_u32(np, "clock-frequency", &pdata->sysclk);
225 if (ret) 223 if (ret)
226 goto err; 224 return ret;
227#endif 225#endif
228 226
229 prop = of_get_property(np, "mode", NULL); 227 prop = of_get_property(np, "mode", NULL);
@@ -237,8 +235,4 @@ int of_mpc8xxx_spi_probe(struct platform_device *ofdev)
237 pdata->flags = SPI_CPM_MODE | SPI_CPM1; 235 pdata->flags = SPI_CPM_MODE | SPI_CPM1;
238 236
239 return 0; 237 return 0;
240
241err:
242 kfree(pinfo);
243 return ret;
244} 238}
diff --git a/drivers/spi/spi-fsl-spi.c b/drivers/spi/spi-fsl-spi.c
index f2af3eb3ceb7..b3e7775034db 100644
--- a/drivers/spi/spi-fsl-spi.c
+++ b/drivers/spi/spi-fsl-spi.c
@@ -239,12 +239,6 @@ static int fsl_spi_setup_transfer(struct spi_device *spi,
239 if (!bits_per_word) 239 if (!bits_per_word)
240 bits_per_word = spi->bits_per_word; 240 bits_per_word = spi->bits_per_word;
241 241
242 /* Make sure its a bit width we support [4..16, 32] */
243 if ((bits_per_word < 4)
244 || ((bits_per_word > 16) && (bits_per_word != 32))
245 || (bits_per_word > mpc8xxx_spi->max_bits_per_word))
246 return -EINVAL;
247
248 if (!hz) 242 if (!hz)
249 hz = spi->max_speed_hz; 243 hz = spi->max_speed_hz;
250 244
@@ -362,18 +356,28 @@ static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t,
362static void fsl_spi_do_one_msg(struct spi_message *m) 356static void fsl_spi_do_one_msg(struct spi_message *m)
363{ 357{
364 struct spi_device *spi = m->spi; 358 struct spi_device *spi = m->spi;
365 struct spi_transfer *t; 359 struct spi_transfer *t, *first;
366 unsigned int cs_change; 360 unsigned int cs_change;
367 const int nsecs = 50; 361 const int nsecs = 50;
368 int status; 362 int status;
369 363
370 cs_change = 1; 364 /* Don't allow changes if CS is active */
371 status = 0; 365 first = list_first_entry(&m->transfers, struct spi_transfer,
366 transfer_list);
372 list_for_each_entry(t, &m->transfers, transfer_list) { 367 list_for_each_entry(t, &m->transfers, transfer_list) {
373 if (t->bits_per_word || t->speed_hz) { 368 if ((first->bits_per_word != t->bits_per_word) ||
374 /* Don't allow changes if CS is active */ 369 (first->speed_hz != t->speed_hz)) {
375 status = -EINVAL; 370 status = -EINVAL;
371 dev_err(&spi->dev,
372 "bits_per_word/speed_hz should be same for the same SPI transfer\n");
373 return;
374 }
375 }
376 376
377 cs_change = 1;
378 status = -EINVAL;
379 list_for_each_entry(t, &m->transfers, transfer_list) {
380 if (t->bits_per_word || t->speed_hz) {
377 if (cs_change) 381 if (cs_change)
378 status = fsl_spi_setup_transfer(spi, t); 382 status = fsl_spi_setup_transfer(spi, t);
379 if (status < 0) 383 if (status < 0)
@@ -642,6 +646,10 @@ static struct spi_master * fsl_spi_probe(struct device *dev,
642 if (mpc8xxx_spi->type == TYPE_GRLIB) 646 if (mpc8xxx_spi->type == TYPE_GRLIB)
643 fsl_spi_grlib_probe(dev); 647 fsl_spi_grlib_probe(dev);
644 648
649 master->bits_per_word_mask =
650 (SPI_BPW_RANGE_MASK(4, 16) | SPI_BPW_MASK(32)) &
651 SPI_BPW_RANGE_MASK(1, mpc8xxx_spi->max_bits_per_word);
652
645 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) 653 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
646 mpc8xxx_spi->set_shifts = fsl_spi_qe_cpu_set_shifts; 654 mpc8xxx_spi->set_shifts = fsl_spi_qe_cpu_set_shifts;
647 655
diff --git a/drivers/spi/spi-gpio.c b/drivers/spi/spi-gpio.c
index 7beeb29472ac..09823076df88 100644
--- a/drivers/spi/spi-gpio.c
+++ b/drivers/spi/spi-gpio.c
@@ -19,7 +19,6 @@
19 */ 19 */
20#include <linux/kernel.h> 20#include <linux/kernel.h>
21#include <linux/module.h> 21#include <linux/module.h>
22#include <linux/init.h>
23#include <linux/platform_device.h> 22#include <linux/platform_device.h>
24#include <linux/gpio.h> 23#include <linux/gpio.h>
25#include <linux/of.h> 24#include <linux/of.h>
@@ -250,7 +249,7 @@ static int spi_gpio_setup(struct spi_device *spi)
250 /* 249 /*
251 * ... otherwise, take it from spi->controller_data 250 * ... otherwise, take it from spi->controller_data
252 */ 251 */
253 cs = (unsigned int) spi->controller_data; 252 cs = (unsigned int)(uintptr_t) spi->controller_data;
254 } 253 }
255 254
256 if (!spi->controller_state) { 255 if (!spi->controller_state) {
@@ -503,13 +502,12 @@ static int spi_gpio_remove(struct platform_device *pdev)
503{ 502{
504 struct spi_gpio *spi_gpio; 503 struct spi_gpio *spi_gpio;
505 struct spi_gpio_platform_data *pdata; 504 struct spi_gpio_platform_data *pdata;
506 int status;
507 505
508 spi_gpio = platform_get_drvdata(pdev); 506 spi_gpio = platform_get_drvdata(pdev);
509 pdata = dev_get_platdata(&pdev->dev); 507 pdata = dev_get_platdata(&pdev->dev);
510 508
511 /* stop() unregisters child devices too */ 509 /* stop() unregisters child devices too */
512 status = spi_bitbang_stop(&spi_gpio->bitbang); 510 spi_bitbang_stop(&spi_gpio->bitbang);
513 511
514 if (SPI_MISO_GPIO != SPI_GPIO_NO_MISO) 512 if (SPI_MISO_GPIO != SPI_GPIO_NO_MISO)
515 gpio_free(SPI_MISO_GPIO); 513 gpio_free(SPI_MISO_GPIO);
@@ -518,7 +516,7 @@ static int spi_gpio_remove(struct platform_device *pdev)
518 gpio_free(SPI_SCK_GPIO); 516 gpio_free(SPI_SCK_GPIO);
519 spi_master_put(spi_gpio->bitbang.master); 517 spi_master_put(spi_gpio->bitbang.master);
520 518
521 return status; 519 return 0;
522} 520}
523 521
524MODULE_ALIAS("platform:" DRIVER_NAME); 522MODULE_ALIAS("platform:" DRIVER_NAME);
diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
index 47f15d97e7fa..5daff2054ae4 100644
--- a/drivers/spi/spi-imx.c
+++ b/drivers/spi/spi-imx.c
@@ -23,7 +23,6 @@
23#include <linux/delay.h> 23#include <linux/delay.h>
24#include <linux/err.h> 24#include <linux/err.h>
25#include <linux/gpio.h> 25#include <linux/gpio.h>
26#include <linux/init.h>
27#include <linux/interrupt.h> 26#include <linux/interrupt.h>
28#include <linux/io.h> 27#include <linux/io.h>
29#include <linux/irq.h> 28#include <linux/irq.h>
@@ -741,7 +740,7 @@ static int spi_imx_transfer(struct spi_device *spi,
741 spi_imx->count = transfer->len; 740 spi_imx->count = transfer->len;
742 spi_imx->txfifo = 0; 741 spi_imx->txfifo = 0;
743 742
744 init_completion(&spi_imx->xfer_done); 743 reinit_completion(&spi_imx->xfer_done);
745 744
746 spi_imx_push(spi_imx); 745 spi_imx_push(spi_imx);
747 746
@@ -880,12 +879,12 @@ static int spi_imx_probe(struct platform_device *pdev)
880 879
881 spi_imx->irq = platform_get_irq(pdev, 0); 880 spi_imx->irq = platform_get_irq(pdev, 0);
882 if (spi_imx->irq < 0) { 881 if (spi_imx->irq < 0) {
883 ret = -EINVAL; 882 ret = spi_imx->irq;
884 goto out_master_put; 883 goto out_master_put;
885 } 884 }
886 885
887 ret = devm_request_irq(&pdev->dev, spi_imx->irq, spi_imx_isr, 0, 886 ret = devm_request_irq(&pdev->dev, spi_imx->irq, spi_imx_isr, 0,
888 DRIVER_NAME, spi_imx); 887 dev_name(&pdev->dev), spi_imx);
889 if (ret) { 888 if (ret) {
890 dev_err(&pdev->dev, "can't get irq%d: %d\n", spi_imx->irq, ret); 889 dev_err(&pdev->dev, "can't get irq%d: %d\n", spi_imx->irq, ret);
891 goto out_master_put; 890 goto out_master_put;
diff --git a/drivers/spi/spi-mpc512x-psc.c b/drivers/spi/spi-mpc512x-psc.c
index 8eee745e8471..577d23a12763 100644
--- a/drivers/spi/spi-mpc512x-psc.c
+++ b/drivers/spi/spi-mpc512x-psc.c
@@ -16,7 +16,6 @@
16 16
17#include <linux/module.h> 17#include <linux/module.h>
18#include <linux/kernel.h> 18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/errno.h> 19#include <linux/errno.h>
21#include <linux/interrupt.h> 20#include <linux/interrupt.h>
22#include <linux/of_address.h> 21#include <linux/of_address.h>
@@ -467,10 +466,8 @@ static void mpc512x_spi_cs_control(struct spi_device *spi, bool onoff)
467 gpio_set_value(spi->cs_gpio, onoff); 466 gpio_set_value(spi->cs_gpio, onoff);
468} 467}
469 468
470/* bus_num is used only for the case dev->platform_data == NULL */
471static int mpc512x_psc_spi_do_probe(struct device *dev, u32 regaddr, 469static int mpc512x_psc_spi_do_probe(struct device *dev, u32 regaddr,
472 u32 size, unsigned int irq, 470 u32 size, unsigned int irq)
473 s16 bus_num)
474{ 471{
475 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); 472 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
476 struct mpc512x_psc_spi *mps; 473 struct mpc512x_psc_spi *mps;
@@ -489,7 +486,6 @@ static int mpc512x_psc_spi_do_probe(struct device *dev, u32 regaddr,
489 486
490 if (pdata == NULL) { 487 if (pdata == NULL) {
491 mps->cs_control = mpc512x_spi_cs_control; 488 mps->cs_control = mpc512x_spi_cs_control;
492 master->bus_num = bus_num;
493 } else { 489 } else {
494 mps->cs_control = pdata->cs_control; 490 mps->cs_control = pdata->cs_control;
495 master->bus_num = pdata->bus_num; 491 master->bus_num = pdata->bus_num;
@@ -575,7 +571,6 @@ static int mpc512x_psc_spi_of_probe(struct platform_device *op)
575{ 571{
576 const u32 *regaddr_p; 572 const u32 *regaddr_p;
577 u64 regaddr64, size64; 573 u64 regaddr64, size64;
578 s16 id = -1;
579 574
580 regaddr_p = of_get_address(op->dev.of_node, 0, &size64, NULL); 575 regaddr_p = of_get_address(op->dev.of_node, 0, &size64, NULL);
581 if (!regaddr_p) { 576 if (!regaddr_p) {
@@ -584,16 +579,8 @@ static int mpc512x_psc_spi_of_probe(struct platform_device *op)
584 } 579 }
585 regaddr64 = of_translate_address(op->dev.of_node, regaddr_p); 580 regaddr64 = of_translate_address(op->dev.of_node, regaddr_p);
586 581
587 /* get PSC id (0..11, used by port_config) */
588 id = of_alias_get_id(op->dev.of_node, "spi");
589 if (id < 0) {
590 dev_err(&op->dev, "no alias id for %s\n",
591 op->dev.of_node->full_name);
592 return id;
593 }
594
595 return mpc512x_psc_spi_do_probe(&op->dev, (u32) regaddr64, (u32) size64, 582 return mpc512x_psc_spi_do_probe(&op->dev, (u32) regaddr64, (u32) size64,
596 irq_of_parse_and_map(op->dev.of_node, 0), id); 583 irq_of_parse_and_map(op->dev.of_node, 0));
597} 584}
598 585
599static int mpc512x_psc_spi_of_remove(struct platform_device *op) 586static int mpc512x_psc_spi_of_remove(struct platform_device *op)
diff --git a/drivers/spi/spi-mpc52xx-psc.c b/drivers/spi/spi-mpc52xx-psc.c
index d761bc0dc5ce..de532aa11d34 100644
--- a/drivers/spi/spi-mpc52xx-psc.c
+++ b/drivers/spi/spi-mpc52xx-psc.c
@@ -12,7 +12,6 @@
12 */ 12 */
13 13
14#include <linux/module.h> 14#include <linux/module.h>
15#include <linux/init.h>
16#include <linux/types.h> 15#include <linux/types.h>
17#include <linux/errno.h> 16#include <linux/errno.h>
18#include <linux/interrupt.h> 17#include <linux/interrupt.h>
diff --git a/drivers/spi/spi-mpc52xx.c b/drivers/spi/spi-mpc52xx.c
index a0de12ac1deb..b07db4b62d80 100644
--- a/drivers/spi/spi-mpc52xx.c
+++ b/drivers/spi/spi-mpc52xx.c
@@ -12,7 +12,6 @@
12 */ 12 */
13 13
14#include <linux/module.h> 14#include <linux/module.h>
15#include <linux/init.h>
16#include <linux/errno.h> 15#include <linux/errno.h>
17#include <linux/of_platform.h> 16#include <linux/of_platform.h>
18#include <linux/interrupt.h> 17#include <linux/interrupt.h>
@@ -359,20 +358,6 @@ static void mpc52xx_spi_wq(struct work_struct *work)
359 * spi_master ops 358 * spi_master ops
360 */ 359 */
361 360
362static int mpc52xx_spi_setup(struct spi_device *spi)
363{
364 if (spi->bits_per_word % 8)
365 return -EINVAL;
366
367 if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST))
368 return -EINVAL;
369
370 if (spi->chip_select >= spi->master->num_chipselect)
371 return -EINVAL;
372
373 return 0;
374}
375
376static int mpc52xx_spi_transfer(struct spi_device *spi, struct spi_message *m) 361static int mpc52xx_spi_transfer(struct spi_device *spi, struct spi_message *m)
377{ 362{
378 struct mpc52xx_spi *ms = spi_master_get_devdata(spi->master); 363 struct mpc52xx_spi *ms = spi_master_get_devdata(spi->master);
@@ -435,9 +420,9 @@ static int mpc52xx_spi_probe(struct platform_device *op)
435 goto err_alloc; 420 goto err_alloc;
436 } 421 }
437 422
438 master->setup = mpc52xx_spi_setup;
439 master->transfer = mpc52xx_spi_transfer; 423 master->transfer = mpc52xx_spi_transfer;
440 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; 424 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
425 master->bits_per_word_mask = SPI_BPW_MASK(8);
441 master->dev.of_node = op->dev.of_node; 426 master->dev.of_node = op->dev.of_node;
442 427
443 platform_set_drvdata(op, master); 428 platform_set_drvdata(op, master);
diff --git a/drivers/spi/spi-mxs.c b/drivers/spi/spi-mxs.c
index 79e5aa2250c8..2884f0c2f5f0 100644
--- a/drivers/spi/spi-mxs.c
+++ b/drivers/spi/spi-mxs.c
@@ -29,7 +29,6 @@
29 */ 29 */
30 30
31#include <linux/kernel.h> 31#include <linux/kernel.h>
32#include <linux/init.h>
33#include <linux/ioport.h> 32#include <linux/ioport.h>
34#include <linux/of.h> 33#include <linux/of.h>
35#include <linux/of_device.h> 34#include <linux/of_device.h>
@@ -371,7 +370,7 @@ static int mxs_spi_transfer_one(struct spi_master *master,
371{ 370{
372 struct mxs_spi *spi = spi_master_get_devdata(master); 371 struct mxs_spi *spi = spi_master_get_devdata(master);
373 struct mxs_ssp *ssp = &spi->ssp; 372 struct mxs_ssp *ssp = &spi->ssp;
374 struct spi_transfer *t, *tmp_t; 373 struct spi_transfer *t;
375 unsigned int flag; 374 unsigned int flag;
376 int status = 0; 375 int status = 0;
377 376
@@ -381,7 +380,7 @@ static int mxs_spi_transfer_one(struct spi_master *master,
381 writel(mxs_spi_cs_to_reg(m->spi->chip_select), 380 writel(mxs_spi_cs_to_reg(m->spi->chip_select),
382 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); 381 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
383 382
384 list_for_each_entry_safe(t, tmp_t, &m->transfers, transfer_list) { 383 list_for_each_entry(t, &m->transfers, transfer_list) {
385 384
386 status = mxs_spi_setup_transfer(m->spi, t); 385 status = mxs_spi_setup_transfer(m->spi, t);
387 if (status) 386 if (status)
@@ -473,7 +472,7 @@ static int mxs_spi_probe(struct platform_device *pdev)
473 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 472 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
474 irq_err = platform_get_irq(pdev, 0); 473 irq_err = platform_get_irq(pdev, 0);
475 if (irq_err < 0) 474 if (irq_err < 0)
476 return -EINVAL; 475 return irq_err;
477 476
478 base = devm_ioremap_resource(&pdev->dev, iores); 477 base = devm_ioremap_resource(&pdev->dev, iores);
479 if (IS_ERR(base)) 478 if (IS_ERR(base))
diff --git a/drivers/spi/spi-nuc900.c b/drivers/spi/spi-nuc900.c
index bae97ffec4b9..16e30de650b0 100644
--- a/drivers/spi/spi-nuc900.c
+++ b/drivers/spi/spi-nuc900.c
@@ -9,7 +9,6 @@
9 */ 9 */
10 10
11#include <linux/module.h> 11#include <linux/module.h>
12#include <linux/init.h>
13#include <linux/spinlock.h> 12#include <linux/spinlock.h>
14#include <linux/workqueue.h> 13#include <linux/workqueue.h>
15#include <linux/interrupt.h> 14#include <linux/interrupt.h>
@@ -38,7 +37,9 @@
38/* usi register bit */ 37/* usi register bit */
39#define ENINT (0x01 << 17) 38#define ENINT (0x01 << 17)
40#define ENFLG (0x01 << 16) 39#define ENFLG (0x01 << 16)
40#define SLEEP (0x0f << 12)
41#define TXNUM (0x03 << 8) 41#define TXNUM (0x03 << 8)
42#define TXBITLEN (0x1f << 3)
42#define TXNEG (0x01 << 2) 43#define TXNEG (0x01 << 2)
43#define RXNEG (0x01 << 1) 44#define RXNEG (0x01 << 1)
44#define LSB (0x01 << 10) 45#define LSB (0x01 << 10)
@@ -58,11 +59,8 @@ struct nuc900_spi {
58 unsigned char *rx; 59 unsigned char *rx;
59 struct clk *clk; 60 struct clk *clk;
60 struct spi_master *master; 61 struct spi_master *master;
61 struct spi_device *curdev;
62 struct device *dev;
63 struct nuc900_spi_info *pdata; 62 struct nuc900_spi_info *pdata;
64 spinlock_t lock; 63 spinlock_t lock;
65 struct resource *res;
66}; 64};
67 65
68static inline struct nuc900_spi *to_hw(struct spi_device *sdev) 66static inline struct nuc900_spi *to_hw(struct spi_device *sdev)
@@ -119,19 +117,16 @@ static void nuc900_spi_chipsel(struct spi_device *spi, int value)
119 } 117 }
120} 118}
121 119
122static void nuc900_spi_setup_txnum(struct nuc900_spi *hw, 120static void nuc900_spi_setup_txnum(struct nuc900_spi *hw, unsigned int txnum)
123 unsigned int txnum)
124{ 121{
125 unsigned int val; 122 unsigned int val;
126 unsigned long flags; 123 unsigned long flags;
127 124
128 spin_lock_irqsave(&hw->lock, flags); 125 spin_lock_irqsave(&hw->lock, flags);
129 126
130 val = __raw_readl(hw->regs + USI_CNT); 127 val = __raw_readl(hw->regs + USI_CNT) & ~TXNUM;
131 128
132 if (!txnum) 129 if (txnum)
133 val &= ~TXNUM;
134 else
135 val |= txnum << 0x08; 130 val |= txnum << 0x08;
136 131
137 __raw_writel(val, hw->regs + USI_CNT); 132 __raw_writel(val, hw->regs + USI_CNT);
@@ -148,7 +143,7 @@ static void nuc900_spi_setup_txbitlen(struct nuc900_spi *hw,
148 143
149 spin_lock_irqsave(&hw->lock, flags); 144 spin_lock_irqsave(&hw->lock, flags);
150 145
151 val = __raw_readl(hw->regs + USI_CNT); 146 val = __raw_readl(hw->regs + USI_CNT) & ~TXBITLEN;
152 147
153 val |= (txbitlen << 0x03); 148 val |= (txbitlen << 0x03);
154 149
@@ -287,12 +282,11 @@ static void nuc900_set_sleep(struct nuc900_spi *hw, unsigned int sleep)
287 282
288 spin_lock_irqsave(&hw->lock, flags); 283 spin_lock_irqsave(&hw->lock, flags);
289 284
290 val = __raw_readl(hw->regs + USI_CNT); 285 val = __raw_readl(hw->regs + USI_CNT) & ~SLEEP;
291 286
292 if (sleep) 287 if (sleep)
293 val |= (sleep << 12); 288 val |= (sleep << 12);
294 else 289
295 val &= ~(0x0f << 12);
296 __raw_writel(val, hw->regs + USI_CNT); 290 __raw_writel(val, hw->regs + USI_CNT);
297 291
298 spin_unlock_irqrestore(&hw->lock, flags); 292 spin_unlock_irqrestore(&hw->lock, flags);
@@ -338,6 +332,7 @@ static int nuc900_spi_probe(struct platform_device *pdev)
338{ 332{
339 struct nuc900_spi *hw; 333 struct nuc900_spi *hw;
340 struct spi_master *master; 334 struct spi_master *master;
335 struct resource *res;
341 int err = 0; 336 int err = 0;
342 337
343 master = spi_alloc_master(&pdev->dev, sizeof(struct nuc900_spi)); 338 master = spi_alloc_master(&pdev->dev, sizeof(struct nuc900_spi));
@@ -349,7 +344,6 @@ static int nuc900_spi_probe(struct platform_device *pdev)
349 hw = spi_master_get_devdata(master); 344 hw = spi_master_get_devdata(master);
350 hw->master = master; 345 hw->master = master;
351 hw->pdata = dev_get_platdata(&pdev->dev); 346 hw->pdata = dev_get_platdata(&pdev->dev);
352 hw->dev = &pdev->dev;
353 347
354 if (hw->pdata == NULL) { 348 if (hw->pdata == NULL) {
355 dev_err(&pdev->dev, "No platform data supplied\n"); 349 dev_err(&pdev->dev, "No platform data supplied\n");
@@ -369,8 +363,8 @@ static int nuc900_spi_probe(struct platform_device *pdev)
369 hw->bitbang.chipselect = nuc900_spi_chipsel; 363 hw->bitbang.chipselect = nuc900_spi_chipsel;
370 hw->bitbang.txrx_bufs = nuc900_spi_txrx; 364 hw->bitbang.txrx_bufs = nuc900_spi_txrx;
371 365
372 hw->res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 366 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
373 hw->regs = devm_ioremap_resource(&pdev->dev, hw->res); 367 hw->regs = devm_ioremap_resource(&pdev->dev, res);
374 if (IS_ERR(hw->regs)) { 368 if (IS_ERR(hw->regs)) {
375 err = PTR_ERR(hw->regs); 369 err = PTR_ERR(hw->regs);
376 goto err_pdata; 370 goto err_pdata;
diff --git a/drivers/spi/spi-oc-tiny.c b/drivers/spi/spi-oc-tiny.c
index f7c896e2981e..8998d11c7238 100644
--- a/drivers/spi/spi-oc-tiny.c
+++ b/drivers/spi/spi-oc-tiny.c
@@ -15,7 +15,6 @@
15 * published by the Free Software Foundation. 15 * published by the Free Software Foundation.
16 */ 16 */
17 17
18#include <linux/init.h>
19#include <linux/interrupt.h> 18#include <linux/interrupt.h>
20#include <linux/errno.h> 19#include <linux/errno.h>
21#include <linux/module.h> 20#include <linux/module.h>
@@ -267,8 +266,6 @@ static int tiny_spi_probe(struct platform_device *pdev)
267 266
268 /* setup the state for the bitbang driver */ 267 /* setup the state for the bitbang driver */
269 hw->bitbang.master = master; 268 hw->bitbang.master = master;
270 if (!hw->bitbang.master)
271 return err;
272 hw->bitbang.setup_transfer = tiny_spi_setup_transfer; 269 hw->bitbang.setup_transfer = tiny_spi_setup_transfer;
273 hw->bitbang.chipselect = tiny_spi_chipselect; 270 hw->bitbang.chipselect = tiny_spi_chipselect;
274 hw->bitbang.txrx_bufs = tiny_spi_txrx_bufs; 271 hw->bitbang.txrx_bufs = tiny_spi_txrx_bufs;
diff --git a/drivers/spi/spi-octeon.c b/drivers/spi/spi-octeon.c
index 67249a48b391..c5e2f718eebd 100644
--- a/drivers/spi/spi-octeon.c
+++ b/drivers/spi/spi-octeon.c
@@ -11,7 +11,6 @@
11#include <linux/spi/spi.h> 11#include <linux/spi/spi.h>
12#include <linux/module.h> 12#include <linux/module.h>
13#include <linux/delay.h> 13#include <linux/delay.h>
14#include <linux/init.h>
15#include <linux/io.h> 14#include <linux/io.h>
16#include <linux/of.h> 15#include <linux/of.h>
17 16
@@ -33,13 +32,6 @@ struct octeon_spi {
33 u64 cs_enax; 32 u64 cs_enax;
34}; 33};
35 34
36struct octeon_spi_setup {
37 u32 max_speed_hz;
38 u8 chip_select;
39 u8 mode;
40 u8 bits_per_word;
41};
42
43static void octeon_spi_wait_ready(struct octeon_spi *p) 35static void octeon_spi_wait_ready(struct octeon_spi *p)
44{ 36{
45 union cvmx_mpi_sts mpi_sts; 37 union cvmx_mpi_sts mpi_sts;
@@ -57,6 +49,7 @@ static int octeon_spi_do_transfer(struct octeon_spi *p,
57 struct spi_transfer *xfer, 49 struct spi_transfer *xfer,
58 bool last_xfer) 50 bool last_xfer)
59{ 51{
52 struct spi_device *spi = msg->spi;
60 union cvmx_mpi_cfg mpi_cfg; 53 union cvmx_mpi_cfg mpi_cfg;
61 union cvmx_mpi_tx mpi_tx; 54 union cvmx_mpi_tx mpi_tx;
62 unsigned int clkdiv; 55 unsigned int clkdiv;
@@ -68,18 +61,11 @@ static int octeon_spi_do_transfer(struct octeon_spi *p,
68 int len; 61 int len;
69 int i; 62 int i;
70 63
71 struct octeon_spi_setup *msg_setup = spi_get_ctldata(msg->spi); 64 mode = spi->mode;
72
73 speed_hz = msg_setup->max_speed_hz;
74 mode = msg_setup->mode;
75 cpha = mode & SPI_CPHA; 65 cpha = mode & SPI_CPHA;
76 cpol = mode & SPI_CPOL; 66 cpol = mode & SPI_CPOL;
77 67
78 if (xfer->speed_hz) 68 speed_hz = xfer->speed_hz ? : spi->max_speed_hz;
79 speed_hz = xfer->speed_hz;
80
81 if (speed_hz > OCTEON_SPI_MAX_CLOCK_HZ)
82 speed_hz = OCTEON_SPI_MAX_CLOCK_HZ;
83 69
84 clkdiv = octeon_get_io_clock_rate() / (2 * speed_hz); 70 clkdiv = octeon_get_io_clock_rate() / (2 * speed_hz);
85 71
@@ -93,8 +79,8 @@ static int octeon_spi_do_transfer(struct octeon_spi *p,
93 mpi_cfg.s.cslate = cpha ? 1 : 0; 79 mpi_cfg.s.cslate = cpha ? 1 : 0;
94 mpi_cfg.s.enable = 1; 80 mpi_cfg.s.enable = 1;
95 81
96 if (msg_setup->chip_select < 4) 82 if (spi->chip_select < 4)
97 p->cs_enax |= 1ull << (12 + msg_setup->chip_select); 83 p->cs_enax |= 1ull << (12 + spi->chip_select);
98 mpi_cfg.u64 |= p->cs_enax; 84 mpi_cfg.u64 |= p->cs_enax;
99 85
100 if (mpi_cfg.u64 != p->last_cfg) { 86 if (mpi_cfg.u64 != p->last_cfg) {
@@ -114,7 +100,7 @@ static int octeon_spi_do_transfer(struct octeon_spi *p,
114 cvmx_write_csr(p->register_base + OCTEON_SPI_DAT0 + (8 * i), d); 100 cvmx_write_csr(p->register_base + OCTEON_SPI_DAT0 + (8 * i), d);
115 } 101 }
116 mpi_tx.u64 = 0; 102 mpi_tx.u64 = 0;
117 mpi_tx.s.csid = msg_setup->chip_select; 103 mpi_tx.s.csid = spi->chip_select;
118 mpi_tx.s.leavecs = 1; 104 mpi_tx.s.leavecs = 1;
119 mpi_tx.s.txnum = tx_buf ? OCTEON_SPI_MAX_BYTES : 0; 105 mpi_tx.s.txnum = tx_buf ? OCTEON_SPI_MAX_BYTES : 0;
120 mpi_tx.s.totnum = OCTEON_SPI_MAX_BYTES; 106 mpi_tx.s.totnum = OCTEON_SPI_MAX_BYTES;
@@ -139,7 +125,7 @@ static int octeon_spi_do_transfer(struct octeon_spi *p,
139 } 125 }
140 126
141 mpi_tx.u64 = 0; 127 mpi_tx.u64 = 0;
142 mpi_tx.s.csid = msg_setup->chip_select; 128 mpi_tx.s.csid = spi->chip_select;
143 if (last_xfer) 129 if (last_xfer)
144 mpi_tx.s.leavecs = xfer->cs_change; 130 mpi_tx.s.leavecs = xfer->cs_change;
145 else 131 else
@@ -169,17 +155,9 @@ static int octeon_spi_transfer_one_message(struct spi_master *master,
169 int status = 0; 155 int status = 0;
170 struct spi_transfer *xfer; 156 struct spi_transfer *xfer;
171 157
172 /*
173 * We better have set the configuration via a call to .setup
174 * before we get here.
175 */
176 if (spi_get_ctldata(msg->spi) == NULL) {
177 status = -EINVAL;
178 goto err;
179 }
180
181 list_for_each_entry(xfer, &msg->transfers, transfer_list) { 158 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
182 bool last_xfer = &xfer->transfer_list == msg->transfers.prev; 159 bool last_xfer = list_is_last(&xfer->transfer_list,
160 &msg->transfers);
183 int r = octeon_spi_do_transfer(p, msg, xfer, last_xfer); 161 int r = octeon_spi_do_transfer(p, msg, xfer, last_xfer);
184 if (r < 0) { 162 if (r < 0) {
185 status = r; 163 status = r;
@@ -194,41 +172,6 @@ err:
194 return status; 172 return status;
195} 173}
196 174
197static struct octeon_spi_setup *octeon_spi_new_setup(struct spi_device *spi)
198{
199 struct octeon_spi_setup *setup = kzalloc(sizeof(*setup), GFP_KERNEL);
200 if (!setup)
201 return NULL;
202
203 setup->max_speed_hz = spi->max_speed_hz;
204 setup->chip_select = spi->chip_select;
205 setup->mode = spi->mode;
206 setup->bits_per_word = spi->bits_per_word;
207 return setup;
208}
209
210static int octeon_spi_setup(struct spi_device *spi)
211{
212 struct octeon_spi_setup *new_setup;
213 struct octeon_spi_setup *old_setup = spi_get_ctldata(spi);
214
215 new_setup = octeon_spi_new_setup(spi);
216 if (!new_setup)
217 return -ENOMEM;
218
219 spi_set_ctldata(spi, new_setup);
220 kfree(old_setup);
221
222 return 0;
223}
224
225static void octeon_spi_cleanup(struct spi_device *spi)
226{
227 struct octeon_spi_setup *old_setup = spi_get_ctldata(spi);
228 spi_set_ctldata(spi, NULL);
229 kfree(old_setup);
230}
231
232static int octeon_spi_probe(struct platform_device *pdev) 175static int octeon_spi_probe(struct platform_device *pdev)
233{ 176{
234 struct resource *res_mem; 177 struct resource *res_mem;
@@ -257,8 +200,6 @@ static int octeon_spi_probe(struct platform_device *pdev)
257 p->register_base = (u64)devm_ioremap(&pdev->dev, res_mem->start, 200 p->register_base = (u64)devm_ioremap(&pdev->dev, res_mem->start,
258 resource_size(res_mem)); 201 resource_size(res_mem));
259 202
260 /* Dynamic bus numbering */
261 master->bus_num = -1;
262 master->num_chipselect = 4; 203 master->num_chipselect = 4;
263 master->mode_bits = SPI_CPHA | 204 master->mode_bits = SPI_CPHA |
264 SPI_CPOL | 205 SPI_CPOL |
@@ -266,10 +207,9 @@ static int octeon_spi_probe(struct platform_device *pdev)
266 SPI_LSB_FIRST | 207 SPI_LSB_FIRST |
267 SPI_3WIRE; 208 SPI_3WIRE;
268 209
269 master->setup = octeon_spi_setup;
270 master->cleanup = octeon_spi_cleanup;
271 master->transfer_one_message = octeon_spi_transfer_one_message; 210 master->transfer_one_message = octeon_spi_transfer_one_message;
272 master->bits_per_word_mask = SPI_BPW_MASK(8); 211 master->bits_per_word_mask = SPI_BPW_MASK(8);
212 master->max_speed_hz = OCTEON_SPI_MAX_CLOCK_HZ;
273 213
274 master->dev.of_node = pdev->dev.of_node; 214 master->dev.of_node = pdev->dev.of_node;
275 err = devm_spi_register_master(&pdev->dev, master); 215 err = devm_spi_register_master(&pdev->dev, master);
diff --git a/drivers/spi/spi-omap-100k.c b/drivers/spi/spi-omap-100k.c
index 0d32054bfc0d..e7ffcded4e14 100644
--- a/drivers/spi/spi-omap-100k.c
+++ b/drivers/spi/spi-omap-100k.c
@@ -83,15 +83,11 @@
83#define SPI_SHUTDOWN 1 83#define SPI_SHUTDOWN 1
84 84
85struct omap1_spi100k { 85struct omap1_spi100k {
86 struct spi_master *master;
87 struct clk *ick; 86 struct clk *ick;
88 struct clk *fck; 87 struct clk *fck;
89 88
90 /* Virtual base address of the controller */ 89 /* Virtual base address of the controller */
91 void __iomem *base; 90 void __iomem *base;
92
93 /* State of the SPI */
94 unsigned int state;
95}; 91};
96 92
97struct omap1_spi100k_cs { 93struct omap1_spi100k_cs {
@@ -99,13 +95,6 @@ struct omap1_spi100k_cs {
99 int word_len; 95 int word_len;
100}; 96};
101 97
102#define MOD_REG_BIT(val, mask, set) do { \
103 if (set) \
104 val |= mask; \
105 else \
106 val &= ~mask; \
107} while (0)
108
109static void spi100k_enable_clock(struct spi_master *master) 98static void spi100k_enable_clock(struct spi_master *master)
110{ 99{
111 unsigned int val; 100 unsigned int val;
@@ -139,7 +128,7 @@ static void spi100k_write_data(struct spi_master *master, int len, int data)
139 } 128 }
140 129
141 spi100k_enable_clock(master); 130 spi100k_enable_clock(master);
142 writew( data , spi100k->base + SPI_TX_MSB); 131 writew(data , spi100k->base + SPI_TX_MSB);
143 132
144 writew(SPI_CTRL_SEN(0) | 133 writew(SPI_CTRL_SEN(0) |
145 SPI_CTRL_WORD_SIZE(len) | 134 SPI_CTRL_WORD_SIZE(len) |
@@ -147,7 +136,8 @@ static void spi100k_write_data(struct spi_master *master, int len, int data)
147 spi100k->base + SPI_CTRL); 136 spi100k->base + SPI_CTRL);
148 137
149 /* Wait for bit ack send change */ 138 /* Wait for bit ack send change */
150 while((readw(spi100k->base + SPI_STATUS) & SPI_STATUS_WE) != SPI_STATUS_WE); 139 while ((readw(spi100k->base + SPI_STATUS) & SPI_STATUS_WE) != SPI_STATUS_WE)
140 ;
151 udelay(1000); 141 udelay(1000);
152 142
153 spi100k_disable_clock(master); 143 spi100k_disable_clock(master);
@@ -155,7 +145,7 @@ static void spi100k_write_data(struct spi_master *master, int len, int data)
155 145
156static int spi100k_read_data(struct spi_master *master, int len) 146static int spi100k_read_data(struct spi_master *master, int len)
157{ 147{
158 int dataH,dataL; 148 int dataH, dataL;
159 struct omap1_spi100k *spi100k = spi_master_get_devdata(master); 149 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
160 150
161 /* Always do at least 16 bits */ 151 /* Always do at least 16 bits */
@@ -168,7 +158,8 @@ static int spi100k_read_data(struct spi_master *master, int len)
168 SPI_CTRL_RD, 158 SPI_CTRL_RD,
169 spi100k->base + SPI_CTRL); 159 spi100k->base + SPI_CTRL);
170 160
171 while((readw(spi100k->base + SPI_STATUS) & SPI_STATUS_RD) != SPI_STATUS_RD); 161 while ((readw(spi100k->base + SPI_STATUS) & SPI_STATUS_RD) != SPI_STATUS_RD)
162 ;
172 udelay(1000); 163 udelay(1000);
173 164
174 dataL = readw(spi100k->base + SPI_RX_LSB); 165 dataL = readw(spi100k->base + SPI_RX_LSB);
@@ -204,12 +195,10 @@ static void omap1_spi100k_force_cs(struct omap1_spi100k *spi100k, int enable)
204static unsigned 195static unsigned
205omap1_spi100k_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer) 196omap1_spi100k_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
206{ 197{
207 struct omap1_spi100k *spi100k;
208 struct omap1_spi100k_cs *cs = spi->controller_state; 198 struct omap1_spi100k_cs *cs = spi->controller_state;
209 unsigned int count, c; 199 unsigned int count, c;
210 int word_len; 200 int word_len;
211 201
212 spi100k = spi_master_get_devdata(spi->master);
213 count = xfer->len; 202 count = xfer->len;
214 c = count; 203 c = count;
215 word_len = cs->word_len; 204 word_len = cs->word_len;
@@ -221,12 +210,12 @@ omap1_spi100k_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
221 rx = xfer->rx_buf; 210 rx = xfer->rx_buf;
222 tx = xfer->tx_buf; 211 tx = xfer->tx_buf;
223 do { 212 do {
224 c-=1; 213 c -= 1;
225 if (xfer->tx_buf != NULL) 214 if (xfer->tx_buf != NULL)
226 spi100k_write_data(spi->master, word_len, *tx++); 215 spi100k_write_data(spi->master, word_len, *tx++);
227 if (xfer->rx_buf != NULL) 216 if (xfer->rx_buf != NULL)
228 *rx++ = spi100k_read_data(spi->master, word_len); 217 *rx++ = spi100k_read_data(spi->master, word_len);
229 } while(c); 218 } while (c);
230 } else if (word_len <= 16) { 219 } else if (word_len <= 16) {
231 u16 *rx; 220 u16 *rx;
232 const u16 *tx; 221 const u16 *tx;
@@ -234,12 +223,12 @@ omap1_spi100k_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
234 rx = xfer->rx_buf; 223 rx = xfer->rx_buf;
235 tx = xfer->tx_buf; 224 tx = xfer->tx_buf;
236 do { 225 do {
237 c-=2; 226 c -= 2;
238 if (xfer->tx_buf != NULL) 227 if (xfer->tx_buf != NULL)
239 spi100k_write_data(spi->master,word_len, *tx++); 228 spi100k_write_data(spi->master, word_len, *tx++);
240 if (xfer->rx_buf != NULL) 229 if (xfer->rx_buf != NULL)
241 *rx++ = spi100k_read_data(spi->master,word_len); 230 *rx++ = spi100k_read_data(spi->master, word_len);
242 } while(c); 231 } while (c);
243 } else if (word_len <= 32) { 232 } else if (word_len <= 32) {
244 u32 *rx; 233 u32 *rx;
245 const u32 *tx; 234 const u32 *tx;
@@ -247,12 +236,12 @@ omap1_spi100k_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
247 rx = xfer->rx_buf; 236 rx = xfer->rx_buf;
248 tx = xfer->tx_buf; 237 tx = xfer->tx_buf;
249 do { 238 do {
250 c-=4; 239 c -= 4;
251 if (xfer->tx_buf != NULL) 240 if (xfer->tx_buf != NULL)
252 spi100k_write_data(spi->master,word_len, *tx); 241 spi100k_write_data(spi->master, word_len, *tx);
253 if (xfer->rx_buf != NULL) 242 if (xfer->rx_buf != NULL)
254 *rx = spi100k_read_data(spi->master,word_len); 243 *rx = spi100k_read_data(spi->master, word_len);
255 } while(c); 244 } while (c);
256 } 245 }
257 return count - c; 246 return count - c;
258} 247}
@@ -294,7 +283,7 @@ static int omap1_spi100k_setup(struct spi_device *spi)
294 spi100k = spi_master_get_devdata(spi->master); 283 spi100k = spi_master_get_devdata(spi->master);
295 284
296 if (!cs) { 285 if (!cs) {
297 cs = kzalloc(sizeof *cs, GFP_KERNEL); 286 cs = devm_kzalloc(&spi->dev, sizeof(*cs), GFP_KERNEL);
298 if (!cs) 287 if (!cs)
299 return -ENOMEM; 288 return -ENOMEM;
300 cs->base = spi100k->base + spi->chip_select * 0x14; 289 cs->base = spi100k->base + spi->chip_select * 0x14;
@@ -411,14 +400,14 @@ static int omap1_spi100k_probe(struct platform_device *pdev)
411 if (!pdev->id) 400 if (!pdev->id)
412 return -EINVAL; 401 return -EINVAL;
413 402
414 master = spi_alloc_master(&pdev->dev, sizeof *spi100k); 403 master = spi_alloc_master(&pdev->dev, sizeof(*spi100k));
415 if (master == NULL) { 404 if (master == NULL) {
416 dev_dbg(&pdev->dev, "master allocation failed\n"); 405 dev_dbg(&pdev->dev, "master allocation failed\n");
417 return -ENOMEM; 406 return -ENOMEM;
418 } 407 }
419 408
420 if (pdev->id != -1) 409 if (pdev->id != -1)
421 master->bus_num = pdev->id; 410 master->bus_num = pdev->id;
422 411
423 master->setup = omap1_spi100k_setup; 412 master->setup = omap1_spi100k_setup;
424 master->transfer_one_message = omap1_spi100k_transfer_one_message; 413 master->transfer_one_message = omap1_spi100k_transfer_one_message;
@@ -434,7 +423,6 @@ static int omap1_spi100k_probe(struct platform_device *pdev)
434 platform_set_drvdata(pdev, master); 423 platform_set_drvdata(pdev, master);
435 424
436 spi100k = spi_master_get_devdata(master); 425 spi100k = spi_master_get_devdata(master);
437 spi100k->master = master;
438 426
439 /* 427 /*
440 * The memory region base address is taken as the platform_data. 428 * The memory region base address is taken as the platform_data.
@@ -461,8 +449,6 @@ static int omap1_spi100k_probe(struct platform_device *pdev)
461 if (status < 0) 449 if (status < 0)
462 goto err; 450 goto err;
463 451
464 spi100k->state = SPI_RUNNING;
465
466 return status; 452 return status;
467 453
468err: 454err:
diff --git a/drivers/spi/spi-omap-uwire.c b/drivers/spi/spi-omap-uwire.c
index 9313fd3b413d..be2a2e108e2f 100644
--- a/drivers/spi/spi-omap-uwire.c
+++ b/drivers/spi/spi-omap-uwire.c
@@ -99,7 +99,6 @@ struct uwire_spi {
99}; 99};
100 100
101struct uwire_state { 101struct uwire_state {
102 unsigned bits_per_word;
103 unsigned div1_idx; 102 unsigned div1_idx;
104}; 103};
105 104
@@ -210,9 +209,8 @@ static void uwire_chipselect(struct spi_device *spi, int value)
210 209
211static int uwire_txrx(struct spi_device *spi, struct spi_transfer *t) 210static int uwire_txrx(struct spi_device *spi, struct spi_transfer *t)
212{ 211{
213 struct uwire_state *ust = spi->controller_state;
214 unsigned len = t->len; 212 unsigned len = t->len;
215 unsigned bits = ust->bits_per_word; 213 unsigned bits = t->bits_per_word ? : spi->bits_per_word;
216 unsigned bytes; 214 unsigned bytes;
217 u16 val, w; 215 u16 val, w;
218 int status = 0; 216 int status = 0;
@@ -220,10 +218,6 @@ static int uwire_txrx(struct spi_device *spi, struct spi_transfer *t)
220 if (!t->tx_buf && !t->rx_buf) 218 if (!t->tx_buf && !t->rx_buf)
221 return 0; 219 return 0;
222 220
223 /* Microwire doesn't read and write concurrently */
224 if (t->tx_buf && t->rx_buf)
225 return -EPERM;
226
227 w = spi->chip_select << 10; 221 w = spi->chip_select << 10;
228 w |= CS_CMD; 222 w |= CS_CMD;
229 223
@@ -322,7 +316,6 @@ static int uwire_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
322 struct uwire_state *ust = spi->controller_state; 316 struct uwire_state *ust = spi->controller_state;
323 struct uwire_spi *uwire; 317 struct uwire_spi *uwire;
324 unsigned flags = 0; 318 unsigned flags = 0;
325 unsigned bits;
326 unsigned hz; 319 unsigned hz;
327 unsigned long rate; 320 unsigned long rate;
328 int div1_idx; 321 int div1_idx;
@@ -332,23 +325,6 @@ static int uwire_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
332 325
333 uwire = spi_master_get_devdata(spi->master); 326 uwire = spi_master_get_devdata(spi->master);
334 327
335 if (spi->chip_select > 3) {
336 pr_debug("%s: cs%d?\n", dev_name(&spi->dev), spi->chip_select);
337 status = -ENODEV;
338 goto done;
339 }
340
341 bits = spi->bits_per_word;
342 if (t != NULL && t->bits_per_word)
343 bits = t->bits_per_word;
344
345 if (bits > 16) {
346 pr_debug("%s: wordsize %d?\n", dev_name(&spi->dev), bits);
347 status = -ENODEV;
348 goto done;
349 }
350 ust->bits_per_word = bits;
351
352 /* mode 0..3, clock inverted separately; 328 /* mode 0..3, clock inverted separately;
353 * standard nCS signaling; 329 * standard nCS signaling;
354 * don't treat DI=high as "not ready" 330 * don't treat DI=high as "not ready"
@@ -502,6 +478,7 @@ static int uwire_probe(struct platform_device *pdev)
502 status = PTR_ERR(uwire->ck); 478 status = PTR_ERR(uwire->ck);
503 dev_dbg(&pdev->dev, "no functional clock?\n"); 479 dev_dbg(&pdev->dev, "no functional clock?\n");
504 spi_master_put(master); 480 spi_master_put(master);
481 iounmap(uwire_base);
505 return status; 482 return status;
506 } 483 }
507 clk_enable(uwire->ck); 484 clk_enable(uwire->ck);
@@ -515,7 +492,7 @@ static int uwire_probe(struct platform_device *pdev)
515 492
516 /* the spi->mode bits understood by this driver: */ 493 /* the spi->mode bits understood by this driver: */
517 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 494 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
518 495 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 16);
519 master->flags = SPI_MASTER_HALF_DUPLEX; 496 master->flags = SPI_MASTER_HALF_DUPLEX;
520 497
521 master->bus_num = 2; /* "official" */ 498 master->bus_num = 2; /* "official" */
@@ -539,14 +516,13 @@ static int uwire_probe(struct platform_device *pdev)
539static int uwire_remove(struct platform_device *pdev) 516static int uwire_remove(struct platform_device *pdev)
540{ 517{
541 struct uwire_spi *uwire = platform_get_drvdata(pdev); 518 struct uwire_spi *uwire = platform_get_drvdata(pdev);
542 int status;
543 519
544 // FIXME remove all child devices, somewhere ... 520 // FIXME remove all child devices, somewhere ...
545 521
546 status = spi_bitbang_stop(&uwire->bitbang); 522 spi_bitbang_stop(&uwire->bitbang);
547 uwire_off(uwire); 523 uwire_off(uwire);
548 iounmap(uwire_base); 524 iounmap(uwire_base);
549 return status; 525 return 0;
550} 526}
551 527
552/* work with hotplug and coldplug */ 528/* work with hotplug and coldplug */
diff --git a/drivers/spi/spi-omap2-mcspi.c b/drivers/spi/spi-omap2-mcspi.c
index a72127f08e39..4dc77df38864 100644
--- a/drivers/spi/spi-omap2-mcspi.c
+++ b/drivers/spi/spi-omap2-mcspi.c
@@ -22,7 +22,6 @@
22 */ 22 */
23 23
24#include <linux/kernel.h> 24#include <linux/kernel.h>
25#include <linux/init.h>
26#include <linux/interrupt.h> 25#include <linux/interrupt.h>
27#include <linux/module.h> 26#include <linux/module.h>
28#include <linux/device.h> 27#include <linux/device.h>
@@ -45,6 +44,7 @@
45#include <linux/platform_data/spi-omap2-mcspi.h> 44#include <linux/platform_data/spi-omap2-mcspi.h>
46 45
47#define OMAP2_MCSPI_MAX_FREQ 48000000 46#define OMAP2_MCSPI_MAX_FREQ 48000000
47#define OMAP2_MCSPI_MAX_DIVIDER 4096
48#define OMAP2_MCSPI_MAX_FIFODEPTH 64 48#define OMAP2_MCSPI_MAX_FIFODEPTH 64
49#define OMAP2_MCSPI_MAX_FIFOWCNT 0xFFFF 49#define OMAP2_MCSPI_MAX_FIFOWCNT 0xFFFF
50#define SPI_AUTOSUSPEND_TIMEOUT 2000 50#define SPI_AUTOSUSPEND_TIMEOUT 2000
@@ -89,6 +89,7 @@
89#define OMAP2_MCSPI_CHCONF_FORCE BIT(20) 89#define OMAP2_MCSPI_CHCONF_FORCE BIT(20)
90#define OMAP2_MCSPI_CHCONF_FFET BIT(27) 90#define OMAP2_MCSPI_CHCONF_FFET BIT(27)
91#define OMAP2_MCSPI_CHCONF_FFER BIT(28) 91#define OMAP2_MCSPI_CHCONF_FFER BIT(28)
92#define OMAP2_MCSPI_CHCONF_CLKG BIT(29)
92 93
93#define OMAP2_MCSPI_CHSTAT_RXS BIT(0) 94#define OMAP2_MCSPI_CHSTAT_RXS BIT(0)
94#define OMAP2_MCSPI_CHSTAT_TXS BIT(1) 95#define OMAP2_MCSPI_CHSTAT_TXS BIT(1)
@@ -96,6 +97,7 @@
96#define OMAP2_MCSPI_CHSTAT_TXFFE BIT(3) 97#define OMAP2_MCSPI_CHSTAT_TXFFE BIT(3)
97 98
98#define OMAP2_MCSPI_CHCTRL_EN BIT(0) 99#define OMAP2_MCSPI_CHCTRL_EN BIT(0)
100#define OMAP2_MCSPI_CHCTRL_EXTCLK_MASK (0xff << 8)
99 101
100#define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0) 102#define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0)
101 103
@@ -149,7 +151,7 @@ struct omap2_mcspi_cs {
149 int word_len; 151 int word_len;
150 struct list_head node; 152 struct list_head node;
151 /* Context save and restore shadow register */ 153 /* Context save and restore shadow register */
152 u32 chconf0; 154 u32 chconf0, chctrl0;
153}; 155};
154 156
155static inline void mcspi_write_reg(struct spi_master *master, 157static inline void mcspi_write_reg(struct spi_master *master,
@@ -230,10 +232,16 @@ static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
230 232
231static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable) 233static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
232{ 234{
235 struct omap2_mcspi_cs *cs = spi->controller_state;
233 u32 l; 236 u32 l;
234 237
235 l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0; 238 l = cs->chctrl0;
236 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l); 239 if (enable)
240 l |= OMAP2_MCSPI_CHCTRL_EN;
241 else
242 l &= ~OMAP2_MCSPI_CHCTRL_EN;
243 cs->chctrl0 = l;
244 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
237 /* Flash post-writes */ 245 /* Flash post-writes */
238 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0); 246 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
239} 247}
@@ -840,7 +848,7 @@ static int omap2_mcspi_setup_transfer(struct spi_device *spi,
840 struct omap2_mcspi_cs *cs = spi->controller_state; 848 struct omap2_mcspi_cs *cs = spi->controller_state;
841 struct omap2_mcspi *mcspi; 849 struct omap2_mcspi *mcspi;
842 struct spi_master *spi_cntrl; 850 struct spi_master *spi_cntrl;
843 u32 l = 0, div = 0; 851 u32 l = 0, clkd = 0, div, extclk = 0, clkg = 0;
844 u8 word_len = spi->bits_per_word; 852 u8 word_len = spi->bits_per_word;
845 u32 speed_hz = spi->max_speed_hz; 853 u32 speed_hz = spi->max_speed_hz;
846 854
@@ -856,7 +864,17 @@ static int omap2_mcspi_setup_transfer(struct spi_device *spi,
856 speed_hz = t->speed_hz; 864 speed_hz = t->speed_hz;
857 865
858 speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ); 866 speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ);
859 div = omap2_mcspi_calc_divisor(speed_hz); 867 if (speed_hz < (OMAP2_MCSPI_MAX_FREQ / OMAP2_MCSPI_MAX_DIVIDER)) {
868 clkd = omap2_mcspi_calc_divisor(speed_hz);
869 speed_hz = OMAP2_MCSPI_MAX_FREQ >> clkd;
870 clkg = 0;
871 } else {
872 div = (OMAP2_MCSPI_MAX_FREQ + speed_hz - 1) / speed_hz;
873 speed_hz = OMAP2_MCSPI_MAX_FREQ / div;
874 clkd = (div - 1) & 0xf;
875 extclk = (div - 1) >> 4;
876 clkg = OMAP2_MCSPI_CHCONF_CLKG;
877 }
860 878
861 l = mcspi_cached_chconf0(spi); 879 l = mcspi_cached_chconf0(spi);
862 880
@@ -885,7 +903,16 @@ static int omap2_mcspi_setup_transfer(struct spi_device *spi,
885 903
886 /* set clock divisor */ 904 /* set clock divisor */
887 l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK; 905 l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
888 l |= div << 2; 906 l |= clkd << 2;
907
908 /* set clock granularity */
909 l &= ~OMAP2_MCSPI_CHCONF_CLKG;
910 l |= clkg;
911 if (clkg) {
912 cs->chctrl0 &= ~OMAP2_MCSPI_CHCTRL_EXTCLK_MASK;
913 cs->chctrl0 |= extclk << 8;
914 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
915 }
889 916
890 /* set SPI mode 0..3 */ 917 /* set SPI mode 0..3 */
891 if (spi->mode & SPI_CPOL) 918 if (spi->mode & SPI_CPOL)
@@ -900,7 +927,7 @@ static int omap2_mcspi_setup_transfer(struct spi_device *spi,
900 mcspi_write_chconf0(spi, l); 927 mcspi_write_chconf0(spi, l);
901 928
902 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n", 929 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
903 OMAP2_MCSPI_MAX_FREQ >> div, 930 speed_hz,
904 (spi->mode & SPI_CPHA) ? "trailing" : "leading", 931 (spi->mode & SPI_CPHA) ? "trailing" : "leading",
905 (spi->mode & SPI_CPOL) ? "inverted" : "normal"); 932 (spi->mode & SPI_CPOL) ? "inverted" : "normal");
906 933
@@ -972,6 +999,7 @@ static int omap2_mcspi_setup(struct spi_device *spi)
972 cs->base = mcspi->base + spi->chip_select * 0x14; 999 cs->base = mcspi->base + spi->chip_select * 0x14;
973 cs->phys = mcspi->phys + spi->chip_select * 0x14; 1000 cs->phys = mcspi->phys + spi->chip_select * 0x14;
974 cs->chconf0 = 0; 1001 cs->chconf0 = 0;
1002 cs->chctrl0 = 0;
975 spi->controller_state = cs; 1003 spi->controller_state = cs;
976 /* Link this to context save list */ 1004 /* Link this to context save list */
977 list_add_tail(&cs->node, &ctx->cs); 1005 list_add_tail(&cs->node, &ctx->cs);
@@ -1057,12 +1085,15 @@ static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m)
1057 status = -EINVAL; 1085 status = -EINVAL;
1058 break; 1086 break;
1059 } 1087 }
1060 if (par_override || t->speed_hz || t->bits_per_word) { 1088 if (par_override ||
1089 (t->speed_hz != spi->max_speed_hz) ||
1090 (t->bits_per_word != spi->bits_per_word)) {
1061 par_override = 1; 1091 par_override = 1;
1062 status = omap2_mcspi_setup_transfer(spi, t); 1092 status = omap2_mcspi_setup_transfer(spi, t);
1063 if (status < 0) 1093 if (status < 0)
1064 break; 1094 break;
1065 if (!t->speed_hz && !t->bits_per_word) 1095 if (t->speed_hz == spi->max_speed_hz &&
1096 t->bits_per_word == spi->bits_per_word)
1066 par_override = 0; 1097 par_override = 0;
1067 } 1098 }
1068 if (cd && cd->cs_per_word) { 1099 if (cd && cd->cs_per_word) {
@@ -1176,16 +1207,12 @@ static int omap2_mcspi_transfer_one_message(struct spi_master *master,
1176 m->actual_length = 0; 1207 m->actual_length = 0;
1177 m->status = 0; 1208 m->status = 0;
1178 1209
1179 /* reject invalid messages and transfers */
1180 if (list_empty(&m->transfers))
1181 return -EINVAL;
1182 list_for_each_entry(t, &m->transfers, transfer_list) { 1210 list_for_each_entry(t, &m->transfers, transfer_list) {
1183 const void *tx_buf = t->tx_buf; 1211 const void *tx_buf = t->tx_buf;
1184 void *rx_buf = t->rx_buf; 1212 void *rx_buf = t->rx_buf;
1185 unsigned len = t->len; 1213 unsigned len = t->len;
1186 1214
1187 if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ 1215 if ((len && !(rx_buf || tx_buf))) {
1188 || (len && !(rx_buf || tx_buf))) {
1189 dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n", 1216 dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
1190 t->speed_hz, 1217 t->speed_hz,
1191 len, 1218 len,
@@ -1194,12 +1221,6 @@ static int omap2_mcspi_transfer_one_message(struct spi_master *master,
1194 t->bits_per_word); 1221 t->bits_per_word);
1195 return -EINVAL; 1222 return -EINVAL;
1196 } 1223 }
1197 if (t->speed_hz && t->speed_hz < (OMAP2_MCSPI_MAX_FREQ >> 15)) {
1198 dev_dbg(mcspi->dev, "speed_hz %d below minimum %d Hz\n",
1199 t->speed_hz,
1200 OMAP2_MCSPI_MAX_FREQ >> 15);
1201 return -EINVAL;
1202 }
1203 1224
1204 if (m->is_dma_mapped || len < DMA_MIN_BYTES) 1225 if (m->is_dma_mapped || len < DMA_MIN_BYTES)
1205 continue; 1226 continue;
@@ -1311,6 +1332,8 @@ static int omap2_mcspi_probe(struct platform_device *pdev)
1311 master->transfer_one_message = omap2_mcspi_transfer_one_message; 1332 master->transfer_one_message = omap2_mcspi_transfer_one_message;
1312 master->cleanup = omap2_mcspi_cleanup; 1333 master->cleanup = omap2_mcspi_cleanup;
1313 master->dev.of_node = node; 1334 master->dev.of_node = node;
1335 master->max_speed_hz = OMAP2_MCSPI_MAX_FREQ;
1336 master->min_speed_hz = OMAP2_MCSPI_MAX_FREQ >> 15;
1314 1337
1315 platform_set_drvdata(pdev, master); 1338 platform_set_drvdata(pdev, master);
1316 1339
@@ -1356,12 +1379,13 @@ static int omap2_mcspi_probe(struct platform_device *pdev)
1356 1379
1357 INIT_LIST_HEAD(&mcspi->ctx.cs); 1380 INIT_LIST_HEAD(&mcspi->ctx.cs);
1358 1381
1359 mcspi->dma_channels = kcalloc(master->num_chipselect, 1382 mcspi->dma_channels = devm_kcalloc(&pdev->dev, master->num_chipselect,
1360 sizeof(struct omap2_mcspi_dma), 1383 sizeof(struct omap2_mcspi_dma),
1361 GFP_KERNEL); 1384 GFP_KERNEL);
1362 1385 if (mcspi->dma_channels == NULL) {
1363 if (mcspi->dma_channels == NULL) 1386 status = -ENOMEM;
1364 goto free_master; 1387 goto free_master;
1388 }
1365 1389
1366 for (i = 0; i < master->num_chipselect; i++) { 1390 for (i = 0; i < master->num_chipselect; i++) {
1367 char *dma_rx_ch_name = mcspi->dma_channels[i].dma_rx_ch_name; 1391 char *dma_rx_ch_name = mcspi->dma_channels[i].dma_rx_ch_name;
@@ -1403,7 +1427,7 @@ static int omap2_mcspi_probe(struct platform_device *pdev)
1403 } 1427 }
1404 1428
1405 if (status < 0) 1429 if (status < 0)
1406 goto dma_chnl_free; 1430 goto free_master;
1407 1431
1408 pm_runtime_use_autosuspend(&pdev->dev); 1432 pm_runtime_use_autosuspend(&pdev->dev);
1409 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); 1433 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
@@ -1421,8 +1445,6 @@ static int omap2_mcspi_probe(struct platform_device *pdev)
1421 1445
1422disable_pm: 1446disable_pm:
1423 pm_runtime_disable(&pdev->dev); 1447 pm_runtime_disable(&pdev->dev);
1424dma_chnl_free:
1425 kfree(mcspi->dma_channels);
1426free_master: 1448free_master:
1427 spi_master_put(master); 1449 spi_master_put(master);
1428 return status; 1450 return status;
@@ -1430,19 +1452,12 @@ free_master:
1430 1452
1431static int omap2_mcspi_remove(struct platform_device *pdev) 1453static int omap2_mcspi_remove(struct platform_device *pdev)
1432{ 1454{
1433 struct spi_master *master; 1455 struct spi_master *master = platform_get_drvdata(pdev);
1434 struct omap2_mcspi *mcspi; 1456 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1435 struct omap2_mcspi_dma *dma_channels;
1436
1437 master = platform_get_drvdata(pdev);
1438 mcspi = spi_master_get_devdata(master);
1439 dma_channels = mcspi->dma_channels;
1440 1457
1441 pm_runtime_put_sync(mcspi->dev); 1458 pm_runtime_put_sync(mcspi->dev);
1442 pm_runtime_disable(&pdev->dev); 1459 pm_runtime_disable(&pdev->dev);
1443 1460
1444 kfree(dma_channels);
1445
1446 return 0; 1461 return 0;
1447} 1462}
1448 1463
diff --git a/drivers/spi/spi-orion.c b/drivers/spi/spi-orion.c
index 7f2121fe2622..d018a4aac3a1 100644
--- a/drivers/spi/spi-orion.c
+++ b/drivers/spi/spi-orion.c
@@ -9,7 +9,6 @@
9 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10 */ 10 */
11 11
12#include <linux/init.h>
13#include <linux/interrupt.h> 12#include <linux/interrupt.h>
14#include <linux/delay.h> 13#include <linux/delay.h>
15#include <linux/platform_device.h> 14#include <linux/platform_device.h>
@@ -43,8 +42,6 @@
43struct orion_spi { 42struct orion_spi {
44 struct spi_master *master; 43 struct spi_master *master;
45 void __iomem *base; 44 void __iomem *base;
46 unsigned int max_speed;
47 unsigned int min_speed;
48 struct clk *clk; 45 struct clk *clk;
49}; 46};
50 47
@@ -75,23 +72,6 @@ orion_spi_clrbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
75 writel(val, reg_addr); 72 writel(val, reg_addr);
76} 73}
77 74
78static int orion_spi_set_transfer_size(struct orion_spi *orion_spi, int size)
79{
80 if (size == 16) {
81 orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
82 ORION_SPI_IF_8_16_BIT_MODE);
83 } else if (size == 8) {
84 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
85 ORION_SPI_IF_8_16_BIT_MODE);
86 } else {
87 pr_debug("Bad bits per word value %d (only 8 or 16 are allowed).\n",
88 size);
89 return -EINVAL;
90 }
91
92 return 0;
93}
94
95static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed) 75static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
96{ 76{
97 u32 tclk_hz; 77 u32 tclk_hz;
@@ -170,7 +150,14 @@ orion_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
170 if (rc) 150 if (rc)
171 return rc; 151 return rc;
172 152
173 return orion_spi_set_transfer_size(orion_spi, bits_per_word); 153 if (bits_per_word == 16)
154 orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
155 ORION_SPI_IF_8_16_BIT_MODE);
156 else
157 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
158 ORION_SPI_IF_8_16_BIT_MODE);
159
160 return 0;
174} 161}
175 162
176static void orion_spi_set_cs(struct orion_spi *orion_spi, int enable) 163static void orion_spi_set_cs(struct orion_spi *orion_spi, int enable)
@@ -260,11 +247,9 @@ orion_spi_write_read_16bit(struct spi_device *spi,
260static unsigned int 247static unsigned int
261orion_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer) 248orion_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
262{ 249{
263 struct orion_spi *orion_spi;
264 unsigned int count; 250 unsigned int count;
265 int word_len; 251 int word_len;
266 252
267 orion_spi = spi_master_get_devdata(spi->master);
268 word_len = spi->bits_per_word; 253 word_len = spi->bits_per_word;
269 count = xfer->len; 254 count = xfer->len;
270 255
@@ -310,27 +295,6 @@ static int orion_spi_transfer_one_message(struct spi_master *master,
310 goto msg_done; 295 goto msg_done;
311 296
312 list_for_each_entry(t, &m->transfers, transfer_list) { 297 list_for_each_entry(t, &m->transfers, transfer_list) {
313 /* make sure buffer length is even when working in 16
314 * bit mode*/
315 if ((t->bits_per_word == 16) && (t->len & 1)) {
316 dev_err(&spi->dev,
317 "message rejected : "
318 "odd data length %d while in 16 bit mode\n",
319 t->len);
320 status = -EIO;
321 goto msg_done;
322 }
323
324 if (t->speed_hz && t->speed_hz < orion_spi->min_speed) {
325 dev_err(&spi->dev,
326 "message rejected : "
327 "device min speed (%d Hz) exceeds "
328 "required transfer speed (%d Hz)\n",
329 orion_spi->min_speed, t->speed_hz);
330 status = -EIO;
331 goto msg_done;
332 }
333
334 if (par_override || t->speed_hz || t->bits_per_word) { 298 if (par_override || t->speed_hz || t->bits_per_word) {
335 par_override = 1; 299 par_override = 1;
336 status = orion_spi_setup_transfer(spi, t); 300 status = orion_spi_setup_transfer(spi, t);
@@ -375,28 +339,6 @@ static int orion_spi_reset(struct orion_spi *orion_spi)
375 return 0; 339 return 0;
376} 340}
377 341
378static int orion_spi_setup(struct spi_device *spi)
379{
380 struct orion_spi *orion_spi;
381
382 orion_spi = spi_master_get_devdata(spi->master);
383
384 if ((spi->max_speed_hz == 0)
385 || (spi->max_speed_hz > orion_spi->max_speed))
386 spi->max_speed_hz = orion_spi->max_speed;
387
388 if (spi->max_speed_hz < orion_spi->min_speed) {
389 dev_err(&spi->dev, "setup: requested speed too low %d Hz\n",
390 spi->max_speed_hz);
391 return -EINVAL;
392 }
393
394 /*
395 * baudrate & width will be set orion_spi_setup_transfer
396 */
397 return 0;
398}
399
400static int orion_spi_probe(struct platform_device *pdev) 342static int orion_spi_probe(struct platform_device *pdev)
401{ 343{
402 struct spi_master *master; 344 struct spi_master *master;
@@ -425,9 +367,9 @@ static int orion_spi_probe(struct platform_device *pdev)
425 /* we support only mode 0, and no options */ 367 /* we support only mode 0, and no options */
426 master->mode_bits = SPI_CPHA | SPI_CPOL; 368 master->mode_bits = SPI_CPHA | SPI_CPOL;
427 369
428 master->setup = orion_spi_setup;
429 master->transfer_one_message = orion_spi_transfer_one_message; 370 master->transfer_one_message = orion_spi_transfer_one_message;
430 master->num_chipselect = ORION_NUM_CHIPSELECTS; 371 master->num_chipselect = ORION_NUM_CHIPSELECTS;
372 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
431 373
432 platform_set_drvdata(pdev, master); 374 platform_set_drvdata(pdev, master);
433 375
@@ -443,8 +385,8 @@ static int orion_spi_probe(struct platform_device *pdev)
443 clk_prepare(spi->clk); 385 clk_prepare(spi->clk);
444 clk_enable(spi->clk); 386 clk_enable(spi->clk);
445 tclk_hz = clk_get_rate(spi->clk); 387 tclk_hz = clk_get_rate(spi->clk);
446 spi->max_speed = DIV_ROUND_UP(tclk_hz, 4); 388 master->max_speed_hz = DIV_ROUND_UP(tclk_hz, 4);
447 spi->min_speed = DIV_ROUND_UP(tclk_hz, 30); 389 master->min_speed_hz = DIV_ROUND_UP(tclk_hz, 30);
448 390
449 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 391 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
450 spi->base = devm_ioremap_resource(&pdev->dev, r); 392 spi->base = devm_ioremap_resource(&pdev->dev, r);
diff --git a/drivers/spi/spi-pl022.c b/drivers/spi/spi-pl022.c
index 2789b452e711..51d99779682f 100644
--- a/drivers/spi/spi-pl022.c
+++ b/drivers/spi/spi-pl022.c
@@ -459,9 +459,8 @@ static void giveback(struct pl022 *pl022)
459 struct spi_transfer *last_transfer; 459 struct spi_transfer *last_transfer;
460 pl022->next_msg_cs_active = false; 460 pl022->next_msg_cs_active = false;
461 461
462 last_transfer = list_entry(pl022->cur_msg->transfers.prev, 462 last_transfer = list_last_entry(&pl022->cur_msg->transfers,
463 struct spi_transfer, 463 struct spi_transfer, transfer_list);
464 transfer_list);
465 464
466 /* Delay if requested before any change in chip select */ 465 /* Delay if requested before any change in chip select */
467 if (last_transfer->delay_usecs) 466 if (last_transfer->delay_usecs)
@@ -2109,8 +2108,6 @@ static int pl022_probe(struct amba_device *adev, const struct amba_id *id)
2109 pl022->chipselects = devm_kzalloc(dev, num_cs * sizeof(int), 2108 pl022->chipselects = devm_kzalloc(dev, num_cs * sizeof(int),
2110 GFP_KERNEL); 2109 GFP_KERNEL);
2111 2110
2112 pinctrl_pm_select_default_state(dev);
2113
2114 /* 2111 /*
2115 * Bus Number Which has been Assigned to this SSP controller 2112 * Bus Number Which has been Assigned to this SSP controller
2116 * on this board 2113 * on this board
@@ -2183,13 +2180,7 @@ static int pl022_probe(struct amba_device *adev, const struct amba_id *id)
2183 goto err_no_clk; 2180 goto err_no_clk;
2184 } 2181 }
2185 2182
2186 status = clk_prepare(pl022->clk); 2183 status = clk_prepare_enable(pl022->clk);
2187 if (status) {
2188 dev_err(&adev->dev, "could not prepare SSP/SPI bus clock\n");
2189 goto err_clk_prep;
2190 }
2191
2192 status = clk_enable(pl022->clk);
2193 if (status) { 2184 if (status) {
2194 dev_err(&adev->dev, "could not enable SSP/SPI bus clock\n"); 2185 dev_err(&adev->dev, "could not enable SSP/SPI bus clock\n");
2195 goto err_no_clk_en; 2186 goto err_no_clk_en;
@@ -2250,10 +2241,8 @@ static int pl022_probe(struct amba_device *adev, const struct amba_id *id)
2250 if (platform_info->enable_dma) 2241 if (platform_info->enable_dma)
2251 pl022_dma_remove(pl022); 2242 pl022_dma_remove(pl022);
2252 err_no_irq: 2243 err_no_irq:
2253 clk_disable(pl022->clk); 2244 clk_disable_unprepare(pl022->clk);
2254 err_no_clk_en: 2245 err_no_clk_en:
2255 clk_unprepare(pl022->clk);
2256 err_clk_prep:
2257 err_no_clk: 2246 err_no_clk:
2258 err_no_ioremap: 2247 err_no_ioremap:
2259 amba_release_regions(adev); 2248 amba_release_regions(adev);
@@ -2281,42 +2270,13 @@ pl022_remove(struct amba_device *adev)
2281 if (pl022->master_info->enable_dma) 2270 if (pl022->master_info->enable_dma)
2282 pl022_dma_remove(pl022); 2271 pl022_dma_remove(pl022);
2283 2272
2284 clk_disable(pl022->clk); 2273 clk_disable_unprepare(pl022->clk);
2285 clk_unprepare(pl022->clk);
2286 amba_release_regions(adev); 2274 amba_release_regions(adev);
2287 tasklet_disable(&pl022->pump_transfers); 2275 tasklet_disable(&pl022->pump_transfers);
2288 return 0; 2276 return 0;
2289} 2277}
2290 2278
2291#if defined(CONFIG_SUSPEND) || defined(CONFIG_PM_RUNTIME) 2279#ifdef CONFIG_PM_SLEEP
2292/*
2293 * These two functions are used from both suspend/resume and
2294 * the runtime counterparts to handle external resources like
2295 * clocks, pins and regulators when going to sleep.
2296 */
2297static void pl022_suspend_resources(struct pl022 *pl022, bool runtime)
2298{
2299 clk_disable(pl022->clk);
2300
2301 if (runtime)
2302 pinctrl_pm_select_idle_state(&pl022->adev->dev);
2303 else
2304 pinctrl_pm_select_sleep_state(&pl022->adev->dev);
2305}
2306
2307static void pl022_resume_resources(struct pl022 *pl022, bool runtime)
2308{
2309 /* First go to the default state */
2310 pinctrl_pm_select_default_state(&pl022->adev->dev);
2311 if (!runtime)
2312 /* Then let's idle the pins until the next transfer happens */
2313 pinctrl_pm_select_idle_state(&pl022->adev->dev);
2314
2315 clk_enable(pl022->clk);
2316}
2317#endif
2318
2319#ifdef CONFIG_SUSPEND
2320static int pl022_suspend(struct device *dev) 2280static int pl022_suspend(struct device *dev)
2321{ 2281{
2322 struct pl022 *pl022 = dev_get_drvdata(dev); 2282 struct pl022 *pl022 = dev_get_drvdata(dev);
@@ -2328,8 +2288,13 @@ static int pl022_suspend(struct device *dev)
2328 return ret; 2288 return ret;
2329 } 2289 }
2330 2290
2331 pm_runtime_get_sync(dev); 2291 ret = pm_runtime_force_suspend(dev);
2332 pl022_suspend_resources(pl022, false); 2292 if (ret) {
2293 spi_master_resume(pl022->master);
2294 return ret;
2295 }
2296
2297 pinctrl_pm_select_sleep_state(dev);
2333 2298
2334 dev_dbg(dev, "suspended\n"); 2299 dev_dbg(dev, "suspended\n");
2335 return 0; 2300 return 0;
@@ -2340,8 +2305,9 @@ static int pl022_resume(struct device *dev)
2340 struct pl022 *pl022 = dev_get_drvdata(dev); 2305 struct pl022 *pl022 = dev_get_drvdata(dev);
2341 int ret; 2306 int ret;
2342 2307
2343 pl022_resume_resources(pl022, false); 2308 ret = pm_runtime_force_resume(dev);
2344 pm_runtime_put(dev); 2309 if (ret)
2310 dev_err(dev, "problem resuming\n");
2345 2311
2346 /* Start the queue running */ 2312 /* Start the queue running */
2347 ret = spi_master_resume(pl022->master); 2313 ret = spi_master_resume(pl022->master);
@@ -2352,14 +2318,16 @@ static int pl022_resume(struct device *dev)
2352 2318
2353 return ret; 2319 return ret;
2354} 2320}
2355#endif /* CONFIG_PM */ 2321#endif
2356 2322
2357#ifdef CONFIG_PM_RUNTIME 2323#ifdef CONFIG_PM
2358static int pl022_runtime_suspend(struct device *dev) 2324static int pl022_runtime_suspend(struct device *dev)
2359{ 2325{
2360 struct pl022 *pl022 = dev_get_drvdata(dev); 2326 struct pl022 *pl022 = dev_get_drvdata(dev);
2361 2327
2362 pl022_suspend_resources(pl022, true); 2328 clk_disable_unprepare(pl022->clk);
2329 pinctrl_pm_select_idle_state(dev);
2330
2363 return 0; 2331 return 0;
2364} 2332}
2365 2333
@@ -2367,14 +2335,16 @@ static int pl022_runtime_resume(struct device *dev)
2367{ 2335{
2368 struct pl022 *pl022 = dev_get_drvdata(dev); 2336 struct pl022 *pl022 = dev_get_drvdata(dev);
2369 2337
2370 pl022_resume_resources(pl022, true); 2338 pinctrl_pm_select_default_state(dev);
2339 clk_prepare_enable(pl022->clk);
2340
2371 return 0; 2341 return 0;
2372} 2342}
2373#endif 2343#endif
2374 2344
2375static const struct dev_pm_ops pl022_dev_pm_ops = { 2345static const struct dev_pm_ops pl022_dev_pm_ops = {
2376 SET_SYSTEM_SLEEP_PM_OPS(pl022_suspend, pl022_resume) 2346 SET_SYSTEM_SLEEP_PM_OPS(pl022_suspend, pl022_resume)
2377 SET_RUNTIME_PM_OPS(pl022_runtime_suspend, pl022_runtime_resume, NULL) 2347 SET_PM_RUNTIME_PM_OPS(pl022_runtime_suspend, pl022_runtime_resume, NULL)
2378}; 2348};
2379 2349
2380static struct vendor_data vendor_arm = { 2350static struct vendor_data vendor_arm = {
diff --git a/drivers/spi/spi-ppc4xx.c b/drivers/spi/spi-ppc4xx.c
index 5ee56726f8d0..80b8408ac3e3 100644
--- a/drivers/spi/spi-ppc4xx.c
+++ b/drivers/spi/spi-ppc4xx.c
@@ -24,7 +24,6 @@
24 */ 24 */
25 25
26#include <linux/module.h> 26#include <linux/module.h>
27#include <linux/init.h>
28#include <linux/sched.h> 27#include <linux/sched.h>
29#include <linux/slab.h> 28#include <linux/slab.h>
30#include <linux/errno.h> 29#include <linux/errno.h>
diff --git a/drivers/spi/spi-pxa2xx-dma.c b/drivers/spi/spi-pxa2xx-dma.c
index 3c0b55125f1e..713af4806f26 100644
--- a/drivers/spi/spi-pxa2xx-dma.c
+++ b/drivers/spi/spi-pxa2xx-dma.c
@@ -9,7 +9,6 @@
9 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10 */ 10 */
11 11
12#include <linux/init.h>
13#include <linux/device.h> 12#include <linux/device.h>
14#include <linux/dma-mapping.h> 13#include <linux/dma-mapping.h>
15#include <linux/dmaengine.h> 14#include <linux/dmaengine.h>
diff --git a/drivers/spi/spi-pxa2xx-pxadma.c b/drivers/spi/spi-pxa2xx-pxadma.c
index 2916efc7cfe5..e8a26f25d5c0 100644
--- a/drivers/spi/spi-pxa2xx-pxadma.c
+++ b/drivers/spi/spi-pxa2xx-pxadma.c
@@ -18,7 +18,6 @@
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */ 19 */
20 20
21#include <linux/init.h>
22#include <linux/delay.h> 21#include <linux/delay.h>
23#include <linux/device.h> 22#include <linux/device.h>
24#include <linux/dma-mapping.h> 23#include <linux/dma-mapping.h>
diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c
index c702fc536a77..41185d0557fa 100644
--- a/drivers/spi/spi-pxa2xx.c
+++ b/drivers/spi/spi-pxa2xx.c
@@ -362,8 +362,7 @@ static void giveback(struct driver_data *drv_data)
362 drv_data->cur_msg = NULL; 362 drv_data->cur_msg = NULL;
363 drv_data->cur_transfer = NULL; 363 drv_data->cur_transfer = NULL;
364 364
365 last_transfer = list_entry(msg->transfers.prev, 365 last_transfer = list_last_entry(&msg->transfers, struct spi_transfer,
366 struct spi_transfer,
367 transfer_list); 366 transfer_list);
368 367
369 /* Delay if requested before any change in chip select */ 368 /* Delay if requested before any change in chip select */
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
new file mode 100644
index 000000000000..b032e8885e24
--- /dev/null
+++ b/drivers/spi/spi-qup.c
@@ -0,0 +1,779 @@
1/*
2 * Copyright (c) 2008-2014, The Linux foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License rev 2 and
6 * only rev 2 as published by the free Software foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or fITNESS fOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/clk.h>
15#include <linux/delay.h>
16#include <linux/err.h>
17#include <linux/interrupt.h>
18#include <linux/io.h>
19#include <linux/list.h>
20#include <linux/module.h>
21#include <linux/of.h>
22#include <linux/platform_device.h>
23#include <linux/pm_runtime.h>
24#include <linux/spi/spi.h>
25
26#define QUP_CONFIG 0x0000
27#define QUP_STATE 0x0004
28#define QUP_IO_M_MODES 0x0008
29#define QUP_SW_RESET 0x000c
30#define QUP_OPERATIONAL 0x0018
31#define QUP_ERROR_FLAGS 0x001c
32#define QUP_ERROR_FLAGS_EN 0x0020
33#define QUP_OPERATIONAL_MASK 0x0028
34#define QUP_HW_VERSION 0x0030
35#define QUP_MX_OUTPUT_CNT 0x0100
36#define QUP_OUTPUT_FIFO 0x0110
37#define QUP_MX_WRITE_CNT 0x0150
38#define QUP_MX_INPUT_CNT 0x0200
39#define QUP_MX_READ_CNT 0x0208
40#define QUP_INPUT_FIFO 0x0218
41
42#define SPI_CONFIG 0x0300
43#define SPI_IO_CONTROL 0x0304
44#define SPI_ERROR_FLAGS 0x0308
45#define SPI_ERROR_FLAGS_EN 0x030c
46
47/* QUP_CONFIG fields */
48#define QUP_CONFIG_SPI_MODE (1 << 8)
49#define QUP_CONFIG_CLOCK_AUTO_GATE BIT(13)
50#define QUP_CONFIG_NO_INPUT BIT(7)
51#define QUP_CONFIG_NO_OUTPUT BIT(6)
52#define QUP_CONFIG_N 0x001f
53
54/* QUP_STATE fields */
55#define QUP_STATE_VALID BIT(2)
56#define QUP_STATE_RESET 0
57#define QUP_STATE_RUN 1
58#define QUP_STATE_PAUSE 3
59#define QUP_STATE_MASK 3
60#define QUP_STATE_CLEAR 2
61
62#define QUP_HW_VERSION_2_1_1 0x20010001
63
64/* QUP_IO_M_MODES fields */
65#define QUP_IO_M_PACK_EN BIT(15)
66#define QUP_IO_M_UNPACK_EN BIT(14)
67#define QUP_IO_M_INPUT_MODE_MASK_SHIFT 12
68#define QUP_IO_M_OUTPUT_MODE_MASK_SHIFT 10
69#define QUP_IO_M_INPUT_MODE_MASK (3 << QUP_IO_M_INPUT_MODE_MASK_SHIFT)
70#define QUP_IO_M_OUTPUT_MODE_MASK (3 << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT)
71
72#define QUP_IO_M_OUTPUT_BLOCK_SIZE(x) (((x) & (0x03 << 0)) >> 0)
73#define QUP_IO_M_OUTPUT_FIFO_SIZE(x) (((x) & (0x07 << 2)) >> 2)
74#define QUP_IO_M_INPUT_BLOCK_SIZE(x) (((x) & (0x03 << 5)) >> 5)
75#define QUP_IO_M_INPUT_FIFO_SIZE(x) (((x) & (0x07 << 7)) >> 7)
76
77#define QUP_IO_M_MODE_FIFO 0
78#define QUP_IO_M_MODE_BLOCK 1
79#define QUP_IO_M_MODE_DMOV 2
80#define QUP_IO_M_MODE_BAM 3
81
82/* QUP_OPERATIONAL fields */
83#define QUP_OP_MAX_INPUT_DONE_FLAG BIT(11)
84#define QUP_OP_MAX_OUTPUT_DONE_FLAG BIT(10)
85#define QUP_OP_IN_SERVICE_FLAG BIT(9)
86#define QUP_OP_OUT_SERVICE_FLAG BIT(8)
87#define QUP_OP_IN_FIFO_FULL BIT(7)
88#define QUP_OP_OUT_FIFO_FULL BIT(6)
89#define QUP_OP_IN_FIFO_NOT_EMPTY BIT(5)
90#define QUP_OP_OUT_FIFO_NOT_EMPTY BIT(4)
91
92/* QUP_ERROR_FLAGS and QUP_ERROR_FLAGS_EN fields */
93#define QUP_ERROR_OUTPUT_OVER_RUN BIT(5)
94#define QUP_ERROR_INPUT_UNDER_RUN BIT(4)
95#define QUP_ERROR_OUTPUT_UNDER_RUN BIT(3)
96#define QUP_ERROR_INPUT_OVER_RUN BIT(2)
97
98/* SPI_CONFIG fields */
99#define SPI_CONFIG_HS_MODE BIT(10)
100#define SPI_CONFIG_INPUT_FIRST BIT(9)
101#define SPI_CONFIG_LOOPBACK BIT(8)
102
103/* SPI_IO_CONTROL fields */
104#define SPI_IO_C_FORCE_CS BIT(11)
105#define SPI_IO_C_CLK_IDLE_HIGH BIT(10)
106#define SPI_IO_C_MX_CS_MODE BIT(8)
107#define SPI_IO_C_CS_N_POLARITY_0 BIT(4)
108#define SPI_IO_C_CS_SELECT(x) (((x) & 3) << 2)
109#define SPI_IO_C_CS_SELECT_MASK 0x000c
110#define SPI_IO_C_TRISTATE_CS BIT(1)
111#define SPI_IO_C_NO_TRI_STATE BIT(0)
112
113/* SPI_ERROR_FLAGS and SPI_ERROR_FLAGS_EN fields */
114#define SPI_ERROR_CLK_OVER_RUN BIT(1)
115#define SPI_ERROR_CLK_UNDER_RUN BIT(0)
116
117#define SPI_NUM_CHIPSELECTS 4
118
119/* high speed mode is when bus rate is greater then 26MHz */
120#define SPI_HS_MIN_RATE 26000000
121#define SPI_MAX_RATE 50000000
122
123#define SPI_DELAY_THRESHOLD 1
124#define SPI_DELAY_RETRY 10
125
126struct spi_qup {
127 void __iomem *base;
128 struct device *dev;
129 struct clk *cclk; /* core clock */
130 struct clk *iclk; /* interface clock */
131 int irq;
132 spinlock_t lock;
133
134 int in_fifo_sz;
135 int out_fifo_sz;
136 int in_blk_sz;
137 int out_blk_sz;
138
139 struct spi_transfer *xfer;
140 struct completion done;
141 int error;
142 int w_size; /* bytes per SPI word */
143 int tx_bytes;
144 int rx_bytes;
145};
146
147
148static inline bool spi_qup_is_valid_state(struct spi_qup *controller)
149{
150 u32 opstate = readl_relaxed(controller->base + QUP_STATE);
151
152 return opstate & QUP_STATE_VALID;
153}
154
155static int spi_qup_set_state(struct spi_qup *controller, u32 state)
156{
157 unsigned long loop;
158 u32 cur_state;
159
160 loop = 0;
161 while (!spi_qup_is_valid_state(controller)) {
162
163 usleep_range(SPI_DELAY_THRESHOLD, SPI_DELAY_THRESHOLD * 2);
164
165 if (++loop > SPI_DELAY_RETRY)
166 return -EIO;
167 }
168
169 if (loop)
170 dev_dbg(controller->dev, "invalid state for %ld,us %d\n",
171 loop, state);
172
173 cur_state = readl_relaxed(controller->base + QUP_STATE);
174 /*
175 * Per spec: for PAUSE_STATE to RESET_STATE, two writes
176 * of (b10) are required
177 */
178 if (((cur_state & QUP_STATE_MASK) == QUP_STATE_PAUSE) &&
179 (state == QUP_STATE_RESET)) {
180 writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE);
181 writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE);
182 } else {
183 cur_state &= ~QUP_STATE_MASK;
184 cur_state |= state;
185 writel_relaxed(cur_state, controller->base + QUP_STATE);
186 }
187
188 loop = 0;
189 while (!spi_qup_is_valid_state(controller)) {
190
191 usleep_range(SPI_DELAY_THRESHOLD, SPI_DELAY_THRESHOLD * 2);
192
193 if (++loop > SPI_DELAY_RETRY)
194 return -EIO;
195 }
196
197 return 0;
198}
199
200
201static void spi_qup_fifo_read(struct spi_qup *controller,
202 struct spi_transfer *xfer)
203{
204 u8 *rx_buf = xfer->rx_buf;
205 u32 word, state;
206 int idx, shift, w_size;
207
208 w_size = controller->w_size;
209
210 while (controller->rx_bytes < xfer->len) {
211
212 state = readl_relaxed(controller->base + QUP_OPERATIONAL);
213 if (0 == (state & QUP_OP_IN_FIFO_NOT_EMPTY))
214 break;
215
216 word = readl_relaxed(controller->base + QUP_INPUT_FIFO);
217
218 if (!rx_buf) {
219 controller->rx_bytes += w_size;
220 continue;
221 }
222
223 for (idx = 0; idx < w_size; idx++, controller->rx_bytes++) {
224 /*
225 * The data format depends on bytes per SPI word:
226 * 4 bytes: 0x12345678
227 * 2 bytes: 0x00001234
228 * 1 byte : 0x00000012
229 */
230 shift = BITS_PER_BYTE;
231 shift *= (w_size - idx - 1);
232 rx_buf[controller->rx_bytes] = word >> shift;
233 }
234 }
235}
236
237static void spi_qup_fifo_write(struct spi_qup *controller,
238 struct spi_transfer *xfer)
239{
240 const u8 *tx_buf = xfer->tx_buf;
241 u32 word, state, data;
242 int idx, w_size;
243
244 w_size = controller->w_size;
245
246 while (controller->tx_bytes < xfer->len) {
247
248 state = readl_relaxed(controller->base + QUP_OPERATIONAL);
249 if (state & QUP_OP_OUT_FIFO_FULL)
250 break;
251
252 word = 0;
253 for (idx = 0; idx < w_size; idx++, controller->tx_bytes++) {
254
255 if (!tx_buf) {
256 controller->tx_bytes += w_size;
257 break;
258 }
259
260 data = tx_buf[controller->tx_bytes];
261 word |= data << (BITS_PER_BYTE * (3 - idx));
262 }
263
264 writel_relaxed(word, controller->base + QUP_OUTPUT_FIFO);
265 }
266}
267
268static irqreturn_t spi_qup_qup_irq(int irq, void *dev_id)
269{
270 struct spi_qup *controller = dev_id;
271 struct spi_transfer *xfer;
272 u32 opflags, qup_err, spi_err;
273 unsigned long flags;
274 int error = 0;
275
276 spin_lock_irqsave(&controller->lock, flags);
277 xfer = controller->xfer;
278 controller->xfer = NULL;
279 spin_unlock_irqrestore(&controller->lock, flags);
280
281 qup_err = readl_relaxed(controller->base + QUP_ERROR_FLAGS);
282 spi_err = readl_relaxed(controller->base + SPI_ERROR_FLAGS);
283 opflags = readl_relaxed(controller->base + QUP_OPERATIONAL);
284
285 writel_relaxed(qup_err, controller->base + QUP_ERROR_FLAGS);
286 writel_relaxed(spi_err, controller->base + SPI_ERROR_FLAGS);
287 writel_relaxed(opflags, controller->base + QUP_OPERATIONAL);
288
289 if (!xfer) {
290 dev_err_ratelimited(controller->dev, "unexpected irq %x08 %x08 %x08\n",
291 qup_err, spi_err, opflags);
292 return IRQ_HANDLED;
293 }
294
295 if (qup_err) {
296 if (qup_err & QUP_ERROR_OUTPUT_OVER_RUN)
297 dev_warn(controller->dev, "OUTPUT_OVER_RUN\n");
298 if (qup_err & QUP_ERROR_INPUT_UNDER_RUN)
299 dev_warn(controller->dev, "INPUT_UNDER_RUN\n");
300 if (qup_err & QUP_ERROR_OUTPUT_UNDER_RUN)
301 dev_warn(controller->dev, "OUTPUT_UNDER_RUN\n");
302 if (qup_err & QUP_ERROR_INPUT_OVER_RUN)
303 dev_warn(controller->dev, "INPUT_OVER_RUN\n");
304
305 error = -EIO;
306 }
307
308 if (spi_err) {
309 if (spi_err & SPI_ERROR_CLK_OVER_RUN)
310 dev_warn(controller->dev, "CLK_OVER_RUN\n");
311 if (spi_err & SPI_ERROR_CLK_UNDER_RUN)
312 dev_warn(controller->dev, "CLK_UNDER_RUN\n");
313
314 error = -EIO;
315 }
316
317 if (opflags & QUP_OP_IN_SERVICE_FLAG)
318 spi_qup_fifo_read(controller, xfer);
319
320 if (opflags & QUP_OP_OUT_SERVICE_FLAG)
321 spi_qup_fifo_write(controller, xfer);
322
323 spin_lock_irqsave(&controller->lock, flags);
324 controller->error = error;
325 controller->xfer = xfer;
326 spin_unlock_irqrestore(&controller->lock, flags);
327
328 if (controller->rx_bytes == xfer->len || error)
329 complete(&controller->done);
330
331 return IRQ_HANDLED;
332}
333
334
335/* set clock freq ... bits per word */
336static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
337{
338 struct spi_qup *controller = spi_master_get_devdata(spi->master);
339 u32 config, iomode, mode;
340 int ret, n_words, w_size;
341
342 if (spi->mode & SPI_LOOP && xfer->len > controller->in_fifo_sz) {
343 dev_err(controller->dev, "too big size for loopback %d > %d\n",
344 xfer->len, controller->in_fifo_sz);
345 return -EIO;
346 }
347
348 ret = clk_set_rate(controller->cclk, xfer->speed_hz);
349 if (ret) {
350 dev_err(controller->dev, "fail to set frequency %d",
351 xfer->speed_hz);
352 return -EIO;
353 }
354
355 if (spi_qup_set_state(controller, QUP_STATE_RESET)) {
356 dev_err(controller->dev, "cannot set RESET state\n");
357 return -EIO;
358 }
359
360 w_size = 4;
361 if (xfer->bits_per_word <= 8)
362 w_size = 1;
363 else if (xfer->bits_per_word <= 16)
364 w_size = 2;
365
366 n_words = xfer->len / w_size;
367 controller->w_size = w_size;
368
369 if (n_words <= controller->in_fifo_sz) {
370 mode = QUP_IO_M_MODE_FIFO;
371 writel_relaxed(n_words, controller->base + QUP_MX_READ_CNT);
372 writel_relaxed(n_words, controller->base + QUP_MX_WRITE_CNT);
373 /* must be zero for FIFO */
374 writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT);
375 writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
376 } else {
377 mode = QUP_IO_M_MODE_BLOCK;
378 writel_relaxed(n_words, controller->base + QUP_MX_INPUT_CNT);
379 writel_relaxed(n_words, controller->base + QUP_MX_OUTPUT_CNT);
380 /* must be zero for BLOCK and BAM */
381 writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
382 writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
383 }
384
385 iomode = readl_relaxed(controller->base + QUP_IO_M_MODES);
386 /* Set input and output transfer mode */
387 iomode &= ~(QUP_IO_M_INPUT_MODE_MASK | QUP_IO_M_OUTPUT_MODE_MASK);
388 iomode &= ~(QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN);
389 iomode |= (mode << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT);
390 iomode |= (mode << QUP_IO_M_INPUT_MODE_MASK_SHIFT);
391
392 writel_relaxed(iomode, controller->base + QUP_IO_M_MODES);
393
394 config = readl_relaxed(controller->base + SPI_CONFIG);
395
396 if (spi->mode & SPI_LOOP)
397 config |= SPI_CONFIG_LOOPBACK;
398 else
399 config &= ~SPI_CONFIG_LOOPBACK;
400
401 if (spi->mode & SPI_CPHA)
402 config &= ~SPI_CONFIG_INPUT_FIRST;
403 else
404 config |= SPI_CONFIG_INPUT_FIRST;
405
406 /*
407 * HS_MODE improves signal stability for spi-clk high rates,
408 * but is invalid in loop back mode.
409 */
410 if ((xfer->speed_hz >= SPI_HS_MIN_RATE) && !(spi->mode & SPI_LOOP))
411 config |= SPI_CONFIG_HS_MODE;
412 else
413 config &= ~SPI_CONFIG_HS_MODE;
414
415 writel_relaxed(config, controller->base + SPI_CONFIG);
416
417 config = readl_relaxed(controller->base + QUP_CONFIG);
418 config &= ~(QUP_CONFIG_NO_INPUT | QUP_CONFIG_NO_OUTPUT | QUP_CONFIG_N);
419 config |= xfer->bits_per_word - 1;
420 config |= QUP_CONFIG_SPI_MODE;
421 writel_relaxed(config, controller->base + QUP_CONFIG);
422
423 writel_relaxed(0, controller->base + QUP_OPERATIONAL_MASK);
424 return 0;
425}
426
427static void spi_qup_set_cs(struct spi_device *spi, bool enable)
428{
429 struct spi_qup *controller = spi_master_get_devdata(spi->master);
430
431 u32 iocontol, mask;
432
433 iocontol = readl_relaxed(controller->base + SPI_IO_CONTROL);
434
435 /* Disable auto CS toggle and use manual */
436 iocontol &= ~SPI_IO_C_MX_CS_MODE;
437 iocontol |= SPI_IO_C_FORCE_CS;
438
439 iocontol &= ~SPI_IO_C_CS_SELECT_MASK;
440 iocontol |= SPI_IO_C_CS_SELECT(spi->chip_select);
441
442 mask = SPI_IO_C_CS_N_POLARITY_0 << spi->chip_select;
443
444 if (enable)
445 iocontol |= mask;
446 else
447 iocontol &= ~mask;
448
449 writel_relaxed(iocontol, controller->base + SPI_IO_CONTROL);
450}
451
452static int spi_qup_transfer_one(struct spi_master *master,
453 struct spi_device *spi,
454 struct spi_transfer *xfer)
455{
456 struct spi_qup *controller = spi_master_get_devdata(master);
457 unsigned long timeout, flags;
458 int ret = -EIO;
459
460 ret = spi_qup_io_config(spi, xfer);
461 if (ret)
462 return ret;
463
464 timeout = DIV_ROUND_UP(xfer->speed_hz, MSEC_PER_SEC);
465 timeout = DIV_ROUND_UP(xfer->len * 8, timeout);
466 timeout = 100 * msecs_to_jiffies(timeout);
467
468 reinit_completion(&controller->done);
469
470 spin_lock_irqsave(&controller->lock, flags);
471 controller->xfer = xfer;
472 controller->error = 0;
473 controller->rx_bytes = 0;
474 controller->tx_bytes = 0;
475 spin_unlock_irqrestore(&controller->lock, flags);
476
477 if (spi_qup_set_state(controller, QUP_STATE_RUN)) {
478 dev_warn(controller->dev, "cannot set RUN state\n");
479 goto exit;
480 }
481
482 if (spi_qup_set_state(controller, QUP_STATE_PAUSE)) {
483 dev_warn(controller->dev, "cannot set PAUSE state\n");
484 goto exit;
485 }
486
487 spi_qup_fifo_write(controller, xfer);
488
489 if (spi_qup_set_state(controller, QUP_STATE_RUN)) {
490 dev_warn(controller->dev, "cannot set EXECUTE state\n");
491 goto exit;
492 }
493
494 if (!wait_for_completion_timeout(&controller->done, timeout))
495 ret = -ETIMEDOUT;
496exit:
497 spi_qup_set_state(controller, QUP_STATE_RESET);
498 spin_lock_irqsave(&controller->lock, flags);
499 controller->xfer = NULL;
500 if (!ret)
501 ret = controller->error;
502 spin_unlock_irqrestore(&controller->lock, flags);
503 return ret;
504}
505
506static int spi_qup_probe(struct platform_device *pdev)
507{
508 struct spi_master *master;
509 struct clk *iclk, *cclk;
510 struct spi_qup *controller;
511 struct resource *res;
512 struct device *dev;
513 void __iomem *base;
514 u32 data, max_freq, iomode;
515 int ret, irq, size;
516
517 dev = &pdev->dev;
518 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
519 base = devm_ioremap_resource(dev, res);
520 if (IS_ERR(base))
521 return PTR_ERR(base);
522
523 irq = platform_get_irq(pdev, 0);
524 if (irq < 0)
525 return irq;
526
527 cclk = devm_clk_get(dev, "core");
528 if (IS_ERR(cclk))
529 return PTR_ERR(cclk);
530
531 iclk = devm_clk_get(dev, "iface");
532 if (IS_ERR(iclk))
533 return PTR_ERR(iclk);
534
535 /* This is optional parameter */
536 if (of_property_read_u32(dev->of_node, "spi-max-frequency", &max_freq))
537 max_freq = SPI_MAX_RATE;
538
539 if (!max_freq || max_freq > SPI_MAX_RATE) {
540 dev_err(dev, "invalid clock frequency %d\n", max_freq);
541 return -ENXIO;
542 }
543
544 ret = clk_prepare_enable(cclk);
545 if (ret) {
546 dev_err(dev, "cannot enable core clock\n");
547 return ret;
548 }
549
550 ret = clk_prepare_enable(iclk);
551 if (ret) {
552 clk_disable_unprepare(cclk);
553 dev_err(dev, "cannot enable iface clock\n");
554 return ret;
555 }
556
557 data = readl_relaxed(base + QUP_HW_VERSION);
558
559 if (data < QUP_HW_VERSION_2_1_1) {
560 clk_disable_unprepare(cclk);
561 clk_disable_unprepare(iclk);
562 dev_err(dev, "v.%08x is not supported\n", data);
563 return -ENXIO;
564 }
565
566 master = spi_alloc_master(dev, sizeof(struct spi_qup));
567 if (!master) {
568 clk_disable_unprepare(cclk);
569 clk_disable_unprepare(iclk);
570 dev_err(dev, "cannot allocate master\n");
571 return -ENOMEM;
572 }
573
574 master->bus_num = pdev->id;
575 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
576 master->num_chipselect = SPI_NUM_CHIPSELECTS;
577 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
578 master->max_speed_hz = max_freq;
579 master->set_cs = spi_qup_set_cs;
580 master->transfer_one = spi_qup_transfer_one;
581 master->dev.of_node = pdev->dev.of_node;
582 master->auto_runtime_pm = true;
583
584 platform_set_drvdata(pdev, master);
585
586 controller = spi_master_get_devdata(master);
587
588 controller->dev = dev;
589 controller->base = base;
590 controller->iclk = iclk;
591 controller->cclk = cclk;
592 controller->irq = irq;
593
594 spin_lock_init(&controller->lock);
595 init_completion(&controller->done);
596
597 iomode = readl_relaxed(base + QUP_IO_M_MODES);
598
599 size = QUP_IO_M_OUTPUT_BLOCK_SIZE(iomode);
600 if (size)
601 controller->out_blk_sz = size * 16;
602 else
603 controller->out_blk_sz = 4;
604
605 size = QUP_IO_M_INPUT_BLOCK_SIZE(iomode);
606 if (size)
607 controller->in_blk_sz = size * 16;
608 else
609 controller->in_blk_sz = 4;
610
611 size = QUP_IO_M_OUTPUT_FIFO_SIZE(iomode);
612 controller->out_fifo_sz = controller->out_blk_sz * (2 << size);
613
614 size = QUP_IO_M_INPUT_FIFO_SIZE(iomode);
615 controller->in_fifo_sz = controller->in_blk_sz * (2 << size);
616
617 dev_info(dev, "v.%08x IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n",
618 data, controller->in_blk_sz, controller->in_fifo_sz,
619 controller->out_blk_sz, controller->out_fifo_sz);
620
621 writel_relaxed(1, base + QUP_SW_RESET);
622
623 ret = spi_qup_set_state(controller, QUP_STATE_RESET);
624 if (ret) {
625 dev_err(dev, "cannot set RESET state\n");
626 goto error;
627 }
628
629 writel_relaxed(0, base + QUP_OPERATIONAL);
630 writel_relaxed(0, base + QUP_IO_M_MODES);
631 writel_relaxed(0, base + QUP_OPERATIONAL_MASK);
632 writel_relaxed(SPI_ERROR_CLK_UNDER_RUN | SPI_ERROR_CLK_OVER_RUN,
633 base + SPI_ERROR_FLAGS_EN);
634
635 writel_relaxed(0, base + SPI_CONFIG);
636 writel_relaxed(SPI_IO_C_NO_TRI_STATE, base + SPI_IO_CONTROL);
637
638 ret = devm_request_irq(dev, irq, spi_qup_qup_irq,
639 IRQF_TRIGGER_HIGH, pdev->name, controller);
640 if (ret)
641 goto error;
642
643 ret = devm_spi_register_master(dev, master);
644 if (ret)
645 goto error;
646
647 pm_runtime_set_autosuspend_delay(dev, MSEC_PER_SEC);
648 pm_runtime_use_autosuspend(dev);
649 pm_runtime_set_active(dev);
650 pm_runtime_enable(dev);
651 return 0;
652
653error:
654 clk_disable_unprepare(cclk);
655 clk_disable_unprepare(iclk);
656 spi_master_put(master);
657 return ret;
658}
659
660#ifdef CONFIG_PM_RUNTIME
661static int spi_qup_pm_suspend_runtime(struct device *device)
662{
663 struct spi_master *master = dev_get_drvdata(device);
664 struct spi_qup *controller = spi_master_get_devdata(master);
665 u32 config;
666
667 /* Enable clocks auto gaiting */
668 config = readl(controller->base + QUP_CONFIG);
669 config |= QUP_CONFIG_CLOCK_AUTO_GATE;
670 writel_relaxed(config, controller->base + QUP_CONFIG);
671 return 0;
672}
673
674static int spi_qup_pm_resume_runtime(struct device *device)
675{
676 struct spi_master *master = dev_get_drvdata(device);
677 struct spi_qup *controller = spi_master_get_devdata(master);
678 u32 config;
679
680 /* Disable clocks auto gaiting */
681 config = readl_relaxed(controller->base + QUP_CONFIG);
682 config &= ~QUP_CONFIG_CLOCK_AUTO_GATE;
683 writel_relaxed(config, controller->base + QUP_CONFIG);
684 return 0;
685}
686#endif /* CONFIG_PM_RUNTIME */
687
688#ifdef CONFIG_PM_SLEEP
689static int spi_qup_suspend(struct device *device)
690{
691 struct spi_master *master = dev_get_drvdata(device);
692 struct spi_qup *controller = spi_master_get_devdata(master);
693 int ret;
694
695 ret = spi_master_suspend(master);
696 if (ret)
697 return ret;
698
699 ret = spi_qup_set_state(controller, QUP_STATE_RESET);
700 if (ret)
701 return ret;
702
703 clk_disable_unprepare(controller->cclk);
704 clk_disable_unprepare(controller->iclk);
705 return 0;
706}
707
708static int spi_qup_resume(struct device *device)
709{
710 struct spi_master *master = dev_get_drvdata(device);
711 struct spi_qup *controller = spi_master_get_devdata(master);
712 int ret;
713
714 ret = clk_prepare_enable(controller->iclk);
715 if (ret)
716 return ret;
717
718 ret = clk_prepare_enable(controller->cclk);
719 if (ret)
720 return ret;
721
722 ret = spi_qup_set_state(controller, QUP_STATE_RESET);
723 if (ret)
724 return ret;
725
726 return spi_master_resume(master);
727}
728#endif /* CONFIG_PM_SLEEP */
729
730static int spi_qup_remove(struct platform_device *pdev)
731{
732 struct spi_master *master = dev_get_drvdata(&pdev->dev);
733 struct spi_qup *controller = spi_master_get_devdata(master);
734 int ret;
735
736 ret = pm_runtime_get_sync(&pdev->dev);
737 if (ret)
738 return ret;
739
740 ret = spi_qup_set_state(controller, QUP_STATE_RESET);
741 if (ret)
742 return ret;
743
744 clk_disable_unprepare(controller->cclk);
745 clk_disable_unprepare(controller->iclk);
746
747 pm_runtime_put_noidle(&pdev->dev);
748 pm_runtime_disable(&pdev->dev);
749 return 0;
750}
751
752static struct of_device_id spi_qup_dt_match[] = {
753 { .compatible = "qcom,spi-qup-v2.1.1", },
754 { .compatible = "qcom,spi-qup-v2.2.1", },
755 { }
756};
757MODULE_DEVICE_TABLE(of, spi_qup_dt_match);
758
759static const struct dev_pm_ops spi_qup_dev_pm_ops = {
760 SET_SYSTEM_SLEEP_PM_OPS(spi_qup_suspend, spi_qup_resume)
761 SET_RUNTIME_PM_OPS(spi_qup_pm_suspend_runtime,
762 spi_qup_pm_resume_runtime,
763 NULL)
764};
765
766static struct platform_driver spi_qup_driver = {
767 .driver = {
768 .name = "spi_qup",
769 .owner = THIS_MODULE,
770 .pm = &spi_qup_dev_pm_ops,
771 .of_match_table = spi_qup_dt_match,
772 },
773 .probe = spi_qup_probe,
774 .remove = spi_qup_remove,
775};
776module_platform_driver(spi_qup_driver);
777
778MODULE_LICENSE("GPL v2");
779MODULE_ALIAS("platform:spi_qup");
diff --git a/drivers/spi/spi-rspi.c b/drivers/spi/spi-rspi.c
index 28987d9fcfe5..1fb0ad213324 100644
--- a/drivers/spi/spi-rspi.c
+++ b/drivers/spi/spi-rspi.c
@@ -1,7 +1,8 @@
1/* 1/*
2 * SH RSPI driver 2 * SH RSPI driver
3 * 3 *
4 * Copyright (C) 2012 Renesas Solutions Corp. 4 * Copyright (C) 2012, 2013 Renesas Solutions Corp.
5 * Copyright (C) 2014 Glider bvba
5 * 6 *
6 * Based on spi-sh.c: 7 * Based on spi-sh.c:
7 * Copyright (C) 2011 Renesas Solutions Corp. 8 * Copyright (C) 2011 Renesas Solutions Corp.
@@ -25,14 +26,14 @@
25#include <linux/kernel.h> 26#include <linux/kernel.h>
26#include <linux/sched.h> 27#include <linux/sched.h>
27#include <linux/errno.h> 28#include <linux/errno.h>
28#include <linux/list.h>
29#include <linux/workqueue.h>
30#include <linux/interrupt.h> 29#include <linux/interrupt.h>
31#include <linux/platform_device.h> 30#include <linux/platform_device.h>
32#include <linux/io.h> 31#include <linux/io.h>
33#include <linux/clk.h> 32#include <linux/clk.h>
34#include <linux/dmaengine.h> 33#include <linux/dmaengine.h>
35#include <linux/dma-mapping.h> 34#include <linux/dma-mapping.h>
35#include <linux/of_device.h>
36#include <linux/pm_runtime.h>
36#include <linux/sh_dma.h> 37#include <linux/sh_dma.h>
37#include <linux/spi/spi.h> 38#include <linux/spi/spi.h>
38#include <linux/spi/rspi.h> 39#include <linux/spi/rspi.h>
@@ -49,7 +50,7 @@
49#define RSPI_SPCKD 0x0c /* Clock Delay Register */ 50#define RSPI_SPCKD 0x0c /* Clock Delay Register */
50#define RSPI_SSLND 0x0d /* Slave Select Negation Delay Register */ 51#define RSPI_SSLND 0x0d /* Slave Select Negation Delay Register */
51#define RSPI_SPND 0x0e /* Next-Access Delay Register */ 52#define RSPI_SPND 0x0e /* Next-Access Delay Register */
52#define RSPI_SPCR2 0x0f /* Control Register 2 */ 53#define RSPI_SPCR2 0x0f /* Control Register 2 (SH only) */
53#define RSPI_SPCMD0 0x10 /* Command Register 0 */ 54#define RSPI_SPCMD0 0x10 /* Command Register 0 */
54#define RSPI_SPCMD1 0x12 /* Command Register 1 */ 55#define RSPI_SPCMD1 0x12 /* Command Register 1 */
55#define RSPI_SPCMD2 0x14 /* Command Register 2 */ 56#define RSPI_SPCMD2 0x14 /* Command Register 2 */
@@ -58,16 +59,23 @@
58#define RSPI_SPCMD5 0x1a /* Command Register 5 */ 59#define RSPI_SPCMD5 0x1a /* Command Register 5 */
59#define RSPI_SPCMD6 0x1c /* Command Register 6 */ 60#define RSPI_SPCMD6 0x1c /* Command Register 6 */
60#define RSPI_SPCMD7 0x1e /* Command Register 7 */ 61#define RSPI_SPCMD7 0x1e /* Command Register 7 */
62#define RSPI_SPCMD(i) (RSPI_SPCMD0 + (i) * 2)
63#define RSPI_NUM_SPCMD 8
64#define RSPI_RZ_NUM_SPCMD 4
65#define QSPI_NUM_SPCMD 4
66
67/* RSPI on RZ only */
61#define RSPI_SPBFCR 0x20 /* Buffer Control Register */ 68#define RSPI_SPBFCR 0x20 /* Buffer Control Register */
62#define RSPI_SPBFDR 0x22 /* Buffer Data Count Setting Register */ 69#define RSPI_SPBFDR 0x22 /* Buffer Data Count Setting Register */
63 70
64/*qspi only */ 71/* QSPI only */
65#define QSPI_SPBFCR 0x18 /* Buffer Control Register */ 72#define QSPI_SPBFCR 0x18 /* Buffer Control Register */
66#define QSPI_SPBDCR 0x1a /* Buffer Data Count Register */ 73#define QSPI_SPBDCR 0x1a /* Buffer Data Count Register */
67#define QSPI_SPBMUL0 0x1c /* Transfer Data Length Multiplier Setting Register 0 */ 74#define QSPI_SPBMUL0 0x1c /* Transfer Data Length Multiplier Setting Register 0 */
68#define QSPI_SPBMUL1 0x20 /* Transfer Data Length Multiplier Setting Register 1 */ 75#define QSPI_SPBMUL1 0x20 /* Transfer Data Length Multiplier Setting Register 1 */
69#define QSPI_SPBMUL2 0x24 /* Transfer Data Length Multiplier Setting Register 2 */ 76#define QSPI_SPBMUL2 0x24 /* Transfer Data Length Multiplier Setting Register 2 */
70#define QSPI_SPBMUL3 0x28 /* Transfer Data Length Multiplier Setting Register 3 */ 77#define QSPI_SPBMUL3 0x28 /* Transfer Data Length Multiplier Setting Register 3 */
78#define QSPI_SPBMUL(i) (QSPI_SPBMUL0 + (i) * 4)
71 79
72/* SPCR - Control Register */ 80/* SPCR - Control Register */
73#define SPCR_SPRIE 0x80 /* Receive Interrupt Enable */ 81#define SPCR_SPRIE 0x80 /* Receive Interrupt Enable */
@@ -104,7 +112,7 @@
104#define SPSR_PERF 0x08 /* Parity Error Flag */ 112#define SPSR_PERF 0x08 /* Parity Error Flag */
105#define SPSR_MODF 0x04 /* Mode Fault Error Flag */ 113#define SPSR_MODF 0x04 /* Mode Fault Error Flag */
106#define SPSR_IDLNF 0x02 /* RSPI Idle Flag */ 114#define SPSR_IDLNF 0x02 /* RSPI Idle Flag */
107#define SPSR_OVRF 0x01 /* Overrun Error Flag */ 115#define SPSR_OVRF 0x01 /* Overrun Error Flag (RSPI only) */
108 116
109/* SPSCR - Sequence Control Register */ 117/* SPSCR - Sequence Control Register */
110#define SPSCR_SPSLN_MASK 0x07 /* Sequence Length Specification */ 118#define SPSCR_SPSLN_MASK 0x07 /* Sequence Length Specification */
@@ -121,13 +129,13 @@
121#define SPDCR_SPLWORD SPDCR_SPLW1 129#define SPDCR_SPLWORD SPDCR_SPLW1
122#define SPDCR_SPLBYTE SPDCR_SPLW0 130#define SPDCR_SPLBYTE SPDCR_SPLW0
123#define SPDCR_SPLW 0x20 /* Access Width Specification (SH) */ 131#define SPDCR_SPLW 0x20 /* Access Width Specification (SH) */
124#define SPDCR_SPRDTD 0x10 /* Receive Transmit Data Select */ 132#define SPDCR_SPRDTD 0x10 /* Receive Transmit Data Select (SH) */
125#define SPDCR_SLSEL1 0x08 133#define SPDCR_SLSEL1 0x08
126#define SPDCR_SLSEL0 0x04 134#define SPDCR_SLSEL0 0x04
127#define SPDCR_SLSEL_MASK 0x0c /* SSL1 Output Select */ 135#define SPDCR_SLSEL_MASK 0x0c /* SSL1 Output Select (SH) */
128#define SPDCR_SPFC1 0x02 136#define SPDCR_SPFC1 0x02
129#define SPDCR_SPFC0 0x01 137#define SPDCR_SPFC0 0x01
130#define SPDCR_SPFC_MASK 0x03 /* Frame Count Setting (1-4) */ 138#define SPDCR_SPFC_MASK 0x03 /* Frame Count Setting (1-4) (SH) */
131 139
132/* SPCKD - Clock Delay Register */ 140/* SPCKD - Clock Delay Register */
133#define SPCKD_SCKDL_MASK 0x07 /* Clock Delay Setting (1-8) */ 141#define SPCKD_SCKDL_MASK 0x07 /* Clock Delay Setting (1-8) */
@@ -151,7 +159,7 @@
151#define SPCMD_LSBF 0x1000 /* LSB First */ 159#define SPCMD_LSBF 0x1000 /* LSB First */
152#define SPCMD_SPB_MASK 0x0f00 /* Data Length Setting */ 160#define SPCMD_SPB_MASK 0x0f00 /* Data Length Setting */
153#define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK) 161#define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK)
154#define SPCMD_SPB_8BIT 0x0000 /* qspi only */ 162#define SPCMD_SPB_8BIT 0x0000 /* QSPI only */
155#define SPCMD_SPB_16BIT 0x0100 163#define SPCMD_SPB_16BIT 0x0100
156#define SPCMD_SPB_20BIT 0x0000 164#define SPCMD_SPB_20BIT 0x0000
157#define SPCMD_SPB_24BIT 0x0100 165#define SPCMD_SPB_24BIT 0x0100
@@ -170,8 +178,8 @@
170#define SPCMD_CPHA 0x0001 /* Clock Phase Setting */ 178#define SPCMD_CPHA 0x0001 /* Clock Phase Setting */
171 179
172/* SPBFCR - Buffer Control Register */ 180/* SPBFCR - Buffer Control Register */
173#define SPBFCR_TXRST 0x80 /* Transmit Buffer Data Reset (qspi only) */ 181#define SPBFCR_TXRST 0x80 /* Transmit Buffer Data Reset */
174#define SPBFCR_RXRST 0x40 /* Receive Buffer Data Reset (qspi only) */ 182#define SPBFCR_RXRST 0x40 /* Receive Buffer Data Reset */
175#define SPBFCR_TXTRG_MASK 0x30 /* Transmit Buffer Data Triggering Number */ 183#define SPBFCR_TXTRG_MASK 0x30 /* Transmit Buffer Data Triggering Number */
176#define SPBFCR_RXTRG_MASK 0x07 /* Receive Buffer Data Triggering Number */ 184#define SPBFCR_RXTRG_MASK 0x07 /* Receive Buffer Data Triggering Number */
177 185
@@ -181,22 +189,21 @@ struct rspi_data {
181 void __iomem *addr; 189 void __iomem *addr;
182 u32 max_speed_hz; 190 u32 max_speed_hz;
183 struct spi_master *master; 191 struct spi_master *master;
184 struct list_head queue;
185 struct work_struct ws;
186 wait_queue_head_t wait; 192 wait_queue_head_t wait;
187 spinlock_t lock;
188 struct clk *clk; 193 struct clk *clk;
189 u8 spsr;
190 u16 spcmd; 194 u16 spcmd;
195 u8 spsr;
196 u8 sppcr;
197 int rx_irq, tx_irq;
191 const struct spi_ops *ops; 198 const struct spi_ops *ops;
192 199
193 /* for dmaengine */ 200 /* for dmaengine */
194 struct dma_chan *chan_tx; 201 struct dma_chan *chan_tx;
195 struct dma_chan *chan_rx; 202 struct dma_chan *chan_rx;
196 int irq;
197 203
198 unsigned dma_width_16bit:1; 204 unsigned dma_width_16bit:1;
199 unsigned dma_callbacked:1; 205 unsigned dma_callbacked:1;
206 unsigned byte_access:1;
200}; 207};
201 208
202static void rspi_write8(const struct rspi_data *rspi, u8 data, u16 offset) 209static void rspi_write8(const struct rspi_data *rspi, u8 data, u16 offset)
@@ -224,34 +231,47 @@ static u16 rspi_read16(const struct rspi_data *rspi, u16 offset)
224 return ioread16(rspi->addr + offset); 231 return ioread16(rspi->addr + offset);
225} 232}
226 233
234static void rspi_write_data(const struct rspi_data *rspi, u16 data)
235{
236 if (rspi->byte_access)
237 rspi_write8(rspi, data, RSPI_SPDR);
238 else /* 16 bit */
239 rspi_write16(rspi, data, RSPI_SPDR);
240}
241
242static u16 rspi_read_data(const struct rspi_data *rspi)
243{
244 if (rspi->byte_access)
245 return rspi_read8(rspi, RSPI_SPDR);
246 else /* 16 bit */
247 return rspi_read16(rspi, RSPI_SPDR);
248}
249
227/* optional functions */ 250/* optional functions */
228struct spi_ops { 251struct spi_ops {
229 int (*set_config_register)(const struct rspi_data *rspi, 252 int (*set_config_register)(struct rspi_data *rspi, int access_size);
230 int access_size); 253 int (*transfer_one)(struct spi_master *master, struct spi_device *spi,
231 int (*send_pio)(struct rspi_data *rspi, struct spi_message *mesg, 254 struct spi_transfer *xfer);
232 struct spi_transfer *t); 255 u16 mode_bits;
233 int (*receive_pio)(struct rspi_data *rspi, struct spi_message *mesg,
234 struct spi_transfer *t);
235
236}; 256};
237 257
238/* 258/*
239 * functions for RSPI 259 * functions for RSPI on legacy SH
240 */ 260 */
241static int rspi_set_config_register(const struct rspi_data *rspi, 261static int rspi_set_config_register(struct rspi_data *rspi, int access_size)
242 int access_size)
243{ 262{
244 int spbr; 263 int spbr;
245 264
246 /* Sets output mode(CMOS) and MOSI signal(from previous transfer) */ 265 /* Sets output mode, MOSI signal, and (optionally) loopback */
247 rspi_write8(rspi, 0x00, RSPI_SPPCR); 266 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
248 267
249 /* Sets transfer bit rate */ 268 /* Sets transfer bit rate */
250 spbr = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz) - 1; 269 spbr = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz) - 1;
251 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); 270 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
252 271
253 /* Sets number of frames to be used: 1 frame */ 272 /* Disable dummy transmission, set 16-bit word access, 1 frame */
254 rspi_write8(rspi, 0x00, RSPI_SPDCR); 273 rspi_write8(rspi, 0, RSPI_SPDCR);
274 rspi->byte_access = 0;
255 275
256 /* Sets RSPCK, SSL, next-access delay value */ 276 /* Sets RSPCK, SSL, next-access delay value */
257 rspi_write8(rspi, 0x00, RSPI_SPCKD); 277 rspi_write8(rspi, 0x00, RSPI_SPCKD);
@@ -262,8 +282,41 @@ static int rspi_set_config_register(const struct rspi_data *rspi,
262 rspi_write8(rspi, 0x00, RSPI_SPCR2); 282 rspi_write8(rspi, 0x00, RSPI_SPCR2);
263 283
264 /* Sets SPCMD */ 284 /* Sets SPCMD */
265 rspi_write16(rspi, SPCMD_SPB_8_TO_16(access_size) | rspi->spcmd, 285 rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);
266 RSPI_SPCMD0); 286 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
287
288 /* Sets RSPI mode */
289 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
290
291 return 0;
292}
293
294/*
295 * functions for RSPI on RZ
296 */
297static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size)
298{
299 int spbr;
300
301 /* Sets output mode, MOSI signal, and (optionally) loopback */
302 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
303
304 /* Sets transfer bit rate */
305 spbr = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz) - 1;
306 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
307
308 /* Disable dummy transmission, set byte access */
309 rspi_write8(rspi, SPDCR_SPLBYTE, RSPI_SPDCR);
310 rspi->byte_access = 1;
311
312 /* Sets RSPCK, SSL, next-access delay value */
313 rspi_write8(rspi, 0x00, RSPI_SPCKD);
314 rspi_write8(rspi, 0x00, RSPI_SSLND);
315 rspi_write8(rspi, 0x00, RSPI_SPND);
316
317 /* Sets SPCMD */
318 rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);
319 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
267 320
268 /* Sets RSPI mode */ 321 /* Sets RSPI mode */
269 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR); 322 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
@@ -274,21 +327,20 @@ static int rspi_set_config_register(const struct rspi_data *rspi,
274/* 327/*
275 * functions for QSPI 328 * functions for QSPI
276 */ 329 */
277static int qspi_set_config_register(const struct rspi_data *rspi, 330static int qspi_set_config_register(struct rspi_data *rspi, int access_size)
278 int access_size)
279{ 331{
280 u16 spcmd;
281 int spbr; 332 int spbr;
282 333
283 /* Sets output mode(CMOS) and MOSI signal(from previous transfer) */ 334 /* Sets output mode, MOSI signal, and (optionally) loopback */
284 rspi_write8(rspi, 0x00, RSPI_SPPCR); 335 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
285 336
286 /* Sets transfer bit rate */ 337 /* Sets transfer bit rate */
287 spbr = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz); 338 spbr = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz);
288 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); 339 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
289 340
290 /* Sets number of frames to be used: 1 frame */ 341 /* Disable dummy transmission, set byte access */
291 rspi_write8(rspi, 0x00, RSPI_SPDCR); 342 rspi_write8(rspi, 0, RSPI_SPDCR);
343 rspi->byte_access = 1;
292 344
293 /* Sets RSPCK, SSL, next-access delay value */ 345 /* Sets RSPCK, SSL, next-access delay value */
294 rspi_write8(rspi, 0x00, RSPI_SPCKD); 346 rspi_write8(rspi, 0x00, RSPI_SPCKD);
@@ -297,13 +349,13 @@ static int qspi_set_config_register(const struct rspi_data *rspi,
297 349
298 /* Data Length Setting */ 350 /* Data Length Setting */
299 if (access_size == 8) 351 if (access_size == 8)
300 spcmd = SPCMD_SPB_8BIT; 352 rspi->spcmd |= SPCMD_SPB_8BIT;
301 else if (access_size == 16) 353 else if (access_size == 16)
302 spcmd = SPCMD_SPB_16BIT; 354 rspi->spcmd |= SPCMD_SPB_16BIT;
303 else 355 else
304 spcmd = SPCMD_SPB_32BIT; 356 rspi->spcmd |= SPCMD_SPB_32BIT;
305 357
306 spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | rspi->spcmd | SPCMD_SPNDEN; 358 rspi->spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | SPCMD_SPNDEN;
307 359
308 /* Resets transfer data length */ 360 /* Resets transfer data length */
309 rspi_write32(rspi, 0, QSPI_SPBMUL0); 361 rspi_write32(rspi, 0, QSPI_SPBMUL0);
@@ -314,9 +366,9 @@ static int qspi_set_config_register(const struct rspi_data *rspi,
314 rspi_write8(rspi, 0x00, QSPI_SPBFCR); 366 rspi_write8(rspi, 0x00, QSPI_SPBFCR);
315 367
316 /* Sets SPCMD */ 368 /* Sets SPCMD */
317 rspi_write16(rspi, spcmd, RSPI_SPCMD0); 369 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
318 370
319 /* Enables SPI function in a master mode */ 371 /* Enables SPI function in master mode */
320 rspi_write8(rspi, SPCR_SPE | SPCR_MSTR, RSPI_SPCR); 372 rspi_write8(rspi, SPCR_SPE | SPCR_MSTR, RSPI_SPCR);
321 373
322 return 0; 374 return 0;
@@ -340,6 +392,9 @@ static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask,
340 int ret; 392 int ret;
341 393
342 rspi->spsr = rspi_read8(rspi, RSPI_SPSR); 394 rspi->spsr = rspi_read8(rspi, RSPI_SPSR);
395 if (rspi->spsr & wait_mask)
396 return 0;
397
343 rspi_enable_irq(rspi, enable_bit); 398 rspi_enable_irq(rspi, enable_bit);
344 ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ); 399 ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ);
345 if (ret == 0 && !(rspi->spsr & wait_mask)) 400 if (ret == 0 && !(rspi->spsr & wait_mask))
@@ -348,78 +403,39 @@ static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask,
348 return 0; 403 return 0;
349} 404}
350 405
351static void rspi_assert_ssl(const struct rspi_data *rspi) 406static int rspi_data_out(struct rspi_data *rspi, u8 data)
352{
353 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR);
354}
355
356static void rspi_negate_ssl(const struct rspi_data *rspi)
357{ 407{
358 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR); 408 if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) {
409 dev_err(&rspi->master->dev, "transmit timeout\n");
410 return -ETIMEDOUT;
411 }
412 rspi_write_data(rspi, data);
413 return 0;
359} 414}
360 415
361static int rspi_send_pio(struct rspi_data *rspi, struct spi_message *mesg, 416static int rspi_data_in(struct rspi_data *rspi)
362 struct spi_transfer *t)
363{ 417{
364 int remain = t->len; 418 u8 data;
365 const u8 *data = t->tx_buf;
366 while (remain > 0) {
367 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_TXMD,
368 RSPI_SPCR);
369
370 if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) {
371 dev_err(&rspi->master->dev,
372 "%s: tx empty timeout\n", __func__);
373 return -ETIMEDOUT;
374 }
375 419
376 rspi_write16(rspi, *data, RSPI_SPDR); 420 if (rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE) < 0) {
377 data++; 421 dev_err(&rspi->master->dev, "receive timeout\n");
378 remain--; 422 return -ETIMEDOUT;
379 } 423 }
380 424 data = rspi_read_data(rspi);
381 /* Waiting for the last transmission */ 425 return data;
382 rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
383
384 return 0;
385} 426}
386 427
387static int qspi_send_pio(struct rspi_data *rspi, struct spi_message *mesg, 428static int rspi_data_out_in(struct rspi_data *rspi, u8 data)
388 struct spi_transfer *t)
389{ 429{
390 int remain = t->len; 430 int ret;
391 const u8 *data = t->tx_buf;
392
393 rspi_write8(rspi, SPBFCR_TXRST, QSPI_SPBFCR);
394 rspi_write8(rspi, 0x00, QSPI_SPBFCR);
395
396 while (remain > 0) {
397
398 if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) {
399 dev_err(&rspi->master->dev,
400 "%s: tx empty timeout\n", __func__);
401 return -ETIMEDOUT;
402 }
403 rspi_write8(rspi, *data++, RSPI_SPDR);
404
405 if (rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE) < 0) {
406 dev_err(&rspi->master->dev,
407 "%s: receive timeout\n", __func__);
408 return -ETIMEDOUT;
409 }
410 rspi_read8(rspi, RSPI_SPDR);
411
412 remain--;
413 }
414 431
415 /* Waiting for the last transmission */ 432 ret = rspi_data_out(rspi, data);
416 rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE); 433 if (ret < 0)
434 return ret;
417 435
418 return 0; 436 return rspi_data_in(rspi);
419} 437}
420 438
421#define send_pio(spi, mesg, t) spi->ops->send_pio(spi, mesg, t)
422
423static void rspi_dma_complete(void *arg) 439static void rspi_dma_complete(void *arg)
424{ 440{
425 struct rspi_data *rspi = arg; 441 struct rspi_data *rspi = arg;
@@ -471,7 +487,7 @@ static int rspi_send_dma(struct rspi_data *rspi, struct spi_transfer *t)
471 struct scatterlist sg; 487 struct scatterlist sg;
472 const void *buf = NULL; 488 const void *buf = NULL;
473 struct dma_async_tx_descriptor *desc; 489 struct dma_async_tx_descriptor *desc;
474 unsigned len; 490 unsigned int len;
475 int ret = 0; 491 int ret = 0;
476 492
477 if (rspi->dma_width_16bit) { 493 if (rspi->dma_width_16bit) {
@@ -509,7 +525,7 @@ static int rspi_send_dma(struct rspi_data *rspi, struct spi_transfer *t)
509 * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be 525 * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be
510 * called. So, this driver disables the IRQ while DMA transfer. 526 * called. So, this driver disables the IRQ while DMA transfer.
511 */ 527 */
512 disable_irq(rspi->irq); 528 disable_irq(rspi->tx_irq);
513 529
514 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_TXMD, RSPI_SPCR); 530 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_TXMD, RSPI_SPCR);
515 rspi_enable_irq(rspi, SPCR_SPTIE); 531 rspi_enable_irq(rspi, SPCR_SPTIE);
@@ -528,7 +544,7 @@ static int rspi_send_dma(struct rspi_data *rspi, struct spi_transfer *t)
528 ret = -ETIMEDOUT; 544 ret = -ETIMEDOUT;
529 rspi_disable_irq(rspi, SPCR_SPTIE); 545 rspi_disable_irq(rspi, SPCR_SPTIE);
530 546
531 enable_irq(rspi->irq); 547 enable_irq(rspi->tx_irq);
532 548
533end: 549end:
534 rspi_dma_unmap_sg(&sg, rspi->chan_tx, DMA_TO_DEVICE); 550 rspi_dma_unmap_sg(&sg, rspi->chan_tx, DMA_TO_DEVICE);
@@ -545,46 +561,17 @@ static void rspi_receive_init(const struct rspi_data *rspi)
545 561
546 spsr = rspi_read8(rspi, RSPI_SPSR); 562 spsr = rspi_read8(rspi, RSPI_SPSR);
547 if (spsr & SPSR_SPRF) 563 if (spsr & SPSR_SPRF)
548 rspi_read16(rspi, RSPI_SPDR); /* dummy read */ 564 rspi_read_data(rspi); /* dummy read */
549 if (spsr & SPSR_OVRF) 565 if (spsr & SPSR_OVRF)
550 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF, 566 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF,
551 RSPI_SPSR); 567 RSPI_SPSR);
552} 568}
553 569
554static int rspi_receive_pio(struct rspi_data *rspi, struct spi_message *mesg, 570static void rspi_rz_receive_init(const struct rspi_data *rspi)
555 struct spi_transfer *t)
556{ 571{
557 int remain = t->len;
558 u8 *data;
559
560 rspi_receive_init(rspi); 572 rspi_receive_init(rspi);
561 573 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, RSPI_SPBFCR);
562 data = t->rx_buf; 574 rspi_write8(rspi, 0, RSPI_SPBFCR);
563 while (remain > 0) {
564 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_TXMD,
565 RSPI_SPCR);
566
567 if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) {
568 dev_err(&rspi->master->dev,
569 "%s: tx empty timeout\n", __func__);
570 return -ETIMEDOUT;
571 }
572 /* dummy write for generate clock */
573 rspi_write16(rspi, DUMMY_DATA, RSPI_SPDR);
574
575 if (rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE) < 0) {
576 dev_err(&rspi->master->dev,
577 "%s: receive timeout\n", __func__);
578 return -ETIMEDOUT;
579 }
580 /* SPDR allows 16 or 32-bit access only */
581 *data = (u8)rspi_read16(rspi, RSPI_SPDR);
582
583 data++;
584 remain--;
585 }
586
587 return 0;
588} 575}
589 576
590static void qspi_receive_init(const struct rspi_data *rspi) 577static void qspi_receive_init(const struct rspi_data *rspi)
@@ -593,51 +580,17 @@ static void qspi_receive_init(const struct rspi_data *rspi)
593 580
594 spsr = rspi_read8(rspi, RSPI_SPSR); 581 spsr = rspi_read8(rspi, RSPI_SPSR);
595 if (spsr & SPSR_SPRF) 582 if (spsr & SPSR_SPRF)
596 rspi_read8(rspi, RSPI_SPDR); /* dummy read */ 583 rspi_read_data(rspi); /* dummy read */
597 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR); 584 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR);
598 rspi_write8(rspi, 0x00, QSPI_SPBFCR); 585 rspi_write8(rspi, 0, QSPI_SPBFCR);
599} 586}
600 587
601static int qspi_receive_pio(struct rspi_data *rspi, struct spi_message *mesg,
602 struct spi_transfer *t)
603{
604 int remain = t->len;
605 u8 *data;
606
607 qspi_receive_init(rspi);
608
609 data = t->rx_buf;
610 while (remain > 0) {
611
612 if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) {
613 dev_err(&rspi->master->dev,
614 "%s: tx empty timeout\n", __func__);
615 return -ETIMEDOUT;
616 }
617 /* dummy write for generate clock */
618 rspi_write8(rspi, DUMMY_DATA, RSPI_SPDR);
619
620 if (rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE) < 0) {
621 dev_err(&rspi->master->dev,
622 "%s: receive timeout\n", __func__);
623 return -ETIMEDOUT;
624 }
625 /* SPDR allows 8, 16 or 32-bit access */
626 *data++ = rspi_read8(rspi, RSPI_SPDR);
627 remain--;
628 }
629
630 return 0;
631}
632
633#define receive_pio(spi, mesg, t) spi->ops->receive_pio(spi, mesg, t)
634
635static int rspi_receive_dma(struct rspi_data *rspi, struct spi_transfer *t) 588static int rspi_receive_dma(struct rspi_data *rspi, struct spi_transfer *t)
636{ 589{
637 struct scatterlist sg, sg_dummy; 590 struct scatterlist sg, sg_dummy;
638 void *dummy = NULL, *rx_buf = NULL; 591 void *dummy = NULL, *rx_buf = NULL;
639 struct dma_async_tx_descriptor *desc, *desc_dummy; 592 struct dma_async_tx_descriptor *desc, *desc_dummy;
640 unsigned len; 593 unsigned int len;
641 int ret = 0; 594 int ret = 0;
642 595
643 if (rspi->dma_width_16bit) { 596 if (rspi->dma_width_16bit) {
@@ -695,7 +648,9 @@ static int rspi_receive_dma(struct rspi_data *rspi, struct spi_transfer *t)
695 * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be 648 * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be
696 * called. So, this driver disables the IRQ while DMA transfer. 649 * called. So, this driver disables the IRQ while DMA transfer.
697 */ 650 */
698 disable_irq(rspi->irq); 651 disable_irq(rspi->tx_irq);
652 if (rspi->rx_irq != rspi->tx_irq)
653 disable_irq(rspi->rx_irq);
699 654
700 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_TXMD, RSPI_SPCR); 655 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_TXMD, RSPI_SPCR);
701 rspi_enable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE); 656 rspi_enable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE);
@@ -718,7 +673,9 @@ static int rspi_receive_dma(struct rspi_data *rspi, struct spi_transfer *t)
718 ret = -ETIMEDOUT; 673 ret = -ETIMEDOUT;
719 rspi_disable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE); 674 rspi_disable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE);
720 675
721 enable_irq(rspi->irq); 676 enable_irq(rspi->tx_irq);
677 if (rspi->rx_irq != rspi->tx_irq)
678 enable_irq(rspi->rx_irq);
722 679
723end: 680end:
724 rspi_dma_unmap_sg(&sg, rspi->chan_rx, DMA_FROM_DEVICE); 681 rspi_dma_unmap_sg(&sg, rspi->chan_rx, DMA_FROM_DEVICE);
@@ -746,56 +703,175 @@ static int rspi_is_dma(const struct rspi_data *rspi, struct spi_transfer *t)
746 return 0; 703 return 0;
747} 704}
748 705
749static void rspi_work(struct work_struct *work) 706static int rspi_transfer_out_in(struct rspi_data *rspi,
707 struct spi_transfer *xfer)
750{ 708{
751 struct rspi_data *rspi = container_of(work, struct rspi_data, ws); 709 int remain = xfer->len, ret;
752 struct spi_message *mesg; 710 const u8 *tx_buf = xfer->tx_buf;
753 struct spi_transfer *t; 711 u8 *rx_buf = xfer->rx_buf;
754 unsigned long flags; 712 u8 spcr, data;
755 int ret;
756 713
757 while (1) { 714 rspi_receive_init(rspi);
758 spin_lock_irqsave(&rspi->lock, flags); 715
759 if (list_empty(&rspi->queue)) { 716 spcr = rspi_read8(rspi, RSPI_SPCR);
760 spin_unlock_irqrestore(&rspi->lock, flags); 717 if (rx_buf)
761 break; 718 spcr &= ~SPCR_TXMD;
762 } 719 else
763 mesg = list_entry(rspi->queue.next, struct spi_message, queue); 720 spcr |= SPCR_TXMD;
764 list_del_init(&mesg->queue); 721 rspi_write8(rspi, spcr, RSPI_SPCR);
765 spin_unlock_irqrestore(&rspi->lock, flags); 722
766 723 while (remain > 0) {
767 rspi_assert_ssl(rspi); 724 data = tx_buf ? *tx_buf++ : DUMMY_DATA;
768 725 ret = rspi_data_out(rspi, data);
769 list_for_each_entry(t, &mesg->transfers, transfer_list) { 726 if (ret < 0)
770 if (t->tx_buf) { 727 return ret;
771 if (rspi_is_dma(rspi, t)) 728 if (rx_buf) {
772 ret = rspi_send_dma(rspi, t); 729 ret = rspi_data_in(rspi);
773 else 730 if (ret < 0)
774 ret = send_pio(rspi, mesg, t); 731 return ret;
775 if (ret < 0) 732 *rx_buf++ = ret;
776 goto error;
777 }
778 if (t->rx_buf) {
779 if (rspi_is_dma(rspi, t))
780 ret = rspi_receive_dma(rspi, t);
781 else
782 ret = receive_pio(rspi, mesg, t);
783 if (ret < 0)
784 goto error;
785 }
786 mesg->actual_length += t->len;
787 } 733 }
788 rspi_negate_ssl(rspi); 734 remain--;
735 }
736
737 /* Wait for the last transmission */
738 rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
739
740 return 0;
741}
742
743static int rspi_transfer_one(struct spi_master *master, struct spi_device *spi,
744 struct spi_transfer *xfer)
745{
746 struct rspi_data *rspi = spi_master_get_devdata(master);
747 int ret;
748
749 if (!rspi_is_dma(rspi, xfer))
750 return rspi_transfer_out_in(rspi, xfer);
751
752 if (xfer->tx_buf) {
753 ret = rspi_send_dma(rspi, xfer);
754 if (ret < 0)
755 return ret;
756 }
757 if (xfer->rx_buf)
758 return rspi_receive_dma(rspi, xfer);
759
760 return 0;
761}
762
763static int rspi_rz_transfer_out_in(struct rspi_data *rspi,
764 struct spi_transfer *xfer)
765{
766 int remain = xfer->len, ret;
767 const u8 *tx_buf = xfer->tx_buf;
768 u8 *rx_buf = xfer->rx_buf;
769 u8 data;
770
771 rspi_rz_receive_init(rspi);
772
773 while (remain > 0) {
774 data = tx_buf ? *tx_buf++ : DUMMY_DATA;
775 ret = rspi_data_out_in(rspi, data);
776 if (ret < 0)
777 return ret;
778 if (rx_buf)
779 *rx_buf++ = ret;
780 remain--;
781 }
782
783 /* Wait for the last transmission */
784 rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
785
786 return 0;
787}
788
789static int rspi_rz_transfer_one(struct spi_master *master,
790 struct spi_device *spi,
791 struct spi_transfer *xfer)
792{
793 struct rspi_data *rspi = spi_master_get_devdata(master);
794
795 return rspi_rz_transfer_out_in(rspi, xfer);
796}
797
798static int qspi_transfer_out_in(struct rspi_data *rspi,
799 struct spi_transfer *xfer)
800{
801 int remain = xfer->len, ret;
802 const u8 *tx_buf = xfer->tx_buf;
803 u8 *rx_buf = xfer->rx_buf;
804 u8 data;
789 805
790 mesg->status = 0; 806 qspi_receive_init(rspi);
791 mesg->complete(mesg->context); 807
808 while (remain > 0) {
809 data = tx_buf ? *tx_buf++ : DUMMY_DATA;
810 ret = rspi_data_out_in(rspi, data);
811 if (ret < 0)
812 return ret;
813 if (rx_buf)
814 *rx_buf++ = ret;
815 remain--;
816 }
817
818 /* Wait for the last transmission */
819 rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
820
821 return 0;
822}
823
824static int qspi_transfer_out(struct rspi_data *rspi, struct spi_transfer *xfer)
825{
826 const u8 *buf = xfer->tx_buf;
827 unsigned int i;
828 int ret;
829
830 for (i = 0; i < xfer->len; i++) {
831 ret = rspi_data_out(rspi, *buf++);
832 if (ret < 0)
833 return ret;
792 } 834 }
793 835
794 return; 836 /* Wait for the last transmission */
837 rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
795 838
796error: 839 return 0;
797 mesg->status = ret; 840}
798 mesg->complete(mesg->context); 841
842static int qspi_transfer_in(struct rspi_data *rspi, struct spi_transfer *xfer)
843{
844 u8 *buf = xfer->rx_buf;
845 unsigned int i;
846 int ret;
847
848 for (i = 0; i < xfer->len; i++) {
849 ret = rspi_data_in(rspi);
850 if (ret < 0)
851 return ret;
852 *buf++ = ret;
853 }
854
855 return 0;
856}
857
858static int qspi_transfer_one(struct spi_master *master, struct spi_device *spi,
859 struct spi_transfer *xfer)
860{
861 struct rspi_data *rspi = spi_master_get_devdata(master);
862
863 if (spi->mode & SPI_LOOP) {
864 return qspi_transfer_out_in(rspi, xfer);
865 } else if (xfer->tx_buf && xfer->tx_nbits > SPI_NBITS_SINGLE) {
866 /* Quad or Dual SPI Write */
867 return qspi_transfer_out(rspi, xfer);
868 } else if (xfer->rx_buf && xfer->rx_nbits > SPI_NBITS_SINGLE) {
869 /* Quad or Dual SPI Read */
870 return qspi_transfer_in(rspi, xfer);
871 } else {
872 /* Single SPI Transfer */
873 return qspi_transfer_out_in(rspi, xfer);
874 }
799} 875}
800 876
801static int rspi_setup(struct spi_device *spi) 877static int rspi_setup(struct spi_device *spi)
@@ -810,32 +886,115 @@ static int rspi_setup(struct spi_device *spi)
810 if (spi->mode & SPI_CPHA) 886 if (spi->mode & SPI_CPHA)
811 rspi->spcmd |= SPCMD_CPHA; 887 rspi->spcmd |= SPCMD_CPHA;
812 888
889 /* CMOS output mode and MOSI signal from previous transfer */
890 rspi->sppcr = 0;
891 if (spi->mode & SPI_LOOP)
892 rspi->sppcr |= SPPCR_SPLP;
893
813 set_config_register(rspi, 8); 894 set_config_register(rspi, 8);
814 895
815 return 0; 896 return 0;
816} 897}
817 898
818static int rspi_transfer(struct spi_device *spi, struct spi_message *mesg) 899static u16 qspi_transfer_mode(const struct spi_transfer *xfer)
819{ 900{
820 struct rspi_data *rspi = spi_master_get_devdata(spi->master); 901 if (xfer->tx_buf)
821 unsigned long flags; 902 switch (xfer->tx_nbits) {
903 case SPI_NBITS_QUAD:
904 return SPCMD_SPIMOD_QUAD;
905 case SPI_NBITS_DUAL:
906 return SPCMD_SPIMOD_DUAL;
907 default:
908 return 0;
909 }
910 if (xfer->rx_buf)
911 switch (xfer->rx_nbits) {
912 case SPI_NBITS_QUAD:
913 return SPCMD_SPIMOD_QUAD | SPCMD_SPRW;
914 case SPI_NBITS_DUAL:
915 return SPCMD_SPIMOD_DUAL | SPCMD_SPRW;
916 default:
917 return 0;
918 }
919
920 return 0;
921}
822 922
823 mesg->actual_length = 0; 923static int qspi_setup_sequencer(struct rspi_data *rspi,
824 mesg->status = -EINPROGRESS; 924 const struct spi_message *msg)
925{
926 const struct spi_transfer *xfer;
927 unsigned int i = 0, len = 0;
928 u16 current_mode = 0xffff, mode;
929
930 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
931 mode = qspi_transfer_mode(xfer);
932 if (mode == current_mode) {
933 len += xfer->len;
934 continue;
935 }
936
937 /* Transfer mode change */
938 if (i) {
939 /* Set transfer data length of previous transfer */
940 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1));
941 }
825 942
826 spin_lock_irqsave(&rspi->lock, flags); 943 if (i >= QSPI_NUM_SPCMD) {
827 list_add_tail(&mesg->queue, &rspi->queue); 944 dev_err(&msg->spi->dev,
828 schedule_work(&rspi->ws); 945 "Too many different transfer modes");
829 spin_unlock_irqrestore(&rspi->lock, flags); 946 return -EINVAL;
947 }
948
949 /* Program transfer mode for this transfer */
950 rspi_write16(rspi, rspi->spcmd | mode, RSPI_SPCMD(i));
951 current_mode = mode;
952 len = xfer->len;
953 i++;
954 }
955 if (i) {
956 /* Set final transfer data length and sequence length */
957 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1));
958 rspi_write8(rspi, i - 1, RSPI_SPSCR);
959 }
830 960
831 return 0; 961 return 0;
832} 962}
833 963
834static void rspi_cleanup(struct spi_device *spi) 964static int rspi_prepare_message(struct spi_master *master,
965 struct spi_message *msg)
835{ 966{
967 struct rspi_data *rspi = spi_master_get_devdata(master);
968 int ret;
969
970 if (msg->spi->mode &
971 (SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD)) {
972 /* Setup sequencer for messages with multiple transfer modes */
973 ret = qspi_setup_sequencer(rspi, msg);
974 if (ret < 0)
975 return ret;
976 }
977
978 /* Enable SPI function in master mode */
979 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR);
980 return 0;
836} 981}
837 982
838static irqreturn_t rspi_irq(int irq, void *_sr) 983static int rspi_unprepare_message(struct spi_master *master,
984 struct spi_message *msg)
985{
986 struct rspi_data *rspi = spi_master_get_devdata(master);
987
988 /* Disable SPI function */
989 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR);
990
991 /* Reset sequencer for Single SPI Transfers */
992 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
993 rspi_write8(rspi, 0, RSPI_SPSCR);
994 return 0;
995}
996
997static irqreturn_t rspi_irq_mux(int irq, void *_sr)
839{ 998{
840 struct rspi_data *rspi = _sr; 999 struct rspi_data *rspi = _sr;
841 u8 spsr; 1000 u8 spsr;
@@ -857,6 +1016,36 @@ static irqreturn_t rspi_irq(int irq, void *_sr)
857 return ret; 1016 return ret;
858} 1017}
859 1018
1019static irqreturn_t rspi_irq_rx(int irq, void *_sr)
1020{
1021 struct rspi_data *rspi = _sr;
1022 u8 spsr;
1023
1024 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
1025 if (spsr & SPSR_SPRF) {
1026 rspi_disable_irq(rspi, SPCR_SPRIE);
1027 wake_up(&rspi->wait);
1028 return IRQ_HANDLED;
1029 }
1030
1031 return 0;
1032}
1033
1034static irqreturn_t rspi_irq_tx(int irq, void *_sr)
1035{
1036 struct rspi_data *rspi = _sr;
1037 u8 spsr;
1038
1039 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
1040 if (spsr & SPSR_SPTEF) {
1041 rspi_disable_irq(rspi, SPCR_SPTIE);
1042 wake_up(&rspi->wait);
1043 return IRQ_HANDLED;
1044 }
1045
1046 return 0;
1047}
1048
860static int rspi_request_dma(struct rspi_data *rspi, 1049static int rspi_request_dma(struct rspi_data *rspi,
861 struct platform_device *pdev) 1050 struct platform_device *pdev)
862{ 1051{
@@ -923,34 +1112,89 @@ static int rspi_remove(struct platform_device *pdev)
923 struct rspi_data *rspi = platform_get_drvdata(pdev); 1112 struct rspi_data *rspi = platform_get_drvdata(pdev);
924 1113
925 rspi_release_dma(rspi); 1114 rspi_release_dma(rspi);
926 clk_disable(rspi->clk); 1115 pm_runtime_disable(&pdev->dev);
927 1116
928 return 0; 1117 return 0;
929} 1118}
930 1119
1120static const struct spi_ops rspi_ops = {
1121 .set_config_register = rspi_set_config_register,
1122 .transfer_one = rspi_transfer_one,
1123 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP,
1124};
1125
1126static const struct spi_ops rspi_rz_ops = {
1127 .set_config_register = rspi_rz_set_config_register,
1128 .transfer_one = rspi_rz_transfer_one,
1129 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP,
1130};
1131
1132static const struct spi_ops qspi_ops = {
1133 .set_config_register = qspi_set_config_register,
1134 .transfer_one = qspi_transfer_one,
1135 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP |
1136 SPI_TX_DUAL | SPI_TX_QUAD |
1137 SPI_RX_DUAL | SPI_RX_QUAD,
1138};
1139
1140#ifdef CONFIG_OF
1141static const struct of_device_id rspi_of_match[] = {
1142 /* RSPI on legacy SH */
1143 { .compatible = "renesas,rspi", .data = &rspi_ops },
1144 /* RSPI on RZ/A1H */
1145 { .compatible = "renesas,rspi-rz", .data = &rspi_rz_ops },
1146 /* QSPI on R-Car Gen2 */
1147 { .compatible = "renesas,qspi", .data = &qspi_ops },
1148 { /* sentinel */ }
1149};
1150
1151MODULE_DEVICE_TABLE(of, rspi_of_match);
1152
1153static int rspi_parse_dt(struct device *dev, struct spi_master *master)
1154{
1155 u32 num_cs;
1156 int error;
1157
1158 /* Parse DT properties */
1159 error = of_property_read_u32(dev->of_node, "num-cs", &num_cs);
1160 if (error) {
1161 dev_err(dev, "of_property_read_u32 num-cs failed %d\n", error);
1162 return error;
1163 }
1164
1165 master->num_chipselect = num_cs;
1166 return 0;
1167}
1168#else
1169#define rspi_of_match NULL
1170static inline int rspi_parse_dt(struct device *dev, struct spi_master *master)
1171{
1172 return -EINVAL;
1173}
1174#endif /* CONFIG_OF */
1175
1176static int rspi_request_irq(struct device *dev, unsigned int irq,
1177 irq_handler_t handler, const char *suffix,
1178 void *dev_id)
1179{
1180 const char *base = dev_name(dev);
1181 size_t len = strlen(base) + strlen(suffix) + 2;
1182 char *name = devm_kzalloc(dev, len, GFP_KERNEL);
1183 if (!name)
1184 return -ENOMEM;
1185 snprintf(name, len, "%s:%s", base, suffix);
1186 return devm_request_irq(dev, irq, handler, 0, name, dev_id);
1187}
1188
931static int rspi_probe(struct platform_device *pdev) 1189static int rspi_probe(struct platform_device *pdev)
932{ 1190{
933 struct resource *res; 1191 struct resource *res;
934 struct spi_master *master; 1192 struct spi_master *master;
935 struct rspi_data *rspi; 1193 struct rspi_data *rspi;
936 int ret, irq; 1194 int ret;
937 char clk_name[16]; 1195 const struct of_device_id *of_id;
938 const struct rspi_plat_data *rspi_pd = dev_get_platdata(&pdev->dev); 1196 const struct rspi_plat_data *rspi_pd;
939 const struct spi_ops *ops; 1197 const struct spi_ops *ops;
940 const struct platform_device_id *id_entry = pdev->id_entry;
941
942 ops = (struct spi_ops *)id_entry->driver_data;
943 /* ops parameter check */
944 if (!ops->set_config_register) {
945 dev_err(&pdev->dev, "there is no set_config_register\n");
946 return -ENODEV;
947 }
948
949 irq = platform_get_irq(pdev, 0);
950 if (irq < 0) {
951 dev_err(&pdev->dev, "platform_get_irq error\n");
952 return -ENODEV;
953 }
954 1198
955 master = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data)); 1199 master = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data));
956 if (master == NULL) { 1200 if (master == NULL) {
@@ -958,6 +1202,28 @@ static int rspi_probe(struct platform_device *pdev)
958 return -ENOMEM; 1202 return -ENOMEM;
959 } 1203 }
960 1204
1205 of_id = of_match_device(rspi_of_match, &pdev->dev);
1206 if (of_id) {
1207 ops = of_id->data;
1208 ret = rspi_parse_dt(&pdev->dev, master);
1209 if (ret)
1210 goto error1;
1211 } else {
1212 ops = (struct spi_ops *)pdev->id_entry->driver_data;
1213 rspi_pd = dev_get_platdata(&pdev->dev);
1214 if (rspi_pd && rspi_pd->num_chipselect)
1215 master->num_chipselect = rspi_pd->num_chipselect;
1216 else
1217 master->num_chipselect = 2; /* default */
1218 };
1219
1220 /* ops parameter check */
1221 if (!ops->set_config_register) {
1222 dev_err(&pdev->dev, "there is no set_config_register\n");
1223 ret = -ENODEV;
1224 goto error1;
1225 }
1226
961 rspi = spi_master_get_devdata(master); 1227 rspi = spi_master_get_devdata(master);
962 platform_set_drvdata(pdev, rspi); 1228 platform_set_drvdata(pdev, rspi);
963 rspi->ops = ops; 1229 rspi->ops = ops;
@@ -970,39 +1236,61 @@ static int rspi_probe(struct platform_device *pdev)
970 goto error1; 1236 goto error1;
971 } 1237 }
972 1238
973 snprintf(clk_name, sizeof(clk_name), "%s%d", id_entry->name, pdev->id); 1239 rspi->clk = devm_clk_get(&pdev->dev, NULL);
974 rspi->clk = devm_clk_get(&pdev->dev, clk_name);
975 if (IS_ERR(rspi->clk)) { 1240 if (IS_ERR(rspi->clk)) {
976 dev_err(&pdev->dev, "cannot get clock\n"); 1241 dev_err(&pdev->dev, "cannot get clock\n");
977 ret = PTR_ERR(rspi->clk); 1242 ret = PTR_ERR(rspi->clk);
978 goto error1; 1243 goto error1;
979 } 1244 }
980 clk_enable(rspi->clk);
981 1245
982 INIT_LIST_HEAD(&rspi->queue); 1246 pm_runtime_enable(&pdev->dev);
983 spin_lock_init(&rspi->lock);
984 INIT_WORK(&rspi->ws, rspi_work);
985 init_waitqueue_head(&rspi->wait);
986 1247
987 if (rspi_pd && rspi_pd->num_chipselect) 1248 init_waitqueue_head(&rspi->wait);
988 master->num_chipselect = rspi_pd->num_chipselect;
989 else
990 master->num_chipselect = 2; /* default */
991 1249
992 master->bus_num = pdev->id; 1250 master->bus_num = pdev->id;
993 master->setup = rspi_setup; 1251 master->setup = rspi_setup;
994 master->transfer = rspi_transfer; 1252 master->auto_runtime_pm = true;
995 master->cleanup = rspi_cleanup; 1253 master->transfer_one = ops->transfer_one;
996 master->mode_bits = SPI_CPHA | SPI_CPOL; 1254 master->prepare_message = rspi_prepare_message;
1255 master->unprepare_message = rspi_unprepare_message;
1256 master->mode_bits = ops->mode_bits;
1257 master->dev.of_node = pdev->dev.of_node;
1258
1259 ret = platform_get_irq_byname(pdev, "rx");
1260 if (ret < 0) {
1261 ret = platform_get_irq_byname(pdev, "mux");
1262 if (ret < 0)
1263 ret = platform_get_irq(pdev, 0);
1264 if (ret >= 0)
1265 rspi->rx_irq = rspi->tx_irq = ret;
1266 } else {
1267 rspi->rx_irq = ret;
1268 ret = platform_get_irq_byname(pdev, "tx");
1269 if (ret >= 0)
1270 rspi->tx_irq = ret;
1271 }
1272 if (ret < 0) {
1273 dev_err(&pdev->dev, "platform_get_irq error\n");
1274 goto error2;
1275 }
997 1276
998 ret = devm_request_irq(&pdev->dev, irq, rspi_irq, 0, 1277 if (rspi->rx_irq == rspi->tx_irq) {
999 dev_name(&pdev->dev), rspi); 1278 /* Single multiplexed interrupt */
1279 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_mux,
1280 "mux", rspi);
1281 } else {
1282 /* Multi-interrupt mode, only SPRI and SPTI are used */
1283 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_rx,
1284 "rx", rspi);
1285 if (!ret)
1286 ret = rspi_request_irq(&pdev->dev, rspi->tx_irq,
1287 rspi_irq_tx, "tx", rspi);
1288 }
1000 if (ret < 0) { 1289 if (ret < 0) {
1001 dev_err(&pdev->dev, "request_irq error\n"); 1290 dev_err(&pdev->dev, "request_irq error\n");
1002 goto error2; 1291 goto error2;
1003 } 1292 }
1004 1293
1005 rspi->irq = irq;
1006 ret = rspi_request_dma(rspi, pdev); 1294 ret = rspi_request_dma(rspi, pdev);
1007 if (ret < 0) { 1295 if (ret < 0) {
1008 dev_err(&pdev->dev, "rspi_request_dma failed.\n"); 1296 dev_err(&pdev->dev, "rspi_request_dma failed.\n");
@@ -1022,27 +1310,16 @@ static int rspi_probe(struct platform_device *pdev)
1022error3: 1310error3:
1023 rspi_release_dma(rspi); 1311 rspi_release_dma(rspi);
1024error2: 1312error2:
1025 clk_disable(rspi->clk); 1313 pm_runtime_disable(&pdev->dev);
1026error1: 1314error1:
1027 spi_master_put(master); 1315 spi_master_put(master);
1028 1316
1029 return ret; 1317 return ret;
1030} 1318}
1031 1319
1032static struct spi_ops rspi_ops = {
1033 .set_config_register = rspi_set_config_register,
1034 .send_pio = rspi_send_pio,
1035 .receive_pio = rspi_receive_pio,
1036};
1037
1038static struct spi_ops qspi_ops = {
1039 .set_config_register = qspi_set_config_register,
1040 .send_pio = qspi_send_pio,
1041 .receive_pio = qspi_receive_pio,
1042};
1043
1044static struct platform_device_id spi_driver_ids[] = { 1320static struct platform_device_id spi_driver_ids[] = {
1045 { "rspi", (kernel_ulong_t)&rspi_ops }, 1321 { "rspi", (kernel_ulong_t)&rspi_ops },
1322 { "rspi-rz", (kernel_ulong_t)&rspi_rz_ops },
1046 { "qspi", (kernel_ulong_t)&qspi_ops }, 1323 { "qspi", (kernel_ulong_t)&qspi_ops },
1047 {}, 1324 {},
1048}; 1325};
@@ -1056,6 +1333,7 @@ static struct platform_driver rspi_driver = {
1056 .driver = { 1333 .driver = {
1057 .name = "renesas_spi", 1334 .name = "renesas_spi",
1058 .owner = THIS_MODULE, 1335 .owner = THIS_MODULE,
1336 .of_match_table = of_match_ptr(rspi_of_match),
1059 }, 1337 },
1060}; 1338};
1061module_platform_driver(rspi_driver); 1339module_platform_driver(rspi_driver);
diff --git a/drivers/spi/spi-s3c24xx.c b/drivers/spi/spi-s3c24xx.c
index 746424aa5353..bed23384dfab 100644
--- a/drivers/spi/spi-s3c24xx.c
+++ b/drivers/spi/spi-s3c24xx.c
@@ -9,7 +9,6 @@
9 * 9 *
10*/ 10*/
11 11
12#include <linux/init.h>
13#include <linux/spinlock.h> 12#include <linux/spinlock.h>
14#include <linux/workqueue.h> 13#include <linux/workqueue.h>
15#include <linux/interrupt.h> 14#include <linux/interrupt.h>
@@ -123,25 +122,15 @@ static int s3c24xx_spi_update_state(struct spi_device *spi,
123{ 122{
124 struct s3c24xx_spi *hw = to_hw(spi); 123 struct s3c24xx_spi *hw = to_hw(spi);
125 struct s3c24xx_spi_devstate *cs = spi->controller_state; 124 struct s3c24xx_spi_devstate *cs = spi->controller_state;
126 unsigned int bpw;
127 unsigned int hz; 125 unsigned int hz;
128 unsigned int div; 126 unsigned int div;
129 unsigned long clk; 127 unsigned long clk;
130 128
131 bpw = t ? t->bits_per_word : spi->bits_per_word;
132 hz = t ? t->speed_hz : spi->max_speed_hz; 129 hz = t ? t->speed_hz : spi->max_speed_hz;
133 130
134 if (!bpw)
135 bpw = 8;
136
137 if (!hz) 131 if (!hz)
138 hz = spi->max_speed_hz; 132 hz = spi->max_speed_hz;
139 133
140 if (bpw != 8) {
141 dev_err(&spi->dev, "invalid bits-per-word (%d)\n", bpw);
142 return -EINVAL;
143 }
144
145 if (spi->mode != cs->mode) { 134 if (spi->mode != cs->mode) {
146 u8 spcon = SPCON_DEFAULT | S3C2410_SPCON_ENSCK; 135 u8 spcon = SPCON_DEFAULT | S3C2410_SPCON_ENSCK;
147 136
@@ -544,6 +533,7 @@ static int s3c24xx_spi_probe(struct platform_device *pdev)
544 533
545 master->num_chipselect = hw->pdata->num_cs; 534 master->num_chipselect = hw->pdata->num_cs;
546 master->bus_num = pdata->bus_num; 535 master->bus_num = pdata->bus_num;
536 master->bits_per_word_mask = SPI_BPW_MASK(8);
547 537
548 /* setup the state for the bitbang driver */ 538 /* setup the state for the bitbang driver */
549 539
@@ -643,6 +633,11 @@ static int s3c24xx_spi_remove(struct platform_device *dev)
643static int s3c24xx_spi_suspend(struct device *dev) 633static int s3c24xx_spi_suspend(struct device *dev)
644{ 634{
645 struct s3c24xx_spi *hw = dev_get_drvdata(dev); 635 struct s3c24xx_spi *hw = dev_get_drvdata(dev);
636 int ret;
637
638 ret = spi_master_suspend(hw->master);
639 if (ret)
640 return ret;
646 641
647 if (hw->pdata && hw->pdata->gpio_setup) 642 if (hw->pdata && hw->pdata->gpio_setup)
648 hw->pdata->gpio_setup(hw->pdata, 0); 643 hw->pdata->gpio_setup(hw->pdata, 0);
@@ -656,7 +651,7 @@ static int s3c24xx_spi_resume(struct device *dev)
656 struct s3c24xx_spi *hw = dev_get_drvdata(dev); 651 struct s3c24xx_spi *hw = dev_get_drvdata(dev);
657 652
658 s3c24xx_spi_initialsetup(hw); 653 s3c24xx_spi_initialsetup(hw);
659 return 0; 654 return spi_master_resume(hw->master);
660} 655}
661 656
662static const struct dev_pm_ops s3c24xx_spi_pmops = { 657static const struct dev_pm_ops s3c24xx_spi_pmops = {
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index ae907dde1371..f19cd97855e8 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -34,10 +34,6 @@
34 34
35#include <linux/platform_data/spi-s3c64xx.h> 35#include <linux/platform_data/spi-s3c64xx.h>
36 36
37#ifdef CONFIG_S3C_DMA
38#include <mach/dma.h>
39#endif
40
41#define MAX_SPI_PORTS 3 37#define MAX_SPI_PORTS 3
42#define S3C64XX_SPI_QUIRK_POLL (1 << 0) 38#define S3C64XX_SPI_QUIRK_POLL (1 << 0)
43 39
@@ -200,9 +196,6 @@ struct s3c64xx_spi_driver_data {
200 unsigned cur_speed; 196 unsigned cur_speed;
201 struct s3c64xx_spi_dma_data rx_dma; 197 struct s3c64xx_spi_dma_data rx_dma;
202 struct s3c64xx_spi_dma_data tx_dma; 198 struct s3c64xx_spi_dma_data tx_dma;
203#ifdef CONFIG_S3C_DMA
204 struct samsung_dma_ops *ops;
205#endif
206 struct s3c64xx_spi_port_config *port_conf; 199 struct s3c64xx_spi_port_config *port_conf;
207 unsigned int port_id; 200 unsigned int port_id;
208 bool cs_gpio; 201 bool cs_gpio;
@@ -284,104 +277,8 @@ static void s3c64xx_spi_dmacb(void *data)
284 spin_unlock_irqrestore(&sdd->lock, flags); 277 spin_unlock_irqrestore(&sdd->lock, flags);
285} 278}
286 279
287#ifdef CONFIG_S3C_DMA
288/* FIXME: remove this section once arch/arm/mach-s3c64xx uses dmaengine */
289
290static struct s3c2410_dma_client s3c64xx_spi_dma_client = {
291 .name = "samsung-spi-dma",
292};
293
294static void prepare_dma(struct s3c64xx_spi_dma_data *dma,
295 unsigned len, dma_addr_t buf)
296{
297 struct s3c64xx_spi_driver_data *sdd;
298 struct samsung_dma_prep info;
299 struct samsung_dma_config config;
300
301 if (dma->direction == DMA_DEV_TO_MEM) {
302 sdd = container_of((void *)dma,
303 struct s3c64xx_spi_driver_data, rx_dma);
304 config.direction = sdd->rx_dma.direction;
305 config.fifo = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
306 config.width = sdd->cur_bpw / 8;
307 sdd->ops->config((enum dma_ch)sdd->rx_dma.ch, &config);
308 } else {
309 sdd = container_of((void *)dma,
310 struct s3c64xx_spi_driver_data, tx_dma);
311 config.direction = sdd->tx_dma.direction;
312 config.fifo = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
313 config.width = sdd->cur_bpw / 8;
314 sdd->ops->config((enum dma_ch)sdd->tx_dma.ch, &config);
315 }
316
317 info.cap = DMA_SLAVE;
318 info.len = len;
319 info.fp = s3c64xx_spi_dmacb;
320 info.fp_param = dma;
321 info.direction = dma->direction;
322 info.buf = buf;
323
324 sdd->ops->prepare((enum dma_ch)dma->ch, &info);
325 sdd->ops->trigger((enum dma_ch)dma->ch);
326}
327
328static int acquire_dma(struct s3c64xx_spi_driver_data *sdd)
329{
330 struct samsung_dma_req req;
331 struct device *dev = &sdd->pdev->dev;
332
333 sdd->ops = samsung_dma_get_ops();
334
335 req.cap = DMA_SLAVE;
336 req.client = &s3c64xx_spi_dma_client;
337
338 sdd->rx_dma.ch = (struct dma_chan *)(unsigned long)sdd->ops->request(
339 sdd->rx_dma.dmach, &req, dev, "rx");
340 sdd->tx_dma.ch = (struct dma_chan *)(unsigned long)sdd->ops->request(
341 sdd->tx_dma.dmach, &req, dev, "tx");
342
343 return 1;
344}
345
346static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
347{
348 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
349
350 /*
351 * If DMA resource was not available during
352 * probe, no need to continue with dma requests
353 * else Acquire DMA channels
354 */
355 while (!is_polling(sdd) && !acquire_dma(sdd))
356 usleep_range(10000, 11000);
357
358 return 0;
359}
360
361static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi)
362{
363 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
364
365 /* Free DMA channels */
366 if (!is_polling(sdd)) {
367 sdd->ops->release((enum dma_ch)sdd->rx_dma.ch,
368 &s3c64xx_spi_dma_client);
369 sdd->ops->release((enum dma_ch)sdd->tx_dma.ch,
370 &s3c64xx_spi_dma_client);
371 }
372
373 return 0;
374}
375
376static void s3c64xx_spi_dma_stop(struct s3c64xx_spi_driver_data *sdd,
377 struct s3c64xx_spi_dma_data *dma)
378{
379 sdd->ops->stop((enum dma_ch)dma->ch);
380}
381#else
382
383static void prepare_dma(struct s3c64xx_spi_dma_data *dma, 280static void prepare_dma(struct s3c64xx_spi_dma_data *dma,
384 unsigned len, dma_addr_t buf) 281 struct sg_table *sgt)
385{ 282{
386 struct s3c64xx_spi_driver_data *sdd; 283 struct s3c64xx_spi_driver_data *sdd;
387 struct dma_slave_config config; 284 struct dma_slave_config config;
@@ -407,8 +304,8 @@ static void prepare_dma(struct s3c64xx_spi_dma_data *dma,
407 dmaengine_slave_config(dma->ch, &config); 304 dmaengine_slave_config(dma->ch, &config);
408 } 305 }
409 306
410 desc = dmaengine_prep_slave_single(dma->ch, buf, len, 307 desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents,
411 dma->direction, DMA_PREP_INTERRUPT); 308 dma->direction, DMA_PREP_INTERRUPT);
412 309
413 desc->callback = s3c64xx_spi_dmacb; 310 desc->callback = s3c64xx_spi_dmacb;
414 desc->callback_param = dma; 311 desc->callback_param = dma;
@@ -437,6 +334,7 @@ static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
437 ret = -EBUSY; 334 ret = -EBUSY;
438 goto out; 335 goto out;
439 } 336 }
337 spi->dma_rx = sdd->rx_dma.ch;
440 338
441 sdd->tx_dma.ch = dma_request_slave_channel_compat(mask, filter, 339 sdd->tx_dma.ch = dma_request_slave_channel_compat(mask, filter,
442 (void *)sdd->tx_dma.dmach, dev, "tx"); 340 (void *)sdd->tx_dma.dmach, dev, "tx");
@@ -445,6 +343,7 @@ static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
445 ret = -EBUSY; 343 ret = -EBUSY;
446 goto out_rx; 344 goto out_rx;
447 } 345 }
346 spi->dma_tx = sdd->tx_dma.ch;
448 } 347 }
449 348
450 ret = pm_runtime_get_sync(&sdd->pdev->dev); 349 ret = pm_runtime_get_sync(&sdd->pdev->dev);
@@ -477,12 +376,14 @@ static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi)
477 return 0; 376 return 0;
478} 377}
479 378
480static void s3c64xx_spi_dma_stop(struct s3c64xx_spi_driver_data *sdd, 379static bool s3c64xx_spi_can_dma(struct spi_master *master,
481 struct s3c64xx_spi_dma_data *dma) 380 struct spi_device *spi,
381 struct spi_transfer *xfer)
482{ 382{
483 dmaengine_terminate_all(dma->ch); 383 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
384
385 return xfer->len > (FIFO_LVL_MASK(sdd) >> 1) + 1;
484} 386}
485#endif
486 387
487static void enable_datapath(struct s3c64xx_spi_driver_data *sdd, 388static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
488 struct spi_device *spi, 389 struct spi_device *spi,
@@ -515,7 +416,7 @@ static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
515 chcfg |= S3C64XX_SPI_CH_TXCH_ON; 416 chcfg |= S3C64XX_SPI_CH_TXCH_ON;
516 if (dma_mode) { 417 if (dma_mode) {
517 modecfg |= S3C64XX_SPI_MODE_TXDMA_ON; 418 modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
518 prepare_dma(&sdd->tx_dma, xfer->len, xfer->tx_dma); 419 prepare_dma(&sdd->tx_dma, &xfer->tx_sg);
519 } else { 420 } else {
520 switch (sdd->cur_bpw) { 421 switch (sdd->cur_bpw) {
521 case 32: 422 case 32:
@@ -547,7 +448,7 @@ static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
547 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) 448 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
548 | S3C64XX_SPI_PACKET_CNT_EN, 449 | S3C64XX_SPI_PACKET_CNT_EN,
549 regs + S3C64XX_SPI_PACKET_CNT); 450 regs + S3C64XX_SPI_PACKET_CNT);
550 prepare_dma(&sdd->rx_dma, xfer->len, xfer->rx_dma); 451 prepare_dma(&sdd->rx_dma, &xfer->rx_sg);
551 } 452 }
552 } 453 }
553 454
@@ -555,23 +456,6 @@ static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
555 writel(chcfg, regs + S3C64XX_SPI_CH_CFG); 456 writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
556} 457}
557 458
558static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd,
559 struct spi_device *spi)
560{
561 if (sdd->tgl_spi != NULL) { /* If last device toggled after mssg */
562 if (sdd->tgl_spi != spi) { /* if last mssg on diff device */
563 /* Deselect the last toggled device */
564 if (spi->cs_gpio >= 0)
565 gpio_set_value(spi->cs_gpio,
566 spi->mode & SPI_CS_HIGH ? 0 : 1);
567 }
568 sdd->tgl_spi = NULL;
569 }
570
571 if (spi->cs_gpio >= 0)
572 gpio_set_value(spi->cs_gpio, spi->mode & SPI_CS_HIGH ? 1 : 0);
573}
574
575static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd, 459static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd,
576 int timeout_ms) 460 int timeout_ms)
577{ 461{
@@ -593,112 +477,111 @@ static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd,
593 return RX_FIFO_LVL(status, sdd); 477 return RX_FIFO_LVL(status, sdd);
594} 478}
595 479
596static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd, 480static int wait_for_dma(struct s3c64xx_spi_driver_data *sdd,
597 struct spi_transfer *xfer, int dma_mode) 481 struct spi_transfer *xfer)
598{ 482{
599 void __iomem *regs = sdd->regs; 483 void __iomem *regs = sdd->regs;
600 unsigned long val; 484 unsigned long val;
485 u32 status;
601 int ms; 486 int ms;
602 487
603 /* millisecs to xfer 'len' bytes @ 'cur_speed' */ 488 /* millisecs to xfer 'len' bytes @ 'cur_speed' */
604 ms = xfer->len * 8 * 1000 / sdd->cur_speed; 489 ms = xfer->len * 8 * 1000 / sdd->cur_speed;
605 ms += 10; /* some tolerance */ 490 ms += 10; /* some tolerance */
606 491
607 if (dma_mode) { 492 val = msecs_to_jiffies(ms) + 10;
608 val = msecs_to_jiffies(ms) + 10; 493 val = wait_for_completion_timeout(&sdd->xfer_completion, val);
609 val = wait_for_completion_timeout(&sdd->xfer_completion, val); 494
610 } else { 495 /*
611 u32 status; 496 * If the previous xfer was completed within timeout, then
612 val = msecs_to_loops(ms); 497 * proceed further else return -EIO.
613 do { 498 * DmaTx returns after simply writing data in the FIFO,
499 * w/o waiting for real transmission on the bus to finish.
500 * DmaRx returns only after Dma read data from FIFO which
501 * needs bus transmission to finish, so we don't worry if
502 * Xfer involved Rx(with or without Tx).
503 */
504 if (val && !xfer->rx_buf) {
505 val = msecs_to_loops(10);
506 status = readl(regs + S3C64XX_SPI_STATUS);
507 while ((TX_FIFO_LVL(status, sdd)
508 || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
509 && --val) {
510 cpu_relax();
614 status = readl(regs + S3C64XX_SPI_STATUS); 511 status = readl(regs + S3C64XX_SPI_STATUS);
615 } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val); 512 }
513
616 } 514 }
617 515
618 if (dma_mode) { 516 /* If timed out while checking rx/tx status return error */
619 u32 status; 517 if (!val)
620 518 return -EIO;
621 /*
622 * If the previous xfer was completed within timeout, then
623 * proceed further else return -EIO.
624 * DmaTx returns after simply writing data in the FIFO,
625 * w/o waiting for real transmission on the bus to finish.
626 * DmaRx returns only after Dma read data from FIFO which
627 * needs bus transmission to finish, so we don't worry if
628 * Xfer involved Rx(with or without Tx).
629 */
630 if (val && !xfer->rx_buf) {
631 val = msecs_to_loops(10);
632 status = readl(regs + S3C64XX_SPI_STATUS);
633 while ((TX_FIFO_LVL(status, sdd)
634 || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
635 && --val) {
636 cpu_relax();
637 status = readl(regs + S3C64XX_SPI_STATUS);
638 }
639 519
640 } 520 return 0;
521}
641 522
642 /* If timed out while checking rx/tx status return error */ 523static int wait_for_pio(struct s3c64xx_spi_driver_data *sdd,
643 if (!val) 524 struct spi_transfer *xfer)
644 return -EIO; 525{
645 } else { 526 void __iomem *regs = sdd->regs;
646 int loops; 527 unsigned long val;
647 u32 cpy_len; 528 u32 status;
648 u8 *buf; 529 int loops;
649 530 u32 cpy_len;
650 /* If it was only Tx */ 531 u8 *buf;
651 if (!xfer->rx_buf) { 532 int ms;
652 sdd->state &= ~TXBUSY;
653 return 0;
654 }
655 533
656 /* 534 /* millisecs to xfer 'len' bytes @ 'cur_speed' */
657 * If the receive length is bigger than the controller fifo 535 ms = xfer->len * 8 * 1000 / sdd->cur_speed;
658 * size, calculate the loops and read the fifo as many times. 536 ms += 10; /* some tolerance */
659 * loops = length / max fifo size (calculated by using the
660 * fifo mask).
661 * For any size less than the fifo size the below code is
662 * executed atleast once.
663 */
664 loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1);
665 buf = xfer->rx_buf;
666 do {
667 /* wait for data to be received in the fifo */
668 cpy_len = s3c64xx_spi_wait_for_timeout(sdd,
669 (loops ? ms : 0));
670 537
671 switch (sdd->cur_bpw) { 538 val = msecs_to_loops(ms);
672 case 32: 539 do {
673 ioread32_rep(regs + S3C64XX_SPI_RX_DATA, 540 status = readl(regs + S3C64XX_SPI_STATUS);
674 buf, cpy_len / 4); 541 } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
675 break;
676 case 16:
677 ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
678 buf, cpy_len / 2);
679 break;
680 default:
681 ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
682 buf, cpy_len);
683 break;
684 }
685 542
686 buf = buf + cpy_len; 543
687 } while (loops--); 544 /* If it was only Tx */
688 sdd->state &= ~RXBUSY; 545 if (!xfer->rx_buf) {
546 sdd->state &= ~TXBUSY;
547 return 0;
689 } 548 }
690 549
691 return 0; 550 /*
692} 551 * If the receive length is bigger than the controller fifo
552 * size, calculate the loops and read the fifo as many times.
553 * loops = length / max fifo size (calculated by using the
554 * fifo mask).
555 * For any size less than the fifo size the below code is
556 * executed atleast once.
557 */
558 loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1);
559 buf = xfer->rx_buf;
560 do {
561 /* wait for data to be received in the fifo */
562 cpy_len = s3c64xx_spi_wait_for_timeout(sdd,
563 (loops ? ms : 0));
564
565 switch (sdd->cur_bpw) {
566 case 32:
567 ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
568 buf, cpy_len / 4);
569 break;
570 case 16:
571 ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
572 buf, cpy_len / 2);
573 break;
574 default:
575 ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
576 buf, cpy_len);
577 break;
578 }
693 579
694static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd, 580 buf = buf + cpy_len;
695 struct spi_device *spi) 581 } while (loops--);
696{ 582 sdd->state &= ~RXBUSY;
697 if (sdd->tgl_spi == spi)
698 sdd->tgl_spi = NULL;
699 583
700 if (spi->cs_gpio >= 0) 584 return 0;
701 gpio_set_value(spi->cs_gpio, spi->mode & SPI_CS_HIGH ? 0 : 1);
702} 585}
703 586
704static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) 587static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
@@ -774,81 +657,6 @@ static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
774 657
775#define XFER_DMAADDR_INVALID DMA_BIT_MASK(32) 658#define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
776 659
777static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd,
778 struct spi_message *msg)
779{
780 struct device *dev = &sdd->pdev->dev;
781 struct spi_transfer *xfer;
782
783 if (is_polling(sdd) || msg->is_dma_mapped)
784 return 0;
785
786 /* First mark all xfer unmapped */
787 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
788 xfer->rx_dma = XFER_DMAADDR_INVALID;
789 xfer->tx_dma = XFER_DMAADDR_INVALID;
790 }
791
792 /* Map until end or first fail */
793 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
794
795 if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
796 continue;
797
798 if (xfer->tx_buf != NULL) {
799 xfer->tx_dma = dma_map_single(dev,
800 (void *)xfer->tx_buf, xfer->len,
801 DMA_TO_DEVICE);
802 if (dma_mapping_error(dev, xfer->tx_dma)) {
803 dev_err(dev, "dma_map_single Tx failed\n");
804 xfer->tx_dma = XFER_DMAADDR_INVALID;
805 return -ENOMEM;
806 }
807 }
808
809 if (xfer->rx_buf != NULL) {
810 xfer->rx_dma = dma_map_single(dev, xfer->rx_buf,
811 xfer->len, DMA_FROM_DEVICE);
812 if (dma_mapping_error(dev, xfer->rx_dma)) {
813 dev_err(dev, "dma_map_single Rx failed\n");
814 dma_unmap_single(dev, xfer->tx_dma,
815 xfer->len, DMA_TO_DEVICE);
816 xfer->tx_dma = XFER_DMAADDR_INVALID;
817 xfer->rx_dma = XFER_DMAADDR_INVALID;
818 return -ENOMEM;
819 }
820 }
821 }
822
823 return 0;
824}
825
826static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd,
827 struct spi_message *msg)
828{
829 struct device *dev = &sdd->pdev->dev;
830 struct spi_transfer *xfer;
831
832 if (is_polling(sdd) || msg->is_dma_mapped)
833 return;
834
835 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
836
837 if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
838 continue;
839
840 if (xfer->rx_buf != NULL
841 && xfer->rx_dma != XFER_DMAADDR_INVALID)
842 dma_unmap_single(dev, xfer->rx_dma,
843 xfer->len, DMA_FROM_DEVICE);
844
845 if (xfer->tx_buf != NULL
846 && xfer->tx_dma != XFER_DMAADDR_INVALID)
847 dma_unmap_single(dev, xfer->tx_dma,
848 xfer->len, DMA_TO_DEVICE);
849 }
850}
851
852static int s3c64xx_spi_prepare_message(struct spi_master *master, 660static int s3c64xx_spi_prepare_message(struct spi_master *master,
853 struct spi_message *msg) 661 struct spi_message *msg)
854{ 662{
@@ -866,13 +674,6 @@ static int s3c64xx_spi_prepare_message(struct spi_master *master,
866 s3c64xx_spi_config(sdd); 674 s3c64xx_spi_config(sdd);
867 } 675 }
868 676
869 /* Map all the transfers if needed */
870 if (s3c64xx_spi_map_mssg(sdd, msg)) {
871 dev_err(&spi->dev,
872 "Xfer: Unable to map message buffers!\n");
873 return -ENOMEM;
874 }
875
876 /* Configure feedback delay */ 677 /* Configure feedback delay */
877 writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK); 678 writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
878 679
@@ -896,13 +697,6 @@ static int s3c64xx_spi_transfer_one(struct spi_master *master,
896 bpw = xfer->bits_per_word; 697 bpw = xfer->bits_per_word;
897 speed = xfer->speed_hz ? : spi->max_speed_hz; 698 speed = xfer->speed_hz ? : spi->max_speed_hz;
898 699
899 if (xfer->len % (bpw / 8)) {
900 dev_err(&spi->dev,
901 "Xfer length(%u) not a multiple of word size(%u)\n",
902 xfer->len, bpw / 8);
903 return -EIO;
904 }
905
906 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) { 700 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
907 sdd->cur_bpw = bpw; 701 sdd->cur_bpw = bpw;
908 sdd->cur_speed = speed; 702 sdd->cur_speed = speed;
@@ -929,7 +723,10 @@ static int s3c64xx_spi_transfer_one(struct spi_master *master,
929 723
930 spin_unlock_irqrestore(&sdd->lock, flags); 724 spin_unlock_irqrestore(&sdd->lock, flags);
931 725
932 status = wait_for_xfer(sdd, xfer, use_dma); 726 if (use_dma)
727 status = wait_for_dma(sdd, xfer);
728 else
729 status = wait_for_pio(sdd, xfer);
933 730
934 if (status) { 731 if (status) {
935 dev_err(&spi->dev, "I/O Error: rx-%d tx-%d res:rx-%c tx-%c len-%d\n", 732 dev_err(&spi->dev, "I/O Error: rx-%d tx-%d res:rx-%c tx-%c len-%d\n",
@@ -941,10 +738,10 @@ static int s3c64xx_spi_transfer_one(struct spi_master *master,
941 if (use_dma) { 738 if (use_dma) {
942 if (xfer->tx_buf != NULL 739 if (xfer->tx_buf != NULL
943 && (sdd->state & TXBUSY)) 740 && (sdd->state & TXBUSY))
944 s3c64xx_spi_dma_stop(sdd, &sdd->tx_dma); 741 dmaengine_terminate_all(sdd->tx_dma.ch);
945 if (xfer->rx_buf != NULL 742 if (xfer->rx_buf != NULL
946 && (sdd->state & RXBUSY)) 743 && (sdd->state & RXBUSY))
947 s3c64xx_spi_dma_stop(sdd, &sdd->rx_dma); 744 dmaengine_terminate_all(sdd->rx_dma.ch);
948 } 745 }
949 } else { 746 } else {
950 flush_fifo(sdd); 747 flush_fifo(sdd);
@@ -953,16 +750,6 @@ static int s3c64xx_spi_transfer_one(struct spi_master *master,
953 return status; 750 return status;
954} 751}
955 752
956static int s3c64xx_spi_unprepare_message(struct spi_master *master,
957 struct spi_message *msg)
958{
959 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
960
961 s3c64xx_spi_unmap_mssg(sdd, msg);
962
963 return 0;
964}
965
966static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata( 753static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
967 struct spi_device *spi) 754 struct spi_device *spi)
968{ 755{
@@ -1092,14 +879,12 @@ static int s3c64xx_spi_setup(struct spi_device *spi)
1092 879
1093 pm_runtime_put(&sdd->pdev->dev); 880 pm_runtime_put(&sdd->pdev->dev);
1094 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL); 881 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
1095 disable_cs(sdd, spi);
1096 return 0; 882 return 0;
1097 883
1098setup_exit: 884setup_exit:
1099 pm_runtime_put(&sdd->pdev->dev); 885 pm_runtime_put(&sdd->pdev->dev);
1100 /* setup() returns with device de-selected */ 886 /* setup() returns with device de-selected */
1101 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL); 887 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
1102 disable_cs(sdd, spi);
1103 888
1104 gpio_free(cs->line); 889 gpio_free(cs->line);
1105 spi_set_ctldata(spi, NULL); 890 spi_set_ctldata(spi, NULL);
@@ -1338,7 +1123,6 @@ static int s3c64xx_spi_probe(struct platform_device *pdev)
1338 master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer; 1123 master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
1339 master->prepare_message = s3c64xx_spi_prepare_message; 1124 master->prepare_message = s3c64xx_spi_prepare_message;
1340 master->transfer_one = s3c64xx_spi_transfer_one; 1125 master->transfer_one = s3c64xx_spi_transfer_one;
1341 master->unprepare_message = s3c64xx_spi_unprepare_message;
1342 master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer; 1126 master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer;
1343 master->num_chipselect = sci->num_cs; 1127 master->num_chipselect = sci->num_cs;
1344 master->dma_alignment = 8; 1128 master->dma_alignment = 8;
@@ -1347,6 +1131,8 @@ static int s3c64xx_spi_probe(struct platform_device *pdev)
1347 /* the spi->mode bits understood by this driver: */ 1131 /* the spi->mode bits understood by this driver: */
1348 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 1132 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1349 master->auto_runtime_pm = true; 1133 master->auto_runtime_pm = true;
1134 if (!is_polling(sdd))
1135 master->can_dma = s3c64xx_spi_can_dma;
1350 1136
1351 sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res); 1137 sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res);
1352 if (IS_ERR(sdd->regs)) { 1138 if (IS_ERR(sdd->regs)) {
diff --git a/drivers/spi/spi-sc18is602.c b/drivers/spi/spi-sc18is602.c
index 121c2e1dea36..237f2e7a7179 100644
--- a/drivers/spi/spi-sc18is602.c
+++ b/drivers/spi/spi-sc18is602.c
@@ -183,17 +183,9 @@ static int sc18is602_setup_transfer(struct sc18is602 *hw, u32 hz, u8 mode)
183static int sc18is602_check_transfer(struct spi_device *spi, 183static int sc18is602_check_transfer(struct spi_device *spi,
184 struct spi_transfer *t, int tlen) 184 struct spi_transfer *t, int tlen)
185{ 185{
186 uint32_t hz;
187
188 if (t && t->len + tlen > SC18IS602_BUFSIZ) 186 if (t && t->len + tlen > SC18IS602_BUFSIZ)
189 return -EINVAL; 187 return -EINVAL;
190 188
191 hz = spi->max_speed_hz;
192 if (t && t->speed_hz)
193 hz = t->speed_hz;
194 if (hz == 0)
195 return -EINVAL;
196
197 return 0; 189 return 0;
198} 190}
199 191
@@ -205,22 +197,15 @@ static int sc18is602_transfer_one(struct spi_master *master,
205 struct spi_transfer *t; 197 struct spi_transfer *t;
206 int status = 0; 198 int status = 0;
207 199
208 /* SC18IS602 does not support CS2 */
209 if (hw->id == sc18is602 && spi->chip_select == 2) {
210 status = -ENXIO;
211 goto error;
212 }
213
214 hw->tlen = 0; 200 hw->tlen = 0;
215 list_for_each_entry(t, &m->transfers, transfer_list) { 201 list_for_each_entry(t, &m->transfers, transfer_list) {
216 u32 hz = t->speed_hz ? : spi->max_speed_hz;
217 bool do_transfer; 202 bool do_transfer;
218 203
219 status = sc18is602_check_transfer(spi, t, hw->tlen); 204 status = sc18is602_check_transfer(spi, t, hw->tlen);
220 if (status < 0) 205 if (status < 0)
221 break; 206 break;
222 207
223 status = sc18is602_setup_transfer(hw, hz, spi->mode); 208 status = sc18is602_setup_transfer(hw, t->speed_hz, spi->mode);
224 if (status < 0) 209 if (status < 0)
225 break; 210 break;
226 211
@@ -238,7 +223,6 @@ static int sc18is602_transfer_one(struct spi_master *master,
238 if (t->delay_usecs) 223 if (t->delay_usecs)
239 udelay(t->delay_usecs); 224 udelay(t->delay_usecs);
240 } 225 }
241error:
242 m->status = status; 226 m->status = status;
243 spi_finalize_current_message(master); 227 spi_finalize_current_message(master);
244 228
@@ -247,10 +231,13 @@ error:
247 231
248static int sc18is602_setup(struct spi_device *spi) 232static int sc18is602_setup(struct spi_device *spi)
249{ 233{
250 if (spi->mode & ~(SPI_CPHA | SPI_CPOL | SPI_LSB_FIRST)) 234 struct sc18is602 *hw = spi_master_get_devdata(spi->master);
251 return -EINVAL;
252 235
253 return sc18is602_check_transfer(spi, NULL, 0); 236 /* SC18IS602 does not support CS2 */
237 if (hw->id == sc18is602 && spi->chip_select == 2)
238 return -ENXIO;
239
240 return 0;
254} 241}
255 242
256static int sc18is602_probe(struct i2c_client *client, 243static int sc18is602_probe(struct i2c_client *client,
@@ -309,6 +296,8 @@ static int sc18is602_probe(struct i2c_client *client,
309 master->setup = sc18is602_setup; 296 master->setup = sc18is602_setup;
310 master->transfer_one_message = sc18is602_transfer_one; 297 master->transfer_one_message = sc18is602_transfer_one;
311 master->dev.of_node = np; 298 master->dev.of_node = np;
299 master->min_speed_hz = hw->freq / 128;
300 master->max_speed_hz = hw->freq / 4;
312 301
313 error = devm_spi_register_master(dev, master); 302 error = devm_spi_register_master(dev, master);
314 if (error) 303 if (error)
diff --git a/drivers/spi/spi-sh-hspi.c b/drivers/spi/spi-sh-hspi.c
index 82d2f922ffa0..9009456bdf4d 100644
--- a/drivers/spi/spi-sh-hspi.c
+++ b/drivers/spi/spi-sh-hspi.c
@@ -46,8 +46,6 @@
46/* SPSR */ 46/* SPSR */
47#define RXFL (1 << 2) 47#define RXFL (1 << 2)
48 48
49#define hspi2info(h) (h->dev->platform_data)
50
51struct hspi_priv { 49struct hspi_priv {
52 void __iomem *addr; 50 void __iomem *addr;
53 struct spi_master *master; 51 struct spi_master *master;
@@ -113,14 +111,9 @@ static void hspi_hw_setup(struct hspi_priv *hspi,
113{ 111{
114 struct spi_device *spi = msg->spi; 112 struct spi_device *spi = msg->spi;
115 struct device *dev = hspi->dev; 113 struct device *dev = hspi->dev;
116 u32 target_rate;
117 u32 spcr, idiv_clk; 114 u32 spcr, idiv_clk;
118 u32 rate, best_rate, min, tmp; 115 u32 rate, best_rate, min, tmp;
119 116
120 target_rate = t ? t->speed_hz : 0;
121 if (!target_rate)
122 target_rate = spi->max_speed_hz;
123
124 /* 117 /*
125 * find best IDIV/CLKCx settings 118 * find best IDIV/CLKCx settings
126 */ 119 */
@@ -140,7 +133,7 @@ static void hspi_hw_setup(struct hspi_priv *hspi,
140 rate /= (((idiv_clk & 0x1F) + 1) * 2); 133 rate /= (((idiv_clk & 0x1F) + 1) * 2);
141 134
142 /* save best settings */ 135 /* save best settings */
143 tmp = abs(target_rate - rate); 136 tmp = abs(t->speed_hz - rate);
144 if (tmp < min) { 137 if (tmp < min) {
145 min = tmp; 138 min = tmp;
146 spcr = idiv_clk; 139 spcr = idiv_clk;
@@ -153,7 +146,7 @@ static void hspi_hw_setup(struct hspi_priv *hspi,
153 if (spi->mode & SPI_CPOL) 146 if (spi->mode & SPI_CPOL)
154 spcr |= 1 << 6; 147 spcr |= 1 << 6;
155 148
156 dev_dbg(dev, "speed %d/%d\n", target_rate, best_rate); 149 dev_dbg(dev, "speed %d/%d\n", t->speed_hz, best_rate);
157 150
158 hspi_write(hspi, SPCR, spcr); 151 hspi_write(hspi, SPCR, spcr);
159 hspi_write(hspi, SPSR, 0x0); 152 hspi_write(hspi, SPSR, 0x0);
@@ -230,29 +223,6 @@ static int hspi_transfer_one_message(struct spi_master *master,
230 return ret; 223 return ret;
231} 224}
232 225
233static int hspi_setup(struct spi_device *spi)
234{
235 struct hspi_priv *hspi = spi_master_get_devdata(spi->master);
236 struct device *dev = hspi->dev;
237
238 if (8 != spi->bits_per_word) {
239 dev_err(dev, "bits_per_word should be 8\n");
240 return -EIO;
241 }
242
243 dev_dbg(dev, "%s setup\n", spi->modalias);
244
245 return 0;
246}
247
248static void hspi_cleanup(struct spi_device *spi)
249{
250 struct hspi_priv *hspi = spi_master_get_devdata(spi->master);
251 struct device *dev = hspi->dev;
252
253 dev_dbg(dev, "%s cleanup\n", spi->modalias);
254}
255
256static int hspi_probe(struct platform_device *pdev) 226static int hspi_probe(struct platform_device *pdev)
257{ 227{
258 struct resource *res; 228 struct resource *res;
@@ -298,22 +268,23 @@ static int hspi_probe(struct platform_device *pdev)
298 268
299 pm_runtime_enable(&pdev->dev); 269 pm_runtime_enable(&pdev->dev);
300 270
301 master->num_chipselect = 1;
302 master->bus_num = pdev->id; 271 master->bus_num = pdev->id;
303 master->setup = hspi_setup;
304 master->cleanup = hspi_cleanup;
305 master->mode_bits = SPI_CPOL | SPI_CPHA; 272 master->mode_bits = SPI_CPOL | SPI_CPHA;
306 master->dev.of_node = pdev->dev.of_node; 273 master->dev.of_node = pdev->dev.of_node;
307 master->auto_runtime_pm = true; 274 master->auto_runtime_pm = true;
308 master->transfer_one_message = hspi_transfer_one_message; 275 master->transfer_one_message = hspi_transfer_one_message;
276 master->bits_per_word_mask = SPI_BPW_MASK(8);
277
309 ret = devm_spi_register_master(&pdev->dev, master); 278 ret = devm_spi_register_master(&pdev->dev, master);
310 if (ret < 0) { 279 if (ret < 0) {
311 dev_err(&pdev->dev, "spi_register_master error.\n"); 280 dev_err(&pdev->dev, "spi_register_master error.\n");
312 goto error1; 281 goto error2;
313 } 282 }
314 283
315 return 0; 284 return 0;
316 285
286 error2:
287 pm_runtime_disable(&pdev->dev);
317 error1: 288 error1:
318 clk_put(clk); 289 clk_put(clk);
319 error0: 290 error0:
diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c
index 81cc02f5f9b0..e850d03e7190 100644
--- a/drivers/spi/spi-sh-msiof.c
+++ b/drivers/spi/spi-sh-msiof.c
@@ -15,59 +15,108 @@
15#include <linux/delay.h> 15#include <linux/delay.h>
16#include <linux/err.h> 16#include <linux/err.h>
17#include <linux/gpio.h> 17#include <linux/gpio.h>
18#include <linux/init.h>
19#include <linux/interrupt.h> 18#include <linux/interrupt.h>
20#include <linux/io.h> 19#include <linux/io.h>
21#include <linux/kernel.h> 20#include <linux/kernel.h>
22#include <linux/module.h> 21#include <linux/module.h>
23#include <linux/of.h> 22#include <linux/of.h>
23#include <linux/of_device.h>
24#include <linux/platform_device.h> 24#include <linux/platform_device.h>
25#include <linux/pm_runtime.h> 25#include <linux/pm_runtime.h>
26 26
27#include <linux/spi/sh_msiof.h> 27#include <linux/spi/sh_msiof.h>
28#include <linux/spi/spi.h> 28#include <linux/spi/spi.h>
29#include <linux/spi/spi_bitbang.h>
30 29
31#include <asm/unaligned.h> 30#include <asm/unaligned.h>
32 31
32
33struct sh_msiof_chipdata {
34 u16 tx_fifo_size;
35 u16 rx_fifo_size;
36 u16 master_flags;
37};
38
33struct sh_msiof_spi_priv { 39struct sh_msiof_spi_priv {
34 struct spi_bitbang bitbang; /* must be first for spi_bitbang.c */
35 void __iomem *mapbase; 40 void __iomem *mapbase;
36 struct clk *clk; 41 struct clk *clk;
37 struct platform_device *pdev; 42 struct platform_device *pdev;
43 const struct sh_msiof_chipdata *chipdata;
38 struct sh_msiof_spi_info *info; 44 struct sh_msiof_spi_info *info;
39 struct completion done; 45 struct completion done;
40 unsigned long flags;
41 int tx_fifo_size; 46 int tx_fifo_size;
42 int rx_fifo_size; 47 int rx_fifo_size;
43}; 48};
44 49
45#define TMDR1 0x00 50#define TMDR1 0x00 /* Transmit Mode Register 1 */
46#define TMDR2 0x04 51#define TMDR2 0x04 /* Transmit Mode Register 2 */
47#define TMDR3 0x08 52#define TMDR3 0x08 /* Transmit Mode Register 3 */
48#define RMDR1 0x10 53#define RMDR1 0x10 /* Receive Mode Register 1 */
49#define RMDR2 0x14 54#define RMDR2 0x14 /* Receive Mode Register 2 */
50#define RMDR3 0x18 55#define RMDR3 0x18 /* Receive Mode Register 3 */
51#define TSCR 0x20 56#define TSCR 0x20 /* Transmit Clock Select Register */
52#define RSCR 0x22 57#define RSCR 0x22 /* Receive Clock Select Register (SH, A1, APE6) */
53#define CTR 0x28 58#define CTR 0x28 /* Control Register */
54#define FCTR 0x30 59#define FCTR 0x30 /* FIFO Control Register */
55#define STR 0x40 60#define STR 0x40 /* Status Register */
56#define IER 0x44 61#define IER 0x44 /* Interrupt Enable Register */
57#define TDR1 0x48 62#define TDR1 0x48 /* Transmit Control Data Register 1 (SH, A1) */
58#define TDR2 0x4c 63#define TDR2 0x4c /* Transmit Control Data Register 2 (SH, A1) */
59#define TFDR 0x50 64#define TFDR 0x50 /* Transmit FIFO Data Register */
60#define RDR1 0x58 65#define RDR1 0x58 /* Receive Control Data Register 1 (SH, A1) */
61#define RDR2 0x5c 66#define RDR2 0x5c /* Receive Control Data Register 2 (SH, A1) */
62#define RFDR 0x60 67#define RFDR 0x60 /* Receive FIFO Data Register */
63 68
64#define CTR_TSCKE (1 << 15) 69/* TMDR1 and RMDR1 */
65#define CTR_TFSE (1 << 14) 70#define MDR1_TRMD 0x80000000 /* Transfer Mode (1 = Master mode) */
66#define CTR_TXE (1 << 9) 71#define MDR1_SYNCMD_MASK 0x30000000 /* SYNC Mode */
67#define CTR_RXE (1 << 8) 72#define MDR1_SYNCMD_SPI 0x20000000 /* Level mode/SPI */
68 73#define MDR1_SYNCMD_LR 0x30000000 /* L/R mode */
69#define STR_TEOF (1 << 23) 74#define MDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */
70#define STR_REOF (1 << 7) 75#define MDR1_BITLSB_SHIFT 24 /* MSB/LSB First (1 = LSB first) */
76#define MDR1_FLD_MASK 0x000000c0 /* Frame Sync Signal Interval (0-3) */
77#define MDR1_FLD_SHIFT 2
78#define MDR1_XXSTP 0x00000001 /* Transmission/Reception Stop on FIFO */
79/* TMDR1 */
80#define TMDR1_PCON 0x40000000 /* Transfer Signal Connection */
81
82/* TMDR2 and RMDR2 */
83#define MDR2_BITLEN1(i) (((i) - 1) << 24) /* Data Size (8-32 bits) */
84#define MDR2_WDLEN1(i) (((i) - 1) << 16) /* Word Count (1-64/256 (SH, A1))) */
85#define MDR2_GRPMASK1 0x00000001 /* Group Output Mask 1 (SH, A1) */
86
87/* TSCR and RSCR */
88#define SCR_BRPS_MASK 0x1f00 /* Prescaler Setting (1-32) */
89#define SCR_BRPS(i) (((i) - 1) << 8)
90#define SCR_BRDV_MASK 0x0007 /* Baud Rate Generator's Division Ratio */
91#define SCR_BRDV_DIV_2 0x0000
92#define SCR_BRDV_DIV_4 0x0001
93#define SCR_BRDV_DIV_8 0x0002
94#define SCR_BRDV_DIV_16 0x0003
95#define SCR_BRDV_DIV_32 0x0004
96#define SCR_BRDV_DIV_1 0x0007
97
98/* CTR */
99#define CTR_TSCKIZ_MASK 0xc0000000 /* Transmit Clock I/O Polarity Select */
100#define CTR_TSCKIZ_SCK 0x80000000 /* Disable SCK when TX disabled */
101#define CTR_TSCKIZ_POL_SHIFT 30 /* Transmit Clock Polarity */
102#define CTR_RSCKIZ_MASK 0x30000000 /* Receive Clock Polarity Select */
103#define CTR_RSCKIZ_SCK 0x20000000 /* Must match CTR_TSCKIZ_SCK */
104#define CTR_RSCKIZ_POL_SHIFT 28 /* Receive Clock Polarity */
105#define CTR_TEDG_SHIFT 27 /* Transmit Timing (1 = falling edge) */
106#define CTR_REDG_SHIFT 26 /* Receive Timing (1 = falling edge) */
107#define CTR_TXDIZ_MASK 0x00c00000 /* Pin Output When TX is Disabled */
108#define CTR_TXDIZ_LOW 0x00000000 /* 0 */
109#define CTR_TXDIZ_HIGH 0x00400000 /* 1 */
110#define CTR_TXDIZ_HIZ 0x00800000 /* High-impedance */
111#define CTR_TSCKE 0x00008000 /* Transmit Serial Clock Output Enable */
112#define CTR_TFSE 0x00004000 /* Transmit Frame Sync Signal Output Enable */
113#define CTR_TXE 0x00000200 /* Transmit Enable */
114#define CTR_RXE 0x00000100 /* Receive Enable */
115
116/* STR and IER */
117#define STR_TEOF 0x00800000 /* Frame Transmission End */
118#define STR_REOF 0x00000080 /* Frame Reception End */
119
71 120
72static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs) 121static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs)
73{ 122{
@@ -131,22 +180,21 @@ static struct {
131 unsigned short div; 180 unsigned short div;
132 unsigned short scr; 181 unsigned short scr;
133} const sh_msiof_spi_clk_table[] = { 182} const sh_msiof_spi_clk_table[] = {
134 { 1, 0x0007 }, 183 { 1, SCR_BRPS( 1) | SCR_BRDV_DIV_1 },
135 { 2, 0x0000 }, 184 { 2, SCR_BRPS( 1) | SCR_BRDV_DIV_2 },
136 { 4, 0x0001 }, 185 { 4, SCR_BRPS( 1) | SCR_BRDV_DIV_4 },
137 { 8, 0x0002 }, 186 { 8, SCR_BRPS( 1) | SCR_BRDV_DIV_8 },
138 { 16, 0x0003 }, 187 { 16, SCR_BRPS( 1) | SCR_BRDV_DIV_16 },
139 { 32, 0x0004 }, 188 { 32, SCR_BRPS( 1) | SCR_BRDV_DIV_32 },
140 { 64, 0x1f00 }, 189 { 64, SCR_BRPS(32) | SCR_BRDV_DIV_2 },
141 { 128, 0x1f01 }, 190 { 128, SCR_BRPS(32) | SCR_BRDV_DIV_4 },
142 { 256, 0x1f02 }, 191 { 256, SCR_BRPS(32) | SCR_BRDV_DIV_8 },
143 { 512, 0x1f03 }, 192 { 512, SCR_BRPS(32) | SCR_BRDV_DIV_16 },
144 { 1024, 0x1f04 }, 193 { 1024, SCR_BRPS(32) | SCR_BRDV_DIV_32 },
145}; 194};
146 195
147static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p, 196static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
148 unsigned long parent_rate, 197 unsigned long parent_rate, u32 spi_hz)
149 unsigned long spi_hz)
150{ 198{
151 unsigned long div = 1024; 199 unsigned long div = 1024;
152 size_t k; 200 size_t k;
@@ -164,7 +212,8 @@ static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
164 k = min_t(int, k, ARRAY_SIZE(sh_msiof_spi_clk_table) - 1); 212 k = min_t(int, k, ARRAY_SIZE(sh_msiof_spi_clk_table) - 1);
165 213
166 sh_msiof_write(p, TSCR, sh_msiof_spi_clk_table[k].scr); 214 sh_msiof_write(p, TSCR, sh_msiof_spi_clk_table[k].scr);
167 sh_msiof_write(p, RSCR, sh_msiof_spi_clk_table[k].scr); 215 if (!(p->chipdata->master_flags & SPI_MASTER_MUST_TX))
216 sh_msiof_write(p, RSCR, sh_msiof_spi_clk_table[k].scr);
168} 217}
169 218
170static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, 219static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p,
@@ -183,21 +232,25 @@ static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p,
183 */ 232 */
184 sh_msiof_write(p, FCTR, 0); 233 sh_msiof_write(p, FCTR, 0);
185 234
186 tmp = 0; 235 tmp = MDR1_SYNCMD_SPI | 1 << MDR1_FLD_SHIFT | MDR1_XXSTP;
187 tmp |= !cs_high << 25; 236 tmp |= !cs_high << MDR1_SYNCAC_SHIFT;
188 tmp |= lsb_first << 24; 237 tmp |= lsb_first << MDR1_BITLSB_SHIFT;
189 sh_msiof_write(p, TMDR1, 0xe0000005 | tmp); 238 sh_msiof_write(p, TMDR1, tmp | MDR1_TRMD | TMDR1_PCON);
190 sh_msiof_write(p, RMDR1, 0x20000005 | tmp); 239 if (p->chipdata->master_flags & SPI_MASTER_MUST_TX) {
240 /* These bits are reserved if RX needs TX */
241 tmp &= ~0x0000ffff;
242 }
243 sh_msiof_write(p, RMDR1, tmp);
191 244
192 tmp = 0xa0000000; 245 tmp = 0;
193 tmp |= cpol << 30; /* TSCKIZ */ 246 tmp |= CTR_TSCKIZ_SCK | cpol << CTR_TSCKIZ_POL_SHIFT;
194 tmp |= cpol << 28; /* RSCKIZ */ 247 tmp |= CTR_RSCKIZ_SCK | cpol << CTR_RSCKIZ_POL_SHIFT;
195 248
196 edge = cpol ^ !cpha; 249 edge = cpol ^ !cpha;
197 250
198 tmp |= edge << 27; /* TEDG */ 251 tmp |= edge << CTR_TEDG_SHIFT;
199 tmp |= edge << 26; /* REDG */ 252 tmp |= edge << CTR_REDG_SHIFT;
200 tmp |= (tx_hi_z ? 2 : 0) << 22; /* TXDIZ */ 253 tmp |= tx_hi_z ? CTR_TXDIZ_HIZ : CTR_TXDIZ_LOW;
201 sh_msiof_write(p, CTR, tmp); 254 sh_msiof_write(p, CTR, tmp);
202} 255}
203 256
@@ -205,12 +258,12 @@ static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p,
205 const void *tx_buf, void *rx_buf, 258 const void *tx_buf, void *rx_buf,
206 u32 bits, u32 words) 259 u32 bits, u32 words)
207{ 260{
208 u32 dr2 = ((bits - 1) << 24) | ((words - 1) << 16); 261 u32 dr2 = MDR2_BITLEN1(bits) | MDR2_WDLEN1(words);
209 262
210 if (tx_buf) 263 if (tx_buf || (p->chipdata->master_flags & SPI_MASTER_MUST_TX))
211 sh_msiof_write(p, TMDR2, dr2); 264 sh_msiof_write(p, TMDR2, dr2);
212 else 265 else
213 sh_msiof_write(p, TMDR2, dr2 | 1); 266 sh_msiof_write(p, TMDR2, dr2 | MDR2_GRPMASK1);
214 267
215 if (rx_buf) 268 if (rx_buf)
216 sh_msiof_write(p, RMDR2, dr2); 269 sh_msiof_write(p, RMDR2, dr2);
@@ -363,77 +416,45 @@ static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p,
363 put_unaligned(swab32(sh_msiof_read(p, RFDR) >> fs), &buf_32[k]); 416 put_unaligned(swab32(sh_msiof_read(p, RFDR) >> fs), &buf_32[k]);
364} 417}
365 418
366static int sh_msiof_spi_bits(struct spi_device *spi, struct spi_transfer *t) 419static int sh_msiof_spi_setup(struct spi_device *spi)
367{ 420{
368 int bits; 421 struct device_node *np = spi->master->dev.of_node;
369 422 struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master);
370 bits = t ? t->bits_per_word : 0;
371 if (!bits)
372 bits = spi->bits_per_word;
373 return bits;
374}
375
376static unsigned long sh_msiof_spi_hz(struct spi_device *spi,
377 struct spi_transfer *t)
378{
379 unsigned long hz;
380
381 hz = t ? t->speed_hz : 0;
382 if (!hz)
383 hz = spi->max_speed_hz;
384 return hz;
385}
386 423
387static int sh_msiof_spi_setup_transfer(struct spi_device *spi, 424 if (!np) {
388 struct spi_transfer *t) 425 /*
389{ 426 * Use spi->controller_data for CS (same strategy as spi_gpio),
390 int bits; 427 * if any. otherwise let HW control CS
428 */
429 spi->cs_gpio = (uintptr_t)spi->controller_data;
430 }
391 431
392 /* noting to check hz values against since parent clock is disabled */ 432 /* Configure pins before deasserting CS */
433 sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL),
434 !!(spi->mode & SPI_CPHA),
435 !!(spi->mode & SPI_3WIRE),
436 !!(spi->mode & SPI_LSB_FIRST),
437 !!(spi->mode & SPI_CS_HIGH));
393 438
394 bits = sh_msiof_spi_bits(spi, t); 439 if (spi->cs_gpio >= 0)
395 if (bits < 8) 440 gpio_set_value(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
396 return -EINVAL;
397 if (bits > 32)
398 return -EINVAL;
399 441
400 return spi_bitbang_setup_transfer(spi, t); 442 return 0;
401} 443}
402 444
403static void sh_msiof_spi_chipselect(struct spi_device *spi, int is_on) 445static int sh_msiof_prepare_message(struct spi_master *master,
446 struct spi_message *msg)
404{ 447{
405 struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master); 448 struct sh_msiof_spi_priv *p = spi_master_get_devdata(master);
406 int value; 449 const struct spi_device *spi = msg->spi;
407
408 /* chip select is active low unless SPI_CS_HIGH is set */
409 if (spi->mode & SPI_CS_HIGH)
410 value = (is_on == BITBANG_CS_ACTIVE) ? 1 : 0;
411 else
412 value = (is_on == BITBANG_CS_ACTIVE) ? 0 : 1;
413
414 if (is_on == BITBANG_CS_ACTIVE) {
415 if (!test_and_set_bit(0, &p->flags)) {
416 pm_runtime_get_sync(&p->pdev->dev);
417 clk_enable(p->clk);
418 }
419
420 /* Configure pins before asserting CS */
421 sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL),
422 !!(spi->mode & SPI_CPHA),
423 !!(spi->mode & SPI_3WIRE),
424 !!(spi->mode & SPI_LSB_FIRST),
425 !!(spi->mode & SPI_CS_HIGH));
426 }
427 450
428 /* use spi->controller data for CS (same strategy as spi_gpio) */ 451 /* Configure pins before asserting CS */
429 gpio_set_value((uintptr_t)spi->controller_data, value); 452 sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL),
430 453 !!(spi->mode & SPI_CPHA),
431 if (is_on == BITBANG_CS_INACTIVE) { 454 !!(spi->mode & SPI_3WIRE),
432 if (test_and_clear_bit(0, &p->flags)) { 455 !!(spi->mode & SPI_LSB_FIRST),
433 clk_disable(p->clk); 456 !!(spi->mode & SPI_CS_HIGH));
434 pm_runtime_put(&p->pdev->dev); 457 return 0;
435 }
436 }
437} 458}
438 459
439static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p, 460static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p,
@@ -487,7 +508,7 @@ static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p,
487 /* clear status bits */ 508 /* clear status bits */
488 sh_msiof_reset_str(p); 509 sh_msiof_reset_str(p);
489 510
490 /* shut down frame, tx/tx and clock signals */ 511 /* shut down frame, rx/tx and clock signals */
491 ret = sh_msiof_modify_ctr_wait(p, CTR_TFSE, 0); 512 ret = sh_msiof_modify_ctr_wait(p, CTR_TFSE, 0);
492 ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_TXE, 0); 513 ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_TXE, 0);
493 if (rx_buf) 514 if (rx_buf)
@@ -505,9 +526,11 @@ static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p,
505 return ret; 526 return ret;
506} 527}
507 528
508static int sh_msiof_spi_txrx(struct spi_device *spi, struct spi_transfer *t) 529static int sh_msiof_transfer_one(struct spi_master *master,
530 struct spi_device *spi,
531 struct spi_transfer *t)
509{ 532{
510 struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master); 533 struct sh_msiof_spi_priv *p = spi_master_get_devdata(master);
511 void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int); 534 void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int);
512 void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int); 535 void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int);
513 int bits; 536 int bits;
@@ -517,7 +540,7 @@ static int sh_msiof_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
517 int n; 540 int n;
518 bool swab; 541 bool swab;
519 542
520 bits = sh_msiof_spi_bits(spi, t); 543 bits = t->bits_per_word;
521 544
522 if (bits <= 8 && t->len > 15 && !(t->len & 3)) { 545 if (bits <= 8 && t->len > 15 && !(t->len & 3)) {
523 bits = 32; 546 bits = 32;
@@ -567,8 +590,7 @@ static int sh_msiof_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
567 } 590 }
568 591
569 /* setup clocks (clock already enabled in chipselect()) */ 592 /* setup clocks (clock already enabled in chipselect()) */
570 sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), 593 sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), t->speed_hz);
571 sh_msiof_spi_hz(spi, t));
572 594
573 /* transfer in fifo sized chunks */ 595 /* transfer in fifo sized chunks */
574 words = t->len / bytes_per_word; 596 words = t->len / bytes_per_word;
@@ -588,22 +610,36 @@ static int sh_msiof_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
588 words -= n; 610 words -= n;
589 } 611 }
590 612
591 return bytes_done;
592}
593
594static u32 sh_msiof_spi_txrx_word(struct spi_device *spi, unsigned nsecs,
595 u32 word, u8 bits)
596{
597 BUG(); /* unused but needed by bitbang code */
598 return 0; 613 return 0;
599} 614}
600 615
616static const struct sh_msiof_chipdata sh_data = {
617 .tx_fifo_size = 64,
618 .rx_fifo_size = 64,
619 .master_flags = 0,
620};
621
622static const struct sh_msiof_chipdata r8a779x_data = {
623 .tx_fifo_size = 64,
624 .rx_fifo_size = 256,
625 .master_flags = SPI_MASTER_MUST_TX,
626};
627
628static const struct of_device_id sh_msiof_match[] = {
629 { .compatible = "renesas,sh-msiof", .data = &sh_data },
630 { .compatible = "renesas,sh-mobile-msiof", .data = &sh_data },
631 { .compatible = "renesas,msiof-r8a7790", .data = &r8a779x_data },
632 { .compatible = "renesas,msiof-r8a7791", .data = &r8a779x_data },
633 {},
634};
635MODULE_DEVICE_TABLE(of, sh_msiof_match);
636
601#ifdef CONFIG_OF 637#ifdef CONFIG_OF
602static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev) 638static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
603{ 639{
604 struct sh_msiof_spi_info *info; 640 struct sh_msiof_spi_info *info;
605 struct device_node *np = dev->of_node; 641 struct device_node *np = dev->of_node;
606 u32 num_cs = 0; 642 u32 num_cs = 1;
607 643
608 info = devm_kzalloc(dev, sizeof(struct sh_msiof_spi_info), GFP_KERNEL); 644 info = devm_kzalloc(dev, sizeof(struct sh_msiof_spi_info), GFP_KERNEL);
609 if (!info) { 645 if (!info) {
@@ -633,6 +669,7 @@ static int sh_msiof_spi_probe(struct platform_device *pdev)
633{ 669{
634 struct resource *r; 670 struct resource *r;
635 struct spi_master *master; 671 struct spi_master *master;
672 const struct of_device_id *of_id;
636 struct sh_msiof_spi_priv *p; 673 struct sh_msiof_spi_priv *p;
637 int i; 674 int i;
638 int ret; 675 int ret;
@@ -646,10 +683,15 @@ static int sh_msiof_spi_probe(struct platform_device *pdev)
646 p = spi_master_get_devdata(master); 683 p = spi_master_get_devdata(master);
647 684
648 platform_set_drvdata(pdev, p); 685 platform_set_drvdata(pdev, p);
649 if (pdev->dev.of_node) 686
687 of_id = of_match_device(sh_msiof_match, &pdev->dev);
688 if (of_id) {
689 p->chipdata = of_id->data;
650 p->info = sh_msiof_spi_parse_dt(&pdev->dev); 690 p->info = sh_msiof_spi_parse_dt(&pdev->dev);
651 else 691 } else {
692 p->chipdata = (const void *)pdev->id_entry->driver_data;
652 p->info = dev_get_platdata(&pdev->dev); 693 p->info = dev_get_platdata(&pdev->dev);
694 }
653 695
654 if (!p->info) { 696 if (!p->info) {
655 dev_err(&pdev->dev, "failed to obtain device info\n"); 697 dev_err(&pdev->dev, "failed to obtain device info\n");
@@ -687,49 +729,40 @@ static int sh_msiof_spi_probe(struct platform_device *pdev)
687 goto err1; 729 goto err1;
688 } 730 }
689 731
690 ret = clk_prepare(p->clk);
691 if (ret < 0) {
692 dev_err(&pdev->dev, "unable to prepare clock\n");
693 goto err1;
694 }
695
696 p->pdev = pdev; 732 p->pdev = pdev;
697 pm_runtime_enable(&pdev->dev); 733 pm_runtime_enable(&pdev->dev);
698 734
699 /* The standard version of MSIOF use 64 word FIFOs */
700 p->tx_fifo_size = 64;
701 p->rx_fifo_size = 64;
702
703 /* Platform data may override FIFO sizes */ 735 /* Platform data may override FIFO sizes */
736 p->tx_fifo_size = p->chipdata->tx_fifo_size;
737 p->rx_fifo_size = p->chipdata->rx_fifo_size;
704 if (p->info->tx_fifo_override) 738 if (p->info->tx_fifo_override)
705 p->tx_fifo_size = p->info->tx_fifo_override; 739 p->tx_fifo_size = p->info->tx_fifo_override;
706 if (p->info->rx_fifo_override) 740 if (p->info->rx_fifo_override)
707 p->rx_fifo_size = p->info->rx_fifo_override; 741 p->rx_fifo_size = p->info->rx_fifo_override;
708 742
709 /* init master and bitbang code */ 743 /* init master code */
710 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 744 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
711 master->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE; 745 master->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE;
712 master->flags = 0; 746 master->flags = p->chipdata->master_flags;
713 master->bus_num = pdev->id; 747 master->bus_num = pdev->id;
748 master->dev.of_node = pdev->dev.of_node;
714 master->num_chipselect = p->info->num_chipselect; 749 master->num_chipselect = p->info->num_chipselect;
715 master->setup = spi_bitbang_setup; 750 master->setup = sh_msiof_spi_setup;
716 master->cleanup = spi_bitbang_cleanup; 751 master->prepare_message = sh_msiof_prepare_message;
717 752 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32);
718 p->bitbang.master = master; 753 master->auto_runtime_pm = true;
719 p->bitbang.chipselect = sh_msiof_spi_chipselect; 754 master->transfer_one = sh_msiof_transfer_one;
720 p->bitbang.setup_transfer = sh_msiof_spi_setup_transfer; 755
721 p->bitbang.txrx_bufs = sh_msiof_spi_txrx; 756 ret = devm_spi_register_master(&pdev->dev, master);
722 p->bitbang.txrx_word[SPI_MODE_0] = sh_msiof_spi_txrx_word; 757 if (ret < 0) {
723 p->bitbang.txrx_word[SPI_MODE_1] = sh_msiof_spi_txrx_word; 758 dev_err(&pdev->dev, "spi_register_master error.\n");
724 p->bitbang.txrx_word[SPI_MODE_2] = sh_msiof_spi_txrx_word; 759 goto err2;
725 p->bitbang.txrx_word[SPI_MODE_3] = sh_msiof_spi_txrx_word; 760 }
726
727 ret = spi_bitbang_start(&p->bitbang);
728 if (ret == 0)
729 return 0;
730 761
762 return 0;
763
764 err2:
731 pm_runtime_disable(&pdev->dev); 765 pm_runtime_disable(&pdev->dev);
732 clk_unprepare(p->clk);
733 err1: 766 err1:
734 spi_master_put(master); 767 spi_master_put(master);
735 return ret; 768 return ret;
@@ -737,30 +770,22 @@ static int sh_msiof_spi_probe(struct platform_device *pdev)
737 770
738static int sh_msiof_spi_remove(struct platform_device *pdev) 771static int sh_msiof_spi_remove(struct platform_device *pdev)
739{ 772{
740 struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev); 773 pm_runtime_disable(&pdev->dev);
741 int ret; 774 return 0;
742
743 ret = spi_bitbang_stop(&p->bitbang);
744 if (!ret) {
745 pm_runtime_disable(&pdev->dev);
746 clk_unprepare(p->clk);
747 spi_master_put(p->bitbang.master);
748 }
749 return ret;
750} 775}
751 776
752#ifdef CONFIG_OF 777static struct platform_device_id spi_driver_ids[] = {
753static const struct of_device_id sh_msiof_match[] = { 778 { "spi_sh_msiof", (kernel_ulong_t)&sh_data },
754 { .compatible = "renesas,sh-msiof", }, 779 { "spi_r8a7790_msiof", (kernel_ulong_t)&r8a779x_data },
755 { .compatible = "renesas,sh-mobile-msiof", }, 780 { "spi_r8a7791_msiof", (kernel_ulong_t)&r8a779x_data },
756 {}, 781 {},
757}; 782};
758MODULE_DEVICE_TABLE(of, sh_msiof_match); 783MODULE_DEVICE_TABLE(platform, spi_driver_ids);
759#endif
760 784
761static struct platform_driver sh_msiof_spi_drv = { 785static struct platform_driver sh_msiof_spi_drv = {
762 .probe = sh_msiof_spi_probe, 786 .probe = sh_msiof_spi_probe,
763 .remove = sh_msiof_spi_remove, 787 .remove = sh_msiof_spi_remove,
788 .id_table = spi_driver_ids,
764 .driver = { 789 .driver = {
765 .name = "spi_sh_msiof", 790 .name = "spi_sh_msiof",
766 .owner = THIS_MODULE, 791 .owner = THIS_MODULE,
diff --git a/drivers/spi/spi-sh-sci.c b/drivers/spi/spi-sh-sci.c
index 38eb24df796c..8b44b71f5024 100644
--- a/drivers/spi/spi-sh-sci.c
+++ b/drivers/spi/spi-sh-sci.c
@@ -14,7 +14,6 @@
14 */ 14 */
15 15
16#include <linux/kernel.h> 16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/delay.h> 17#include <linux/delay.h>
19#include <linux/spinlock.h> 18#include <linux/spinlock.h>
20#include <linux/workqueue.h> 19#include <linux/workqueue.h>
@@ -109,7 +108,7 @@ static void sh_sci_spi_chipselect(struct spi_device *dev, int value)
109{ 108{
110 struct sh_sci_spi *sp = spi_master_get_devdata(dev->master); 109 struct sh_sci_spi *sp = spi_master_get_devdata(dev->master);
111 110
112 if (sp->info && sp->info->chip_select) 111 if (sp->info->chip_select)
113 (sp->info->chip_select)(sp->info, dev->chip_select, value); 112 (sp->info->chip_select)(sp->info, dev->chip_select, value);
114} 113}
115 114
@@ -131,6 +130,11 @@ static int sh_sci_spi_probe(struct platform_device *dev)
131 130
132 platform_set_drvdata(dev, sp); 131 platform_set_drvdata(dev, sp);
133 sp->info = dev_get_platdata(&dev->dev); 132 sp->info = dev_get_platdata(&dev->dev);
133 if (!sp->info) {
134 dev_err(&dev->dev, "platform data is missing\n");
135 ret = -ENOENT;
136 goto err1;
137 }
134 138
135 /* setup spi bitbang adaptor */ 139 /* setup spi bitbang adaptor */
136 sp->bitbang.master = master; 140 sp->bitbang.master = master;
diff --git a/drivers/spi/spi-sirf.c b/drivers/spi/spi-sirf.c
index e430689c3837..1a77ad52812f 100644
--- a/drivers/spi/spi-sirf.c
+++ b/drivers/spi/spi-sirf.c
@@ -22,7 +22,6 @@
22#include <linux/dmaengine.h> 22#include <linux/dmaengine.h>
23#include <linux/dma-direction.h> 23#include <linux/dma-direction.h>
24#include <linux/dma-mapping.h> 24#include <linux/dma-mapping.h>
25#include <linux/sirfsoc_dma.h>
26 25
27#define DRIVER_NAME "sirfsoc_spi" 26#define DRIVER_NAME "sirfsoc_spi"
28 27
@@ -132,6 +131,8 @@
132#define IS_DMA_VALID(x) (x && ALIGNED(x->tx_buf) && ALIGNED(x->rx_buf) && \ 131#define IS_DMA_VALID(x) (x && ALIGNED(x->tx_buf) && ALIGNED(x->rx_buf) && \
133 ALIGNED(x->len) && (x->len < 2 * PAGE_SIZE)) 132 ALIGNED(x->len) && (x->len < 2 * PAGE_SIZE))
134 133
134#define SIRFSOC_MAX_CMD_BYTES 4
135
135struct sirfsoc_spi { 136struct sirfsoc_spi {
136 struct spi_bitbang bitbang; 137 struct spi_bitbang bitbang;
137 struct completion rx_done; 138 struct completion rx_done;
@@ -162,6 +163,12 @@ struct sirfsoc_spi {
162 void *dummypage; 163 void *dummypage;
163 int word_width; /* in bytes */ 164 int word_width; /* in bytes */
164 165
166 /*
167 * if tx size is not more than 4 and rx size is NULL, use
168 * command model
169 */
170 bool tx_by_cmd;
171
165 int chipselect[0]; 172 int chipselect[0];
166}; 173};
167 174
@@ -260,6 +267,12 @@ static irqreturn_t spi_sirfsoc_irq(int irq, void *dev_id)
260 267
261 writel(spi_stat, sspi->base + SIRFSOC_SPI_INT_STATUS); 268 writel(spi_stat, sspi->base + SIRFSOC_SPI_INT_STATUS);
262 269
270 if (sspi->tx_by_cmd && (spi_stat & SIRFSOC_SPI_FRM_END)) {
271 complete(&sspi->tx_done);
272 writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN);
273 return IRQ_HANDLED;
274 }
275
263 /* Error Conditions */ 276 /* Error Conditions */
264 if (spi_stat & SIRFSOC_SPI_RX_OFLOW || 277 if (spi_stat & SIRFSOC_SPI_RX_OFLOW ||
265 spi_stat & SIRFSOC_SPI_TX_UFLOW) { 278 spi_stat & SIRFSOC_SPI_TX_UFLOW) {
@@ -310,6 +323,34 @@ static int spi_sirfsoc_transfer(struct spi_device *spi, struct spi_transfer *t)
310 323
311 writel(SIRFSOC_SPI_INT_MASK_ALL, sspi->base + SIRFSOC_SPI_INT_STATUS); 324 writel(SIRFSOC_SPI_INT_MASK_ALL, sspi->base + SIRFSOC_SPI_INT_STATUS);
312 325
326 /*
327 * fill tx_buf into command register and wait for its completion
328 */
329 if (sspi->tx_by_cmd) {
330 u32 cmd;
331 memcpy(&cmd, sspi->tx, t->len);
332
333 if (sspi->word_width == 1 && !(spi->mode & SPI_LSB_FIRST))
334 cmd = cpu_to_be32(cmd) >>
335 ((SIRFSOC_MAX_CMD_BYTES - t->len) * 8);
336 if (sspi->word_width == 2 && t->len == 4 &&
337 (!(spi->mode & SPI_LSB_FIRST)))
338 cmd = ((cmd & 0xffff) << 16) | (cmd >> 16);
339
340 writel(cmd, sspi->base + SIRFSOC_SPI_CMD);
341 writel(SIRFSOC_SPI_FRM_END_INT_EN,
342 sspi->base + SIRFSOC_SPI_INT_EN);
343 writel(SIRFSOC_SPI_CMD_TX_EN,
344 sspi->base + SIRFSOC_SPI_TX_RX_EN);
345
346 if (wait_for_completion_timeout(&sspi->tx_done, timeout) == 0) {
347 dev_err(&spi->dev, "transfer timeout\n");
348 return 0;
349 }
350
351 return t->len;
352 }
353
313 if (sspi->left_tx_word == 1) { 354 if (sspi->left_tx_word == 1) {
314 writel(readl(sspi->base + SIRFSOC_SPI_CTRL) | 355 writel(readl(sspi->base + SIRFSOC_SPI_CTRL) |
315 SIRFSOC_SPI_ENA_AUTO_CLR, 356 SIRFSOC_SPI_ENA_AUTO_CLR,
@@ -459,11 +500,6 @@ spi_sirfsoc_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
459 regval |= SIRFSOC_SPI_TRAN_DAT_FORMAT_8; 500 regval |= SIRFSOC_SPI_TRAN_DAT_FORMAT_8;
460 sspi->rx_word = spi_sirfsoc_rx_word_u8; 501 sspi->rx_word = spi_sirfsoc_rx_word_u8;
461 sspi->tx_word = spi_sirfsoc_tx_word_u8; 502 sspi->tx_word = spi_sirfsoc_tx_word_u8;
462 txfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
463 SIRFSOC_SPI_FIFO_WIDTH_BYTE;
464 rxfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
465 SIRFSOC_SPI_FIFO_WIDTH_BYTE;
466 sspi->word_width = 1;
467 break; 503 break;
468 case 12: 504 case 12:
469 case 16: 505 case 16:
@@ -471,26 +507,22 @@ spi_sirfsoc_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
471 SIRFSOC_SPI_TRAN_DAT_FORMAT_16; 507 SIRFSOC_SPI_TRAN_DAT_FORMAT_16;
472 sspi->rx_word = spi_sirfsoc_rx_word_u16; 508 sspi->rx_word = spi_sirfsoc_rx_word_u16;
473 sspi->tx_word = spi_sirfsoc_tx_word_u16; 509 sspi->tx_word = spi_sirfsoc_tx_word_u16;
474 txfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
475 SIRFSOC_SPI_FIFO_WIDTH_WORD;
476 rxfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
477 SIRFSOC_SPI_FIFO_WIDTH_WORD;
478 sspi->word_width = 2;
479 break; 510 break;
480 case 32: 511 case 32:
481 regval |= SIRFSOC_SPI_TRAN_DAT_FORMAT_32; 512 regval |= SIRFSOC_SPI_TRAN_DAT_FORMAT_32;
482 sspi->rx_word = spi_sirfsoc_rx_word_u32; 513 sspi->rx_word = spi_sirfsoc_rx_word_u32;
483 sspi->tx_word = spi_sirfsoc_tx_word_u32; 514 sspi->tx_word = spi_sirfsoc_tx_word_u32;
484 txfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
485 SIRFSOC_SPI_FIFO_WIDTH_DWORD;
486 rxfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
487 SIRFSOC_SPI_FIFO_WIDTH_DWORD;
488 sspi->word_width = 4;
489 break; 515 break;
490 default: 516 default:
491 BUG(); 517 BUG();
492 } 518 }
493 519
520 sspi->word_width = DIV_ROUND_UP(bits_per_word, 8);
521 txfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
522 sspi->word_width;
523 rxfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
524 sspi->word_width;
525
494 if (!(spi->mode & SPI_CS_HIGH)) 526 if (!(spi->mode & SPI_CS_HIGH))
495 regval |= SIRFSOC_SPI_CS_IDLE_STAT; 527 regval |= SIRFSOC_SPI_CS_IDLE_STAT;
496 if (!(spi->mode & SPI_LSB_FIRST)) 528 if (!(spi->mode & SPI_LSB_FIRST))
@@ -519,6 +551,14 @@ spi_sirfsoc_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
519 writel(txfifo_ctrl, sspi->base + SIRFSOC_SPI_TXFIFO_CTRL); 551 writel(txfifo_ctrl, sspi->base + SIRFSOC_SPI_TXFIFO_CTRL);
520 writel(rxfifo_ctrl, sspi->base + SIRFSOC_SPI_RXFIFO_CTRL); 552 writel(rxfifo_ctrl, sspi->base + SIRFSOC_SPI_RXFIFO_CTRL);
521 553
554 if (t && t->tx_buf && !t->rx_buf && (t->len <= SIRFSOC_MAX_CMD_BYTES)) {
555 regval |= (SIRFSOC_SPI_CMD_BYTE_NUM((t->len - 1)) |
556 SIRFSOC_SPI_CMD_MODE);
557 sspi->tx_by_cmd = true;
558 } else {
559 regval &= ~SIRFSOC_SPI_CMD_MODE;
560 sspi->tx_by_cmd = false;
561 }
522 writel(regval, sspi->base + SIRFSOC_SPI_CTRL); 562 writel(regval, sspi->base + SIRFSOC_SPI_CTRL);
523 563
524 if (IS_DMA_VALID(t)) { 564 if (IS_DMA_VALID(t)) {
@@ -548,8 +588,6 @@ static int spi_sirfsoc_probe(struct platform_device *pdev)
548 struct spi_master *master; 588 struct spi_master *master;
549 struct resource *mem_res; 589 struct resource *mem_res;
550 int num_cs, cs_gpio, irq; 590 int num_cs, cs_gpio, irq;
551 u32 rx_dma_ch, tx_dma_ch;
552 dma_cap_mask_t dma_cap_mask;
553 int i; 591 int i;
554 int ret; 592 int ret;
555 593
@@ -560,20 +598,6 @@ static int spi_sirfsoc_probe(struct platform_device *pdev)
560 goto err_cs; 598 goto err_cs;
561 } 599 }
562 600
563 ret = of_property_read_u32(pdev->dev.of_node,
564 "sirf,spi-dma-rx-channel", &rx_dma_ch);
565 if (ret < 0) {
566 dev_err(&pdev->dev, "Unable to get rx dma channel\n");
567 goto err_cs;
568 }
569
570 ret = of_property_read_u32(pdev->dev.of_node,
571 "sirf,spi-dma-tx-channel", &tx_dma_ch);
572 if (ret < 0) {
573 dev_err(&pdev->dev, "Unable to get tx dma channel\n");
574 goto err_cs;
575 }
576
577 master = spi_alloc_master(&pdev->dev, sizeof(*sspi) + sizeof(int) * num_cs); 601 master = spi_alloc_master(&pdev->dev, sizeof(*sspi) + sizeof(int) * num_cs);
578 if (!master) { 602 if (!master) {
579 dev_err(&pdev->dev, "Unable to allocate SPI master\n"); 603 dev_err(&pdev->dev, "Unable to allocate SPI master\n");
@@ -637,18 +661,13 @@ static int spi_sirfsoc_probe(struct platform_device *pdev)
637 sspi->bitbang.master->dev.of_node = pdev->dev.of_node; 661 sspi->bitbang.master->dev.of_node = pdev->dev.of_node;
638 662
639 /* request DMA channels */ 663 /* request DMA channels */
640 dma_cap_zero(dma_cap_mask); 664 sspi->rx_chan = dma_request_slave_channel(&pdev->dev, "rx");
641 dma_cap_set(DMA_INTERLEAVE, dma_cap_mask);
642
643 sspi->rx_chan = dma_request_channel(dma_cap_mask, (dma_filter_fn)sirfsoc_dma_filter_id,
644 (void *)rx_dma_ch);
645 if (!sspi->rx_chan) { 665 if (!sspi->rx_chan) {
646 dev_err(&pdev->dev, "can not allocate rx dma channel\n"); 666 dev_err(&pdev->dev, "can not allocate rx dma channel\n");
647 ret = -ENODEV; 667 ret = -ENODEV;
648 goto free_master; 668 goto free_master;
649 } 669 }
650 sspi->tx_chan = dma_request_channel(dma_cap_mask, (dma_filter_fn)sirfsoc_dma_filter_id, 670 sspi->tx_chan = dma_request_slave_channel(&pdev->dev, "tx");
651 (void *)tx_dma_ch);
652 if (!sspi->tx_chan) { 671 if (!sspi->tx_chan) {
653 dev_err(&pdev->dev, "can not allocate tx dma channel\n"); 672 dev_err(&pdev->dev, "can not allocate tx dma channel\n");
654 ret = -ENODEV; 673 ret = -ENODEV;
@@ -724,11 +743,16 @@ static int spi_sirfsoc_remove(struct platform_device *pdev)
724 return 0; 743 return 0;
725} 744}
726 745
727#ifdef CONFIG_PM 746#ifdef CONFIG_PM_SLEEP
728static int spi_sirfsoc_suspend(struct device *dev) 747static int spi_sirfsoc_suspend(struct device *dev)
729{ 748{
730 struct spi_master *master = dev_get_drvdata(dev); 749 struct spi_master *master = dev_get_drvdata(dev);
731 struct sirfsoc_spi *sspi = spi_master_get_devdata(master); 750 struct sirfsoc_spi *sspi = spi_master_get_devdata(master);
751 int ret;
752
753 ret = spi_master_suspend(master);
754 if (ret)
755 return ret;
732 756
733 clk_disable(sspi->clk); 757 clk_disable(sspi->clk);
734 return 0; 758 return 0;
@@ -745,15 +769,13 @@ static int spi_sirfsoc_resume(struct device *dev)
745 writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP); 769 writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
746 writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP); 770 writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
747 771
748 return 0; 772 return spi_master_resume(master);
749} 773}
750
751static const struct dev_pm_ops spi_sirfsoc_pm_ops = {
752 .suspend = spi_sirfsoc_suspend,
753 .resume = spi_sirfsoc_resume,
754};
755#endif 774#endif
756 775
776static SIMPLE_DEV_PM_OPS(spi_sirfsoc_pm_ops, spi_sirfsoc_suspend,
777 spi_sirfsoc_resume);
778
757static const struct of_device_id spi_sirfsoc_of_match[] = { 779static const struct of_device_id spi_sirfsoc_of_match[] = {
758 { .compatible = "sirf,prima2-spi", }, 780 { .compatible = "sirf,prima2-spi", },
759 { .compatible = "sirf,marco-spi", }, 781 { .compatible = "sirf,marco-spi", },
@@ -765,9 +787,7 @@ static struct platform_driver spi_sirfsoc_driver = {
765 .driver = { 787 .driver = {
766 .name = DRIVER_NAME, 788 .name = DRIVER_NAME,
767 .owner = THIS_MODULE, 789 .owner = THIS_MODULE,
768#ifdef CONFIG_PM
769 .pm = &spi_sirfsoc_pm_ops, 790 .pm = &spi_sirfsoc_pm_ops,
770#endif
771 .of_match_table = spi_sirfsoc_of_match, 791 .of_match_table = spi_sirfsoc_of_match,
772 }, 792 },
773 .probe = spi_sirfsoc_probe, 793 .probe = spi_sirfsoc_probe,
diff --git a/drivers/spi/spi-sun4i.c b/drivers/spi/spi-sun4i.c
new file mode 100644
index 000000000000..d266a8702067
--- /dev/null
+++ b/drivers/spi/spi-sun4i.c
@@ -0,0 +1,478 @@
1/*
2 * Copyright (C) 2012 - 2014 Allwinner Tech
3 * Pan Nan <pannan@allwinnertech.com>
4 *
5 * Copyright (C) 2014 Maxime Ripard
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 */
13
14#include <linux/clk.h>
15#include <linux/delay.h>
16#include <linux/device.h>
17#include <linux/interrupt.h>
18#include <linux/io.h>
19#include <linux/module.h>
20#include <linux/platform_device.h>
21#include <linux/pm_runtime.h>
22#include <linux/workqueue.h>
23
24#include <linux/spi/spi.h>
25
26#define SUN4I_FIFO_DEPTH 64
27
28#define SUN4I_RXDATA_REG 0x00
29
30#define SUN4I_TXDATA_REG 0x04
31
32#define SUN4I_CTL_REG 0x08
33#define SUN4I_CTL_ENABLE BIT(0)
34#define SUN4I_CTL_MASTER BIT(1)
35#define SUN4I_CTL_CPHA BIT(2)
36#define SUN4I_CTL_CPOL BIT(3)
37#define SUN4I_CTL_CS_ACTIVE_LOW BIT(4)
38#define SUN4I_CTL_LMTF BIT(6)
39#define SUN4I_CTL_TF_RST BIT(8)
40#define SUN4I_CTL_RF_RST BIT(9)
41#define SUN4I_CTL_XCH BIT(10)
42#define SUN4I_CTL_CS_MASK 0x3000
43#define SUN4I_CTL_CS(cs) (((cs) << 12) & SUN4I_CTL_CS_MASK)
44#define SUN4I_CTL_DHB BIT(15)
45#define SUN4I_CTL_CS_MANUAL BIT(16)
46#define SUN4I_CTL_CS_LEVEL BIT(17)
47#define SUN4I_CTL_TP BIT(18)
48
49#define SUN4I_INT_CTL_REG 0x0c
50#define SUN4I_INT_CTL_TC BIT(16)
51
52#define SUN4I_INT_STA_REG 0x10
53
54#define SUN4I_DMA_CTL_REG 0x14
55
56#define SUN4I_WAIT_REG 0x18
57
58#define SUN4I_CLK_CTL_REG 0x1c
59#define SUN4I_CLK_CTL_CDR2_MASK 0xff
60#define SUN4I_CLK_CTL_CDR2(div) ((div) & SUN4I_CLK_CTL_CDR2_MASK)
61#define SUN4I_CLK_CTL_CDR1_MASK 0xf
62#define SUN4I_CLK_CTL_CDR1(div) (((div) & SUN4I_CLK_CTL_CDR1_MASK) << 8)
63#define SUN4I_CLK_CTL_DRS BIT(12)
64
65#define SUN4I_BURST_CNT_REG 0x20
66#define SUN4I_BURST_CNT(cnt) ((cnt) & 0xffffff)
67
68#define SUN4I_XMIT_CNT_REG 0x24
69#define SUN4I_XMIT_CNT(cnt) ((cnt) & 0xffffff)
70
71#define SUN4I_FIFO_STA_REG 0x28
72#define SUN4I_FIFO_STA_RF_CNT_MASK 0x7f
73#define SUN4I_FIFO_STA_RF_CNT_BITS 0
74#define SUN4I_FIFO_STA_TF_CNT_MASK 0x7f
75#define SUN4I_FIFO_STA_TF_CNT_BITS 16
76
77struct sun4i_spi {
78 struct spi_master *master;
79 void __iomem *base_addr;
80 struct clk *hclk;
81 struct clk *mclk;
82
83 struct completion done;
84
85 const u8 *tx_buf;
86 u8 *rx_buf;
87 int len;
88};
89
90static inline u32 sun4i_spi_read(struct sun4i_spi *sspi, u32 reg)
91{
92 return readl(sspi->base_addr + reg);
93}
94
95static inline void sun4i_spi_write(struct sun4i_spi *sspi, u32 reg, u32 value)
96{
97 writel(value, sspi->base_addr + reg);
98}
99
100static inline void sun4i_spi_drain_fifo(struct sun4i_spi *sspi, int len)
101{
102 u32 reg, cnt;
103 u8 byte;
104
105 /* See how much data is available */
106 reg = sun4i_spi_read(sspi, SUN4I_FIFO_STA_REG);
107 reg &= SUN4I_FIFO_STA_RF_CNT_MASK;
108 cnt = reg >> SUN4I_FIFO_STA_RF_CNT_BITS;
109
110 if (len > cnt)
111 len = cnt;
112
113 while (len--) {
114 byte = readb(sspi->base_addr + SUN4I_RXDATA_REG);
115 if (sspi->rx_buf)
116 *sspi->rx_buf++ = byte;
117 }
118}
119
120static inline void sun4i_spi_fill_fifo(struct sun4i_spi *sspi, int len)
121{
122 u8 byte;
123
124 if (len > sspi->len)
125 len = sspi->len;
126
127 while (len--) {
128 byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
129 writeb(byte, sspi->base_addr + SUN4I_TXDATA_REG);
130 sspi->len--;
131 }
132}
133
134static void sun4i_spi_set_cs(struct spi_device *spi, bool enable)
135{
136 struct sun4i_spi *sspi = spi_master_get_devdata(spi->master);
137 u32 reg;
138
139 reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
140
141 reg &= ~SUN4I_CTL_CS_MASK;
142 reg |= SUN4I_CTL_CS(spi->chip_select);
143
144 if (enable)
145 reg |= SUN4I_CTL_CS_LEVEL;
146 else
147 reg &= ~SUN4I_CTL_CS_LEVEL;
148
149 /*
150 * Even though this looks irrelevant since we are supposed to
151 * be controlling the chip select manually, this bit also
152 * controls the levels of the chip select for inactive
153 * devices.
154 *
155 * If we don't set it, the chip select level will go low by
156 * default when the device is idle, which is not really
157 * expected in the common case where the chip select is active
158 * low.
159 */
160 if (spi->mode & SPI_CS_HIGH)
161 reg &= ~SUN4I_CTL_CS_ACTIVE_LOW;
162 else
163 reg |= SUN4I_CTL_CS_ACTIVE_LOW;
164
165 sun4i_spi_write(sspi, SUN4I_CTL_REG, reg);
166}
167
168static int sun4i_spi_transfer_one(struct spi_master *master,
169 struct spi_device *spi,
170 struct spi_transfer *tfr)
171{
172 struct sun4i_spi *sspi = spi_master_get_devdata(master);
173 unsigned int mclk_rate, div, timeout;
174 unsigned int tx_len = 0;
175 int ret = 0;
176 u32 reg;
177
178 /* We don't support transfer larger than the FIFO */
179 if (tfr->len > SUN4I_FIFO_DEPTH)
180 return -EINVAL;
181
182 reinit_completion(&sspi->done);
183 sspi->tx_buf = tfr->tx_buf;
184 sspi->rx_buf = tfr->rx_buf;
185 sspi->len = tfr->len;
186
187 /* Clear pending interrupts */
188 sun4i_spi_write(sspi, SUN4I_INT_STA_REG, ~0);
189
190
191 reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
192
193 /* Reset FIFOs */
194 sun4i_spi_write(sspi, SUN4I_CTL_REG,
195 reg | SUN4I_CTL_RF_RST | SUN4I_CTL_TF_RST);
196
197 /*
198 * Setup the transfer control register: Chip Select,
199 * polarities, etc.
200 */
201 if (spi->mode & SPI_CPOL)
202 reg |= SUN4I_CTL_CPOL;
203 else
204 reg &= ~SUN4I_CTL_CPOL;
205
206 if (spi->mode & SPI_CPHA)
207 reg |= SUN4I_CTL_CPHA;
208 else
209 reg &= ~SUN4I_CTL_CPHA;
210
211 if (spi->mode & SPI_LSB_FIRST)
212 reg |= SUN4I_CTL_LMTF;
213 else
214 reg &= ~SUN4I_CTL_LMTF;
215
216
217 /*
218 * If it's a TX only transfer, we don't want to fill the RX
219 * FIFO with bogus data
220 */
221 if (sspi->rx_buf)
222 reg &= ~SUN4I_CTL_DHB;
223 else
224 reg |= SUN4I_CTL_DHB;
225
226 /* We want to control the chip select manually */
227 reg |= SUN4I_CTL_CS_MANUAL;
228
229 sun4i_spi_write(sspi, SUN4I_CTL_REG, reg);
230
231 /* Ensure that we have a parent clock fast enough */
232 mclk_rate = clk_get_rate(sspi->mclk);
233 if (mclk_rate < (2 * spi->max_speed_hz)) {
234 clk_set_rate(sspi->mclk, 2 * spi->max_speed_hz);
235 mclk_rate = clk_get_rate(sspi->mclk);
236 }
237
238 /*
239 * Setup clock divider.
240 *
241 * We have two choices there. Either we can use the clock
242 * divide rate 1, which is calculated thanks to this formula:
243 * SPI_CLK = MOD_CLK / (2 ^ (cdr + 1))
244 * Or we can use CDR2, which is calculated with the formula:
245 * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
246 * Wether we use the former or the latter is set through the
247 * DRS bit.
248 *
249 * First try CDR2, and if we can't reach the expected
250 * frequency, fall back to CDR1.
251 */
252 div = mclk_rate / (2 * spi->max_speed_hz);
253 if (div <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) {
254 if (div > 0)
255 div--;
256
257 reg = SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS;
258 } else {
259 div = ilog2(mclk_rate) - ilog2(spi->max_speed_hz);
260 reg = SUN4I_CLK_CTL_CDR1(div);
261 }
262
263 sun4i_spi_write(sspi, SUN4I_CLK_CTL_REG, reg);
264
265 /* Setup the transfer now... */
266 if (sspi->tx_buf)
267 tx_len = tfr->len;
268
269 /* Setup the counters */
270 sun4i_spi_write(sspi, SUN4I_BURST_CNT_REG, SUN4I_BURST_CNT(tfr->len));
271 sun4i_spi_write(sspi, SUN4I_XMIT_CNT_REG, SUN4I_XMIT_CNT(tx_len));
272
273 /* Fill the TX FIFO */
274 sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH);
275
276 /* Enable the interrupts */
277 sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, SUN4I_INT_CTL_TC);
278
279 /* Start the transfer */
280 reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
281 sun4i_spi_write(sspi, SUN4I_CTL_REG, reg | SUN4I_CTL_XCH);
282
283 timeout = wait_for_completion_timeout(&sspi->done,
284 msecs_to_jiffies(1000));
285 if (!timeout) {
286 ret = -ETIMEDOUT;
287 goto out;
288 }
289
290 sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH);
291
292out:
293 sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, 0);
294
295 return ret;
296}
297
298static irqreturn_t sun4i_spi_handler(int irq, void *dev_id)
299{
300 struct sun4i_spi *sspi = dev_id;
301 u32 status = sun4i_spi_read(sspi, SUN4I_INT_STA_REG);
302
303 /* Transfer complete */
304 if (status & SUN4I_INT_CTL_TC) {
305 sun4i_spi_write(sspi, SUN4I_INT_STA_REG, SUN4I_INT_CTL_TC);
306 complete(&sspi->done);
307 return IRQ_HANDLED;
308 }
309
310 return IRQ_NONE;
311}
312
313static int sun4i_spi_runtime_resume(struct device *dev)
314{
315 struct spi_master *master = dev_get_drvdata(dev);
316 struct sun4i_spi *sspi = spi_master_get_devdata(master);
317 int ret;
318
319 ret = clk_prepare_enable(sspi->hclk);
320 if (ret) {
321 dev_err(dev, "Couldn't enable AHB clock\n");
322 goto out;
323 }
324
325 ret = clk_prepare_enable(sspi->mclk);
326 if (ret) {
327 dev_err(dev, "Couldn't enable module clock\n");
328 goto err;
329 }
330
331 sun4i_spi_write(sspi, SUN4I_CTL_REG,
332 SUN4I_CTL_ENABLE | SUN4I_CTL_MASTER | SUN4I_CTL_TP);
333
334 return 0;
335
336err:
337 clk_disable_unprepare(sspi->hclk);
338out:
339 return ret;
340}
341
342static int sun4i_spi_runtime_suspend(struct device *dev)
343{
344 struct spi_master *master = dev_get_drvdata(dev);
345 struct sun4i_spi *sspi = spi_master_get_devdata(master);
346
347 clk_disable_unprepare(sspi->mclk);
348 clk_disable_unprepare(sspi->hclk);
349
350 return 0;
351}
352
353static int sun4i_spi_probe(struct platform_device *pdev)
354{
355 struct spi_master *master;
356 struct sun4i_spi *sspi;
357 struct resource *res;
358 int ret = 0, irq;
359
360 master = spi_alloc_master(&pdev->dev, sizeof(struct sun4i_spi));
361 if (!master) {
362 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
363 return -ENOMEM;
364 }
365
366 platform_set_drvdata(pdev, master);
367 sspi = spi_master_get_devdata(master);
368
369 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
370 sspi->base_addr = devm_ioremap_resource(&pdev->dev, res);
371 if (IS_ERR(sspi->base_addr)) {
372 ret = PTR_ERR(sspi->base_addr);
373 goto err_free_master;
374 }
375
376 irq = platform_get_irq(pdev, 0);
377 if (irq < 0) {
378 dev_err(&pdev->dev, "No spi IRQ specified\n");
379 ret = -ENXIO;
380 goto err_free_master;
381 }
382
383 ret = devm_request_irq(&pdev->dev, irq, sun4i_spi_handler,
384 0, "sun4i-spi", sspi);
385 if (ret) {
386 dev_err(&pdev->dev, "Cannot request IRQ\n");
387 goto err_free_master;
388 }
389
390 sspi->master = master;
391 master->set_cs = sun4i_spi_set_cs;
392 master->transfer_one = sun4i_spi_transfer_one;
393 master->num_chipselect = 4;
394 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
395 master->bits_per_word_mask = SPI_BPW_MASK(8);
396 master->dev.of_node = pdev->dev.of_node;
397 master->auto_runtime_pm = true;
398
399 sspi->hclk = devm_clk_get(&pdev->dev, "ahb");
400 if (IS_ERR(sspi->hclk)) {
401 dev_err(&pdev->dev, "Unable to acquire AHB clock\n");
402 ret = PTR_ERR(sspi->hclk);
403 goto err_free_master;
404 }
405
406 sspi->mclk = devm_clk_get(&pdev->dev, "mod");
407 if (IS_ERR(sspi->mclk)) {
408 dev_err(&pdev->dev, "Unable to acquire module clock\n");
409 ret = PTR_ERR(sspi->mclk);
410 goto err_free_master;
411 }
412
413 init_completion(&sspi->done);
414
415 /*
416 * This wake-up/shutdown pattern is to be able to have the
417 * device woken up, even if runtime_pm is disabled
418 */
419 ret = sun4i_spi_runtime_resume(&pdev->dev);
420 if (ret) {
421 dev_err(&pdev->dev, "Couldn't resume the device\n");
422 goto err_free_master;
423 }
424
425 pm_runtime_set_active(&pdev->dev);
426 pm_runtime_enable(&pdev->dev);
427 pm_runtime_idle(&pdev->dev);
428
429 ret = devm_spi_register_master(&pdev->dev, master);
430 if (ret) {
431 dev_err(&pdev->dev, "cannot register SPI master\n");
432 goto err_pm_disable;
433 }
434
435 return 0;
436
437err_pm_disable:
438 pm_runtime_disable(&pdev->dev);
439 sun4i_spi_runtime_suspend(&pdev->dev);
440err_free_master:
441 spi_master_put(master);
442 return ret;
443}
444
445static int sun4i_spi_remove(struct platform_device *pdev)
446{
447 pm_runtime_disable(&pdev->dev);
448
449 return 0;
450}
451
452static const struct of_device_id sun4i_spi_match[] = {
453 { .compatible = "allwinner,sun4i-a10-spi", },
454 {}
455};
456MODULE_DEVICE_TABLE(of, sun4i_spi_match);
457
458static const struct dev_pm_ops sun4i_spi_pm_ops = {
459 .runtime_resume = sun4i_spi_runtime_resume,
460 .runtime_suspend = sun4i_spi_runtime_suspend,
461};
462
463static struct platform_driver sun4i_spi_driver = {
464 .probe = sun4i_spi_probe,
465 .remove = sun4i_spi_remove,
466 .driver = {
467 .name = "sun4i-spi",
468 .owner = THIS_MODULE,
469 .of_match_table = sun4i_spi_match,
470 .pm = &sun4i_spi_pm_ops,
471 },
472};
473module_platform_driver(sun4i_spi_driver);
474
475MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>");
476MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
477MODULE_DESCRIPTION("Allwinner A1X/A20 SPI controller driver");
478MODULE_LICENSE("GPL");
diff --git a/drivers/spi/spi-sun6i.c b/drivers/spi/spi-sun6i.c
new file mode 100644
index 000000000000..b3e3498a7e6f
--- /dev/null
+++ b/drivers/spi/spi-sun6i.c
@@ -0,0 +1,484 @@
1/*
2 * Copyright (C) 2012 - 2014 Allwinner Tech
3 * Pan Nan <pannan@allwinnertech.com>
4 *
5 * Copyright (C) 2014 Maxime Ripard
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 */
13
14#include <linux/clk.h>
15#include <linux/delay.h>
16#include <linux/device.h>
17#include <linux/interrupt.h>
18#include <linux/io.h>
19#include <linux/module.h>
20#include <linux/platform_device.h>
21#include <linux/pm_runtime.h>
22#include <linux/reset.h>
23#include <linux/workqueue.h>
24
25#include <linux/spi/spi.h>
26
27#define SUN6I_FIFO_DEPTH 128
28
29#define SUN6I_GBL_CTL_REG 0x04
30#define SUN6I_GBL_CTL_BUS_ENABLE BIT(0)
31#define SUN6I_GBL_CTL_MASTER BIT(1)
32#define SUN6I_GBL_CTL_TP BIT(7)
33#define SUN6I_GBL_CTL_RST BIT(31)
34
35#define SUN6I_TFR_CTL_REG 0x08
36#define SUN6I_TFR_CTL_CPHA BIT(0)
37#define SUN6I_TFR_CTL_CPOL BIT(1)
38#define SUN6I_TFR_CTL_SPOL BIT(2)
39#define SUN6I_TFR_CTL_CS_MASK 0x30
40#define SUN6I_TFR_CTL_CS(cs) (((cs) << 4) & SUN6I_TFR_CTL_CS_MASK)
41#define SUN6I_TFR_CTL_CS_MANUAL BIT(6)
42#define SUN6I_TFR_CTL_CS_LEVEL BIT(7)
43#define SUN6I_TFR_CTL_DHB BIT(8)
44#define SUN6I_TFR_CTL_FBS BIT(12)
45#define SUN6I_TFR_CTL_XCH BIT(31)
46
47#define SUN6I_INT_CTL_REG 0x10
48#define SUN6I_INT_CTL_RF_OVF BIT(8)
49#define SUN6I_INT_CTL_TC BIT(12)
50
51#define SUN6I_INT_STA_REG 0x14
52
53#define SUN6I_FIFO_CTL_REG 0x18
54#define SUN6I_FIFO_CTL_RF_RST BIT(15)
55#define SUN6I_FIFO_CTL_TF_RST BIT(31)
56
57#define SUN6I_FIFO_STA_REG 0x1c
58#define SUN6I_FIFO_STA_RF_CNT_MASK 0x7f
59#define SUN6I_FIFO_STA_RF_CNT_BITS 0
60#define SUN6I_FIFO_STA_TF_CNT_MASK 0x7f
61#define SUN6I_FIFO_STA_TF_CNT_BITS 16
62
63#define SUN6I_CLK_CTL_REG 0x24
64#define SUN6I_CLK_CTL_CDR2_MASK 0xff
65#define SUN6I_CLK_CTL_CDR2(div) (((div) & SUN6I_CLK_CTL_CDR2_MASK) << 0)
66#define SUN6I_CLK_CTL_CDR1_MASK 0xf
67#define SUN6I_CLK_CTL_CDR1(div) (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8)
68#define SUN6I_CLK_CTL_DRS BIT(12)
69
70#define SUN6I_BURST_CNT_REG 0x30
71#define SUN6I_BURST_CNT(cnt) ((cnt) & 0xffffff)
72
73#define SUN6I_XMIT_CNT_REG 0x34
74#define SUN6I_XMIT_CNT(cnt) ((cnt) & 0xffffff)
75
76#define SUN6I_BURST_CTL_CNT_REG 0x38
77#define SUN6I_BURST_CTL_CNT_STC(cnt) ((cnt) & 0xffffff)
78
79#define SUN6I_TXDATA_REG 0x200
80#define SUN6I_RXDATA_REG 0x300
81
82struct sun6i_spi {
83 struct spi_master *master;
84 void __iomem *base_addr;
85 struct clk *hclk;
86 struct clk *mclk;
87 struct reset_control *rstc;
88
89 struct completion done;
90
91 const u8 *tx_buf;
92 u8 *rx_buf;
93 int len;
94};
95
96static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg)
97{
98 return readl(sspi->base_addr + reg);
99}
100
101static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value)
102{
103 writel(value, sspi->base_addr + reg);
104}
105
106static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len)
107{
108 u32 reg, cnt;
109 u8 byte;
110
111 /* See how much data is available */
112 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
113 reg &= SUN6I_FIFO_STA_RF_CNT_MASK;
114 cnt = reg >> SUN6I_FIFO_STA_RF_CNT_BITS;
115
116 if (len > cnt)
117 len = cnt;
118
119 while (len--) {
120 byte = readb(sspi->base_addr + SUN6I_RXDATA_REG);
121 if (sspi->rx_buf)
122 *sspi->rx_buf++ = byte;
123 }
124}
125
126static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi, int len)
127{
128 u8 byte;
129
130 if (len > sspi->len)
131 len = sspi->len;
132
133 while (len--) {
134 byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
135 writeb(byte, sspi->base_addr + SUN6I_TXDATA_REG);
136 sspi->len--;
137 }
138}
139
140static void sun6i_spi_set_cs(struct spi_device *spi, bool enable)
141{
142 struct sun6i_spi *sspi = spi_master_get_devdata(spi->master);
143 u32 reg;
144
145 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
146 reg &= ~SUN6I_TFR_CTL_CS_MASK;
147 reg |= SUN6I_TFR_CTL_CS(spi->chip_select);
148
149 if (enable)
150 reg |= SUN6I_TFR_CTL_CS_LEVEL;
151 else
152 reg &= ~SUN6I_TFR_CTL_CS_LEVEL;
153
154 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
155}
156
157
158static int sun6i_spi_transfer_one(struct spi_master *master,
159 struct spi_device *spi,
160 struct spi_transfer *tfr)
161{
162 struct sun6i_spi *sspi = spi_master_get_devdata(master);
163 unsigned int mclk_rate, div, timeout;
164 unsigned int tx_len = 0;
165 int ret = 0;
166 u32 reg;
167
168 /* We don't support transfer larger than the FIFO */
169 if (tfr->len > SUN6I_FIFO_DEPTH)
170 return -EINVAL;
171
172 reinit_completion(&sspi->done);
173 sspi->tx_buf = tfr->tx_buf;
174 sspi->rx_buf = tfr->rx_buf;
175 sspi->len = tfr->len;
176
177 /* Clear pending interrupts */
178 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, ~0);
179
180 /* Reset FIFO */
181 sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG,
182 SUN6I_FIFO_CTL_RF_RST | SUN6I_FIFO_CTL_TF_RST);
183
184 /*
185 * Setup the transfer control register: Chip Select,
186 * polarities, etc.
187 */
188 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
189
190 if (spi->mode & SPI_CPOL)
191 reg |= SUN6I_TFR_CTL_CPOL;
192 else
193 reg &= ~SUN6I_TFR_CTL_CPOL;
194
195 if (spi->mode & SPI_CPHA)
196 reg |= SUN6I_TFR_CTL_CPHA;
197 else
198 reg &= ~SUN6I_TFR_CTL_CPHA;
199
200 if (spi->mode & SPI_LSB_FIRST)
201 reg |= SUN6I_TFR_CTL_FBS;
202 else
203 reg &= ~SUN6I_TFR_CTL_FBS;
204
205 /*
206 * If it's a TX only transfer, we don't want to fill the RX
207 * FIFO with bogus data
208 */
209 if (sspi->rx_buf)
210 reg &= ~SUN6I_TFR_CTL_DHB;
211 else
212 reg |= SUN6I_TFR_CTL_DHB;
213
214 /* We want to control the chip select manually */
215 reg |= SUN6I_TFR_CTL_CS_MANUAL;
216
217 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
218
219 /* Ensure that we have a parent clock fast enough */
220 mclk_rate = clk_get_rate(sspi->mclk);
221 if (mclk_rate < (2 * spi->max_speed_hz)) {
222 clk_set_rate(sspi->mclk, 2 * spi->max_speed_hz);
223 mclk_rate = clk_get_rate(sspi->mclk);
224 }
225
226 /*
227 * Setup clock divider.
228 *
229 * We have two choices there. Either we can use the clock
230 * divide rate 1, which is calculated thanks to this formula:
231 * SPI_CLK = MOD_CLK / (2 ^ cdr)
232 * Or we can use CDR2, which is calculated with the formula:
233 * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
234 * Wether we use the former or the latter is set through the
235 * DRS bit.
236 *
237 * First try CDR2, and if we can't reach the expected
238 * frequency, fall back to CDR1.
239 */
240 div = mclk_rate / (2 * spi->max_speed_hz);
241 if (div <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) {
242 if (div > 0)
243 div--;
244
245 reg = SUN6I_CLK_CTL_CDR2(div) | SUN6I_CLK_CTL_DRS;
246 } else {
247 div = ilog2(mclk_rate) - ilog2(spi->max_speed_hz);
248 reg = SUN6I_CLK_CTL_CDR1(div);
249 }
250
251 sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg);
252
253 /* Setup the transfer now... */
254 if (sspi->tx_buf)
255 tx_len = tfr->len;
256
257 /* Setup the counters */
258 sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, SUN6I_BURST_CNT(tfr->len));
259 sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, SUN6I_XMIT_CNT(tx_len));
260 sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG,
261 SUN6I_BURST_CTL_CNT_STC(tx_len));
262
263 /* Fill the TX FIFO */
264 sun6i_spi_fill_fifo(sspi, SUN6I_FIFO_DEPTH);
265
266 /* Enable the interrupts */
267 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, SUN6I_INT_CTL_TC);
268
269 /* Start the transfer */
270 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
271 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg | SUN6I_TFR_CTL_XCH);
272
273 timeout = wait_for_completion_timeout(&sspi->done,
274 msecs_to_jiffies(1000));
275 if (!timeout) {
276 ret = -ETIMEDOUT;
277 goto out;
278 }
279
280 sun6i_spi_drain_fifo(sspi, SUN6I_FIFO_DEPTH);
281
282out:
283 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0);
284
285 return ret;
286}
287
288static irqreturn_t sun6i_spi_handler(int irq, void *dev_id)
289{
290 struct sun6i_spi *sspi = dev_id;
291 u32 status = sun6i_spi_read(sspi, SUN6I_INT_STA_REG);
292
293 /* Transfer complete */
294 if (status & SUN6I_INT_CTL_TC) {
295 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC);
296 complete(&sspi->done);
297 return IRQ_HANDLED;
298 }
299
300 return IRQ_NONE;
301}
302
303static int sun6i_spi_runtime_resume(struct device *dev)
304{
305 struct spi_master *master = dev_get_drvdata(dev);
306 struct sun6i_spi *sspi = spi_master_get_devdata(master);
307 int ret;
308
309 ret = clk_prepare_enable(sspi->hclk);
310 if (ret) {
311 dev_err(dev, "Couldn't enable AHB clock\n");
312 goto out;
313 }
314
315 ret = clk_prepare_enable(sspi->mclk);
316 if (ret) {
317 dev_err(dev, "Couldn't enable module clock\n");
318 goto err;
319 }
320
321 ret = reset_control_deassert(sspi->rstc);
322 if (ret) {
323 dev_err(dev, "Couldn't deassert the device from reset\n");
324 goto err2;
325 }
326
327 sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG,
328 SUN6I_GBL_CTL_BUS_ENABLE | SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP);
329
330 return 0;
331
332err2:
333 clk_disable_unprepare(sspi->mclk);
334err:
335 clk_disable_unprepare(sspi->hclk);
336out:
337 return ret;
338}
339
340static int sun6i_spi_runtime_suspend(struct device *dev)
341{
342 struct spi_master *master = dev_get_drvdata(dev);
343 struct sun6i_spi *sspi = spi_master_get_devdata(master);
344
345 reset_control_assert(sspi->rstc);
346 clk_disable_unprepare(sspi->mclk);
347 clk_disable_unprepare(sspi->hclk);
348
349 return 0;
350}
351
352static int sun6i_spi_probe(struct platform_device *pdev)
353{
354 struct spi_master *master;
355 struct sun6i_spi *sspi;
356 struct resource *res;
357 int ret = 0, irq;
358
359 master = spi_alloc_master(&pdev->dev, sizeof(struct sun6i_spi));
360 if (!master) {
361 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
362 return -ENOMEM;
363 }
364
365 platform_set_drvdata(pdev, master);
366 sspi = spi_master_get_devdata(master);
367
368 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
369 sspi->base_addr = devm_ioremap_resource(&pdev->dev, res);
370 if (IS_ERR(sspi->base_addr)) {
371 ret = PTR_ERR(sspi->base_addr);
372 goto err_free_master;
373 }
374
375 irq = platform_get_irq(pdev, 0);
376 if (irq < 0) {
377 dev_err(&pdev->dev, "No spi IRQ specified\n");
378 ret = -ENXIO;
379 goto err_free_master;
380 }
381
382 ret = devm_request_irq(&pdev->dev, irq, sun6i_spi_handler,
383 0, "sun6i-spi", sspi);
384 if (ret) {
385 dev_err(&pdev->dev, "Cannot request IRQ\n");
386 goto err_free_master;
387 }
388
389 sspi->master = master;
390 master->set_cs = sun6i_spi_set_cs;
391 master->transfer_one = sun6i_spi_transfer_one;
392 master->num_chipselect = 4;
393 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
394 master->bits_per_word_mask = SPI_BPW_MASK(8);
395 master->dev.of_node = pdev->dev.of_node;
396 master->auto_runtime_pm = true;
397
398 sspi->hclk = devm_clk_get(&pdev->dev, "ahb");
399 if (IS_ERR(sspi->hclk)) {
400 dev_err(&pdev->dev, "Unable to acquire AHB clock\n");
401 ret = PTR_ERR(sspi->hclk);
402 goto err_free_master;
403 }
404
405 sspi->mclk = devm_clk_get(&pdev->dev, "mod");
406 if (IS_ERR(sspi->mclk)) {
407 dev_err(&pdev->dev, "Unable to acquire module clock\n");
408 ret = PTR_ERR(sspi->mclk);
409 goto err_free_master;
410 }
411
412 init_completion(&sspi->done);
413
414 sspi->rstc = devm_reset_control_get(&pdev->dev, NULL);
415 if (IS_ERR(sspi->rstc)) {
416 dev_err(&pdev->dev, "Couldn't get reset controller\n");
417 ret = PTR_ERR(sspi->rstc);
418 goto err_free_master;
419 }
420
421 /*
422 * This wake-up/shutdown pattern is to be able to have the
423 * device woken up, even if runtime_pm is disabled
424 */
425 ret = sun6i_spi_runtime_resume(&pdev->dev);
426 if (ret) {
427 dev_err(&pdev->dev, "Couldn't resume the device\n");
428 goto err_free_master;
429 }
430
431 pm_runtime_set_active(&pdev->dev);
432 pm_runtime_enable(&pdev->dev);
433 pm_runtime_idle(&pdev->dev);
434
435 ret = devm_spi_register_master(&pdev->dev, master);
436 if (ret) {
437 dev_err(&pdev->dev, "cannot register SPI master\n");
438 goto err_pm_disable;
439 }
440
441 return 0;
442
443err_pm_disable:
444 pm_runtime_disable(&pdev->dev);
445 sun6i_spi_runtime_suspend(&pdev->dev);
446err_free_master:
447 spi_master_put(master);
448 return ret;
449}
450
451static int sun6i_spi_remove(struct platform_device *pdev)
452{
453 pm_runtime_disable(&pdev->dev);
454
455 return 0;
456}
457
458static const struct of_device_id sun6i_spi_match[] = {
459 { .compatible = "allwinner,sun6i-a31-spi", },
460 {}
461};
462MODULE_DEVICE_TABLE(of, sun6i_spi_match);
463
464static const struct dev_pm_ops sun6i_spi_pm_ops = {
465 .runtime_resume = sun6i_spi_runtime_resume,
466 .runtime_suspend = sun6i_spi_runtime_suspend,
467};
468
469static struct platform_driver sun6i_spi_driver = {
470 .probe = sun6i_spi_probe,
471 .remove = sun6i_spi_remove,
472 .driver = {
473 .name = "sun6i-spi",
474 .owner = THIS_MODULE,
475 .of_match_table = sun6i_spi_match,
476 .pm = &sun6i_spi_pm_ops,
477 },
478};
479module_platform_driver(sun6i_spi_driver);
480
481MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>");
482MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
483MODULE_DESCRIPTION("Allwinner A31 SPI controller driver");
484MODULE_LICENSE("GPL");
diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c
index 413c71843492..400649595505 100644
--- a/drivers/spi/spi-tegra114.c
+++ b/drivers/spi/spi-tegra114.c
@@ -23,7 +23,6 @@
23#include <linux/dma-mapping.h> 23#include <linux/dma-mapping.h>
24#include <linux/dmapool.h> 24#include <linux/dmapool.h>
25#include <linux/err.h> 25#include <linux/err.h>
26#include <linux/init.h>
27#include <linux/interrupt.h> 26#include <linux/interrupt.h>
28#include <linux/io.h> 27#include <linux/io.h>
29#include <linux/kernel.h> 28#include <linux/kernel.h>
@@ -172,7 +171,6 @@ struct tegra_spi_data {
172 void __iomem *base; 171 void __iomem *base;
173 phys_addr_t phys; 172 phys_addr_t phys;
174 unsigned irq; 173 unsigned irq;
175 u32 spi_max_frequency;
176 u32 cur_speed; 174 u32 cur_speed;
177 175
178 struct spi_device *cur_spi; 176 struct spi_device *cur_spi;
@@ -761,11 +759,6 @@ static int tegra_spi_setup(struct spi_device *spi)
761 spi->mode & SPI_CPHA ? "" : "~", 759 spi->mode & SPI_CPHA ? "" : "~",
762 spi->max_speed_hz); 760 spi->max_speed_hz);
763 761
764 BUG_ON(spi->chip_select >= MAX_CHIP_SELECT);
765
766 /* Set speed to the spi max fequency if spi device has not set */
767 spi->max_speed_hz = spi->max_speed_hz ? : tspi->spi_max_frequency;
768
769 ret = pm_runtime_get_sync(tspi->dev); 762 ret = pm_runtime_get_sync(tspi->dev);
770 if (ret < 0) { 763 if (ret < 0) {
771 dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret); 764 dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret);
@@ -853,8 +846,8 @@ complete_xfer:
853 SPI_COMMAND1); 846 SPI_COMMAND1);
854 tegra_spi_transfer_delay(xfer->delay_usecs); 847 tegra_spi_transfer_delay(xfer->delay_usecs);
855 goto exit; 848 goto exit;
856 } else if (msg->transfers.prev == &xfer->transfer_list) { 849 } else if (list_is_last(&xfer->transfer_list,
857 /* This is the last transfer in message */ 850 &msg->transfers)) {
858 if (xfer->cs_change) 851 if (xfer->cs_change)
859 tspi->cs_control = spi; 852 tspi->cs_control = spi;
860 else { 853 else {
@@ -1019,16 +1012,6 @@ static irqreturn_t tegra_spi_isr(int irq, void *context_data)
1019 return IRQ_WAKE_THREAD; 1012 return IRQ_WAKE_THREAD;
1020} 1013}
1021 1014
1022static void tegra_spi_parse_dt(struct platform_device *pdev,
1023 struct tegra_spi_data *tspi)
1024{
1025 struct device_node *np = pdev->dev.of_node;
1026
1027 if (of_property_read_u32(np, "spi-max-frequency",
1028 &tspi->spi_max_frequency))
1029 tspi->spi_max_frequency = 25000000; /* 25MHz */
1030}
1031
1032static struct of_device_id tegra_spi_of_match[] = { 1015static struct of_device_id tegra_spi_of_match[] = {
1033 { .compatible = "nvidia,tegra114-spi", }, 1016 { .compatible = "nvidia,tegra114-spi", },
1034 {} 1017 {}
@@ -1050,15 +1033,15 @@ static int tegra_spi_probe(struct platform_device *pdev)
1050 platform_set_drvdata(pdev, master); 1033 platform_set_drvdata(pdev, master);
1051 tspi = spi_master_get_devdata(master); 1034 tspi = spi_master_get_devdata(master);
1052 1035
1053 /* Parse DT */ 1036 if (of_property_read_u32(pdev->dev.of_node, "spi-max-frequency",
1054 tegra_spi_parse_dt(pdev, tspi); 1037 &master->max_speed_hz))
1038 master->max_speed_hz = 25000000; /* 25MHz */
1055 1039
1056 /* the spi->mode bits understood by this driver: */ 1040 /* the spi->mode bits understood by this driver: */
1057 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 1041 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1058 master->setup = tegra_spi_setup; 1042 master->setup = tegra_spi_setup;
1059 master->transfer_one_message = tegra_spi_transfer_one_message; 1043 master->transfer_one_message = tegra_spi_transfer_one_message;
1060 master->num_chipselect = MAX_CHIP_SELECT; 1044 master->num_chipselect = MAX_CHIP_SELECT;
1061 master->bus_num = -1;
1062 master->auto_runtime_pm = true; 1045 master->auto_runtime_pm = true;
1063 1046
1064 tspi->master = master; 1047 tspi->master = master;
diff --git a/drivers/spi/spi-tegra20-sflash.c b/drivers/spi/spi-tegra20-sflash.c
index 08794977f21a..47869ea636e1 100644
--- a/drivers/spi/spi-tegra20-sflash.c
+++ b/drivers/spi/spi-tegra20-sflash.c
@@ -22,7 +22,6 @@
22#include <linux/completion.h> 22#include <linux/completion.h>
23#include <linux/delay.h> 23#include <linux/delay.h>
24#include <linux/err.h> 24#include <linux/err.h>
25#include <linux/init.h>
26#include <linux/interrupt.h> 25#include <linux/interrupt.h>
27#include <linux/io.h> 26#include <linux/io.h>
28#include <linux/kernel.h> 27#include <linux/kernel.h>
@@ -121,7 +120,6 @@ struct tegra_sflash_data {
121 struct reset_control *rst; 120 struct reset_control *rst;
122 void __iomem *base; 121 void __iomem *base;
123 unsigned irq; 122 unsigned irq;
124 u32 spi_max_frequency;
125 u32 cur_speed; 123 u32 cur_speed;
126 124
127 struct spi_device *cur_spi; 125 struct spi_device *cur_spi;
@@ -315,15 +313,6 @@ static int tegra_sflash_start_transfer_one(struct spi_device *spi,
315 return tegra_sflash_start_cpu_based_transfer(tsd, t); 313 return tegra_sflash_start_cpu_based_transfer(tsd, t);
316} 314}
317 315
318static int tegra_sflash_setup(struct spi_device *spi)
319{
320 struct tegra_sflash_data *tsd = spi_master_get_devdata(spi->master);
321
322 /* Set speed to the spi max fequency if spi device has not set */
323 spi->max_speed_hz = spi->max_speed_hz ? : tsd->spi_max_frequency;
324 return 0;
325}
326
327static int tegra_sflash_transfer_one_message(struct spi_master *master, 316static int tegra_sflash_transfer_one_message(struct spi_master *master,
328 struct spi_message *msg) 317 struct spi_message *msg)
329{ 318{
@@ -430,15 +419,6 @@ static irqreturn_t tegra_sflash_isr(int irq, void *context_data)
430 return handle_cpu_based_xfer(tsd); 419 return handle_cpu_based_xfer(tsd);
431} 420}
432 421
433static void tegra_sflash_parse_dt(struct tegra_sflash_data *tsd)
434{
435 struct device_node *np = tsd->dev->of_node;
436
437 if (of_property_read_u32(np, "spi-max-frequency",
438 &tsd->spi_max_frequency))
439 tsd->spi_max_frequency = 25000000; /* 25MHz */
440}
441
442static struct of_device_id tegra_sflash_of_match[] = { 422static struct of_device_id tegra_sflash_of_match[] = {
443 { .compatible = "nvidia,tegra20-sflash", }, 423 { .compatible = "nvidia,tegra20-sflash", },
444 {} 424 {}
@@ -467,11 +447,9 @@ static int tegra_sflash_probe(struct platform_device *pdev)
467 447
468 /* the spi->mode bits understood by this driver: */ 448 /* the spi->mode bits understood by this driver: */
469 master->mode_bits = SPI_CPOL | SPI_CPHA; 449 master->mode_bits = SPI_CPOL | SPI_CPHA;
470 master->setup = tegra_sflash_setup;
471 master->transfer_one_message = tegra_sflash_transfer_one_message; 450 master->transfer_one_message = tegra_sflash_transfer_one_message;
472 master->auto_runtime_pm = true; 451 master->auto_runtime_pm = true;
473 master->num_chipselect = MAX_CHIP_SELECT; 452 master->num_chipselect = MAX_CHIP_SELECT;
474 master->bus_num = -1;
475 453
476 platform_set_drvdata(pdev, master); 454 platform_set_drvdata(pdev, master);
477 tsd = spi_master_get_devdata(master); 455 tsd = spi_master_get_devdata(master);
@@ -479,7 +457,9 @@ static int tegra_sflash_probe(struct platform_device *pdev)
479 tsd->dev = &pdev->dev; 457 tsd->dev = &pdev->dev;
480 spin_lock_init(&tsd->lock); 458 spin_lock_init(&tsd->lock);
481 459
482 tegra_sflash_parse_dt(tsd); 460 if (of_property_read_u32(tsd->dev->of_node, "spi-max-frequency",
461 &master->max_speed_hz))
462 master->max_speed_hz = 25000000; /* 25MHz */
483 463
484 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 464 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
485 tsd->base = devm_ioremap_resource(&pdev->dev, r); 465 tsd->base = devm_ioremap_resource(&pdev->dev, r);
diff --git a/drivers/spi/spi-tegra20-slink.c b/drivers/spi/spi-tegra20-slink.c
index be3a069879c3..e3c1b93e45d1 100644
--- a/drivers/spi/spi-tegra20-slink.c
+++ b/drivers/spi/spi-tegra20-slink.c
@@ -23,7 +23,6 @@
23#include <linux/dma-mapping.h> 23#include <linux/dma-mapping.h>
24#include <linux/dmapool.h> 24#include <linux/dmapool.h>
25#include <linux/err.h> 25#include <linux/err.h>
26#include <linux/init.h>
27#include <linux/interrupt.h> 26#include <linux/interrupt.h>
28#include <linux/io.h> 27#include <linux/io.h>
29#include <linux/kernel.h> 28#include <linux/kernel.h>
@@ -171,7 +170,6 @@ struct tegra_slink_data {
171 void __iomem *base; 170 void __iomem *base;
172 phys_addr_t phys; 171 phys_addr_t phys;
173 unsigned irq; 172 unsigned irq;
174 u32 spi_max_frequency;
175 u32 cur_speed; 173 u32 cur_speed;
176 174
177 struct spi_device *cur_spi; 175 struct spi_device *cur_spi;
@@ -761,10 +759,6 @@ static int tegra_slink_setup(struct spi_device *spi)
761 spi->mode & SPI_CPHA ? "" : "~", 759 spi->mode & SPI_CPHA ? "" : "~",
762 spi->max_speed_hz); 760 spi->max_speed_hz);
763 761
764 BUG_ON(spi->chip_select >= MAX_CHIP_SELECT);
765
766 /* Set speed to the spi max fequency if spi device has not set */
767 spi->max_speed_hz = spi->max_speed_hz ? : tspi->spi_max_frequency;
768 ret = pm_runtime_get_sync(tspi->dev); 762 ret = pm_runtime_get_sync(tspi->dev);
769 if (ret < 0) { 763 if (ret < 0) {
770 dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret); 764 dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret);
@@ -999,15 +993,6 @@ static irqreturn_t tegra_slink_isr(int irq, void *context_data)
999 return IRQ_WAKE_THREAD; 993 return IRQ_WAKE_THREAD;
1000} 994}
1001 995
1002static void tegra_slink_parse_dt(struct tegra_slink_data *tspi)
1003{
1004 struct device_node *np = tspi->dev->of_node;
1005
1006 if (of_property_read_u32(np, "spi-max-frequency",
1007 &tspi->spi_max_frequency))
1008 tspi->spi_max_frequency = 25000000; /* 25MHz */
1009}
1010
1011static const struct tegra_slink_chip_data tegra30_spi_cdata = { 996static const struct tegra_slink_chip_data tegra30_spi_cdata = {
1012 .cs_hold_time = true, 997 .cs_hold_time = true,
1013}; 998};
@@ -1053,7 +1038,6 @@ static int tegra_slink_probe(struct platform_device *pdev)
1053 master->unprepare_message = tegra_slink_unprepare_message; 1038 master->unprepare_message = tegra_slink_unprepare_message;
1054 master->auto_runtime_pm = true; 1039 master->auto_runtime_pm = true;
1055 master->num_chipselect = MAX_CHIP_SELECT; 1040 master->num_chipselect = MAX_CHIP_SELECT;
1056 master->bus_num = -1;
1057 1041
1058 platform_set_drvdata(pdev, master); 1042 platform_set_drvdata(pdev, master);
1059 tspi = spi_master_get_devdata(master); 1043 tspi = spi_master_get_devdata(master);
@@ -1062,7 +1046,9 @@ static int tegra_slink_probe(struct platform_device *pdev)
1062 tspi->chip_data = cdata; 1046 tspi->chip_data = cdata;
1063 spin_lock_init(&tspi->lock); 1047 spin_lock_init(&tspi->lock);
1064 1048
1065 tegra_slink_parse_dt(tspi); 1049 if (of_property_read_u32(tspi->dev->of_node, "spi-max-frequency",
1050 &master->max_speed_hz))
1051 master->max_speed_hz = 25000000; /* 25MHz */
1066 1052
1067 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1053 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1068 if (!r) { 1054 if (!r) {
diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
index 3d09265b5133..6c211d1910b0 100644
--- a/drivers/spi/spi-ti-qspi.c
+++ b/drivers/spi/spi-ti-qspi.c
@@ -429,13 +429,13 @@ static int ti_qspi_probe(struct platform_device *pdev)
429 429
430 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD; 430 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD;
431 431
432 master->bus_num = -1;
433 master->flags = SPI_MASTER_HALF_DUPLEX; 432 master->flags = SPI_MASTER_HALF_DUPLEX;
434 master->setup = ti_qspi_setup; 433 master->setup = ti_qspi_setup;
435 master->auto_runtime_pm = true; 434 master->auto_runtime_pm = true;
436 master->transfer_one_message = ti_qspi_start_transfer_one; 435 master->transfer_one_message = ti_qspi_start_transfer_one;
437 master->dev.of_node = pdev->dev.of_node; 436 master->dev.of_node = pdev->dev.of_node;
438 master->bits_per_word_mask = BIT(32 - 1) | BIT(16 - 1) | BIT(8 - 1); 437 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
438 SPI_BPW_MASK(8);
439 439
440 if (!of_property_read_u32(np, "num-cs", &num_cs)) 440 if (!of_property_read_u32(np, "num-cs", &num_cs))
441 master->num_chipselect = num_cs; 441 master->num_chipselect = num_cs;
@@ -461,7 +461,6 @@ static int ti_qspi_probe(struct platform_device *pdev)
461 if (res_mmap == NULL) { 461 if (res_mmap == NULL) {
462 dev_err(&pdev->dev, 462 dev_err(&pdev->dev,
463 "memory mapped resource not required\n"); 463 "memory mapped resource not required\n");
464 return -ENODEV;
465 } 464 }
466 } 465 }
467 466
diff --git a/drivers/spi/spi-ti-ssp.c b/drivers/spi/spi-ti-ssp.c
deleted file mode 100644
index 7d20e121e4c1..000000000000
--- a/drivers/spi/spi-ti-ssp.c
+++ /dev/null
@@ -1,378 +0,0 @@
1/*
2 * Sequencer Serial Port (SSP) based SPI master driver
3 *
4 * Copyright (C) 2010 Texas Instruments Inc
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#include <linux/kernel.h>
22#include <linux/err.h>
23#include <linux/completion.h>
24#include <linux/delay.h>
25#include <linux/module.h>
26#include <linux/platform_device.h>
27#include <linux/spi/spi.h>
28#include <linux/mfd/ti_ssp.h>
29
30#define MODE_BITS (SPI_CPHA | SPI_CPOL | SPI_CS_HIGH)
31
32struct ti_ssp_spi {
33 struct spi_master *master;
34 struct device *dev;
35 spinlock_t lock;
36 struct list_head msg_queue;
37 struct completion complete;
38 bool shutdown;
39 struct workqueue_struct *workqueue;
40 struct work_struct work;
41 u8 mode, bpw;
42 int cs_active;
43 u32 pc_en, pc_dis, pc_wr, pc_rd;
44 void (*select)(int cs);
45};
46
47static u32 ti_ssp_spi_rx(struct ti_ssp_spi *hw)
48{
49 u32 ret;
50
51 ti_ssp_run(hw->dev, hw->pc_rd, 0, &ret);
52 return ret;
53}
54
55static void ti_ssp_spi_tx(struct ti_ssp_spi *hw, u32 data)
56{
57 ti_ssp_run(hw->dev, hw->pc_wr, data << (32 - hw->bpw), NULL);
58}
59
60static int ti_ssp_spi_txrx(struct ti_ssp_spi *hw, struct spi_message *msg,
61 struct spi_transfer *t)
62{
63 int count;
64
65 if (hw->bpw <= 8) {
66 u8 *rx = t->rx_buf;
67 const u8 *tx = t->tx_buf;
68
69 for (count = 0; count < t->len; count += 1) {
70 if (t->tx_buf)
71 ti_ssp_spi_tx(hw, *tx++);
72 if (t->rx_buf)
73 *rx++ = ti_ssp_spi_rx(hw);
74 }
75 } else if (hw->bpw <= 16) {
76 u16 *rx = t->rx_buf;
77 const u16 *tx = t->tx_buf;
78
79 for (count = 0; count < t->len; count += 2) {
80 if (t->tx_buf)
81 ti_ssp_spi_tx(hw, *tx++);
82 if (t->rx_buf)
83 *rx++ = ti_ssp_spi_rx(hw);
84 }
85 } else {
86 u32 *rx = t->rx_buf;
87 const u32 *tx = t->tx_buf;
88
89 for (count = 0; count < t->len; count += 4) {
90 if (t->tx_buf)
91 ti_ssp_spi_tx(hw, *tx++);
92 if (t->rx_buf)
93 *rx++ = ti_ssp_spi_rx(hw);
94 }
95 }
96
97 msg->actual_length += count; /* bytes transferred */
98
99 dev_dbg(&msg->spi->dev, "xfer %s%s, %d bytes, %d bpw, count %d%s\n",
100 t->tx_buf ? "tx" : "", t->rx_buf ? "rx" : "", t->len,
101 hw->bpw, count, (count < t->len) ? " (under)" : "");
102
103 return (count < t->len) ? -EIO : 0; /* left over data */
104}
105
106static void ti_ssp_spi_chip_select(struct ti_ssp_spi *hw, int cs_active)
107{
108 cs_active = !!cs_active;
109 if (cs_active == hw->cs_active)
110 return;
111 ti_ssp_run(hw->dev, cs_active ? hw->pc_en : hw->pc_dis, 0, NULL);
112 hw->cs_active = cs_active;
113}
114
115#define __SHIFT_OUT(bits) (SSP_OPCODE_SHIFT | SSP_OUT_MODE | \
116 cs_en | clk | SSP_COUNT((bits) * 2 - 1))
117#define __SHIFT_IN(bits) (SSP_OPCODE_SHIFT | SSP_IN_MODE | \
118 cs_en | clk | SSP_COUNT((bits) * 2 - 1))
119
120static int ti_ssp_spi_setup_transfer(struct ti_ssp_spi *hw, u8 bpw, u8 mode)
121{
122 int error, idx = 0;
123 u32 seqram[16];
124 u32 cs_en, cs_dis, clk;
125 u32 topbits, botbits;
126
127 mode &= MODE_BITS;
128 if (mode == hw->mode && bpw == hw->bpw)
129 return 0;
130
131 cs_en = (mode & SPI_CS_HIGH) ? SSP_CS_HIGH : SSP_CS_LOW;
132 cs_dis = (mode & SPI_CS_HIGH) ? SSP_CS_LOW : SSP_CS_HIGH;
133 clk = (mode & SPI_CPOL) ? SSP_CLK_HIGH : SSP_CLK_LOW;
134
135 /* Construct instructions */
136
137 /* Disable Chip Select */
138 hw->pc_dis = idx;
139 seqram[idx++] = SSP_OPCODE_DIRECT | SSP_OUT_MODE | cs_dis | clk;
140 seqram[idx++] = SSP_OPCODE_STOP | SSP_OUT_MODE | cs_dis | clk;
141
142 /* Enable Chip Select */
143 hw->pc_en = idx;
144 seqram[idx++] = SSP_OPCODE_DIRECT | SSP_OUT_MODE | cs_en | clk;
145 seqram[idx++] = SSP_OPCODE_STOP | SSP_OUT_MODE | cs_en | clk;
146
147 /* Reads and writes need to be split for bpw > 16 */
148 topbits = (bpw > 16) ? 16 : bpw;
149 botbits = bpw - topbits;
150
151 /* Write */
152 hw->pc_wr = idx;
153 seqram[idx++] = __SHIFT_OUT(topbits) | SSP_ADDR_REG;
154 if (botbits)
155 seqram[idx++] = __SHIFT_OUT(botbits) | SSP_DATA_REG;
156 seqram[idx++] = SSP_OPCODE_STOP | SSP_OUT_MODE | cs_en | clk;
157
158 /* Read */
159 hw->pc_rd = idx;
160 if (botbits)
161 seqram[idx++] = __SHIFT_IN(botbits) | SSP_ADDR_REG;
162 seqram[idx++] = __SHIFT_IN(topbits) | SSP_DATA_REG;
163 seqram[idx++] = SSP_OPCODE_STOP | SSP_OUT_MODE | cs_en | clk;
164
165 error = ti_ssp_load(hw->dev, 0, seqram, idx);
166 if (error < 0)
167 return error;
168
169 error = ti_ssp_set_mode(hw->dev, ((mode & SPI_CPHA) ?
170 0 : SSP_EARLY_DIN));
171 if (error < 0)
172 return error;
173
174 hw->bpw = bpw;
175 hw->mode = mode;
176
177 return error;
178}
179
180static void ti_ssp_spi_work(struct work_struct *work)
181{
182 struct ti_ssp_spi *hw = container_of(work, struct ti_ssp_spi, work);
183
184 spin_lock(&hw->lock);
185
186 while (!list_empty(&hw->msg_queue)) {
187 struct spi_message *m;
188 struct spi_device *spi;
189 struct spi_transfer *t = NULL;
190 int status = 0;
191
192 m = container_of(hw->msg_queue.next, struct spi_message,
193 queue);
194
195 list_del_init(&m->queue);
196
197 spin_unlock(&hw->lock);
198
199 spi = m->spi;
200
201 if (hw->select)
202 hw->select(spi->chip_select);
203
204 list_for_each_entry(t, &m->transfers, transfer_list) {
205 int bpw = spi->bits_per_word;
206 int xfer_status;
207
208 if (t->bits_per_word)
209 bpw = t->bits_per_word;
210
211 if (ti_ssp_spi_setup_transfer(hw, bpw, spi->mode) < 0)
212 break;
213
214 ti_ssp_spi_chip_select(hw, 1);
215
216 xfer_status = ti_ssp_spi_txrx(hw, m, t);
217 if (xfer_status < 0)
218 status = xfer_status;
219
220 if (t->delay_usecs)
221 udelay(t->delay_usecs);
222
223 if (t->cs_change)
224 ti_ssp_spi_chip_select(hw, 0);
225 }
226
227 ti_ssp_spi_chip_select(hw, 0);
228 m->status = status;
229 m->complete(m->context);
230
231 spin_lock(&hw->lock);
232 }
233
234 if (hw->shutdown)
235 complete(&hw->complete);
236
237 spin_unlock(&hw->lock);
238}
239
240static int ti_ssp_spi_transfer(struct spi_device *spi, struct spi_message *m)
241{
242 struct ti_ssp_spi *hw;
243 struct spi_transfer *t;
244 int error = 0;
245
246 m->actual_length = 0;
247 m->status = -EINPROGRESS;
248
249 hw = spi_master_get_devdata(spi->master);
250
251 if (list_empty(&m->transfers) || !m->complete)
252 return -EINVAL;
253
254 list_for_each_entry(t, &m->transfers, transfer_list) {
255 if (t->len && !(t->rx_buf || t->tx_buf)) {
256 dev_err(&spi->dev, "invalid xfer, no buffer\n");
257 return -EINVAL;
258 }
259
260 if (t->len && t->rx_buf && t->tx_buf) {
261 dev_err(&spi->dev, "invalid xfer, full duplex\n");
262 return -EINVAL;
263 }
264 }
265
266 spin_lock(&hw->lock);
267 if (hw->shutdown) {
268 error = -ESHUTDOWN;
269 goto error_unlock;
270 }
271 list_add_tail(&m->queue, &hw->msg_queue);
272 queue_work(hw->workqueue, &hw->work);
273error_unlock:
274 spin_unlock(&hw->lock);
275 return error;
276}
277
278static int ti_ssp_spi_probe(struct platform_device *pdev)
279{
280 const struct ti_ssp_spi_data *pdata;
281 struct ti_ssp_spi *hw;
282 struct spi_master *master;
283 struct device *dev = &pdev->dev;
284 int error = 0;
285
286 pdata = dev_get_platdata(dev);
287 if (!pdata) {
288 dev_err(dev, "platform data not found\n");
289 return -EINVAL;
290 }
291
292 master = spi_alloc_master(dev, sizeof(struct ti_ssp_spi));
293 if (!master) {
294 dev_err(dev, "cannot allocate SPI master\n");
295 return -ENOMEM;
296 }
297
298 hw = spi_master_get_devdata(master);
299 platform_set_drvdata(pdev, hw);
300
301 hw->master = master;
302 hw->dev = dev;
303 hw->select = pdata->select;
304
305 spin_lock_init(&hw->lock);
306 init_completion(&hw->complete);
307 INIT_LIST_HEAD(&hw->msg_queue);
308 INIT_WORK(&hw->work, ti_ssp_spi_work);
309
310 hw->workqueue = create_singlethread_workqueue(dev_name(dev));
311 if (!hw->workqueue) {
312 error = -ENOMEM;
313 dev_err(dev, "work queue creation failed\n");
314 goto error_wq;
315 }
316
317 error = ti_ssp_set_iosel(hw->dev, pdata->iosel);
318 if (error < 0) {
319 dev_err(dev, "io setup failed\n");
320 goto error_iosel;
321 }
322
323 master->bus_num = pdev->id;
324 master->num_chipselect = pdata->num_cs;
325 master->mode_bits = MODE_BITS;
326 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
327 master->flags = SPI_MASTER_HALF_DUPLEX;
328 master->transfer = ti_ssp_spi_transfer;
329
330 error = spi_register_master(master);
331 if (error) {
332 dev_err(dev, "master registration failed\n");
333 goto error_reg;
334 }
335
336 return 0;
337
338error_reg:
339error_iosel:
340 destroy_workqueue(hw->workqueue);
341error_wq:
342 spi_master_put(master);
343 return error;
344}
345
346static int ti_ssp_spi_remove(struct platform_device *pdev)
347{
348 struct ti_ssp_spi *hw = platform_get_drvdata(pdev);
349 int error;
350
351 hw->shutdown = 1;
352 while (!list_empty(&hw->msg_queue)) {
353 error = wait_for_completion_interruptible(&hw->complete);
354 if (error < 0) {
355 hw->shutdown = 0;
356 return error;
357 }
358 }
359 destroy_workqueue(hw->workqueue);
360 spi_unregister_master(hw->master);
361
362 return 0;
363}
364
365static struct platform_driver ti_ssp_spi_driver = {
366 .probe = ti_ssp_spi_probe,
367 .remove = ti_ssp_spi_remove,
368 .driver = {
369 .name = "ti-ssp-spi",
370 .owner = THIS_MODULE,
371 },
372};
373module_platform_driver(ti_ssp_spi_driver);
374
375MODULE_DESCRIPTION("SSP SPI Master");
376MODULE_AUTHOR("Cyril Chemparathy");
377MODULE_LICENSE("GPL");
378MODULE_ALIAS("platform:ti-ssp-spi");
diff --git a/drivers/spi/spi-topcliff-pch.c b/drivers/spi/spi-topcliff-pch.c
index 88eb57e858b3..f406b30af961 100644
--- a/drivers/spi/spi-topcliff-pch.c
+++ b/drivers/spi/spi-topcliff-pch.c
@@ -332,7 +332,7 @@ static void pch_spi_handler_sub(struct pch_spi_data *data, u32 reg_spsr_val,
332 data->transfer_active = false; 332 data->transfer_active = false;
333 wake_up(&data->wait); 333 wake_up(&data->wait);
334 } else { 334 } else {
335 dev_err(&data->master->dev, 335 dev_vdbg(&data->master->dev,
336 "%s : Transfer is not completed", 336 "%s : Transfer is not completed",
337 __func__); 337 __func__);
338 } 338 }
@@ -464,20 +464,6 @@ static void pch_spi_reset(struct spi_master *master)
464 pch_spi_writereg(master, PCH_SRST, 0x0); 464 pch_spi_writereg(master, PCH_SRST, 0x0);
465} 465}
466 466
467static int pch_spi_setup(struct spi_device *pspi)
468{
469 /* Check baud rate setting */
470 /* if baud rate of chip is greater than
471 max we can support,return error */
472 if ((pspi->max_speed_hz) > PCH_MAX_BAUDRATE)
473 pspi->max_speed_hz = PCH_MAX_BAUDRATE;
474
475 dev_dbg(&pspi->dev, "%s MODE = %x\n", __func__,
476 (pspi->mode) & (SPI_CPOL | SPI_CPHA));
477
478 return 0;
479}
480
481static int pch_spi_transfer(struct spi_device *pspi, struct spi_message *pmsg) 467static int pch_spi_transfer(struct spi_device *pspi, struct spi_message *pmsg)
482{ 468{
483 469
@@ -486,23 +472,6 @@ static int pch_spi_transfer(struct spi_device *pspi, struct spi_message *pmsg)
486 int retval; 472 int retval;
487 unsigned long flags; 473 unsigned long flags;
488 474
489 /* validate spi message and baud rate */
490 if (unlikely(list_empty(&pmsg->transfers) == 1)) {
491 dev_err(&pspi->dev, "%s list empty\n", __func__);
492 retval = -EINVAL;
493 goto err_out;
494 }
495
496 if (unlikely(pspi->max_speed_hz == 0)) {
497 dev_err(&pspi->dev, "%s pch_spi_transfer maxspeed=%d\n",
498 __func__, pspi->max_speed_hz);
499 retval = -EINVAL;
500 goto err_out;
501 }
502
503 dev_dbg(&pspi->dev,
504 "%s Transfer List not empty. Transfer Speed is set.\n", __func__);
505
506 spin_lock_irqsave(&data->lock, flags); 475 spin_lock_irqsave(&data->lock, flags);
507 /* validate Tx/Rx buffers and Transfer length */ 476 /* validate Tx/Rx buffers and Transfer length */
508 list_for_each_entry(transfer, &pmsg->transfers, transfer_list) { 477 list_for_each_entry(transfer, &pmsg->transfers, transfer_list) {
@@ -523,10 +492,6 @@ static int pch_spi_transfer(struct spi_device *pspi, struct spi_message *pmsg)
523 dev_dbg(&pspi->dev, 492 dev_dbg(&pspi->dev,
524 "%s Tx/Rx buffer valid. Transfer length valid\n", 493 "%s Tx/Rx buffer valid. Transfer length valid\n",
525 __func__); 494 __func__);
526
527 /* if baud rate has been specified validate the same */
528 if (transfer->speed_hz > PCH_MAX_BAUDRATE)
529 transfer->speed_hz = PCH_MAX_BAUDRATE;
530 } 495 }
531 spin_unlock_irqrestore(&data->lock, flags); 496 spin_unlock_irqrestore(&data->lock, flags);
532 497
@@ -1151,8 +1116,7 @@ static void pch_spi_handle_dma(struct pch_spi_data *data, int *bpw)
1151 dma->nent = num; 1116 dma->nent = num;
1152 dma->desc_tx = desc_tx; 1117 dma->desc_tx = desc_tx;
1153 1118
1154 dev_dbg(&data->master->dev, "\n%s:Pulling down SSN low - writing " 1119 dev_dbg(&data->master->dev, "%s:Pulling down SSN low - writing 0x2 to SSNXCR\n", __func__);
1155 "0x2 to SSNXCR\n", __func__);
1156 1120
1157 spin_lock_irqsave(&data->lock, flags); 1121 spin_lock_irqsave(&data->lock, flags);
1158 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW); 1122 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW);
@@ -1418,10 +1382,10 @@ static int pch_spi_pd_probe(struct platform_device *plat_dev)
1418 1382
1419 /* initialize members of SPI master */ 1383 /* initialize members of SPI master */
1420 master->num_chipselect = PCH_MAX_CS; 1384 master->num_chipselect = PCH_MAX_CS;
1421 master->setup = pch_spi_setup;
1422 master->transfer = pch_spi_transfer; 1385 master->transfer = pch_spi_transfer;
1423 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; 1386 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
1424 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16); 1387 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
1388 master->max_speed_hz = PCH_MAX_BAUDRATE;
1425 1389
1426 data->board_dat = board_dat; 1390 data->board_dat = board_dat;
1427 data->plat_dev = plat_dev; 1391 data->plat_dev = plat_dev;
@@ -1605,8 +1569,7 @@ static struct platform_driver pch_spi_pd_driver = {
1605 .resume = pch_spi_pd_resume 1569 .resume = pch_spi_pd_resume
1606}; 1570};
1607 1571
1608static int pch_spi_probe(struct pci_dev *pdev, 1572static int pch_spi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1609 const struct pci_device_id *id)
1610{ 1573{
1611 struct pch_spi_board_data *board_dat; 1574 struct pch_spi_board_data *board_dat;
1612 struct platform_device *pd_dev = NULL; 1575 struct platform_device *pd_dev = NULL;
@@ -1676,6 +1639,8 @@ static int pch_spi_probe(struct pci_dev *pdev,
1676 return 0; 1639 return 0;
1677 1640
1678err_platform_device: 1641err_platform_device:
1642 while (--i >= 0)
1643 platform_device_unregister(pd_dev_save->pd_save[i]);
1679 pci_disable_device(pdev); 1644 pci_disable_device(pdev);
1680pci_enable_device: 1645pci_enable_device:
1681 pci_release_regions(pdev); 1646 pci_release_regions(pdev);
diff --git a/drivers/spi/spi-txx9.c b/drivers/spi/spi-txx9.c
index 57a14977101c..5f183baa91a9 100644
--- a/drivers/spi/spi-txx9.c
+++ b/drivers/spi/spi-txx9.c
@@ -80,7 +80,6 @@ struct txx9spi {
80 void __iomem *membase; 80 void __iomem *membase;
81 int baseclk; 81 int baseclk;
82 struct clk *clk; 82 struct clk *clk;
83 u32 max_speed_hz, min_speed_hz;
84 int last_chipselect; 83 int last_chipselect;
85 int last_chipselect_val; 84 int last_chipselect_val;
86}; 85};
@@ -117,9 +116,7 @@ static int txx9spi_setup(struct spi_device *spi)
117{ 116{
118 struct txx9spi *c = spi_master_get_devdata(spi->master); 117 struct txx9spi *c = spi_master_get_devdata(spi->master);
119 118
120 if (!spi->max_speed_hz 119 if (!spi->max_speed_hz)
121 || spi->max_speed_hz > c->max_speed_hz
122 || spi->max_speed_hz < c->min_speed_hz)
123 return -EINVAL; 120 return -EINVAL;
124 121
125 if (gpio_direction_output(spi->chip_select, 122 if (gpio_direction_output(spi->chip_select,
@@ -310,15 +307,8 @@ static int txx9spi_transfer(struct spi_device *spi, struct spi_message *m)
310 307
311 /* check each transfer's parameters */ 308 /* check each transfer's parameters */
312 list_for_each_entry(t, &m->transfers, transfer_list) { 309 list_for_each_entry(t, &m->transfers, transfer_list) {
313 u32 speed_hz = t->speed_hz ? : spi->max_speed_hz;
314 u8 bits_per_word = t->bits_per_word;
315
316 if (!t->tx_buf && !t->rx_buf && t->len) 310 if (!t->tx_buf && !t->rx_buf && t->len)
317 return -EINVAL; 311 return -EINVAL;
318 if (t->len & ((bits_per_word >> 3) - 1))
319 return -EINVAL;
320 if (speed_hz < c->min_speed_hz || speed_hz > c->max_speed_hz)
321 return -EINVAL;
322 } 312 }
323 313
324 spin_lock_irqsave(&c->lock, flags); 314 spin_lock_irqsave(&c->lock, flags);
@@ -361,17 +351,12 @@ static int txx9spi_probe(struct platform_device *dev)
361 goto exit; 351 goto exit;
362 } 352 }
363 c->baseclk = clk_get_rate(c->clk); 353 c->baseclk = clk_get_rate(c->clk);
364 c->min_speed_hz = DIV_ROUND_UP(c->baseclk, SPI_MAX_DIVIDER + 1); 354 master->min_speed_hz = DIV_ROUND_UP(c->baseclk, SPI_MAX_DIVIDER + 1);
365 c->max_speed_hz = c->baseclk / (SPI_MIN_DIVIDER + 1); 355 master->max_speed_hz = c->baseclk / (SPI_MIN_DIVIDER + 1);
366 356
367 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 357 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
368 if (!res) 358 c->membase = devm_ioremap_resource(&dev->dev, res);
369 goto exit_busy; 359 if (IS_ERR(c->membase))
370 if (!devm_request_mem_region(&dev->dev, res->start, resource_size(res),
371 "spi_txx9"))
372 goto exit_busy;
373 c->membase = devm_ioremap(&dev->dev, res->start, resource_size(res));
374 if (!c->membase)
375 goto exit_busy; 360 goto exit_busy;
376 361
377 /* enter config mode */ 362 /* enter config mode */
diff --git a/drivers/spi/spi-xcomm.c b/drivers/spi/spi-xcomm.c
index 24c40b13dab1..bb478dccf1d8 100644
--- a/drivers/spi/spi-xcomm.c
+++ b/drivers/spi/spi-xcomm.c
@@ -8,7 +8,6 @@
8 */ 8 */
9 9
10#include <linux/kernel.h> 10#include <linux/kernel.h>
11#include <linux/init.h>
12#include <linux/module.h> 11#include <linux/module.h>
13#include <linux/delay.h> 12#include <linux/delay.h>
14#include <linux/i2c.h> 13#include <linux/i2c.h>
@@ -74,15 +73,13 @@ static void spi_xcomm_chipselect(struct spi_xcomm *spi_xcomm,
74static int spi_xcomm_setup_transfer(struct spi_xcomm *spi_xcomm, 73static int spi_xcomm_setup_transfer(struct spi_xcomm *spi_xcomm,
75 struct spi_device *spi, struct spi_transfer *t, unsigned int *settings) 74 struct spi_device *spi, struct spi_transfer *t, unsigned int *settings)
76{ 75{
77 unsigned int speed;
78
79 if (t->len > 62) 76 if (t->len > 62)
80 return -EINVAL; 77 return -EINVAL;
81 78
82 speed = t->speed_hz ? t->speed_hz : spi->max_speed_hz; 79 if (t->speed_hz != spi_xcomm->current_speed) {
80 unsigned int divider;
83 81
84 if (speed != spi_xcomm->current_speed) { 82 divider = DIV_ROUND_UP(SPI_XCOMM_CLOCK, t->speed_hz);
85 unsigned int divider = DIV_ROUND_UP(SPI_XCOMM_CLOCK, speed);
86 if (divider >= 64) 83 if (divider >= 64)
87 *settings |= SPI_XCOMM_SETTINGS_CLOCK_DIV_64; 84 *settings |= SPI_XCOMM_SETTINGS_CLOCK_DIV_64;
88 else if (divider >= 16) 85 else if (divider >= 16)
@@ -90,7 +87,7 @@ static int spi_xcomm_setup_transfer(struct spi_xcomm *spi_xcomm,
90 else 87 else
91 *settings |= SPI_XCOMM_SETTINGS_CLOCK_DIV_4; 88 *settings |= SPI_XCOMM_SETTINGS_CLOCK_DIV_4;
92 89
93 spi_xcomm->current_speed = speed; 90 spi_xcomm->current_speed = t->speed_hz;
94 } 91 }
95 92
96 if (spi->mode & SPI_CPOL) 93 if (spi->mode & SPI_CPOL)
@@ -148,8 +145,6 @@ static int spi_xcomm_transfer_one(struct spi_master *master,
148 int status = 0; 145 int status = 0;
149 bool is_last; 146 bool is_last;
150 147
151 is_first = true;
152
153 spi_xcomm_chipselect(spi_xcomm, spi, true); 148 spi_xcomm_chipselect(spi_xcomm, spi, true);
154 149
155 list_for_each_entry(t, &msg->transfers, transfer_list) { 150 list_for_each_entry(t, &msg->transfers, transfer_list) {
diff --git a/drivers/spi/spi-xilinx.c b/drivers/spi/spi-xilinx.c
index 6d4ce4615163..a3b0b9944bf0 100644
--- a/drivers/spi/spi-xilinx.c
+++ b/drivers/spi/spi-xilinx.c
@@ -14,7 +14,6 @@
14 */ 14 */
15 15
16#include <linux/module.h> 16#include <linux/module.h>
17#include <linux/init.h>
18#include <linux/interrupt.h> 17#include <linux/interrupt.h>
19#include <linux/of.h> 18#include <linux/of.h>
20#include <linux/platform_device.h> 19#include <linux/platform_device.h>
@@ -88,10 +87,10 @@ struct xilinx_spi {
88 const u8 *tx_ptr; /* pointer in the Rx buffer */ 87 const u8 *tx_ptr; /* pointer in the Rx buffer */
89 int remaining_bytes; /* the number of bytes left to transfer */ 88 int remaining_bytes; /* the number of bytes left to transfer */
90 u8 bits_per_word; 89 u8 bits_per_word;
91 unsigned int (*read_fn) (void __iomem *); 90 unsigned int (*read_fn)(void __iomem *);
92 void (*write_fn) (u32, void __iomem *); 91 void (*write_fn)(u32, void __iomem *);
93 void (*tx_fn) (struct xilinx_spi *); 92 void (*tx_fn)(struct xilinx_spi *);
94 void (*rx_fn) (struct xilinx_spi *); 93 void (*rx_fn)(struct xilinx_spi *);
95}; 94};
96 95
97static void xspi_write32(u32 val, void __iomem *addr) 96static void xspi_write32(u32 val, void __iomem *addr)
@@ -209,26 +208,11 @@ static void xilinx_spi_chipselect(struct spi_device *spi, int is_on)
209} 208}
210 209
211/* spi_bitbang requires custom setup_transfer() to be defined if there is a 210/* spi_bitbang requires custom setup_transfer() to be defined if there is a
212 * custom txrx_bufs(). We have nothing to setup here as the SPI IP block 211 * custom txrx_bufs().
213 * supports 8 or 16 bits per word which cannot be changed in software.
214 * SPI clock can't be changed in software either.
215 * Check for correct bits per word. Chip select delay calculations could be
216 * added here as soon as bitbang_work() can be made aware of the delay value.
217 */ 212 */
218static int xilinx_spi_setup_transfer(struct spi_device *spi, 213static int xilinx_spi_setup_transfer(struct spi_device *spi,
219 struct spi_transfer *t) 214 struct spi_transfer *t)
220{ 215{
221 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
222 u8 bits_per_word;
223
224 bits_per_word = (t && t->bits_per_word)
225 ? t->bits_per_word : spi->bits_per_word;
226 if (bits_per_word != xspi->bits_per_word) {
227 dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
228 __func__, bits_per_word);
229 return -EINVAL;
230 }
231
232 return 0; 216 return 0;
233} 217}
234 218
@@ -407,6 +391,7 @@ static int xilinx_spi_probe(struct platform_device *pdev)
407 xspi->write_fn = xspi_write32_be; 391 xspi->write_fn = xspi_write32_be;
408 } 392 }
409 393
394 master->bits_per_word_mask = SPI_BPW_MASK(bits_per_word);
410 xspi->bits_per_word = bits_per_word; 395 xspi->bits_per_word = bits_per_word;
411 if (xspi->bits_per_word == 8) { 396 if (xspi->bits_per_word == 8) {
412 xspi->tx_fn = xspi_tx8; 397 xspi->tx_fn = xspi_tx8;
diff --git a/drivers/spi/spi-xtensa-xtfpga.c b/drivers/spi/spi-xtensa-xtfpga.c
new file mode 100644
index 000000000000..41e158187f9d
--- /dev/null
+++ b/drivers/spi/spi-xtensa-xtfpga.c
@@ -0,0 +1,170 @@
1/*
2 * Xtensa xtfpga SPI controller driver
3 *
4 * Copyright (c) 2014 Cadence Design Systems Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/delay.h>
12#include <linux/io.h>
13#include <linux/module.h>
14#include <linux/of.h>
15#include <linux/platform_device.h>
16#include <linux/spi/spi.h>
17#include <linux/spi/spi_bitbang.h>
18
19#define XTFPGA_SPI_NAME "xtfpga_spi"
20
21#define XTFPGA_SPI_START 0x0
22#define XTFPGA_SPI_BUSY 0x4
23#define XTFPGA_SPI_DATA 0x8
24
25#define BUSY_WAIT_US 100
26
27struct xtfpga_spi {
28 struct spi_bitbang bitbang;
29 void __iomem *regs;
30 u32 data;
31 unsigned data_sz;
32};
33
34static inline void xtfpga_spi_write32(const struct xtfpga_spi *spi,
35 unsigned addr, u32 val)
36{
37 iowrite32(val, spi->regs + addr);
38}
39
40static inline unsigned int xtfpga_spi_read32(const struct xtfpga_spi *spi,
41 unsigned addr)
42{
43 return ioread32(spi->regs + addr);
44}
45
46static inline void xtfpga_spi_wait_busy(struct xtfpga_spi *xspi)
47{
48 unsigned i;
49 for (i = 0; xtfpga_spi_read32(xspi, XTFPGA_SPI_BUSY) &&
50 i < BUSY_WAIT_US; ++i)
51 udelay(1);
52 WARN_ON_ONCE(i == BUSY_WAIT_US);
53}
54
55static u32 xtfpga_spi_txrx_word(struct spi_device *spi, unsigned nsecs,
56 u32 v, u8 bits)
57{
58 struct xtfpga_spi *xspi = spi_master_get_devdata(spi->master);
59
60 xspi->data = (xspi->data << bits) | (v & GENMASK(bits - 1, 0));
61 xspi->data_sz += bits;
62 if (xspi->data_sz >= 16) {
63 xtfpga_spi_write32(xspi, XTFPGA_SPI_DATA,
64 xspi->data >> (xspi->data_sz - 16));
65 xspi->data_sz -= 16;
66 xtfpga_spi_write32(xspi, XTFPGA_SPI_START, 1);
67 xtfpga_spi_wait_busy(xspi);
68 xtfpga_spi_write32(xspi, XTFPGA_SPI_START, 0);
69 }
70
71 return 0;
72}
73
74static void xtfpga_spi_chipselect(struct spi_device *spi, int is_on)
75{
76 struct xtfpga_spi *xspi = spi_master_get_devdata(spi->master);
77
78 WARN_ON(xspi->data_sz != 0);
79 xspi->data_sz = 0;
80}
81
82static int xtfpga_spi_probe(struct platform_device *pdev)
83{
84 struct xtfpga_spi *xspi;
85 struct resource *mem;
86 int ret;
87 struct spi_master *master;
88
89 master = spi_alloc_master(&pdev->dev, sizeof(struct xtfpga_spi));
90 if (!master)
91 return -ENOMEM;
92
93 master->flags = SPI_MASTER_NO_RX;
94 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 16);
95 master->bus_num = pdev->dev.id;
96 master->dev.of_node = pdev->dev.of_node;
97
98 xspi = spi_master_get_devdata(master);
99 xspi->bitbang.master = master;
100 xspi->bitbang.chipselect = xtfpga_spi_chipselect;
101 xspi->bitbang.txrx_word[SPI_MODE_0] = xtfpga_spi_txrx_word;
102
103 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
104 if (!mem) {
105 dev_err(&pdev->dev, "No memory resource\n");
106 ret = -ENODEV;
107 goto err;
108 }
109 xspi->regs = devm_ioremap_resource(&pdev->dev, mem);
110 if (IS_ERR(xspi->regs)) {
111 ret = PTR_ERR(xspi->regs);
112 goto err;
113 }
114
115 xtfpga_spi_write32(xspi, XTFPGA_SPI_START, 0);
116 usleep_range(1000, 2000);
117 if (xtfpga_spi_read32(xspi, XTFPGA_SPI_BUSY)) {
118 dev_err(&pdev->dev, "Device stuck in busy state\n");
119 ret = -EBUSY;
120 goto err;
121 }
122
123 ret = spi_bitbang_start(&xspi->bitbang);
124 if (ret < 0) {
125 dev_err(&pdev->dev, "spi_bitbang_start failed\n");
126 goto err;
127 }
128
129 platform_set_drvdata(pdev, master);
130 return 0;
131err:
132 spi_master_put(master);
133 return ret;
134}
135
136static int xtfpga_spi_remove(struct platform_device *pdev)
137{
138 struct spi_master *master = platform_get_drvdata(pdev);
139 struct xtfpga_spi *xspi = spi_master_get_devdata(master);
140
141 spi_bitbang_stop(&xspi->bitbang);
142 spi_master_put(master);
143
144 return 0;
145}
146
147MODULE_ALIAS("platform:" XTFPGA_SPI_NAME);
148
149#ifdef CONFIG_OF
150static const struct of_device_id xtfpga_spi_of_match[] = {
151 { .compatible = "cdns,xtfpga-spi", },
152 {}
153};
154MODULE_DEVICE_TABLE(of, xtfpga_spi_of_match);
155#endif
156
157static struct platform_driver xtfpga_spi_driver = {
158 .probe = xtfpga_spi_probe,
159 .remove = xtfpga_spi_remove,
160 .driver = {
161 .name = XTFPGA_SPI_NAME,
162 .owner = THIS_MODULE,
163 .of_match_table = of_match_ptr(xtfpga_spi_of_match),
164 },
165};
166module_platform_driver(xtfpga_spi_driver);
167
168MODULE_AUTHOR("Max Filippov <jcmvbkbc@gmail.com>");
169MODULE_DESCRIPTION("xtensa xtfpga SPI driver");
170MODULE_LICENSE("GPL");
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index d0b28bba38be..4eb9bf02996c 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -24,6 +24,8 @@
24#include <linux/device.h> 24#include <linux/device.h>
25#include <linux/init.h> 25#include <linux/init.h>
26#include <linux/cache.h> 26#include <linux/cache.h>
27#include <linux/dma-mapping.h>
28#include <linux/dmaengine.h>
27#include <linux/mutex.h> 29#include <linux/mutex.h>
28#include <linux/of_device.h> 30#include <linux/of_device.h>
29#include <linux/of_irq.h> 31#include <linux/of_irq.h>
@@ -255,13 +257,12 @@ EXPORT_SYMBOL_GPL(spi_bus_type);
255static int spi_drv_probe(struct device *dev) 257static int spi_drv_probe(struct device *dev)
256{ 258{
257 const struct spi_driver *sdrv = to_spi_driver(dev->driver); 259 const struct spi_driver *sdrv = to_spi_driver(dev->driver);
258 struct spi_device *spi = to_spi_device(dev);
259 int ret; 260 int ret;
260 261
261 acpi_dev_pm_attach(&spi->dev, true); 262 acpi_dev_pm_attach(dev, true);
262 ret = sdrv->probe(spi); 263 ret = sdrv->probe(to_spi_device(dev));
263 if (ret) 264 if (ret)
264 acpi_dev_pm_detach(&spi->dev, true); 265 acpi_dev_pm_detach(dev, true);
265 266
266 return ret; 267 return ret;
267} 268}
@@ -269,11 +270,10 @@ static int spi_drv_probe(struct device *dev)
269static int spi_drv_remove(struct device *dev) 270static int spi_drv_remove(struct device *dev)
270{ 271{
271 const struct spi_driver *sdrv = to_spi_driver(dev->driver); 272 const struct spi_driver *sdrv = to_spi_driver(dev->driver);
272 struct spi_device *spi = to_spi_device(dev);
273 int ret; 273 int ret;
274 274
275 ret = sdrv->remove(spi); 275 ret = sdrv->remove(to_spi_device(dev));
276 acpi_dev_pm_detach(&spi->dev, true); 276 acpi_dev_pm_detach(dev, true);
277 277
278 return ret; 278 return ret;
279} 279}
@@ -580,6 +580,169 @@ static void spi_set_cs(struct spi_device *spi, bool enable)
580 spi->master->set_cs(spi, !enable); 580 spi->master->set_cs(spi, !enable);
581} 581}
582 582
583static int spi_map_buf(struct spi_master *master, struct device *dev,
584 struct sg_table *sgt, void *buf, size_t len,
585 enum dma_data_direction dir)
586{
587 const bool vmalloced_buf = is_vmalloc_addr(buf);
588 const int desc_len = vmalloced_buf ? PAGE_SIZE : master->max_dma_len;
589 const int sgs = DIV_ROUND_UP(len, desc_len);
590 struct page *vm_page;
591 void *sg_buf;
592 size_t min;
593 int i, ret;
594
595 ret = sg_alloc_table(sgt, sgs, GFP_KERNEL);
596 if (ret != 0)
597 return ret;
598
599 for (i = 0; i < sgs; i++) {
600 min = min_t(size_t, len, desc_len);
601
602 if (vmalloced_buf) {
603 vm_page = vmalloc_to_page(buf);
604 if (!vm_page) {
605 sg_free_table(sgt);
606 return -ENOMEM;
607 }
608 sg_buf = page_address(vm_page) +
609 ((size_t)buf & ~PAGE_MASK);
610 } else {
611 sg_buf = buf;
612 }
613
614 sg_set_buf(&sgt->sgl[i], sg_buf, min);
615
616 buf += min;
617 len -= min;
618 }
619
620 ret = dma_map_sg(dev, sgt->sgl, sgt->nents, dir);
621 if (ret < 0) {
622 sg_free_table(sgt);
623 return ret;
624 }
625
626 sgt->nents = ret;
627
628 return 0;
629}
630
631static void spi_unmap_buf(struct spi_master *master, struct device *dev,
632 struct sg_table *sgt, enum dma_data_direction dir)
633{
634 if (sgt->orig_nents) {
635 dma_unmap_sg(dev, sgt->sgl, sgt->orig_nents, dir);
636 sg_free_table(sgt);
637 }
638}
639
640static int spi_map_msg(struct spi_master *master, struct spi_message *msg)
641{
642 struct device *tx_dev, *rx_dev;
643 struct spi_transfer *xfer;
644 void *tmp;
645 unsigned int max_tx, max_rx;
646 int ret;
647
648 if (master->flags & (SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX)) {
649 max_tx = 0;
650 max_rx = 0;
651
652 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
653 if ((master->flags & SPI_MASTER_MUST_TX) &&
654 !xfer->tx_buf)
655 max_tx = max(xfer->len, max_tx);
656 if ((master->flags & SPI_MASTER_MUST_RX) &&
657 !xfer->rx_buf)
658 max_rx = max(xfer->len, max_rx);
659 }
660
661 if (max_tx) {
662 tmp = krealloc(master->dummy_tx, max_tx,
663 GFP_KERNEL | GFP_DMA);
664 if (!tmp)
665 return -ENOMEM;
666 master->dummy_tx = tmp;
667 memset(tmp, 0, max_tx);
668 }
669
670 if (max_rx) {
671 tmp = krealloc(master->dummy_rx, max_rx,
672 GFP_KERNEL | GFP_DMA);
673 if (!tmp)
674 return -ENOMEM;
675 master->dummy_rx = tmp;
676 }
677
678 if (max_tx || max_rx) {
679 list_for_each_entry(xfer, &msg->transfers,
680 transfer_list) {
681 if (!xfer->tx_buf)
682 xfer->tx_buf = master->dummy_tx;
683 if (!xfer->rx_buf)
684 xfer->rx_buf = master->dummy_rx;
685 }
686 }
687 }
688
689 if (!master->can_dma)
690 return 0;
691
692 tx_dev = &master->dma_tx->dev->device;
693 rx_dev = &master->dma_rx->dev->device;
694
695 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
696 if (!master->can_dma(master, msg->spi, xfer))
697 continue;
698
699 if (xfer->tx_buf != NULL) {
700 ret = spi_map_buf(master, tx_dev, &xfer->tx_sg,
701 (void *)xfer->tx_buf, xfer->len,
702 DMA_TO_DEVICE);
703 if (ret != 0)
704 return ret;
705 }
706
707 if (xfer->rx_buf != NULL) {
708 ret = spi_map_buf(master, rx_dev, &xfer->rx_sg,
709 xfer->rx_buf, xfer->len,
710 DMA_FROM_DEVICE);
711 if (ret != 0) {
712 spi_unmap_buf(master, tx_dev, &xfer->tx_sg,
713 DMA_TO_DEVICE);
714 return ret;
715 }
716 }
717 }
718
719 master->cur_msg_mapped = true;
720
721 return 0;
722}
723
724static int spi_unmap_msg(struct spi_master *master, struct spi_message *msg)
725{
726 struct spi_transfer *xfer;
727 struct device *tx_dev, *rx_dev;
728
729 if (!master->cur_msg_mapped || !master->can_dma)
730 return 0;
731
732 tx_dev = &master->dma_tx->dev->device;
733 rx_dev = &master->dma_rx->dev->device;
734
735 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
736 if (!master->can_dma(master, msg->spi, xfer))
737 continue;
738
739 spi_unmap_buf(master, rx_dev, &xfer->rx_sg, DMA_FROM_DEVICE);
740 spi_unmap_buf(master, tx_dev, &xfer->tx_sg, DMA_TO_DEVICE);
741 }
742
743 return 0;
744}
745
583/* 746/*
584 * spi_transfer_one_message - Default implementation of transfer_one_message() 747 * spi_transfer_one_message - Default implementation of transfer_one_message()
585 * 748 *
@@ -591,9 +754,9 @@ static int spi_transfer_one_message(struct spi_master *master,
591 struct spi_message *msg) 754 struct spi_message *msg)
592{ 755{
593 struct spi_transfer *xfer; 756 struct spi_transfer *xfer;
594 bool cur_cs = true;
595 bool keep_cs = false; 757 bool keep_cs = false;
596 int ret = 0; 758 int ret = 0;
759 int ms = 1;
597 760
598 spi_set_cs(msg->spi, true); 761 spi_set_cs(msg->spi, true);
599 762
@@ -611,7 +774,16 @@ static int spi_transfer_one_message(struct spi_master *master,
611 774
612 if (ret > 0) { 775 if (ret > 0) {
613 ret = 0; 776 ret = 0;
614 wait_for_completion(&master->xfer_completion); 777 ms = xfer->len * 8 * 1000 / xfer->speed_hz;
778 ms += 10; /* some tolerance */
779
780 ms = wait_for_completion_timeout(&master->xfer_completion,
781 msecs_to_jiffies(ms));
782 }
783
784 if (ms == 0) {
785 dev_err(&msg->spi->dev, "SPI transfer timed out\n");
786 msg->status = -ETIMEDOUT;
615 } 787 }
616 788
617 trace_spi_transfer_stop(msg, xfer); 789 trace_spi_transfer_stop(msg, xfer);
@@ -627,8 +799,9 @@ static int spi_transfer_one_message(struct spi_master *master,
627 &msg->transfers)) { 799 &msg->transfers)) {
628 keep_cs = true; 800 keep_cs = true;
629 } else { 801 } else {
630 cur_cs = !cur_cs; 802 spi_set_cs(msg->spi, false);
631 spi_set_cs(msg->spi, cur_cs); 803 udelay(10);
804 spi_set_cs(msg->spi, true);
632 } 805 }
633 } 806 }
634 807
@@ -686,6 +859,10 @@ static void spi_pump_messages(struct kthread_work *work)
686 } 859 }
687 master->busy = false; 860 master->busy = false;
688 spin_unlock_irqrestore(&master->queue_lock, flags); 861 spin_unlock_irqrestore(&master->queue_lock, flags);
862 kfree(master->dummy_rx);
863 master->dummy_rx = NULL;
864 kfree(master->dummy_tx);
865 master->dummy_tx = NULL;
689 if (master->unprepare_transfer_hardware && 866 if (master->unprepare_transfer_hardware &&
690 master->unprepare_transfer_hardware(master)) 867 master->unprepare_transfer_hardware(master))
691 dev_err(&master->dev, 868 dev_err(&master->dev,
@@ -752,6 +929,13 @@ static void spi_pump_messages(struct kthread_work *work)
752 master->cur_msg_prepared = true; 929 master->cur_msg_prepared = true;
753 } 930 }
754 931
932 ret = spi_map_msg(master, master->cur_msg);
933 if (ret) {
934 master->cur_msg->status = ret;
935 spi_finalize_current_message(master);
936 return;
937 }
938
755 ret = master->transfer_one_message(master, master->cur_msg); 939 ret = master->transfer_one_message(master, master->cur_msg);
756 if (ret) { 940 if (ret) {
757 dev_err(&master->dev, 941 dev_err(&master->dev,
@@ -839,6 +1023,8 @@ void spi_finalize_current_message(struct spi_master *master)
839 queue_kthread_work(&master->kworker, &master->pump_messages); 1023 queue_kthread_work(&master->kworker, &master->pump_messages);
840 spin_unlock_irqrestore(&master->queue_lock, flags); 1024 spin_unlock_irqrestore(&master->queue_lock, flags);
841 1025
1026 spi_unmap_msg(master, mesg);
1027
842 if (master->cur_msg_prepared && master->unprepare_message) { 1028 if (master->cur_msg_prepared && master->unprepare_message) {
843 ret = master->unprepare_message(master, mesg); 1029 ret = master->unprepare_message(master, mesg);
844 if (ret) { 1030 if (ret) {
@@ -892,7 +1078,7 @@ static int spi_stop_queue(struct spi_master *master)
892 */ 1078 */
893 while ((!list_empty(&master->queue) || master->busy) && limit--) { 1079 while ((!list_empty(&master->queue) || master->busy) && limit--) {
894 spin_unlock_irqrestore(&master->queue_lock, flags); 1080 spin_unlock_irqrestore(&master->queue_lock, flags);
895 msleep(10); 1081 usleep_range(10000, 11000);
896 spin_lock_irqsave(&master->queue_lock, flags); 1082 spin_lock_irqsave(&master->queue_lock, flags);
897 } 1083 }
898 1084
@@ -1372,6 +1558,8 @@ int spi_register_master(struct spi_master *master)
1372 mutex_init(&master->bus_lock_mutex); 1558 mutex_init(&master->bus_lock_mutex);
1373 master->bus_lock_flag = 0; 1559 master->bus_lock_flag = 0;
1374 init_completion(&master->xfer_completion); 1560 init_completion(&master->xfer_completion);
1561 if (!master->max_dma_len)
1562 master->max_dma_len = INT_MAX;
1375 1563
1376 /* register the device, then userspace will see it. 1564 /* register the device, then userspace will see it.
1377 * registration fails if the bus ID is in use. 1565 * registration fails if the bus ID is in use.
@@ -1597,6 +1785,9 @@ int spi_setup(struct spi_device *spi)
1597 if (!spi->bits_per_word) 1785 if (!spi->bits_per_word)
1598 spi->bits_per_word = 8; 1786 spi->bits_per_word = 8;
1599 1787
1788 if (!spi->max_speed_hz)
1789 spi->max_speed_hz = spi->master->max_speed_hz;
1790
1600 if (spi->master->setup) 1791 if (spi->master->setup)
1601 status = spi->master->setup(spi); 1792 status = spi->master->setup(spi);
1602 1793
@@ -1617,11 +1808,10 @@ static int __spi_validate(struct spi_device *spi, struct spi_message *message)
1617{ 1808{
1618 struct spi_master *master = spi->master; 1809 struct spi_master *master = spi->master;
1619 struct spi_transfer *xfer; 1810 struct spi_transfer *xfer;
1811 int w_size;
1620 1812
1621 if (list_empty(&message->transfers)) 1813 if (list_empty(&message->transfers))
1622 return -EINVAL; 1814 return -EINVAL;
1623 if (!message->complete)
1624 return -EINVAL;
1625 1815
1626 /* Half-duplex links include original MicroWire, and ones with 1816 /* Half-duplex links include original MicroWire, and ones with
1627 * only one data pin like SPI_3WIRE (switches direction) or where 1817 * only one data pin like SPI_3WIRE (switches direction) or where
@@ -1652,12 +1842,13 @@ static int __spi_validate(struct spi_device *spi, struct spi_message *message)
1652 message->frame_length += xfer->len; 1842 message->frame_length += xfer->len;
1653 if (!xfer->bits_per_word) 1843 if (!xfer->bits_per_word)
1654 xfer->bits_per_word = spi->bits_per_word; 1844 xfer->bits_per_word = spi->bits_per_word;
1655 if (!xfer->speed_hz) { 1845
1846 if (!xfer->speed_hz)
1656 xfer->speed_hz = spi->max_speed_hz; 1847 xfer->speed_hz = spi->max_speed_hz;
1657 if (master->max_speed_hz && 1848
1658 xfer->speed_hz > master->max_speed_hz) 1849 if (master->max_speed_hz &&
1659 xfer->speed_hz = master->max_speed_hz; 1850 xfer->speed_hz > master->max_speed_hz)
1660 } 1851 xfer->speed_hz = master->max_speed_hz;
1661 1852
1662 if (master->bits_per_word_mask) { 1853 if (master->bits_per_word_mask) {
1663 /* Only 32 bits fit in the mask */ 1854 /* Only 32 bits fit in the mask */
@@ -1668,12 +1859,24 @@ static int __spi_validate(struct spi_device *spi, struct spi_message *message)
1668 return -EINVAL; 1859 return -EINVAL;
1669 } 1860 }
1670 1861
1862 /*
1863 * SPI transfer length should be multiple of SPI word size
1864 * where SPI word size should be power-of-two multiple
1865 */
1866 if (xfer->bits_per_word <= 8)
1867 w_size = 1;
1868 else if (xfer->bits_per_word <= 16)
1869 w_size = 2;
1870 else
1871 w_size = 4;
1872
1873 /* No partial transfers accepted */
1874 if (xfer->len % w_size)
1875 return -EINVAL;
1876
1671 if (xfer->speed_hz && master->min_speed_hz && 1877 if (xfer->speed_hz && master->min_speed_hz &&
1672 xfer->speed_hz < master->min_speed_hz) 1878 xfer->speed_hz < master->min_speed_hz)
1673 return -EINVAL; 1879 return -EINVAL;
1674 if (xfer->speed_hz && master->max_speed_hz &&
1675 xfer->speed_hz > master->max_speed_hz)
1676 return -EINVAL;
1677 1880
1678 if (xfer->tx_buf && !xfer->tx_nbits) 1881 if (xfer->tx_buf && !xfer->tx_nbits)
1679 xfer->tx_nbits = SPI_NBITS_SINGLE; 1882 xfer->tx_nbits = SPI_NBITS_SINGLE;
diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c
index d7c6e36021e8..e3bc23bb5883 100644
--- a/drivers/spi/spidev.c
+++ b/drivers/spi/spidev.c
@@ -73,7 +73,8 @@ static DECLARE_BITMAP(minors, N_SPI_MINORS);
73 */ 73 */
74#define SPI_MODE_MASK (SPI_CPHA | SPI_CPOL | SPI_CS_HIGH \ 74#define SPI_MODE_MASK (SPI_CPHA | SPI_CPOL | SPI_CS_HIGH \
75 | SPI_LSB_FIRST | SPI_3WIRE | SPI_LOOP \ 75 | SPI_LSB_FIRST | SPI_3WIRE | SPI_LOOP \
76 | SPI_NO_CS | SPI_READY) 76 | SPI_NO_CS | SPI_READY | SPI_TX_DUAL \
77 | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD)
77 78
78struct spidev_data { 79struct spidev_data {
79 dev_t devt; 80 dev_t devt;
@@ -265,6 +266,8 @@ static int spidev_message(struct spidev_data *spidev,
265 buf += k_tmp->len; 266 buf += k_tmp->len;
266 267
267 k_tmp->cs_change = !!u_tmp->cs_change; 268 k_tmp->cs_change = !!u_tmp->cs_change;
269 k_tmp->tx_nbits = u_tmp->tx_nbits;
270 k_tmp->rx_nbits = u_tmp->rx_nbits;
268 k_tmp->bits_per_word = u_tmp->bits_per_word; 271 k_tmp->bits_per_word = u_tmp->bits_per_word;
269 k_tmp->delay_usecs = u_tmp->delay_usecs; 272 k_tmp->delay_usecs = u_tmp->delay_usecs;
270 k_tmp->speed_hz = u_tmp->speed_hz; 273 k_tmp->speed_hz = u_tmp->speed_hz;
@@ -359,6 +362,10 @@ spidev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
359 retval = __put_user(spi->mode & SPI_MODE_MASK, 362 retval = __put_user(spi->mode & SPI_MODE_MASK,
360 (__u8 __user *)arg); 363 (__u8 __user *)arg);
361 break; 364 break;
365 case SPI_IOC_RD_MODE32:
366 retval = __put_user(spi->mode & SPI_MODE_MASK,
367 (__u32 __user *)arg);
368 break;
362 case SPI_IOC_RD_LSB_FIRST: 369 case SPI_IOC_RD_LSB_FIRST:
363 retval = __put_user((spi->mode & SPI_LSB_FIRST) ? 1 : 0, 370 retval = __put_user((spi->mode & SPI_LSB_FIRST) ? 1 : 0,
364 (__u8 __user *)arg); 371 (__u8 __user *)arg);
@@ -372,9 +379,13 @@ spidev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
372 379
373 /* write requests */ 380 /* write requests */
374 case SPI_IOC_WR_MODE: 381 case SPI_IOC_WR_MODE:
375 retval = __get_user(tmp, (u8 __user *)arg); 382 case SPI_IOC_WR_MODE32:
383 if (cmd == SPI_IOC_WR_MODE)
384 retval = __get_user(tmp, (u8 __user *)arg);
385 else
386 retval = __get_user(tmp, (u32 __user *)arg);
376 if (retval == 0) { 387 if (retval == 0) {
377 u8 save = spi->mode; 388 u32 save = spi->mode;
378 389
379 if (tmp & ~SPI_MODE_MASK) { 390 if (tmp & ~SPI_MODE_MASK) {
380 retval = -EINVAL; 391 retval = -EINVAL;
@@ -382,18 +393,18 @@ spidev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
382 } 393 }
383 394
384 tmp |= spi->mode & ~SPI_MODE_MASK; 395 tmp |= spi->mode & ~SPI_MODE_MASK;
385 spi->mode = (u8)tmp; 396 spi->mode = (u16)tmp;
386 retval = spi_setup(spi); 397 retval = spi_setup(spi);
387 if (retval < 0) 398 if (retval < 0)
388 spi->mode = save; 399 spi->mode = save;
389 else 400 else
390 dev_dbg(&spi->dev, "spi mode %02x\n", tmp); 401 dev_dbg(&spi->dev, "spi mode %x\n", tmp);
391 } 402 }
392 break; 403 break;
393 case SPI_IOC_WR_LSB_FIRST: 404 case SPI_IOC_WR_LSB_FIRST:
394 retval = __get_user(tmp, (__u8 __user *)arg); 405 retval = __get_user(tmp, (__u8 __user *)arg);
395 if (retval == 0) { 406 if (retval == 0) {
396 u8 save = spi->mode; 407 u32 save = spi->mode;
397 408
398 if (tmp) 409 if (tmp)
399 spi->mode |= SPI_LSB_FIRST; 410 spi->mode |= SPI_LSB_FIRST;
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-12 06:20:47 -0500