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-rw-r--r--drivers/spi/Kconfig53
-rw-r--r--drivers/spi/Makefile3
-rw-r--r--drivers/spi/spi-altera.c46
-rw-r--r--drivers/spi/spi-atmel.c36
-rw-r--r--drivers/spi/spi-bcm2835.c10
-rw-r--r--drivers/spi/spi-bcm63xx.c8
-rw-r--r--drivers/spi/spi-bfin-v3.c965
-rw-r--r--drivers/spi/spi-bitbang.c260
-rw-r--r--drivers/spi/spi-clps711x.c6
-rw-r--r--drivers/spi/spi-davinci.c2
-rw-r--r--drivers/spi/spi-efm32.c516
-rw-r--r--drivers/spi/spi-ep93xx.c353
-rw-r--r--drivers/spi/spi-fsl-dspi.c557
-rw-r--r--drivers/spi/spi-imx.c76
-rw-r--r--drivers/spi/spi-mpc512x-psc.c48
-rw-r--r--drivers/spi/spi-mxs.c28
-rw-r--r--drivers/spi/spi-nuc900.c15
-rw-r--r--drivers/spi/spi-oc-tiny.c22
-rw-r--r--drivers/spi/spi-octeon.c49
-rw-r--r--drivers/spi/spi-omap-100k.c276
-rw-r--r--drivers/spi/spi-orion.c1
-rw-r--r--drivers/spi/spi-xilinx.c16
-rw-r--r--drivers/spi/spi.c24
23 files changed, 2490 insertions, 880 deletions
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 89cbbabaff44..8aad2c1dc33d 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -70,14 +70,14 @@ config SPI_ATH79
70 70
71config SPI_ATMEL 71config SPI_ATMEL
72 tristate "Atmel SPI Controller" 72 tristate "Atmel SPI Controller"
73 depends on (ARCH_AT91 || AVR32) 73 depends on (ARCH_AT91 || AVR32 || COMPILE_TEST)
74 help 74 help
75 This selects a driver for the Atmel SPI Controller, present on 75 This selects a driver for the Atmel SPI Controller, present on
76 many AT32 (AVR32) and AT91 (ARM) chips. 76 many AT32 (AVR32) and AT91 (ARM) chips.
77 77
78config SPI_BCM2835 78config SPI_BCM2835
79 tristate "BCM2835 SPI controller" 79 tristate "BCM2835 SPI controller"
80 depends on ARCH_BCM2835 80 depends on ARCH_BCM2835 || COMPILE_TEST
81 help 81 help
82 This selects a driver for the Broadcom BCM2835 SPI master. 82 This selects a driver for the Broadcom BCM2835 SPI master.
83 83
@@ -88,10 +88,17 @@ config SPI_BCM2835
88 88
89config SPI_BFIN5XX 89config SPI_BFIN5XX
90 tristate "SPI controller driver for ADI Blackfin5xx" 90 tristate "SPI controller driver for ADI Blackfin5xx"
91 depends on BLACKFIN 91 depends on BLACKFIN && !BF60x
92 help 92 help
93 This is the SPI controller master driver for Blackfin 5xx processor. 93 This is the SPI controller master driver for Blackfin 5xx processor.
94 94
95config SPI_BFIN_V3
96 tristate "SPI controller v3 for Blackfin"
97 depends on BF60x
98 help
99 This is the SPI controller v3 master driver
100 found on Blackfin 60x processor.
101
95config SPI_BFIN_SPORT 102config SPI_BFIN_SPORT
96 tristate "SPI bus via Blackfin SPORT" 103 tristate "SPI bus via Blackfin SPORT"
97 depends on BLACKFIN 104 depends on BLACKFIN
@@ -151,15 +158,22 @@ config SPI_COLDFIRE_QSPI
151 158
152config SPI_DAVINCI 159config SPI_DAVINCI
153 tristate "Texas Instruments DaVinci/DA8x/OMAP-L/AM1x SoC SPI controller" 160 tristate "Texas Instruments DaVinci/DA8x/OMAP-L/AM1x SoC SPI controller"
154 depends on ARCH_DAVINCI 161 depends on ARCH_DAVINCI || ARCH_KEYSTONE
155 select SPI_BITBANG 162 select SPI_BITBANG
156 select TI_EDMA 163 select TI_EDMA
157 help 164 help
158 SPI master controller for DaVinci/DA8x/OMAP-L/AM1x SPI modules. 165 SPI master controller for DaVinci/DA8x/OMAP-L/AM1x SPI modules.
159 166
167config SPI_EFM32
168 tristate "EFM32 SPI controller"
169 depends on OF && ARM && (ARCH_EFM32 || COMPILE_TEST)
170 select SPI_BITBANG
171 help
172 Driver for the spi controller found on Energy Micro's EFM32 SoCs.
173
160config SPI_EP93XX 174config SPI_EP93XX
161 tristate "Cirrus Logic EP93xx SPI controller" 175 tristate "Cirrus Logic EP93xx SPI controller"
162 depends on ARCH_EP93XX 176 depends on ARCH_EP93XX || COMPILE_TEST
163 help 177 help
164 This enables using the Cirrus EP93xx SPI controller in master 178 This enables using the Cirrus EP93xx SPI controller in master
165 mode. 179 mode.
@@ -191,7 +205,7 @@ config SPI_GPIO
191 205
192config SPI_IMX 206config SPI_IMX
193 tristate "Freescale i.MX SPI controllers" 207 tristate "Freescale i.MX SPI controllers"
194 depends on ARCH_MXC 208 depends on ARCH_MXC || COMPILE_TEST
195 select SPI_BITBANG 209 select SPI_BITBANG
196 default m if IMX_HAVE_PLATFORM_SPI_IMX 210 default m if IMX_HAVE_PLATFORM_SPI_IMX
197 help 211 help
@@ -248,6 +262,13 @@ config SPI_FSL_SPI
248 This also enables using the Aeroflex Gaisler GRLIB SPI controller in 262 This also enables using the Aeroflex Gaisler GRLIB SPI controller in
249 master mode. 263 master mode.
250 264
265config SPI_FSL_DSPI
266 tristate "Freescale DSPI controller"
267 select SPI_BITBANG
268 help
269 This enables support for the Freescale DSPI controller in master
270 mode. VF610 platform uses the controller.
271
251config SPI_FSL_ESPI 272config SPI_FSL_ESPI
252 bool "Freescale eSPI controller" 273 bool "Freescale eSPI controller"
253 depends on FSL_SOC 274 depends on FSL_SOC
@@ -280,20 +301,20 @@ config SPI_OMAP_UWIRE
280 301
281config SPI_OMAP24XX 302config SPI_OMAP24XX
282 tristate "McSPI driver for OMAP" 303 tristate "McSPI driver for OMAP"
283 depends on ARCH_OMAP2PLUS 304 depends on ARCH_OMAP2PLUS || COMPILE_TEST
284 help 305 help
285 SPI master controller for OMAP24XX and later Multichannel SPI 306 SPI master controller for OMAP24XX and later Multichannel SPI
286 (McSPI) modules. 307 (McSPI) modules.
287 308
288config SPI_OMAP_100K 309config SPI_OMAP_100K
289 tristate "OMAP SPI 100K" 310 tristate "OMAP SPI 100K"
290 depends on ARCH_OMAP850 || ARCH_OMAP730 311 depends on ARCH_OMAP850 || ARCH_OMAP730 || COMPILE_TEST
291 help 312 help
292 OMAP SPI 100K master controller for omap7xx boards. 313 OMAP SPI 100K master controller for omap7xx boards.
293 314
294config SPI_ORION 315config SPI_ORION
295 tristate "Orion SPI master" 316 tristate "Orion SPI master"
296 depends on PLAT_ORION 317 depends on PLAT_ORION || COMPILE_TEST
297 help 318 help
298 This enables using the SPI master controller on the Orion chips. 319 This enables using the SPI master controller on the Orion chips.
299 320
@@ -341,7 +362,7 @@ config SPI_PXA2XX_PCI
341 362
342config SPI_RSPI 363config SPI_RSPI
343 tristate "Renesas RSPI controller" 364 tristate "Renesas RSPI controller"
344 depends on SUPERH 365 depends on SUPERH && SH_DMAE_BASE
345 help 366 help
346 SPI driver for Renesas RSPI blocks. 367 SPI driver for Renesas RSPI blocks.
347 368
@@ -385,7 +406,7 @@ config SPI_SH_MSIOF
385 406
386config SPI_SH 407config SPI_SH
387 tristate "SuperH SPI controller" 408 tristate "SuperH SPI controller"
388 depends on SUPERH 409 depends on SUPERH || COMPILE_TEST
389 help 410 help
390 SPI driver for SuperH SPI blocks. 411 SPI driver for SuperH SPI blocks.
391 412
@@ -398,7 +419,7 @@ config SPI_SH_SCI
398 419
399config SPI_SH_HSPI 420config SPI_SH_HSPI
400 tristate "SuperH HSPI controller" 421 tristate "SuperH HSPI controller"
401 depends on ARCH_SHMOBILE 422 depends on ARCH_SHMOBILE || COMPILE_TEST
402 help 423 help
403 SPI driver for SuperH HSPI blocks. 424 SPI driver for SuperH HSPI blocks.
404 425
@@ -418,7 +439,7 @@ config SPI_MXS
418 439
419config SPI_TEGRA114 440config SPI_TEGRA114
420 tristate "NVIDIA Tegra114 SPI Controller" 441 tristate "NVIDIA Tegra114 SPI Controller"
421 depends on ARCH_TEGRA && TEGRA20_APB_DMA 442 depends on (ARCH_TEGRA && TEGRA20_APB_DMA) || COMPILE_TEST
422 help 443 help
423 SPI driver for NVIDIA Tegra114 SPI Controller interface. This controller 444 SPI driver for NVIDIA Tegra114 SPI Controller interface. This controller
424 is different than the older SoCs SPI controller and also register interface 445 is different than the older SoCs SPI controller and also register interface
@@ -426,7 +447,7 @@ config SPI_TEGRA114
426 447
427config SPI_TEGRA20_SFLASH 448config SPI_TEGRA20_SFLASH
428 tristate "Nvidia Tegra20 Serial flash Controller" 449 tristate "Nvidia Tegra20 Serial flash Controller"
429 depends on ARCH_TEGRA 450 depends on ARCH_TEGRA || COMPILE_TEST
430 help 451 help
431 SPI driver for Nvidia Tegra20 Serial flash Controller interface. 452 SPI driver for Nvidia Tegra20 Serial flash Controller interface.
432 The main usecase of this controller is to use spi flash as boot 453 The main usecase of this controller is to use spi flash as boot
@@ -434,7 +455,7 @@ config SPI_TEGRA20_SFLASH
434 455
435config SPI_TEGRA20_SLINK 456config SPI_TEGRA20_SLINK
436 tristate "Nvidia Tegra20/Tegra30 SLINK Controller" 457 tristate "Nvidia Tegra20/Tegra30 SLINK Controller"
437 depends on ARCH_TEGRA && TEGRA20_APB_DMA 458 depends on (ARCH_TEGRA && TEGRA20_APB_DMA) || COMPILE_TEST
438 help 459 help
439 SPI driver for Nvidia Tegra20/Tegra30 SLINK Controller interface. 460 SPI driver for Nvidia Tegra20/Tegra30 SLINK Controller interface.
440 461
@@ -457,7 +478,7 @@ config SPI_TOPCLIFF_PCH
457 478
458config SPI_TXX9 479config SPI_TXX9
459 tristate "Toshiba TXx9 SPI controller" 480 tristate "Toshiba TXx9 SPI controller"
460 depends on GPIOLIB && CPU_TX49XX 481 depends on GPIOLIB && (CPU_TX49XX || COMPILE_TEST)
461 help 482 help
462 SPI driver for Toshiba TXx9 MIPS SoCs 483 SPI driver for Toshiba TXx9 MIPS SoCs
463 484
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 33f9c09561e7..985d7bad7932 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_SPI_AU1550) += spi-au1550.o
17obj-$(CONFIG_SPI_BCM2835) += spi-bcm2835.o 17obj-$(CONFIG_SPI_BCM2835) += spi-bcm2835.o
18obj-$(CONFIG_SPI_BCM63XX) += spi-bcm63xx.o 18obj-$(CONFIG_SPI_BCM63XX) += spi-bcm63xx.o
19obj-$(CONFIG_SPI_BFIN5XX) += spi-bfin5xx.o 19obj-$(CONFIG_SPI_BFIN5XX) += spi-bfin5xx.o
20obj-$(CONFIG_SPI_BFIN_V3) += spi-bfin-v3.o
20obj-$(CONFIG_SPI_BFIN_SPORT) += spi-bfin-sport.o 21obj-$(CONFIG_SPI_BFIN_SPORT) += spi-bfin-sport.o
21obj-$(CONFIG_SPI_BITBANG) += spi-bitbang.o 22obj-$(CONFIG_SPI_BITBANG) += spi-bitbang.o
22obj-$(CONFIG_SPI_BUTTERFLY) += spi-butterfly.o 23obj-$(CONFIG_SPI_BUTTERFLY) += spi-butterfly.o
@@ -27,9 +28,11 @@ obj-$(CONFIG_SPI_DESIGNWARE) += spi-dw.o
27obj-$(CONFIG_SPI_DW_MMIO) += spi-dw-mmio.o 28obj-$(CONFIG_SPI_DW_MMIO) += spi-dw-mmio.o
28obj-$(CONFIG_SPI_DW_PCI) += spi-dw-midpci.o 29obj-$(CONFIG_SPI_DW_PCI) += spi-dw-midpci.o
29spi-dw-midpci-objs := spi-dw-pci.o spi-dw-mid.o 30spi-dw-midpci-objs := spi-dw-pci.o spi-dw-mid.o
31obj-$(CONFIG_SPI_EFM32) += spi-efm32.o
30obj-$(CONFIG_SPI_EP93XX) += spi-ep93xx.o 32obj-$(CONFIG_SPI_EP93XX) += spi-ep93xx.o
31obj-$(CONFIG_SPI_FALCON) += spi-falcon.o 33obj-$(CONFIG_SPI_FALCON) += spi-falcon.o
32obj-$(CONFIG_SPI_FSL_CPM) += spi-fsl-cpm.o 34obj-$(CONFIG_SPI_FSL_CPM) += spi-fsl-cpm.o
35obj-$(CONFIG_SPI_FSL_DSPI) += spi-fsl-dspi.o
33obj-$(CONFIG_SPI_FSL_LIB) += spi-fsl-lib.o 36obj-$(CONFIG_SPI_FSL_LIB) += spi-fsl-lib.o
34obj-$(CONFIG_SPI_FSL_ESPI) += spi-fsl-espi.o 37obj-$(CONFIG_SPI_FSL_ESPI) += spi-fsl-espi.o
35obj-$(CONFIG_SPI_FSL_SPI) += spi-fsl-spi.o 38obj-$(CONFIG_SPI_FSL_SPI) += spi-fsl-spi.o
diff --git a/drivers/spi/spi-altera.c b/drivers/spi/spi-altera.c
index 81b9adb6e766..156eb888655e 100644
--- a/drivers/spi/spi-altera.c
+++ b/drivers/spi/spi-altera.c
@@ -103,16 +103,6 @@ static void altera_spi_chipsel(struct spi_device *spi, int value)
103 } 103 }
104} 104}
105 105
106static int altera_spi_setupxfer(struct spi_device *spi, struct spi_transfer *t)
107{
108 return 0;
109}
110
111static int altera_spi_setup(struct spi_device *spi)
112{
113 return 0;
114}
115
116static inline unsigned int hw_txbyte(struct altera_spi *hw, int count) 106static inline unsigned int hw_txbyte(struct altera_spi *hw, int count)
117{ 107{
118 if (hw->tx) { 108 if (hw->tx) {
@@ -134,7 +124,7 @@ static int altera_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
134 hw->tx = t->tx_buf; 124 hw->tx = t->tx_buf;
135 hw->rx = t->rx_buf; 125 hw->rx = t->rx_buf;
136 hw->count = 0; 126 hw->count = 0;
137 hw->bytes_per_word = t->bits_per_word / 8; 127 hw->bytes_per_word = DIV_ROUND_UP(t->bits_per_word, 8);
138 hw->len = t->len / hw->bytes_per_word; 128 hw->len = t->len / hw->bytes_per_word;
139 129
140 if (hw->irq >= 0) { 130 if (hw->irq >= 0) {
@@ -150,12 +140,12 @@ static int altera_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
150 hw->imr &= ~ALTERA_SPI_CONTROL_IRRDY_MSK; 140 hw->imr &= ~ALTERA_SPI_CONTROL_IRRDY_MSK;
151 writel(hw->imr, hw->base + ALTERA_SPI_CONTROL); 141 writel(hw->imr, hw->base + ALTERA_SPI_CONTROL);
152 } else { 142 } else {
153 /* send the first byte */ 143 while (hw->count < hw->len) {
154 writel(hw_txbyte(hw, 0), hw->base + ALTERA_SPI_TXDATA);
155
156 while (1) {
157 unsigned int rxd; 144 unsigned int rxd;
158 145
146 writel(hw_txbyte(hw, hw->count),
147 hw->base + ALTERA_SPI_TXDATA);
148
159 while (!(readl(hw->base + ALTERA_SPI_STATUS) & 149 while (!(readl(hw->base + ALTERA_SPI_STATUS) &
160 ALTERA_SPI_STATUS_RRDY_MSK)) 150 ALTERA_SPI_STATUS_RRDY_MSK))
161 cpu_relax(); 151 cpu_relax();
@@ -174,14 +164,7 @@ static int altera_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
174 } 164 }
175 165
176 hw->count++; 166 hw->count++;
177
178 if (hw->count < hw->len)
179 writel(hw_txbyte(hw, hw->count),
180 hw->base + ALTERA_SPI_TXDATA);
181 else
182 break;
183 } 167 }
184
185 } 168 }
186 169
187 return hw->count * hw->bytes_per_word; 170 return hw->count * hw->bytes_per_word;
@@ -231,7 +214,6 @@ static int altera_spi_probe(struct platform_device *pdev)
231 master->bus_num = pdev->id; 214 master->bus_num = pdev->id;
232 master->num_chipselect = 16; 215 master->num_chipselect = 16;
233 master->mode_bits = SPI_CS_HIGH; 216 master->mode_bits = SPI_CS_HIGH;
234 master->setup = altera_spi_setup;
235 217
236 hw = spi_master_get_devdata(master); 218 hw = spi_master_get_devdata(master);
237 platform_set_drvdata(pdev, hw); 219 platform_set_drvdata(pdev, hw);
@@ -240,21 +222,16 @@ static int altera_spi_probe(struct platform_device *pdev)
240 hw->bitbang.master = spi_master_get(master); 222 hw->bitbang.master = spi_master_get(master);
241 if (!hw->bitbang.master) 223 if (!hw->bitbang.master)
242 return err; 224 return err;
243 hw->bitbang.setup_transfer = altera_spi_setupxfer;
244 hw->bitbang.chipselect = altera_spi_chipsel; 225 hw->bitbang.chipselect = altera_spi_chipsel;
245 hw->bitbang.txrx_bufs = altera_spi_txrx; 226 hw->bitbang.txrx_bufs = altera_spi_txrx;
246 227
247 /* find and map our resources */ 228 /* find and map our resources */
248 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 229 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
249 if (!res) 230 hw->base = devm_ioremap_resource(&pdev->dev, res);
250 goto exit_busy; 231 if (IS_ERR(hw->base)) {
251 if (!devm_request_mem_region(&pdev->dev, res->start, resource_size(res), 232 err = PTR_ERR(hw->base);
252 pdev->name)) 233 goto exit;
253 goto exit_busy; 234 }
254 hw->base = devm_ioremap_nocache(&pdev->dev, res->start,
255 resource_size(res));
256 if (!hw->base)
257 goto exit_busy;
258 /* program defaults into the registers */ 235 /* program defaults into the registers */
259 hw->imr = 0; /* disable spi interrupts */ 236 hw->imr = 0; /* disable spi interrupts */
260 writel(hw->imr, hw->base + ALTERA_SPI_CONTROL); 237 writel(hw->imr, hw->base + ALTERA_SPI_CONTROL);
@@ -281,9 +258,6 @@ static int altera_spi_probe(struct platform_device *pdev)
281 dev_info(&pdev->dev, "base %p, irq %d\n", hw->base, hw->irq); 258 dev_info(&pdev->dev, "base %p, irq %d\n", hw->base, hw->irq);
282 259
283 return 0; 260 return 0;
284
285exit_busy:
286 err = -EBUSY;
287exit: 261exit:
288 spi_master_put(master); 262 spi_master_put(master);
289 return err; 263 return err;
diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
index ea1ec009f44d..fd7cc566095a 100644
--- a/drivers/spi/spi-atmel.c
+++ b/drivers/spi/spi-atmel.c
@@ -360,12 +360,12 @@ static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
360 gpio_set_value(asd->npcs_pin, !active); 360 gpio_set_value(asd->npcs_pin, !active);
361} 361}
362 362
363static void atmel_spi_lock(struct atmel_spi *as) 363static void atmel_spi_lock(struct atmel_spi *as) __acquires(&as->lock)
364{ 364{
365 spin_lock_irqsave(&as->lock, as->flags); 365 spin_lock_irqsave(&as->lock, as->flags);
366} 366}
367 367
368static void atmel_spi_unlock(struct atmel_spi *as) 368static void atmel_spi_unlock(struct atmel_spi *as) __releases(&as->lock)
369{ 369{
370 spin_unlock_irqrestore(&as->lock, as->flags); 370 spin_unlock_irqrestore(&as->lock, as->flags);
371} 371}
@@ -629,9 +629,9 @@ static int atmel_spi_next_xfer_dma_submit(struct spi_master *master,
629 goto err_dma; 629 goto err_dma;
630 630
631 dev_dbg(master->dev.parent, 631 dev_dbg(master->dev.parent,
632 " start dma xfer %p: len %u tx %p/%08x rx %p/%08x\n", 632 " start dma xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
633 xfer, xfer->len, xfer->tx_buf, xfer->tx_dma, 633 xfer, xfer->len, xfer->tx_buf, (unsigned long long)xfer->tx_dma,
634 xfer->rx_buf, xfer->rx_dma); 634 xfer->rx_buf, (unsigned long long)xfer->rx_dma);
635 635
636 /* Enable relevant interrupts */ 636 /* Enable relevant interrupts */
637 spi_writel(as, IER, SPI_BIT(OVRES)); 637 spi_writel(as, IER, SPI_BIT(OVRES));
@@ -732,9 +732,10 @@ static void atmel_spi_pdc_next_xfer(struct spi_master *master,
732 spi_writel(as, TCR, len); 732 spi_writel(as, TCR, len);
733 733
734 dev_dbg(&msg->spi->dev, 734 dev_dbg(&msg->spi->dev,
735 " start xfer %p: len %u tx %p/%08x rx %p/%08x\n", 735 " start xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
736 xfer, xfer->len, xfer->tx_buf, xfer->tx_dma, 736 xfer, xfer->len, xfer->tx_buf,
737 xfer->rx_buf, xfer->rx_dma); 737 (unsigned long long)xfer->tx_dma, xfer->rx_buf,
738 (unsigned long long)xfer->rx_dma);
738 } else { 739 } else {
739 xfer = as->next_transfer; 740 xfer = as->next_transfer;
740 remaining = as->next_remaining_bytes; 741 remaining = as->next_remaining_bytes;
@@ -771,9 +772,10 @@ static void atmel_spi_pdc_next_xfer(struct spi_master *master,
771 spi_writel(as, TNCR, len); 772 spi_writel(as, TNCR, len);
772 773
773 dev_dbg(&msg->spi->dev, 774 dev_dbg(&msg->spi->dev,
774 " next xfer %p: len %u tx %p/%08x rx %p/%08x\n", 775 " next xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
775 xfer, xfer->len, xfer->tx_buf, xfer->tx_dma, 776 xfer, xfer->len, xfer->tx_buf,
776 xfer->rx_buf, xfer->rx_dma); 777 (unsigned long long)xfer->tx_dma, xfer->rx_buf,
778 (unsigned long long)xfer->rx_dma);
777 ieval = SPI_BIT(ENDRX) | SPI_BIT(OVRES); 779 ieval = SPI_BIT(ENDRX) | SPI_BIT(OVRES);
778 } else { 780 } else {
779 spi_writel(as, RNCR, 0); 781 spi_writel(as, RNCR, 0);
@@ -1579,7 +1581,9 @@ static int atmel_spi_probe(struct platform_device *pdev)
1579 goto out_unmap_regs; 1581 goto out_unmap_regs;
1580 1582
1581 /* Initialize the hardware */ 1583 /* Initialize the hardware */
1582 clk_enable(clk); 1584 ret = clk_prepare_enable(clk);
1585 if (ret)
1586 goto out_unmap_regs;
1583 spi_writel(as, CR, SPI_BIT(SWRST)); 1587 spi_writel(as, CR, SPI_BIT(SWRST));
1584 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */ 1588 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1585 if (as->caps.has_wdrbt) { 1589 if (as->caps.has_wdrbt) {
@@ -1609,7 +1613,7 @@ out_free_dma:
1609 1613
1610 spi_writel(as, CR, SPI_BIT(SWRST)); 1614 spi_writel(as, CR, SPI_BIT(SWRST));
1611 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */ 1615 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1612 clk_disable(clk); 1616 clk_disable_unprepare(clk);
1613 free_irq(irq, master); 1617 free_irq(irq, master);
1614out_unmap_regs: 1618out_unmap_regs:
1615 iounmap(as->regs); 1619 iounmap(as->regs);
@@ -1661,7 +1665,7 @@ static int atmel_spi_remove(struct platform_device *pdev)
1661 dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer, 1665 dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
1662 as->buffer_dma); 1666 as->buffer_dma);
1663 1667
1664 clk_disable(as->clk); 1668 clk_disable_unprepare(as->clk);
1665 clk_put(as->clk); 1669 clk_put(as->clk);
1666 free_irq(as->irq, master); 1670 free_irq(as->irq, master);
1667 iounmap(as->regs); 1671 iounmap(as->regs);
@@ -1678,7 +1682,7 @@ static int atmel_spi_suspend(struct platform_device *pdev, pm_message_t mesg)
1678 struct spi_master *master = platform_get_drvdata(pdev); 1682 struct spi_master *master = platform_get_drvdata(pdev);
1679 struct atmel_spi *as = spi_master_get_devdata(master); 1683 struct atmel_spi *as = spi_master_get_devdata(master);
1680 1684
1681 clk_disable(as->clk); 1685 clk_disable_unprepare(as->clk);
1682 return 0; 1686 return 0;
1683} 1687}
1684 1688
@@ -1687,7 +1691,7 @@ static int atmel_spi_resume(struct platform_device *pdev)
1687 struct spi_master *master = platform_get_drvdata(pdev); 1691 struct spi_master *master = platform_get_drvdata(pdev);
1688 struct atmel_spi *as = spi_master_get_devdata(master); 1692 struct atmel_spi *as = spi_master_get_devdata(master);
1689 1693
1690 clk_enable(as->clk); 1694 return clk_prepare_enable(as->clk);
1691 return 0; 1695 return 0;
1692} 1696}
1693 1697
diff --git a/drivers/spi/spi-bcm2835.c b/drivers/spi/spi-bcm2835.c
index a4185e492321..52c81481c5c7 100644
--- a/drivers/spi/spi-bcm2835.c
+++ b/drivers/spi/spi-bcm2835.c
@@ -314,7 +314,7 @@ static int bcm2835_spi_probe(struct platform_device *pdev)
314 platform_set_drvdata(pdev, master); 314 platform_set_drvdata(pdev, master);
315 315
316 master->mode_bits = BCM2835_SPI_MODE_BITS; 316 master->mode_bits = BCM2835_SPI_MODE_BITS;
317 master->bits_per_word_mask = BIT(8 - 1); 317 master->bits_per_word_mask = SPI_BPW_MASK(8);
318 master->bus_num = -1; 318 master->bus_num = -1;
319 master->num_chipselect = 3; 319 master->num_chipselect = 3;
320 master->transfer_one_message = bcm2835_spi_transfer_one; 320 master->transfer_one_message = bcm2835_spi_transfer_one;
@@ -325,12 +325,6 @@ static int bcm2835_spi_probe(struct platform_device *pdev)
325 init_completion(&bs->done); 325 init_completion(&bs->done);
326 326
327 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 327 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
328 if (!res) {
329 dev_err(&pdev->dev, "could not get memory resource\n");
330 err = -ENODEV;
331 goto out_master_put;
332 }
333
334 bs->regs = devm_ioremap_resource(&pdev->dev, res); 328 bs->regs = devm_ioremap_resource(&pdev->dev, res);
335 if (IS_ERR(bs->regs)) { 329 if (IS_ERR(bs->regs)) {
336 err = PTR_ERR(bs->regs); 330 err = PTR_ERR(bs->regs);
@@ -383,7 +377,7 @@ out_master_put:
383 377
384static int bcm2835_spi_remove(struct platform_device *pdev) 378static int bcm2835_spi_remove(struct platform_device *pdev)
385{ 379{
386 struct spi_master *master = platform_get_drvdata(pdev); 380 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
387 struct bcm2835_spi *bs = spi_master_get_devdata(master); 381 struct bcm2835_spi *bs = spi_master_get_devdata(master);
388 382
389 free_irq(bs->irq, master); 383 free_irq(bs->irq, master);
diff --git a/drivers/spi/spi-bcm63xx.c b/drivers/spi/spi-bcm63xx.c
index 9fd7a39b8029..a21fef4a3bb1 100644
--- a/drivers/spi/spi-bcm63xx.c
+++ b/drivers/spi/spi-bcm63xx.c
@@ -360,13 +360,6 @@ static int bcm63xx_spi_probe(struct platform_device *pdev)
360 struct bcm63xx_spi *bs; 360 struct bcm63xx_spi *bs;
361 int ret; 361 int ret;
362 362
363 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
364 if (!r) {
365 dev_err(dev, "no iomem\n");
366 ret = -ENXIO;
367 goto out;
368 }
369
370 irq = platform_get_irq(pdev, 0); 363 irq = platform_get_irq(pdev, 0);
371 if (irq < 0) { 364 if (irq < 0) {
372 dev_err(dev, "no irq\n"); 365 dev_err(dev, "no irq\n");
@@ -393,6 +386,7 @@ static int bcm63xx_spi_probe(struct platform_device *pdev)
393 platform_set_drvdata(pdev, master); 386 platform_set_drvdata(pdev, master);
394 bs->pdev = pdev; 387 bs->pdev = pdev;
395 388
389 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
396 bs->regs = devm_ioremap_resource(&pdev->dev, r); 390 bs->regs = devm_ioremap_resource(&pdev->dev, r);
397 if (IS_ERR(bs->regs)) { 391 if (IS_ERR(bs->regs)) {
398 ret = PTR_ERR(bs->regs); 392 ret = PTR_ERR(bs->regs);
diff --git a/drivers/spi/spi-bfin-v3.c b/drivers/spi/spi-bfin-v3.c
new file mode 100644
index 000000000000..e4394ebf08f3
--- /dev/null
+++ b/drivers/spi/spi-bfin-v3.c
@@ -0,0 +1,965 @@
1/*
2 * Analog Devices SPI3 controller driver
3 *
4 * Copyright (c) 2013 Analog Devices Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/delay.h>
17#include <linux/device.h>
18#include <linux/dma-mapping.h>
19#include <linux/errno.h>
20#include <linux/gpio.h>
21#include <linux/init.h>
22#include <linux/interrupt.h>
23#include <linux/io.h>
24#include <linux/ioport.h>
25#include <linux/module.h>
26#include <linux/platform_device.h>
27#include <linux/slab.h>
28#include <linux/spi/spi.h>
29#include <linux/types.h>
30
31#include <asm/bfin_spi3.h>
32#include <asm/cacheflush.h>
33#include <asm/dma.h>
34#include <asm/portmux.h>
35
36enum bfin_spi_state {
37 START_STATE,
38 RUNNING_STATE,
39 DONE_STATE,
40 ERROR_STATE
41};
42
43struct bfin_spi_master;
44
45struct bfin_spi_transfer_ops {
46 void (*write) (struct bfin_spi_master *);
47 void (*read) (struct bfin_spi_master *);
48 void (*duplex) (struct bfin_spi_master *);
49};
50
51/* runtime info for spi master */
52struct bfin_spi_master {
53 /* SPI framework hookup */
54 struct spi_master *master;
55
56 /* Regs base of SPI controller */
57 struct bfin_spi_regs __iomem *regs;
58
59 /* Pin request list */
60 u16 *pin_req;
61
62 /* Message Transfer pump */
63 struct tasklet_struct pump_transfers;
64
65 /* Current message transfer state info */
66 struct spi_message *cur_msg;
67 struct spi_transfer *cur_transfer;
68 struct bfin_spi_device *cur_chip;
69 unsigned transfer_len;
70
71 /* transfer buffer */
72 void *tx;
73 void *tx_end;
74 void *rx;
75 void *rx_end;
76
77 /* dma info */
78 unsigned int tx_dma;
79 unsigned int rx_dma;
80 dma_addr_t tx_dma_addr;
81 dma_addr_t rx_dma_addr;
82 unsigned long dummy_buffer; /* used in unidirectional transfer */
83 unsigned long tx_dma_size;
84 unsigned long rx_dma_size;
85 int tx_num;
86 int rx_num;
87
88 /* store register value for suspend/resume */
89 u32 control;
90 u32 ssel;
91
92 unsigned long sclk;
93 enum bfin_spi_state state;
94
95 const struct bfin_spi_transfer_ops *ops;
96};
97
98struct bfin_spi_device {
99 u32 control;
100 u32 clock;
101 u32 ssel;
102
103 u8 cs;
104 u16 cs_chg_udelay; /* Some devices require > 255usec delay */
105 u32 cs_gpio;
106 u32 tx_dummy_val; /* tx value for rx only transfer */
107 bool enable_dma;
108 const struct bfin_spi_transfer_ops *ops;
109};
110
111static void bfin_spi_enable(struct bfin_spi_master *drv_data)
112{
113 bfin_write_or(&drv_data->regs->control, SPI_CTL_EN);
114}
115
116static void bfin_spi_disable(struct bfin_spi_master *drv_data)
117{
118 bfin_write_and(&drv_data->regs->control, ~SPI_CTL_EN);
119}
120
121/* Caculate the SPI_CLOCK register value based on input HZ */
122static u32 hz_to_spi_clock(u32 sclk, u32 speed_hz)
123{
124 u32 spi_clock = sclk / speed_hz;
125
126 if (spi_clock)
127 spi_clock--;
128 return spi_clock;
129}
130
131static int bfin_spi_flush(struct bfin_spi_master *drv_data)
132{
133 unsigned long limit = loops_per_jiffy << 1;
134
135 /* wait for stop and clear stat */
136 while (!(bfin_read(&drv_data->regs->status) & SPI_STAT_SPIF) && --limit)
137 cpu_relax();
138
139 bfin_write(&drv_data->regs->status, 0xFFFFFFFF);
140
141 return limit;
142}
143
144/* Chip select operation functions for cs_change flag */
145static void bfin_spi_cs_active(struct bfin_spi_master *drv_data, struct bfin_spi_device *chip)
146{
147 if (likely(chip->cs < MAX_CTRL_CS))
148 bfin_write_and(&drv_data->regs->ssel, ~chip->ssel);
149 else
150 gpio_set_value(chip->cs_gpio, 0);
151}
152
153static void bfin_spi_cs_deactive(struct bfin_spi_master *drv_data,
154 struct bfin_spi_device *chip)
155{
156 if (likely(chip->cs < MAX_CTRL_CS))
157 bfin_write_or(&drv_data->regs->ssel, chip->ssel);
158 else
159 gpio_set_value(chip->cs_gpio, 1);
160
161 /* Move delay here for consistency */
162 if (chip->cs_chg_udelay)
163 udelay(chip->cs_chg_udelay);
164}
165
166/* enable or disable the pin muxed by GPIO and SPI CS to work as SPI CS */
167static inline void bfin_spi_cs_enable(struct bfin_spi_master *drv_data,
168 struct bfin_spi_device *chip)
169{
170 if (chip->cs < MAX_CTRL_CS)
171 bfin_write_or(&drv_data->regs->ssel, chip->ssel >> 8);
172}
173
174static inline void bfin_spi_cs_disable(struct bfin_spi_master *drv_data,
175 struct bfin_spi_device *chip)
176{
177 if (chip->cs < MAX_CTRL_CS)
178 bfin_write_and(&drv_data->regs->ssel, ~(chip->ssel >> 8));
179}
180
181/* stop controller and re-config current chip*/
182static void bfin_spi_restore_state(struct bfin_spi_master *drv_data)
183{
184 struct bfin_spi_device *chip = drv_data->cur_chip;
185
186 /* Clear status and disable clock */
187 bfin_write(&drv_data->regs->status, 0xFFFFFFFF);
188 bfin_write(&drv_data->regs->rx_control, 0x0);
189 bfin_write(&drv_data->regs->tx_control, 0x0);
190 bfin_spi_disable(drv_data);
191
192 SSYNC();
193
194 /* Load the registers */
195 bfin_write(&drv_data->regs->control, chip->control);
196 bfin_write(&drv_data->regs->clock, chip->clock);
197
198 bfin_spi_enable(drv_data);
199 drv_data->tx_num = drv_data->rx_num = 0;
200 /* we always choose tx transfer initiate */
201 bfin_write(&drv_data->regs->rx_control, SPI_RXCTL_REN);
202 bfin_write(&drv_data->regs->tx_control,
203 SPI_TXCTL_TEN | SPI_TXCTL_TTI);
204 bfin_spi_cs_active(drv_data, chip);
205}
206
207/* discard invalid rx data and empty rfifo */
208static inline void dummy_read(struct bfin_spi_master *drv_data)
209{
210 while (!(bfin_read(&drv_data->regs->status) & SPI_STAT_RFE))
211 bfin_read(&drv_data->regs->rfifo);
212}
213
214static void bfin_spi_u8_write(struct bfin_spi_master *drv_data)
215{
216 dummy_read(drv_data);
217 while (drv_data->tx < drv_data->tx_end) {
218 bfin_write(&drv_data->regs->tfifo, (*(u8 *)(drv_data->tx++)));
219 while (bfin_read(&drv_data->regs->status) & SPI_STAT_RFE)
220 cpu_relax();
221 bfin_read(&drv_data->regs->rfifo);
222 }
223}
224
225static void bfin_spi_u8_read(struct bfin_spi_master *drv_data)
226{
227 u32 tx_val = drv_data->cur_chip->tx_dummy_val;
228
229 dummy_read(drv_data);
230 while (drv_data->rx < drv_data->rx_end) {
231 bfin_write(&drv_data->regs->tfifo, tx_val);
232 while (bfin_read(&drv_data->regs->status) & SPI_STAT_RFE)
233 cpu_relax();
234 *(u8 *)(drv_data->rx++) = bfin_read(&drv_data->regs->rfifo);
235 }
236}
237
238static void bfin_spi_u8_duplex(struct bfin_spi_master *drv_data)
239{
240 dummy_read(drv_data);
241 while (drv_data->rx < drv_data->rx_end) {
242 bfin_write(&drv_data->regs->tfifo, (*(u8 *)(drv_data->tx++)));
243 while (bfin_read(&drv_data->regs->status) & SPI_STAT_RFE)
244 cpu_relax();
245 *(u8 *)(drv_data->rx++) = bfin_read(&drv_data->regs->rfifo);
246 }
247}
248
249static const struct bfin_spi_transfer_ops bfin_bfin_spi_transfer_ops_u8 = {
250 .write = bfin_spi_u8_write,
251 .read = bfin_spi_u8_read,
252 .duplex = bfin_spi_u8_duplex,
253};
254
255static void bfin_spi_u16_write(struct bfin_spi_master *drv_data)
256{
257 dummy_read(drv_data);
258 while (drv_data->tx < drv_data->tx_end) {
259 bfin_write(&drv_data->regs->tfifo, (*(u16 *)drv_data->tx));
260 drv_data->tx += 2;
261 while (bfin_read(&drv_data->regs->status) & SPI_STAT_RFE)
262 cpu_relax();
263 bfin_read(&drv_data->regs->rfifo);
264 }
265}
266
267static void bfin_spi_u16_read(struct bfin_spi_master *drv_data)
268{
269 u32 tx_val = drv_data->cur_chip->tx_dummy_val;
270
271 dummy_read(drv_data);
272 while (drv_data->rx < drv_data->rx_end) {
273 bfin_write(&drv_data->regs->tfifo, tx_val);
274 while (bfin_read(&drv_data->regs->status) & SPI_STAT_RFE)
275 cpu_relax();
276 *(u16 *)drv_data->rx = bfin_read(&drv_data->regs->rfifo);
277 drv_data->rx += 2;
278 }
279}
280
281static void bfin_spi_u16_duplex(struct bfin_spi_master *drv_data)
282{
283 dummy_read(drv_data);
284 while (drv_data->rx < drv_data->rx_end) {
285 bfin_write(&drv_data->regs->tfifo, (*(u16 *)drv_data->tx));
286 drv_data->tx += 2;
287 while (bfin_read(&drv_data->regs->status) & SPI_STAT_RFE)
288 cpu_relax();
289 *(u16 *)drv_data->rx = bfin_read(&drv_data->regs->rfifo);
290 drv_data->rx += 2;
291 }
292}
293
294static const struct bfin_spi_transfer_ops bfin_bfin_spi_transfer_ops_u16 = {
295 .write = bfin_spi_u16_write,
296 .read = bfin_spi_u16_read,
297 .duplex = bfin_spi_u16_duplex,
298};
299
300static void bfin_spi_u32_write(struct bfin_spi_master *drv_data)
301{
302 dummy_read(drv_data);
303 while (drv_data->tx < drv_data->tx_end) {
304 bfin_write(&drv_data->regs->tfifo, (*(u32 *)drv_data->tx));
305 drv_data->tx += 4;
306 while (bfin_read(&drv_data->regs->status) & SPI_STAT_RFE)
307 cpu_relax();
308 bfin_read(&drv_data->regs->rfifo);
309 }
310}
311
312static void bfin_spi_u32_read(struct bfin_spi_master *drv_data)
313{
314 u32 tx_val = drv_data->cur_chip->tx_dummy_val;
315
316 dummy_read(drv_data);
317 while (drv_data->rx < drv_data->rx_end) {
318 bfin_write(&drv_data->regs->tfifo, tx_val);
319 while (bfin_read(&drv_data->regs->status) & SPI_STAT_RFE)
320 cpu_relax();
321 *(u32 *)drv_data->rx = bfin_read(&drv_data->regs->rfifo);
322 drv_data->rx += 4;
323 }
324}
325
326static void bfin_spi_u32_duplex(struct bfin_spi_master *drv_data)
327{
328 dummy_read(drv_data);
329 while (drv_data->rx < drv_data->rx_end) {
330 bfin_write(&drv_data->regs->tfifo, (*(u32 *)drv_data->tx));
331 drv_data->tx += 4;
332 while (bfin_read(&drv_data->regs->status) & SPI_STAT_RFE)
333 cpu_relax();
334 *(u32 *)drv_data->rx = bfin_read(&drv_data->regs->rfifo);
335 drv_data->rx += 4;
336 }
337}
338
339static const struct bfin_spi_transfer_ops bfin_bfin_spi_transfer_ops_u32 = {
340 .write = bfin_spi_u32_write,
341 .read = bfin_spi_u32_read,
342 .duplex = bfin_spi_u32_duplex,
343};
344
345
346/* test if there is more transfer to be done */
347static void bfin_spi_next_transfer(struct bfin_spi_master *drv)
348{
349 struct spi_message *msg = drv->cur_msg;
350 struct spi_transfer *t = drv->cur_transfer;
351
352 /* Move to next transfer */
353 if (t->transfer_list.next != &msg->transfers) {
354 drv->cur_transfer = list_entry(t->transfer_list.next,
355 struct spi_transfer, transfer_list);
356 drv->state = RUNNING_STATE;
357 } else {
358 drv->state = DONE_STATE;
359 drv->cur_transfer = NULL;
360 }
361}
362
363static void bfin_spi_giveback(struct bfin_spi_master *drv_data)
364{
365 struct bfin_spi_device *chip = drv_data->cur_chip;
366
367 bfin_spi_cs_deactive(drv_data, chip);
368 spi_finalize_current_message(drv_data->master);
369}
370
371static int bfin_spi_setup_transfer(struct bfin_spi_master *drv)
372{
373 struct spi_transfer *t = drv->cur_transfer;
374 u32 cr, cr_width;
375
376 if (t->tx_buf) {
377 drv->tx = (void *)t->tx_buf;
378 drv->tx_end = drv->tx + t->len;
379 } else {
380 drv->tx = NULL;
381 }
382
383 if (t->rx_buf) {
384 drv->rx = t->rx_buf;
385 drv->rx_end = drv->rx + t->len;
386 } else {
387 drv->rx = NULL;
388 }
389
390 drv->transfer_len = t->len;
391
392 /* bits per word setup */
393 switch (t->bits_per_word) {
394 case 8:
395 cr_width = SPI_CTL_SIZE08;
396 drv->ops = &bfin_bfin_spi_transfer_ops_u8;
397 break;
398 case 16:
399 cr_width = SPI_CTL_SIZE16;
400 drv->ops = &bfin_bfin_spi_transfer_ops_u16;
401 break;
402 case 32:
403 cr_width = SPI_CTL_SIZE32;
404 drv->ops = &bfin_bfin_spi_transfer_ops_u32;
405 break;
406 default:
407 return -EINVAL;
408 }
409 cr = bfin_read(&drv->regs->control) & ~SPI_CTL_SIZE;
410 cr |= cr_width;
411 bfin_write(&drv->regs->control, cr);
412
413 /* speed setup */
414 bfin_write(&drv->regs->clock,
415 hz_to_spi_clock(drv->sclk, t->speed_hz));
416 return 0;
417}
418
419static int bfin_spi_dma_xfer(struct bfin_spi_master *drv_data)
420{
421 struct spi_transfer *t = drv_data->cur_transfer;
422 struct spi_message *msg = drv_data->cur_msg;
423 struct bfin_spi_device *chip = drv_data->cur_chip;
424 u32 dma_config;
425 unsigned long word_count, word_size;
426 void *tx_buf, *rx_buf;
427
428 switch (t->bits_per_word) {
429 case 8:
430 dma_config = WDSIZE_8 | PSIZE_8;
431 word_count = drv_data->transfer_len;
432 word_size = 1;
433 break;
434 case 16:
435 dma_config = WDSIZE_16 | PSIZE_16;
436 word_count = drv_data->transfer_len / 2;
437 word_size = 2;
438 break;
439 default:
440 dma_config = WDSIZE_32 | PSIZE_32;
441 word_count = drv_data->transfer_len / 4;
442 word_size = 4;
443 break;
444 }
445
446 if (!drv_data->rx) {
447 tx_buf = drv_data->tx;
448 rx_buf = &drv_data->dummy_buffer;
449 drv_data->tx_dma_size = drv_data->transfer_len;
450 drv_data->rx_dma_size = sizeof(drv_data->dummy_buffer);
451 set_dma_x_modify(drv_data->tx_dma, word_size);
452 set_dma_x_modify(drv_data->rx_dma, 0);
453 } else if (!drv_data->tx) {
454 drv_data->dummy_buffer = chip->tx_dummy_val;
455 tx_buf = &drv_data->dummy_buffer;
456 rx_buf = drv_data->rx;
457 drv_data->tx_dma_size = sizeof(drv_data->dummy_buffer);
458 drv_data->rx_dma_size = drv_data->transfer_len;
459 set_dma_x_modify(drv_data->tx_dma, 0);
460 set_dma_x_modify(drv_data->rx_dma, word_size);
461 } else {
462 tx_buf = drv_data->tx;
463 rx_buf = drv_data->rx;
464 drv_data->tx_dma_size = drv_data->rx_dma_size
465 = drv_data->transfer_len;
466 set_dma_x_modify(drv_data->tx_dma, word_size);
467 set_dma_x_modify(drv_data->rx_dma, word_size);
468 }
469
470 drv_data->tx_dma_addr = dma_map_single(&msg->spi->dev,
471 (void *)tx_buf,
472 drv_data->tx_dma_size,
473 DMA_TO_DEVICE);
474 if (dma_mapping_error(&msg->spi->dev,
475 drv_data->tx_dma_addr))
476 return -ENOMEM;
477
478 drv_data->rx_dma_addr = dma_map_single(&msg->spi->dev,
479 (void *)rx_buf,
480 drv_data->rx_dma_size,
481 DMA_FROM_DEVICE);
482 if (dma_mapping_error(&msg->spi->dev,
483 drv_data->rx_dma_addr)) {
484 dma_unmap_single(&msg->spi->dev,
485 drv_data->tx_dma_addr,
486 drv_data->tx_dma_size,
487 DMA_TO_DEVICE);
488 return -ENOMEM;
489 }
490
491 dummy_read(drv_data);
492 set_dma_x_count(drv_data->tx_dma, word_count);
493 set_dma_x_count(drv_data->rx_dma, word_count);
494 set_dma_start_addr(drv_data->tx_dma, drv_data->tx_dma_addr);
495 set_dma_start_addr(drv_data->rx_dma, drv_data->rx_dma_addr);
496 dma_config |= DMAFLOW_STOP | RESTART | DI_EN;
497 set_dma_config(drv_data->tx_dma, dma_config);
498 set_dma_config(drv_data->rx_dma, dma_config | WNR);
499 enable_dma(drv_data->tx_dma);
500 enable_dma(drv_data->rx_dma);
501 SSYNC();
502
503 bfin_write(&drv_data->regs->rx_control, SPI_RXCTL_REN | SPI_RXCTL_RDR_NE);
504 SSYNC();
505 bfin_write(&drv_data->regs->tx_control,
506 SPI_TXCTL_TEN | SPI_TXCTL_TTI | SPI_TXCTL_TDR_NF);
507
508 return 0;
509}
510
511static int bfin_spi_pio_xfer(struct bfin_spi_master *drv_data)
512{
513 struct spi_message *msg = drv_data->cur_msg;
514
515 if (!drv_data->rx) {
516 /* write only half duplex */
517 drv_data->ops->write(drv_data);
518 if (drv_data->tx != drv_data->tx_end)
519 return -EIO;
520 } else if (!drv_data->tx) {
521 /* read only half duplex */
522 drv_data->ops->read(drv_data);
523 if (drv_data->rx != drv_data->rx_end)
524 return -EIO;
525 } else {
526 /* full duplex mode */
527 drv_data->ops->duplex(drv_data);
528 if (drv_data->tx != drv_data->tx_end)
529 return -EIO;
530 }
531
532 if (!bfin_spi_flush(drv_data))
533 return -EIO;
534 msg->actual_length += drv_data->transfer_len;
535 tasklet_schedule(&drv_data->pump_transfers);
536 return 0;
537}
538
539static void bfin_spi_pump_transfers(unsigned long data)
540{
541 struct bfin_spi_master *drv_data = (struct bfin_spi_master *)data;
542 struct spi_message *msg = NULL;
543 struct spi_transfer *t = NULL;
544 struct bfin_spi_device *chip = NULL;
545 int ret;
546
547 /* Get current state information */
548 msg = drv_data->cur_msg;
549 t = drv_data->cur_transfer;
550 chip = drv_data->cur_chip;
551
552 /* Handle for abort */
553 if (drv_data->state == ERROR_STATE) {
554 msg->status = -EIO;
555 bfin_spi_giveback(drv_data);
556 return;
557 }
558
559 if (drv_data->state == RUNNING_STATE) {
560 if (t->delay_usecs)
561 udelay(t->delay_usecs);
562 if (t->cs_change)
563 bfin_spi_cs_deactive(drv_data, chip);
564 bfin_spi_next_transfer(drv_data);
565 t = drv_data->cur_transfer;
566 }
567 /* Handle end of message */
568 if (drv_data->state == DONE_STATE) {
569 msg->status = 0;
570 bfin_spi_giveback(drv_data);
571 return;
572 }
573
574 if ((t->len == 0) || (t->tx_buf == NULL && t->rx_buf == NULL)) {
575 /* Schedule next transfer tasklet */
576 tasklet_schedule(&drv_data->pump_transfers);
577 return;
578 }
579
580 ret = bfin_spi_setup_transfer(drv_data);
581 if (ret) {
582 msg->status = ret;
583 bfin_spi_giveback(drv_data);
584 }
585
586 bfin_write(&drv_data->regs->status, 0xFFFFFFFF);
587 bfin_spi_cs_active(drv_data, chip);
588 drv_data->state = RUNNING_STATE;
589
590 if (chip->enable_dma)
591 ret = bfin_spi_dma_xfer(drv_data);
592 else
593 ret = bfin_spi_pio_xfer(drv_data);
594 if (ret) {
595 msg->status = ret;
596 bfin_spi_giveback(drv_data);
597 }
598}
599
600static int bfin_spi_transfer_one_message(struct spi_master *master,
601 struct spi_message *m)
602{
603 struct bfin_spi_master *drv_data = spi_master_get_devdata(master);
604
605 drv_data->cur_msg = m;
606 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
607 bfin_spi_restore_state(drv_data);
608
609 drv_data->state = START_STATE;
610 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
611 struct spi_transfer, transfer_list);
612
613 tasklet_schedule(&drv_data->pump_transfers);
614 return 0;
615}
616
617#define MAX_SPI_SSEL 7
618
619static const u16 ssel[][MAX_SPI_SSEL] = {
620 {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
621 P_SPI0_SSEL4, P_SPI0_SSEL5,
622 P_SPI0_SSEL6, P_SPI0_SSEL7},
623
624 {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3,
625 P_SPI1_SSEL4, P_SPI1_SSEL5,
626 P_SPI1_SSEL6, P_SPI1_SSEL7},
627
628 {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3,
629 P_SPI2_SSEL4, P_SPI2_SSEL5,
630 P_SPI2_SSEL6, P_SPI2_SSEL7},
631};
632
633static int bfin_spi_setup(struct spi_device *spi)
634{
635 struct bfin_spi_master *drv_data = spi_master_get_devdata(spi->master);
636 struct bfin_spi_device *chip = spi_get_ctldata(spi);
637 u32 bfin_ctl_reg = SPI_CTL_ODM | SPI_CTL_PSSE;
638 int ret = -EINVAL;
639
640 if (!chip) {
641 struct bfin_spi3_chip *chip_info = spi->controller_data;
642
643 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
644 if (!chip) {
645 dev_err(&spi->dev, "can not allocate chip data\n");
646 return -ENOMEM;
647 }
648 if (chip_info) {
649 if (chip_info->control & ~bfin_ctl_reg) {
650 dev_err(&spi->dev,
651 "do not set bits that the SPI framework manages\n");
652 goto error;
653 }
654 chip->control = chip_info->control;
655 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
656 chip->tx_dummy_val = chip_info->tx_dummy_val;
657 chip->enable_dma = chip_info->enable_dma;
658 }
659 chip->cs = spi->chip_select;
660 if (chip->cs < MAX_CTRL_CS) {
661 chip->ssel = (1 << chip->cs) << 8;
662 ret = peripheral_request(ssel[spi->master->bus_num]
663 [chip->cs-1], dev_name(&spi->dev));
664 if (ret) {
665 dev_err(&spi->dev, "peripheral_request() error\n");
666 goto error;
667 }
668 } else {
669 chip->cs_gpio = chip->cs - MAX_CTRL_CS;
670 ret = gpio_request_one(chip->cs_gpio, GPIOF_OUT_INIT_HIGH,
671 dev_name(&spi->dev));
672 if (ret) {
673 dev_err(&spi->dev, "gpio_request_one() error\n");
674 goto error;
675 }
676 }
677 spi_set_ctldata(spi, chip);
678 }
679
680 /* force a default base state */
681 chip->control &= bfin_ctl_reg;
682
683 if (spi->mode & SPI_CPOL)
684 chip->control |= SPI_CTL_CPOL;
685 if (spi->mode & SPI_CPHA)
686 chip->control |= SPI_CTL_CPHA;
687 if (spi->mode & SPI_LSB_FIRST)
688 chip->control |= SPI_CTL_LSBF;
689 chip->control |= SPI_CTL_MSTR;
690 /* we choose software to controll cs */
691 chip->control &= ~SPI_CTL_ASSEL;
692
693 chip->clock = hz_to_spi_clock(drv_data->sclk, spi->max_speed_hz);
694
695 bfin_spi_cs_enable(drv_data, chip);
696 bfin_spi_cs_deactive(drv_data, chip);
697
698 return 0;
699error:
700 if (chip) {
701 kfree(chip);
702 spi_set_ctldata(spi, NULL);
703 }
704
705 return ret;
706}
707
708static void bfin_spi_cleanup(struct spi_device *spi)
709{
710 struct bfin_spi_device *chip = spi_get_ctldata(spi);
711 struct bfin_spi_master *drv_data = spi_master_get_devdata(spi->master);
712
713 if (!chip)
714 return;
715
716 if (chip->cs < MAX_CTRL_CS) {
717 peripheral_free(ssel[spi->master->bus_num]
718 [chip->cs-1]);
719 bfin_spi_cs_disable(drv_data, chip);
720 } else {
721 gpio_free(chip->cs_gpio);
722 }
723
724 kfree(chip);
725 spi_set_ctldata(spi, NULL);
726}
727
728static irqreturn_t bfin_spi_tx_dma_isr(int irq, void *dev_id)
729{
730 struct bfin_spi_master *drv_data = dev_id;
731 u32 dma_stat = get_dma_curr_irqstat(drv_data->tx_dma);
732
733 clear_dma_irqstat(drv_data->tx_dma);
734 if (dma_stat & DMA_DONE) {
735 drv_data->tx_num++;
736 } else {
737 dev_err(&drv_data->master->dev,
738 "spi tx dma error: %d\n", dma_stat);
739 if (drv_data->tx)
740 drv_data->state = ERROR_STATE;
741 }
742 bfin_write_and(&drv_data->regs->tx_control, ~SPI_TXCTL_TDR_NF);
743 return IRQ_HANDLED;
744}
745
746static irqreturn_t bfin_spi_rx_dma_isr(int irq, void *dev_id)
747{
748 struct bfin_spi_master *drv_data = dev_id;
749 struct spi_message *msg = drv_data->cur_msg;
750 u32 dma_stat = get_dma_curr_irqstat(drv_data->rx_dma);
751
752 clear_dma_irqstat(drv_data->rx_dma);
753 if (dma_stat & DMA_DONE) {
754 drv_data->rx_num++;
755 /* we may fail on tx dma */
756 if (drv_data->state != ERROR_STATE)
757 msg->actual_length += drv_data->transfer_len;
758 } else {
759 drv_data->state = ERROR_STATE;
760 dev_err(&drv_data->master->dev,
761 "spi rx dma error: %d\n", dma_stat);
762 }
763 bfin_write(&drv_data->regs->tx_control, 0);
764 bfin_write(&drv_data->regs->rx_control, 0);
765 if (drv_data->rx_num != drv_data->tx_num)
766 dev_dbg(&drv_data->master->dev,
767 "dma interrupt missing: tx=%d,rx=%d\n",
768 drv_data->tx_num, drv_data->rx_num);
769 tasklet_schedule(&drv_data->pump_transfers);
770 return IRQ_HANDLED;
771}
772
773static int bfin_spi_probe(struct platform_device *pdev)
774{
775 struct device *dev = &pdev->dev;
776 struct bfin_spi3_master *info = dev->platform_data;
777 struct spi_master *master;
778 struct bfin_spi_master *drv_data;
779 struct resource *mem, *res;
780 unsigned int tx_dma, rx_dma;
781 unsigned long sclk;
782 int ret;
783
784 if (!info) {
785 dev_err(dev, "platform data missing!\n");
786 return -ENODEV;
787 }
788
789 sclk = get_sclk1();
790 if (!sclk) {
791 dev_err(dev, "can not get sclk1\n");
792 return -ENXIO;
793 }
794
795 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
796 if (!res) {
797 dev_err(dev, "can not get tx dma resource\n");
798 return -ENXIO;
799 }
800 tx_dma = res->start;
801
802 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
803 if (!res) {
804 dev_err(dev, "can not get rx dma resource\n");
805 return -ENXIO;
806 }
807 rx_dma = res->start;
808
809 /* allocate master with space for drv_data */
810 master = spi_alloc_master(dev, sizeof(*drv_data));
811 if (!master) {
812 dev_err(dev, "can not alloc spi_master\n");
813 return -ENOMEM;
814 }
815 platform_set_drvdata(pdev, master);
816
817 /* the mode bits supported by this driver */
818 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
819
820 master->bus_num = pdev->id;
821 master->num_chipselect = info->num_chipselect;
822 master->cleanup = bfin_spi_cleanup;
823 master->setup = bfin_spi_setup;
824 master->transfer_one_message = bfin_spi_transfer_one_message;
825 master->bits_per_word_mask = BIT(32 - 1) | BIT(16 - 1) | BIT(8 - 1);
826
827 drv_data = spi_master_get_devdata(master);
828 drv_data->master = master;
829 drv_data->tx_dma = tx_dma;
830 drv_data->rx_dma = rx_dma;
831 drv_data->pin_req = info->pin_req;
832 drv_data->sclk = sclk;
833
834 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
835 drv_data->regs = devm_ioremap_resource(dev, mem);
836 if (IS_ERR(drv_data->regs)) {
837 ret = PTR_ERR(drv_data->regs);
838 goto err_put_master;
839 }
840
841 /* request tx and rx dma */
842 ret = request_dma(tx_dma, "SPI_TX_DMA");
843 if (ret) {
844 dev_err(dev, "can not request SPI TX DMA channel\n");
845 goto err_put_master;
846 }
847 set_dma_callback(tx_dma, bfin_spi_tx_dma_isr, drv_data);
848
849 ret = request_dma(rx_dma, "SPI_RX_DMA");
850 if (ret) {
851 dev_err(dev, "can not request SPI RX DMA channel\n");
852 goto err_free_tx_dma;
853 }
854 set_dma_callback(drv_data->rx_dma, bfin_spi_rx_dma_isr, drv_data);
855
856 /* request CLK, MOSI and MISO */
857 ret = peripheral_request_list(drv_data->pin_req, "bfin-spi3");
858 if (ret < 0) {
859 dev_err(dev, "can not request spi pins\n");
860 goto err_free_rx_dma;
861 }
862
863 bfin_write(&drv_data->regs->control, SPI_CTL_MSTR | SPI_CTL_CPHA);
864 bfin_write(&drv_data->regs->ssel, 0x0000FE00);
865 bfin_write(&drv_data->regs->delay, 0x0);
866
867 tasklet_init(&drv_data->pump_transfers,
868 bfin_spi_pump_transfers, (unsigned long)drv_data);
869 /* register with the SPI framework */
870 ret = spi_register_master(master);
871 if (ret) {
872 dev_err(dev, "can not register spi master\n");
873 goto err_free_peripheral;
874 }
875
876 return ret;
877
878err_free_peripheral:
879 peripheral_free_list(drv_data->pin_req);
880err_free_rx_dma:
881 free_dma(rx_dma);
882err_free_tx_dma:
883 free_dma(tx_dma);
884err_put_master:
885 spi_master_put(master);
886
887 return ret;
888}
889
890static int bfin_spi_remove(struct platform_device *pdev)
891{
892 struct spi_master *master = platform_get_drvdata(pdev);
893 struct bfin_spi_master *drv_data = spi_master_get_devdata(master);
894
895 bfin_spi_disable(drv_data);
896
897 peripheral_free_list(drv_data->pin_req);
898 free_dma(drv_data->rx_dma);
899 free_dma(drv_data->tx_dma);
900
901 spi_unregister_master(drv_data->master);
902 return 0;
903}
904
905#ifdef CONFIG_PM
906static int bfin_spi_suspend(struct device *dev)
907{
908 struct spi_master *master = dev_get_drvdata(dev);
909 struct bfin_spi_master *drv_data = spi_master_get_devdata(master);
910
911 spi_master_suspend(master);
912
913 drv_data->control = bfin_read(&drv_data->regs->control);
914 drv_data->ssel = bfin_read(&drv_data->regs->ssel);
915
916 bfin_write(&drv_data->regs->control, SPI_CTL_MSTR | SPI_CTL_CPHA);
917 bfin_write(&drv_data->regs->ssel, 0x0000FE00);
918 dma_disable_irq(drv_data->rx_dma);
919 dma_disable_irq(drv_data->tx_dma);
920
921 return 0;
922}
923
924static int bfin_spi_resume(struct device *dev)
925{
926 struct spi_master *master = dev_get_drvdata(dev);
927 struct bfin_spi_master *drv_data = spi_master_get_devdata(master);
928 int ret = 0;
929
930 /* bootrom may modify spi and dma status when resume in spi boot mode */
931 disable_dma(drv_data->rx_dma);
932
933 dma_enable_irq(drv_data->rx_dma);
934 dma_enable_irq(drv_data->tx_dma);
935 bfin_write(&drv_data->regs->control, drv_data->control);
936 bfin_write(&drv_data->regs->ssel, drv_data->ssel);
937
938 ret = spi_master_resume(master);
939 if (ret) {
940 free_dma(drv_data->rx_dma);
941 free_dma(drv_data->tx_dma);
942 }
943
944 return ret;
945}
946#endif
947static const struct dev_pm_ops bfin_spi_pm_ops = {
948 SET_SYSTEM_SLEEP_PM_OPS(bfin_spi_suspend, bfin_spi_resume)
949};
950
951MODULE_ALIAS("platform:bfin-spi3");
952static struct platform_driver bfin_spi_driver = {
953 .driver = {
954 .name = "bfin-spi3",
955 .owner = THIS_MODULE,
956 .pm = &bfin_spi_pm_ops,
957 },
958 .remove = bfin_spi_remove,
959};
960
961module_platform_driver_probe(bfin_spi_driver, bfin_spi_probe);
962
963MODULE_DESCRIPTION("Analog Devices SPI3 controller driver");
964MODULE_AUTHOR("Scott Jiang <Scott.Jiang.Linux@gmail.com>");
965MODULE_LICENSE("GPL v2");
diff --git a/drivers/spi/spi-bitbang.c b/drivers/spi/spi-bitbang.c
index a63d7da3bfe2..e3946e44e076 100644
--- a/drivers/spi/spi-bitbang.c
+++ b/drivers/spi/spi-bitbang.c
@@ -255,150 +255,140 @@ static int spi_bitbang_bufs(struct spi_device *spi, struct spi_transfer *t)
255 * Drivers can provide word-at-a-time i/o primitives, or provide 255 * Drivers can provide word-at-a-time i/o primitives, or provide
256 * transfer-at-a-time ones to leverage dma or fifo hardware. 256 * transfer-at-a-time ones to leverage dma or fifo hardware.
257 */ 257 */
258static void bitbang_work(struct work_struct *work) 258
259static int spi_bitbang_prepare_hardware(struct spi_master *spi)
259{ 260{
260 struct spi_bitbang *bitbang = 261 struct spi_bitbang *bitbang;
261 container_of(work, struct spi_bitbang, work);
262 unsigned long flags; 262 unsigned long flags;
263 struct spi_message *m, *_m; 263
264 bitbang = spi_master_get_devdata(spi);
264 265
265 spin_lock_irqsave(&bitbang->lock, flags); 266 spin_lock_irqsave(&bitbang->lock, flags);
266 bitbang->busy = 1; 267 bitbang->busy = 1;
267 list_for_each_entry_safe(m, _m, &bitbang->queue, queue) { 268 spin_unlock_irqrestore(&bitbang->lock, flags);
268 struct spi_device *spi;
269 unsigned nsecs;
270 struct spi_transfer *t = NULL;
271 unsigned tmp;
272 unsigned cs_change;
273 int status;
274 int do_setup = -1;
275
276 list_del(&m->queue);
277 spin_unlock_irqrestore(&bitbang->lock, flags);
278
279 /* FIXME this is made-up ... the correct value is known to
280 * word-at-a-time bitbang code, and presumably chipselect()
281 * should enforce these requirements too?
282 */
283 nsecs = 100;
284 269
285 spi = m->spi; 270 return 0;
286 tmp = 0; 271}
287 cs_change = 1;
288 status = 0;
289 272
290 list_for_each_entry (t, &m->transfers, transfer_list) { 273static int spi_bitbang_transfer_one(struct spi_master *master,
291 274 struct spi_message *m)
292 /* override speed or wordsize? */ 275{
293 if (t->speed_hz || t->bits_per_word) 276 struct spi_bitbang *bitbang;
294 do_setup = 1; 277 unsigned nsecs;
295 278 struct spi_transfer *t = NULL;
296 /* init (-1) or override (1) transfer params */ 279 unsigned cs_change;
297 if (do_setup != 0) { 280 int status;
298 status = bitbang->setup_transfer(spi, t); 281 int do_setup = -1;
299 if (status < 0) 282 struct spi_device *spi = m->spi;
300 break; 283
301 if (do_setup == -1) 284 bitbang = spi_master_get_devdata(master);
302 do_setup = 0; 285
303 } 286 /* FIXME this is made-up ... the correct value is known to
304 287 * word-at-a-time bitbang code, and presumably chipselect()
305 /* set up default clock polarity, and activate chip; 288 * should enforce these requirements too?
306 * this implicitly updates clock and spi modes as 289 */
307 * previously recorded for this device via setup(). 290 nsecs = 100;
308 * (and also deselects any other chip that might be
309 * selected ...)
310 */
311 if (cs_change) {
312 bitbang->chipselect(spi, BITBANG_CS_ACTIVE);
313 ndelay(nsecs);
314 }
315 cs_change = t->cs_change;
316 if (!t->tx_buf && !t->rx_buf && t->len) {
317 status = -EINVAL;
318 break;
319 }
320 291
321 /* transfer data. the lower level code handles any 292 cs_change = 1;
322 * new dma mappings it needs. our caller always gave 293 status = 0;
323 * us dma-safe buffers. 294
324 */ 295 list_for_each_entry (t, &m->transfers, transfer_list) {
325 if (t->len) { 296
326 /* REVISIT dma API still needs a designated 297 /* override speed or wordsize? */
327 * DMA_ADDR_INVALID; ~0 might be better. 298 if (t->speed_hz || t->bits_per_word)
328 */ 299 do_setup = 1;
329 if (!m->is_dma_mapped) 300
330 t->rx_dma = t->tx_dma = 0; 301 /* init (-1) or override (1) transfer params */
331 status = bitbang->txrx_bufs(spi, t); 302 if (do_setup != 0) {
332 } 303 status = bitbang->setup_transfer(spi, t);
333 if (status > 0) 304 if (status < 0)
334 m->actual_length += status;
335 if (status != t->len) {
336 /* always report some kind of error */
337 if (status >= 0)
338 status = -EREMOTEIO;
339 break; 305 break;
340 } 306 if (do_setup == -1)
341 status = 0; 307 do_setup = 0;
342
343 /* protocol tweaks before next transfer */
344 if (t->delay_usecs)
345 udelay(t->delay_usecs);
346
347 if (cs_change && !list_is_last(&t->transfer_list, &m->transfers)) {
348 /* sometimes a short mid-message deselect of the chip
349 * may be needed to terminate a mode or command
350 */
351 ndelay(nsecs);
352 bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
353 ndelay(nsecs);
354 }
355 } 308 }
356 309
357 m->status = status; 310 /* set up default clock polarity, and activate chip;
358 m->complete(m->context); 311 * this implicitly updates clock and spi modes as
312 * previously recorded for this device via setup().
313 * (and also deselects any other chip that might be
314 * selected ...)
315 */
316 if (cs_change) {
317 bitbang->chipselect(spi, BITBANG_CS_ACTIVE);
318 ndelay(nsecs);
319 }
320 cs_change = t->cs_change;
321 if (!t->tx_buf && !t->rx_buf && t->len) {
322 status = -EINVAL;
323 break;
324 }
359 325
360 /* normally deactivate chipselect ... unless no error and 326 /* transfer data. the lower level code handles any
361 * cs_change has hinted that the next message will probably 327 * new dma mappings it needs. our caller always gave
362 * be for this chip too. 328 * us dma-safe buffers.
363 */ 329 */
364 if (!(status == 0 && cs_change)) { 330 if (t->len) {
331 /* REVISIT dma API still needs a designated
332 * DMA_ADDR_INVALID; ~0 might be better.
333 */
334 if (!m->is_dma_mapped)
335 t->rx_dma = t->tx_dma = 0;
336 status = bitbang->txrx_bufs(spi, t);
337 }
338 if (status > 0)
339 m->actual_length += status;
340 if (status != t->len) {
341 /* always report some kind of error */
342 if (status >= 0)
343 status = -EREMOTEIO;
344 break;
345 }
346 status = 0;
347
348 /* protocol tweaks before next transfer */
349 if (t->delay_usecs)
350 udelay(t->delay_usecs);
351
352 if (cs_change && !list_is_last(&t->transfer_list, &m->transfers)) {
353 /* sometimes a short mid-message deselect of the chip
354 * may be needed to terminate a mode or command
355 */
365 ndelay(nsecs); 356 ndelay(nsecs);
366 bitbang->chipselect(spi, BITBANG_CS_INACTIVE); 357 bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
367 ndelay(nsecs); 358 ndelay(nsecs);
368 } 359 }
360 }
361
362 m->status = status;
369 363
370 spin_lock_irqsave(&bitbang->lock, flags); 364 /* normally deactivate chipselect ... unless no error and
365 * cs_change has hinted that the next message will probably
366 * be for this chip too.
367 */
368 if (!(status == 0 && cs_change)) {
369 ndelay(nsecs);
370 bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
371 ndelay(nsecs);
371 } 372 }
372 bitbang->busy = 0; 373
373 spin_unlock_irqrestore(&bitbang->lock, flags); 374 spi_finalize_current_message(master);
375
376 return status;
374} 377}
375 378
376/** 379static int spi_bitbang_unprepare_hardware(struct spi_master *spi)
377 * spi_bitbang_transfer - default submit to transfer queue
378 */
379int spi_bitbang_transfer(struct spi_device *spi, struct spi_message *m)
380{ 380{
381 struct spi_bitbang *bitbang; 381 struct spi_bitbang *bitbang;
382 unsigned long flags; 382 unsigned long flags;
383 int status = 0;
384 383
385 m->actual_length = 0; 384 bitbang = spi_master_get_devdata(spi);
386 m->status = -EINPROGRESS;
387
388 bitbang = spi_master_get_devdata(spi->master);
389 385
390 spin_lock_irqsave(&bitbang->lock, flags); 386 spin_lock_irqsave(&bitbang->lock, flags);
391 if (!spi->max_speed_hz) 387 bitbang->busy = 0;
392 status = -ENETDOWN;
393 else {
394 list_add_tail(&m->queue, &bitbang->queue);
395 queue_work(bitbang->workqueue, &bitbang->work);
396 }
397 spin_unlock_irqrestore(&bitbang->lock, flags); 388 spin_unlock_irqrestore(&bitbang->lock, flags);
398 389
399 return status; 390 return 0;
400} 391}
401EXPORT_SYMBOL_GPL(spi_bitbang_transfer);
402 392
403/*----------------------------------------------------------------------*/ 393/*----------------------------------------------------------------------*/
404 394
@@ -428,20 +418,22 @@ EXPORT_SYMBOL_GPL(spi_bitbang_transfer);
428int spi_bitbang_start(struct spi_bitbang *bitbang) 418int spi_bitbang_start(struct spi_bitbang *bitbang)
429{ 419{
430 struct spi_master *master = bitbang->master; 420 struct spi_master *master = bitbang->master;
431 int status;
432 421
433 if (!master || !bitbang->chipselect) 422 if (!master || !bitbang->chipselect)
434 return -EINVAL; 423 return -EINVAL;
435 424
436 INIT_WORK(&bitbang->work, bitbang_work);
437 spin_lock_init(&bitbang->lock); 425 spin_lock_init(&bitbang->lock);
438 INIT_LIST_HEAD(&bitbang->queue);
439 426
440 if (!master->mode_bits) 427 if (!master->mode_bits)
441 master->mode_bits = SPI_CPOL | SPI_CPHA | bitbang->flags; 428 master->mode_bits = SPI_CPOL | SPI_CPHA | bitbang->flags;
442 429
443 if (!master->transfer) 430 if (master->transfer || master->transfer_one_message)
444 master->transfer = spi_bitbang_transfer; 431 return -EINVAL;
432
433 master->prepare_transfer_hardware = spi_bitbang_prepare_hardware;
434 master->unprepare_transfer_hardware = spi_bitbang_unprepare_hardware;
435 master->transfer_one_message = spi_bitbang_transfer_one;
436
445 if (!bitbang->txrx_bufs) { 437 if (!bitbang->txrx_bufs) {
446 bitbang->use_dma = 0; 438 bitbang->use_dma = 0;
447 bitbang->txrx_bufs = spi_bitbang_bufs; 439 bitbang->txrx_bufs = spi_bitbang_bufs;
@@ -452,34 +444,12 @@ int spi_bitbang_start(struct spi_bitbang *bitbang)
452 master->setup = spi_bitbang_setup; 444 master->setup = spi_bitbang_setup;
453 master->cleanup = spi_bitbang_cleanup; 445 master->cleanup = spi_bitbang_cleanup;
454 } 446 }
455 } else if (!master->setup)
456 return -EINVAL;
457 if (master->transfer == spi_bitbang_transfer &&
458 !bitbang->setup_transfer)
459 return -EINVAL;
460
461 /* this task is the only thing to touch the SPI bits */
462 bitbang->busy = 0;
463 bitbang->workqueue = create_singlethread_workqueue(
464 dev_name(master->dev.parent));
465 if (bitbang->workqueue == NULL) {
466 status = -EBUSY;
467 goto err1;
468 } 447 }
469 448
470 /* driver may get busy before register() returns, especially 449 /* driver may get busy before register() returns, especially
471 * if someone registered boardinfo for devices 450 * if someone registered boardinfo for devices
472 */ 451 */
473 status = spi_register_master(master); 452 return spi_register_master(master);
474 if (status < 0)
475 goto err2;
476
477 return status;
478
479err2:
480 destroy_workqueue(bitbang->workqueue);
481err1:
482 return status;
483} 453}
484EXPORT_SYMBOL_GPL(spi_bitbang_start); 454EXPORT_SYMBOL_GPL(spi_bitbang_start);
485 455
@@ -490,10 +460,6 @@ int spi_bitbang_stop(struct spi_bitbang *bitbang)
490{ 460{
491 spi_unregister_master(bitbang->master); 461 spi_unregister_master(bitbang->master);
492 462
493 WARN_ON(!list_empty(&bitbang->queue));
494
495 destroy_workqueue(bitbang->workqueue);
496
497 return 0; 463 return 0;
498} 464}
499EXPORT_SYMBOL_GPL(spi_bitbang_stop); 465EXPORT_SYMBOL_GPL(spi_bitbang_stop);
diff --git a/drivers/spi/spi-clps711x.c b/drivers/spi/spi-clps711x.c
index 17965fe225cc..5655acf55bfe 100644
--- a/drivers/spi/spi-clps711x.c
+++ b/drivers/spi/spi-clps711x.c
@@ -239,11 +239,8 @@ static int spi_clps711x_probe(struct platform_device *pdev)
239 } 239 }
240 240
241 dev_err(&pdev->dev, "Failed to register master\n"); 241 dev_err(&pdev->dev, "Failed to register master\n");
242 devm_free_irq(&pdev->dev, IRQ_SSEOTI, hw);
243 242
244clk_out: 243clk_out:
245 devm_clk_put(&pdev->dev, hw->spi_clk);
246
247err_out: 244err_out:
248 while (--i >= 0) 245 while (--i >= 0)
249 if (gpio_is_valid(hw->chipselect[i])) 246 if (gpio_is_valid(hw->chipselect[i]))
@@ -261,13 +258,10 @@ static int spi_clps711x_remove(struct platform_device *pdev)
261 struct spi_master *master = platform_get_drvdata(pdev); 258 struct spi_master *master = platform_get_drvdata(pdev);
262 struct spi_clps711x_data *hw = spi_master_get_devdata(master); 259 struct spi_clps711x_data *hw = spi_master_get_devdata(master);
263 260
264 devm_free_irq(&pdev->dev, IRQ_SSEOTI, hw);
265
266 for (i = 0; i < master->num_chipselect; i++) 261 for (i = 0; i < master->num_chipselect; i++)
267 if (gpio_is_valid(hw->chipselect[i])) 262 if (gpio_is_valid(hw->chipselect[i]))
268 gpio_free(hw->chipselect[i]); 263 gpio_free(hw->chipselect[i]);
269 264
270 devm_clk_put(&pdev->dev, hw->spi_clk);
271 spi_unregister_master(master); 265 spi_unregister_master(master);
272 kfree(master); 266 kfree(master);
273 267
diff --git a/drivers/spi/spi-davinci.c b/drivers/spi/spi-davinci.c
index 222d3e37fc28..707966bd5610 100644
--- a/drivers/spi/spi-davinci.c
+++ b/drivers/spi/spi-davinci.c
@@ -609,7 +609,7 @@ static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
609 else 609 else
610 buf = (void *)t->tx_buf; 610 buf = (void *)t->tx_buf;
611 t->tx_dma = dma_map_single(&spi->dev, buf, 611 t->tx_dma = dma_map_single(&spi->dev, buf,
612 t->len, DMA_FROM_DEVICE); 612 t->len, DMA_TO_DEVICE);
613 if (!t->tx_dma) { 613 if (!t->tx_dma) {
614 ret = -EFAULT; 614 ret = -EFAULT;
615 goto err_tx_map; 615 goto err_tx_map;
diff --git a/drivers/spi/spi-efm32.c b/drivers/spi/spi-efm32.c
new file mode 100644
index 000000000000..7d84418a01d8
--- /dev/null
+++ b/drivers/spi/spi-efm32.c
@@ -0,0 +1,516 @@
1/*
2 * Copyright (C) 2012-2013 Uwe Kleine-Koenig for Pengutronix
3 *
4 * This program is free software; you can redistribute it and/or modify it under
5 * the terms of the GNU General Public License version 2 as published by the
6 * Free Software Foundation.
7 */
8#include <linux/kernel.h>
9#include <linux/io.h>
10#include <linux/spi/spi.h>
11#include <linux/spi/spi_bitbang.h>
12#include <linux/gpio.h>
13#include <linux/interrupt.h>
14#include <linux/platform_device.h>
15#include <linux/clk.h>
16#include <linux/err.h>
17#include <linux/module.h>
18#include <linux/of_gpio.h>
19#include <linux/platform_data/efm32-spi.h>
20
21#define DRIVER_NAME "efm32-spi"
22
23#define MASK_VAL(mask, val) ((val << __ffs(mask)) & mask)
24
25#define REG_CTRL 0x00
26#define REG_CTRL_SYNC 0x0001
27#define REG_CTRL_CLKPOL 0x0100
28#define REG_CTRL_CLKPHA 0x0200
29#define REG_CTRL_MSBF 0x0400
30#define REG_CTRL_TXBIL 0x1000
31
32#define REG_FRAME 0x04
33#define REG_FRAME_DATABITS__MASK 0x000f
34#define REG_FRAME_DATABITS(n) ((n) - 3)
35
36#define REG_CMD 0x0c
37#define REG_CMD_RXEN 0x0001
38#define REG_CMD_RXDIS 0x0002
39#define REG_CMD_TXEN 0x0004
40#define REG_CMD_TXDIS 0x0008
41#define REG_CMD_MASTEREN 0x0010
42
43#define REG_STATUS 0x10
44#define REG_STATUS_TXENS 0x0002
45#define REG_STATUS_TXC 0x0020
46#define REG_STATUS_TXBL 0x0040
47#define REG_STATUS_RXDATAV 0x0080
48
49#define REG_CLKDIV 0x14
50
51#define REG_RXDATAX 0x18
52#define REG_RXDATAX_RXDATA__MASK 0x01ff
53#define REG_RXDATAX_PERR 0x4000
54#define REG_RXDATAX_FERR 0x8000
55
56#define REG_TXDATA 0x34
57
58#define REG_IF 0x40
59#define REG_IF_TXBL 0x0002
60#define REG_IF_RXDATAV 0x0004
61
62#define REG_IFS 0x44
63#define REG_IFC 0x48
64#define REG_IEN 0x4c
65
66#define REG_ROUTE 0x54
67#define REG_ROUTE_RXPEN 0x0001
68#define REG_ROUTE_TXPEN 0x0002
69#define REG_ROUTE_CLKPEN 0x0008
70#define REG_ROUTE_LOCATION__MASK 0x0700
71#define REG_ROUTE_LOCATION(n) MASK_VAL(REG_ROUTE_LOCATION__MASK, (n))
72
73struct efm32_spi_ddata {
74 struct spi_bitbang bitbang;
75
76 spinlock_t lock;
77
78 struct clk *clk;
79 void __iomem *base;
80 unsigned int rxirq, txirq;
81 struct efm32_spi_pdata pdata;
82
83 /* irq data */
84 struct completion done;
85 const u8 *tx_buf;
86 u8 *rx_buf;
87 unsigned tx_len, rx_len;
88
89 /* chip selects */
90 unsigned csgpio[];
91};
92
93#define ddata_to_dev(ddata) (&(ddata->bitbang.master->dev))
94#define efm32_spi_vdbg(ddata, format, arg...) \
95 dev_vdbg(ddata_to_dev(ddata), format, ##arg)
96
97static void efm32_spi_write32(struct efm32_spi_ddata *ddata,
98 u32 value, unsigned offset)
99{
100 writel_relaxed(value, ddata->base + offset);
101}
102
103static u32 efm32_spi_read32(struct efm32_spi_ddata *ddata, unsigned offset)
104{
105 return readl_relaxed(ddata->base + offset);
106}
107
108static void efm32_spi_chipselect(struct spi_device *spi, int is_on)
109{
110 struct efm32_spi_ddata *ddata = spi_master_get_devdata(spi->master);
111 int value = !(spi->mode & SPI_CS_HIGH) == !(is_on == BITBANG_CS_ACTIVE);
112
113 gpio_set_value(ddata->csgpio[spi->chip_select], value);
114}
115
116static int efm32_spi_setup_transfer(struct spi_device *spi,
117 struct spi_transfer *t)
118{
119 struct efm32_spi_ddata *ddata = spi_master_get_devdata(spi->master);
120
121 unsigned bpw = t->bits_per_word ?: spi->bits_per_word;
122 unsigned speed = t->speed_hz ?: spi->max_speed_hz;
123 unsigned long clkfreq = clk_get_rate(ddata->clk);
124 u32 clkdiv;
125
126 efm32_spi_write32(ddata, REG_CTRL_SYNC | REG_CTRL_MSBF |
127 (spi->mode & SPI_CPHA ? REG_CTRL_CLKPHA : 0) |
128 (spi->mode & SPI_CPOL ? REG_CTRL_CLKPOL : 0), REG_CTRL);
129
130 efm32_spi_write32(ddata,
131 REG_FRAME_DATABITS(bpw), REG_FRAME);
132
133 if (2 * speed >= clkfreq)
134 clkdiv = 0;
135 else
136 clkdiv = 64 * (DIV_ROUND_UP(2 * clkfreq, speed) - 4);
137
138 if (clkdiv > (1U << 21))
139 return -EINVAL;
140
141 efm32_spi_write32(ddata, clkdiv, REG_CLKDIV);
142 efm32_spi_write32(ddata, REG_CMD_MASTEREN, REG_CMD);
143 efm32_spi_write32(ddata, REG_CMD_RXEN | REG_CMD_TXEN, REG_CMD);
144
145 return 0;
146}
147
148static void efm32_spi_tx_u8(struct efm32_spi_ddata *ddata)
149{
150 u8 val = 0;
151
152 if (ddata->tx_buf) {
153 val = *ddata->tx_buf;
154 ddata->tx_buf++;
155 }
156
157 ddata->tx_len--;
158 efm32_spi_write32(ddata, val, REG_TXDATA);
159 efm32_spi_vdbg(ddata, "%s: tx 0x%x\n", __func__, val);
160}
161
162static void efm32_spi_rx_u8(struct efm32_spi_ddata *ddata)
163{
164 u32 rxdata = efm32_spi_read32(ddata, REG_RXDATAX);
165 efm32_spi_vdbg(ddata, "%s: rx 0x%x\n", __func__, rxdata);
166
167 if (ddata->rx_buf) {
168 *ddata->rx_buf = rxdata;
169 ddata->rx_buf++;
170 }
171
172 ddata->rx_len--;
173}
174
175static void efm32_spi_filltx(struct efm32_spi_ddata *ddata)
176{
177 while (ddata->tx_len &&
178 ddata->tx_len + 2 > ddata->rx_len &&
179 efm32_spi_read32(ddata, REG_STATUS) & REG_STATUS_TXBL) {
180 efm32_spi_tx_u8(ddata);
181 }
182}
183
184static int efm32_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
185{
186 struct efm32_spi_ddata *ddata = spi_master_get_devdata(spi->master);
187 int ret = -EBUSY;
188
189 spin_lock_irq(&ddata->lock);
190
191 if (ddata->tx_buf || ddata->rx_buf)
192 goto out_unlock;
193
194 ddata->tx_buf = t->tx_buf;
195 ddata->rx_buf = t->rx_buf;
196 ddata->tx_len = ddata->rx_len =
197 t->len * DIV_ROUND_UP(t->bits_per_word, 8);
198
199 efm32_spi_filltx(ddata);
200
201 init_completion(&ddata->done);
202
203 efm32_spi_write32(ddata, REG_IF_TXBL | REG_IF_RXDATAV, REG_IEN);
204
205 spin_unlock_irq(&ddata->lock);
206
207 wait_for_completion(&ddata->done);
208
209 spin_lock_irq(&ddata->lock);
210
211 ret = t->len - max(ddata->tx_len, ddata->rx_len);
212
213 efm32_spi_write32(ddata, 0, REG_IEN);
214 ddata->tx_buf = ddata->rx_buf = NULL;
215
216out_unlock:
217 spin_unlock_irq(&ddata->lock);
218
219 return ret;
220}
221
222static irqreturn_t efm32_spi_rxirq(int irq, void *data)
223{
224 struct efm32_spi_ddata *ddata = data;
225 irqreturn_t ret = IRQ_NONE;
226
227 spin_lock(&ddata->lock);
228
229 while (ddata->rx_len > 0 &&
230 efm32_spi_read32(ddata, REG_STATUS) &
231 REG_STATUS_RXDATAV) {
232 efm32_spi_rx_u8(ddata);
233
234 ret = IRQ_HANDLED;
235 }
236
237 if (!ddata->rx_len) {
238 u32 ien = efm32_spi_read32(ddata, REG_IEN);
239
240 ien &= ~REG_IF_RXDATAV;
241
242 efm32_spi_write32(ddata, ien, REG_IEN);
243
244 complete(&ddata->done);
245 }
246
247 spin_unlock(&ddata->lock);
248
249 return ret;
250}
251
252static irqreturn_t efm32_spi_txirq(int irq, void *data)
253{
254 struct efm32_spi_ddata *ddata = data;
255
256 efm32_spi_vdbg(ddata,
257 "%s: txlen = %u, rxlen = %u, if=0x%08x, stat=0x%08x\n",
258 __func__, ddata->tx_len, ddata->rx_len,
259 efm32_spi_read32(ddata, REG_IF),
260 efm32_spi_read32(ddata, REG_STATUS));
261
262 spin_lock(&ddata->lock);
263
264 efm32_spi_filltx(ddata);
265
266 efm32_spi_vdbg(ddata, "%s: txlen = %u, rxlen = %u\n",
267 __func__, ddata->tx_len, ddata->rx_len);
268
269 if (!ddata->tx_len) {
270 u32 ien = efm32_spi_read32(ddata, REG_IEN);
271
272 ien &= ~REG_IF_TXBL;
273
274 efm32_spi_write32(ddata, ien, REG_IEN);
275 efm32_spi_vdbg(ddata, "disable TXBL\n");
276 }
277
278 spin_unlock(&ddata->lock);
279
280 return IRQ_HANDLED;
281}
282
283static const struct efm32_spi_pdata efm32_spi_pdata_default = {
284 .location = 1,
285};
286
287static u32 efm32_spi_get_configured_location(struct efm32_spi_ddata *ddata)
288{
289 u32 reg = efm32_spi_read32(ddata, REG_ROUTE);
290
291 return (reg & REG_ROUTE_LOCATION__MASK) >> __ffs(REG_ROUTE_LOCATION__MASK);
292}
293
294static int efm32_spi_probe_dt(struct platform_device *pdev,
295 struct spi_master *master, struct efm32_spi_ddata *ddata)
296{
297 struct device_node *np = pdev->dev.of_node;
298 u32 location;
299 int ret;
300
301 if (!np)
302 return 1;
303
304 ret = of_property_read_u32(np, "location", &location);
305 if (!ret) {
306 dev_dbg(&pdev->dev, "using location %u\n", location);
307 } else {
308 /* default to location configured in hardware */
309 location = efm32_spi_get_configured_location(ddata);
310
311 dev_info(&pdev->dev, "fall back to location %u\n", location);
312 }
313
314 ddata->pdata.location = location;
315
316 /* spi core takes care about the bus number using an alias */
317 master->bus_num = -1;
318
319 return 0;
320}
321
322static int efm32_spi_probe(struct platform_device *pdev)
323{
324 struct efm32_spi_ddata *ddata;
325 struct resource *res;
326 int ret;
327 struct spi_master *master;
328 struct device_node *np = pdev->dev.of_node;
329 unsigned int num_cs, i;
330
331 num_cs = of_gpio_named_count(np, "cs-gpios");
332
333 master = spi_alloc_master(&pdev->dev,
334 sizeof(*ddata) + num_cs * sizeof(unsigned));
335 if (!master) {
336 dev_dbg(&pdev->dev,
337 "failed to allocate spi master controller\n");
338 return -ENOMEM;
339 }
340 platform_set_drvdata(pdev, master);
341
342 master->dev.of_node = pdev->dev.of_node;
343
344 master->num_chipselect = num_cs;
345 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
346 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
347
348 ddata = spi_master_get_devdata(master);
349
350 ddata->bitbang.master = spi_master_get(master);
351 ddata->bitbang.chipselect = efm32_spi_chipselect;
352 ddata->bitbang.setup_transfer = efm32_spi_setup_transfer;
353 ddata->bitbang.txrx_bufs = efm32_spi_txrx_bufs;
354
355 spin_lock_init(&ddata->lock);
356
357 ddata->clk = devm_clk_get(&pdev->dev, NULL);
358 if (IS_ERR(ddata->clk)) {
359 ret = PTR_ERR(ddata->clk);
360 dev_err(&pdev->dev, "failed to get clock: %d\n", ret);
361 goto err;
362 }
363
364 for (i = 0; i < num_cs; ++i) {
365 ret = of_get_named_gpio(np, "cs-gpios", i);
366 if (ret < 0) {
367 dev_err(&pdev->dev, "failed to get csgpio#%u (%d)\n",
368 i, ret);
369 goto err;
370 }
371 ddata->csgpio[i] = ret;
372 dev_dbg(&pdev->dev, "csgpio#%u = %u\n", i, ddata->csgpio[i]);
373 ret = devm_gpio_request_one(&pdev->dev, ddata->csgpio[i],
374 GPIOF_OUT_INIT_LOW, DRIVER_NAME);
375 if (ret < 0) {
376 dev_err(&pdev->dev,
377 "failed to configure csgpio#%u (%d)\n",
378 i, ret);
379 goto err;
380 }
381 }
382
383 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
384 if (!res) {
385 ret = -ENODEV;
386 dev_err(&pdev->dev, "failed to determine base address\n");
387 goto err;
388 }
389
390 if (resource_size(res) < 60) {
391 ret = -EINVAL;
392 dev_err(&pdev->dev, "memory resource too small\n");
393 goto err;
394 }
395
396 ddata->base = devm_ioremap_resource(&pdev->dev, res);
397 if (IS_ERR(ddata->base)) {
398 ret = PTR_ERR(ddata->base);
399 goto err;
400 }
401
402 ret = platform_get_irq(pdev, 0);
403 if (ret <= 0) {
404 dev_err(&pdev->dev, "failed to get rx irq (%d)\n", ret);
405 goto err;
406 }
407
408 ddata->rxirq = ret;
409
410 ret = platform_get_irq(pdev, 1);
411 if (ret <= 0)
412 ret = ddata->rxirq + 1;
413
414 ddata->txirq = ret;
415
416 ret = clk_prepare_enable(ddata->clk);
417 if (ret < 0) {
418 dev_err(&pdev->dev, "failed to enable clock (%d)\n", ret);
419 goto err;
420 }
421
422 ret = efm32_spi_probe_dt(pdev, master, ddata);
423 if (ret > 0) {
424 /* not created by device tree */
425 const struct efm32_spi_pdata *pdata =
426 dev_get_platdata(&pdev->dev);
427
428 if (pdata)
429 ddata->pdata = *pdata;
430 else
431 ddata->pdata.location =
432 efm32_spi_get_configured_location(ddata);
433
434 master->bus_num = pdev->id;
435
436 } else if (ret < 0) {
437 goto err_disable_clk;
438 }
439
440 efm32_spi_write32(ddata, 0, REG_IEN);
441 efm32_spi_write32(ddata, REG_ROUTE_TXPEN | REG_ROUTE_RXPEN |
442 REG_ROUTE_CLKPEN |
443 REG_ROUTE_LOCATION(ddata->pdata.location), REG_ROUTE);
444
445 ret = request_irq(ddata->rxirq, efm32_spi_rxirq,
446 0, DRIVER_NAME " rx", ddata);
447 if (ret) {
448 dev_err(&pdev->dev, "failed to register rxirq (%d)\n", ret);
449 goto err_disable_clk;
450 }
451
452 ret = request_irq(ddata->txirq, efm32_spi_txirq,
453 0, DRIVER_NAME " tx", ddata);
454 if (ret) {
455 dev_err(&pdev->dev, "failed to register txirq (%d)\n", ret);
456 goto err_free_rx_irq;
457 }
458
459 ret = spi_bitbang_start(&ddata->bitbang);
460 if (ret) {
461 dev_err(&pdev->dev, "spi_bitbang_start failed (%d)\n", ret);
462
463 free_irq(ddata->txirq, ddata);
464err_free_rx_irq:
465 free_irq(ddata->rxirq, ddata);
466err_disable_clk:
467 clk_disable_unprepare(ddata->clk);
468err:
469 spi_master_put(master);
470 kfree(master);
471 }
472
473 return ret;
474}
475
476static int efm32_spi_remove(struct platform_device *pdev)
477{
478 struct spi_master *master = platform_get_drvdata(pdev);
479 struct efm32_spi_ddata *ddata = spi_master_get_devdata(master);
480
481 efm32_spi_write32(ddata, 0, REG_IEN);
482
483 free_irq(ddata->txirq, ddata);
484 free_irq(ddata->rxirq, ddata);
485 clk_disable_unprepare(ddata->clk);
486 spi_master_put(master);
487 kfree(master);
488
489 return 0;
490}
491
492static const struct of_device_id efm32_spi_dt_ids[] = {
493 {
494 .compatible = "efm32,spi",
495 }, {
496 /* sentinel */
497 }
498};
499MODULE_DEVICE_TABLE(of, efm32_spi_dt_ids);
500
501static struct platform_driver efm32_spi_driver = {
502 .probe = efm32_spi_probe,
503 .remove = efm32_spi_remove,
504
505 .driver = {
506 .name = DRIVER_NAME,
507 .owner = THIS_MODULE,
508 .of_match_table = efm32_spi_dt_ids,
509 },
510};
511module_platform_driver(efm32_spi_driver);
512
513MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>");
514MODULE_DESCRIPTION("EFM32 SPI driver");
515MODULE_LICENSE("GPL v2");
516MODULE_ALIAS("platform:" DRIVER_NAME);
diff --git a/drivers/spi/spi-ep93xx.c b/drivers/spi/spi-ep93xx.c
index cad30b8a1d71..31611f7d7be9 100644
--- a/drivers/spi/spi-ep93xx.c
+++ b/drivers/spi/spi-ep93xx.c
@@ -26,7 +26,6 @@
26#include <linux/interrupt.h> 26#include <linux/interrupt.h>
27#include <linux/module.h> 27#include <linux/module.h>
28#include <linux/platform_device.h> 28#include <linux/platform_device.h>
29#include <linux/workqueue.h>
30#include <linux/sched.h> 29#include <linux/sched.h>
31#include <linux/scatterlist.h> 30#include <linux/scatterlist.h>
32#include <linux/spi/spi.h> 31#include <linux/spi/spi.h>
@@ -70,19 +69,13 @@
70 69
71/** 70/**
72 * struct ep93xx_spi - EP93xx SPI controller structure 71 * struct ep93xx_spi - EP93xx SPI controller structure
73 * @lock: spinlock that protects concurrent accesses to fields @running,
74 * @current_msg and @msg_queue
75 * @pdev: pointer to platform device 72 * @pdev: pointer to platform device
76 * @clk: clock for the controller 73 * @clk: clock for the controller
77 * @regs_base: pointer to ioremap()'d registers 74 * @regs_base: pointer to ioremap()'d registers
78 * @sspdr_phys: physical address of the SSPDR register 75 * @sspdr_phys: physical address of the SSPDR register
79 * @min_rate: minimum clock rate (in Hz) supported by the controller 76 * @min_rate: minimum clock rate (in Hz) supported by the controller
80 * @max_rate: maximum clock rate (in Hz) supported by the controller 77 * @max_rate: maximum clock rate (in Hz) supported by the controller
81 * @running: is the queue running
82 * @wq: workqueue used by the driver
83 * @msg_work: work that is queued for the driver
84 * @wait: wait here until given transfer is completed 78 * @wait: wait here until given transfer is completed
85 * @msg_queue: queue for the messages
86 * @current_msg: message that is currently processed (or %NULL if none) 79 * @current_msg: message that is currently processed (or %NULL if none)
87 * @tx: current byte in transfer to transmit 80 * @tx: current byte in transfer to transmit
88 * @rx: current byte in transfer to receive 81 * @rx: current byte in transfer to receive
@@ -96,30 +89,15 @@
96 * @tx_sgt: sg table for TX transfers 89 * @tx_sgt: sg table for TX transfers
97 * @zeropage: dummy page used as RX buffer when only TX buffer is passed in by 90 * @zeropage: dummy page used as RX buffer when only TX buffer is passed in by
98 * the client 91 * the client
99 *
100 * This structure holds EP93xx SPI controller specific information. When
101 * @running is %true, driver accepts transfer requests from protocol drivers.
102 * @current_msg is used to hold pointer to the message that is currently
103 * processed. If @current_msg is %NULL, it means that no processing is going
104 * on.
105 *
106 * Most of the fields are only written once and they can be accessed without
107 * taking the @lock. Fields that are accessed concurrently are: @current_msg,
108 * @running, and @msg_queue.
109 */ 92 */
110struct ep93xx_spi { 93struct ep93xx_spi {
111 spinlock_t lock;
112 const struct platform_device *pdev; 94 const struct platform_device *pdev;
113 struct clk *clk; 95 struct clk *clk;
114 void __iomem *regs_base; 96 void __iomem *regs_base;
115 unsigned long sspdr_phys; 97 unsigned long sspdr_phys;
116 unsigned long min_rate; 98 unsigned long min_rate;
117 unsigned long max_rate; 99 unsigned long max_rate;
118 bool running;
119 struct workqueue_struct *wq;
120 struct work_struct msg_work;
121 struct completion wait; 100 struct completion wait;
122 struct list_head msg_queue;
123 struct spi_message *current_msg; 101 struct spi_message *current_msg;
124 size_t tx; 102 size_t tx;
125 size_t rx; 103 size_t rx;
@@ -136,50 +114,36 @@ struct ep93xx_spi {
136/** 114/**
137 * struct ep93xx_spi_chip - SPI device hardware settings 115 * struct ep93xx_spi_chip - SPI device hardware settings
138 * @spi: back pointer to the SPI device 116 * @spi: back pointer to the SPI device
139 * @rate: max rate in hz this chip supports
140 * @div_cpsr: cpsr (pre-scaler) divider
141 * @div_scr: scr divider
142 * @dss: bits per word (4 - 16 bits)
143 * @ops: private chip operations 117 * @ops: private chip operations
144 *
145 * This structure is used to store hardware register specific settings for each
146 * SPI device. Settings are written to hardware by function
147 * ep93xx_spi_chip_setup().
148 */ 118 */
149struct ep93xx_spi_chip { 119struct ep93xx_spi_chip {
150 const struct spi_device *spi; 120 const struct spi_device *spi;
151 unsigned long rate;
152 u8 div_cpsr;
153 u8 div_scr;
154 u8 dss;
155 struct ep93xx_spi_chip_ops *ops; 121 struct ep93xx_spi_chip_ops *ops;
156}; 122};
157 123
158/* converts bits per word to CR0.DSS value */ 124/* converts bits per word to CR0.DSS value */
159#define bits_per_word_to_dss(bpw) ((bpw) - 1) 125#define bits_per_word_to_dss(bpw) ((bpw) - 1)
160 126
161static inline void 127static void ep93xx_spi_write_u8(const struct ep93xx_spi *espi,
162ep93xx_spi_write_u8(const struct ep93xx_spi *espi, u16 reg, u8 value) 128 u16 reg, u8 value)
163{ 129{
164 __raw_writeb(value, espi->regs_base + reg); 130 writeb(value, espi->regs_base + reg);
165} 131}
166 132
167static inline u8 133static u8 ep93xx_spi_read_u8(const struct ep93xx_spi *spi, u16 reg)
168ep93xx_spi_read_u8(const struct ep93xx_spi *spi, u16 reg)
169{ 134{
170 return __raw_readb(spi->regs_base + reg); 135 return readb(spi->regs_base + reg);
171} 136}
172 137
173static inline void 138static void ep93xx_spi_write_u16(const struct ep93xx_spi *espi,
174ep93xx_spi_write_u16(const struct ep93xx_spi *espi, u16 reg, u16 value) 139 u16 reg, u16 value)
175{ 140{
176 __raw_writew(value, espi->regs_base + reg); 141 writew(value, espi->regs_base + reg);
177} 142}
178 143
179static inline u16 144static u16 ep93xx_spi_read_u16(const struct ep93xx_spi *spi, u16 reg)
180ep93xx_spi_read_u16(const struct ep93xx_spi *spi, u16 reg)
181{ 145{
182 return __raw_readw(spi->regs_base + reg); 146 return readw(spi->regs_base + reg);
183} 147}
184 148
185static int ep93xx_spi_enable(const struct ep93xx_spi *espi) 149static int ep93xx_spi_enable(const struct ep93xx_spi *espi)
@@ -230,17 +194,13 @@ static void ep93xx_spi_disable_interrupts(const struct ep93xx_spi *espi)
230/** 194/**
231 * ep93xx_spi_calc_divisors() - calculates SPI clock divisors 195 * ep93xx_spi_calc_divisors() - calculates SPI clock divisors
232 * @espi: ep93xx SPI controller struct 196 * @espi: ep93xx SPI controller struct
233 * @chip: divisors are calculated for this chip
234 * @rate: desired SPI output clock rate 197 * @rate: desired SPI output clock rate
235 * 198 * @div_cpsr: pointer to return the cpsr (pre-scaler) divider
236 * Function calculates cpsr (clock pre-scaler) and scr divisors based on 199 * @div_scr: pointer to return the scr divider
237 * given @rate and places them to @chip->div_cpsr and @chip->div_scr. If,
238 * for some reason, divisors cannot be calculated nothing is stored and
239 * %-EINVAL is returned.
240 */ 200 */
241static int ep93xx_spi_calc_divisors(const struct ep93xx_spi *espi, 201static int ep93xx_spi_calc_divisors(const struct ep93xx_spi *espi,
242 struct ep93xx_spi_chip *chip, 202 unsigned long rate,
243 unsigned long rate) 203 u8 *div_cpsr, u8 *div_scr)
244{ 204{
245 unsigned long spi_clk_rate = clk_get_rate(espi->clk); 205 unsigned long spi_clk_rate = clk_get_rate(espi->clk);
246 int cpsr, scr; 206 int cpsr, scr;
@@ -248,7 +208,7 @@ static int ep93xx_spi_calc_divisors(const struct ep93xx_spi *espi,
248 /* 208 /*
249 * Make sure that max value is between values supported by the 209 * Make sure that max value is between values supported by the
250 * controller. Note that minimum value is already checked in 210 * controller. Note that minimum value is already checked in
251 * ep93xx_spi_transfer(). 211 * ep93xx_spi_transfer_one_message().
252 */ 212 */
253 rate = clamp(rate, espi->min_rate, espi->max_rate); 213 rate = clamp(rate, espi->min_rate, espi->max_rate);
254 214
@@ -263,8 +223,8 @@ static int ep93xx_spi_calc_divisors(const struct ep93xx_spi *espi,
263 for (cpsr = 2; cpsr <= 254; cpsr += 2) { 223 for (cpsr = 2; cpsr <= 254; cpsr += 2) {
264 for (scr = 0; scr <= 255; scr++) { 224 for (scr = 0; scr <= 255; scr++) {
265 if ((spi_clk_rate / (cpsr * (scr + 1))) <= rate) { 225 if ((spi_clk_rate / (cpsr * (scr + 1))) <= rate) {
266 chip->div_scr = (u8)scr; 226 *div_scr = (u8)scr;
267 chip->div_cpsr = (u8)cpsr; 227 *div_cpsr = (u8)cpsr;
268 return 0; 228 return 0;
269 } 229 }
270 } 230 }
@@ -319,73 +279,11 @@ static int ep93xx_spi_setup(struct spi_device *spi)
319 spi_set_ctldata(spi, chip); 279 spi_set_ctldata(spi, chip);
320 } 280 }
321 281
322 if (spi->max_speed_hz != chip->rate) {
323 int err;
324
325 err = ep93xx_spi_calc_divisors(espi, chip, spi->max_speed_hz);
326 if (err != 0) {
327 spi_set_ctldata(spi, NULL);
328 kfree(chip);
329 return err;
330 }
331 chip->rate = spi->max_speed_hz;
332 }
333
334 chip->dss = bits_per_word_to_dss(spi->bits_per_word);
335
336 ep93xx_spi_cs_control(spi, false); 282 ep93xx_spi_cs_control(spi, false);
337 return 0; 283 return 0;
338} 284}
339 285
340/** 286/**
341 * ep93xx_spi_transfer() - queue message to be transferred
342 * @spi: target SPI device
343 * @msg: message to be transferred
344 *
345 * This function is called by SPI device drivers when they are going to transfer
346 * a new message. It simply puts the message in the queue and schedules
347 * workqueue to perform the actual transfer later on.
348 *
349 * Returns %0 on success and negative error in case of failure.
350 */
351static int ep93xx_spi_transfer(struct spi_device *spi, struct spi_message *msg)
352{
353 struct ep93xx_spi *espi = spi_master_get_devdata(spi->master);
354 struct spi_transfer *t;
355 unsigned long flags;
356
357 if (!msg || !msg->complete)
358 return -EINVAL;
359
360 /* first validate each transfer */
361 list_for_each_entry(t, &msg->transfers, transfer_list) {
362 if (t->speed_hz && t->speed_hz < espi->min_rate)
363 return -EINVAL;
364 }
365
366 /*
367 * Now that we own the message, let's initialize it so that it is
368 * suitable for us. We use @msg->status to signal whether there was
369 * error in transfer and @msg->state is used to hold pointer to the
370 * current transfer (or %NULL if no active current transfer).
371 */
372 msg->state = NULL;
373 msg->status = 0;
374 msg->actual_length = 0;
375
376 spin_lock_irqsave(&espi->lock, flags);
377 if (!espi->running) {
378 spin_unlock_irqrestore(&espi->lock, flags);
379 return -ESHUTDOWN;
380 }
381 list_add_tail(&msg->queue, &espi->msg_queue);
382 queue_work(espi->wq, &espi->msg_work);
383 spin_unlock_irqrestore(&espi->lock, flags);
384
385 return 0;
386}
387
388/**
389 * ep93xx_spi_cleanup() - cleans up master controller specific state 287 * ep93xx_spi_cleanup() - cleans up master controller specific state
390 * @spi: SPI device to cleanup 288 * @spi: SPI device to cleanup
391 * 289 *
@@ -409,39 +307,40 @@ static void ep93xx_spi_cleanup(struct spi_device *spi)
409 * ep93xx_spi_chip_setup() - configures hardware according to given @chip 307 * ep93xx_spi_chip_setup() - configures hardware according to given @chip
410 * @espi: ep93xx SPI controller struct 308 * @espi: ep93xx SPI controller struct
411 * @chip: chip specific settings 309 * @chip: chip specific settings
412 * 310 * @speed_hz: transfer speed
413 * This function sets up the actual hardware registers with settings given in 311 * @bits_per_word: transfer bits_per_word
414 * @chip. Note that no validation is done so make sure that callers validate
415 * settings before calling this.
416 */ 312 */
417static void ep93xx_spi_chip_setup(const struct ep93xx_spi *espi, 313static int ep93xx_spi_chip_setup(const struct ep93xx_spi *espi,
418 const struct ep93xx_spi_chip *chip) 314 const struct ep93xx_spi_chip *chip,
315 u32 speed_hz, u8 bits_per_word)
419{ 316{
317 u8 dss = bits_per_word_to_dss(bits_per_word);
318 u8 div_cpsr = 0;
319 u8 div_scr = 0;
420 u16 cr0; 320 u16 cr0;
321 int err;
421 322
422 cr0 = chip->div_scr << SSPCR0_SCR_SHIFT; 323 err = ep93xx_spi_calc_divisors(espi, speed_hz, &div_cpsr, &div_scr);
324 if (err)
325 return err;
326
327 cr0 = div_scr << SSPCR0_SCR_SHIFT;
423 cr0 |= (chip->spi->mode & (SPI_CPHA|SPI_CPOL)) << SSPCR0_MODE_SHIFT; 328 cr0 |= (chip->spi->mode & (SPI_CPHA|SPI_CPOL)) << SSPCR0_MODE_SHIFT;
424 cr0 |= chip->dss; 329 cr0 |= dss;
425 330
426 dev_dbg(&espi->pdev->dev, "setup: mode %d, cpsr %d, scr %d, dss %d\n", 331 dev_dbg(&espi->pdev->dev, "setup: mode %d, cpsr %d, scr %d, dss %d\n",
427 chip->spi->mode, chip->div_cpsr, chip->div_scr, chip->dss); 332 chip->spi->mode, div_cpsr, div_scr, dss);
428 dev_dbg(&espi->pdev->dev, "setup: cr0 %#x", cr0); 333 dev_dbg(&espi->pdev->dev, "setup: cr0 %#x", cr0);
429 334
430 ep93xx_spi_write_u8(espi, SSPCPSR, chip->div_cpsr); 335 ep93xx_spi_write_u8(espi, SSPCPSR, div_cpsr);
431 ep93xx_spi_write_u16(espi, SSPCR0, cr0); 336 ep93xx_spi_write_u16(espi, SSPCR0, cr0);
432}
433
434static inline int bits_per_word(const struct ep93xx_spi *espi)
435{
436 struct spi_message *msg = espi->current_msg;
437 struct spi_transfer *t = msg->state;
438 337
439 return t->bits_per_word; 338 return 0;
440} 339}
441 340
442static void ep93xx_do_write(struct ep93xx_spi *espi, struct spi_transfer *t) 341static void ep93xx_do_write(struct ep93xx_spi *espi, struct spi_transfer *t)
443{ 342{
444 if (bits_per_word(espi) > 8) { 343 if (t->bits_per_word > 8) {
445 u16 tx_val = 0; 344 u16 tx_val = 0;
446 345
447 if (t->tx_buf) 346 if (t->tx_buf)
@@ -460,7 +359,7 @@ static void ep93xx_do_write(struct ep93xx_spi *espi, struct spi_transfer *t)
460 359
461static void ep93xx_do_read(struct ep93xx_spi *espi, struct spi_transfer *t) 360static void ep93xx_do_read(struct ep93xx_spi *espi, struct spi_transfer *t)
462{ 361{
463 if (bits_per_word(espi) > 8) { 362 if (t->bits_per_word > 8) {
464 u16 rx_val; 363 u16 rx_val;
465 364
466 rx_val = ep93xx_spi_read_u16(espi, SSPDR); 365 rx_val = ep93xx_spi_read_u16(espi, SSPDR);
@@ -546,7 +445,7 @@ ep93xx_spi_dma_prepare(struct ep93xx_spi *espi, enum dma_transfer_direction dir)
546 size_t len = t->len; 445 size_t len = t->len;
547 int i, ret, nents; 446 int i, ret, nents;
548 447
549 if (bits_per_word(espi) > 8) 448 if (t->bits_per_word > 8)
550 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES; 449 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
551 else 450 else
552 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE; 451 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
@@ -610,7 +509,7 @@ ep93xx_spi_dma_prepare(struct ep93xx_spi *espi, enum dma_transfer_direction dir)
610 } 509 }
611 510
612 if (WARN_ON(len)) { 511 if (WARN_ON(len)) {
613 dev_warn(&espi->pdev->dev, "len = %d expected 0!", len); 512 dev_warn(&espi->pdev->dev, "len = %zu expected 0!", len);
614 return ERR_PTR(-EINVAL); 513 return ERR_PTR(-EINVAL);
615 } 514 }
616 515
@@ -708,37 +607,16 @@ static void ep93xx_spi_process_transfer(struct ep93xx_spi *espi,
708 struct spi_transfer *t) 607 struct spi_transfer *t)
709{ 608{
710 struct ep93xx_spi_chip *chip = spi_get_ctldata(msg->spi); 609 struct ep93xx_spi_chip *chip = spi_get_ctldata(msg->spi);
610 int err;
711 611
712 msg->state = t; 612 msg->state = t;
713 613
714 /* 614 err = ep93xx_spi_chip_setup(espi, chip, t->speed_hz, t->bits_per_word);
715 * Handle any transfer specific settings if needed. We use 615 if (err) {
716 * temporary chip settings here and restore original later when 616 dev_err(&espi->pdev->dev,
717 * the transfer is finished. 617 "failed to setup chip for transfer\n");
718 */ 618 msg->status = err;
719 if (t->speed_hz || t->bits_per_word) { 619 return;
720 struct ep93xx_spi_chip tmp_chip = *chip;
721
722 if (t->speed_hz) {
723 int err;
724
725 err = ep93xx_spi_calc_divisors(espi, &tmp_chip,
726 t->speed_hz);
727 if (err) {
728 dev_err(&espi->pdev->dev,
729 "failed to adjust speed\n");
730 msg->status = err;
731 return;
732 }
733 }
734
735 if (t->bits_per_word)
736 tmp_chip.dss = bits_per_word_to_dss(t->bits_per_word);
737
738 /*
739 * Set up temporary new hw settings for this transfer.
740 */
741 ep93xx_spi_chip_setup(espi, &tmp_chip);
742 } 620 }
743 621
744 espi->rx = 0; 622 espi->rx = 0;
@@ -783,9 +661,6 @@ static void ep93xx_spi_process_transfer(struct ep93xx_spi *espi,
783 ep93xx_spi_cs_control(msg->spi, true); 661 ep93xx_spi_cs_control(msg->spi, true);
784 } 662 }
785 } 663 }
786
787 if (t->speed_hz || t->bits_per_word)
788 ep93xx_spi_chip_setup(espi, chip);
789} 664}
790 665
791/* 666/*
@@ -838,10 +713,8 @@ static void ep93xx_spi_process_message(struct ep93xx_spi *espi,
838 espi->fifo_level = 0; 713 espi->fifo_level = 0;
839 714
840 /* 715 /*
841 * Update SPI controller registers according to spi device and assert 716 * Assert the chipselect.
842 * the chipselect.
843 */ 717 */
844 ep93xx_spi_chip_setup(espi, spi_get_ctldata(msg->spi));
845 ep93xx_spi_cs_control(msg->spi, true); 718 ep93xx_spi_cs_control(msg->spi, true);
846 719
847 list_for_each_entry(t, &msg->transfers, transfer_list) { 720 list_for_each_entry(t, &msg->transfers, transfer_list) {
@@ -858,50 +731,29 @@ static void ep93xx_spi_process_message(struct ep93xx_spi *espi,
858 ep93xx_spi_disable(espi); 731 ep93xx_spi_disable(espi);
859} 732}
860 733
861#define work_to_espi(work) (container_of((work), struct ep93xx_spi, msg_work)) 734static int ep93xx_spi_transfer_one_message(struct spi_master *master,
862 735 struct spi_message *msg)
863/**
864 * ep93xx_spi_work() - EP93xx SPI workqueue worker function
865 * @work: work struct
866 *
867 * Workqueue worker function. This function is called when there are new
868 * SPI messages to be processed. Message is taken out from the queue and then
869 * passed to ep93xx_spi_process_message().
870 *
871 * After message is transferred, protocol driver is notified by calling
872 * @msg->complete(). In case of error, @msg->status is set to negative error
873 * number, otherwise it contains zero (and @msg->actual_length is updated).
874 */
875static void ep93xx_spi_work(struct work_struct *work)
876{ 736{
877 struct ep93xx_spi *espi = work_to_espi(work); 737 struct ep93xx_spi *espi = spi_master_get_devdata(master);
878 struct spi_message *msg; 738 struct spi_transfer *t;
879 739
880 spin_lock_irq(&espi->lock); 740 /* first validate each transfer */
881 if (!espi->running || espi->current_msg || 741 list_for_each_entry(t, &msg->transfers, transfer_list) {
882 list_empty(&espi->msg_queue)) { 742 if (t->speed_hz < espi->min_rate)
883 spin_unlock_irq(&espi->lock); 743 return -EINVAL;
884 return;
885 } 744 }
886 msg = list_first_entry(&espi->msg_queue, struct spi_message, queue);
887 list_del_init(&msg->queue);
888 espi->current_msg = msg;
889 spin_unlock_irq(&espi->lock);
890 745
891 ep93xx_spi_process_message(espi, msg); 746 msg->state = NULL;
747 msg->status = 0;
748 msg->actual_length = 0;
892 749
893 /* 750 espi->current_msg = msg;
894 * Update the current message and re-schedule ourselves if there are 751 ep93xx_spi_process_message(espi, msg);
895 * more messages in the queue.
896 */
897 spin_lock_irq(&espi->lock);
898 espi->current_msg = NULL; 752 espi->current_msg = NULL;
899 if (espi->running && !list_empty(&espi->msg_queue))
900 queue_work(espi->wq, &espi->msg_work);
901 spin_unlock_irq(&espi->lock);
902 753
903 /* notify the protocol driver that we are done with this message */ 754 spi_finalize_current_message(master);
904 msg->complete(msg->context); 755
756 return 0;
905} 757}
906 758
907static irqreturn_t ep93xx_spi_interrupt(int irq, void *dev_id) 759static irqreturn_t ep93xx_spi_interrupt(int irq, void *dev_id)
@@ -1024,14 +876,24 @@ static int ep93xx_spi_probe(struct platform_device *pdev)
1024 876
1025 info = pdev->dev.platform_data; 877 info = pdev->dev.platform_data;
1026 878
879 irq = platform_get_irq(pdev, 0);
880 if (irq < 0) {
881 dev_err(&pdev->dev, "failed to get irq resources\n");
882 return -EBUSY;
883 }
884
885 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
886 if (!res) {
887 dev_err(&pdev->dev, "unable to get iomem resource\n");
888 return -ENODEV;
889 }
890
1027 master = spi_alloc_master(&pdev->dev, sizeof(*espi)); 891 master = spi_alloc_master(&pdev->dev, sizeof(*espi));
1028 if (!master) { 892 if (!master)
1029 dev_err(&pdev->dev, "failed to allocate spi master\n");
1030 return -ENOMEM; 893 return -ENOMEM;
1031 }
1032 894
1033 master->setup = ep93xx_spi_setup; 895 master->setup = ep93xx_spi_setup;
1034 master->transfer = ep93xx_spi_transfer; 896 master->transfer_one_message = ep93xx_spi_transfer_one_message;
1035 master->cleanup = ep93xx_spi_cleanup; 897 master->cleanup = ep93xx_spi_cleanup;
1036 master->bus_num = pdev->id; 898 master->bus_num = pdev->id;
1037 master->num_chipselect = info->num_chipselect; 899 master->num_chipselect = info->num_chipselect;
@@ -1042,14 +904,13 @@ static int ep93xx_spi_probe(struct platform_device *pdev)
1042 904
1043 espi = spi_master_get_devdata(master); 905 espi = spi_master_get_devdata(master);
1044 906
1045 espi->clk = clk_get(&pdev->dev, NULL); 907 espi->clk = devm_clk_get(&pdev->dev, NULL);
1046 if (IS_ERR(espi->clk)) { 908 if (IS_ERR(espi->clk)) {
1047 dev_err(&pdev->dev, "unable to get spi clock\n"); 909 dev_err(&pdev->dev, "unable to get spi clock\n");
1048 error = PTR_ERR(espi->clk); 910 error = PTR_ERR(espi->clk);
1049 goto fail_release_master; 911 goto fail_release_master;
1050 } 912 }
1051 913
1052 spin_lock_init(&espi->lock);
1053 init_completion(&espi->wait); 914 init_completion(&espi->wait);
1054 915
1055 /* 916 /*
@@ -1060,55 +921,31 @@ static int ep93xx_spi_probe(struct platform_device *pdev)
1060 espi->min_rate = clk_get_rate(espi->clk) / (254 * 256); 921 espi->min_rate = clk_get_rate(espi->clk) / (254 * 256);
1061 espi->pdev = pdev; 922 espi->pdev = pdev;
1062 923
1063 irq = platform_get_irq(pdev, 0);
1064 if (irq < 0) {
1065 error = -EBUSY;
1066 dev_err(&pdev->dev, "failed to get irq resources\n");
1067 goto fail_put_clock;
1068 }
1069
1070 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1071 if (!res) {
1072 dev_err(&pdev->dev, "unable to get iomem resource\n");
1073 error = -ENODEV;
1074 goto fail_put_clock;
1075 }
1076
1077 espi->sspdr_phys = res->start + SSPDR; 924 espi->sspdr_phys = res->start + SSPDR;
1078 925
1079 espi->regs_base = devm_ioremap_resource(&pdev->dev, res); 926 espi->regs_base = devm_ioremap_resource(&pdev->dev, res);
1080 if (IS_ERR(espi->regs_base)) { 927 if (IS_ERR(espi->regs_base)) {
1081 error = PTR_ERR(espi->regs_base); 928 error = PTR_ERR(espi->regs_base);
1082 goto fail_put_clock; 929 goto fail_release_master;
1083 } 930 }
1084 931
1085 error = devm_request_irq(&pdev->dev, irq, ep93xx_spi_interrupt, 932 error = devm_request_irq(&pdev->dev, irq, ep93xx_spi_interrupt,
1086 0, "ep93xx-spi", espi); 933 0, "ep93xx-spi", espi);
1087 if (error) { 934 if (error) {
1088 dev_err(&pdev->dev, "failed to request irq\n"); 935 dev_err(&pdev->dev, "failed to request irq\n");
1089 goto fail_put_clock; 936 goto fail_release_master;
1090 } 937 }
1091 938
1092 if (info->use_dma && ep93xx_spi_setup_dma(espi)) 939 if (info->use_dma && ep93xx_spi_setup_dma(espi))
1093 dev_warn(&pdev->dev, "DMA setup failed. Falling back to PIO\n"); 940 dev_warn(&pdev->dev, "DMA setup failed. Falling back to PIO\n");
1094 941
1095 espi->wq = create_singlethread_workqueue("ep93xx_spid");
1096 if (!espi->wq) {
1097 dev_err(&pdev->dev, "unable to create workqueue\n");
1098 error = -ENOMEM;
1099 goto fail_free_dma;
1100 }
1101 INIT_WORK(&espi->msg_work, ep93xx_spi_work);
1102 INIT_LIST_HEAD(&espi->msg_queue);
1103 espi->running = true;
1104
1105 /* make sure that the hardware is disabled */ 942 /* make sure that the hardware is disabled */
1106 ep93xx_spi_write_u8(espi, SSPCR1, 0); 943 ep93xx_spi_write_u8(espi, SSPCR1, 0);
1107 944
1108 error = spi_register_master(master); 945 error = spi_register_master(master);
1109 if (error) { 946 if (error) {
1110 dev_err(&pdev->dev, "failed to register SPI master\n"); 947 dev_err(&pdev->dev, "failed to register SPI master\n");
1111 goto fail_free_queue; 948 goto fail_free_dma;
1112 } 949 }
1113 950
1114 dev_info(&pdev->dev, "EP93xx SPI Controller at 0x%08lx irq %d\n", 951 dev_info(&pdev->dev, "EP93xx SPI Controller at 0x%08lx irq %d\n",
@@ -1116,12 +953,8 @@ static int ep93xx_spi_probe(struct platform_device *pdev)
1116 953
1117 return 0; 954 return 0;
1118 955
1119fail_free_queue:
1120 destroy_workqueue(espi->wq);
1121fail_free_dma: 956fail_free_dma:
1122 ep93xx_spi_release_dma(espi); 957 ep93xx_spi_release_dma(espi);
1123fail_put_clock:
1124 clk_put(espi->clk);
1125fail_release_master: 958fail_release_master:
1126 spi_master_put(master); 959 spi_master_put(master);
1127 960
@@ -1133,31 +966,7 @@ static int ep93xx_spi_remove(struct platform_device *pdev)
1133 struct spi_master *master = platform_get_drvdata(pdev); 966 struct spi_master *master = platform_get_drvdata(pdev);
1134 struct ep93xx_spi *espi = spi_master_get_devdata(master); 967 struct ep93xx_spi *espi = spi_master_get_devdata(master);
1135 968
1136 spin_lock_irq(&espi->lock);
1137 espi->running = false;
1138 spin_unlock_irq(&espi->lock);
1139
1140 destroy_workqueue(espi->wq);
1141
1142 /*
1143 * Complete remaining messages with %-ESHUTDOWN status.
1144 */
1145 spin_lock_irq(&espi->lock);
1146 while (!list_empty(&espi->msg_queue)) {
1147 struct spi_message *msg;
1148
1149 msg = list_first_entry(&espi->msg_queue,
1150 struct spi_message, queue);
1151 list_del_init(&msg->queue);
1152 msg->status = -ESHUTDOWN;
1153 spin_unlock_irq(&espi->lock);
1154 msg->complete(msg->context);
1155 spin_lock_irq(&espi->lock);
1156 }
1157 spin_unlock_irq(&espi->lock);
1158
1159 ep93xx_spi_release_dma(espi); 969 ep93xx_spi_release_dma(espi);
1160 clk_put(espi->clk);
1161 970
1162 spi_unregister_master(master); 971 spi_unregister_master(master);
1163 return 0; 972 return 0;
diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c
new file mode 100644
index 000000000000..6cd07d13ecab
--- /dev/null
+++ b/drivers/spi/spi-fsl-dspi.c
@@ -0,0 +1,557 @@
1/*
2 * drivers/spi/spi-fsl-dspi.c
3 *
4 * Copyright 2013 Freescale Semiconductor, Inc.
5 *
6 * Freescale DSPI driver
7 * This file contains a driver for the Freescale DSPI
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 */
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/interrupt.h>
19#include <linux/errno.h>
20#include <linux/platform_device.h>
21#include <linux/sched.h>
22#include <linux/delay.h>
23#include <linux/io.h>
24#include <linux/clk.h>
25#include <linux/err.h>
26#include <linux/spi/spi.h>
27#include <linux/spi/spi_bitbang.h>
28#include <linux/pm_runtime.h>
29#include <linux/of.h>
30#include <linux/of_device.h>
31
32#define DRIVER_NAME "fsl-dspi"
33
34#define TRAN_STATE_RX_VOID 0x01
35#define TRAN_STATE_TX_VOID 0x02
36#define TRAN_STATE_WORD_ODD_NUM 0x04
37
38#define DSPI_FIFO_SIZE 4
39
40#define SPI_MCR 0x00
41#define SPI_MCR_MASTER (1 << 31)
42#define SPI_MCR_PCSIS (0x3F << 16)
43#define SPI_MCR_CLR_TXF (1 << 11)
44#define SPI_MCR_CLR_RXF (1 << 10)
45
46#define SPI_TCR 0x08
47
48#define SPI_CTAR(x) (0x0c + (x * 4))
49#define SPI_CTAR_FMSZ(x) (((x) & 0x0000000f) << 27)
50#define SPI_CTAR_CPOL(x) ((x) << 26)
51#define SPI_CTAR_CPHA(x) ((x) << 25)
52#define SPI_CTAR_LSBFE(x) ((x) << 24)
53#define SPI_CTAR_PCSSCR(x) (((x) & 0x00000003) << 22)
54#define SPI_CTAR_PASC(x) (((x) & 0x00000003) << 20)
55#define SPI_CTAR_PDT(x) (((x) & 0x00000003) << 18)
56#define SPI_CTAR_PBR(x) (((x) & 0x00000003) << 16)
57#define SPI_CTAR_CSSCK(x) (((x) & 0x0000000f) << 12)
58#define SPI_CTAR_ASC(x) (((x) & 0x0000000f) << 8)
59#define SPI_CTAR_DT(x) (((x) & 0x0000000f) << 4)
60#define SPI_CTAR_BR(x) ((x) & 0x0000000f)
61
62#define SPI_CTAR0_SLAVE 0x0c
63
64#define SPI_SR 0x2c
65#define SPI_SR_EOQF 0x10000000
66
67#define SPI_RSER 0x30
68#define SPI_RSER_EOQFE 0x10000000
69
70#define SPI_PUSHR 0x34
71#define SPI_PUSHR_CONT (1 << 31)
72#define SPI_PUSHR_CTAS(x) (((x) & 0x00000007) << 28)
73#define SPI_PUSHR_EOQ (1 << 27)
74#define SPI_PUSHR_CTCNT (1 << 26)
75#define SPI_PUSHR_PCS(x) (((1 << x) & 0x0000003f) << 16)
76#define SPI_PUSHR_TXDATA(x) ((x) & 0x0000ffff)
77
78#define SPI_PUSHR_SLAVE 0x34
79
80#define SPI_POPR 0x38
81#define SPI_POPR_RXDATA(x) ((x) & 0x0000ffff)
82
83#define SPI_TXFR0 0x3c
84#define SPI_TXFR1 0x40
85#define SPI_TXFR2 0x44
86#define SPI_TXFR3 0x48
87#define SPI_RXFR0 0x7c
88#define SPI_RXFR1 0x80
89#define SPI_RXFR2 0x84
90#define SPI_RXFR3 0x88
91
92#define SPI_FRAME_BITS(bits) SPI_CTAR_FMSZ((bits) - 1)
93#define SPI_FRAME_BITS_MASK SPI_CTAR_FMSZ(0xf)
94#define SPI_FRAME_BITS_16 SPI_CTAR_FMSZ(0xf)
95#define SPI_FRAME_BITS_8 SPI_CTAR_FMSZ(0x7)
96
97#define SPI_CS_INIT 0x01
98#define SPI_CS_ASSERT 0x02
99#define SPI_CS_DROP 0x04
100
101struct chip_data {
102 u32 mcr_val;
103 u32 ctar_val;
104 u16 void_write_data;
105};
106
107struct fsl_dspi {
108 struct spi_bitbang bitbang;
109 struct platform_device *pdev;
110
111 void *base;
112 int irq;
113 struct clk *clk;
114
115 struct spi_transfer *cur_transfer;
116 struct chip_data *cur_chip;
117 size_t len;
118 void *tx;
119 void *tx_end;
120 void *rx;
121 void *rx_end;
122 char dataflags;
123 u8 cs;
124 u16 void_write_data;
125
126 wait_queue_head_t waitq;
127 u32 waitflags;
128};
129
130static inline int is_double_byte_mode(struct fsl_dspi *dspi)
131{
132 return ((readl(dspi->base + SPI_CTAR(dspi->cs)) & SPI_FRAME_BITS_MASK)
133 == SPI_FRAME_BITS(8)) ? 0 : 1;
134}
135
136static void set_bit_mode(struct fsl_dspi *dspi, unsigned char bits)
137{
138 u32 temp;
139
140 temp = readl(dspi->base + SPI_CTAR(dspi->cs));
141 temp &= ~SPI_FRAME_BITS_MASK;
142 temp |= SPI_FRAME_BITS(bits);
143 writel(temp, dspi->base + SPI_CTAR(dspi->cs));
144}
145
146static void hz_to_spi_baud(char *pbr, char *br, int speed_hz,
147 unsigned long clkrate)
148{
149 /* Valid baud rate pre-scaler values */
150 int pbr_tbl[4] = {2, 3, 5, 7};
151 int brs[16] = { 2, 4, 6, 8,
152 16, 32, 64, 128,
153 256, 512, 1024, 2048,
154 4096, 8192, 16384, 32768 };
155 int temp, i = 0, j = 0;
156
157 temp = clkrate / 2 / speed_hz;
158
159 for (i = 0; i < ARRAY_SIZE(pbr_tbl); i++)
160 for (j = 0; j < ARRAY_SIZE(brs); j++) {
161 if (pbr_tbl[i] * brs[j] >= temp) {
162 *pbr = i;
163 *br = j;
164 return;
165 }
166 }
167
168 pr_warn("Can not find valid buad rate,speed_hz is %d,clkrate is %ld\
169 ,we use the max prescaler value.\n", speed_hz, clkrate);
170 *pbr = ARRAY_SIZE(pbr_tbl) - 1;
171 *br = ARRAY_SIZE(brs) - 1;
172}
173
174static int dspi_transfer_write(struct fsl_dspi *dspi)
175{
176 int tx_count = 0;
177 int tx_word;
178 u16 d16;
179 u8 d8;
180 u32 dspi_pushr = 0;
181 int first = 1;
182
183 tx_word = is_double_byte_mode(dspi);
184
185 /* If we are in word mode, but only have a single byte to transfer
186 * then switch to byte mode temporarily. Will switch back at the
187 * end of the transfer.
188 */
189 if (tx_word && (dspi->len == 1)) {
190 dspi->dataflags |= TRAN_STATE_WORD_ODD_NUM;
191 set_bit_mode(dspi, 8);
192 tx_word = 0;
193 }
194
195 while (dspi->len && (tx_count < DSPI_FIFO_SIZE)) {
196 if (tx_word) {
197 if (dspi->len == 1)
198 break;
199
200 if (!(dspi->dataflags & TRAN_STATE_TX_VOID)) {
201 d16 = *(u16 *)dspi->tx;
202 dspi->tx += 2;
203 } else {
204 d16 = dspi->void_write_data;
205 }
206
207 dspi_pushr = SPI_PUSHR_TXDATA(d16) |
208 SPI_PUSHR_PCS(dspi->cs) |
209 SPI_PUSHR_CTAS(dspi->cs) |
210 SPI_PUSHR_CONT;
211
212 dspi->len -= 2;
213 } else {
214 if (!(dspi->dataflags & TRAN_STATE_TX_VOID)) {
215
216 d8 = *(u8 *)dspi->tx;
217 dspi->tx++;
218 } else {
219 d8 = (u8)dspi->void_write_data;
220 }
221
222 dspi_pushr = SPI_PUSHR_TXDATA(d8) |
223 SPI_PUSHR_PCS(dspi->cs) |
224 SPI_PUSHR_CTAS(dspi->cs) |
225 SPI_PUSHR_CONT;
226
227 dspi->len--;
228 }
229
230 if (dspi->len == 0 || tx_count == DSPI_FIFO_SIZE - 1) {
231 /* last transfer in the transfer */
232 dspi_pushr |= SPI_PUSHR_EOQ;
233 } else if (tx_word && (dspi->len == 1))
234 dspi_pushr |= SPI_PUSHR_EOQ;
235
236 if (first) {
237 first = 0;
238 dspi_pushr |= SPI_PUSHR_CTCNT; /* clear counter */
239 }
240
241 writel(dspi_pushr, dspi->base + SPI_PUSHR);
242 tx_count++;
243 }
244
245 return tx_count * (tx_word + 1);
246}
247
248static int dspi_transfer_read(struct fsl_dspi *dspi)
249{
250 int rx_count = 0;
251 int rx_word = is_double_byte_mode(dspi);
252 u16 d;
253 while ((dspi->rx < dspi->rx_end)
254 && (rx_count < DSPI_FIFO_SIZE)) {
255 if (rx_word) {
256 if ((dspi->rx_end - dspi->rx) == 1)
257 break;
258
259 d = SPI_POPR_RXDATA(readl(dspi->base + SPI_POPR));
260
261 if (!(dspi->dataflags & TRAN_STATE_RX_VOID))
262 *(u16 *)dspi->rx = d;
263 dspi->rx += 2;
264
265 } else {
266 d = SPI_POPR_RXDATA(readl(dspi->base + SPI_POPR));
267 if (!(dspi->dataflags & TRAN_STATE_RX_VOID))
268 *(u8 *)dspi->rx = d;
269 dspi->rx++;
270 }
271 rx_count++;
272 }
273
274 return rx_count;
275}
276
277static int dspi_txrx_transfer(struct spi_device *spi, struct spi_transfer *t)
278{
279 struct fsl_dspi *dspi = spi_master_get_devdata(spi->master);
280 dspi->cur_transfer = t;
281 dspi->cur_chip = spi_get_ctldata(spi);
282 dspi->cs = spi->chip_select;
283 dspi->void_write_data = dspi->cur_chip->void_write_data;
284
285 dspi->dataflags = 0;
286 dspi->tx = (void *)t->tx_buf;
287 dspi->tx_end = dspi->tx + t->len;
288 dspi->rx = t->rx_buf;
289 dspi->rx_end = dspi->rx + t->len;
290 dspi->len = t->len;
291
292 if (!dspi->rx)
293 dspi->dataflags |= TRAN_STATE_RX_VOID;
294
295 if (!dspi->tx)
296 dspi->dataflags |= TRAN_STATE_TX_VOID;
297
298 writel(dspi->cur_chip->mcr_val, dspi->base + SPI_MCR);
299 writel(dspi->cur_chip->ctar_val, dspi->base + SPI_CTAR(dspi->cs));
300 writel(SPI_RSER_EOQFE, dspi->base + SPI_RSER);
301
302 if (t->speed_hz)
303 writel(dspi->cur_chip->ctar_val,
304 dspi->base + SPI_CTAR(dspi->cs));
305
306 dspi_transfer_write(dspi);
307
308 if (wait_event_interruptible(dspi->waitq, dspi->waitflags))
309 dev_err(&dspi->pdev->dev, "wait transfer complete fail!\n");
310 dspi->waitflags = 0;
311
312 return t->len - dspi->len;
313}
314
315static void dspi_chipselect(struct spi_device *spi, int value)
316{
317 struct fsl_dspi *dspi = spi_master_get_devdata(spi->master);
318 u32 pushr = readl(dspi->base + SPI_PUSHR);
319
320 switch (value) {
321 case BITBANG_CS_ACTIVE:
322 pushr |= SPI_PUSHR_CONT;
323 case BITBANG_CS_INACTIVE:
324 pushr &= ~SPI_PUSHR_CONT;
325 }
326
327 writel(pushr, dspi->base + SPI_PUSHR);
328}
329
330static int dspi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
331{
332 struct chip_data *chip;
333 struct fsl_dspi *dspi = spi_master_get_devdata(spi->master);
334 unsigned char br = 0, pbr = 0, fmsz = 0;
335
336 /* Only alloc on first setup */
337 chip = spi_get_ctldata(spi);
338 if (chip == NULL) {
339 chip = kcalloc(1, sizeof(struct chip_data), GFP_KERNEL);
340 if (!chip)
341 return -ENOMEM;
342 }
343
344 chip->mcr_val = SPI_MCR_MASTER | SPI_MCR_PCSIS |
345 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF;
346 if ((spi->bits_per_word >= 4) && (spi->bits_per_word <= 16)) {
347 fmsz = spi->bits_per_word - 1;
348 } else {
349 pr_err("Invalid wordsize\n");
350 kfree(chip);
351 return -ENODEV;
352 }
353
354 chip->void_write_data = 0;
355
356 hz_to_spi_baud(&pbr, &br,
357 spi->max_speed_hz, clk_get_rate(dspi->clk));
358
359 chip->ctar_val = SPI_CTAR_FMSZ(fmsz)
360 | SPI_CTAR_CPOL(spi->mode & SPI_CPOL ? 1 : 0)
361 | SPI_CTAR_CPHA(spi->mode & SPI_CPHA ? 1 : 0)
362 | SPI_CTAR_LSBFE(spi->mode & SPI_LSB_FIRST ? 1 : 0)
363 | SPI_CTAR_PBR(pbr)
364 | SPI_CTAR_BR(br);
365
366 spi_set_ctldata(spi, chip);
367
368 return 0;
369}
370
371static int dspi_setup(struct spi_device *spi)
372{
373 if (!spi->max_speed_hz)
374 return -EINVAL;
375
376 if (!spi->bits_per_word)
377 spi->bits_per_word = 8;
378
379 return dspi_setup_transfer(spi, NULL);
380}
381
382static irqreturn_t dspi_interrupt(int irq, void *dev_id)
383{
384 struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id;
385
386 writel(SPI_SR_EOQF, dspi->base + SPI_SR);
387
388 dspi_transfer_read(dspi);
389
390 if (!dspi->len) {
391 if (dspi->dataflags & TRAN_STATE_WORD_ODD_NUM)
392 set_bit_mode(dspi, 16);
393 dspi->waitflags = 1;
394 wake_up_interruptible(&dspi->waitq);
395 } else {
396 dspi_transfer_write(dspi);
397
398 return IRQ_HANDLED;
399 }
400
401 return IRQ_HANDLED;
402}
403
404static struct of_device_id fsl_dspi_dt_ids[] = {
405 { .compatible = "fsl,vf610-dspi", .data = NULL, },
406 { /* sentinel */ }
407};
408MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids);
409
410#ifdef CONFIG_PM_SLEEP
411static int dspi_suspend(struct device *dev)
412{
413 struct spi_master *master = dev_get_drvdata(dev);
414 struct fsl_dspi *dspi = spi_master_get_devdata(master);
415
416 spi_master_suspend(master);
417 clk_disable_unprepare(dspi->clk);
418
419 return 0;
420}
421
422static int dspi_resume(struct device *dev)
423{
424
425 struct spi_master *master = dev_get_drvdata(dev);
426 struct fsl_dspi *dspi = spi_master_get_devdata(master);
427
428 clk_prepare_enable(dspi->clk);
429 spi_master_resume(master);
430
431 return 0;
432}
433#endif /* CONFIG_PM_SLEEP */
434
435static const struct dev_pm_ops dspi_pm = {
436 SET_SYSTEM_SLEEP_PM_OPS(dspi_suspend, dspi_resume)
437};
438
439static int dspi_probe(struct platform_device *pdev)
440{
441 struct device_node *np = pdev->dev.of_node;
442 struct spi_master *master;
443 struct fsl_dspi *dspi;
444 struct resource *res;
445 int ret = 0, cs_num, bus_num;
446
447 master = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi));
448 if (!master)
449 return -ENOMEM;
450
451 dspi = spi_master_get_devdata(master);
452 dspi->pdev = pdev;
453 dspi->bitbang.master = spi_master_get(master);
454 dspi->bitbang.chipselect = dspi_chipselect;
455 dspi->bitbang.setup_transfer = dspi_setup_transfer;
456 dspi->bitbang.txrx_bufs = dspi_txrx_transfer;
457 dspi->bitbang.master->setup = dspi_setup;
458 dspi->bitbang.master->dev.of_node = pdev->dev.of_node;
459
460 master->mode_bits = SPI_CPOL | SPI_CPHA;
461 master->bits_per_word_mask = SPI_BPW_MASK(4) | SPI_BPW_MASK(8) |
462 SPI_BPW_MASK(16);
463
464 ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num);
465 if (ret < 0) {
466 dev_err(&pdev->dev, "can't get spi-num-chipselects\n");
467 goto out_master_put;
468 }
469 master->num_chipselect = cs_num;
470
471 ret = of_property_read_u32(np, "bus-num", &bus_num);
472 if (ret < 0) {
473 dev_err(&pdev->dev, "can't get bus-num\n");
474 goto out_master_put;
475 }
476 master->bus_num = bus_num;
477
478 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
479 if (!res) {
480 dev_err(&pdev->dev, "can't get platform resource\n");
481 ret = -EINVAL;
482 goto out_master_put;
483 }
484
485 dspi->base = devm_ioremap_resource(&pdev->dev, res);
486 if (!dspi->base) {
487 ret = -EINVAL;
488 goto out_master_put;
489 }
490
491 dspi->irq = platform_get_irq(pdev, 0);
492 if (dspi->irq < 0) {
493 dev_err(&pdev->dev, "can't get platform irq\n");
494 ret = dspi->irq;
495 goto out_master_put;
496 }
497
498 ret = devm_request_irq(&pdev->dev, dspi->irq, dspi_interrupt, 0,
499 pdev->name, dspi);
500 if (ret < 0) {
501 dev_err(&pdev->dev, "Unable to attach DSPI interrupt\n");
502 goto out_master_put;
503 }
504
505 dspi->clk = devm_clk_get(&pdev->dev, "dspi");
506 if (IS_ERR(dspi->clk)) {
507 ret = PTR_ERR(dspi->clk);
508 dev_err(&pdev->dev, "unable to get clock\n");
509 goto out_master_put;
510 }
511 clk_prepare_enable(dspi->clk);
512
513 init_waitqueue_head(&dspi->waitq);
514 platform_set_drvdata(pdev, dspi);
515
516 ret = spi_bitbang_start(&dspi->bitbang);
517 if (ret != 0) {
518 dev_err(&pdev->dev, "Problem registering DSPI master\n");
519 goto out_clk_put;
520 }
521
522 pr_info(KERN_INFO "Freescale DSPI master initialized\n");
523 return ret;
524
525out_clk_put:
526 clk_disable_unprepare(dspi->clk);
527out_master_put:
528 spi_master_put(master);
529 platform_set_drvdata(pdev, NULL);
530
531 return ret;
532}
533
534static int dspi_remove(struct platform_device *pdev)
535{
536 struct fsl_dspi *dspi = platform_get_drvdata(pdev);
537
538 /* Disconnect from the SPI framework */
539 spi_bitbang_stop(&dspi->bitbang);
540 spi_master_put(dspi->bitbang.master);
541
542 return 0;
543}
544
545static struct platform_driver fsl_dspi_driver = {
546 .driver.name = DRIVER_NAME,
547 .driver.of_match_table = fsl_dspi_dt_ids,
548 .driver.owner = THIS_MODULE,
549 .driver.pm = &dspi_pm,
550 .probe = dspi_probe,
551 .remove = dspi_remove,
552};
553module_platform_driver(fsl_dspi_driver);
554
555MODULE_DESCRIPTION("Freescale DSPI Controller Driver");
556MODULE_LICENSE("GPL v2");
557MODULE_ALIAS("platform:" DRIVER_NAME);
diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
index 7db4f43ee4d8..15323d8bd9cf 100644
--- a/drivers/spi/spi-imx.c
+++ b/drivers/spi/spi-imx.c
@@ -619,6 +619,7 @@ static const struct of_device_id spi_imx_dt_ids[] = {
619 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, }, 619 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
620 { /* sentinel */ } 620 { /* sentinel */ }
621}; 621};
622MODULE_DEVICE_TABLE(of, spi_imx_dt_ids);
622 623
623static void spi_imx_chipselect(struct spi_device *spi, int is_active) 624static void spi_imx_chipselect(struct spi_device *spi, int is_active)
624{ 625{
@@ -796,10 +797,11 @@ static int spi_imx_probe(struct platform_device *pdev)
796 if (!gpio_is_valid(cs_gpio)) 797 if (!gpio_is_valid(cs_gpio))
797 continue; 798 continue;
798 799
799 ret = gpio_request(spi_imx->chipselect[i], DRIVER_NAME); 800 ret = devm_gpio_request(&pdev->dev, spi_imx->chipselect[i],
801 DRIVER_NAME);
800 if (ret) { 802 if (ret) {
801 dev_err(&pdev->dev, "can't get cs gpios\n"); 803 dev_err(&pdev->dev, "can't get cs gpios\n");
802 goto out_gpio_free; 804 goto out_master_put;
803 } 805 }
804 } 806 }
805 807
@@ -816,50 +818,44 @@ static int spi_imx_probe(struct platform_device *pdev)
816 (struct spi_imx_devtype_data *) pdev->id_entry->driver_data; 818 (struct spi_imx_devtype_data *) pdev->id_entry->driver_data;
817 819
818 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 820 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
819 if (!res) { 821 spi_imx->base = devm_ioremap_resource(&pdev->dev, res);
820 dev_err(&pdev->dev, "can't get platform resource\n"); 822 if (IS_ERR(spi_imx->base)) {
821 ret = -ENOMEM; 823 ret = PTR_ERR(spi_imx->base);
822 goto out_gpio_free; 824 goto out_master_put;
823 }
824
825 if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
826 dev_err(&pdev->dev, "request_mem_region failed\n");
827 ret = -EBUSY;
828 goto out_gpio_free;
829 }
830
831 spi_imx->base = ioremap(res->start, resource_size(res));
832 if (!spi_imx->base) {
833 ret = -EINVAL;
834 goto out_release_mem;
835 } 825 }
836 826
837 spi_imx->irq = platform_get_irq(pdev, 0); 827 spi_imx->irq = platform_get_irq(pdev, 0);
838 if (spi_imx->irq < 0) { 828 if (spi_imx->irq < 0) {
839 ret = -EINVAL; 829 ret = -EINVAL;
840 goto out_iounmap; 830 goto out_master_put;
841 } 831 }
842 832
843 ret = request_irq(spi_imx->irq, spi_imx_isr, 0, DRIVER_NAME, spi_imx); 833 ret = devm_request_irq(&pdev->dev, spi_imx->irq, spi_imx_isr, 0,
834 DRIVER_NAME, spi_imx);
844 if (ret) { 835 if (ret) {
845 dev_err(&pdev->dev, "can't get irq%d: %d\n", spi_imx->irq, ret); 836 dev_err(&pdev->dev, "can't get irq%d: %d\n", spi_imx->irq, ret);
846 goto out_iounmap; 837 goto out_master_put;
847 } 838 }
848 839
849 spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 840 spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
850 if (IS_ERR(spi_imx->clk_ipg)) { 841 if (IS_ERR(spi_imx->clk_ipg)) {
851 ret = PTR_ERR(spi_imx->clk_ipg); 842 ret = PTR_ERR(spi_imx->clk_ipg);
852 goto out_free_irq; 843 goto out_master_put;
853 } 844 }
854 845
855 spi_imx->clk_per = devm_clk_get(&pdev->dev, "per"); 846 spi_imx->clk_per = devm_clk_get(&pdev->dev, "per");
856 if (IS_ERR(spi_imx->clk_per)) { 847 if (IS_ERR(spi_imx->clk_per)) {
857 ret = PTR_ERR(spi_imx->clk_per); 848 ret = PTR_ERR(spi_imx->clk_per);
858 goto out_free_irq; 849 goto out_master_put;
859 } 850 }
860 851
861 clk_prepare_enable(spi_imx->clk_per); 852 ret = clk_prepare_enable(spi_imx->clk_per);
862 clk_prepare_enable(spi_imx->clk_ipg); 853 if (ret)
854 goto out_master_put;
855
856 ret = clk_prepare_enable(spi_imx->clk_ipg);
857 if (ret)
858 goto out_put_per;
863 859
864 spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per); 860 spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
865 861
@@ -879,47 +875,27 @@ static int spi_imx_probe(struct platform_device *pdev)
879 return ret; 875 return ret;
880 876
881out_clk_put: 877out_clk_put:
882 clk_disable_unprepare(spi_imx->clk_per);
883 clk_disable_unprepare(spi_imx->clk_ipg); 878 clk_disable_unprepare(spi_imx->clk_ipg);
884out_free_irq: 879out_put_per:
885 free_irq(spi_imx->irq, spi_imx); 880 clk_disable_unprepare(spi_imx->clk_per);
886out_iounmap: 881out_master_put:
887 iounmap(spi_imx->base);
888out_release_mem:
889 release_mem_region(res->start, resource_size(res));
890out_gpio_free:
891 while (--i >= 0) {
892 if (gpio_is_valid(spi_imx->chipselect[i]))
893 gpio_free(spi_imx->chipselect[i]);
894 }
895 spi_master_put(master); 882 spi_master_put(master);
896 kfree(master); 883
897 return ret; 884 return ret;
898} 885}
899 886
900static int spi_imx_remove(struct platform_device *pdev) 887static int spi_imx_remove(struct platform_device *pdev)
901{ 888{
902 struct spi_master *master = platform_get_drvdata(pdev); 889 struct spi_master *master = platform_get_drvdata(pdev);
903 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
904 struct spi_imx_data *spi_imx = spi_master_get_devdata(master); 890 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
905 int i;
906 891
907 spi_bitbang_stop(&spi_imx->bitbang); 892 spi_bitbang_stop(&spi_imx->bitbang);
908 893
909 writel(0, spi_imx->base + MXC_CSPICTRL); 894 writel(0, spi_imx->base + MXC_CSPICTRL);
910 clk_disable_unprepare(spi_imx->clk_per);
911 clk_disable_unprepare(spi_imx->clk_ipg); 895 clk_disable_unprepare(spi_imx->clk_ipg);
912 free_irq(spi_imx->irq, spi_imx); 896 clk_disable_unprepare(spi_imx->clk_per);
913 iounmap(spi_imx->base);
914
915 for (i = 0; i < master->num_chipselect; i++)
916 if (gpio_is_valid(spi_imx->chipselect[i]))
917 gpio_free(spi_imx->chipselect[i]);
918
919 spi_master_put(master); 897 spi_master_put(master);
920 898
921 release_mem_region(res->start, resource_size(res));
922
923 return 0; 899 return 0;
924} 900}
925 901
diff --git a/drivers/spi/spi-mpc512x-psc.c b/drivers/spi/spi-mpc512x-psc.c
index 29fce6af5145..85581f307945 100644
--- a/drivers/spi/spi-mpc512x-psc.c
+++ b/drivers/spi/spi-mpc512x-psc.c
@@ -38,7 +38,8 @@ struct mpc512x_psc_spi {
38 struct mpc512x_psc_fifo __iomem *fifo; 38 struct mpc512x_psc_fifo __iomem *fifo;
39 unsigned int irq; 39 unsigned int irq;
40 u8 bits_per_word; 40 u8 bits_per_word;
41 u32 mclk; 41 struct clk *clk_mclk;
42 u32 mclk_rate;
42 43
43 struct completion txisrdone; 44 struct completion txisrdone;
44}; 45};
@@ -72,6 +73,7 @@ static void mpc512x_psc_spi_activate_cs(struct spi_device *spi)
72 struct mpc52xx_psc __iomem *psc = mps->psc; 73 struct mpc52xx_psc __iomem *psc = mps->psc;
73 u32 sicr; 74 u32 sicr;
74 u32 ccr; 75 u32 ccr;
76 int speed;
75 u16 bclkdiv; 77 u16 bclkdiv;
76 78
77 sicr = in_be32(&psc->sicr); 79 sicr = in_be32(&psc->sicr);
@@ -95,10 +97,10 @@ static void mpc512x_psc_spi_activate_cs(struct spi_device *spi)
95 97
96 ccr = in_be32(&psc->ccr); 98 ccr = in_be32(&psc->ccr);
97 ccr &= 0xFF000000; 99 ccr &= 0xFF000000;
98 if (cs->speed_hz) 100 speed = cs->speed_hz;
99 bclkdiv = (mps->mclk / cs->speed_hz) - 1; 101 if (!speed)
100 else 102 speed = 1000000; /* default 1MHz */
101 bclkdiv = (mps->mclk / 1000000) - 1; /* default 1MHz */ 103 bclkdiv = (mps->mclk_rate / speed) - 1;
102 104
103 ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8)); 105 ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8));
104 out_be32(&psc->ccr, ccr); 106 out_be32(&psc->ccr, ccr);
@@ -386,19 +388,11 @@ static int mpc512x_psc_spi_port_config(struct spi_master *master,
386{ 388{
387 struct mpc52xx_psc __iomem *psc = mps->psc; 389 struct mpc52xx_psc __iomem *psc = mps->psc;
388 struct mpc512x_psc_fifo __iomem *fifo = mps->fifo; 390 struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
389 struct clk *spiclk;
390 int ret = 0;
391 char name[32];
392 u32 sicr; 391 u32 sicr;
393 u32 ccr; 392 u32 ccr;
393 int speed;
394 u16 bclkdiv; 394 u16 bclkdiv;
395 395
396 sprintf(name, "psc%d_mclk", master->bus_num);
397 spiclk = clk_get(&master->dev, name);
398 clk_enable(spiclk);
399 mps->mclk = clk_get_rate(spiclk);
400 clk_put(spiclk);
401
402 /* Reset the PSC into a known state */ 396 /* Reset the PSC into a known state */
403 out_8(&psc->command, MPC52xx_PSC_RST_RX); 397 out_8(&psc->command, MPC52xx_PSC_RST_RX);
404 out_8(&psc->command, MPC52xx_PSC_RST_TX); 398 out_8(&psc->command, MPC52xx_PSC_RST_TX);
@@ -425,7 +419,8 @@ static int mpc512x_psc_spi_port_config(struct spi_master *master,
425 419
426 ccr = in_be32(&psc->ccr); 420 ccr = in_be32(&psc->ccr);
427 ccr &= 0xFF000000; 421 ccr &= 0xFF000000;
428 bclkdiv = (mps->mclk / 1000000) - 1; /* default 1MHz */ 422 speed = 1000000; /* default 1MHz */
423 bclkdiv = (mps->mclk_rate / speed) - 1;
429 ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8)); 424 ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8));
430 out_be32(&psc->ccr, ccr); 425 out_be32(&psc->ccr, ccr);
431 426
@@ -445,7 +440,7 @@ static int mpc512x_psc_spi_port_config(struct spi_master *master,
445 440
446 mps->bits_per_word = 8; 441 mps->bits_per_word = 8;
447 442
448 return ret; 443 return 0;
449} 444}
450 445
451static irqreturn_t mpc512x_psc_spi_isr(int irq, void *dev_id) 446static irqreturn_t mpc512x_psc_spi_isr(int irq, void *dev_id)
@@ -479,6 +474,9 @@ static int mpc512x_psc_spi_do_probe(struct device *dev, u32 regaddr,
479 struct spi_master *master; 474 struct spi_master *master;
480 int ret; 475 int ret;
481 void *tempp; 476 void *tempp;
477 int psc_num;
478 char clk_name[16];
479 struct clk *clk;
482 480
483 master = spi_alloc_master(dev, sizeof *mps); 481 master = spi_alloc_master(dev, sizeof *mps);
484 if (master == NULL) 482 if (master == NULL)
@@ -521,16 +519,29 @@ static int mpc512x_psc_spi_do_probe(struct device *dev, u32 regaddr,
521 goto free_master; 519 goto free_master;
522 init_completion(&mps->txisrdone); 520 init_completion(&mps->txisrdone);
523 521
522 psc_num = master->bus_num;
523 snprintf(clk_name, sizeof(clk_name), "psc%d_mclk", psc_num);
524 clk = devm_clk_get(dev, clk_name);
525 if (IS_ERR(clk))
526 goto free_irq;
527 ret = clk_prepare_enable(clk);
528 if (ret)
529 goto free_irq;
530 mps->clk_mclk = clk;
531 mps->mclk_rate = clk_get_rate(clk);
532
524 ret = mpc512x_psc_spi_port_config(master, mps); 533 ret = mpc512x_psc_spi_port_config(master, mps);
525 if (ret < 0) 534 if (ret < 0)
526 goto free_irq; 535 goto free_clock;
527 536
528 ret = spi_register_master(master); 537 ret = spi_register_master(master);
529 if (ret < 0) 538 if (ret < 0)
530 goto free_irq; 539 goto free_clock;
531 540
532 return ret; 541 return ret;
533 542
543free_clock:
544 clk_disable_unprepare(mps->clk_mclk);
534free_irq: 545free_irq:
535 free_irq(mps->irq, mps); 546 free_irq(mps->irq, mps);
536free_master: 547free_master:
@@ -547,6 +558,7 @@ static int mpc512x_psc_spi_do_remove(struct device *dev)
547 struct mpc512x_psc_spi *mps = spi_master_get_devdata(master); 558 struct mpc512x_psc_spi *mps = spi_master_get_devdata(master);
548 559
549 spi_unregister_master(master); 560 spi_unregister_master(master);
561 clk_disable_unprepare(mps->clk_mclk);
550 free_irq(mps->irq, mps); 562 free_irq(mps->irq, mps);
551 if (mps->psc) 563 if (mps->psc)
552 iounmap(mps->psc); 564 iounmap(mps->psc);
diff --git a/drivers/spi/spi-mxs.c b/drivers/spi/spi-mxs.c
index 424d38e59421..de7b1141b90f 100644
--- a/drivers/spi/spi-mxs.c
+++ b/drivers/spi/spi-mxs.c
@@ -67,13 +67,8 @@ static int mxs_spi_setup_transfer(struct spi_device *dev,
67{ 67{
68 struct mxs_spi *spi = spi_master_get_devdata(dev->master); 68 struct mxs_spi *spi = spi_master_get_devdata(dev->master);
69 struct mxs_ssp *ssp = &spi->ssp; 69 struct mxs_ssp *ssp = &spi->ssp;
70 uint8_t bits_per_word;
71 uint32_t hz = 0; 70 uint32_t hz = 0;
72 71
73 bits_per_word = dev->bits_per_word;
74 if (t && t->bits_per_word)
75 bits_per_word = t->bits_per_word;
76
77 hz = dev->max_speed_hz; 72 hz = dev->max_speed_hz;
78 if (t && t->speed_hz) 73 if (t && t->speed_hz)
79 hz = min(hz, t->speed_hz); 74 hz = min(hz, t->speed_hz);
@@ -513,7 +508,7 @@ static int mxs_spi_probe(struct platform_device *pdev)
513 508
514 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 509 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
515 irq_err = platform_get_irq(pdev, 0); 510 irq_err = platform_get_irq(pdev, 0);
516 if (!iores || irq_err < 0) 511 if (irq_err < 0)
517 return -EINVAL; 512 return -EINVAL;
518 513
519 base = devm_ioremap_resource(&pdev->dev, iores); 514 base = devm_ioremap_resource(&pdev->dev, iores);
@@ -563,25 +558,31 @@ static int mxs_spi_probe(struct platform_device *pdev)
563 goto out_master_free; 558 goto out_master_free;
564 } 559 }
565 560
566 clk_prepare_enable(ssp->clk); 561 ret = clk_prepare_enable(ssp->clk);
562 if (ret)
563 goto out_dma_release;
564
567 clk_set_rate(ssp->clk, clk_freq); 565 clk_set_rate(ssp->clk, clk_freq);
568 ssp->clk_rate = clk_get_rate(ssp->clk) / 1000; 566 ssp->clk_rate = clk_get_rate(ssp->clk) / 1000;
569 567
570 stmp_reset_block(ssp->base); 568 ret = stmp_reset_block(ssp->base);
569 if (ret)
570 goto out_disable_clk;
571 571
572 platform_set_drvdata(pdev, master); 572 platform_set_drvdata(pdev, master);
573 573
574 ret = spi_register_master(master); 574 ret = spi_register_master(master);
575 if (ret) { 575 if (ret) {
576 dev_err(&pdev->dev, "Cannot register SPI master, %d\n", ret); 576 dev_err(&pdev->dev, "Cannot register SPI master, %d\n", ret);
577 goto out_free_dma; 577 goto out_disable_clk;
578 } 578 }
579 579
580 return 0; 580 return 0;
581 581
582out_free_dma: 582out_disable_clk:
583 dma_release_channel(ssp->dmach);
584 clk_disable_unprepare(ssp->clk); 583 clk_disable_unprepare(ssp->clk);
584out_dma_release:
585 dma_release_channel(ssp->dmach);
585out_master_free: 586out_master_free:
586 spi_master_put(master); 587 spi_master_put(master);
587 return ret; 588 return ret;
@@ -598,11 +599,8 @@ static int mxs_spi_remove(struct platform_device *pdev)
598 ssp = &spi->ssp; 599 ssp = &spi->ssp;
599 600
600 spi_unregister_master(master); 601 spi_unregister_master(master);
601
602 dma_release_channel(ssp->dmach);
603
604 clk_disable_unprepare(ssp->clk); 602 clk_disable_unprepare(ssp->clk);
605 603 dma_release_channel(ssp->dmach);
606 spi_master_put(master); 604 spi_master_put(master);
607 605
608 return 0; 606 return 0;
diff --git a/drivers/spi/spi-nuc900.c b/drivers/spi/spi-nuc900.c
index 150d85453c27..b21f8f20060a 100644
--- a/drivers/spi/spi-nuc900.c
+++ b/drivers/spi/spi-nuc900.c
@@ -174,17 +174,6 @@ static void nuc900_spi_gobusy(struct nuc900_spi *hw)
174 spin_unlock_irqrestore(&hw->lock, flags); 174 spin_unlock_irqrestore(&hw->lock, flags);
175} 175}
176 176
177static int nuc900_spi_setupxfer(struct spi_device *spi,
178 struct spi_transfer *t)
179{
180 return 0;
181}
182
183static int nuc900_spi_setup(struct spi_device *spi)
184{
185 return 0;
186}
187
188static inline unsigned int hw_txbyte(struct nuc900_spi *hw, int count) 177static inline unsigned int hw_txbyte(struct nuc900_spi *hw, int count)
189{ 178{
190 return hw->tx ? hw->tx[count] : 0; 179 return hw->tx ? hw->tx[count] : 0;
@@ -373,14 +362,12 @@ static int nuc900_spi_probe(struct platform_device *pdev)
373 platform_set_drvdata(pdev, hw); 362 platform_set_drvdata(pdev, hw);
374 init_completion(&hw->done); 363 init_completion(&hw->done);
375 364
376 master->mode_bits = SPI_MODE_0; 365 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
377 master->num_chipselect = hw->pdata->num_cs; 366 master->num_chipselect = hw->pdata->num_cs;
378 master->bus_num = hw->pdata->bus_num; 367 master->bus_num = hw->pdata->bus_num;
379 hw->bitbang.master = hw->master; 368 hw->bitbang.master = hw->master;
380 hw->bitbang.setup_transfer = nuc900_spi_setupxfer;
381 hw->bitbang.chipselect = nuc900_spi_chipsel; 369 hw->bitbang.chipselect = nuc900_spi_chipsel;
382 hw->bitbang.txrx_bufs = nuc900_spi_txrx; 370 hw->bitbang.txrx_bufs = nuc900_spi_txrx;
383 hw->bitbang.master->setup = nuc900_spi_setup;
384 371
385 hw->res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 372 hw->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
386 if (hw->res == NULL) { 373 if (hw->res == NULL) {
diff --git a/drivers/spi/spi-oc-tiny.c b/drivers/spi/spi-oc-tiny.c
index 58deb79d046b..d36ba907743d 100644
--- a/drivers/spi/spi-oc-tiny.c
+++ b/drivers/spi/spi-oc-tiny.c
@@ -315,15 +315,11 @@ static int tiny_spi_probe(struct platform_device *pdev)
315 315
316 /* find and map our resources */ 316 /* find and map our resources */
317 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 317 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
318 if (!res) 318 hw->base = devm_ioremap_resource(&pdev->dev, res);
319 goto exit_busy; 319 if (IS_ERR(hw->base)) {
320 if (!devm_request_mem_region(&pdev->dev, res->start, resource_size(res), 320 err = PTR_ERR(hw->base);
321 pdev->name)) 321 goto exit;
322 goto exit_busy; 322 }
323 hw->base = devm_ioremap_nocache(&pdev->dev, res->start,
324 resource_size(res));
325 if (!hw->base)
326 goto exit_busy;
327 /* irq is optional */ 323 /* irq is optional */
328 hw->irq = platform_get_irq(pdev, 0); 324 hw->irq = platform_get_irq(pdev, 0);
329 if (hw->irq >= 0) { 325 if (hw->irq >= 0) {
@@ -337,8 +333,10 @@ static int tiny_spi_probe(struct platform_device *pdev)
337 if (platp) { 333 if (platp) {
338 hw->gpio_cs_count = platp->gpio_cs_count; 334 hw->gpio_cs_count = platp->gpio_cs_count;
339 hw->gpio_cs = platp->gpio_cs; 335 hw->gpio_cs = platp->gpio_cs;
340 if (platp->gpio_cs_count && !platp->gpio_cs) 336 if (platp->gpio_cs_count && !platp->gpio_cs) {
341 goto exit_busy; 337 err = -EBUSY;
338 goto exit;
339 }
342 hw->freq = platp->freq; 340 hw->freq = platp->freq;
343 hw->baudwidth = platp->baudwidth; 341 hw->baudwidth = platp->baudwidth;
344 } else { 342 } else {
@@ -365,8 +363,6 @@ static int tiny_spi_probe(struct platform_device *pdev)
365exit_gpio: 363exit_gpio:
366 while (i-- > 0) 364 while (i-- > 0)
367 gpio_free(hw->gpio_cs[i]); 365 gpio_free(hw->gpio_cs[i]);
368exit_busy:
369 err = -EBUSY;
370exit: 366exit:
371 spi_master_put(master); 367 spi_master_put(master);
372 return err; 368 return err;
diff --git a/drivers/spi/spi-octeon.c b/drivers/spi/spi-octeon.c
index 24daf964a409..5f28ddbe4f7e 100644
--- a/drivers/spi/spi-octeon.c
+++ b/drivers/spi/spi-octeon.c
@@ -28,7 +28,6 @@
28#define OCTEON_SPI_MAX_CLOCK_HZ 16000000 28#define OCTEON_SPI_MAX_CLOCK_HZ 16000000
29 29
30struct octeon_spi { 30struct octeon_spi {
31 struct spi_master *my_master;
32 u64 register_base; 31 u64 register_base;
33 u64 last_cfg; 32 u64 last_cfg;
34 u64 cs_enax; 33 u64 cs_enax;
@@ -64,7 +63,6 @@ static int octeon_spi_do_transfer(struct octeon_spi *p,
64 unsigned int speed_hz; 63 unsigned int speed_hz;
65 int mode; 64 int mode;
66 bool cpha, cpol; 65 bool cpha, cpol;
67 int bits_per_word;
68 const u8 *tx_buf; 66 const u8 *tx_buf;
69 u8 *rx_buf; 67 u8 *rx_buf;
70 int len; 68 int len;
@@ -76,12 +74,9 @@ static int octeon_spi_do_transfer(struct octeon_spi *p,
76 mode = msg_setup->mode; 74 mode = msg_setup->mode;
77 cpha = mode & SPI_CPHA; 75 cpha = mode & SPI_CPHA;
78 cpol = mode & SPI_CPOL; 76 cpol = mode & SPI_CPOL;
79 bits_per_word = msg_setup->bits_per_word;
80 77
81 if (xfer->speed_hz) 78 if (xfer->speed_hz)
82 speed_hz = xfer->speed_hz; 79 speed_hz = xfer->speed_hz;
83 if (xfer->bits_per_word)
84 bits_per_word = xfer->bits_per_word;
85 80
86 if (speed_hz > OCTEON_SPI_MAX_CLOCK_HZ) 81 if (speed_hz > OCTEON_SPI_MAX_CLOCK_HZ)
87 speed_hz = OCTEON_SPI_MAX_CLOCK_HZ; 82 speed_hz = OCTEON_SPI_MAX_CLOCK_HZ;
@@ -166,19 +161,6 @@ static int octeon_spi_do_transfer(struct octeon_spi *p,
166 return xfer->len; 161 return xfer->len;
167} 162}
168 163
169static int octeon_spi_validate_bpw(struct spi_device *spi, u32 speed)
170{
171 switch (speed) {
172 case 8:
173 break;
174 default:
175 dev_err(&spi->dev, "Error: %d bits per word not supported\n",
176 speed);
177 return -EINVAL;
178 }
179 return 0;
180}
181
182static int octeon_spi_transfer_one_message(struct spi_master *master, 164static int octeon_spi_transfer_one_message(struct spi_master *master,
183 struct spi_message *msg) 165 struct spi_message *msg)
184{ 166{
@@ -197,15 +179,6 @@ static int octeon_spi_transfer_one_message(struct spi_master *master,
197 } 179 }
198 180
199 list_for_each_entry(xfer, &msg->transfers, transfer_list) { 181 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
200 if (xfer->bits_per_word) {
201 status = octeon_spi_validate_bpw(msg->spi,
202 xfer->bits_per_word);
203 if (status)
204 goto err;
205 }
206 }
207
208 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
209 bool last_xfer = &xfer->transfer_list == msg->transfers.prev; 182 bool last_xfer = &xfer->transfer_list == msg->transfers.prev;
210 int r = octeon_spi_do_transfer(p, msg, xfer, last_xfer); 183 int r = octeon_spi_do_transfer(p, msg, xfer, last_xfer);
211 if (r < 0) { 184 if (r < 0) {
@@ -236,14 +209,9 @@ static struct octeon_spi_setup *octeon_spi_new_setup(struct spi_device *spi)
236 209
237static int octeon_spi_setup(struct spi_device *spi) 210static int octeon_spi_setup(struct spi_device *spi)
238{ 211{
239 int r;
240 struct octeon_spi_setup *new_setup; 212 struct octeon_spi_setup *new_setup;
241 struct octeon_spi_setup *old_setup = spi_get_ctldata(spi); 213 struct octeon_spi_setup *old_setup = spi_get_ctldata(spi);
242 214
243 r = octeon_spi_validate_bpw(spi, spi->bits_per_word);
244 if (r)
245 return r;
246
247 new_setup = octeon_spi_new_setup(spi); 215 new_setup = octeon_spi_new_setup(spi);
248 if (!new_setup) 216 if (!new_setup)
249 return -ENOMEM; 217 return -ENOMEM;
@@ -261,14 +229,8 @@ static void octeon_spi_cleanup(struct spi_device *spi)
261 kfree(old_setup); 229 kfree(old_setup);
262} 230}
263 231
264static int octeon_spi_nop_transfer_hardware(struct spi_master *master)
265{
266 return 0;
267}
268
269static int octeon_spi_probe(struct platform_device *pdev) 232static int octeon_spi_probe(struct platform_device *pdev)
270{ 233{
271
272 struct resource *res_mem; 234 struct resource *res_mem;
273 struct spi_master *master; 235 struct spi_master *master;
274 struct octeon_spi *p; 236 struct octeon_spi *p;
@@ -278,8 +240,7 @@ static int octeon_spi_probe(struct platform_device *pdev)
278 if (!master) 240 if (!master)
279 return -ENOMEM; 241 return -ENOMEM;
280 p = spi_master_get_devdata(master); 242 p = spi_master_get_devdata(master);
281 platform_set_drvdata(pdev, p); 243 platform_set_drvdata(pdev, master);
282 p->my_master = master;
283 244
284 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 245 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
285 246
@@ -307,9 +268,8 @@ static int octeon_spi_probe(struct platform_device *pdev)
307 268
308 master->setup = octeon_spi_setup; 269 master->setup = octeon_spi_setup;
309 master->cleanup = octeon_spi_cleanup; 270 master->cleanup = octeon_spi_cleanup;
310 master->prepare_transfer_hardware = octeon_spi_nop_transfer_hardware;
311 master->transfer_one_message = octeon_spi_transfer_one_message; 271 master->transfer_one_message = octeon_spi_transfer_one_message;
312 master->unprepare_transfer_hardware = octeon_spi_nop_transfer_hardware; 272 master->bits_per_word_mask = SPI_BPW_MASK(8);
313 273
314 master->dev.of_node = pdev->dev.of_node; 274 master->dev.of_node = pdev->dev.of_node;
315 err = spi_register_master(master); 275 err = spi_register_master(master);
@@ -328,10 +288,11 @@ fail:
328 288
329static int octeon_spi_remove(struct platform_device *pdev) 289static int octeon_spi_remove(struct platform_device *pdev)
330{ 290{
331 struct octeon_spi *p = platform_get_drvdata(pdev); 291 struct spi_master *master = platform_get_drvdata(pdev);
292 struct octeon_spi *p = spi_master_get_devdata(master);
332 u64 register_base = p->register_base; 293 u64 register_base = p->register_base;
333 294
334 spi_unregister_master(p->my_master); 295 spi_unregister_master(master);
335 296
336 /* Clear the CSENA* and put everything in a known state. */ 297 /* Clear the CSENA* and put everything in a known state. */
337 cvmx_write_csr(register_base + OCTEON_SPI_CFG, 0); 298 cvmx_write_csr(register_base + OCTEON_SPI_CFG, 0);
diff --git a/drivers/spi/spi-omap-100k.c b/drivers/spi/spi-omap-100k.c
index ee25670f8cfd..cdcc72c5d380 100644
--- a/drivers/spi/spi-omap-100k.c
+++ b/drivers/spi/spi-omap-100k.c
@@ -83,11 +83,6 @@
83#define SPI_SHUTDOWN 1 83#define SPI_SHUTDOWN 1
84 84
85struct omap1_spi100k { 85struct omap1_spi100k {
86 struct work_struct work;
87
88 /* lock protects queue and registers */
89 spinlock_t lock;
90 struct list_head msg_queue;
91 struct spi_master *master; 86 struct spi_master *master;
92 struct clk *ick; 87 struct clk *ick;
93 struct clk *fck; 88 struct clk *fck;
@@ -104,8 +99,6 @@ struct omap1_spi100k_cs {
104 int word_len; 99 int word_len;
105}; 100};
106 101
107static struct workqueue_struct *omap1_spi100k_wq;
108
109#define MOD_REG_BIT(val, mask, set) do { \ 102#define MOD_REG_BIT(val, mask, set) do { \
110 if (set) \ 103 if (set) \
111 val |= mask; \ 104 val |= mask; \
@@ -310,170 +303,102 @@ static int omap1_spi100k_setup(struct spi_device *spi)
310 303
311 spi100k_open(spi->master); 304 spi100k_open(spi->master);
312 305
313 clk_enable(spi100k->ick); 306 clk_prepare_enable(spi100k->ick);
314 clk_enable(spi100k->fck); 307 clk_prepare_enable(spi100k->fck);
315 308
316 ret = omap1_spi100k_setup_transfer(spi, NULL); 309 ret = omap1_spi100k_setup_transfer(spi, NULL);
317 310
318 clk_disable(spi100k->ick); 311 clk_disable_unprepare(spi100k->ick);
319 clk_disable(spi100k->fck); 312 clk_disable_unprepare(spi100k->fck);
320 313
321 return ret; 314 return ret;
322} 315}
323 316
324static void omap1_spi100k_work(struct work_struct *work) 317static int omap1_spi100k_prepare_hardware(struct spi_master *master)
325{ 318{
326 struct omap1_spi100k *spi100k; 319 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
327 int status = 0;
328 320
329 spi100k = container_of(work, struct omap1_spi100k, work); 321 clk_prepare_enable(spi100k->ick);
330 spin_lock_irq(&spi100k->lock); 322 clk_prepare_enable(spi100k->fck);
331 323
332 clk_enable(spi100k->ick); 324 return 0;
333 clk_enable(spi100k->fck); 325}
334 326
335 /* We only enable one channel at a time -- the one whose message is 327static int omap1_spi100k_transfer_one_message(struct spi_master *master,
336 * at the head of the queue -- although this controller would gladly 328 struct spi_message *m)
337 * arbitrate among multiple channels. This corresponds to "single 329{
338 * channel" master mode. As a side effect, we need to manage the 330 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
339 * chipselect with the FORCE bit ... CS != channel enable. 331 struct spi_device *spi = m->spi;
340 */ 332 struct spi_transfer *t = NULL;
341 while (!list_empty(&spi100k->msg_queue)) { 333 int cs_active = 0;
342 struct spi_message *m; 334 int par_override = 0;
343 struct spi_device *spi; 335 int status = 0;
344 struct spi_transfer *t = NULL; 336
345 int cs_active = 0; 337 list_for_each_entry(t, &m->transfers, transfer_list) {
346 struct omap1_spi100k_cs *cs; 338 if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
347 int par_override = 0; 339 status = -EINVAL;
348 340 break;
349 m = container_of(spi100k->msg_queue.next, struct spi_message, 341 }
350 queue); 342 if (par_override || t->speed_hz || t->bits_per_word) {
351 343 par_override = 1;
352 list_del_init(&m->queue); 344 status = omap1_spi100k_setup_transfer(spi, t);
353 spin_unlock_irq(&spi100k->lock); 345 if (status < 0)
354
355 spi = m->spi;
356 cs = spi->controller_state;
357
358 list_for_each_entry(t, &m->transfers, transfer_list) {
359 if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
360 status = -EINVAL;
361 break; 346 break;
362 } 347 if (!t->speed_hz && !t->bits_per_word)
363 if (par_override || t->speed_hz || t->bits_per_word) { 348 par_override = 0;
364 par_override = 1; 349 }
365 status = omap1_spi100k_setup_transfer(spi, t);
366 if (status < 0)
367 break;
368 if (!t->speed_hz && !t->bits_per_word)
369 par_override = 0;
370 }
371 350
372 if (!cs_active) { 351 if (!cs_active) {
373 omap1_spi100k_force_cs(spi100k, 1); 352 omap1_spi100k_force_cs(spi100k, 1);
374 cs_active = 1; 353 cs_active = 1;
375 } 354 }
376 355
377 if (t->len) { 356 if (t->len) {
378 unsigned count; 357 unsigned count;
379 358
380 count = omap1_spi100k_txrx_pio(spi, t); 359 count = omap1_spi100k_txrx_pio(spi, t);
381 m->actual_length += count; 360 m->actual_length += count;
382 361
383 if (count != t->len) { 362 if (count != t->len) {
384 status = -EIO; 363 status = -EIO;
385 break; 364 break;
386 }
387 } 365 }
366 }
388 367
389 if (t->delay_usecs) 368 if (t->delay_usecs)
390 udelay(t->delay_usecs); 369 udelay(t->delay_usecs);
391 370
392 /* ignore the "leave it on after last xfer" hint */ 371 /* ignore the "leave it on after last xfer" hint */
393 372
394 if (t->cs_change) { 373 if (t->cs_change) {
395 omap1_spi100k_force_cs(spi100k, 0); 374 omap1_spi100k_force_cs(spi100k, 0);
396 cs_active = 0; 375 cs_active = 0;
397 }
398 }
399
400 /* Restore defaults if they were overriden */
401 if (par_override) {
402 par_override = 0;
403 status = omap1_spi100k_setup_transfer(spi, NULL);
404 } 376 }
377 }
405 378
406 if (cs_active) 379 /* Restore defaults if they were overriden */
407 omap1_spi100k_force_cs(spi100k, 0); 380 if (par_override) {
381 par_override = 0;
382 status = omap1_spi100k_setup_transfer(spi, NULL);
383 }
408 384
409 m->status = status; 385 if (cs_active)
410 m->complete(m->context); 386 omap1_spi100k_force_cs(spi100k, 0);
411 387
412 spin_lock_irq(&spi100k->lock); 388 m->status = status;
413 }
414 389
415 clk_disable(spi100k->ick); 390 spi_finalize_current_message(master);
416 clk_disable(spi100k->fck);
417 spin_unlock_irq(&spi100k->lock);
418 391
419 if (status < 0) 392 return status;
420 printk(KERN_WARNING "spi transfer failed with %d\n", status);
421} 393}
422 394
423static int omap1_spi100k_transfer(struct spi_device *spi, struct spi_message *m) 395static int omap1_spi100k_unprepare_hardware(struct spi_master *master)
424{ 396{
425 struct omap1_spi100k *spi100k; 397 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
426 unsigned long flags;
427 struct spi_transfer *t;
428
429 m->actual_length = 0;
430 m->status = -EINPROGRESS;
431
432 spi100k = spi_master_get_devdata(spi->master);
433
434 /* Don't accept new work if we're shutting down */
435 if (spi100k->state == SPI_SHUTDOWN)
436 return -ESHUTDOWN;
437
438 /* reject invalid messages and transfers */
439 if (list_empty(&m->transfers) || !m->complete)
440 return -EINVAL;
441
442 list_for_each_entry(t, &m->transfers, transfer_list) {
443 const void *tx_buf = t->tx_buf;
444 void *rx_buf = t->rx_buf;
445 unsigned len = t->len;
446
447 if (t->speed_hz > OMAP1_SPI100K_MAX_FREQ
448 || (len && !(rx_buf || tx_buf))) {
449 dev_dbg(&spi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
450 t->speed_hz,
451 len,
452 tx_buf ? "tx" : "",
453 rx_buf ? "rx" : "",
454 t->bits_per_word);
455 return -EINVAL;
456 }
457
458 if (t->speed_hz && t->speed_hz < OMAP1_SPI100K_MAX_FREQ/(1<<16)) {
459 dev_dbg(&spi->dev, "%d Hz max exceeds %d\n",
460 t->speed_hz,
461 OMAP1_SPI100K_MAX_FREQ/(1<<16));
462 return -EINVAL;
463 }
464
465 }
466
467 spin_lock_irqsave(&spi100k->lock, flags);
468 list_add_tail(&m->queue, &spi100k->msg_queue);
469 queue_work(omap1_spi100k_wq, &spi100k->work);
470 spin_unlock_irqrestore(&spi100k->lock, flags);
471 398
472 return 0; 399 clk_disable_unprepare(spi100k->ick);
473} 400 clk_disable_unprepare(spi100k->fck);
474 401
475static int omap1_spi100k_reset(struct omap1_spi100k *spi100k)
476{
477 return 0; 402 return 0;
478} 403}
479 404
@@ -496,11 +421,15 @@ static int omap1_spi100k_probe(struct platform_device *pdev)
496 master->bus_num = pdev->id; 421 master->bus_num = pdev->id;
497 422
498 master->setup = omap1_spi100k_setup; 423 master->setup = omap1_spi100k_setup;
499 master->transfer = omap1_spi100k_transfer; 424 master->transfer_one_message = omap1_spi100k_transfer_one_message;
425 master->prepare_transfer_hardware = omap1_spi100k_prepare_hardware;
426 master->unprepare_transfer_hardware = omap1_spi100k_unprepare_hardware;
500 master->cleanup = NULL; 427 master->cleanup = NULL;
501 master->num_chipselect = 2; 428 master->num_chipselect = 2;
502 master->mode_bits = MODEBITS; 429 master->mode_bits = MODEBITS;
503 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); 430 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
431 master->min_speed_hz = OMAP1_SPI100K_MAX_FREQ/(1<<16);
432 master->max_speed_hz = OMAP1_SPI100K_MAX_FREQ;
504 433
505 platform_set_drvdata(pdev, master); 434 platform_set_drvdata(pdev, master);
506 435
@@ -514,40 +443,29 @@ static int omap1_spi100k_probe(struct platform_device *pdev)
514 */ 443 */
515 spi100k->base = (void __iomem *) pdev->dev.platform_data; 444 spi100k->base = (void __iomem *) pdev->dev.platform_data;
516 445
517 INIT_WORK(&spi100k->work, omap1_spi100k_work); 446 spi100k->ick = devm_clk_get(&pdev->dev, "ick");
518
519 spin_lock_init(&spi100k->lock);
520 INIT_LIST_HEAD(&spi100k->msg_queue);
521 spi100k->ick = clk_get(&pdev->dev, "ick");
522 if (IS_ERR(spi100k->ick)) { 447 if (IS_ERR(spi100k->ick)) {
523 dev_dbg(&pdev->dev, "can't get spi100k_ick\n"); 448 dev_dbg(&pdev->dev, "can't get spi100k_ick\n");
524 status = PTR_ERR(spi100k->ick); 449 status = PTR_ERR(spi100k->ick);
525 goto err1; 450 goto err;
526 } 451 }
527 452
528 spi100k->fck = clk_get(&pdev->dev, "fck"); 453 spi100k->fck = devm_clk_get(&pdev->dev, "fck");
529 if (IS_ERR(spi100k->fck)) { 454 if (IS_ERR(spi100k->fck)) {
530 dev_dbg(&pdev->dev, "can't get spi100k_fck\n"); 455 dev_dbg(&pdev->dev, "can't get spi100k_fck\n");
531 status = PTR_ERR(spi100k->fck); 456 status = PTR_ERR(spi100k->fck);
532 goto err2; 457 goto err;
533 } 458 }
534 459
535 if (omap1_spi100k_reset(spi100k) < 0)
536 goto err3;
537
538 status = spi_register_master(master); 460 status = spi_register_master(master);
539 if (status < 0) 461 if (status < 0)
540 goto err3; 462 goto err;
541 463
542 spi100k->state = SPI_RUNNING; 464 spi100k->state = SPI_RUNNING;
543 465
544 return status; 466 return status;
545 467
546err3: 468err:
547 clk_put(spi100k->fck);
548err2:
549 clk_put(spi100k->ick);
550err1:
551 spi_master_put(master); 469 spi_master_put(master);
552 return status; 470 return status;
553} 471}
@@ -557,33 +475,14 @@ static int omap1_spi100k_remove(struct platform_device *pdev)
557 struct spi_master *master; 475 struct spi_master *master;
558 struct omap1_spi100k *spi100k; 476 struct omap1_spi100k *spi100k;
559 struct resource *r; 477 struct resource *r;
560 unsigned limit = 500;
561 unsigned long flags;
562 int status = 0; 478 int status = 0;
563 479
564 master = platform_get_drvdata(pdev); 480 master = platform_get_drvdata(pdev);
565 spi100k = spi_master_get_devdata(master); 481 spi100k = spi_master_get_devdata(master);
566 482
567 spin_lock_irqsave(&spi100k->lock, flags);
568
569 spi100k->state = SPI_SHUTDOWN;
570 while (!list_empty(&spi100k->msg_queue) && limit--) {
571 spin_unlock_irqrestore(&spi100k->lock, flags);
572 msleep(10);
573 spin_lock_irqsave(&spi100k->lock, flags);
574 }
575
576 if (!list_empty(&spi100k->msg_queue))
577 status = -EBUSY;
578
579 spin_unlock_irqrestore(&spi100k->lock, flags);
580
581 if (status != 0) 483 if (status != 0)
582 return status; 484 return status;
583 485
584 clk_put(spi100k->fck);
585 clk_put(spi100k->ick);
586
587 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 486 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
588 487
589 spi_unregister_master(master); 488 spi_unregister_master(master);
@@ -596,30 +495,11 @@ static struct platform_driver omap1_spi100k_driver = {
596 .name = "omap1_spi100k", 495 .name = "omap1_spi100k",
597 .owner = THIS_MODULE, 496 .owner = THIS_MODULE,
598 }, 497 },
498 .probe = omap1_spi100k_probe,
599 .remove = omap1_spi100k_remove, 499 .remove = omap1_spi100k_remove,
600}; 500};
601 501
602 502module_platform_driver(omap1_spi100k_driver);
603static int __init omap1_spi100k_init(void)
604{
605 omap1_spi100k_wq = create_singlethread_workqueue(
606 omap1_spi100k_driver.driver.name);
607
608 if (omap1_spi100k_wq == NULL)
609 return -1;
610
611 return platform_driver_probe(&omap1_spi100k_driver, omap1_spi100k_probe);
612}
613
614static void __exit omap1_spi100k_exit(void)
615{
616 platform_driver_unregister(&omap1_spi100k_driver);
617
618 destroy_workqueue(omap1_spi100k_wq);
619}
620
621module_init(omap1_spi100k_init);
622module_exit(omap1_spi100k_exit);
623 503
624MODULE_DESCRIPTION("OMAP7xx SPI 100k controller driver"); 504MODULE_DESCRIPTION("OMAP7xx SPI 100k controller driver");
625MODULE_AUTHOR("Fabrice Crohas <fcrohas@gmail.com>"); 505MODULE_AUTHOR("Fabrice Crohas <fcrohas@gmail.com>");
diff --git a/drivers/spi/spi-orion.c b/drivers/spi/spi-orion.c
index 551bea774fd8..1d1d321d90c4 100644
--- a/drivers/spi/spi-orion.c
+++ b/drivers/spi/spi-orion.c
@@ -19,6 +19,7 @@
19#include <linux/module.h> 19#include <linux/module.h>
20#include <linux/of.h> 20#include <linux/of.h>
21#include <linux/clk.h> 21#include <linux/clk.h>
22#include <linux/sizes.h>
22#include <asm/unaligned.h> 23#include <asm/unaligned.h>
23 24
24#define DRIVER_NAME "orion_spi" 25#define DRIVER_NAME "orion_spi"
diff --git a/drivers/spi/spi-xilinx.c b/drivers/spi/spi-xilinx.c
index 09a942852593..fb56fcfdf65e 100644
--- a/drivers/spi/spi-xilinx.c
+++ b/drivers/spi/spi-xilinx.c
@@ -233,21 +233,6 @@ static int xilinx_spi_setup_transfer(struct spi_device *spi,
233 return 0; 233 return 0;
234} 234}
235 235
236static int xilinx_spi_setup(struct spi_device *spi)
237{
238 /* always return 0, we can not check the number of bits.
239 * There are cases when SPI setup is called before any driver is
240 * there, in that case the SPI core defaults to 8 bits, which we
241 * do not support in some cases. But if we return an error, the
242 * SPI device would not be registered and no driver can get hold of it
243 * When the driver is there, it will call SPI setup again with the
244 * correct number of bits per transfer.
245 * If a driver setups with the wrong bit number, it will fail when
246 * it tries to do a transfer
247 */
248 return 0;
249}
250
251static void xilinx_spi_fill_tx_fifo(struct xilinx_spi *xspi) 236static void xilinx_spi_fill_tx_fifo(struct xilinx_spi *xspi)
252{ 237{
253 u8 sr; 238 u8 sr;
@@ -375,7 +360,6 @@ struct spi_master *xilinx_spi_init(struct device *dev, struct resource *mem,
375 xspi->bitbang.chipselect = xilinx_spi_chipselect; 360 xspi->bitbang.chipselect = xilinx_spi_chipselect;
376 xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer; 361 xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer;
377 xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs; 362 xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs;
378 xspi->bitbang.master->setup = xilinx_spi_setup;
379 init_completion(&xspi->done); 363 init_completion(&xspi->done);
380 364
381 if (!request_mem_region(mem->start, resource_size(mem), 365 if (!request_mem_region(mem->start, resource_size(mem),
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index 978dda2c5239..7ed5c147c073 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -774,7 +774,7 @@ static int spi_queued_transfer(struct spi_device *spi, struct spi_message *msg)
774 msg->status = -EINPROGRESS; 774 msg->status = -EINPROGRESS;
775 775
776 list_add_tail(&msg->queue, &master->queue); 776 list_add_tail(&msg->queue, &master->queue);
777 if (master->running && !master->busy) 777 if (!master->busy)
778 queue_kthread_work(&master->kworker, &master->pump_messages); 778 queue_kthread_work(&master->kworker, &master->pump_messages);
779 779
780 spin_unlock_irqrestore(&master->queue_lock, flags); 780 spin_unlock_irqrestore(&master->queue_lock, flags);
@@ -1169,7 +1169,7 @@ int spi_register_master(struct spi_master *master)
1169 else { 1169 else {
1170 status = spi_master_initialize_queue(master); 1170 status = spi_master_initialize_queue(master);
1171 if (status) { 1171 if (status) {
1172 device_unregister(&master->dev); 1172 device_del(&master->dev);
1173 goto done; 1173 goto done;
1174 } 1174 }
1175 } 1175 }
@@ -1351,6 +1351,11 @@ static int __spi_async(struct spi_device *spi, struct spi_message *message)
1351 struct spi_master *master = spi->master; 1351 struct spi_master *master = spi->master;
1352 struct spi_transfer *xfer; 1352 struct spi_transfer *xfer;
1353 1353
1354 if (list_empty(&message->transfers))
1355 return -EINVAL;
1356 if (!message->complete)
1357 return -EINVAL;
1358
1354 /* Half-duplex links include original MicroWire, and ones with 1359 /* Half-duplex links include original MicroWire, and ones with
1355 * only one data pin like SPI_3WIRE (switches direction) or where 1360 * only one data pin like SPI_3WIRE (switches direction) or where
1356 * either MOSI or MISO is missing. They can also be caused by 1361 * either MOSI or MISO is missing. They can also be caused by
@@ -1375,10 +1380,16 @@ static int __spi_async(struct spi_device *spi, struct spi_message *message)
1375 * it is not set for this transfer. 1380 * it is not set for this transfer.
1376 */ 1381 */
1377 list_for_each_entry(xfer, &message->transfers, transfer_list) { 1382 list_for_each_entry(xfer, &message->transfers, transfer_list) {
1383 message->frame_length += xfer->len;
1378 if (!xfer->bits_per_word) 1384 if (!xfer->bits_per_word)
1379 xfer->bits_per_word = spi->bits_per_word; 1385 xfer->bits_per_word = spi->bits_per_word;
1380 if (!xfer->speed_hz) 1386 if (!xfer->speed_hz) {
1381 xfer->speed_hz = spi->max_speed_hz; 1387 xfer->speed_hz = spi->max_speed_hz;
1388 if (master->max_speed_hz &&
1389 xfer->speed_hz > master->max_speed_hz)
1390 xfer->speed_hz = master->max_speed_hz;
1391 }
1392
1382 if (master->bits_per_word_mask) { 1393 if (master->bits_per_word_mask) {
1383 /* Only 32 bits fit in the mask */ 1394 /* Only 32 bits fit in the mask */
1384 if (xfer->bits_per_word > 32) 1395 if (xfer->bits_per_word > 32)
@@ -1387,6 +1398,13 @@ static int __spi_async(struct spi_device *spi, struct spi_message *message)
1387 BIT(xfer->bits_per_word - 1))) 1398 BIT(xfer->bits_per_word - 1)))
1388 return -EINVAL; 1399 return -EINVAL;
1389 } 1400 }
1401
1402 if (xfer->speed_hz && master->min_speed_hz &&
1403 xfer->speed_hz < master->min_speed_hz)
1404 return -EINVAL;
1405 if (xfer->speed_hz && master->max_speed_hz &&
1406 xfer->speed_hz > master->max_speed_hz)
1407 return -EINVAL;
1390 } 1408 }
1391 1409
1392 message->spi = spi; 1410 message->spi = spi;
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-09 23:06:14 -0500