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-rw-r--r--drivers/spi/Kconfig17
-rw-r--r--drivers/spi/Makefile2
-rw-r--r--drivers/spi/spi-atmel.c115
-rw-r--r--drivers/spi/spi-cadence.c33
-rw-r--r--drivers/spi/spi-dw-mid.c114
-rw-r--r--drivers/spi/spi-dw.c6
-rw-r--r--drivers/spi/spi-dw.h2
-rw-r--r--drivers/spi/spi-fsl-cpm.c5
-rw-r--r--drivers/spi/spi-fsl-dspi.c7
-rw-r--r--drivers/spi/spi-fsl-espi.c59
-rw-r--r--drivers/spi/spi-fsl-lib.c59
-rw-r--r--drivers/spi/spi-fsl-lib.h10
-rw-r--r--drivers/spi/spi-fsl-spi.c17
-rw-r--r--drivers/spi/spi-gpio.c37
-rw-r--r--drivers/spi/spi-img-spfi.c746
-rw-r--r--drivers/spi/spi-meson-spifc.c462
-rw-r--r--drivers/spi/spi-mxs.c12
-rw-r--r--drivers/spi/spi-pxa2xx-pci.c8
-rw-r--r--drivers/spi/spi-pxa2xx.c311
-rw-r--r--drivers/spi/spi-pxa2xx.h16
-rw-r--r--drivers/spi/spi-rockchip.c2
-rw-r--r--drivers/spi/spi-s3c64xx.c41
-rw-r--r--drivers/spi/spi-sirf.c16
-rw-r--r--drivers/spi/spi-txx9.c3
-rw-r--r--drivers/spi/spi.c8
25 files changed, 1821 insertions, 287 deletions
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 84e7c9e6ccef..99829985c1a1 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -225,6 +225,13 @@ config SPI_GPIO
225 GPIO operations, you should be able to leverage that for better 225 GPIO operations, you should be able to leverage that for better
226 speed with a custom version of this driver; see the source code. 226 speed with a custom version of this driver; see the source code.
227 227
228config SPI_IMG_SPFI
229 tristate "IMG SPFI controller"
230 depends on MIPS || COMPILE_TEST
231 help
232 This enables support for the SPFI master controller found on
233 IMG SoCs.
234
228config SPI_IMX 235config SPI_IMX
229 tristate "Freescale i.MX SPI controllers" 236 tristate "Freescale i.MX SPI controllers"
230 depends on ARCH_MXC || COMPILE_TEST 237 depends on ARCH_MXC || COMPILE_TEST
@@ -301,6 +308,14 @@ config SPI_FSL_ESPI
301 From MPC8536, 85xx platform uses the controller, and all P10xx, 308 From MPC8536, 85xx platform uses the controller, and all P10xx,
302 P20xx, P30xx,P40xx, P50xx uses this controller. 309 P20xx, P30xx,P40xx, P50xx uses this controller.
303 310
311config SPI_MESON_SPIFC
312 tristate "Amlogic Meson SPIFC controller"
313 depends on ARCH_MESON || COMPILE_TEST
314 select REGMAP_MMIO
315 help
316 This enables master mode support for the SPIFC (SPI flash
317 controller) available in Amlogic Meson SoCs.
318
304config SPI_OC_TINY 319config SPI_OC_TINY
305 tristate "OpenCores tiny SPI" 320 tristate "OpenCores tiny SPI"
306 depends on GPIOLIB 321 depends on GPIOLIB
@@ -444,7 +459,7 @@ config SPI_S3C24XX_FIQ
444 459
445config SPI_S3C64XX 460config SPI_S3C64XX
446 tristate "Samsung S3C64XX series type SPI" 461 tristate "Samsung S3C64XX series type SPI"
447 depends on PLAT_SAMSUNG 462 depends on (PLAT_SAMSUNG || ARCH_EXYNOS)
448 select S3C64XX_PL080 if ARCH_S3C64XX 463 select S3C64XX_PL080 if ARCH_S3C64XX
449 help 464 help
450 SPI driver for Samsung S3C64XX and newer SoCs. 465 SPI driver for Samsung S3C64XX and newer SoCs.
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 78f24ca36fcf..6b9d2ac629cc 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -40,8 +40,10 @@ obj-$(CONFIG_SPI_FSL_LIB) += spi-fsl-lib.o
40obj-$(CONFIG_SPI_FSL_ESPI) += spi-fsl-espi.o 40obj-$(CONFIG_SPI_FSL_ESPI) += spi-fsl-espi.o
41obj-$(CONFIG_SPI_FSL_SPI) += spi-fsl-spi.o 41obj-$(CONFIG_SPI_FSL_SPI) += spi-fsl-spi.o
42obj-$(CONFIG_SPI_GPIO) += spi-gpio.o 42obj-$(CONFIG_SPI_GPIO) += spi-gpio.o
43obj-$(CONFIG_SPI_IMG_SPFI) += spi-img-spfi.o
43obj-$(CONFIG_SPI_IMX) += spi-imx.o 44obj-$(CONFIG_SPI_IMX) += spi-imx.o
44obj-$(CONFIG_SPI_LM70_LLP) += spi-lm70llp.o 45obj-$(CONFIG_SPI_LM70_LLP) += spi-lm70llp.o
46obj-$(CONFIG_SPI_MESON_SPIFC) += spi-meson-spifc.o
45obj-$(CONFIG_SPI_MPC512x_PSC) += spi-mpc512x-psc.o 47obj-$(CONFIG_SPI_MPC512x_PSC) += spi-mpc512x-psc.o
46obj-$(CONFIG_SPI_MPC52xx_PSC) += spi-mpc52xx-psc.o 48obj-$(CONFIG_SPI_MPC52xx_PSC) += spi-mpc52xx-psc.o
47obj-$(CONFIG_SPI_MPC52xx) += spi-mpc52xx.o 49obj-$(CONFIG_SPI_MPC52xx) += spi-mpc52xx.o
diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
index 113c83f44b5c..e4193ccc4970 100644
--- a/drivers/spi/spi-atmel.c
+++ b/drivers/spi/spi-atmel.c
@@ -26,6 +26,7 @@
26#include <linux/io.h> 26#include <linux/io.h>
27#include <linux/gpio.h> 27#include <linux/gpio.h>
28#include <linux/pinctrl/consumer.h> 28#include <linux/pinctrl/consumer.h>
29#include <linux/pm_runtime.h>
29 30
30/* SPI register offsets */ 31/* SPI register offsets */
31#define SPI_CR 0x0000 32#define SPI_CR 0x0000
@@ -191,6 +192,8 @@
191 192
192#define SPI_DMA_TIMEOUT (msecs_to_jiffies(1000)) 193#define SPI_DMA_TIMEOUT (msecs_to_jiffies(1000))
193 194
195#define AUTOSUSPEND_TIMEOUT 2000
196
194struct atmel_spi_dma { 197struct atmel_spi_dma {
195 struct dma_chan *chan_rx; 198 struct dma_chan *chan_rx;
196 struct dma_chan *chan_tx; 199 struct dma_chan *chan_tx;
@@ -414,23 +417,6 @@ static int atmel_spi_dma_slave_config(struct atmel_spi *as,
414 return err; 417 return err;
415} 418}
416 419
417static bool filter(struct dma_chan *chan, void *pdata)
418{
419 struct atmel_spi_dma *sl_pdata = pdata;
420 struct at_dma_slave *sl;
421
422 if (!sl_pdata)
423 return false;
424
425 sl = &sl_pdata->dma_slave;
426 if (sl->dma_dev == chan->device->dev) {
427 chan->private = sl;
428 return true;
429 } else {
430 return false;
431 }
432}
433
434static int atmel_spi_configure_dma(struct atmel_spi *as) 420static int atmel_spi_configure_dma(struct atmel_spi *as)
435{ 421{
436 struct dma_slave_config slave_config; 422 struct dma_slave_config slave_config;
@@ -441,19 +427,24 @@ static int atmel_spi_configure_dma(struct atmel_spi *as)
441 dma_cap_zero(mask); 427 dma_cap_zero(mask);
442 dma_cap_set(DMA_SLAVE, mask); 428 dma_cap_set(DMA_SLAVE, mask);
443 429
444 as->dma.chan_tx = dma_request_slave_channel_compat(mask, filter, 430 as->dma.chan_tx = dma_request_slave_channel_reason(dev, "tx");
445 &as->dma, 431 if (IS_ERR(as->dma.chan_tx)) {
446 dev, "tx"); 432 err = PTR_ERR(as->dma.chan_tx);
447 if (!as->dma.chan_tx) { 433 if (err == -EPROBE_DEFER) {
434 dev_warn(dev, "no DMA channel available at the moment\n");
435 return err;
436 }
448 dev_err(dev, 437 dev_err(dev,
449 "DMA TX channel not available, SPI unable to use DMA\n"); 438 "DMA TX channel not available, SPI unable to use DMA\n");
450 err = -EBUSY; 439 err = -EBUSY;
451 goto error; 440 goto error;
452 } 441 }
453 442
454 as->dma.chan_rx = dma_request_slave_channel_compat(mask, filter, 443 /*
455 &as->dma, 444 * No reason to check EPROBE_DEFER here since we have already requested
456 dev, "rx"); 445 * tx channel. If it fails here, it's for another reason.
446 */
447 as->dma.chan_rx = dma_request_slave_channel(dev, "rx");
457 448
458 if (!as->dma.chan_rx) { 449 if (!as->dma.chan_rx) {
459 dev_err(dev, 450 dev_err(dev,
@@ -474,7 +465,7 @@ static int atmel_spi_configure_dma(struct atmel_spi *as)
474error: 465error:
475 if (as->dma.chan_rx) 466 if (as->dma.chan_rx)
476 dma_release_channel(as->dma.chan_rx); 467 dma_release_channel(as->dma.chan_rx);
477 if (as->dma.chan_tx) 468 if (!IS_ERR(as->dma.chan_tx))
478 dma_release_channel(as->dma.chan_tx); 469 dma_release_channel(as->dma.chan_tx);
479 return err; 470 return err;
480} 471}
@@ -482,11 +473,9 @@ error:
482static void atmel_spi_stop_dma(struct atmel_spi *as) 473static void atmel_spi_stop_dma(struct atmel_spi *as)
483{ 474{
484 if (as->dma.chan_rx) 475 if (as->dma.chan_rx)
485 as->dma.chan_rx->device->device_control(as->dma.chan_rx, 476 dmaengine_terminate_all(as->dma.chan_rx);
486 DMA_TERMINATE_ALL, 0);
487 if (as->dma.chan_tx) 477 if (as->dma.chan_tx)
488 as->dma.chan_tx->device->device_control(as->dma.chan_tx, 478 dmaengine_terminate_all(as->dma.chan_tx);
489 DMA_TERMINATE_ALL, 0);
490} 479}
491 480
492static void atmel_spi_release_dma(struct atmel_spi *as) 481static void atmel_spi_release_dma(struct atmel_spi *as)
@@ -1315,6 +1304,7 @@ static int atmel_spi_probe(struct platform_device *pdev)
1315 master->setup = atmel_spi_setup; 1304 master->setup = atmel_spi_setup;
1316 master->transfer_one_message = atmel_spi_transfer_one_message; 1305 master->transfer_one_message = atmel_spi_transfer_one_message;
1317 master->cleanup = atmel_spi_cleanup; 1306 master->cleanup = atmel_spi_cleanup;
1307 master->auto_runtime_pm = true;
1318 platform_set_drvdata(pdev, master); 1308 platform_set_drvdata(pdev, master);
1319 1309
1320 as = spi_master_get_devdata(master); 1310 as = spi_master_get_devdata(master);
@@ -1347,8 +1337,11 @@ static int atmel_spi_probe(struct platform_device *pdev)
1347 as->use_dma = false; 1337 as->use_dma = false;
1348 as->use_pdc = false; 1338 as->use_pdc = false;
1349 if (as->caps.has_dma_support) { 1339 if (as->caps.has_dma_support) {
1350 if (atmel_spi_configure_dma(as) == 0) 1340 ret = atmel_spi_configure_dma(as);
1341 if (ret == 0)
1351 as->use_dma = true; 1342 as->use_dma = true;
1343 else if (ret == -EPROBE_DEFER)
1344 return ret;
1352 } else { 1345 } else {
1353 as->use_pdc = true; 1346 as->use_pdc = true;
1354 } 1347 }
@@ -1387,6 +1380,11 @@ static int atmel_spi_probe(struct platform_device *pdev)
1387 dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n", 1380 dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n",
1388 (unsigned long)regs->start, irq); 1381 (unsigned long)regs->start, irq);
1389 1382
1383 pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
1384 pm_runtime_use_autosuspend(&pdev->dev);
1385 pm_runtime_set_active(&pdev->dev);
1386 pm_runtime_enable(&pdev->dev);
1387
1390 ret = devm_spi_register_master(&pdev->dev, master); 1388 ret = devm_spi_register_master(&pdev->dev, master);
1391 if (ret) 1389 if (ret)
1392 goto out_free_dma; 1390 goto out_free_dma;
@@ -1394,6 +1392,9 @@ static int atmel_spi_probe(struct platform_device *pdev)
1394 return 0; 1392 return 0;
1395 1393
1396out_free_dma: 1394out_free_dma:
1395 pm_runtime_disable(&pdev->dev);
1396 pm_runtime_set_suspended(&pdev->dev);
1397
1397 if (as->use_dma) 1398 if (as->use_dma)
1398 atmel_spi_release_dma(as); 1399 atmel_spi_release_dma(as);
1399 1400
@@ -1415,6 +1416,8 @@ static int atmel_spi_remove(struct platform_device *pdev)
1415 struct spi_master *master = platform_get_drvdata(pdev); 1416 struct spi_master *master = platform_get_drvdata(pdev);
1416 struct atmel_spi *as = spi_master_get_devdata(master); 1417 struct atmel_spi *as = spi_master_get_devdata(master);
1417 1418
1419 pm_runtime_get_sync(&pdev->dev);
1420
1418 /* reset the hardware and block queue progress */ 1421 /* reset the hardware and block queue progress */
1419 spin_lock_irq(&as->lock); 1422 spin_lock_irq(&as->lock);
1420 if (as->use_dma) { 1423 if (as->use_dma) {
@@ -1432,14 +1435,37 @@ static int atmel_spi_remove(struct platform_device *pdev)
1432 1435
1433 clk_disable_unprepare(as->clk); 1436 clk_disable_unprepare(as->clk);
1434 1437
1438 pm_runtime_put_noidle(&pdev->dev);
1439 pm_runtime_disable(&pdev->dev);
1440
1435 return 0; 1441 return 0;
1436} 1442}
1437 1443
1438#ifdef CONFIG_PM_SLEEP 1444#ifdef CONFIG_PM
1445static int atmel_spi_runtime_suspend(struct device *dev)
1446{
1447 struct spi_master *master = dev_get_drvdata(dev);
1448 struct atmel_spi *as = spi_master_get_devdata(master);
1449
1450 clk_disable_unprepare(as->clk);
1451 pinctrl_pm_select_sleep_state(dev);
1452
1453 return 0;
1454}
1455
1456static int atmel_spi_runtime_resume(struct device *dev)
1457{
1458 struct spi_master *master = dev_get_drvdata(dev);
1459 struct atmel_spi *as = spi_master_get_devdata(master);
1460
1461 pinctrl_pm_select_default_state(dev);
1462
1463 return clk_prepare_enable(as->clk);
1464}
1465
1439static int atmel_spi_suspend(struct device *dev) 1466static int atmel_spi_suspend(struct device *dev)
1440{ 1467{
1441 struct spi_master *master = dev_get_drvdata(dev); 1468 struct spi_master *master = dev_get_drvdata(dev);
1442 struct atmel_spi *as = spi_master_get_devdata(master);
1443 int ret; 1469 int ret;
1444 1470
1445 /* Stop the queue running */ 1471 /* Stop the queue running */
@@ -1449,22 +1475,22 @@ static int atmel_spi_suspend(struct device *dev)
1449 return ret; 1475 return ret;
1450 } 1476 }
1451 1477
1452 clk_disable_unprepare(as->clk); 1478 if (!pm_runtime_suspended(dev))
1453 1479 atmel_spi_runtime_suspend(dev);
1454 pinctrl_pm_select_sleep_state(dev);
1455 1480
1456 return 0; 1481 return 0;
1457} 1482}
1458 1483
1459static int atmel_spi_resume(struct device *dev) 1484static int atmel_spi_resume(struct device *dev)
1460{ 1485{
1461 struct spi_master *master = dev_get_drvdata(dev); 1486 struct spi_master *master = dev_get_drvdata(dev);
1462 struct atmel_spi *as = spi_master_get_devdata(master);
1463 int ret; 1487 int ret;
1464 1488
1465 pinctrl_pm_select_default_state(dev); 1489 if (!pm_runtime_suspended(dev)) {
1466 1490 ret = atmel_spi_runtime_resume(dev);
1467 clk_prepare_enable(as->clk); 1491 if (ret)
1492 return ret;
1493 }
1468 1494
1469 /* Start the queue running */ 1495 /* Start the queue running */
1470 ret = spi_master_resume(master); 1496 ret = spi_master_resume(master);
@@ -1474,8 +1500,11 @@ static int atmel_spi_resume(struct device *dev)
1474 return ret; 1500 return ret;
1475} 1501}
1476 1502
1477static SIMPLE_DEV_PM_OPS(atmel_spi_pm_ops, atmel_spi_suspend, atmel_spi_resume); 1503static const struct dev_pm_ops atmel_spi_pm_ops = {
1478 1504 SET_SYSTEM_SLEEP_PM_OPS(atmel_spi_suspend, atmel_spi_resume)
1505 SET_RUNTIME_PM_OPS(atmel_spi_runtime_suspend,
1506 atmel_spi_runtime_resume, NULL)
1507};
1479#define ATMEL_SPI_PM_OPS (&atmel_spi_pm_ops) 1508#define ATMEL_SPI_PM_OPS (&atmel_spi_pm_ops)
1480#else 1509#else
1481#define ATMEL_SPI_PM_OPS NULL 1510#define ATMEL_SPI_PM_OPS NULL
diff --git a/drivers/spi/spi-cadence.c b/drivers/spi/spi-cadence.c
index 7b811e38c7ad..5a6749881ff9 100644
--- a/drivers/spi/spi-cadence.c
+++ b/drivers/spi/spi-cadence.c
@@ -47,6 +47,7 @@
47#define CDNS_SPI_CR_CPHA_MASK 0x00000004 /* Clock Phase Control */ 47#define CDNS_SPI_CR_CPHA_MASK 0x00000004 /* Clock Phase Control */
48#define CDNS_SPI_CR_CPOL_MASK 0x00000002 /* Clock Polarity Control */ 48#define CDNS_SPI_CR_CPOL_MASK 0x00000002 /* Clock Polarity Control */
49#define CDNS_SPI_CR_SSCTRL_MASK 0x00003C00 /* Slave Select Mask */ 49#define CDNS_SPI_CR_SSCTRL_MASK 0x00003C00 /* Slave Select Mask */
50#define CDNS_SPI_CR_PERI_SEL_MASK 0x00000200 /* Peripheral Select Decode */
50#define CDNS_SPI_CR_BAUD_DIV_MASK 0x00000038 /* Baud Rate Divisor Mask */ 51#define CDNS_SPI_CR_BAUD_DIV_MASK 0x00000038 /* Baud Rate Divisor Mask */
51#define CDNS_SPI_CR_MSTREN_MASK 0x00000001 /* Master Enable Mask */ 52#define CDNS_SPI_CR_MSTREN_MASK 0x00000001 /* Master Enable Mask */
52#define CDNS_SPI_CR_MANSTRTEN_MASK 0x00008000 /* Manual TX Enable Mask */ 53#define CDNS_SPI_CR_MANSTRTEN_MASK 0x00008000 /* Manual TX Enable Mask */
@@ -148,6 +149,11 @@ static inline void cdns_spi_write(struct cdns_spi *xspi, u32 offset, u32 val)
148 */ 149 */
149static void cdns_spi_init_hw(struct cdns_spi *xspi) 150static void cdns_spi_init_hw(struct cdns_spi *xspi)
150{ 151{
152 u32 ctrl_reg = CDNS_SPI_CR_DEFAULT_MASK;
153
154 if (xspi->is_decoded_cs)
155 ctrl_reg |= CDNS_SPI_CR_PERI_SEL_MASK;
156
151 cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET, 157 cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET,
152 CDNS_SPI_ER_DISABLE_MASK); 158 CDNS_SPI_ER_DISABLE_MASK);
153 cdns_spi_write(xspi, CDNS_SPI_IDR_OFFSET, 159 cdns_spi_write(xspi, CDNS_SPI_IDR_OFFSET,
@@ -160,8 +166,7 @@ static void cdns_spi_init_hw(struct cdns_spi *xspi)
160 166
161 cdns_spi_write(xspi, CDNS_SPI_ISR_OFFSET, 167 cdns_spi_write(xspi, CDNS_SPI_ISR_OFFSET,
162 CDNS_SPI_IXR_ALL_MASK); 168 CDNS_SPI_IXR_ALL_MASK);
163 cdns_spi_write(xspi, CDNS_SPI_CR_OFFSET, 169 cdns_spi_write(xspi, CDNS_SPI_CR_OFFSET, ctrl_reg);
164 CDNS_SPI_CR_DEFAULT_MASK);
165 cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET, 170 cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET,
166 CDNS_SPI_ER_ENABLE_MASK); 171 CDNS_SPI_ER_ENABLE_MASK);
167} 172}
@@ -516,6 +521,17 @@ static int cdns_spi_probe(struct platform_device *pdev)
516 goto clk_dis_apb; 521 goto clk_dis_apb;
517 } 522 }
518 523
524 ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
525 if (ret < 0)
526 master->num_chipselect = CDNS_SPI_DEFAULT_NUM_CS;
527 else
528 master->num_chipselect = num_cs;
529
530 ret = of_property_read_u32(pdev->dev.of_node, "is-decoded-cs",
531 &xspi->is_decoded_cs);
532 if (ret < 0)
533 xspi->is_decoded_cs = 0;
534
519 /* SPI controller initializations */ 535 /* SPI controller initializations */
520 cdns_spi_init_hw(xspi); 536 cdns_spi_init_hw(xspi);
521 537
@@ -534,19 +550,6 @@ static int cdns_spi_probe(struct platform_device *pdev)
534 goto remove_master; 550 goto remove_master;
535 } 551 }
536 552
537 ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
538
539 if (ret < 0)
540 master->num_chipselect = CDNS_SPI_DEFAULT_NUM_CS;
541 else
542 master->num_chipselect = num_cs;
543
544 ret = of_property_read_u32(pdev->dev.of_node, "is-decoded-cs",
545 &xspi->is_decoded_cs);
546
547 if (ret < 0)
548 xspi->is_decoded_cs = 0;
549
550 master->prepare_transfer_hardware = cdns_prepare_transfer_hardware; 553 master->prepare_transfer_hardware = cdns_prepare_transfer_hardware;
551 master->prepare_message = cdns_prepare_message; 554 master->prepare_message = cdns_prepare_message;
552 master->transfer_one = cdns_transfer_one; 555 master->transfer_one = cdns_transfer_one;
diff --git a/drivers/spi/spi-dw-mid.c b/drivers/spi/spi-dw-mid.c
index 46c6d58e1fda..7281316a5ecb 100644
--- a/drivers/spi/spi-dw-mid.c
+++ b/drivers/spi/spi-dw-mid.c
@@ -26,6 +26,9 @@
26#include <linux/intel_mid_dma.h> 26#include <linux/intel_mid_dma.h>
27#include <linux/pci.h> 27#include <linux/pci.h>
28 28
29#define RX_BUSY 0
30#define TX_BUSY 1
31
29struct mid_dma { 32struct mid_dma {
30 struct intel_mid_dma_slave dmas_tx; 33 struct intel_mid_dma_slave dmas_tx;
31 struct intel_mid_dma_slave dmas_rx; 34 struct intel_mid_dma_slave dmas_rx;
@@ -98,41 +101,26 @@ static void mid_spi_dma_exit(struct dw_spi *dws)
98} 101}
99 102
100/* 103/*
101 * dws->dma_chan_done is cleared before the dma transfer starts, 104 * dws->dma_chan_busy is set before the dma transfer starts, callback for tx
102 * callback for rx/tx channel will each increment it by 1. 105 * channel will clear a corresponding bit.
103 * Reaching 2 means the whole spi transaction is done.
104 */ 106 */
105static void dw_spi_dma_done(void *arg) 107static void dw_spi_dma_tx_done(void *arg)
106{ 108{
107 struct dw_spi *dws = arg; 109 struct dw_spi *dws = arg;
108 110
109 if (++dws->dma_chan_done != 2) 111 if (test_and_clear_bit(TX_BUSY, &dws->dma_chan_busy) & BIT(RX_BUSY))
110 return; 112 return;
111 dw_spi_xfer_done(dws); 113 dw_spi_xfer_done(dws);
112} 114}
113 115
114static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change) 116static struct dma_async_tx_descriptor *dw_spi_dma_prepare_tx(struct dw_spi *dws)
115{ 117{
116 struct dma_async_tx_descriptor *txdesc, *rxdesc; 118 struct dma_slave_config txconf;
117 struct dma_slave_config txconf, rxconf; 119 struct dma_async_tx_descriptor *txdesc;
118 u16 dma_ctrl = 0;
119
120 /* 1. setup DMA related registers */
121 if (cs_change) {
122 spi_enable_chip(dws, 0);
123 dw_writew(dws, DW_SPI_DMARDLR, 0xf);
124 dw_writew(dws, DW_SPI_DMATDLR, 0x10);
125 if (dws->tx_dma)
126 dma_ctrl |= SPI_DMA_TDMAE;
127 if (dws->rx_dma)
128 dma_ctrl |= SPI_DMA_RDMAE;
129 dw_writew(dws, DW_SPI_DMACR, dma_ctrl);
130 spi_enable_chip(dws, 1);
131 }
132 120
133 dws->dma_chan_done = 0; 121 if (!dws->tx_dma)
122 return NULL;
134 123
135 /* 2. Prepare the TX dma transfer */
136 txconf.direction = DMA_MEM_TO_DEV; 124 txconf.direction = DMA_MEM_TO_DEV;
137 txconf.dst_addr = dws->dma_addr; 125 txconf.dst_addr = dws->dma_addr;
138 txconf.dst_maxburst = LNW_DMA_MSIZE_16; 126 txconf.dst_maxburst = LNW_DMA_MSIZE_16;
@@ -151,10 +139,33 @@ static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change)
151 1, 139 1,
152 DMA_MEM_TO_DEV, 140 DMA_MEM_TO_DEV,
153 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 141 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
154 txdesc->callback = dw_spi_dma_done; 142 txdesc->callback = dw_spi_dma_tx_done;
155 txdesc->callback_param = dws; 143 txdesc->callback_param = dws;
156 144
157 /* 3. Prepare the RX dma transfer */ 145 return txdesc;
146}
147
148/*
149 * dws->dma_chan_busy is set before the dma transfer starts, callback for rx
150 * channel will clear a corresponding bit.
151 */
152static void dw_spi_dma_rx_done(void *arg)
153{
154 struct dw_spi *dws = arg;
155
156 if (test_and_clear_bit(RX_BUSY, &dws->dma_chan_busy) & BIT(TX_BUSY))
157 return;
158 dw_spi_xfer_done(dws);
159}
160
161static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws)
162{
163 struct dma_slave_config rxconf;
164 struct dma_async_tx_descriptor *rxdesc;
165
166 if (!dws->rx_dma)
167 return NULL;
168
158 rxconf.direction = DMA_DEV_TO_MEM; 169 rxconf.direction = DMA_DEV_TO_MEM;
159 rxconf.src_addr = dws->dma_addr; 170 rxconf.src_addr = dws->dma_addr;
160 rxconf.src_maxburst = LNW_DMA_MSIZE_16; 171 rxconf.src_maxburst = LNW_DMA_MSIZE_16;
@@ -173,15 +184,56 @@ static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change)
173 1, 184 1,
174 DMA_DEV_TO_MEM, 185 DMA_DEV_TO_MEM,
175 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 186 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
176 rxdesc->callback = dw_spi_dma_done; 187 rxdesc->callback = dw_spi_dma_rx_done;
177 rxdesc->callback_param = dws; 188 rxdesc->callback_param = dws;
178 189
190 return rxdesc;
191}
192
193static void dw_spi_dma_setup(struct dw_spi *dws)
194{
195 u16 dma_ctrl = 0;
196
197 spi_enable_chip(dws, 0);
198
199 dw_writew(dws, DW_SPI_DMARDLR, 0xf);
200 dw_writew(dws, DW_SPI_DMATDLR, 0x10);
201
202 if (dws->tx_dma)
203 dma_ctrl |= SPI_DMA_TDMAE;
204 if (dws->rx_dma)
205 dma_ctrl |= SPI_DMA_RDMAE;
206 dw_writew(dws, DW_SPI_DMACR, dma_ctrl);
207
208 spi_enable_chip(dws, 1);
209}
210
211static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change)
212{
213 struct dma_async_tx_descriptor *txdesc, *rxdesc;
214
215 /* 1. setup DMA related registers */
216 if (cs_change)
217 dw_spi_dma_setup(dws);
218
219 /* 2. Prepare the TX dma transfer */
220 txdesc = dw_spi_dma_prepare_tx(dws);
221
222 /* 3. Prepare the RX dma transfer */
223 rxdesc = dw_spi_dma_prepare_rx(dws);
224
179 /* rx must be started before tx due to spi instinct */ 225 /* rx must be started before tx due to spi instinct */
180 dmaengine_submit(rxdesc); 226 if (rxdesc) {
181 dma_async_issue_pending(dws->rxchan); 227 set_bit(RX_BUSY, &dws->dma_chan_busy);
228 dmaengine_submit(rxdesc);
229 dma_async_issue_pending(dws->rxchan);
230 }
182 231
183 dmaengine_submit(txdesc); 232 if (txdesc) {
184 dma_async_issue_pending(dws->txchan); 233 set_bit(TX_BUSY, &dws->dma_chan_busy);
234 dmaengine_submit(txdesc);
235 dma_async_issue_pending(dws->txchan);
236 }
185 237
186 return 0; 238 return 0;
187} 239}
diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c
index 72e12bad14b9..d0d5542efc06 100644
--- a/drivers/spi/spi-dw.c
+++ b/drivers/spi/spi-dw.c
@@ -376,9 +376,6 @@ static void pump_transfers(unsigned long data)
376 chip = dws->cur_chip; 376 chip = dws->cur_chip;
377 spi = message->spi; 377 spi = message->spi;
378 378
379 if (unlikely(!chip->clk_div))
380 chip->clk_div = dws->max_freq / chip->speed_hz;
381
382 if (message->state == ERROR_STATE) { 379 if (message->state == ERROR_STATE) {
383 message->status = -EIO; 380 message->status = -EIO;
384 goto early_exit; 381 goto early_exit;
@@ -419,7 +416,7 @@ static void pump_transfers(unsigned long data)
419 if (transfer->speed_hz) { 416 if (transfer->speed_hz) {
420 speed = chip->speed_hz; 417 speed = chip->speed_hz;
421 418
422 if (transfer->speed_hz != speed) { 419 if ((transfer->speed_hz != speed) || (!chip->clk_div)) {
423 speed = transfer->speed_hz; 420 speed = transfer->speed_hz;
424 421
425 /* clk_div doesn't support odd number */ 422 /* clk_div doesn't support odd number */
@@ -581,7 +578,6 @@ static int dw_spi_setup(struct spi_device *spi)
581 dev_err(&spi->dev, "No max speed HZ parameter\n"); 578 dev_err(&spi->dev, "No max speed HZ parameter\n");
582 return -EINVAL; 579 return -EINVAL;
583 } 580 }
584 chip->speed_hz = spi->max_speed_hz;
585 581
586 chip->tmode = 0; /* Tx & Rx */ 582 chip->tmode = 0; /* Tx & Rx */
587 /* Default SPI mode is SCPOL = 0, SCPH = 0 */ 583 /* Default SPI mode is SCPOL = 0, SCPH = 0 */
diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
index 83a103a76481..3d32be68c142 100644
--- a/drivers/spi/spi-dw.h
+++ b/drivers/spi/spi-dw.h
@@ -139,7 +139,7 @@ struct dw_spi {
139 struct scatterlist tx_sgl; 139 struct scatterlist tx_sgl;
140 struct dma_chan *rxchan; 140 struct dma_chan *rxchan;
141 struct scatterlist rx_sgl; 141 struct scatterlist rx_sgl;
142 int dma_chan_done; 142 unsigned long dma_chan_busy;
143 struct device *dma_dev; 143 struct device *dma_dev;
144 dma_addr_t dma_addr; /* phy address of the Data register */ 144 dma_addr_t dma_addr; /* phy address of the Data register */
145 struct dw_spi_dma_ops *dma_ops; 145 struct dw_spi_dma_ops *dma_ops;
diff --git a/drivers/spi/spi-fsl-cpm.c b/drivers/spi/spi-fsl-cpm.c
index c5dd20beee22..e85ab1cb17a2 100644
--- a/drivers/spi/spi-fsl-cpm.c
+++ b/drivers/spi/spi-fsl-cpm.c
@@ -56,12 +56,15 @@ void fsl_spi_cpm_reinit_txrx(struct mpc8xxx_spi *mspi)
56 qe_issue_cmd(QE_INIT_TX_RX, mspi->subblock, 56 qe_issue_cmd(QE_INIT_TX_RX, mspi->subblock,
57 QE_CR_PROTOCOL_UNSPECIFIED, 0); 57 QE_CR_PROTOCOL_UNSPECIFIED, 0);
58 } else { 58 } else {
59 cpm_command(CPM_SPI_CMD, CPM_CR_INIT_TRX);
60 if (mspi->flags & SPI_CPM1) { 59 if (mspi->flags & SPI_CPM1) {
60 out_be32(&mspi->pram->rstate, 0);
61 out_be16(&mspi->pram->rbptr, 61 out_be16(&mspi->pram->rbptr,
62 in_be16(&mspi->pram->rbase)); 62 in_be16(&mspi->pram->rbase));
63 out_be32(&mspi->pram->tstate, 0);
63 out_be16(&mspi->pram->tbptr, 64 out_be16(&mspi->pram->tbptr,
64 in_be16(&mspi->pram->tbase)); 65 in_be16(&mspi->pram->tbase));
66 } else {
67 cpm_command(CPM_SPI_CMD, CPM_CR_INIT_TRX);
65 } 68 }
66 } 69 }
67} 70}
diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c
index 448216025ce8..4cda994d3f40 100644
--- a/drivers/spi/spi-fsl-dspi.c
+++ b/drivers/spi/spi-fsl-dspi.c
@@ -46,7 +46,7 @@
46 46
47#define SPI_TCR 0x08 47#define SPI_TCR 0x08
48 48
49#define SPI_CTAR(x) (0x0c + (x * 4)) 49#define SPI_CTAR(x) (0x0c + (((x) & 0x3) * 4))
50#define SPI_CTAR_FMSZ(x) (((x) & 0x0000000f) << 27) 50#define SPI_CTAR_FMSZ(x) (((x) & 0x0000000f) << 27)
51#define SPI_CTAR_CPOL(x) ((x) << 26) 51#define SPI_CTAR_CPOL(x) ((x) << 26)
52#define SPI_CTAR_CPHA(x) ((x) << 25) 52#define SPI_CTAR_CPHA(x) ((x) << 25)
@@ -70,7 +70,7 @@
70 70
71#define SPI_PUSHR 0x34 71#define SPI_PUSHR 0x34
72#define SPI_PUSHR_CONT (1 << 31) 72#define SPI_PUSHR_CONT (1 << 31)
73#define SPI_PUSHR_CTAS(x) (((x) & 0x00000007) << 28) 73#define SPI_PUSHR_CTAS(x) (((x) & 0x00000003) << 28)
74#define SPI_PUSHR_EOQ (1 << 27) 74#define SPI_PUSHR_EOQ (1 << 27)
75#define SPI_PUSHR_CTCNT (1 << 26) 75#define SPI_PUSHR_CTCNT (1 << 26)
76#define SPI_PUSHR_PCS(x) (((1 << x) & 0x0000003f) << 16) 76#define SPI_PUSHR_PCS(x) (((1 << x) & 0x0000003f) << 16)
@@ -438,7 +438,7 @@ static int dspi_resume(struct device *dev)
438 438
439static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume); 439static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume);
440 440
441static struct regmap_config dspi_regmap_config = { 441static const struct regmap_config dspi_regmap_config = {
442 .reg_bits = 32, 442 .reg_bits = 32,
443 .val_bits = 32, 443 .val_bits = 32,
444 .reg_stride = 4, 444 .reg_stride = 4,
@@ -492,7 +492,6 @@ static int dspi_probe(struct platform_device *pdev)
492 goto out_master_put; 492 goto out_master_put;
493 } 493 }
494 494
495 dspi_regmap_config.lock_arg = dspi;
496 dspi->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "dspi", base, 495 dspi->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "dspi", base,
497 &dspi_regmap_config); 496 &dspi_regmap_config);
498 if (IS_ERR(dspi->regmap)) { 497 if (IS_ERR(dspi->regmap)) {
diff --git a/drivers/spi/spi-fsl-espi.c b/drivers/spi/spi-fsl-espi.c
index a7f94b6a9e70..56cadf13519e 100644
--- a/drivers/spi/spi-fsl-espi.c
+++ b/drivers/spi/spi-fsl-espi.c
@@ -411,7 +411,8 @@ static void fsl_espi_rw_trans(struct spi_message *m,
411 kfree(local_buf); 411 kfree(local_buf);
412} 412}
413 413
414static void fsl_espi_do_one_msg(struct spi_message *m) 414static int fsl_espi_do_one_msg(struct spi_master *master,
415 struct spi_message *m)
415{ 416{
416 struct spi_transfer *t; 417 struct spi_transfer *t;
417 u8 *rx_buf = NULL; 418 u8 *rx_buf = NULL;
@@ -441,8 +442,8 @@ static void fsl_espi_do_one_msg(struct spi_message *m)
441 442
442 m->actual_length = espi_trans.actual_length; 443 m->actual_length = espi_trans.actual_length;
443 m->status = espi_trans.status; 444 m->status = espi_trans.status;
444 if (m->complete) 445 spi_finalize_current_message(master);
445 m->complete(m->context); 446 return 0;
446} 447}
447 448
448static int fsl_espi_setup(struct spi_device *spi) 449static int fsl_espi_setup(struct spi_device *spi)
@@ -587,6 +588,38 @@ static void fsl_espi_remove(struct mpc8xxx_spi *mspi)
587 iounmap(mspi->reg_base); 588 iounmap(mspi->reg_base);
588} 589}
589 590
591static int fsl_espi_suspend(struct spi_master *master)
592{
593 struct mpc8xxx_spi *mpc8xxx_spi;
594 struct fsl_espi_reg *reg_base;
595 u32 regval;
596
597 mpc8xxx_spi = spi_master_get_devdata(master);
598 reg_base = mpc8xxx_spi->reg_base;
599
600 regval = mpc8xxx_spi_read_reg(&reg_base->mode);
601 regval &= ~SPMODE_ENABLE;
602 mpc8xxx_spi_write_reg(&reg_base->mode, regval);
603
604 return 0;
605}
606
607static int fsl_espi_resume(struct spi_master *master)
608{
609 struct mpc8xxx_spi *mpc8xxx_spi;
610 struct fsl_espi_reg *reg_base;
611 u32 regval;
612
613 mpc8xxx_spi = spi_master_get_devdata(master);
614 reg_base = mpc8xxx_spi->reg_base;
615
616 regval = mpc8xxx_spi_read_reg(&reg_base->mode);
617 regval |= SPMODE_ENABLE;
618 mpc8xxx_spi_write_reg(&reg_base->mode, regval);
619
620 return 0;
621}
622
590static struct spi_master * fsl_espi_probe(struct device *dev, 623static struct spi_master * fsl_espi_probe(struct device *dev,
591 struct resource *mem, unsigned int irq) 624 struct resource *mem, unsigned int irq)
592{ 625{
@@ -607,16 +640,16 @@ static struct spi_master * fsl_espi_probe(struct device *dev,
607 640
608 dev_set_drvdata(dev, master); 641 dev_set_drvdata(dev, master);
609 642
610 ret = mpc8xxx_spi_probe(dev, mem, irq); 643 mpc8xxx_spi_probe(dev, mem, irq);
611 if (ret)
612 goto err_probe;
613 644
614 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); 645 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
615 master->setup = fsl_espi_setup; 646 master->setup = fsl_espi_setup;
616 master->cleanup = fsl_espi_cleanup; 647 master->cleanup = fsl_espi_cleanup;
648 master->transfer_one_message = fsl_espi_do_one_msg;
649 master->prepare_transfer_hardware = fsl_espi_resume;
650 master->unprepare_transfer_hardware = fsl_espi_suspend;
617 651
618 mpc8xxx_spi = spi_master_get_devdata(master); 652 mpc8xxx_spi = spi_master_get_devdata(master);
619 mpc8xxx_spi->spi_do_one_msg = fsl_espi_do_one_msg;
620 mpc8xxx_spi->spi_remove = fsl_espi_remove; 653 mpc8xxx_spi->spi_remove = fsl_espi_remove;
621 654
622 mpc8xxx_spi->reg_base = ioremap(mem->start, resource_size(mem)); 655 mpc8xxx_spi->reg_base = ioremap(mem->start, resource_size(mem));
@@ -762,25 +795,15 @@ static int of_fsl_espi_remove(struct platform_device *dev)
762static int of_fsl_espi_suspend(struct device *dev) 795static int of_fsl_espi_suspend(struct device *dev)
763{ 796{
764 struct spi_master *master = dev_get_drvdata(dev); 797 struct spi_master *master = dev_get_drvdata(dev);
765 struct mpc8xxx_spi *mpc8xxx_spi;
766 struct fsl_espi_reg *reg_base;
767 u32 regval;
768 int ret; 798 int ret;
769 799
770 mpc8xxx_spi = spi_master_get_devdata(master);
771 reg_base = mpc8xxx_spi->reg_base;
772
773 ret = spi_master_suspend(master); 800 ret = spi_master_suspend(master);
774 if (ret) { 801 if (ret) {
775 dev_warn(dev, "cannot suspend master\n"); 802 dev_warn(dev, "cannot suspend master\n");
776 return ret; 803 return ret;
777 } 804 }
778 805
779 regval = mpc8xxx_spi_read_reg(&reg_base->mode); 806 return fsl_espi_suspend(master);
780 regval &= ~SPMODE_ENABLE;
781 mpc8xxx_spi_write_reg(&reg_base->mode, regval);
782
783 return 0;
784} 807}
785 808
786static int of_fsl_espi_resume(struct device *dev) 809static int of_fsl_espi_resume(struct device *dev)
diff --git a/drivers/spi/spi-fsl-lib.c b/drivers/spi/spi-fsl-lib.c
index 5ddb5b098e4e..446b737e1532 100644
--- a/drivers/spi/spi-fsl-lib.c
+++ b/drivers/spi/spi-fsl-lib.c
@@ -61,44 +61,6 @@ struct mpc8xxx_spi_probe_info *to_of_pinfo(struct fsl_spi_platform_data *pdata)
61 return container_of(pdata, struct mpc8xxx_spi_probe_info, pdata); 61 return container_of(pdata, struct mpc8xxx_spi_probe_info, pdata);
62} 62}
63 63
64static void mpc8xxx_spi_work(struct work_struct *work)
65{
66 struct mpc8xxx_spi *mpc8xxx_spi = container_of(work, struct mpc8xxx_spi,
67 work);
68
69 spin_lock_irq(&mpc8xxx_spi->lock);
70 while (!list_empty(&mpc8xxx_spi->queue)) {
71 struct spi_message *m = container_of(mpc8xxx_spi->queue.next,
72 struct spi_message, queue);
73
74 list_del_init(&m->queue);
75 spin_unlock_irq(&mpc8xxx_spi->lock);
76
77 if (mpc8xxx_spi->spi_do_one_msg)
78 mpc8xxx_spi->spi_do_one_msg(m);
79
80 spin_lock_irq(&mpc8xxx_spi->lock);
81 }
82 spin_unlock_irq(&mpc8xxx_spi->lock);
83}
84
85int mpc8xxx_spi_transfer(struct spi_device *spi,
86 struct spi_message *m)
87{
88 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
89 unsigned long flags;
90
91 m->actual_length = 0;
92 m->status = -EINPROGRESS;
93
94 spin_lock_irqsave(&mpc8xxx_spi->lock, flags);
95 list_add_tail(&m->queue, &mpc8xxx_spi->queue);
96 queue_work(mpc8xxx_spi->workqueue, &mpc8xxx_spi->work);
97 spin_unlock_irqrestore(&mpc8xxx_spi->lock, flags);
98
99 return 0;
100}
101
102const char *mpc8xxx_spi_strmode(unsigned int flags) 64const char *mpc8xxx_spi_strmode(unsigned int flags)
103{ 65{
104 if (flags & SPI_QE_CPU_MODE) { 66 if (flags & SPI_QE_CPU_MODE) {
@@ -114,13 +76,12 @@ const char *mpc8xxx_spi_strmode(unsigned int flags)
114 return "CPU"; 76 return "CPU";
115} 77}
116 78
117int mpc8xxx_spi_probe(struct device *dev, struct resource *mem, 79void mpc8xxx_spi_probe(struct device *dev, struct resource *mem,
118 unsigned int irq) 80 unsigned int irq)
119{ 81{
120 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); 82 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
121 struct spi_master *master; 83 struct spi_master *master;
122 struct mpc8xxx_spi *mpc8xxx_spi; 84 struct mpc8xxx_spi *mpc8xxx_spi;
123 int ret = 0;
124 85
125 master = dev_get_drvdata(dev); 86 master = dev_get_drvdata(dev);
126 87
@@ -128,7 +89,6 @@ int mpc8xxx_spi_probe(struct device *dev, struct resource *mem,
128 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH 89 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH
129 | SPI_LSB_FIRST | SPI_LOOP; 90 | SPI_LSB_FIRST | SPI_LOOP;
130 91
131 master->transfer = mpc8xxx_spi_transfer;
132 master->dev.of_node = dev->of_node; 92 master->dev.of_node = dev->of_node;
133 93
134 mpc8xxx_spi = spi_master_get_devdata(master); 94 mpc8xxx_spi = spi_master_get_devdata(master);
@@ -147,22 +107,7 @@ int mpc8xxx_spi_probe(struct device *dev, struct resource *mem,
147 master->bus_num = pdata->bus_num; 107 master->bus_num = pdata->bus_num;
148 master->num_chipselect = pdata->max_chipselect; 108 master->num_chipselect = pdata->max_chipselect;
149 109
150 spin_lock_init(&mpc8xxx_spi->lock);
151 init_completion(&mpc8xxx_spi->done); 110 init_completion(&mpc8xxx_spi->done);
152 INIT_WORK(&mpc8xxx_spi->work, mpc8xxx_spi_work);
153 INIT_LIST_HEAD(&mpc8xxx_spi->queue);
154
155 mpc8xxx_spi->workqueue = create_singlethread_workqueue(
156 dev_name(master->dev.parent));
157 if (mpc8xxx_spi->workqueue == NULL) {
158 ret = -EBUSY;
159 goto err;
160 }
161
162 return 0;
163
164err:
165 return ret;
166} 111}
167 112
168int mpc8xxx_spi_remove(struct device *dev) 113int mpc8xxx_spi_remove(struct device *dev)
@@ -173,8 +118,6 @@ int mpc8xxx_spi_remove(struct device *dev)
173 master = dev_get_drvdata(dev); 118 master = dev_get_drvdata(dev);
174 mpc8xxx_spi = spi_master_get_devdata(master); 119 mpc8xxx_spi = spi_master_get_devdata(master);
175 120
176 flush_workqueue(mpc8xxx_spi->workqueue);
177 destroy_workqueue(mpc8xxx_spi->workqueue);
178 spi_unregister_master(master); 121 spi_unregister_master(master);
179 122
180 free_irq(mpc8xxx_spi->irq, mpc8xxx_spi); 123 free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
diff --git a/drivers/spi/spi-fsl-lib.h b/drivers/spi/spi-fsl-lib.h
index 2fcbfd01d109..b4ed04e8862f 100644
--- a/drivers/spi/spi-fsl-lib.h
+++ b/drivers/spi/spi-fsl-lib.h
@@ -55,7 +55,6 @@ struct mpc8xxx_spi {
55 u32(*get_tx) (struct mpc8xxx_spi *); 55 u32(*get_tx) (struct mpc8xxx_spi *);
56 56
57 /* hooks for different controller driver */ 57 /* hooks for different controller driver */
58 void (*spi_do_one_msg) (struct spi_message *m);
59 void (*spi_remove) (struct mpc8xxx_spi *mspi); 58 void (*spi_remove) (struct mpc8xxx_spi *mspi);
60 59
61 unsigned int count; 60 unsigned int count;
@@ -78,12 +77,6 @@ struct mpc8xxx_spi {
78 int bits_per_word, int msb_first); 77 int bits_per_word, int msb_first);
79#endif 78#endif
80 79
81 struct workqueue_struct *workqueue;
82 struct work_struct work;
83
84 struct list_head queue;
85 spinlock_t lock;
86
87 struct completion done; 80 struct completion done;
88}; 81};
89 82
@@ -123,9 +116,8 @@ extern struct mpc8xxx_spi_probe_info *to_of_pinfo(
123 struct fsl_spi_platform_data *pdata); 116 struct fsl_spi_platform_data *pdata);
124extern int mpc8xxx_spi_bufs(struct mpc8xxx_spi *mspi, 117extern int mpc8xxx_spi_bufs(struct mpc8xxx_spi *mspi,
125 struct spi_transfer *t, unsigned int len); 118 struct spi_transfer *t, unsigned int len);
126extern int mpc8xxx_spi_transfer(struct spi_device *spi, struct spi_message *m);
127extern const char *mpc8xxx_spi_strmode(unsigned int flags); 119extern const char *mpc8xxx_spi_strmode(unsigned int flags);
128extern int mpc8xxx_spi_probe(struct device *dev, struct resource *mem, 120extern void mpc8xxx_spi_probe(struct device *dev, struct resource *mem,
129 unsigned int irq); 121 unsigned int irq);
130extern int mpc8xxx_spi_remove(struct device *dev); 122extern int mpc8xxx_spi_remove(struct device *dev);
131extern int of_mpc8xxx_spi_probe(struct platform_device *ofdev); 123extern int of_mpc8xxx_spi_probe(struct platform_device *ofdev);
diff --git a/drivers/spi/spi-fsl-spi.c b/drivers/spi/spi-fsl-spi.c
index ed792880c9d6..3b159364c459 100644
--- a/drivers/spi/spi-fsl-spi.c
+++ b/drivers/spi/spi-fsl-spi.c
@@ -353,7 +353,8 @@ static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t,
353 return mpc8xxx_spi->count; 353 return mpc8xxx_spi->count;
354} 354}
355 355
356static void fsl_spi_do_one_msg(struct spi_message *m) 356static int fsl_spi_do_one_msg(struct spi_master *master,
357 struct spi_message *m)
357{ 358{
358 struct spi_device *spi = m->spi; 359 struct spi_device *spi = m->spi;
359 struct spi_transfer *t, *first; 360 struct spi_transfer *t, *first;
@@ -367,10 +368,9 @@ static void fsl_spi_do_one_msg(struct spi_message *m)
367 list_for_each_entry(t, &m->transfers, transfer_list) { 368 list_for_each_entry(t, &m->transfers, transfer_list) {
368 if ((first->bits_per_word != t->bits_per_word) || 369 if ((first->bits_per_word != t->bits_per_word) ||
369 (first->speed_hz != t->speed_hz)) { 370 (first->speed_hz != t->speed_hz)) {
370 status = -EINVAL;
371 dev_err(&spi->dev, 371 dev_err(&spi->dev,
372 "bits_per_word/speed_hz should be same for the same SPI transfer\n"); 372 "bits_per_word/speed_hz should be same for the same SPI transfer\n");
373 return; 373 return -EINVAL;
374 } 374 }
375 } 375 }
376 376
@@ -408,8 +408,7 @@ static void fsl_spi_do_one_msg(struct spi_message *m)
408 } 408 }
409 409
410 m->status = status; 410 m->status = status;
411 if (m->complete) 411 spi_finalize_current_message(master);
412 m->complete(m->context);
413 412
414 if (status || !cs_change) { 413 if (status || !cs_change) {
415 ndelay(nsecs); 414 ndelay(nsecs);
@@ -417,6 +416,7 @@ static void fsl_spi_do_one_msg(struct spi_message *m)
417 } 416 }
418 417
419 fsl_spi_setup_transfer(spi, NULL); 418 fsl_spi_setup_transfer(spi, NULL);
419 return 0;
420} 420}
421 421
422static int fsl_spi_setup(struct spi_device *spi) 422static int fsl_spi_setup(struct spi_device *spi)
@@ -624,15 +624,13 @@ static struct spi_master * fsl_spi_probe(struct device *dev,
624 624
625 dev_set_drvdata(dev, master); 625 dev_set_drvdata(dev, master);
626 626
627 ret = mpc8xxx_spi_probe(dev, mem, irq); 627 mpc8xxx_spi_probe(dev, mem, irq);
628 if (ret)
629 goto err_probe;
630 628
631 master->setup = fsl_spi_setup; 629 master->setup = fsl_spi_setup;
632 master->cleanup = fsl_spi_cleanup; 630 master->cleanup = fsl_spi_cleanup;
631 master->transfer_one_message = fsl_spi_do_one_msg;
633 632
634 mpc8xxx_spi = spi_master_get_devdata(master); 633 mpc8xxx_spi = spi_master_get_devdata(master);
635 mpc8xxx_spi->spi_do_one_msg = fsl_spi_do_one_msg;
636 mpc8xxx_spi->spi_remove = fsl_spi_remove; 634 mpc8xxx_spi->spi_remove = fsl_spi_remove;
637 mpc8xxx_spi->max_bits_per_word = 32; 635 mpc8xxx_spi->max_bits_per_word = 32;
638 mpc8xxx_spi->type = fsl_spi_get_type(dev); 636 mpc8xxx_spi->type = fsl_spi_get_type(dev);
@@ -704,7 +702,6 @@ free_irq:
704err_ioremap: 702err_ioremap:
705 fsl_spi_cpm_free(mpc8xxx_spi); 703 fsl_spi_cpm_free(mpc8xxx_spi);
706err_cpm_init: 704err_cpm_init:
707err_probe:
708 spi_master_put(master); 705 spi_master_put(master);
709err: 706err:
710 return ERR_PTR(ret); 707 return ERR_PTR(ret);
diff --git a/drivers/spi/spi-gpio.c b/drivers/spi/spi-gpio.c
index 9f595535cf27..4b600d4f8548 100644
--- a/drivers/spi/spi-gpio.c
+++ b/drivers/spi/spi-gpio.c
@@ -48,7 +48,7 @@ struct spi_gpio {
48 struct spi_bitbang bitbang; 48 struct spi_bitbang bitbang;
49 struct spi_gpio_platform_data pdata; 49 struct spi_gpio_platform_data pdata;
50 struct platform_device *pdev; 50 struct platform_device *pdev;
51 int cs_gpios[0]; 51 unsigned long cs_gpios[0];
52}; 52};
53 53
54/*----------------------------------------------------------------------*/ 54/*----------------------------------------------------------------------*/
@@ -220,7 +220,7 @@ static u32 spi_gpio_spec_txrx_word_mode3(struct spi_device *spi,
220static void spi_gpio_chipselect(struct spi_device *spi, int is_active) 220static void spi_gpio_chipselect(struct spi_device *spi, int is_active)
221{ 221{
222 struct spi_gpio *spi_gpio = spi_to_spi_gpio(spi); 222 struct spi_gpio *spi_gpio = spi_to_spi_gpio(spi);
223 unsigned int cs = spi_gpio->cs_gpios[spi->chip_select]; 223 unsigned long cs = spi_gpio->cs_gpios[spi->chip_select];
224 224
225 /* set initial clock polarity */ 225 /* set initial clock polarity */
226 if (is_active) 226 if (is_active)
@@ -234,7 +234,7 @@ static void spi_gpio_chipselect(struct spi_device *spi, int is_active)
234 234
235static int spi_gpio_setup(struct spi_device *spi) 235static int spi_gpio_setup(struct spi_device *spi)
236{ 236{
237 unsigned int cs; 237 unsigned long cs;
238 int status = 0; 238 int status = 0;
239 struct spi_gpio *spi_gpio = spi_to_spi_gpio(spi); 239 struct spi_gpio *spi_gpio = spi_to_spi_gpio(spi);
240 struct device_node *np = spi->master->dev.of_node; 240 struct device_node *np = spi->master->dev.of_node;
@@ -249,7 +249,7 @@ static int spi_gpio_setup(struct spi_device *spi)
249 /* 249 /*
250 * ... otherwise, take it from spi->controller_data 250 * ... otherwise, take it from spi->controller_data
251 */ 251 */
252 cs = (unsigned int)(uintptr_t) spi->controller_data; 252 cs = (uintptr_t) spi->controller_data;
253 } 253 }
254 254
255 if (!spi->controller_state) { 255 if (!spi->controller_state) {
@@ -277,7 +277,7 @@ static int spi_gpio_setup(struct spi_device *spi)
277static void spi_gpio_cleanup(struct spi_device *spi) 277static void spi_gpio_cleanup(struct spi_device *spi)
278{ 278{
279 struct spi_gpio *spi_gpio = spi_to_spi_gpio(spi); 279 struct spi_gpio *spi_gpio = spi_to_spi_gpio(spi);
280 unsigned int cs = spi_gpio->cs_gpios[spi->chip_select]; 280 unsigned long cs = spi_gpio->cs_gpios[spi->chip_select];
281 281
282 if (cs != SPI_GPIO_NO_CHIPSELECT) 282 if (cs != SPI_GPIO_NO_CHIPSELECT)
283 gpio_free(cs); 283 gpio_free(cs);
@@ -413,6 +413,7 @@ static int spi_gpio_probe(struct platform_device *pdev)
413 struct spi_gpio_platform_data *pdata; 413 struct spi_gpio_platform_data *pdata;
414 u16 master_flags = 0; 414 u16 master_flags = 0;
415 bool use_of = 0; 415 bool use_of = 0;
416 int num_devices;
416 417
417 status = spi_gpio_probe_dt(pdev); 418 status = spi_gpio_probe_dt(pdev);
418 if (status < 0) 419 if (status < 0)
@@ -422,16 +423,21 @@ static int spi_gpio_probe(struct platform_device *pdev)
422 423
423 pdata = dev_get_platdata(&pdev->dev); 424 pdata = dev_get_platdata(&pdev->dev);
424#ifdef GENERIC_BITBANG 425#ifdef GENERIC_BITBANG
425 if (!pdata || !pdata->num_chipselect) 426 if (!pdata || (!use_of && !pdata->num_chipselect))
426 return -ENODEV; 427 return -ENODEV;
427#endif 428#endif
428 429
430 if (use_of && !SPI_N_CHIPSEL)
431 num_devices = 1;
432 else
433 num_devices = SPI_N_CHIPSEL;
434
429 status = spi_gpio_request(pdata, dev_name(&pdev->dev), &master_flags); 435 status = spi_gpio_request(pdata, dev_name(&pdev->dev), &master_flags);
430 if (status < 0) 436 if (status < 0)
431 return status; 437 return status;
432 438
433 master = spi_alloc_master(&pdev->dev, sizeof(*spi_gpio) + 439 master = spi_alloc_master(&pdev->dev, sizeof(*spi_gpio) +
434 (sizeof(int) * SPI_N_CHIPSEL)); 440 (sizeof(unsigned long) * num_devices));
435 if (!master) { 441 if (!master) {
436 status = -ENOMEM; 442 status = -ENOMEM;
437 goto gpio_free; 443 goto gpio_free;
@@ -446,7 +452,7 @@ static int spi_gpio_probe(struct platform_device *pdev)
446 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32); 452 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
447 master->flags = master_flags; 453 master->flags = master_flags;
448 master->bus_num = pdev->id; 454 master->bus_num = pdev->id;
449 master->num_chipselect = SPI_N_CHIPSEL; 455 master->num_chipselect = num_devices;
450 master->setup = spi_gpio_setup; 456 master->setup = spi_gpio_setup;
451 master->cleanup = spi_gpio_cleanup; 457 master->cleanup = spi_gpio_cleanup;
452#ifdef CONFIG_OF 458#ifdef CONFIG_OF
@@ -461,9 +467,18 @@ static int spi_gpio_probe(struct platform_device *pdev)
461 * property of the node. 467 * property of the node.
462 */ 468 */
463 469
464 for (i = 0; i < SPI_N_CHIPSEL; i++) 470 if (!SPI_N_CHIPSEL)
465 spi_gpio->cs_gpios[i] = 471 spi_gpio->cs_gpios[0] = SPI_GPIO_NO_CHIPSELECT;
466 of_get_named_gpio(np, "cs-gpios", i); 472 else
473 for (i = 0; i < SPI_N_CHIPSEL; i++) {
474 status = of_get_named_gpio(np, "cs-gpios", i);
475 if (status < 0) {
476 dev_err(&pdev->dev,
477 "invalid cs-gpios property\n");
478 goto gpio_free;
479 }
480 spi_gpio->cs_gpios[i] = status;
481 }
467 } 482 }
468#endif 483#endif
469 484
diff --git a/drivers/spi/spi-img-spfi.c b/drivers/spi/spi-img-spfi.c
new file mode 100644
index 000000000000..43781c9fe521
--- /dev/null
+++ b/drivers/spi/spi-img-spfi.c
@@ -0,0 +1,746 @@
1/*
2 * IMG SPFI controller driver
3 *
4 * Copyright (C) 2007,2008,2013 Imagination Technologies Ltd.
5 * Copyright (C) 2014 Google, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 */
11
12#include <linux/clk.h>
13#include <linux/delay.h>
14#include <linux/dmaengine.h>
15#include <linux/interrupt.h>
16#include <linux/io.h>
17#include <linux/irq.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/platform_device.h>
21#include <linux/pm_runtime.h>
22#include <linux/scatterlist.h>
23#include <linux/slab.h>
24#include <linux/spi/spi.h>
25#include <linux/spinlock.h>
26
27#define SPFI_DEVICE_PARAMETER(x) (0x00 + 0x4 * (x))
28#define SPFI_DEVICE_PARAMETER_BITCLK_SHIFT 24
29#define SPFI_DEVICE_PARAMETER_BITCLK_MASK 0xff
30#define SPFI_DEVICE_PARAMETER_CSSETUP_SHIFT 16
31#define SPFI_DEVICE_PARAMETER_CSSETUP_MASK 0xff
32#define SPFI_DEVICE_PARAMETER_CSHOLD_SHIFT 8
33#define SPFI_DEVICE_PARAMETER_CSHOLD_MASK 0xff
34#define SPFI_DEVICE_PARAMETER_CSDELAY_SHIFT 0
35#define SPFI_DEVICE_PARAMETER_CSDELAY_MASK 0xff
36
37#define SPFI_CONTROL 0x14
38#define SPFI_CONTROL_CONTINUE BIT(12)
39#define SPFI_CONTROL_SOFT_RESET BIT(11)
40#define SPFI_CONTROL_SEND_DMA BIT(10)
41#define SPFI_CONTROL_GET_DMA BIT(9)
42#define SPFI_CONTROL_TMODE_SHIFT 5
43#define SPFI_CONTROL_TMODE_MASK 0x7
44#define SPFI_CONTROL_TMODE_SINGLE 0
45#define SPFI_CONTROL_TMODE_DUAL 1
46#define SPFI_CONTROL_TMODE_QUAD 2
47#define SPFI_CONTROL_SPFI_EN BIT(0)
48
49#define SPFI_TRANSACTION 0x18
50#define SPFI_TRANSACTION_TSIZE_SHIFT 16
51#define SPFI_TRANSACTION_TSIZE_MASK 0xffff
52
53#define SPFI_PORT_STATE 0x1c
54#define SPFI_PORT_STATE_DEV_SEL_SHIFT 20
55#define SPFI_PORT_STATE_DEV_SEL_MASK 0x7
56#define SPFI_PORT_STATE_CK_POL(x) BIT(19 - (x))
57#define SPFI_PORT_STATE_CK_PHASE(x) BIT(14 - (x))
58
59#define SPFI_TX_32BIT_VALID_DATA 0x20
60#define SPFI_TX_8BIT_VALID_DATA 0x24
61#define SPFI_RX_32BIT_VALID_DATA 0x28
62#define SPFI_RX_8BIT_VALID_DATA 0x2c
63
64#define SPFI_INTERRUPT_STATUS 0x30
65#define SPFI_INTERRUPT_ENABLE 0x34
66#define SPFI_INTERRUPT_CLEAR 0x38
67#define SPFI_INTERRUPT_IACCESS BIT(12)
68#define SPFI_INTERRUPT_GDEX8BIT BIT(11)
69#define SPFI_INTERRUPT_ALLDONETRIG BIT(9)
70#define SPFI_INTERRUPT_GDFUL BIT(8)
71#define SPFI_INTERRUPT_GDHF BIT(7)
72#define SPFI_INTERRUPT_GDEX32BIT BIT(6)
73#define SPFI_INTERRUPT_GDTRIG BIT(5)
74#define SPFI_INTERRUPT_SDFUL BIT(3)
75#define SPFI_INTERRUPT_SDHF BIT(2)
76#define SPFI_INTERRUPT_SDE BIT(1)
77#define SPFI_INTERRUPT_SDTRIG BIT(0)
78
79/*
80 * There are four parallel FIFOs of 16 bytes each. The word buffer
81 * (*_32BIT_VALID_DATA) accesses all four FIFOs at once, resulting in an
82 * effective FIFO size of 64 bytes. The byte buffer (*_8BIT_VALID_DATA)
83 * accesses only a single FIFO, resulting in an effective FIFO size of
84 * 16 bytes.
85 */
86#define SPFI_32BIT_FIFO_SIZE 64
87#define SPFI_8BIT_FIFO_SIZE 16
88
89struct img_spfi {
90 struct device *dev;
91 struct spi_master *master;
92 spinlock_t lock;
93
94 void __iomem *regs;
95 phys_addr_t phys;
96 int irq;
97 struct clk *spfi_clk;
98 struct clk *sys_clk;
99
100 struct dma_chan *rx_ch;
101 struct dma_chan *tx_ch;
102 bool tx_dma_busy;
103 bool rx_dma_busy;
104};
105
106static inline u32 spfi_readl(struct img_spfi *spfi, u32 reg)
107{
108 return readl(spfi->regs + reg);
109}
110
111static inline void spfi_writel(struct img_spfi *spfi, u32 val, u32 reg)
112{
113 writel(val, spfi->regs + reg);
114}
115
116static inline void spfi_start(struct img_spfi *spfi)
117{
118 u32 val;
119
120 val = spfi_readl(spfi, SPFI_CONTROL);
121 val |= SPFI_CONTROL_SPFI_EN;
122 spfi_writel(spfi, val, SPFI_CONTROL);
123}
124
125static inline void spfi_stop(struct img_spfi *spfi)
126{
127 u32 val;
128
129 val = spfi_readl(spfi, SPFI_CONTROL);
130 val &= ~SPFI_CONTROL_SPFI_EN;
131 spfi_writel(spfi, val, SPFI_CONTROL);
132}
133
134static inline void spfi_reset(struct img_spfi *spfi)
135{
136 spfi_writel(spfi, SPFI_CONTROL_SOFT_RESET, SPFI_CONTROL);
137 udelay(1);
138 spfi_writel(spfi, 0, SPFI_CONTROL);
139}
140
141static void spfi_flush_tx_fifo(struct img_spfi *spfi)
142{
143 unsigned long timeout = jiffies + msecs_to_jiffies(10);
144
145 spfi_writel(spfi, SPFI_INTERRUPT_SDE, SPFI_INTERRUPT_CLEAR);
146 while (time_before(jiffies, timeout)) {
147 if (spfi_readl(spfi, SPFI_INTERRUPT_STATUS) &
148 SPFI_INTERRUPT_SDE)
149 return;
150 cpu_relax();
151 }
152
153 dev_err(spfi->dev, "Timed out waiting for FIFO to drain\n");
154 spfi_reset(spfi);
155}
156
157static unsigned int spfi_pio_write32(struct img_spfi *spfi, const u32 *buf,
158 unsigned int max)
159{
160 unsigned int count = 0;
161 u32 status;
162
163 while (count < max) {
164 spfi_writel(spfi, SPFI_INTERRUPT_SDFUL, SPFI_INTERRUPT_CLEAR);
165 status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS);
166 if (status & SPFI_INTERRUPT_SDFUL)
167 break;
168 spfi_writel(spfi, buf[count / 4], SPFI_TX_32BIT_VALID_DATA);
169 count += 4;
170 }
171
172 return count;
173}
174
175static unsigned int spfi_pio_write8(struct img_spfi *spfi, const u8 *buf,
176 unsigned int max)
177{
178 unsigned int count = 0;
179 u32 status;
180
181 while (count < max) {
182 spfi_writel(spfi, SPFI_INTERRUPT_SDFUL, SPFI_INTERRUPT_CLEAR);
183 status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS);
184 if (status & SPFI_INTERRUPT_SDFUL)
185 break;
186 spfi_writel(spfi, buf[count], SPFI_TX_8BIT_VALID_DATA);
187 count++;
188 }
189
190 return count;
191}
192
193static unsigned int spfi_pio_read32(struct img_spfi *spfi, u32 *buf,
194 unsigned int max)
195{
196 unsigned int count = 0;
197 u32 status;
198
199 while (count < max) {
200 spfi_writel(spfi, SPFI_INTERRUPT_GDEX32BIT,
201 SPFI_INTERRUPT_CLEAR);
202 status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS);
203 if (!(status & SPFI_INTERRUPT_GDEX32BIT))
204 break;
205 buf[count / 4] = spfi_readl(spfi, SPFI_RX_32BIT_VALID_DATA);
206 count += 4;
207 }
208
209 return count;
210}
211
212static unsigned int spfi_pio_read8(struct img_spfi *spfi, u8 *buf,
213 unsigned int max)
214{
215 unsigned int count = 0;
216 u32 status;
217
218 while (count < max) {
219 spfi_writel(spfi, SPFI_INTERRUPT_GDEX8BIT,
220 SPFI_INTERRUPT_CLEAR);
221 status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS);
222 if (!(status & SPFI_INTERRUPT_GDEX8BIT))
223 break;
224 buf[count] = spfi_readl(spfi, SPFI_RX_8BIT_VALID_DATA);
225 count++;
226 }
227
228 return count;
229}
230
231static int img_spfi_start_pio(struct spi_master *master,
232 struct spi_device *spi,
233 struct spi_transfer *xfer)
234{
235 struct img_spfi *spfi = spi_master_get_devdata(spi->master);
236 unsigned int tx_bytes = 0, rx_bytes = 0;
237 const void *tx_buf = xfer->tx_buf;
238 void *rx_buf = xfer->rx_buf;
239 unsigned long timeout;
240
241 if (tx_buf)
242 tx_bytes = xfer->len;
243 if (rx_buf)
244 rx_bytes = xfer->len;
245
246 spfi_start(spfi);
247
248 timeout = jiffies +
249 msecs_to_jiffies(xfer->len * 8 * 1000 / xfer->speed_hz + 100);
250 while ((tx_bytes > 0 || rx_bytes > 0) &&
251 time_before(jiffies, timeout)) {
252 unsigned int tx_count, rx_count;
253
254 switch (xfer->bits_per_word) {
255 case 32:
256 tx_count = spfi_pio_write32(spfi, tx_buf, tx_bytes);
257 rx_count = spfi_pio_read32(spfi, rx_buf, rx_bytes);
258 break;
259 case 8:
260 default:
261 tx_count = spfi_pio_write8(spfi, tx_buf, tx_bytes);
262 rx_count = spfi_pio_read8(spfi, rx_buf, rx_bytes);
263 break;
264 }
265
266 tx_buf += tx_count;
267 rx_buf += rx_count;
268 tx_bytes -= tx_count;
269 rx_bytes -= rx_count;
270
271 cpu_relax();
272 }
273
274 if (rx_bytes > 0 || tx_bytes > 0) {
275 dev_err(spfi->dev, "PIO transfer timed out\n");
276 spfi_reset(spfi);
277 return -ETIMEDOUT;
278 }
279
280 if (tx_buf)
281 spfi_flush_tx_fifo(spfi);
282 spfi_stop(spfi);
283
284 return 0;
285}
286
287static void img_spfi_dma_rx_cb(void *data)
288{
289 struct img_spfi *spfi = data;
290 unsigned long flags;
291
292 spin_lock_irqsave(&spfi->lock, flags);
293
294 spfi->rx_dma_busy = false;
295 if (!spfi->tx_dma_busy) {
296 spfi_stop(spfi);
297 spi_finalize_current_transfer(spfi->master);
298 }
299
300 spin_unlock_irqrestore(&spfi->lock, flags);
301}
302
303static void img_spfi_dma_tx_cb(void *data)
304{
305 struct img_spfi *spfi = data;
306 unsigned long flags;
307
308 spfi_flush_tx_fifo(spfi);
309
310 spin_lock_irqsave(&spfi->lock, flags);
311
312 spfi->tx_dma_busy = false;
313 if (!spfi->rx_dma_busy) {
314 spfi_stop(spfi);
315 spi_finalize_current_transfer(spfi->master);
316 }
317
318 spin_unlock_irqrestore(&spfi->lock, flags);
319}
320
321static int img_spfi_start_dma(struct spi_master *master,
322 struct spi_device *spi,
323 struct spi_transfer *xfer)
324{
325 struct img_spfi *spfi = spi_master_get_devdata(spi->master);
326 struct dma_async_tx_descriptor *rxdesc = NULL, *txdesc = NULL;
327 struct dma_slave_config rxconf, txconf;
328
329 spfi->rx_dma_busy = false;
330 spfi->tx_dma_busy = false;
331
332 if (xfer->rx_buf) {
333 rxconf.direction = DMA_DEV_TO_MEM;
334 switch (xfer->bits_per_word) {
335 case 32:
336 rxconf.src_addr = spfi->phys + SPFI_RX_32BIT_VALID_DATA;
337 rxconf.src_addr_width = 4;
338 rxconf.src_maxburst = 4;
339 break;
340 case 8:
341 default:
342 rxconf.src_addr = spfi->phys + SPFI_RX_8BIT_VALID_DATA;
343 rxconf.src_addr_width = 1;
344 rxconf.src_maxburst = 1;
345 }
346 dmaengine_slave_config(spfi->rx_ch, &rxconf);
347
348 rxdesc = dmaengine_prep_slave_sg(spfi->rx_ch, xfer->rx_sg.sgl,
349 xfer->rx_sg.nents,
350 DMA_DEV_TO_MEM,
351 DMA_PREP_INTERRUPT);
352 if (!rxdesc)
353 goto stop_dma;
354
355 rxdesc->callback = img_spfi_dma_rx_cb;
356 rxdesc->callback_param = spfi;
357 }
358
359 if (xfer->tx_buf) {
360 txconf.direction = DMA_MEM_TO_DEV;
361 switch (xfer->bits_per_word) {
362 case 32:
363 txconf.dst_addr = spfi->phys + SPFI_TX_32BIT_VALID_DATA;
364 txconf.dst_addr_width = 4;
365 txconf.dst_maxburst = 4;
366 break;
367 case 8:
368 default:
369 txconf.dst_addr = spfi->phys + SPFI_TX_8BIT_VALID_DATA;
370 txconf.dst_addr_width = 1;
371 txconf.dst_maxburst = 1;
372 break;
373 }
374 dmaengine_slave_config(spfi->tx_ch, &txconf);
375
376 txdesc = dmaengine_prep_slave_sg(spfi->tx_ch, xfer->tx_sg.sgl,
377 xfer->tx_sg.nents,
378 DMA_MEM_TO_DEV,
379 DMA_PREP_INTERRUPT);
380 if (!txdesc)
381 goto stop_dma;
382
383 txdesc->callback = img_spfi_dma_tx_cb;
384 txdesc->callback_param = spfi;
385 }
386
387 if (xfer->rx_buf) {
388 spfi->rx_dma_busy = true;
389 dmaengine_submit(rxdesc);
390 dma_async_issue_pending(spfi->rx_ch);
391 }
392
393 if (xfer->tx_buf) {
394 spfi->tx_dma_busy = true;
395 dmaengine_submit(txdesc);
396 dma_async_issue_pending(spfi->tx_ch);
397 }
398
399 spfi_start(spfi);
400
401 return 1;
402
403stop_dma:
404 dmaengine_terminate_all(spfi->rx_ch);
405 dmaengine_terminate_all(spfi->tx_ch);
406 return -EIO;
407}
408
409static void img_spfi_config(struct spi_master *master, struct spi_device *spi,
410 struct spi_transfer *xfer)
411{
412 struct img_spfi *spfi = spi_master_get_devdata(spi->master);
413 u32 val, div;
414
415 /*
416 * output = spfi_clk * (BITCLK / 512), where BITCLK must be a
417 * power of 2 up to 256 (where 255 == 256 since BITCLK is 8 bits)
418 */
419 div = DIV_ROUND_UP(master->max_speed_hz, xfer->speed_hz);
420 div = clamp(512 / (1 << get_count_order(div)), 1, 255);
421
422 val = spfi_readl(spfi, SPFI_DEVICE_PARAMETER(spi->chip_select));
423 val &= ~(SPFI_DEVICE_PARAMETER_BITCLK_MASK <<
424 SPFI_DEVICE_PARAMETER_BITCLK_SHIFT);
425 val |= div << SPFI_DEVICE_PARAMETER_BITCLK_SHIFT;
426 spfi_writel(spfi, val, SPFI_DEVICE_PARAMETER(spi->chip_select));
427
428 val = spfi_readl(spfi, SPFI_CONTROL);
429 val &= ~(SPFI_CONTROL_SEND_DMA | SPFI_CONTROL_GET_DMA);
430 if (xfer->tx_buf)
431 val |= SPFI_CONTROL_SEND_DMA;
432 if (xfer->rx_buf)
433 val |= SPFI_CONTROL_GET_DMA;
434 val &= ~(SPFI_CONTROL_TMODE_MASK << SPFI_CONTROL_TMODE_SHIFT);
435 if (xfer->tx_nbits == SPI_NBITS_DUAL &&
436 xfer->rx_nbits == SPI_NBITS_DUAL)
437 val |= SPFI_CONTROL_TMODE_DUAL << SPFI_CONTROL_TMODE_SHIFT;
438 else if (xfer->tx_nbits == SPI_NBITS_QUAD &&
439 xfer->rx_nbits == SPI_NBITS_QUAD)
440 val |= SPFI_CONTROL_TMODE_QUAD << SPFI_CONTROL_TMODE_SHIFT;
441 val &= ~SPFI_CONTROL_CONTINUE;
442 if (!xfer->cs_change && !list_is_last(&xfer->transfer_list,
443 &master->cur_msg->transfers))
444 val |= SPFI_CONTROL_CONTINUE;
445 spfi_writel(spfi, val, SPFI_CONTROL);
446
447 val = spfi_readl(spfi, SPFI_PORT_STATE);
448 if (spi->mode & SPI_CPHA)
449 val |= SPFI_PORT_STATE_CK_PHASE(spi->chip_select);
450 else
451 val &= ~SPFI_PORT_STATE_CK_PHASE(spi->chip_select);
452 if (spi->mode & SPI_CPOL)
453 val |= SPFI_PORT_STATE_CK_POL(spi->chip_select);
454 else
455 val &= ~SPFI_PORT_STATE_CK_POL(spi->chip_select);
456 spfi_writel(spfi, val, SPFI_PORT_STATE);
457
458 spfi_writel(spfi, xfer->len << SPFI_TRANSACTION_TSIZE_SHIFT,
459 SPFI_TRANSACTION);
460}
461
462static int img_spfi_transfer_one(struct spi_master *master,
463 struct spi_device *spi,
464 struct spi_transfer *xfer)
465{
466 struct img_spfi *spfi = spi_master_get_devdata(spi->master);
467 bool dma_reset = false;
468 unsigned long flags;
469 int ret;
470
471 /*
472 * Stop all DMA and reset the controller if the previous transaction
473 * timed-out and never completed it's DMA.
474 */
475 spin_lock_irqsave(&spfi->lock, flags);
476 if (spfi->tx_dma_busy || spfi->rx_dma_busy) {
477 dev_err(spfi->dev, "SPI DMA still busy\n");
478 dma_reset = true;
479 }
480 spin_unlock_irqrestore(&spfi->lock, flags);
481
482 if (dma_reset) {
483 dmaengine_terminate_all(spfi->tx_ch);
484 dmaengine_terminate_all(spfi->rx_ch);
485 spfi_reset(spfi);
486 }
487
488 img_spfi_config(master, spi, xfer);
489 if (master->can_dma && master->can_dma(master, spi, xfer))
490 ret = img_spfi_start_dma(master, spi, xfer);
491 else
492 ret = img_spfi_start_pio(master, spi, xfer);
493
494 return ret;
495}
496
497static void img_spfi_set_cs(struct spi_device *spi, bool enable)
498{
499 struct img_spfi *spfi = spi_master_get_devdata(spi->master);
500 u32 val;
501
502 val = spfi_readl(spfi, SPFI_PORT_STATE);
503 val &= ~(SPFI_PORT_STATE_DEV_SEL_MASK << SPFI_PORT_STATE_DEV_SEL_SHIFT);
504 val |= spi->chip_select << SPFI_PORT_STATE_DEV_SEL_SHIFT;
505 spfi_writel(spfi, val, SPFI_PORT_STATE);
506}
507
508static bool img_spfi_can_dma(struct spi_master *master, struct spi_device *spi,
509 struct spi_transfer *xfer)
510{
511 if (xfer->bits_per_word == 8 && xfer->len > SPFI_8BIT_FIFO_SIZE)
512 return true;
513 if (xfer->bits_per_word == 32 && xfer->len > SPFI_32BIT_FIFO_SIZE)
514 return true;
515 return false;
516}
517
518static irqreturn_t img_spfi_irq(int irq, void *dev_id)
519{
520 struct img_spfi *spfi = (struct img_spfi *)dev_id;
521 u32 status;
522
523 status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS);
524 if (status & SPFI_INTERRUPT_IACCESS) {
525 spfi_writel(spfi, SPFI_INTERRUPT_IACCESS, SPFI_INTERRUPT_CLEAR);
526 dev_err(spfi->dev, "Illegal access interrupt");
527 return IRQ_HANDLED;
528 }
529
530 return IRQ_NONE;
531}
532
533static int img_spfi_probe(struct platform_device *pdev)
534{
535 struct spi_master *master;
536 struct img_spfi *spfi;
537 struct resource *res;
538 int ret;
539
540 master = spi_alloc_master(&pdev->dev, sizeof(*spfi));
541 if (!master)
542 return -ENOMEM;
543 platform_set_drvdata(pdev, master);
544
545 spfi = spi_master_get_devdata(master);
546 spfi->dev = &pdev->dev;
547 spfi->master = master;
548 spin_lock_init(&spfi->lock);
549
550 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
551 spfi->regs = devm_ioremap_resource(spfi->dev, res);
552 if (IS_ERR(spfi->regs)) {
553 ret = PTR_ERR(spfi->regs);
554 goto put_spi;
555 }
556 spfi->phys = res->start;
557
558 spfi->irq = platform_get_irq(pdev, 0);
559 if (spfi->irq < 0) {
560 ret = spfi->irq;
561 goto put_spi;
562 }
563 ret = devm_request_irq(spfi->dev, spfi->irq, img_spfi_irq,
564 IRQ_TYPE_LEVEL_HIGH, dev_name(spfi->dev), spfi);
565 if (ret)
566 goto put_spi;
567
568 spfi->sys_clk = devm_clk_get(spfi->dev, "sys");
569 if (IS_ERR(spfi->sys_clk)) {
570 ret = PTR_ERR(spfi->sys_clk);
571 goto put_spi;
572 }
573 spfi->spfi_clk = devm_clk_get(spfi->dev, "spfi");
574 if (IS_ERR(spfi->spfi_clk)) {
575 ret = PTR_ERR(spfi->spfi_clk);
576 goto put_spi;
577 }
578
579 ret = clk_prepare_enable(spfi->sys_clk);
580 if (ret)
581 goto put_spi;
582 ret = clk_prepare_enable(spfi->spfi_clk);
583 if (ret)
584 goto disable_pclk;
585
586 spfi_reset(spfi);
587 /*
588 * Only enable the error (IACCESS) interrupt. In PIO mode we'll
589 * poll the status of the FIFOs.
590 */
591 spfi_writel(spfi, SPFI_INTERRUPT_IACCESS, SPFI_INTERRUPT_ENABLE);
592
593 master->auto_runtime_pm = true;
594 master->bus_num = pdev->id;
595 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_TX_DUAL | SPI_RX_DUAL;
596 if (of_property_read_bool(spfi->dev->of_node, "img,supports-quad-mode"))
597 master->mode_bits |= SPI_TX_QUAD | SPI_RX_QUAD;
598 master->num_chipselect = 5;
599 master->dev.of_node = pdev->dev.of_node;
600 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(8);
601 master->max_speed_hz = clk_get_rate(spfi->spfi_clk);
602 master->min_speed_hz = master->max_speed_hz / 512;
603
604 master->set_cs = img_spfi_set_cs;
605 master->transfer_one = img_spfi_transfer_one;
606
607 spfi->tx_ch = dma_request_slave_channel(spfi->dev, "tx");
608 spfi->rx_ch = dma_request_slave_channel(spfi->dev, "rx");
609 if (!spfi->tx_ch || !spfi->rx_ch) {
610 if (spfi->tx_ch)
611 dma_release_channel(spfi->tx_ch);
612 if (spfi->rx_ch)
613 dma_release_channel(spfi->rx_ch);
614 dev_warn(spfi->dev, "Failed to get DMA channels, falling back to PIO mode\n");
615 } else {
616 master->dma_tx = spfi->tx_ch;
617 master->dma_rx = spfi->rx_ch;
618 master->can_dma = img_spfi_can_dma;
619 }
620
621 pm_runtime_set_active(spfi->dev);
622 pm_runtime_enable(spfi->dev);
623
624 ret = devm_spi_register_master(spfi->dev, master);
625 if (ret)
626 goto disable_pm;
627
628 return 0;
629
630disable_pm:
631 pm_runtime_disable(spfi->dev);
632 if (spfi->rx_ch)
633 dma_release_channel(spfi->rx_ch);
634 if (spfi->tx_ch)
635 dma_release_channel(spfi->tx_ch);
636 clk_disable_unprepare(spfi->spfi_clk);
637disable_pclk:
638 clk_disable_unprepare(spfi->sys_clk);
639put_spi:
640 spi_master_put(master);
641
642 return ret;
643}
644
645static int img_spfi_remove(struct platform_device *pdev)
646{
647 struct spi_master *master = platform_get_drvdata(pdev);
648 struct img_spfi *spfi = spi_master_get_devdata(master);
649
650 if (spfi->tx_ch)
651 dma_release_channel(spfi->tx_ch);
652 if (spfi->rx_ch)
653 dma_release_channel(spfi->rx_ch);
654
655 pm_runtime_disable(spfi->dev);
656 if (!pm_runtime_status_suspended(spfi->dev)) {
657 clk_disable_unprepare(spfi->spfi_clk);
658 clk_disable_unprepare(spfi->sys_clk);
659 }
660
661 spi_master_put(master);
662
663 return 0;
664}
665
666#ifdef CONFIG_PM_RUNTIME
667static int img_spfi_runtime_suspend(struct device *dev)
668{
669 struct spi_master *master = dev_get_drvdata(dev);
670 struct img_spfi *spfi = spi_master_get_devdata(master);
671
672 clk_disable_unprepare(spfi->spfi_clk);
673 clk_disable_unprepare(spfi->sys_clk);
674
675 return 0;
676}
677
678static int img_spfi_runtime_resume(struct device *dev)
679{
680 struct spi_master *master = dev_get_drvdata(dev);
681 struct img_spfi *spfi = spi_master_get_devdata(master);
682 int ret;
683
684 ret = clk_prepare_enable(spfi->sys_clk);
685 if (ret)
686 return ret;
687 ret = clk_prepare_enable(spfi->spfi_clk);
688 if (ret) {
689 clk_disable_unprepare(spfi->sys_clk);
690 return ret;
691 }
692
693 return 0;
694}
695#endif /* CONFIG_PM_RUNTIME */
696
697#ifdef CONFIG_PM_SLEEP
698static int img_spfi_suspend(struct device *dev)
699{
700 struct spi_master *master = dev_get_drvdata(dev);
701
702 return spi_master_suspend(master);
703}
704
705static int img_spfi_resume(struct device *dev)
706{
707 struct spi_master *master = dev_get_drvdata(dev);
708 struct img_spfi *spfi = spi_master_get_devdata(master);
709 int ret;
710
711 ret = pm_runtime_get_sync(dev);
712 if (ret)
713 return ret;
714 spfi_reset(spfi);
715 pm_runtime_put(dev);
716
717 return spi_master_resume(master);
718}
719#endif /* CONFIG_PM_SLEEP */
720
721static const struct dev_pm_ops img_spfi_pm_ops = {
722 SET_RUNTIME_PM_OPS(img_spfi_runtime_suspend, img_spfi_runtime_resume,
723 NULL)
724 SET_SYSTEM_SLEEP_PM_OPS(img_spfi_suspend, img_spfi_resume)
725};
726
727static const struct of_device_id img_spfi_of_match[] = {
728 { .compatible = "img,spfi", },
729 { },
730};
731MODULE_DEVICE_TABLE(of, img_spfi_of_match);
732
733static struct platform_driver img_spfi_driver = {
734 .driver = {
735 .name = "img-spfi",
736 .pm = &img_spfi_pm_ops,
737 .of_match_table = of_match_ptr(img_spfi_of_match),
738 },
739 .probe = img_spfi_probe,
740 .remove = img_spfi_remove,
741};
742module_platform_driver(img_spfi_driver);
743
744MODULE_DESCRIPTION("IMG SPFI controller driver");
745MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>");
746MODULE_LICENSE("GPL v2");
diff --git a/drivers/spi/spi-meson-spifc.c b/drivers/spi/spi-meson-spifc.c
new file mode 100644
index 000000000000..0e48f8c2037d
--- /dev/null
+++ b/drivers/spi/spi-meson-spifc.c
@@ -0,0 +1,462 @@
1/*
2 * Driver for Amlogic Meson SPI flash controller (SPIFC)
3 *
4 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * You should have received a copy of the GNU General Public License
11 * along with this program. If not, see <http://www.gnu.org/licenses/>.
12 */
13
14#include <linux/clk.h>
15#include <linux/delay.h>
16#include <linux/device.h>
17#include <linux/io.h>
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/of.h>
21#include <linux/platform_device.h>
22#include <linux/pm_runtime.h>
23#include <linux/regmap.h>
24#include <linux/spi/spi.h>
25#include <linux/types.h>
26
27/* register map */
28#define REG_CMD 0x00
29#define REG_ADDR 0x04
30#define REG_CTRL 0x08
31#define REG_CTRL1 0x0c
32#define REG_STATUS 0x10
33#define REG_CTRL2 0x14
34#define REG_CLOCK 0x18
35#define REG_USER 0x1c
36#define REG_USER1 0x20
37#define REG_USER2 0x24
38#define REG_USER3 0x28
39#define REG_USER4 0x2c
40#define REG_SLAVE 0x30
41#define REG_SLAVE1 0x34
42#define REG_SLAVE2 0x38
43#define REG_SLAVE3 0x3c
44#define REG_C0 0x40
45#define REG_B8 0x60
46#define REG_MAX 0x7c
47
48/* register fields */
49#define CMD_USER BIT(18)
50#define CTRL_ENABLE_AHB BIT(17)
51#define CLOCK_SOURCE BIT(31)
52#define CLOCK_DIV_SHIFT 12
53#define CLOCK_DIV_MASK (0x3f << CLOCK_DIV_SHIFT)
54#define CLOCK_CNT_HIGH_SHIFT 6
55#define CLOCK_CNT_HIGH_MASK (0x3f << CLOCK_CNT_HIGH_SHIFT)
56#define CLOCK_CNT_LOW_SHIFT 0
57#define CLOCK_CNT_LOW_MASK (0x3f << CLOCK_CNT_LOW_SHIFT)
58#define USER_DIN_EN_MS BIT(0)
59#define USER_CMP_MODE BIT(2)
60#define USER_UC_DOUT_SEL BIT(27)
61#define USER_UC_DIN_SEL BIT(28)
62#define USER_UC_MASK ((BIT(5) - 1) << 27)
63#define USER1_BN_UC_DOUT_SHIFT 17
64#define USER1_BN_UC_DOUT_MASK (0xff << 16)
65#define USER1_BN_UC_DIN_SHIFT 8
66#define USER1_BN_UC_DIN_MASK (0xff << 8)
67#define USER4_CS_ACT BIT(30)
68#define SLAVE_TRST_DONE BIT(4)
69#define SLAVE_OP_MODE BIT(30)
70#define SLAVE_SW_RST BIT(31)
71
72#define SPIFC_BUFFER_SIZE 64
73
74/**
75 * struct meson_spifc
76 * @master: the SPI master
77 * @regmap: regmap for device registers
78 * @clk: input clock of the built-in baud rate generator
79 * @device: the device structure
80 */
81struct meson_spifc {
82 struct spi_master *master;
83 struct regmap *regmap;
84 struct clk *clk;
85 struct device *dev;
86};
87
88static struct regmap_config spifc_regmap_config = {
89 .reg_bits = 32,
90 .val_bits = 32,
91 .reg_stride = 4,
92 .max_register = REG_MAX,
93};
94
95/**
96 * meson_spifc_wait_ready() - wait for the current operation to terminate
97 * @spifc: the Meson SPI device
98 * Return: 0 on success, a negative value on error
99 */
100static int meson_spifc_wait_ready(struct meson_spifc *spifc)
101{
102 unsigned long deadline = jiffies + msecs_to_jiffies(5);
103 u32 data;
104
105 do {
106 regmap_read(spifc->regmap, REG_SLAVE, &data);
107 if (data & SLAVE_TRST_DONE)
108 return 0;
109 cond_resched();
110 } while (!time_after(jiffies, deadline));
111
112 return -ETIMEDOUT;
113}
114
115/**
116 * meson_spifc_drain_buffer() - copy data from device buffer to memory
117 * @spifc: the Meson SPI device
118 * @buf: the destination buffer
119 * @len: number of bytes to copy
120 */
121static void meson_spifc_drain_buffer(struct meson_spifc *spifc, u8 *buf,
122 int len)
123{
124 u32 data;
125 int i = 0;
126
127 while (i < len) {
128 regmap_read(spifc->regmap, REG_C0 + i, &data);
129
130 if (len - i >= 4) {
131 *((u32 *)buf) = data;
132 buf += 4;
133 } else {
134 memcpy(buf, &data, len - i);
135 break;
136 }
137 i += 4;
138 }
139}
140
141/**
142 * meson_spifc_fill_buffer() - copy data from memory to device buffer
143 * @spifc: the Meson SPI device
144 * @buf: the source buffer
145 * @len: number of bytes to copy
146 */
147static void meson_spifc_fill_buffer(struct meson_spifc *spifc, const u8 *buf,
148 int len)
149{
150 u32 data;
151 int i = 0;
152
153 while (i < len) {
154 if (len - i >= 4)
155 data = *(u32 *)buf;
156 else
157 memcpy(&data, buf, len - i);
158
159 regmap_write(spifc->regmap, REG_C0 + i, data);
160
161 buf += 4;
162 i += 4;
163 }
164}
165
166/**
167 * meson_spifc_setup_speed() - program the clock divider
168 * @spifc: the Meson SPI device
169 * @speed: desired speed in Hz
170 */
171static void meson_spifc_setup_speed(struct meson_spifc *spifc, u32 speed)
172{
173 unsigned long parent, value;
174 int n;
175
176 parent = clk_get_rate(spifc->clk);
177 n = max_t(int, parent / speed - 1, 1);
178
179 dev_dbg(spifc->dev, "parent %lu, speed %u, n %d\n", parent,
180 speed, n);
181
182 value = (n << CLOCK_DIV_SHIFT) & CLOCK_DIV_MASK;
183 value |= (n << CLOCK_CNT_LOW_SHIFT) & CLOCK_CNT_LOW_MASK;
184 value |= (((n + 1) / 2 - 1) << CLOCK_CNT_HIGH_SHIFT) &
185 CLOCK_CNT_HIGH_MASK;
186
187 regmap_write(spifc->regmap, REG_CLOCK, value);
188}
189
190/**
191 * meson_spifc_txrx() - transfer a chunk of data
192 * @spifc: the Meson SPI device
193 * @xfer: the current SPI transfer
194 * @offset: offset of the data to transfer
195 * @len: length of the data to transfer
196 * @last_xfer: whether this is the last transfer of the message
197 * @last_chunk: whether this is the last chunk of the transfer
198 * Return: 0 on success, a negative value on error
199 */
200static int meson_spifc_txrx(struct meson_spifc *spifc,
201 struct spi_transfer *xfer,
202 int offset, int len, bool last_xfer,
203 bool last_chunk)
204{
205 bool keep_cs = true;
206 int ret;
207
208 if (xfer->tx_buf)
209 meson_spifc_fill_buffer(spifc, xfer->tx_buf + offset, len);
210
211 /* enable DOUT stage */
212 regmap_update_bits(spifc->regmap, REG_USER, USER_UC_MASK,
213 USER_UC_DOUT_SEL);
214 regmap_write(spifc->regmap, REG_USER1,
215 (8 * len - 1) << USER1_BN_UC_DOUT_SHIFT);
216
217 /* enable data input during DOUT */
218 regmap_update_bits(spifc->regmap, REG_USER, USER_DIN_EN_MS,
219 USER_DIN_EN_MS);
220
221 if (last_chunk) {
222 if (last_xfer)
223 keep_cs = xfer->cs_change;
224 else
225 keep_cs = !xfer->cs_change;
226 }
227
228 regmap_update_bits(spifc->regmap, REG_USER4, USER4_CS_ACT,
229 keep_cs ? USER4_CS_ACT : 0);
230
231 /* clear transition done bit */
232 regmap_update_bits(spifc->regmap, REG_SLAVE, SLAVE_TRST_DONE, 0);
233 /* start transfer */
234 regmap_update_bits(spifc->regmap, REG_CMD, CMD_USER, CMD_USER);
235
236 ret = meson_spifc_wait_ready(spifc);
237
238 if (!ret && xfer->rx_buf)
239 meson_spifc_drain_buffer(spifc, xfer->rx_buf + offset, len);
240
241 return ret;
242}
243
244/**
245 * meson_spifc_transfer_one() - perform a single transfer
246 * @master: the SPI master
247 * @spi: the SPI device
248 * @xfer: the current SPI transfer
249 * Return: 0 on success, a negative value on error
250 */
251static int meson_spifc_transfer_one(struct spi_master *master,
252 struct spi_device *spi,
253 struct spi_transfer *xfer)
254{
255 struct meson_spifc *spifc = spi_master_get_devdata(master);
256 int len, done = 0, ret = 0;
257
258 meson_spifc_setup_speed(spifc, xfer->speed_hz);
259
260 regmap_update_bits(spifc->regmap, REG_CTRL, CTRL_ENABLE_AHB, 0);
261
262 while (done < xfer->len && !ret) {
263 len = min_t(int, xfer->len - done, SPIFC_BUFFER_SIZE);
264 ret = meson_spifc_txrx(spifc, xfer, done, len,
265 spi_transfer_is_last(master, xfer),
266 done + len >= xfer->len);
267 done += len;
268 }
269
270 regmap_update_bits(spifc->regmap, REG_CTRL, CTRL_ENABLE_AHB,
271 CTRL_ENABLE_AHB);
272
273 return ret;
274}
275
276/**
277 * meson_spifc_hw_init() - reset and initialize the SPI controller
278 * @spifc: the Meson SPI device
279 */
280static void meson_spifc_hw_init(struct meson_spifc *spifc)
281{
282 /* reset device */
283 regmap_update_bits(spifc->regmap, REG_SLAVE, SLAVE_SW_RST,
284 SLAVE_SW_RST);
285 /* disable compatible mode */
286 regmap_update_bits(spifc->regmap, REG_USER, USER_CMP_MODE, 0);
287 /* set master mode */
288 regmap_update_bits(spifc->regmap, REG_SLAVE, SLAVE_OP_MODE, 0);
289}
290
291static int meson_spifc_probe(struct platform_device *pdev)
292{
293 struct spi_master *master;
294 struct meson_spifc *spifc;
295 struct resource *res;
296 void __iomem *base;
297 unsigned int rate;
298 int ret = 0;
299
300 master = spi_alloc_master(&pdev->dev, sizeof(struct meson_spifc));
301 if (!master)
302 return -ENOMEM;
303
304 platform_set_drvdata(pdev, master);
305
306 spifc = spi_master_get_devdata(master);
307 spifc->dev = &pdev->dev;
308
309 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
310 base = devm_ioremap_resource(spifc->dev, res);
311 if (IS_ERR(base)) {
312 ret = PTR_ERR(base);
313 goto out_err;
314 }
315
316 spifc->regmap = devm_regmap_init_mmio(spifc->dev, base,
317 &spifc_regmap_config);
318 if (IS_ERR(spifc->regmap)) {
319 ret = PTR_ERR(spifc->regmap);
320 goto out_err;
321 }
322
323 spifc->clk = devm_clk_get(spifc->dev, NULL);
324 if (IS_ERR(spifc->clk)) {
325 dev_err(spifc->dev, "missing clock\n");
326 ret = PTR_ERR(spifc->clk);
327 goto out_err;
328 }
329
330 ret = clk_prepare_enable(spifc->clk);
331 if (ret) {
332 dev_err(spifc->dev, "can't prepare clock\n");
333 goto out_err;
334 }
335
336 rate = clk_get_rate(spifc->clk);
337
338 master->num_chipselect = 1;
339 master->dev.of_node = pdev->dev.of_node;
340 master->bits_per_word_mask = SPI_BPW_MASK(8);
341 master->auto_runtime_pm = true;
342 master->transfer_one = meson_spifc_transfer_one;
343 master->min_speed_hz = rate >> 6;
344 master->max_speed_hz = rate >> 1;
345
346 meson_spifc_hw_init(spifc);
347
348 pm_runtime_set_active(spifc->dev);
349 pm_runtime_enable(spifc->dev);
350
351 ret = devm_spi_register_master(spifc->dev, master);
352 if (ret) {
353 dev_err(spifc->dev, "failed to register spi master\n");
354 goto out_clk;
355 }
356
357 return 0;
358out_clk:
359 clk_disable_unprepare(spifc->clk);
360out_err:
361 spi_master_put(master);
362 return ret;
363}
364
365static int meson_spifc_remove(struct platform_device *pdev)
366{
367 struct spi_master *master = platform_get_drvdata(pdev);
368 struct meson_spifc *spifc = spi_master_get_devdata(master);
369
370 pm_runtime_get_sync(&pdev->dev);
371 clk_disable_unprepare(spifc->clk);
372 pm_runtime_disable(&pdev->dev);
373
374 return 0;
375}
376
377#ifdef CONFIG_PM_SLEEP
378static int meson_spifc_suspend(struct device *dev)
379{
380 struct spi_master *master = dev_get_drvdata(dev);
381 struct meson_spifc *spifc = spi_master_get_devdata(master);
382 int ret;
383
384 ret = spi_master_suspend(master);
385 if (ret)
386 return ret;
387
388 if (!pm_runtime_suspended(dev))
389 clk_disable_unprepare(spifc->clk);
390
391 return 0;
392}
393
394static int meson_spifc_resume(struct device *dev)
395{
396 struct spi_master *master = dev_get_drvdata(dev);
397 struct meson_spifc *spifc = spi_master_get_devdata(master);
398 int ret;
399
400 if (!pm_runtime_suspended(dev)) {
401 ret = clk_prepare_enable(spifc->clk);
402 if (ret)
403 return ret;
404 }
405
406 meson_spifc_hw_init(spifc);
407
408 ret = spi_master_resume(master);
409 if (ret)
410 clk_disable_unprepare(spifc->clk);
411
412 return ret;
413}
414#endif /* CONFIG_PM_SLEEP */
415
416#ifdef CONFIG_PM_RUNTIME
417static int meson_spifc_runtime_suspend(struct device *dev)
418{
419 struct spi_master *master = dev_get_drvdata(dev);
420 struct meson_spifc *spifc = spi_master_get_devdata(master);
421
422 clk_disable_unprepare(spifc->clk);
423
424 return 0;
425}
426
427static int meson_spifc_runtime_resume(struct device *dev)
428{
429 struct spi_master *master = dev_get_drvdata(dev);
430 struct meson_spifc *spifc = spi_master_get_devdata(master);
431
432 return clk_prepare_enable(spifc->clk);
433}
434#endif /* CONFIG_PM_RUNTIME */
435
436static const struct dev_pm_ops meson_spifc_pm_ops = {
437 SET_SYSTEM_SLEEP_PM_OPS(meson_spifc_suspend, meson_spifc_resume)
438 SET_RUNTIME_PM_OPS(meson_spifc_runtime_suspend,
439 meson_spifc_runtime_resume,
440 NULL)
441};
442
443static const struct of_device_id meson_spifc_dt_match[] = {
444 { .compatible = "amlogic,meson6-spifc", },
445 { },
446};
447
448static struct platform_driver meson_spifc_driver = {
449 .probe = meson_spifc_probe,
450 .remove = meson_spifc_remove,
451 .driver = {
452 .name = "meson-spifc",
453 .of_match_table = of_match_ptr(meson_spifc_dt_match),
454 .pm = &meson_spifc_pm_ops,
455 },
456};
457
458module_platform_driver(meson_spifc_driver);
459
460MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
461MODULE_DESCRIPTION("Amlogic Meson SPIFC driver");
462MODULE_LICENSE("GPL v2");
diff --git a/drivers/spi/spi-mxs.c b/drivers/spi/spi-mxs.c
index 51460878af04..06a11546a1a7 100644
--- a/drivers/spi/spi-mxs.c
+++ b/drivers/spi/spi-mxs.c
@@ -182,7 +182,6 @@ static int mxs_spi_txrx_dma(struct mxs_spi *spi,
182 int min, ret; 182 int min, ret;
183 u32 ctrl0; 183 u32 ctrl0;
184 struct page *vm_page; 184 struct page *vm_page;
185 void *sg_buf;
186 struct { 185 struct {
187 u32 pio[4]; 186 u32 pio[4];
188 struct scatterlist sg; 187 struct scatterlist sg;
@@ -232,13 +231,14 @@ static int mxs_spi_txrx_dma(struct mxs_spi *spi,
232 ret = -ENOMEM; 231 ret = -ENOMEM;
233 goto err_vmalloc; 232 goto err_vmalloc;
234 } 233 }
235 sg_buf = page_address(vm_page) + 234
236 ((size_t)buf & ~PAGE_MASK); 235 sg_init_table(&dma_xfer[sg_count].sg, 1);
236 sg_set_page(&dma_xfer[sg_count].sg, vm_page,
237 min, offset_in_page(buf));
237 } else { 238 } else {
238 sg_buf = buf; 239 sg_init_one(&dma_xfer[sg_count].sg, buf, min);
239 } 240 }
240 241
241 sg_init_one(&dma_xfer[sg_count].sg, sg_buf, min);
242 ret = dma_map_sg(ssp->dev, &dma_xfer[sg_count].sg, 1, 242 ret = dma_map_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
243 (flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE); 243 (flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
244 244
@@ -511,7 +511,7 @@ static int mxs_spi_probe(struct platform_device *pdev)
511 init_completion(&spi->c); 511 init_completion(&spi->c);
512 512
513 ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0, 513 ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0,
514 DRIVER_NAME, ssp); 514 dev_name(&pdev->dev), ssp);
515 if (ret) 515 if (ret)
516 goto out_master_free; 516 goto out_master_free;
517 517
diff --git a/drivers/spi/spi-pxa2xx-pci.c b/drivers/spi/spi-pxa2xx-pci.c
index 6beee8ce2d68..fa7399e84bbb 100644
--- a/drivers/spi/spi-pxa2xx-pci.c
+++ b/drivers/spi/spi-pxa2xx-pci.c
@@ -19,6 +19,7 @@ enum {
19 PORT_BSW0, 19 PORT_BSW0,
20 PORT_BSW1, 20 PORT_BSW1,
21 PORT_BSW2, 21 PORT_BSW2,
22 PORT_QUARK_X1000,
22}; 23};
23 24
24struct pxa_spi_info { 25struct pxa_spi_info {
@@ -92,6 +93,12 @@ static struct pxa_spi_info spi_info_configs[] = {
92 .tx_param = &bsw2_tx_param, 93 .tx_param = &bsw2_tx_param,
93 .rx_param = &bsw2_rx_param, 94 .rx_param = &bsw2_rx_param,
94 }, 95 },
96 [PORT_QUARK_X1000] = {
97 .type = QUARK_X1000_SSP,
98 .port_id = -1,
99 .num_chipselect = 1,
100 .max_clk_rate = 50000000,
101 },
95}; 102};
96 103
97static int pxa2xx_spi_pci_probe(struct pci_dev *dev, 104static int pxa2xx_spi_pci_probe(struct pci_dev *dev,
@@ -191,6 +198,7 @@ static void pxa2xx_spi_pci_remove(struct pci_dev *dev)
191 198
192static const struct pci_device_id pxa2xx_spi_pci_devices[] = { 199static const struct pci_device_id pxa2xx_spi_pci_devices[] = {
193 { PCI_VDEVICE(INTEL, 0x2e6a), PORT_CE4100 }, 200 { PCI_VDEVICE(INTEL, 0x2e6a), PORT_CE4100 },
201 { PCI_VDEVICE(INTEL, 0x0935), PORT_QUARK_X1000 },
194 { PCI_VDEVICE(INTEL, 0x0f0e), PORT_BYT }, 202 { PCI_VDEVICE(INTEL, 0x0f0e), PORT_BYT },
195 { PCI_VDEVICE(INTEL, 0x228e), PORT_BSW0 }, 203 { PCI_VDEVICE(INTEL, 0x228e), PORT_BSW0 },
196 { PCI_VDEVICE(INTEL, 0x2290), PORT_BSW1 }, 204 { PCI_VDEVICE(INTEL, 0x2290), PORT_BSW1 },
diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c
index d8a105f76837..1a1df5092aca 100644
--- a/drivers/spi/spi-pxa2xx.c
+++ b/drivers/spi/spi-pxa2xx.c
@@ -63,10 +63,64 @@ MODULE_ALIAS("platform:pxa2xx-spi");
63 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \ 63 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
64 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) 64 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
65 65
66#define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF \
67 | QUARK_X1000_SSCR1_EFWR \
68 | QUARK_X1000_SSCR1_RFT \
69 | QUARK_X1000_SSCR1_TFT \
70 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
71
66#define LPSS_RX_THRESH_DFLT 64 72#define LPSS_RX_THRESH_DFLT 64
67#define LPSS_TX_LOTHRESH_DFLT 160 73#define LPSS_TX_LOTHRESH_DFLT 160
68#define LPSS_TX_HITHRESH_DFLT 224 74#define LPSS_TX_HITHRESH_DFLT 224
69 75
76struct quark_spi_rate {
77 u32 bitrate;
78 u32 dds_clk_rate;
79 u32 clk_div;
80};
81
82/*
83 * 'rate', 'dds', 'clk_div' lookup table, which is defined in
84 * the Quark SPI datasheet.
85 */
86static const struct quark_spi_rate quark_spi_rate_table[] = {
87/* bitrate, dds_clk_rate, clk_div */
88 {50000000, 0x800000, 0},
89 {40000000, 0x666666, 0},
90 {25000000, 0x400000, 0},
91 {20000000, 0x666666, 1},
92 {16667000, 0x800000, 2},
93 {13333000, 0x666666, 2},
94 {12500000, 0x200000, 0},
95 {10000000, 0x800000, 4},
96 {8000000, 0x666666, 4},
97 {6250000, 0x400000, 3},
98 {5000000, 0x400000, 4},
99 {4000000, 0x666666, 9},
100 {3125000, 0x80000, 0},
101 {2500000, 0x400000, 9},
102 {2000000, 0x666666, 19},
103 {1563000, 0x40000, 0},
104 {1250000, 0x200000, 9},
105 {1000000, 0x400000, 24},
106 {800000, 0x666666, 49},
107 {781250, 0x20000, 0},
108 {625000, 0x200000, 19},
109 {500000, 0x400000, 49},
110 {400000, 0x666666, 99},
111 {390625, 0x10000, 0},
112 {250000, 0x400000, 99},
113 {200000, 0x666666, 199},
114 {195313, 0x8000, 0},
115 {125000, 0x100000, 49},
116 {100000, 0x200000, 124},
117 {50000, 0x100000, 124},
118 {25000, 0x80000, 124},
119 {10016, 0x20000, 77},
120 {5040, 0x20000, 154},
121 {1002, 0x8000, 194},
122};
123
70/* Offset from drv_data->lpss_base */ 124/* Offset from drv_data->lpss_base */
71#define GENERAL_REG 0x08 125#define GENERAL_REG 0x08
72#define GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24) 126#define GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24)
@@ -80,6 +134,96 @@ static bool is_lpss_ssp(const struct driver_data *drv_data)
80 return drv_data->ssp_type == LPSS_SSP; 134 return drv_data->ssp_type == LPSS_SSP;
81} 135}
82 136
137static bool is_quark_x1000_ssp(const struct driver_data *drv_data)
138{
139 return drv_data->ssp_type == QUARK_X1000_SSP;
140}
141
142static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data)
143{
144 switch (drv_data->ssp_type) {
145 case QUARK_X1000_SSP:
146 return QUARK_X1000_SSCR1_CHANGE_MASK;
147 default:
148 return SSCR1_CHANGE_MASK;
149 }
150}
151
152static u32
153pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data)
154{
155 switch (drv_data->ssp_type) {
156 case QUARK_X1000_SSP:
157 return RX_THRESH_QUARK_X1000_DFLT;
158 default:
159 return RX_THRESH_DFLT;
160 }
161}
162
163static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data)
164{
165 void __iomem *reg = drv_data->ioaddr;
166 u32 mask;
167
168 switch (drv_data->ssp_type) {
169 case QUARK_X1000_SSP:
170 mask = QUARK_X1000_SSSR_TFL_MASK;
171 break;
172 default:
173 mask = SSSR_TFL_MASK;
174 break;
175 }
176
177 return (read_SSSR(reg) & mask) == mask;
178}
179
180static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data,
181 u32 *sccr1_reg)
182{
183 u32 mask;
184
185 switch (drv_data->ssp_type) {
186 case QUARK_X1000_SSP:
187 mask = QUARK_X1000_SSCR1_RFT;
188 break;
189 default:
190 mask = SSCR1_RFT;
191 break;
192 }
193 *sccr1_reg &= ~mask;
194}
195
196static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data,
197 u32 *sccr1_reg, u32 threshold)
198{
199 switch (drv_data->ssp_type) {
200 case QUARK_X1000_SSP:
201 *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold);
202 break;
203 default:
204 *sccr1_reg |= SSCR1_RxTresh(threshold);
205 break;
206 }
207}
208
209static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data,
210 u32 clk_div, u8 bits)
211{
212 switch (drv_data->ssp_type) {
213 case QUARK_X1000_SSP:
214 return clk_div
215 | QUARK_X1000_SSCR0_Motorola
216 | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits)
217 | SSCR0_SSE;
218 default:
219 return clk_div
220 | SSCR0_Motorola
221 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
222 | SSCR0_SSE
223 | (bits > 16 ? SSCR0_EDSS : 0);
224 }
225}
226
83/* 227/*
84 * Read and write LPSS SSP private registers. Caller must first check that 228 * Read and write LPSS SSP private registers. Caller must first check that
85 * is_lpss_ssp() returns true before these can be called. 229 * is_lpss_ssp() returns true before these can be called.
@@ -234,7 +378,7 @@ static int null_writer(struct driver_data *drv_data)
234 void __iomem *reg = drv_data->ioaddr; 378 void __iomem *reg = drv_data->ioaddr;
235 u8 n_bytes = drv_data->n_bytes; 379 u8 n_bytes = drv_data->n_bytes;
236 380
237 if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) 381 if (pxa2xx_spi_txfifo_full(drv_data)
238 || (drv_data->tx == drv_data->tx_end)) 382 || (drv_data->tx == drv_data->tx_end))
239 return 0; 383 return 0;
240 384
@@ -262,7 +406,7 @@ static int u8_writer(struct driver_data *drv_data)
262{ 406{
263 void __iomem *reg = drv_data->ioaddr; 407 void __iomem *reg = drv_data->ioaddr;
264 408
265 if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) 409 if (pxa2xx_spi_txfifo_full(drv_data)
266 || (drv_data->tx == drv_data->tx_end)) 410 || (drv_data->tx == drv_data->tx_end))
267 return 0; 411 return 0;
268 412
@@ -289,7 +433,7 @@ static int u16_writer(struct driver_data *drv_data)
289{ 433{
290 void __iomem *reg = drv_data->ioaddr; 434 void __iomem *reg = drv_data->ioaddr;
291 435
292 if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) 436 if (pxa2xx_spi_txfifo_full(drv_data)
293 || (drv_data->tx == drv_data->tx_end)) 437 || (drv_data->tx == drv_data->tx_end))
294 return 0; 438 return 0;
295 439
@@ -316,7 +460,7 @@ static int u32_writer(struct driver_data *drv_data)
316{ 460{
317 void __iomem *reg = drv_data->ioaddr; 461 void __iomem *reg = drv_data->ioaddr;
318 462
319 if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) 463 if (pxa2xx_spi_txfifo_full(drv_data)
320 || (drv_data->tx == drv_data->tx_end)) 464 || (drv_data->tx == drv_data->tx_end))
321 return 0; 465 return 0;
322 466
@@ -508,8 +652,9 @@ static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
508 * remaining RX bytes. 652 * remaining RX bytes.
509 */ 653 */
510 if (pxa25x_ssp_comp(drv_data)) { 654 if (pxa25x_ssp_comp(drv_data)) {
655 u32 rx_thre;
511 656
512 sccr1_reg &= ~SSCR1_RFT; 657 pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg);
513 658
514 bytes_left = drv_data->rx_end - drv_data->rx; 659 bytes_left = drv_data->rx_end - drv_data->rx;
515 switch (drv_data->n_bytes) { 660 switch (drv_data->n_bytes) {
@@ -519,10 +664,11 @@ static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
519 bytes_left >>= 1; 664 bytes_left >>= 1;
520 } 665 }
521 666
522 if (bytes_left > RX_THRESH_DFLT) 667 rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data);
523 bytes_left = RX_THRESH_DFLT; 668 if (rx_thre > bytes_left)
669 rx_thre = bytes_left;
524 670
525 sccr1_reg |= SSCR1_RxTresh(bytes_left); 671 pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre);
526 } 672 }
527 write_SSCR1(sccr1_reg, reg); 673 write_SSCR1(sccr1_reg, reg);
528 } 674 }
@@ -585,6 +731,28 @@ static irqreturn_t ssp_int(int irq, void *dev_id)
585 return drv_data->transfer_handler(drv_data); 731 return drv_data->transfer_handler(drv_data);
586} 732}
587 733
734/*
735 * The Quark SPI data sheet gives a table, and for the given 'rate',
736 * the 'dds' and 'clk_div' can be found in the table.
737 */
738static u32 quark_x1000_set_clk_regvals(u32 rate, u32 *dds, u32 *clk_div)
739{
740 unsigned int i;
741
742 for (i = 0; i < ARRAY_SIZE(quark_spi_rate_table); i++) {
743 if (rate >= quark_spi_rate_table[i].bitrate) {
744 *dds = quark_spi_rate_table[i].dds_clk_rate;
745 *clk_div = quark_spi_rate_table[i].clk_div;
746 return quark_spi_rate_table[i].bitrate;
747 }
748 }
749
750 *dds = quark_spi_rate_table[i-1].dds_clk_rate;
751 *clk_div = quark_spi_rate_table[i-1].clk_div;
752
753 return quark_spi_rate_table[i-1].bitrate;
754}
755
588static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate) 756static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
589{ 757{
590 unsigned long ssp_clk = drv_data->max_clk_rate; 758 unsigned long ssp_clk = drv_data->max_clk_rate;
@@ -598,6 +766,20 @@ static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
598 return ((ssp_clk / rate - 1) & 0xfff) << 8; 766 return ((ssp_clk / rate - 1) & 0xfff) << 8;
599} 767}
600 768
769static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data,
770 struct chip_data *chip, int rate)
771{
772 u32 clk_div;
773
774 switch (drv_data->ssp_type) {
775 case QUARK_X1000_SSP:
776 quark_x1000_set_clk_regvals(rate, &chip->dds_rate, &clk_div);
777 return clk_div << 8;
778 default:
779 return ssp_get_clk_div(drv_data, rate);
780 }
781}
782
601static void pump_transfers(unsigned long data) 783static void pump_transfers(unsigned long data)
602{ 784{
603 struct driver_data *drv_data = (struct driver_data *)data; 785 struct driver_data *drv_data = (struct driver_data *)data;
@@ -613,6 +795,7 @@ static void pump_transfers(unsigned long data)
613 u32 cr1; 795 u32 cr1;
614 u32 dma_thresh = drv_data->cur_chip->dma_threshold; 796 u32 dma_thresh = drv_data->cur_chip->dma_threshold;
615 u32 dma_burst = drv_data->cur_chip->dma_burst_size; 797 u32 dma_burst = drv_data->cur_chip->dma_burst_size;
798 u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data);
616 799
617 /* Get current state information */ 800 /* Get current state information */
618 message = drv_data->cur_msg; 801 message = drv_data->cur_msg;
@@ -699,7 +882,7 @@ static void pump_transfers(unsigned long data)
699 if (transfer->bits_per_word) 882 if (transfer->bits_per_word)
700 bits = transfer->bits_per_word; 883 bits = transfer->bits_per_word;
701 884
702 clk_div = ssp_get_clk_div(drv_data, speed); 885 clk_div = pxa2xx_ssp_get_clk_div(drv_data, chip, speed);
703 886
704 if (bits <= 8) { 887 if (bits <= 8) {
705 drv_data->n_bytes = 1; 888 drv_data->n_bytes = 1;
@@ -731,11 +914,7 @@ static void pump_transfers(unsigned long data)
731 "pump_transfers: DMA burst size reduced to match bits_per_word\n"); 914 "pump_transfers: DMA burst size reduced to match bits_per_word\n");
732 } 915 }
733 916
734 cr0 = clk_div 917 cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
735 | SSCR0_Motorola
736 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
737 | SSCR0_SSE
738 | (bits > 16 ? SSCR0_EDSS : 0);
739 } 918 }
740 919
741 message->state = RUNNING_STATE; 920 message->state = RUNNING_STATE;
@@ -771,17 +950,20 @@ static void pump_transfers(unsigned long data)
771 write_SSITF(chip->lpss_tx_threshold, reg); 950 write_SSITF(chip->lpss_tx_threshold, reg);
772 } 951 }
773 952
953 if (is_quark_x1000_ssp(drv_data) &&
954 (read_DDS_RATE(reg) != chip->dds_rate))
955 write_DDS_RATE(chip->dds_rate, reg);
956
774 /* see if we need to reload the config registers */ 957 /* see if we need to reload the config registers */
775 if ((read_SSCR0(reg) != cr0) 958 if ((read_SSCR0(reg) != cr0) ||
776 || (read_SSCR1(reg) & SSCR1_CHANGE_MASK) != 959 (read_SSCR1(reg) & change_mask) != (cr1 & change_mask)) {
777 (cr1 & SSCR1_CHANGE_MASK)) {
778 960
779 /* stop the SSP, and update the other bits */ 961 /* stop the SSP, and update the other bits */
780 write_SSCR0(cr0 & ~SSCR0_SSE, reg); 962 write_SSCR0(cr0 & ~SSCR0_SSE, reg);
781 if (!pxa25x_ssp_comp(drv_data)) 963 if (!pxa25x_ssp_comp(drv_data))
782 write_SSTO(chip->timeout, reg); 964 write_SSTO(chip->timeout, reg);
783 /* first set CR1 without interrupt and service enables */ 965 /* first set CR1 without interrupt and service enables */
784 write_SSCR1(cr1 & SSCR1_CHANGE_MASK, reg); 966 write_SSCR1(cr1 & change_mask, reg);
785 /* restart the SSP */ 967 /* restart the SSP */
786 write_SSCR0(cr0, reg); 968 write_SSCR0(cr0, reg);
787 969
@@ -875,14 +1057,22 @@ static int setup(struct spi_device *spi)
875 unsigned int clk_div; 1057 unsigned int clk_div;
876 uint tx_thres, tx_hi_thres, rx_thres; 1058 uint tx_thres, tx_hi_thres, rx_thres;
877 1059
878 if (is_lpss_ssp(drv_data)) { 1060 switch (drv_data->ssp_type) {
1061 case QUARK_X1000_SSP:
1062 tx_thres = TX_THRESH_QUARK_X1000_DFLT;
1063 tx_hi_thres = 0;
1064 rx_thres = RX_THRESH_QUARK_X1000_DFLT;
1065 break;
1066 case LPSS_SSP:
879 tx_thres = LPSS_TX_LOTHRESH_DFLT; 1067 tx_thres = LPSS_TX_LOTHRESH_DFLT;
880 tx_hi_thres = LPSS_TX_HITHRESH_DFLT; 1068 tx_hi_thres = LPSS_TX_HITHRESH_DFLT;
881 rx_thres = LPSS_RX_THRESH_DFLT; 1069 rx_thres = LPSS_RX_THRESH_DFLT;
882 } else { 1070 break;
1071 default:
883 tx_thres = TX_THRESH_DFLT; 1072 tx_thres = TX_THRESH_DFLT;
884 tx_hi_thres = 0; 1073 tx_hi_thres = 0;
885 rx_thres = RX_THRESH_DFLT; 1074 rx_thres = RX_THRESH_DFLT;
1075 break;
886 } 1076 }
887 1077
888 /* Only alloc on first setup */ 1078 /* Only alloc on first setup */
@@ -935,9 +1125,6 @@ static int setup(struct spi_device *spi)
935 chip->enable_dma = drv_data->master_info->enable_dma; 1125 chip->enable_dma = drv_data->master_info->enable_dma;
936 } 1126 }
937 1127
938 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
939 (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
940
941 chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres); 1128 chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres);
942 chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres) 1129 chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres)
943 | SSITF_TxHiThresh(tx_hi_thres); 1130 | SSITF_TxHiThresh(tx_hi_thres);
@@ -956,15 +1143,24 @@ static int setup(struct spi_device *spi)
956 } 1143 }
957 } 1144 }
958 1145
959 clk_div = ssp_get_clk_div(drv_data, spi->max_speed_hz); 1146 clk_div = pxa2xx_ssp_get_clk_div(drv_data, chip, spi->max_speed_hz);
960 chip->speed_hz = spi->max_speed_hz; 1147 chip->speed_hz = spi->max_speed_hz;
961 1148
962 chip->cr0 = clk_div 1149 chip->cr0 = pxa2xx_configure_sscr0(drv_data, clk_div,
963 | SSCR0_Motorola 1150 spi->bits_per_word);
964 | SSCR0_DataSize(spi->bits_per_word > 16 ? 1151 switch (drv_data->ssp_type) {
965 spi->bits_per_word - 16 : spi->bits_per_word) 1152 case QUARK_X1000_SSP:
966 | SSCR0_SSE 1153 chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres)
967 | (spi->bits_per_word > 16 ? SSCR0_EDSS : 0); 1154 & QUARK_X1000_SSCR1_RFT)
1155 | (QUARK_X1000_SSCR1_TxTresh(tx_thres)
1156 & QUARK_X1000_SSCR1_TFT);
1157 break;
1158 default:
1159 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
1160 (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
1161 break;
1162 }
1163
968 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); 1164 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
969 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0) 1165 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
970 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0); 1166 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
@@ -993,7 +1189,8 @@ static int setup(struct spi_device *spi)
993 chip->read = u16_reader; 1189 chip->read = u16_reader;
994 chip->write = u16_writer; 1190 chip->write = u16_writer;
995 } else if (spi->bits_per_word <= 32) { 1191 } else if (spi->bits_per_word <= 32) {
996 chip->cr0 |= SSCR0_EDSS; 1192 if (!is_quark_x1000_ssp(drv_data))
1193 chip->cr0 |= SSCR0_EDSS;
997 chip->n_bytes = 4; 1194 chip->n_bytes = 4;
998 chip->read = u32_reader; 1195 chip->read = u32_reader;
999 chip->write = u32_writer; 1196 chip->write = u32_writer;
@@ -1144,7 +1341,15 @@ static int pxa2xx_spi_probe(struct platform_device *pdev)
1144 drv_data->ioaddr = ssp->mmio_base; 1341 drv_data->ioaddr = ssp->mmio_base;
1145 drv_data->ssdr_physical = ssp->phys_base + SSDR; 1342 drv_data->ssdr_physical = ssp->phys_base + SSDR;
1146 if (pxa25x_ssp_comp(drv_data)) { 1343 if (pxa25x_ssp_comp(drv_data)) {
1147 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); 1344 switch (drv_data->ssp_type) {
1345 case QUARK_X1000_SSP:
1346 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1347 break;
1348 default:
1349 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1350 break;
1351 }
1352
1148 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE; 1353 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1149 drv_data->dma_cr1 = 0; 1354 drv_data->dma_cr1 = 0;
1150 drv_data->clear_sr = SSSR_ROR; 1355 drv_data->clear_sr = SSSR_ROR;
@@ -1182,16 +1387,35 @@ static int pxa2xx_spi_probe(struct platform_device *pdev)
1182 1387
1183 /* Load default SSP configuration */ 1388 /* Load default SSP configuration */
1184 write_SSCR0(0, drv_data->ioaddr); 1389 write_SSCR0(0, drv_data->ioaddr);
1185 write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) | 1390 switch (drv_data->ssp_type) {
1186 SSCR1_TxTresh(TX_THRESH_DFLT), 1391 case QUARK_X1000_SSP:
1187 drv_data->ioaddr); 1392 write_SSCR1(QUARK_X1000_SSCR1_RxTresh(
1188 write_SSCR0(SSCR0_SCR(2) 1393 RX_THRESH_QUARK_X1000_DFLT) |
1189 | SSCR0_Motorola 1394 QUARK_X1000_SSCR1_TxTresh(
1190 | SSCR0_DataSize(8), 1395 TX_THRESH_QUARK_X1000_DFLT),
1191 drv_data->ioaddr); 1396 drv_data->ioaddr);
1397
1398 /* using the Motorola SPI protocol and use 8 bit frame */
1399 write_SSCR0(QUARK_X1000_SSCR0_Motorola
1400 | QUARK_X1000_SSCR0_DataSize(8),
1401 drv_data->ioaddr);
1402 break;
1403 default:
1404 write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) |
1405 SSCR1_TxTresh(TX_THRESH_DFLT),
1406 drv_data->ioaddr);
1407 write_SSCR0(SSCR0_SCR(2)
1408 | SSCR0_Motorola
1409 | SSCR0_DataSize(8),
1410 drv_data->ioaddr);
1411 break;
1412 }
1413
1192 if (!pxa25x_ssp_comp(drv_data)) 1414 if (!pxa25x_ssp_comp(drv_data))
1193 write_SSTO(0, drv_data->ioaddr); 1415 write_SSTO(0, drv_data->ioaddr);
1194 write_SSPSP(0, drv_data->ioaddr); 1416
1417 if (!is_quark_x1000_ssp(drv_data))
1418 write_SSPSP(0, drv_data->ioaddr);
1195 1419
1196 lpss_ssp_setup(drv_data); 1420 lpss_ssp_setup(drv_data);
1197 1421
@@ -1274,7 +1498,9 @@ static int pxa2xx_spi_suspend(struct device *dev)
1274 if (status != 0) 1498 if (status != 0)
1275 return status; 1499 return status;
1276 write_SSCR0(0, drv_data->ioaddr); 1500 write_SSCR0(0, drv_data->ioaddr);
1277 clk_disable_unprepare(ssp->clk); 1501
1502 if (!pm_runtime_suspended(dev))
1503 clk_disable_unprepare(ssp->clk);
1278 1504
1279 return 0; 1505 return 0;
1280} 1506}
@@ -1288,7 +1514,8 @@ static int pxa2xx_spi_resume(struct device *dev)
1288 pxa2xx_spi_dma_resume(drv_data); 1514 pxa2xx_spi_dma_resume(drv_data);
1289 1515
1290 /* Enable the SSP clock */ 1516 /* Enable the SSP clock */
1291 clk_prepare_enable(ssp->clk); 1517 if (!pm_runtime_suspended(dev))
1518 clk_prepare_enable(ssp->clk);
1292 1519
1293 /* Restore LPSS private register bits */ 1520 /* Restore LPSS private register bits */
1294 lpss_ssp_setup(drv_data); 1521 lpss_ssp_setup(drv_data);
diff --git a/drivers/spi/spi-pxa2xx.h b/drivers/spi/spi-pxa2xx.h
index 5adc2a11c7bc..6bec59c90cd4 100644
--- a/drivers/spi/spi-pxa2xx.h
+++ b/drivers/spi/spi-pxa2xx.h
@@ -93,6 +93,7 @@ struct driver_data {
93struct chip_data { 93struct chip_data {
94 u32 cr0; 94 u32 cr0;
95 u32 cr1; 95 u32 cr1;
96 u32 dds_rate;
96 u32 psp; 97 u32 psp;
97 u32 timeout; 98 u32 timeout;
98 u8 n_bytes; 99 u8 n_bytes;
@@ -126,6 +127,7 @@ DEFINE_SSP_REG(SSCR1, 0x04)
126DEFINE_SSP_REG(SSSR, 0x08) 127DEFINE_SSP_REG(SSSR, 0x08)
127DEFINE_SSP_REG(SSITR, 0x0c) 128DEFINE_SSP_REG(SSITR, 0x0c)
128DEFINE_SSP_REG(SSDR, 0x10) 129DEFINE_SSP_REG(SSDR, 0x10)
130DEFINE_SSP_REG(DDS_RATE, 0x28) /* DDS Clock Rate */
129DEFINE_SSP_REG(SSTO, 0x28) 131DEFINE_SSP_REG(SSTO, 0x28)
130DEFINE_SSP_REG(SSPSP, 0x2c) 132DEFINE_SSP_REG(SSPSP, 0x2c)
131DEFINE_SSP_REG(SSITF, SSITF) 133DEFINE_SSP_REG(SSITF, SSITF)
@@ -141,18 +143,22 @@ DEFINE_SSP_REG(SSIRF, SSIRF)
141 143
142static inline int pxa25x_ssp_comp(struct driver_data *drv_data) 144static inline int pxa25x_ssp_comp(struct driver_data *drv_data)
143{ 145{
144 if (drv_data->ssp_type == PXA25x_SSP) 146 switch (drv_data->ssp_type) {
147 case PXA25x_SSP:
148 case CE4100_SSP:
149 case QUARK_X1000_SSP:
145 return 1; 150 return 1;
146 if (drv_data->ssp_type == CE4100_SSP) 151 default:
147 return 1; 152 return 0;
148 return 0; 153 }
149} 154}
150 155
151static inline void write_SSSR_CS(struct driver_data *drv_data, u32 val) 156static inline void write_SSSR_CS(struct driver_data *drv_data, u32 val)
152{ 157{
153 void __iomem *reg = drv_data->ioaddr; 158 void __iomem *reg = drv_data->ioaddr;
154 159
155 if (drv_data->ssp_type == CE4100_SSP) 160 if (drv_data->ssp_type == CE4100_SSP ||
161 drv_data->ssp_type == QUARK_X1000_SSP)
156 val |= read_SSSR(reg) & SSSR_ALT_FRM_MASK; 162 val |= read_SSSR(reg) & SSSR_ALT_FRM_MASK;
157 163
158 write_SSSR(val, reg); 164 write_SSSR(val, reg);
diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c
index 87bc16f491f0..80637e9406e2 100644
--- a/drivers/spi/spi-rockchip.c
+++ b/drivers/spi/spi-rockchip.c
@@ -749,8 +749,6 @@ static int rockchip_spi_remove(struct platform_device *pdev)
749 if (rs->dma_rx.ch) 749 if (rs->dma_rx.ch)
750 dma_release_channel(rs->dma_rx.ch); 750 dma_release_channel(rs->dma_rx.ch);
751 751
752 spi_master_put(master);
753
754 return 0; 752 return 0;
755} 753}
756 754
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index 480133ee1eb3..0f602cba1989 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -33,8 +33,9 @@
33 33
34#include <linux/platform_data/spi-s3c64xx.h> 34#include <linux/platform_data/spi-s3c64xx.h>
35 35
36#define MAX_SPI_PORTS 3 36#define MAX_SPI_PORTS 6
37#define S3C64XX_SPI_QUIRK_POLL (1 << 0) 37#define S3C64XX_SPI_QUIRK_POLL (1 << 0)
38#define S3C64XX_SPI_QUIRK_CS_AUTO (1 << 1)
38 39
39/* Registers and bit-fields */ 40/* Registers and bit-fields */
40 41
@@ -78,6 +79,7 @@
78 79
79#define S3C64XX_SPI_SLAVE_AUTO (1<<1) 80#define S3C64XX_SPI_SLAVE_AUTO (1<<1)
80#define S3C64XX_SPI_SLAVE_SIG_INACT (1<<0) 81#define S3C64XX_SPI_SLAVE_SIG_INACT (1<<0)
82#define S3C64XX_SPI_SLAVE_NSC_CNT_2 (2<<4)
81 83
82#define S3C64XX_SPI_INT_TRAILING_EN (1<<6) 84#define S3C64XX_SPI_INT_TRAILING_EN (1<<6)
83#define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5) 85#define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5)
@@ -344,16 +346,8 @@ static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
344 spi->dma_tx = sdd->tx_dma.ch; 346 spi->dma_tx = sdd->tx_dma.ch;
345 } 347 }
346 348
347 ret = pm_runtime_get_sync(&sdd->pdev->dev);
348 if (ret < 0) {
349 dev_err(dev, "Failed to enable device: %d\n", ret);
350 goto out_tx;
351 }
352
353 return 0; 349 return 0;
354 350
355out_tx:
356 dma_release_channel(sdd->tx_dma.ch);
357out_rx: 351out_rx:
358 dma_release_channel(sdd->rx_dma.ch); 352 dma_release_channel(sdd->rx_dma.ch);
359out: 353out:
@@ -370,7 +364,6 @@ static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi)
370 dma_release_channel(sdd->tx_dma.ch); 364 dma_release_channel(sdd->tx_dma.ch);
371 } 365 }
372 366
373 pm_runtime_put(&sdd->pdev->dev);
374 return 0; 367 return 0;
375} 368}
376 369
@@ -717,7 +710,12 @@ static int s3c64xx_spi_transfer_one(struct spi_master *master,
717 enable_datapath(sdd, spi, xfer, use_dma); 710 enable_datapath(sdd, spi, xfer, use_dma);
718 711
719 /* Start the signals */ 712 /* Start the signals */
720 writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL); 713 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
714 writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
715 else
716 writel(readl(sdd->regs + S3C64XX_SPI_SLAVE_SEL)
717 | S3C64XX_SPI_SLAVE_AUTO | S3C64XX_SPI_SLAVE_NSC_CNT_2,
718 sdd->regs + S3C64XX_SPI_SLAVE_SEL);
721 719
722 spin_unlock_irqrestore(&sdd->lock, flags); 720 spin_unlock_irqrestore(&sdd->lock, flags);
723 721
@@ -866,13 +864,15 @@ static int s3c64xx_spi_setup(struct spi_device *spi)
866 } 864 }
867 865
868 pm_runtime_put(&sdd->pdev->dev); 866 pm_runtime_put(&sdd->pdev->dev);
869 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL); 867 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
868 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
870 return 0; 869 return 0;
871 870
872setup_exit: 871setup_exit:
873 pm_runtime_put(&sdd->pdev->dev); 872 pm_runtime_put(&sdd->pdev->dev);
874 /* setup() returns with device de-selected */ 873 /* setup() returns with device de-selected */
875 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL); 874 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
875 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
876 876
877 if (gpio_is_valid(spi->cs_gpio)) 877 if (gpio_is_valid(spi->cs_gpio))
878 gpio_free(spi->cs_gpio); 878 gpio_free(spi->cs_gpio);
@@ -946,7 +946,8 @@ static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
946 946
947 sdd->cur_speed = 0; 947 sdd->cur_speed = 0;
948 948
949 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL); 949 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
950 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
950 951
951 /* Disable Interrupts - we use Polling if not DMA mode */ 952 /* Disable Interrupts - we use Polling if not DMA mode */
952 writel(0, regs + S3C64XX_SPI_INT_EN); 953 writel(0, regs + S3C64XX_SPI_INT_EN);
@@ -1341,6 +1342,15 @@ static struct s3c64xx_spi_port_config exynos5440_spi_port_config = {
1341 .quirks = S3C64XX_SPI_QUIRK_POLL, 1342 .quirks = S3C64XX_SPI_QUIRK_POLL,
1342}; 1343};
1343 1344
1345static struct s3c64xx_spi_port_config exynos7_spi_port_config = {
1346 .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F, 0x7F, 0x7F, 0x1ff},
1347 .rx_lvl_offset = 15,
1348 .tx_st_done = 25,
1349 .high_speed = true,
1350 .clk_from_cmu = true,
1351 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
1352};
1353
1344static struct platform_device_id s3c64xx_spi_driver_ids[] = { 1354static struct platform_device_id s3c64xx_spi_driver_ids[] = {
1345 { 1355 {
1346 .name = "s3c2443-spi", 1356 .name = "s3c2443-spi",
@@ -1374,6 +1384,9 @@ static const struct of_device_id s3c64xx_spi_dt_match[] = {
1374 { .compatible = "samsung,exynos5440-spi", 1384 { .compatible = "samsung,exynos5440-spi",
1375 .data = (void *)&exynos5440_spi_port_config, 1385 .data = (void *)&exynos5440_spi_port_config,
1376 }, 1386 },
1387 { .compatible = "samsung,exynos7-spi",
1388 .data = (void *)&exynos7_spi_port_config,
1389 },
1377 { }, 1390 { },
1378}; 1391};
1379MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match); 1392MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match);
diff --git a/drivers/spi/spi-sirf.c b/drivers/spi/spi-sirf.c
index 39e2c0a55a28..73a88b33f810 100644
--- a/drivers/spi/spi-sirf.c
+++ b/drivers/spi/spi-sirf.c
@@ -23,6 +23,7 @@
23#include <linux/dmaengine.h> 23#include <linux/dmaengine.h>
24#include <linux/dma-direction.h> 24#include <linux/dma-direction.h>
25#include <linux/dma-mapping.h> 25#include <linux/dma-mapping.h>
26#include <linux/reset.h>
26 27
27#define DRIVER_NAME "sirfsoc_spi" 28#define DRIVER_NAME "sirfsoc_spi"
28 29
@@ -134,6 +135,7 @@
134 ALIGNED(x->len) && (x->len < 2 * PAGE_SIZE)) 135 ALIGNED(x->len) && (x->len < 2 * PAGE_SIZE))
135 136
136#define SIRFSOC_MAX_CMD_BYTES 4 137#define SIRFSOC_MAX_CMD_BYTES 4
138#define SIRFSOC_SPI_DEFAULT_FRQ 1000000
137 139
138struct sirfsoc_spi { 140struct sirfsoc_spi {
139 struct spi_bitbang bitbang; 141 struct spi_bitbang bitbang;
@@ -562,9 +564,9 @@ spi_sirfsoc_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
562 564
563 sspi->word_width = DIV_ROUND_UP(bits_per_word, 8); 565 sspi->word_width = DIV_ROUND_UP(bits_per_word, 8);
564 txfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) | 566 txfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
565 sspi->word_width; 567 (sspi->word_width >> 1);
566 rxfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) | 568 rxfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
567 sspi->word_width; 569 (sspi->word_width >> 1);
568 570
569 if (!(spi->mode & SPI_CS_HIGH)) 571 if (!(spi->mode & SPI_CS_HIGH))
570 regval |= SIRFSOC_SPI_CS_IDLE_STAT; 572 regval |= SIRFSOC_SPI_CS_IDLE_STAT;
@@ -629,9 +631,6 @@ static int spi_sirfsoc_setup(struct spi_device *spi)
629{ 631{
630 struct sirfsoc_spi *sspi; 632 struct sirfsoc_spi *sspi;
631 633
632 if (!spi->max_speed_hz)
633 return -EINVAL;
634
635 sspi = spi_master_get_devdata(spi->master); 634 sspi = spi_master_get_devdata(spi->master);
636 635
637 if (spi->cs_gpio == -ENOENT) 636 if (spi->cs_gpio == -ENOENT)
@@ -649,6 +648,12 @@ static int spi_sirfsoc_probe(struct platform_device *pdev)
649 int irq; 648 int irq;
650 int i, ret; 649 int i, ret;
651 650
651 ret = device_reset(&pdev->dev);
652 if (ret) {
653 dev_err(&pdev->dev, "SPI reset failed!\n");
654 return ret;
655 }
656
652 master = spi_alloc_master(&pdev->dev, sizeof(*sspi)); 657 master = spi_alloc_master(&pdev->dev, sizeof(*sspi));
653 if (!master) { 658 if (!master) {
654 dev_err(&pdev->dev, "Unable to allocate SPI master\n"); 659 dev_err(&pdev->dev, "Unable to allocate SPI master\n");
@@ -683,6 +688,7 @@ static int spi_sirfsoc_probe(struct platform_device *pdev)
683 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH; 688 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH;
684 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(12) | 689 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(12) |
685 SPI_BPW_MASK(16) | SPI_BPW_MASK(32); 690 SPI_BPW_MASK(16) | SPI_BPW_MASK(32);
691 master->max_speed_hz = SIRFSOC_SPI_DEFAULT_FRQ;
686 sspi->bitbang.master->dev.of_node = pdev->dev.of_node; 692 sspi->bitbang.master->dev.of_node = pdev->dev.of_node;
687 693
688 /* request DMA channels */ 694 /* request DMA channels */
diff --git a/drivers/spi/spi-txx9.c b/drivers/spi/spi-txx9.c
index 2501a8373e89..f2ab827c81bb 100644
--- a/drivers/spi/spi-txx9.c
+++ b/drivers/spi/spi-txx9.c
@@ -402,8 +402,7 @@ exit_busy:
402exit: 402exit:
403 if (c->workqueue) 403 if (c->workqueue)
404 destroy_workqueue(c->workqueue); 404 destroy_workqueue(c->workqueue);
405 if (c->clk) 405 clk_disable(c->clk);
406 clk_disable(c->clk);
407 spi_master_put(master); 406 spi_master_put(master);
408 return ret; 407 return ret;
409} 408}
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index ebcb33df2eb2..da7e6225b8f6 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -615,13 +615,13 @@ static int spi_map_buf(struct spi_master *master, struct device *dev,
615 sg_free_table(sgt); 615 sg_free_table(sgt);
616 return -ENOMEM; 616 return -ENOMEM;
617 } 617 }
618 sg_buf = page_address(vm_page) + 618 sg_set_page(&sgt->sgl[i], vm_page,
619 ((size_t)buf & ~PAGE_MASK); 619 min, offset_in_page(buf));
620 } else { 620 } else {
621 sg_buf = buf; 621 sg_buf = buf;
622 sg_set_buf(&sgt->sgl[i], sg_buf, min);
622 } 623 }
623 624
624 sg_set_buf(&sgt->sgl[i], sg_buf, min);
625 625
626 buf += min; 626 buf += min;
627 len -= min; 627 len -= min;
@@ -1001,7 +1001,7 @@ static int spi_init_queue(struct spi_master *master)
1001 dev_name(&master->dev)); 1001 dev_name(&master->dev));
1002 if (IS_ERR(master->kworker_task)) { 1002 if (IS_ERR(master->kworker_task)) {
1003 dev_err(&master->dev, "failed to create message pump task\n"); 1003 dev_err(&master->dev, "failed to create message pump task\n");
1004 return -ENOMEM; 1004 return PTR_ERR(master->kworker_task);
1005 } 1005 }
1006 init_kthread_work(&master->pump_messages, spi_pump_messages); 1006 init_kthread_work(&master->pump_messages, spi_pump_messages);
1007 1007
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-15 05:52:12 -0500