diff options
Diffstat (limited to 'drivers/spi')
-rw-r--r-- | drivers/spi/Makefile | 2 | ||||
-rw-r--r-- | drivers/spi/amba-pl022.c | 10 | ||||
-rw-r--r-- | drivers/spi/pxa2xx_spi.c | 30 | ||||
-rw-r--r-- | drivers/spi/spi_imx.c (renamed from drivers/spi/mxc_spi.c) | 383 | ||||
-rw-r--r-- | drivers/spi/spi_stmp.c | 2 | ||||
-rw-r--r-- | drivers/spi/spidev.c | 2 |
6 files changed, 213 insertions, 216 deletions
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 6d7a3f82c54b..21a118269cac 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile | |||
@@ -17,7 +17,7 @@ obj-$(CONFIG_SPI_BITBANG) += spi_bitbang.o | |||
17 | obj-$(CONFIG_SPI_AU1550) += au1550_spi.o | 17 | obj-$(CONFIG_SPI_AU1550) += au1550_spi.o |
18 | obj-$(CONFIG_SPI_BUTTERFLY) += spi_butterfly.o | 18 | obj-$(CONFIG_SPI_BUTTERFLY) += spi_butterfly.o |
19 | obj-$(CONFIG_SPI_GPIO) += spi_gpio.o | 19 | obj-$(CONFIG_SPI_GPIO) += spi_gpio.o |
20 | obj-$(CONFIG_SPI_IMX) += mxc_spi.o | 20 | obj-$(CONFIG_SPI_IMX) += spi_imx.o |
21 | obj-$(CONFIG_SPI_LM70_LLP) += spi_lm70llp.o | 21 | obj-$(CONFIG_SPI_LM70_LLP) += spi_lm70llp.o |
22 | obj-$(CONFIG_SPI_PXA2XX) += pxa2xx_spi.o | 22 | obj-$(CONFIG_SPI_PXA2XX) += pxa2xx_spi.o |
23 | obj-$(CONFIG_SPI_OMAP_UWIRE) += omap_uwire.o | 23 | obj-$(CONFIG_SPI_OMAP_UWIRE) += omap_uwire.o |
diff --git a/drivers/spi/amba-pl022.c b/drivers/spi/amba-pl022.c index c0f950a7cbec..ff5bbb9c43c9 100644 --- a/drivers/spi/amba-pl022.c +++ b/drivers/spi/amba-pl022.c | |||
@@ -532,7 +532,7 @@ static void restore_state(struct pl022 *pl022) | |||
532 | GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \ | 532 | GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \ |
533 | GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP, 5) | \ | 533 | GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP, 5) | \ |
534 | GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ | 534 | GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ |
535 | GEN_MASK_BITS(SSP_CLK_FALLING_EDGE, SSP_CR0_MASK_SPH, 7) | \ | 535 | GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ |
536 | GEN_MASK_BITS(NMDK_SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \ | 536 | GEN_MASK_BITS(NMDK_SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \ |
537 | GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS, 16) | \ | 537 | GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS, 16) | \ |
538 | GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 21) \ | 538 | GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 21) \ |
@@ -1247,8 +1247,8 @@ static int verify_controller_parameters(struct pl022 *pl022, | |||
1247 | return -EINVAL; | 1247 | return -EINVAL; |
1248 | } | 1248 | } |
1249 | if (chip_info->iface == SSP_INTERFACE_MOTOROLA_SPI) { | 1249 | if (chip_info->iface == SSP_INTERFACE_MOTOROLA_SPI) { |
1250 | if ((chip_info->clk_phase != SSP_CLK_RISING_EDGE) | 1250 | if ((chip_info->clk_phase != SSP_CLK_FIRST_EDGE) |
1251 | && (chip_info->clk_phase != SSP_CLK_FALLING_EDGE)) { | 1251 | && (chip_info->clk_phase != SSP_CLK_SECOND_EDGE)) { |
1252 | dev_err(chip_info->dev, | 1252 | dev_err(chip_info->dev, |
1253 | "Clock Phase is configured incorrectly\n"); | 1253 | "Clock Phase is configured incorrectly\n"); |
1254 | return -EINVAL; | 1254 | return -EINVAL; |
@@ -1485,7 +1485,7 @@ static int pl022_setup(struct spi_device *spi) | |||
1485 | chip_info->data_size = SSP_DATA_BITS_12; | 1485 | chip_info->data_size = SSP_DATA_BITS_12; |
1486 | chip_info->rx_lev_trig = SSP_RX_1_OR_MORE_ELEM; | 1486 | chip_info->rx_lev_trig = SSP_RX_1_OR_MORE_ELEM; |
1487 | chip_info->tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC; | 1487 | chip_info->tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC; |
1488 | chip_info->clk_phase = SSP_CLK_FALLING_EDGE; | 1488 | chip_info->clk_phase = SSP_CLK_SECOND_EDGE; |
1489 | chip_info->clk_pol = SSP_CLK_POL_IDLE_LOW; | 1489 | chip_info->clk_pol = SSP_CLK_POL_IDLE_LOW; |
1490 | chip_info->ctrl_len = SSP_BITS_8; | 1490 | chip_info->ctrl_len = SSP_BITS_8; |
1491 | chip_info->wait_state = SSP_MWIRE_WAIT_ZERO; | 1491 | chip_info->wait_state = SSP_MWIRE_WAIT_ZERO; |
@@ -1826,7 +1826,7 @@ static struct amba_id pl022_ids[] = { | |||
1826 | * ST Micro derivative, this has 32bit wide | 1826 | * ST Micro derivative, this has 32bit wide |
1827 | * and 32 locations deep TX/RX FIFO | 1827 | * and 32 locations deep TX/RX FIFO |
1828 | */ | 1828 | */ |
1829 | .id = 0x00108022, | 1829 | .id = 0x01080022, |
1830 | .mask = 0xffffffff, | 1830 | .mask = 0xffffffff, |
1831 | .data = &vendor_st, | 1831 | .data = &vendor_st, |
1832 | }, | 1832 | }, |
diff --git a/drivers/spi/pxa2xx_spi.c b/drivers/spi/pxa2xx_spi.c index 31dd56f0dae9..c8c2b693ffac 100644 --- a/drivers/spi/pxa2xx_spi.c +++ b/drivers/spi/pxa2xx_spi.c | |||
@@ -1668,10 +1668,9 @@ static void pxa2xx_spi_shutdown(struct platform_device *pdev) | |||
1668 | } | 1668 | } |
1669 | 1669 | ||
1670 | #ifdef CONFIG_PM | 1670 | #ifdef CONFIG_PM |
1671 | 1671 | static int pxa2xx_spi_suspend(struct device *dev) | |
1672 | static int pxa2xx_spi_suspend(struct platform_device *pdev, pm_message_t state) | ||
1673 | { | 1672 | { |
1674 | struct driver_data *drv_data = platform_get_drvdata(pdev); | 1673 | struct driver_data *drv_data = dev_get_drvdata(dev); |
1675 | struct ssp_device *ssp = drv_data->ssp; | 1674 | struct ssp_device *ssp = drv_data->ssp; |
1676 | int status = 0; | 1675 | int status = 0; |
1677 | 1676 | ||
@@ -1684,9 +1683,9 @@ static int pxa2xx_spi_suspend(struct platform_device *pdev, pm_message_t state) | |||
1684 | return 0; | 1683 | return 0; |
1685 | } | 1684 | } |
1686 | 1685 | ||
1687 | static int pxa2xx_spi_resume(struct platform_device *pdev) | 1686 | static int pxa2xx_spi_resume(struct device *dev) |
1688 | { | 1687 | { |
1689 | struct driver_data *drv_data = platform_get_drvdata(pdev); | 1688 | struct driver_data *drv_data = dev_get_drvdata(dev); |
1690 | struct ssp_device *ssp = drv_data->ssp; | 1689 | struct ssp_device *ssp = drv_data->ssp; |
1691 | int status = 0; | 1690 | int status = 0; |
1692 | 1691 | ||
@@ -1703,26 +1702,29 @@ static int pxa2xx_spi_resume(struct platform_device *pdev) | |||
1703 | /* Start the queue running */ | 1702 | /* Start the queue running */ |
1704 | status = start_queue(drv_data); | 1703 | status = start_queue(drv_data); |
1705 | if (status != 0) { | 1704 | if (status != 0) { |
1706 | dev_err(&pdev->dev, "problem starting queue (%d)\n", status); | 1705 | dev_err(dev, "problem starting queue (%d)\n", status); |
1707 | return status; | 1706 | return status; |
1708 | } | 1707 | } |
1709 | 1708 | ||
1710 | return 0; | 1709 | return 0; |
1711 | } | 1710 | } |
1712 | #else | 1711 | |
1713 | #define pxa2xx_spi_suspend NULL | 1712 | static struct dev_pm_ops pxa2xx_spi_pm_ops = { |
1714 | #define pxa2xx_spi_resume NULL | 1713 | .suspend = pxa2xx_spi_suspend, |
1715 | #endif /* CONFIG_PM */ | 1714 | .resume = pxa2xx_spi_resume, |
1715 | }; | ||
1716 | #endif | ||
1716 | 1717 | ||
1717 | static struct platform_driver driver = { | 1718 | static struct platform_driver driver = { |
1718 | .driver = { | 1719 | .driver = { |
1719 | .name = "pxa2xx-spi", | 1720 | .name = "pxa2xx-spi", |
1720 | .owner = THIS_MODULE, | 1721 | .owner = THIS_MODULE, |
1722 | #ifdef CONFIG_PM | ||
1723 | .pm = &pxa2xx_spi_pm_ops, | ||
1724 | #endif | ||
1721 | }, | 1725 | }, |
1722 | .remove = pxa2xx_spi_remove, | 1726 | .remove = pxa2xx_spi_remove, |
1723 | .shutdown = pxa2xx_spi_shutdown, | 1727 | .shutdown = pxa2xx_spi_shutdown, |
1724 | .suspend = pxa2xx_spi_suspend, | ||
1725 | .resume = pxa2xx_spi_resume, | ||
1726 | }; | 1728 | }; |
1727 | 1729 | ||
1728 | static int __init pxa2xx_spi_init(void) | 1730 | static int __init pxa2xx_spi_init(void) |
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/spi_imx.c index b1447236ae81..89c22efedfb0 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/spi_imx.c | |||
@@ -48,14 +48,14 @@ | |||
48 | #define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */ | 48 | #define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */ |
49 | #define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */ | 49 | #define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */ |
50 | 50 | ||
51 | struct mxc_spi_config { | 51 | struct spi_imx_config { |
52 | unsigned int speed_hz; | 52 | unsigned int speed_hz; |
53 | unsigned int bpw; | 53 | unsigned int bpw; |
54 | unsigned int mode; | 54 | unsigned int mode; |
55 | int cs; | 55 | int cs; |
56 | }; | 56 | }; |
57 | 57 | ||
58 | struct mxc_spi_data { | 58 | struct spi_imx_data { |
59 | struct spi_bitbang bitbang; | 59 | struct spi_bitbang bitbang; |
60 | 60 | ||
61 | struct completion xfer_done; | 61 | struct completion xfer_done; |
@@ -66,43 +66,43 @@ struct mxc_spi_data { | |||
66 | int *chipselect; | 66 | int *chipselect; |
67 | 67 | ||
68 | unsigned int count; | 68 | unsigned int count; |
69 | void (*tx)(struct mxc_spi_data *); | 69 | void (*tx)(struct spi_imx_data *); |
70 | void (*rx)(struct mxc_spi_data *); | 70 | void (*rx)(struct spi_imx_data *); |
71 | void *rx_buf; | 71 | void *rx_buf; |
72 | const void *tx_buf; | 72 | const void *tx_buf; |
73 | unsigned int txfifo; /* number of words pushed in tx FIFO */ | 73 | unsigned int txfifo; /* number of words pushed in tx FIFO */ |
74 | 74 | ||
75 | /* SoC specific functions */ | 75 | /* SoC specific functions */ |
76 | void (*intctrl)(struct mxc_spi_data *, int); | 76 | void (*intctrl)(struct spi_imx_data *, int); |
77 | int (*config)(struct mxc_spi_data *, struct mxc_spi_config *); | 77 | int (*config)(struct spi_imx_data *, struct spi_imx_config *); |
78 | void (*trigger)(struct mxc_spi_data *); | 78 | void (*trigger)(struct spi_imx_data *); |
79 | int (*rx_available)(struct mxc_spi_data *); | 79 | int (*rx_available)(struct spi_imx_data *); |
80 | }; | 80 | }; |
81 | 81 | ||
82 | #define MXC_SPI_BUF_RX(type) \ | 82 | #define MXC_SPI_BUF_RX(type) \ |
83 | static void mxc_spi_buf_rx_##type(struct mxc_spi_data *mxc_spi) \ | 83 | static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \ |
84 | { \ | 84 | { \ |
85 | unsigned int val = readl(mxc_spi->base + MXC_CSPIRXDATA); \ | 85 | unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \ |
86 | \ | 86 | \ |
87 | if (mxc_spi->rx_buf) { \ | 87 | if (spi_imx->rx_buf) { \ |
88 | *(type *)mxc_spi->rx_buf = val; \ | 88 | *(type *)spi_imx->rx_buf = val; \ |
89 | mxc_spi->rx_buf += sizeof(type); \ | 89 | spi_imx->rx_buf += sizeof(type); \ |
90 | } \ | 90 | } \ |
91 | } | 91 | } |
92 | 92 | ||
93 | #define MXC_SPI_BUF_TX(type) \ | 93 | #define MXC_SPI_BUF_TX(type) \ |
94 | static void mxc_spi_buf_tx_##type(struct mxc_spi_data *mxc_spi) \ | 94 | static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \ |
95 | { \ | 95 | { \ |
96 | type val = 0; \ | 96 | type val = 0; \ |
97 | \ | 97 | \ |
98 | if (mxc_spi->tx_buf) { \ | 98 | if (spi_imx->tx_buf) { \ |
99 | val = *(type *)mxc_spi->tx_buf; \ | 99 | val = *(type *)spi_imx->tx_buf; \ |
100 | mxc_spi->tx_buf += sizeof(type); \ | 100 | spi_imx->tx_buf += sizeof(type); \ |
101 | } \ | 101 | } \ |
102 | \ | 102 | \ |
103 | mxc_spi->count -= sizeof(type); \ | 103 | spi_imx->count -= sizeof(type); \ |
104 | \ | 104 | \ |
105 | writel(val, mxc_spi->base + MXC_CSPITXDATA); \ | 105 | writel(val, spi_imx->base + MXC_CSPITXDATA); \ |
106 | } | 106 | } |
107 | 107 | ||
108 | MXC_SPI_BUF_RX(u8) | 108 | MXC_SPI_BUF_RX(u8) |
@@ -119,7 +119,7 @@ static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192, | |||
119 | 256, 384, 512, 768, 1024}; | 119 | 256, 384, 512, 768, 1024}; |
120 | 120 | ||
121 | /* MX21, MX27 */ | 121 | /* MX21, MX27 */ |
122 | static unsigned int mxc_spi_clkdiv_1(unsigned int fin, | 122 | static unsigned int spi_imx_clkdiv_1(unsigned int fin, |
123 | unsigned int fspi) | 123 | unsigned int fspi) |
124 | { | 124 | { |
125 | int i, max; | 125 | int i, max; |
@@ -137,7 +137,7 @@ static unsigned int mxc_spi_clkdiv_1(unsigned int fin, | |||
137 | } | 137 | } |
138 | 138 | ||
139 | /* MX1, MX31, MX35 */ | 139 | /* MX1, MX31, MX35 */ |
140 | static unsigned int mxc_spi_clkdiv_2(unsigned int fin, | 140 | static unsigned int spi_imx_clkdiv_2(unsigned int fin, |
141 | unsigned int fspi) | 141 | unsigned int fspi) |
142 | { | 142 | { |
143 | int i, div = 4; | 143 | int i, div = 4; |
@@ -174,7 +174,7 @@ static unsigned int mxc_spi_clkdiv_2(unsigned int fin, | |||
174 | * the i.MX35 has a slightly different register layout for bits | 174 | * the i.MX35 has a slightly different register layout for bits |
175 | * we do not use here. | 175 | * we do not use here. |
176 | */ | 176 | */ |
177 | static void mx31_intctrl(struct mxc_spi_data *mxc_spi, int enable) | 177 | static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable) |
178 | { | 178 | { |
179 | unsigned int val = 0; | 179 | unsigned int val = 0; |
180 | 180 | ||
@@ -183,24 +183,24 @@ static void mx31_intctrl(struct mxc_spi_data *mxc_spi, int enable) | |||
183 | if (enable & MXC_INT_RR) | 183 | if (enable & MXC_INT_RR) |
184 | val |= MX31_INTREG_RREN; | 184 | val |= MX31_INTREG_RREN; |
185 | 185 | ||
186 | writel(val, mxc_spi->base + MXC_CSPIINT); | 186 | writel(val, spi_imx->base + MXC_CSPIINT); |
187 | } | 187 | } |
188 | 188 | ||
189 | static void mx31_trigger(struct mxc_spi_data *mxc_spi) | 189 | static void mx31_trigger(struct spi_imx_data *spi_imx) |
190 | { | 190 | { |
191 | unsigned int reg; | 191 | unsigned int reg; |
192 | 192 | ||
193 | reg = readl(mxc_spi->base + MXC_CSPICTRL); | 193 | reg = readl(spi_imx->base + MXC_CSPICTRL); |
194 | reg |= MX31_CSPICTRL_XCH; | 194 | reg |= MX31_CSPICTRL_XCH; |
195 | writel(reg, mxc_spi->base + MXC_CSPICTRL); | 195 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
196 | } | 196 | } |
197 | 197 | ||
198 | static int mx31_config(struct mxc_spi_data *mxc_spi, | 198 | static int mx31_config(struct spi_imx_data *spi_imx, |
199 | struct mxc_spi_config *config) | 199 | struct spi_imx_config *config) |
200 | { | 200 | { |
201 | unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER; | 201 | unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER; |
202 | 202 | ||
203 | reg |= mxc_spi_clkdiv_2(mxc_spi->spi_clk, config->speed_hz) << | 203 | reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) << |
204 | MX31_CSPICTRL_DR_SHIFT; | 204 | MX31_CSPICTRL_DR_SHIFT; |
205 | 205 | ||
206 | if (cpu_is_mx31()) | 206 | if (cpu_is_mx31()) |
@@ -223,14 +223,14 @@ static int mx31_config(struct mxc_spi_data *mxc_spi, | |||
223 | reg |= (config->cs + 32) << MX35_CSPICTRL_CS_SHIFT; | 223 | reg |= (config->cs + 32) << MX35_CSPICTRL_CS_SHIFT; |
224 | } | 224 | } |
225 | 225 | ||
226 | writel(reg, mxc_spi->base + MXC_CSPICTRL); | 226 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
227 | 227 | ||
228 | return 0; | 228 | return 0; |
229 | } | 229 | } |
230 | 230 | ||
231 | static int mx31_rx_available(struct mxc_spi_data *mxc_spi) | 231 | static int mx31_rx_available(struct spi_imx_data *spi_imx) |
232 | { | 232 | { |
233 | return readl(mxc_spi->base + MX31_CSPISTATUS) & MX31_STATUS_RR; | 233 | return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR; |
234 | } | 234 | } |
235 | 235 | ||
236 | #define MX27_INTREG_RR (1 << 4) | 236 | #define MX27_INTREG_RR (1 << 4) |
@@ -246,7 +246,7 @@ static int mx31_rx_available(struct mxc_spi_data *mxc_spi) | |||
246 | #define MX27_CSPICTRL_DR_SHIFT 14 | 246 | #define MX27_CSPICTRL_DR_SHIFT 14 |
247 | #define MX27_CSPICTRL_CS_SHIFT 19 | 247 | #define MX27_CSPICTRL_CS_SHIFT 19 |
248 | 248 | ||
249 | static void mx27_intctrl(struct mxc_spi_data *mxc_spi, int enable) | 249 | static void mx27_intctrl(struct spi_imx_data *spi_imx, int enable) |
250 | { | 250 | { |
251 | unsigned int val = 0; | 251 | unsigned int val = 0; |
252 | 252 | ||
@@ -255,24 +255,24 @@ static void mx27_intctrl(struct mxc_spi_data *mxc_spi, int enable) | |||
255 | if (enable & MXC_INT_RR) | 255 | if (enable & MXC_INT_RR) |
256 | val |= MX27_INTREG_RREN; | 256 | val |= MX27_INTREG_RREN; |
257 | 257 | ||
258 | writel(val, mxc_spi->base + MXC_CSPIINT); | 258 | writel(val, spi_imx->base + MXC_CSPIINT); |
259 | } | 259 | } |
260 | 260 | ||
261 | static void mx27_trigger(struct mxc_spi_data *mxc_spi) | 261 | static void mx27_trigger(struct spi_imx_data *spi_imx) |
262 | { | 262 | { |
263 | unsigned int reg; | 263 | unsigned int reg; |
264 | 264 | ||
265 | reg = readl(mxc_spi->base + MXC_CSPICTRL); | 265 | reg = readl(spi_imx->base + MXC_CSPICTRL); |
266 | reg |= MX27_CSPICTRL_XCH; | 266 | reg |= MX27_CSPICTRL_XCH; |
267 | writel(reg, mxc_spi->base + MXC_CSPICTRL); | 267 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
268 | } | 268 | } |
269 | 269 | ||
270 | static int mx27_config(struct mxc_spi_data *mxc_spi, | 270 | static int mx27_config(struct spi_imx_data *spi_imx, |
271 | struct mxc_spi_config *config) | 271 | struct spi_imx_config *config) |
272 | { | 272 | { |
273 | unsigned int reg = MX27_CSPICTRL_ENABLE | MX27_CSPICTRL_MASTER; | 273 | unsigned int reg = MX27_CSPICTRL_ENABLE | MX27_CSPICTRL_MASTER; |
274 | 274 | ||
275 | reg |= mxc_spi_clkdiv_1(mxc_spi->spi_clk, config->speed_hz) << | 275 | reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz) << |
276 | MX27_CSPICTRL_DR_SHIFT; | 276 | MX27_CSPICTRL_DR_SHIFT; |
277 | reg |= config->bpw - 1; | 277 | reg |= config->bpw - 1; |
278 | 278 | ||
@@ -285,14 +285,14 @@ static int mx27_config(struct mxc_spi_data *mxc_spi, | |||
285 | if (config->cs < 0) | 285 | if (config->cs < 0) |
286 | reg |= (config->cs + 32) << MX27_CSPICTRL_CS_SHIFT; | 286 | reg |= (config->cs + 32) << MX27_CSPICTRL_CS_SHIFT; |
287 | 287 | ||
288 | writel(reg, mxc_spi->base + MXC_CSPICTRL); | 288 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
289 | 289 | ||
290 | return 0; | 290 | return 0; |
291 | } | 291 | } |
292 | 292 | ||
293 | static int mx27_rx_available(struct mxc_spi_data *mxc_spi) | 293 | static int mx27_rx_available(struct spi_imx_data *spi_imx) |
294 | { | 294 | { |
295 | return readl(mxc_spi->base + MXC_CSPIINT) & MX27_INTREG_RR; | 295 | return readl(spi_imx->base + MXC_CSPIINT) & MX27_INTREG_RR; |
296 | } | 296 | } |
297 | 297 | ||
298 | #define MX1_INTREG_RR (1 << 3) | 298 | #define MX1_INTREG_RR (1 << 3) |
@@ -306,7 +306,7 @@ static int mx27_rx_available(struct mxc_spi_data *mxc_spi) | |||
306 | #define MX1_CSPICTRL_MASTER (1 << 10) | 306 | #define MX1_CSPICTRL_MASTER (1 << 10) |
307 | #define MX1_CSPICTRL_DR_SHIFT 13 | 307 | #define MX1_CSPICTRL_DR_SHIFT 13 |
308 | 308 | ||
309 | static void mx1_intctrl(struct mxc_spi_data *mxc_spi, int enable) | 309 | static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable) |
310 | { | 310 | { |
311 | unsigned int val = 0; | 311 | unsigned int val = 0; |
312 | 312 | ||
@@ -315,24 +315,24 @@ static void mx1_intctrl(struct mxc_spi_data *mxc_spi, int enable) | |||
315 | if (enable & MXC_INT_RR) | 315 | if (enable & MXC_INT_RR) |
316 | val |= MX1_INTREG_RREN; | 316 | val |= MX1_INTREG_RREN; |
317 | 317 | ||
318 | writel(val, mxc_spi->base + MXC_CSPIINT); | 318 | writel(val, spi_imx->base + MXC_CSPIINT); |
319 | } | 319 | } |
320 | 320 | ||
321 | static void mx1_trigger(struct mxc_spi_data *mxc_spi) | 321 | static void mx1_trigger(struct spi_imx_data *spi_imx) |
322 | { | 322 | { |
323 | unsigned int reg; | 323 | unsigned int reg; |
324 | 324 | ||
325 | reg = readl(mxc_spi->base + MXC_CSPICTRL); | 325 | reg = readl(spi_imx->base + MXC_CSPICTRL); |
326 | reg |= MX1_CSPICTRL_XCH; | 326 | reg |= MX1_CSPICTRL_XCH; |
327 | writel(reg, mxc_spi->base + MXC_CSPICTRL); | 327 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
328 | } | 328 | } |
329 | 329 | ||
330 | static int mx1_config(struct mxc_spi_data *mxc_spi, | 330 | static int mx1_config(struct spi_imx_data *spi_imx, |
331 | struct mxc_spi_config *config) | 331 | struct spi_imx_config *config) |
332 | { | 332 | { |
333 | unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER; | 333 | unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER; |
334 | 334 | ||
335 | reg |= mxc_spi_clkdiv_2(mxc_spi->spi_clk, config->speed_hz) << | 335 | reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) << |
336 | MX1_CSPICTRL_DR_SHIFT; | 336 | MX1_CSPICTRL_DR_SHIFT; |
337 | reg |= config->bpw - 1; | 337 | reg |= config->bpw - 1; |
338 | 338 | ||
@@ -341,156 +341,151 @@ static int mx1_config(struct mxc_spi_data *mxc_spi, | |||
341 | if (config->mode & SPI_CPOL) | 341 | if (config->mode & SPI_CPOL) |
342 | reg |= MX1_CSPICTRL_POL; | 342 | reg |= MX1_CSPICTRL_POL; |
343 | 343 | ||
344 | writel(reg, mxc_spi->base + MXC_CSPICTRL); | 344 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
345 | 345 | ||
346 | return 0; | 346 | return 0; |
347 | } | 347 | } |
348 | 348 | ||
349 | static int mx1_rx_available(struct mxc_spi_data *mxc_spi) | 349 | static int mx1_rx_available(struct spi_imx_data *spi_imx) |
350 | { | 350 | { |
351 | return readl(mxc_spi->base + MXC_CSPIINT) & MX1_INTREG_RR; | 351 | return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR; |
352 | } | 352 | } |
353 | 353 | ||
354 | static void mxc_spi_chipselect(struct spi_device *spi, int is_active) | 354 | static void spi_imx_chipselect(struct spi_device *spi, int is_active) |
355 | { | 355 | { |
356 | struct mxc_spi_data *mxc_spi = spi_master_get_devdata(spi->master); | 356 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
357 | unsigned int cs = 0; | 357 | int gpio = spi_imx->chipselect[spi->chip_select]; |
358 | int gpio = mxc_spi->chipselect[spi->chip_select]; | 358 | int active = is_active != BITBANG_CS_INACTIVE; |
359 | struct mxc_spi_config config; | 359 | int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH); |
360 | 360 | ||
361 | if (spi->mode & SPI_CS_HIGH) | 361 | if (gpio < 0) |
362 | cs = 1; | ||
363 | |||
364 | if (is_active == BITBANG_CS_INACTIVE) { | ||
365 | if (gpio >= 0) | ||
366 | gpio_set_value(gpio, !cs); | ||
367 | return; | 362 | return; |
368 | } | ||
369 | |||
370 | config.bpw = spi->bits_per_word; | ||
371 | config.speed_hz = spi->max_speed_hz; | ||
372 | config.mode = spi->mode; | ||
373 | config.cs = mxc_spi->chipselect[spi->chip_select]; | ||
374 | |||
375 | mxc_spi->config(mxc_spi, &config); | ||
376 | |||
377 | /* Initialize the functions for transfer */ | ||
378 | if (config.bpw <= 8) { | ||
379 | mxc_spi->rx = mxc_spi_buf_rx_u8; | ||
380 | mxc_spi->tx = mxc_spi_buf_tx_u8; | ||
381 | } else if (config.bpw <= 16) { | ||
382 | mxc_spi->rx = mxc_spi_buf_rx_u16; | ||
383 | mxc_spi->tx = mxc_spi_buf_tx_u16; | ||
384 | } else if (config.bpw <= 32) { | ||
385 | mxc_spi->rx = mxc_spi_buf_rx_u32; | ||
386 | mxc_spi->tx = mxc_spi_buf_tx_u32; | ||
387 | } else | ||
388 | BUG(); | ||
389 | 363 | ||
390 | if (gpio >= 0) | 364 | gpio_set_value(gpio, dev_is_lowactive ^ active); |
391 | gpio_set_value(gpio, cs); | ||
392 | |||
393 | return; | ||
394 | } | 365 | } |
395 | 366 | ||
396 | static void mxc_spi_push(struct mxc_spi_data *mxc_spi) | 367 | static void spi_imx_push(struct spi_imx_data *spi_imx) |
397 | { | 368 | { |
398 | while (mxc_spi->txfifo < 8) { | 369 | while (spi_imx->txfifo < 8) { |
399 | if (!mxc_spi->count) | 370 | if (!spi_imx->count) |
400 | break; | 371 | break; |
401 | mxc_spi->tx(mxc_spi); | 372 | spi_imx->tx(spi_imx); |
402 | mxc_spi->txfifo++; | 373 | spi_imx->txfifo++; |
403 | } | 374 | } |
404 | 375 | ||
405 | mxc_spi->trigger(mxc_spi); | 376 | spi_imx->trigger(spi_imx); |
406 | } | 377 | } |
407 | 378 | ||
408 | static irqreturn_t mxc_spi_isr(int irq, void *dev_id) | 379 | static irqreturn_t spi_imx_isr(int irq, void *dev_id) |
409 | { | 380 | { |
410 | struct mxc_spi_data *mxc_spi = dev_id; | 381 | struct spi_imx_data *spi_imx = dev_id; |
411 | 382 | ||
412 | while (mxc_spi->rx_available(mxc_spi)) { | 383 | while (spi_imx->rx_available(spi_imx)) { |
413 | mxc_spi->rx(mxc_spi); | 384 | spi_imx->rx(spi_imx); |
414 | mxc_spi->txfifo--; | 385 | spi_imx->txfifo--; |
415 | } | 386 | } |
416 | 387 | ||
417 | if (mxc_spi->count) { | 388 | if (spi_imx->count) { |
418 | mxc_spi_push(mxc_spi); | 389 | spi_imx_push(spi_imx); |
419 | return IRQ_HANDLED; | 390 | return IRQ_HANDLED; |
420 | } | 391 | } |
421 | 392 | ||
422 | if (mxc_spi->txfifo) { | 393 | if (spi_imx->txfifo) { |
423 | /* No data left to push, but still waiting for rx data, | 394 | /* No data left to push, but still waiting for rx data, |
424 | * enable receive data available interrupt. | 395 | * enable receive data available interrupt. |
425 | */ | 396 | */ |
426 | mxc_spi->intctrl(mxc_spi, MXC_INT_RR); | 397 | spi_imx->intctrl(spi_imx, MXC_INT_RR); |
427 | return IRQ_HANDLED; | 398 | return IRQ_HANDLED; |
428 | } | 399 | } |
429 | 400 | ||
430 | mxc_spi->intctrl(mxc_spi, 0); | 401 | spi_imx->intctrl(spi_imx, 0); |
431 | complete(&mxc_spi->xfer_done); | 402 | complete(&spi_imx->xfer_done); |
432 | 403 | ||
433 | return IRQ_HANDLED; | 404 | return IRQ_HANDLED; |
434 | } | 405 | } |
435 | 406 | ||
436 | static int mxc_spi_setupxfer(struct spi_device *spi, | 407 | static int spi_imx_setupxfer(struct spi_device *spi, |
437 | struct spi_transfer *t) | 408 | struct spi_transfer *t) |
438 | { | 409 | { |
439 | struct mxc_spi_data *mxc_spi = spi_master_get_devdata(spi->master); | 410 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
440 | struct mxc_spi_config config; | 411 | struct spi_imx_config config; |
441 | 412 | ||
442 | config.bpw = t ? t->bits_per_word : spi->bits_per_word; | 413 | config.bpw = t ? t->bits_per_word : spi->bits_per_word; |
443 | config.speed_hz = t ? t->speed_hz : spi->max_speed_hz; | 414 | config.speed_hz = t ? t->speed_hz : spi->max_speed_hz; |
444 | config.mode = spi->mode; | 415 | config.mode = spi->mode; |
416 | config.cs = spi_imx->chipselect[spi->chip_select]; | ||
417 | |||
418 | if (!config.speed_hz) | ||
419 | config.speed_hz = spi->max_speed_hz; | ||
420 | if (!config.bpw) | ||
421 | config.bpw = spi->bits_per_word; | ||
422 | if (!config.speed_hz) | ||
423 | config.speed_hz = spi->max_speed_hz; | ||
424 | |||
425 | /* Initialize the functions for transfer */ | ||
426 | if (config.bpw <= 8) { | ||
427 | spi_imx->rx = spi_imx_buf_rx_u8; | ||
428 | spi_imx->tx = spi_imx_buf_tx_u8; | ||
429 | } else if (config.bpw <= 16) { | ||
430 | spi_imx->rx = spi_imx_buf_rx_u16; | ||
431 | spi_imx->tx = spi_imx_buf_tx_u16; | ||
432 | } else if (config.bpw <= 32) { | ||
433 | spi_imx->rx = spi_imx_buf_rx_u32; | ||
434 | spi_imx->tx = spi_imx_buf_tx_u32; | ||
435 | } else | ||
436 | BUG(); | ||
445 | 437 | ||
446 | mxc_spi->config(mxc_spi, &config); | 438 | spi_imx->config(spi_imx, &config); |
447 | 439 | ||
448 | return 0; | 440 | return 0; |
449 | } | 441 | } |
450 | 442 | ||
451 | static int mxc_spi_transfer(struct spi_device *spi, | 443 | static int spi_imx_transfer(struct spi_device *spi, |
452 | struct spi_transfer *transfer) | 444 | struct spi_transfer *transfer) |
453 | { | 445 | { |
454 | struct mxc_spi_data *mxc_spi = spi_master_get_devdata(spi->master); | 446 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
455 | 447 | ||
456 | mxc_spi->tx_buf = transfer->tx_buf; | 448 | spi_imx->tx_buf = transfer->tx_buf; |
457 | mxc_spi->rx_buf = transfer->rx_buf; | 449 | spi_imx->rx_buf = transfer->rx_buf; |
458 | mxc_spi->count = transfer->len; | 450 | spi_imx->count = transfer->len; |
459 | mxc_spi->txfifo = 0; | 451 | spi_imx->txfifo = 0; |
460 | 452 | ||
461 | init_completion(&mxc_spi->xfer_done); | 453 | init_completion(&spi_imx->xfer_done); |
462 | 454 | ||
463 | mxc_spi_push(mxc_spi); | 455 | spi_imx_push(spi_imx); |
464 | 456 | ||
465 | mxc_spi->intctrl(mxc_spi, MXC_INT_TE); | 457 | spi_imx->intctrl(spi_imx, MXC_INT_TE); |
466 | 458 | ||
467 | wait_for_completion(&mxc_spi->xfer_done); | 459 | wait_for_completion(&spi_imx->xfer_done); |
468 | 460 | ||
469 | return transfer->len; | 461 | return transfer->len; |
470 | } | 462 | } |
471 | 463 | ||
472 | static int mxc_spi_setup(struct spi_device *spi) | 464 | static int spi_imx_setup(struct spi_device *spi) |
473 | { | 465 | { |
474 | if (!spi->bits_per_word) | 466 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
475 | spi->bits_per_word = 8; | 467 | int gpio = spi_imx->chipselect[spi->chip_select]; |
476 | 468 | ||
477 | pr_debug("%s: mode %d, %u bpw, %d hz\n", __func__, | 469 | pr_debug("%s: mode %d, %u bpw, %d hz\n", __func__, |
478 | spi->mode, spi->bits_per_word, spi->max_speed_hz); | 470 | spi->mode, spi->bits_per_word, spi->max_speed_hz); |
479 | 471 | ||
480 | mxc_spi_chipselect(spi, BITBANG_CS_INACTIVE); | 472 | if (gpio >= 0) |
473 | gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1); | ||
474 | |||
475 | spi_imx_chipselect(spi, BITBANG_CS_INACTIVE); | ||
481 | 476 | ||
482 | return 0; | 477 | return 0; |
483 | } | 478 | } |
484 | 479 | ||
485 | static void mxc_spi_cleanup(struct spi_device *spi) | 480 | static void spi_imx_cleanup(struct spi_device *spi) |
486 | { | 481 | { |
487 | } | 482 | } |
488 | 483 | ||
489 | static int __init mxc_spi_probe(struct platform_device *pdev) | 484 | static int __init spi_imx_probe(struct platform_device *pdev) |
490 | { | 485 | { |
491 | struct spi_imx_master *mxc_platform_info; | 486 | struct spi_imx_master *mxc_platform_info; |
492 | struct spi_master *master; | 487 | struct spi_master *master; |
493 | struct mxc_spi_data *mxc_spi; | 488 | struct spi_imx_data *spi_imx; |
494 | struct resource *res; | 489 | struct resource *res; |
495 | int i, ret; | 490 | int i, ret; |
496 | 491 | ||
@@ -500,7 +495,7 @@ static int __init mxc_spi_probe(struct platform_device *pdev) | |||
500 | return -EINVAL; | 495 | return -EINVAL; |
501 | } | 496 | } |
502 | 497 | ||
503 | master = spi_alloc_master(&pdev->dev, sizeof(struct mxc_spi_data)); | 498 | master = spi_alloc_master(&pdev->dev, sizeof(struct spi_imx_data)); |
504 | if (!master) | 499 | if (!master) |
505 | return -ENOMEM; | 500 | return -ENOMEM; |
506 | 501 | ||
@@ -509,32 +504,32 @@ static int __init mxc_spi_probe(struct platform_device *pdev) | |||
509 | master->bus_num = pdev->id; | 504 | master->bus_num = pdev->id; |
510 | master->num_chipselect = mxc_platform_info->num_chipselect; | 505 | master->num_chipselect = mxc_platform_info->num_chipselect; |
511 | 506 | ||
512 | mxc_spi = spi_master_get_devdata(master); | 507 | spi_imx = spi_master_get_devdata(master); |
513 | mxc_spi->bitbang.master = spi_master_get(master); | 508 | spi_imx->bitbang.master = spi_master_get(master); |
514 | mxc_spi->chipselect = mxc_platform_info->chipselect; | 509 | spi_imx->chipselect = mxc_platform_info->chipselect; |
515 | 510 | ||
516 | for (i = 0; i < master->num_chipselect; i++) { | 511 | for (i = 0; i < master->num_chipselect; i++) { |
517 | if (mxc_spi->chipselect[i] < 0) | 512 | if (spi_imx->chipselect[i] < 0) |
518 | continue; | 513 | continue; |
519 | ret = gpio_request(mxc_spi->chipselect[i], DRIVER_NAME); | 514 | ret = gpio_request(spi_imx->chipselect[i], DRIVER_NAME); |
520 | if (ret) { | 515 | if (ret) { |
521 | i--; | 516 | i--; |
522 | while (i > 0) | 517 | while (i > 0) |
523 | if (mxc_spi->chipselect[i] >= 0) | 518 | if (spi_imx->chipselect[i] >= 0) |
524 | gpio_free(mxc_spi->chipselect[i--]); | 519 | gpio_free(spi_imx->chipselect[i--]); |
525 | dev_err(&pdev->dev, "can't get cs gpios"); | 520 | dev_err(&pdev->dev, "can't get cs gpios"); |
526 | goto out_master_put; | 521 | goto out_master_put; |
527 | } | 522 | } |
528 | gpio_direction_output(mxc_spi->chipselect[i], 1); | ||
529 | } | 523 | } |
530 | 524 | ||
531 | mxc_spi->bitbang.chipselect = mxc_spi_chipselect; | 525 | spi_imx->bitbang.chipselect = spi_imx_chipselect; |
532 | mxc_spi->bitbang.setup_transfer = mxc_spi_setupxfer; | 526 | spi_imx->bitbang.setup_transfer = spi_imx_setupxfer; |
533 | mxc_spi->bitbang.txrx_bufs = mxc_spi_transfer; | 527 | spi_imx->bitbang.txrx_bufs = spi_imx_transfer; |
534 | mxc_spi->bitbang.master->setup = mxc_spi_setup; | 528 | spi_imx->bitbang.master->setup = spi_imx_setup; |
535 | mxc_spi->bitbang.master->cleanup = mxc_spi_cleanup; | 529 | spi_imx->bitbang.master->cleanup = spi_imx_cleanup; |
530 | spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; | ||
536 | 531 | ||
537 | init_completion(&mxc_spi->xfer_done); | 532 | init_completion(&spi_imx->xfer_done); |
538 | 533 | ||
539 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 534 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
540 | if (!res) { | 535 | if (!res) { |
@@ -549,58 +544,58 @@ static int __init mxc_spi_probe(struct platform_device *pdev) | |||
549 | goto out_gpio_free; | 544 | goto out_gpio_free; |
550 | } | 545 | } |
551 | 546 | ||
552 | mxc_spi->base = ioremap(res->start, resource_size(res)); | 547 | spi_imx->base = ioremap(res->start, resource_size(res)); |
553 | if (!mxc_spi->base) { | 548 | if (!spi_imx->base) { |
554 | ret = -EINVAL; | 549 | ret = -EINVAL; |
555 | goto out_release_mem; | 550 | goto out_release_mem; |
556 | } | 551 | } |
557 | 552 | ||
558 | mxc_spi->irq = platform_get_irq(pdev, 0); | 553 | spi_imx->irq = platform_get_irq(pdev, 0); |
559 | if (!mxc_spi->irq) { | 554 | if (!spi_imx->irq) { |
560 | ret = -EINVAL; | 555 | ret = -EINVAL; |
561 | goto out_iounmap; | 556 | goto out_iounmap; |
562 | } | 557 | } |
563 | 558 | ||
564 | ret = request_irq(mxc_spi->irq, mxc_spi_isr, 0, DRIVER_NAME, mxc_spi); | 559 | ret = request_irq(spi_imx->irq, spi_imx_isr, 0, DRIVER_NAME, spi_imx); |
565 | if (ret) { | 560 | if (ret) { |
566 | dev_err(&pdev->dev, "can't get irq%d: %d\n", mxc_spi->irq, ret); | 561 | dev_err(&pdev->dev, "can't get irq%d: %d\n", spi_imx->irq, ret); |
567 | goto out_iounmap; | 562 | goto out_iounmap; |
568 | } | 563 | } |
569 | 564 | ||
570 | if (cpu_is_mx31() || cpu_is_mx35()) { | 565 | if (cpu_is_mx31() || cpu_is_mx35()) { |
571 | mxc_spi->intctrl = mx31_intctrl; | 566 | spi_imx->intctrl = mx31_intctrl; |
572 | mxc_spi->config = mx31_config; | 567 | spi_imx->config = mx31_config; |
573 | mxc_spi->trigger = mx31_trigger; | 568 | spi_imx->trigger = mx31_trigger; |
574 | mxc_spi->rx_available = mx31_rx_available; | 569 | spi_imx->rx_available = mx31_rx_available; |
575 | } else if (cpu_is_mx27() || cpu_is_mx21()) { | 570 | } else if (cpu_is_mx27() || cpu_is_mx21()) { |
576 | mxc_spi->intctrl = mx27_intctrl; | 571 | spi_imx->intctrl = mx27_intctrl; |
577 | mxc_spi->config = mx27_config; | 572 | spi_imx->config = mx27_config; |
578 | mxc_spi->trigger = mx27_trigger; | 573 | spi_imx->trigger = mx27_trigger; |
579 | mxc_spi->rx_available = mx27_rx_available; | 574 | spi_imx->rx_available = mx27_rx_available; |
580 | } else if (cpu_is_mx1()) { | 575 | } else if (cpu_is_mx1()) { |
581 | mxc_spi->intctrl = mx1_intctrl; | 576 | spi_imx->intctrl = mx1_intctrl; |
582 | mxc_spi->config = mx1_config; | 577 | spi_imx->config = mx1_config; |
583 | mxc_spi->trigger = mx1_trigger; | 578 | spi_imx->trigger = mx1_trigger; |
584 | mxc_spi->rx_available = mx1_rx_available; | 579 | spi_imx->rx_available = mx1_rx_available; |
585 | } else | 580 | } else |
586 | BUG(); | 581 | BUG(); |
587 | 582 | ||
588 | mxc_spi->clk = clk_get(&pdev->dev, NULL); | 583 | spi_imx->clk = clk_get(&pdev->dev, NULL); |
589 | if (IS_ERR(mxc_spi->clk)) { | 584 | if (IS_ERR(spi_imx->clk)) { |
590 | dev_err(&pdev->dev, "unable to get clock\n"); | 585 | dev_err(&pdev->dev, "unable to get clock\n"); |
591 | ret = PTR_ERR(mxc_spi->clk); | 586 | ret = PTR_ERR(spi_imx->clk); |
592 | goto out_free_irq; | 587 | goto out_free_irq; |
593 | } | 588 | } |
594 | 589 | ||
595 | clk_enable(mxc_spi->clk); | 590 | clk_enable(spi_imx->clk); |
596 | mxc_spi->spi_clk = clk_get_rate(mxc_spi->clk); | 591 | spi_imx->spi_clk = clk_get_rate(spi_imx->clk); |
597 | 592 | ||
598 | if (!cpu_is_mx31() || !cpu_is_mx35()) | 593 | if (!cpu_is_mx31() || !cpu_is_mx35()) |
599 | writel(1, mxc_spi->base + MXC_RESET); | 594 | writel(1, spi_imx->base + MXC_RESET); |
600 | 595 | ||
601 | mxc_spi->intctrl(mxc_spi, 0); | 596 | spi_imx->intctrl(spi_imx, 0); |
602 | 597 | ||
603 | ret = spi_bitbang_start(&mxc_spi->bitbang); | 598 | ret = spi_bitbang_start(&spi_imx->bitbang); |
604 | if (ret) { | 599 | if (ret) { |
605 | dev_err(&pdev->dev, "bitbang start failed with %d\n", ret); | 600 | dev_err(&pdev->dev, "bitbang start failed with %d\n", ret); |
606 | goto out_clk_put; | 601 | goto out_clk_put; |
@@ -611,18 +606,18 @@ static int __init mxc_spi_probe(struct platform_device *pdev) | |||
611 | return ret; | 606 | return ret; |
612 | 607 | ||
613 | out_clk_put: | 608 | out_clk_put: |
614 | clk_disable(mxc_spi->clk); | 609 | clk_disable(spi_imx->clk); |
615 | clk_put(mxc_spi->clk); | 610 | clk_put(spi_imx->clk); |
616 | out_free_irq: | 611 | out_free_irq: |
617 | free_irq(mxc_spi->irq, mxc_spi); | 612 | free_irq(spi_imx->irq, spi_imx); |
618 | out_iounmap: | 613 | out_iounmap: |
619 | iounmap(mxc_spi->base); | 614 | iounmap(spi_imx->base); |
620 | out_release_mem: | 615 | out_release_mem: |
621 | release_mem_region(res->start, resource_size(res)); | 616 | release_mem_region(res->start, resource_size(res)); |
622 | out_gpio_free: | 617 | out_gpio_free: |
623 | for (i = 0; i < master->num_chipselect; i++) | 618 | for (i = 0; i < master->num_chipselect; i++) |
624 | if (mxc_spi->chipselect[i] >= 0) | 619 | if (spi_imx->chipselect[i] >= 0) |
625 | gpio_free(mxc_spi->chipselect[i]); | 620 | gpio_free(spi_imx->chipselect[i]); |
626 | out_master_put: | 621 | out_master_put: |
627 | spi_master_put(master); | 622 | spi_master_put(master); |
628 | kfree(master); | 623 | kfree(master); |
@@ -630,24 +625,24 @@ out_master_put: | |||
630 | return ret; | 625 | return ret; |
631 | } | 626 | } |
632 | 627 | ||
633 | static int __exit mxc_spi_remove(struct platform_device *pdev) | 628 | static int __exit spi_imx_remove(struct platform_device *pdev) |
634 | { | 629 | { |
635 | struct spi_master *master = platform_get_drvdata(pdev); | 630 | struct spi_master *master = platform_get_drvdata(pdev); |
636 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 631 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
637 | struct mxc_spi_data *mxc_spi = spi_master_get_devdata(master); | 632 | struct spi_imx_data *spi_imx = spi_master_get_devdata(master); |
638 | int i; | 633 | int i; |
639 | 634 | ||
640 | spi_bitbang_stop(&mxc_spi->bitbang); | 635 | spi_bitbang_stop(&spi_imx->bitbang); |
641 | 636 | ||
642 | writel(0, mxc_spi->base + MXC_CSPICTRL); | 637 | writel(0, spi_imx->base + MXC_CSPICTRL); |
643 | clk_disable(mxc_spi->clk); | 638 | clk_disable(spi_imx->clk); |
644 | clk_put(mxc_spi->clk); | 639 | clk_put(spi_imx->clk); |
645 | free_irq(mxc_spi->irq, mxc_spi); | 640 | free_irq(spi_imx->irq, spi_imx); |
646 | iounmap(mxc_spi->base); | 641 | iounmap(spi_imx->base); |
647 | 642 | ||
648 | for (i = 0; i < master->num_chipselect; i++) | 643 | for (i = 0; i < master->num_chipselect; i++) |
649 | if (mxc_spi->chipselect[i] >= 0) | 644 | if (spi_imx->chipselect[i] >= 0) |
650 | gpio_free(mxc_spi->chipselect[i]); | 645 | gpio_free(spi_imx->chipselect[i]); |
651 | 646 | ||
652 | spi_master_put(master); | 647 | spi_master_put(master); |
653 | 648 | ||
@@ -658,27 +653,27 @@ static int __exit mxc_spi_remove(struct platform_device *pdev) | |||
658 | return 0; | 653 | return 0; |
659 | } | 654 | } |
660 | 655 | ||
661 | static struct platform_driver mxc_spi_driver = { | 656 | static struct platform_driver spi_imx_driver = { |
662 | .driver = { | 657 | .driver = { |
663 | .name = DRIVER_NAME, | 658 | .name = DRIVER_NAME, |
664 | .owner = THIS_MODULE, | 659 | .owner = THIS_MODULE, |
665 | }, | 660 | }, |
666 | .probe = mxc_spi_probe, | 661 | .probe = spi_imx_probe, |
667 | .remove = __exit_p(mxc_spi_remove), | 662 | .remove = __exit_p(spi_imx_remove), |
668 | }; | 663 | }; |
669 | 664 | ||
670 | static int __init mxc_spi_init(void) | 665 | static int __init spi_imx_init(void) |
671 | { | 666 | { |
672 | return platform_driver_register(&mxc_spi_driver); | 667 | return platform_driver_register(&spi_imx_driver); |
673 | } | 668 | } |
674 | 669 | ||
675 | static void __exit mxc_spi_exit(void) | 670 | static void __exit spi_imx_exit(void) |
676 | { | 671 | { |
677 | platform_driver_unregister(&mxc_spi_driver); | 672 | platform_driver_unregister(&spi_imx_driver); |
678 | } | 673 | } |
679 | 674 | ||
680 | module_init(mxc_spi_init); | 675 | module_init(spi_imx_init); |
681 | module_exit(mxc_spi_exit); | 676 | module_exit(spi_imx_exit); |
682 | 677 | ||
683 | MODULE_DESCRIPTION("SPI Master Controller driver"); | 678 | MODULE_DESCRIPTION("SPI Master Controller driver"); |
684 | MODULE_AUTHOR("Sascha Hauer, Pengutronix"); | 679 | MODULE_AUTHOR("Sascha Hauer, Pengutronix"); |
diff --git a/drivers/spi/spi_stmp.c b/drivers/spi/spi_stmp.c index d871dc23909c..2552bb364005 100644 --- a/drivers/spi/spi_stmp.c +++ b/drivers/spi/spi_stmp.c | |||
@@ -242,7 +242,7 @@ static int stmp_spi_txrx_dma(struct stmp_spi *ss, int cs, | |||
242 | wait_for_completion(&ss->done); | 242 | wait_for_completion(&ss->done); |
243 | 243 | ||
244 | if (!busy_wait(readl(ss->regs + HW_SSP_CTRL0) & BM_SSP_CTRL0_RUN)) | 244 | if (!busy_wait(readl(ss->regs + HW_SSP_CTRL0) & BM_SSP_CTRL0_RUN)) |
245 | status = ETIMEDOUT; | 245 | status = -ETIMEDOUT; |
246 | 246 | ||
247 | if (!dma_buf) | 247 | if (!dma_buf) |
248 | dma_unmap_single(ss->master_dev, spi_buf_dma, len, dir); | 248 | dma_unmap_single(ss->master_dev, spi_buf_dma, len, dir); |
diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c index f921bd1109e1..5d23983f02fc 100644 --- a/drivers/spi/spidev.c +++ b/drivers/spi/spidev.c | |||
@@ -537,7 +537,7 @@ static int spidev_release(struct inode *inode, struct file *filp) | |||
537 | return status; | 537 | return status; |
538 | } | 538 | } |
539 | 539 | ||
540 | static struct file_operations spidev_fops = { | 540 | static const struct file_operations spidev_fops = { |
541 | .owner = THIS_MODULE, | 541 | .owner = THIS_MODULE, |
542 | /* REVISIT switch to aio primitives, so that userspace | 542 | /* REVISIT switch to aio primitives, so that userspace |
543 | * gets more complete API coverage. It'll simplify things | 543 | * gets more complete API coverage. It'll simplify things |