diff options
Diffstat (limited to 'drivers/spi')
-rw-r--r-- | drivers/spi/Kconfig | 3 | ||||
-rw-r--r-- | drivers/spi/spi-tegra114.c | 18 | ||||
-rw-r--r-- | drivers/spi/spi-tegra20-sflash.c | 18 | ||||
-rw-r--r-- | drivers/spi/spi-tegra20-slink.c | 18 |
4 files changed, 42 insertions, 15 deletions
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index eb1f1ef5fa2e..9fc66e83c1a7 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig | |||
@@ -448,6 +448,7 @@ config SPI_MXS | |||
448 | config SPI_TEGRA114 | 448 | config SPI_TEGRA114 |
449 | tristate "NVIDIA Tegra114 SPI Controller" | 449 | tristate "NVIDIA Tegra114 SPI Controller" |
450 | depends on (ARCH_TEGRA && TEGRA20_APB_DMA) || COMPILE_TEST | 450 | depends on (ARCH_TEGRA && TEGRA20_APB_DMA) || COMPILE_TEST |
451 | depends on RESET_CONTROLLER | ||
451 | help | 452 | help |
452 | SPI driver for NVIDIA Tegra114 SPI Controller interface. This controller | 453 | SPI driver for NVIDIA Tegra114 SPI Controller interface. This controller |
453 | is different than the older SoCs SPI controller and also register interface | 454 | is different than the older SoCs SPI controller and also register interface |
@@ -456,6 +457,7 @@ config SPI_TEGRA114 | |||
456 | config SPI_TEGRA20_SFLASH | 457 | config SPI_TEGRA20_SFLASH |
457 | tristate "Nvidia Tegra20 Serial flash Controller" | 458 | tristate "Nvidia Tegra20 Serial flash Controller" |
458 | depends on ARCH_TEGRA || COMPILE_TEST | 459 | depends on ARCH_TEGRA || COMPILE_TEST |
460 | depends on RESET_CONTROLLER | ||
459 | help | 461 | help |
460 | SPI driver for Nvidia Tegra20 Serial flash Controller interface. | 462 | SPI driver for Nvidia Tegra20 Serial flash Controller interface. |
461 | The main usecase of this controller is to use spi flash as boot | 463 | The main usecase of this controller is to use spi flash as boot |
@@ -464,6 +466,7 @@ config SPI_TEGRA20_SFLASH | |||
464 | config SPI_TEGRA20_SLINK | 466 | config SPI_TEGRA20_SLINK |
465 | tristate "Nvidia Tegra20/Tegra30 SLINK Controller" | 467 | tristate "Nvidia Tegra20/Tegra30 SLINK Controller" |
466 | depends on (ARCH_TEGRA && TEGRA20_APB_DMA) || COMPILE_TEST | 468 | depends on (ARCH_TEGRA && TEGRA20_APB_DMA) || COMPILE_TEST |
469 | depends on RESET_CONTROLLER | ||
467 | help | 470 | help |
468 | SPI driver for Nvidia Tegra20/Tegra30 SLINK Controller interface. | 471 | SPI driver for Nvidia Tegra20/Tegra30 SLINK Controller interface. |
469 | 472 | ||
diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c index aaecfb3ebf58..f62e6e5e90e3 100644 --- a/drivers/spi/spi-tegra114.c +++ b/drivers/spi/spi-tegra114.c | |||
@@ -17,7 +17,6 @@ | |||
17 | */ | 17 | */ |
18 | 18 | ||
19 | #include <linux/clk.h> | 19 | #include <linux/clk.h> |
20 | #include <linux/clk/tegra.h> | ||
21 | #include <linux/completion.h> | 20 | #include <linux/completion.h> |
22 | #include <linux/delay.h> | 21 | #include <linux/delay.h> |
23 | #include <linux/dmaengine.h> | 22 | #include <linux/dmaengine.h> |
@@ -34,6 +33,7 @@ | |||
34 | #include <linux/pm_runtime.h> | 33 | #include <linux/pm_runtime.h> |
35 | #include <linux/of.h> | 34 | #include <linux/of.h> |
36 | #include <linux/of_device.h> | 35 | #include <linux/of_device.h> |
36 | #include <linux/reset.h> | ||
37 | #include <linux/spi/spi.h> | 37 | #include <linux/spi/spi.h> |
38 | 38 | ||
39 | #define SPI_COMMAND1 0x000 | 39 | #define SPI_COMMAND1 0x000 |
@@ -174,6 +174,7 @@ struct tegra_spi_data { | |||
174 | spinlock_t lock; | 174 | spinlock_t lock; |
175 | 175 | ||
176 | struct clk *clk; | 176 | struct clk *clk; |
177 | struct reset_control *rst; | ||
177 | void __iomem *base; | 178 | void __iomem *base; |
178 | phys_addr_t phys; | 179 | phys_addr_t phys; |
179 | unsigned irq; | 180 | unsigned irq; |
@@ -918,9 +919,9 @@ static irqreturn_t handle_cpu_based_xfer(struct tegra_spi_data *tspi) | |||
918 | tspi->status_reg); | 919 | tspi->status_reg); |
919 | dev_err(tspi->dev, "CpuXfer 0x%08x:0x%08x\n", | 920 | dev_err(tspi->dev, "CpuXfer 0x%08x:0x%08x\n", |
920 | tspi->command1_reg, tspi->dma_control_reg); | 921 | tspi->command1_reg, tspi->dma_control_reg); |
921 | tegra_periph_reset_assert(tspi->clk); | 922 | reset_control_assert(tspi->rst); |
922 | udelay(2); | 923 | udelay(2); |
923 | tegra_periph_reset_deassert(tspi->clk); | 924 | reset_control_deassert(tspi->rst); |
924 | complete(&tspi->xfer_completion); | 925 | complete(&tspi->xfer_completion); |
925 | goto exit; | 926 | goto exit; |
926 | } | 927 | } |
@@ -990,9 +991,9 @@ static irqreturn_t handle_dma_based_xfer(struct tegra_spi_data *tspi) | |||
990 | tspi->status_reg); | 991 | tspi->status_reg); |
991 | dev_err(tspi->dev, "DmaXfer 0x%08x:0x%08x\n", | 992 | dev_err(tspi->dev, "DmaXfer 0x%08x:0x%08x\n", |
992 | tspi->command1_reg, tspi->dma_control_reg); | 993 | tspi->command1_reg, tspi->dma_control_reg); |
993 | tegra_periph_reset_assert(tspi->clk); | 994 | reset_control_assert(tspi->rst); |
994 | udelay(2); | 995 | udelay(2); |
995 | tegra_periph_reset_deassert(tspi->clk); | 996 | reset_control_deassert(tspi->rst); |
996 | complete(&tspi->xfer_completion); | 997 | complete(&tspi->xfer_completion); |
997 | spin_unlock_irqrestore(&tspi->lock, flags); | 998 | spin_unlock_irqrestore(&tspi->lock, flags); |
998 | return IRQ_HANDLED; | 999 | return IRQ_HANDLED; |
@@ -1127,6 +1128,13 @@ static int tegra_spi_probe(struct platform_device *pdev) | |||
1127 | goto exit_free_irq; | 1128 | goto exit_free_irq; |
1128 | } | 1129 | } |
1129 | 1130 | ||
1131 | tspi->rst = devm_reset_control_get(&pdev->dev, "spi"); | ||
1132 | if (IS_ERR(tspi->rst)) { | ||
1133 | dev_err(&pdev->dev, "can not get reset\n"); | ||
1134 | ret = PTR_ERR(tspi->rst); | ||
1135 | goto exit_free_irq; | ||
1136 | } | ||
1137 | |||
1130 | tspi->max_buf_size = SPI_FIFO_DEPTH << 2; | 1138 | tspi->max_buf_size = SPI_FIFO_DEPTH << 2; |
1131 | tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN; | 1139 | tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN; |
1132 | 1140 | ||
diff --git a/drivers/spi/spi-tegra20-sflash.c b/drivers/spi/spi-tegra20-sflash.c index 4dc8e8129459..e6f382b33818 100644 --- a/drivers/spi/spi-tegra20-sflash.c +++ b/drivers/spi/spi-tegra20-sflash.c | |||
@@ -32,8 +32,8 @@ | |||
32 | #include <linux/pm_runtime.h> | 32 | #include <linux/pm_runtime.h> |
33 | #include <linux/of.h> | 33 | #include <linux/of.h> |
34 | #include <linux/of_device.h> | 34 | #include <linux/of_device.h> |
35 | #include <linux/reset.h> | ||
35 | #include <linux/spi/spi.h> | 36 | #include <linux/spi/spi.h> |
36 | #include <linux/clk/tegra.h> | ||
37 | 37 | ||
38 | #define SPI_COMMAND 0x000 | 38 | #define SPI_COMMAND 0x000 |
39 | #define SPI_GO BIT(30) | 39 | #define SPI_GO BIT(30) |
@@ -118,6 +118,7 @@ struct tegra_sflash_data { | |||
118 | spinlock_t lock; | 118 | spinlock_t lock; |
119 | 119 | ||
120 | struct clk *clk; | 120 | struct clk *clk; |
121 | struct reset_control *rst; | ||
121 | void __iomem *base; | 122 | void __iomem *base; |
122 | unsigned irq; | 123 | unsigned irq; |
123 | u32 spi_max_frequency; | 124 | u32 spi_max_frequency; |
@@ -389,9 +390,9 @@ static irqreturn_t handle_cpu_based_xfer(struct tegra_sflash_data *tsd) | |||
389 | dev_err(tsd->dev, | 390 | dev_err(tsd->dev, |
390 | "CpuXfer 0x%08x:0x%08x\n", tsd->command_reg, | 391 | "CpuXfer 0x%08x:0x%08x\n", tsd->command_reg, |
391 | tsd->dma_control_reg); | 392 | tsd->dma_control_reg); |
392 | tegra_periph_reset_assert(tsd->clk); | 393 | reset_control_assert(tsd->rst); |
393 | udelay(2); | 394 | udelay(2); |
394 | tegra_periph_reset_deassert(tsd->clk); | 395 | reset_control_deassert(tsd->rst); |
395 | complete(&tsd->xfer_completion); | 396 | complete(&tsd->xfer_completion); |
396 | goto exit; | 397 | goto exit; |
397 | } | 398 | } |
@@ -505,6 +506,13 @@ static int tegra_sflash_probe(struct platform_device *pdev) | |||
505 | goto exit_free_irq; | 506 | goto exit_free_irq; |
506 | } | 507 | } |
507 | 508 | ||
509 | tsd->rst = devm_reset_control_get(&pdev->dev, "spi"); | ||
510 | if (IS_ERR(tsd->rst)) { | ||
511 | dev_err(&pdev->dev, "can not get reset\n"); | ||
512 | ret = PTR_ERR(tsd->rst); | ||
513 | goto exit_free_irq; | ||
514 | } | ||
515 | |||
508 | init_completion(&tsd->xfer_completion); | 516 | init_completion(&tsd->xfer_completion); |
509 | pm_runtime_enable(&pdev->dev); | 517 | pm_runtime_enable(&pdev->dev); |
510 | if (!pm_runtime_enabled(&pdev->dev)) { | 518 | if (!pm_runtime_enabled(&pdev->dev)) { |
@@ -520,9 +528,9 @@ static int tegra_sflash_probe(struct platform_device *pdev) | |||
520 | } | 528 | } |
521 | 529 | ||
522 | /* Reset controller */ | 530 | /* Reset controller */ |
523 | tegra_periph_reset_assert(tsd->clk); | 531 | reset_control_assert(tsd->rst); |
524 | udelay(2); | 532 | udelay(2); |
525 | tegra_periph_reset_deassert(tsd->clk); | 533 | reset_control_deassert(tsd->rst); |
526 | 534 | ||
527 | tsd->def_command_reg = SPI_M_S | SPI_CS_SW; | 535 | tsd->def_command_reg = SPI_M_S | SPI_CS_SW; |
528 | tegra_sflash_writel(tsd, tsd->def_command_reg, SPI_COMMAND); | 536 | tegra_sflash_writel(tsd, tsd->def_command_reg, SPI_COMMAND); |
diff --git a/drivers/spi/spi-tegra20-slink.c b/drivers/spi/spi-tegra20-slink.c index e66715ba37ed..1305b8f933ba 100644 --- a/drivers/spi/spi-tegra20-slink.c +++ b/drivers/spi/spi-tegra20-slink.c | |||
@@ -33,8 +33,8 @@ | |||
33 | #include <linux/pm_runtime.h> | 33 | #include <linux/pm_runtime.h> |
34 | #include <linux/of.h> | 34 | #include <linux/of.h> |
35 | #include <linux/of_device.h> | 35 | #include <linux/of_device.h> |
36 | #include <linux/reset.h> | ||
36 | #include <linux/spi/spi.h> | 37 | #include <linux/spi/spi.h> |
37 | #include <linux/clk/tegra.h> | ||
38 | 38 | ||
39 | #define SLINK_COMMAND 0x000 | 39 | #define SLINK_COMMAND 0x000 |
40 | #define SLINK_BIT_LENGTH(x) (((x) & 0x1f) << 0) | 40 | #define SLINK_BIT_LENGTH(x) (((x) & 0x1f) << 0) |
@@ -167,6 +167,7 @@ struct tegra_slink_data { | |||
167 | spinlock_t lock; | 167 | spinlock_t lock; |
168 | 168 | ||
169 | struct clk *clk; | 169 | struct clk *clk; |
170 | struct reset_control *rst; | ||
170 | void __iomem *base; | 171 | void __iomem *base; |
171 | phys_addr_t phys; | 172 | phys_addr_t phys; |
172 | unsigned irq; | 173 | unsigned irq; |
@@ -884,9 +885,9 @@ static irqreturn_t handle_cpu_based_xfer(struct tegra_slink_data *tspi) | |||
884 | dev_err(tspi->dev, | 885 | dev_err(tspi->dev, |
885 | "CpuXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg, | 886 | "CpuXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg, |
886 | tspi->command2_reg, tspi->dma_control_reg); | 887 | tspi->command2_reg, tspi->dma_control_reg); |
887 | tegra_periph_reset_assert(tspi->clk); | 888 | reset_control_assert(tspi->rst); |
888 | udelay(2); | 889 | udelay(2); |
889 | tegra_periph_reset_deassert(tspi->clk); | 890 | reset_control_deassert(tspi->rst); |
890 | complete(&tspi->xfer_completion); | 891 | complete(&tspi->xfer_completion); |
891 | goto exit; | 892 | goto exit; |
892 | } | 893 | } |
@@ -957,9 +958,9 @@ static irqreturn_t handle_dma_based_xfer(struct tegra_slink_data *tspi) | |||
957 | dev_err(tspi->dev, | 958 | dev_err(tspi->dev, |
958 | "DmaXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg, | 959 | "DmaXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg, |
959 | tspi->command2_reg, tspi->dma_control_reg); | 960 | tspi->command2_reg, tspi->dma_control_reg); |
960 | tegra_periph_reset_assert(tspi->clk); | 961 | reset_control_assert(tspi->rst); |
961 | udelay(2); | 962 | udelay(2); |
962 | tegra_periph_reset_deassert(tspi->clk); | 963 | reset_control_assert(tspi->rst); |
963 | complete(&tspi->xfer_completion); | 964 | complete(&tspi->xfer_completion); |
964 | spin_unlock_irqrestore(&tspi->lock, flags); | 965 | spin_unlock_irqrestore(&tspi->lock, flags); |
965 | return IRQ_HANDLED; | 966 | return IRQ_HANDLED; |
@@ -1118,6 +1119,13 @@ static int tegra_slink_probe(struct platform_device *pdev) | |||
1118 | goto exit_free_irq; | 1119 | goto exit_free_irq; |
1119 | } | 1120 | } |
1120 | 1121 | ||
1122 | tspi->rst = devm_reset_control_get(&pdev->dev, "spi"); | ||
1123 | if (IS_ERR(tspi->rst)) { | ||
1124 | dev_err(&pdev->dev, "can not get reset\n"); | ||
1125 | ret = PTR_ERR(tspi->rst); | ||
1126 | goto exit_free_irq; | ||
1127 | } | ||
1128 | |||
1121 | tspi->max_buf_size = SLINK_FIFO_DEPTH << 2; | 1129 | tspi->max_buf_size = SLINK_FIFO_DEPTH << 2; |
1122 | tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN; | 1130 | tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN; |
1123 | 1131 | ||