diff options
Diffstat (limited to 'drivers/spi')
38 files changed, 2036 insertions, 1147 deletions
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 2e188e1127eb..e79884e997ae 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig | |||
@@ -297,9 +297,20 @@ config SPI_PPC4xx | |||
297 | help | 297 | help |
298 | This selects a driver for the PPC4xx SPI Controller. | 298 | This selects a driver for the PPC4xx SPI Controller. |
299 | 299 | ||
300 | config SPI_PXA2XX_PXADMA | ||
301 | bool "PXA2xx SSP legacy PXA DMA API support" | ||
302 | depends on SPI_PXA2XX && ARCH_PXA | ||
303 | help | ||
304 | Enable PXA private legacy DMA API support. Note that this is | ||
305 | deprecated in favor of generic DMA engine API. | ||
306 | |||
307 | config SPI_PXA2XX_DMA | ||
308 | def_bool y | ||
309 | depends on SPI_PXA2XX && !SPI_PXA2XX_PXADMA | ||
310 | |||
300 | config SPI_PXA2XX | 311 | config SPI_PXA2XX |
301 | tristate "PXA2xx SSP SPI master" | 312 | tristate "PXA2xx SSP SPI master" |
302 | depends on (ARCH_PXA || (X86_32 && PCI)) && EXPERIMENTAL | 313 | depends on ARCH_PXA || PCI || ACPI |
303 | select PXA_SSP if ARCH_PXA | 314 | select PXA_SSP if ARCH_PXA |
304 | help | 315 | help |
305 | This enables using a PXA2xx or Sodaville SSP port as a SPI master | 316 | This enables using a PXA2xx or Sodaville SSP port as a SPI master |
@@ -307,7 +318,7 @@ config SPI_PXA2XX | |||
307 | additional documentation can be found a Documentation/spi/pxa2xx. | 318 | additional documentation can be found a Documentation/spi/pxa2xx. |
308 | 319 | ||
309 | config SPI_PXA2XX_PCI | 320 | config SPI_PXA2XX_PCI |
310 | def_bool SPI_PXA2XX && X86_32 && PCI | 321 | def_tristate SPI_PXA2XX && PCI |
311 | 322 | ||
312 | config SPI_RSPI | 323 | config SPI_RSPI |
313 | tristate "Renesas RSPI controller" | 324 | tristate "Renesas RSPI controller" |
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 64e970ba261c..e53c30941340 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile | |||
@@ -47,7 +47,10 @@ obj-$(CONFIG_SPI_OMAP24XX) += spi-omap2-mcspi.o | |||
47 | obj-$(CONFIG_SPI_ORION) += spi-orion.o | 47 | obj-$(CONFIG_SPI_ORION) += spi-orion.o |
48 | obj-$(CONFIG_SPI_PL022) += spi-pl022.o | 48 | obj-$(CONFIG_SPI_PL022) += spi-pl022.o |
49 | obj-$(CONFIG_SPI_PPC4xx) += spi-ppc4xx.o | 49 | obj-$(CONFIG_SPI_PPC4xx) += spi-ppc4xx.o |
50 | obj-$(CONFIG_SPI_PXA2XX) += spi-pxa2xx.o | 50 | spi-pxa2xx-platform-objs := spi-pxa2xx.o |
51 | spi-pxa2xx-platform-$(CONFIG_SPI_PXA2XX_PXADMA) += spi-pxa2xx-pxadma.o | ||
52 | spi-pxa2xx-platform-$(CONFIG_SPI_PXA2XX_DMA) += spi-pxa2xx-dma.o | ||
53 | obj-$(CONFIG_SPI_PXA2XX) += spi-pxa2xx-platform.o | ||
51 | obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa2xx-pci.o | 54 | obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa2xx-pci.o |
52 | obj-$(CONFIG_SPI_RSPI) += spi-rspi.o | 55 | obj-$(CONFIG_SPI_RSPI) += spi-rspi.o |
53 | obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o | 56 | obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o |
diff --git a/drivers/spi/spi-altera.c b/drivers/spi/spi-altera.c index 5e7314ac51e9..a537f8dffc09 100644 --- a/drivers/spi/spi-altera.c +++ b/drivers/spi/spi-altera.c | |||
@@ -134,7 +134,7 @@ static int altera_spi_txrx(struct spi_device *spi, struct spi_transfer *t) | |||
134 | hw->tx = t->tx_buf; | 134 | hw->tx = t->tx_buf; |
135 | hw->rx = t->rx_buf; | 135 | hw->rx = t->rx_buf; |
136 | hw->count = 0; | 136 | hw->count = 0; |
137 | hw->bytes_per_word = (t->bits_per_word ? : spi->bits_per_word) / 8; | 137 | hw->bytes_per_word = t->bits_per_word / 8; |
138 | hw->len = t->len / hw->bytes_per_word; | 138 | hw->len = t->len / hw->bytes_per_word; |
139 | 139 | ||
140 | if (hw->irq >= 0) { | 140 | if (hw->irq >= 0) { |
diff --git a/drivers/spi/spi-ath79.c b/drivers/spi/spi-ath79.c index 9a5d7791c5fb..e504b7636058 100644 --- a/drivers/spi/spi-ath79.c +++ b/drivers/spi/spi-ath79.c | |||
@@ -24,17 +24,24 @@ | |||
24 | #include <linux/spi/spi_bitbang.h> | 24 | #include <linux/spi/spi_bitbang.h> |
25 | #include <linux/bitops.h> | 25 | #include <linux/bitops.h> |
26 | #include <linux/gpio.h> | 26 | #include <linux/gpio.h> |
27 | #include <linux/clk.h> | ||
28 | #include <linux/err.h> | ||
27 | 29 | ||
28 | #include <asm/mach-ath79/ar71xx_regs.h> | 30 | #include <asm/mach-ath79/ar71xx_regs.h> |
29 | #include <asm/mach-ath79/ath79_spi_platform.h> | 31 | #include <asm/mach-ath79/ath79_spi_platform.h> |
30 | 32 | ||
31 | #define DRV_NAME "ath79-spi" | 33 | #define DRV_NAME "ath79-spi" |
32 | 34 | ||
35 | #define ATH79_SPI_RRW_DELAY_FACTOR 12000 | ||
36 | #define MHZ (1000 * 1000) | ||
37 | |||
33 | struct ath79_spi { | 38 | struct ath79_spi { |
34 | struct spi_bitbang bitbang; | 39 | struct spi_bitbang bitbang; |
35 | u32 ioc_base; | 40 | u32 ioc_base; |
36 | u32 reg_ctrl; | 41 | u32 reg_ctrl; |
37 | void __iomem *base; | 42 | void __iomem *base; |
43 | struct clk *clk; | ||
44 | unsigned rrw_delay; | ||
38 | }; | 45 | }; |
39 | 46 | ||
40 | static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned reg) | 47 | static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned reg) |
@@ -52,6 +59,12 @@ static inline struct ath79_spi *ath79_spidev_to_sp(struct spi_device *spi) | |||
52 | return spi_master_get_devdata(spi->master); | 59 | return spi_master_get_devdata(spi->master); |
53 | } | 60 | } |
54 | 61 | ||
62 | static inline void ath79_spi_delay(struct ath79_spi *sp, unsigned nsecs) | ||
63 | { | ||
64 | if (nsecs > sp->rrw_delay) | ||
65 | ndelay(nsecs - sp->rrw_delay); | ||
66 | } | ||
67 | |||
55 | static void ath79_spi_chipselect(struct spi_device *spi, int is_active) | 68 | static void ath79_spi_chipselect(struct spi_device *spi, int is_active) |
56 | { | 69 | { |
57 | struct ath79_spi *sp = ath79_spidev_to_sp(spi); | 70 | struct ath79_spi *sp = ath79_spidev_to_sp(spi); |
@@ -83,15 +96,8 @@ static void ath79_spi_chipselect(struct spi_device *spi, int is_active) | |||
83 | 96 | ||
84 | } | 97 | } |
85 | 98 | ||
86 | static int ath79_spi_setup_cs(struct spi_device *spi) | 99 | static void ath79_spi_enable(struct ath79_spi *sp) |
87 | { | 100 | { |
88 | struct ath79_spi *sp = ath79_spidev_to_sp(spi); | ||
89 | struct ath79_spi_controller_data *cdata; | ||
90 | |||
91 | cdata = spi->controller_data; | ||
92 | if (spi->chip_select && !cdata) | ||
93 | return -EINVAL; | ||
94 | |||
95 | /* enable GPIO mode */ | 101 | /* enable GPIO mode */ |
96 | ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO); | 102 | ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO); |
97 | 103 | ||
@@ -101,44 +107,48 @@ static int ath79_spi_setup_cs(struct spi_device *spi) | |||
101 | 107 | ||
102 | /* TODO: setup speed? */ | 108 | /* TODO: setup speed? */ |
103 | ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43); | 109 | ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43); |
110 | } | ||
104 | 111 | ||
105 | if (spi->chip_select) { | 112 | static void ath79_spi_disable(struct ath79_spi *sp) |
106 | int status = 0; | 113 | { |
114 | /* restore CTRL register */ | ||
115 | ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl); | ||
116 | /* disable GPIO mode */ | ||
117 | ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0); | ||
118 | } | ||
107 | 119 | ||
108 | status = gpio_request(cdata->gpio, dev_name(&spi->dev)); | 120 | static int ath79_spi_setup_cs(struct spi_device *spi) |
109 | if (status) | 121 | { |
110 | return status; | 122 | struct ath79_spi_controller_data *cdata; |
123 | int status; | ||
111 | 124 | ||
112 | status = gpio_direction_output(cdata->gpio, | 125 | cdata = spi->controller_data; |
113 | spi->mode & SPI_CS_HIGH); | 126 | if (spi->chip_select && !cdata) |
114 | if (status) { | 127 | return -EINVAL; |
115 | gpio_free(cdata->gpio); | 128 | |
116 | return status; | 129 | status = 0; |
117 | } | 130 | if (spi->chip_select) { |
118 | } else { | 131 | unsigned long flags; |
132 | |||
133 | flags = GPIOF_DIR_OUT; | ||
119 | if (spi->mode & SPI_CS_HIGH) | 134 | if (spi->mode & SPI_CS_HIGH) |
120 | sp->ioc_base |= AR71XX_SPI_IOC_CS0; | 135 | flags |= GPIOF_INIT_HIGH; |
121 | else | 136 | else |
122 | sp->ioc_base &= ~AR71XX_SPI_IOC_CS0; | 137 | flags |= GPIOF_INIT_LOW; |
123 | ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); | 138 | |
139 | status = gpio_request_one(cdata->gpio, flags, | ||
140 | dev_name(&spi->dev)); | ||
124 | } | 141 | } |
125 | 142 | ||
126 | return 0; | 143 | return status; |
127 | } | 144 | } |
128 | 145 | ||
129 | static void ath79_spi_cleanup_cs(struct spi_device *spi) | 146 | static void ath79_spi_cleanup_cs(struct spi_device *spi) |
130 | { | 147 | { |
131 | struct ath79_spi *sp = ath79_spidev_to_sp(spi); | ||
132 | |||
133 | if (spi->chip_select) { | 148 | if (spi->chip_select) { |
134 | struct ath79_spi_controller_data *cdata = spi->controller_data; | 149 | struct ath79_spi_controller_data *cdata = spi->controller_data; |
135 | gpio_free(cdata->gpio); | 150 | gpio_free(cdata->gpio); |
136 | } | 151 | } |
137 | |||
138 | /* restore CTRL register */ | ||
139 | ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl); | ||
140 | /* disable GPIO mode */ | ||
141 | ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0); | ||
142 | } | 152 | } |
143 | 153 | ||
144 | static int ath79_spi_setup(struct spi_device *spi) | 154 | static int ath79_spi_setup(struct spi_device *spi) |
@@ -184,7 +194,11 @@ static u32 ath79_spi_txrx_mode0(struct spi_device *spi, unsigned nsecs, | |||
184 | 194 | ||
185 | /* setup MSB (to slave) on trailing edge */ | 195 | /* setup MSB (to slave) on trailing edge */ |
186 | ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out); | 196 | ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out); |
197 | ath79_spi_delay(sp, nsecs); | ||
187 | ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK); | 198 | ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK); |
199 | ath79_spi_delay(sp, nsecs); | ||
200 | if (bits == 1) | ||
201 | ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out); | ||
188 | 202 | ||
189 | word <<= 1; | 203 | word <<= 1; |
190 | } | 204 | } |
@@ -198,6 +212,7 @@ static int ath79_spi_probe(struct platform_device *pdev) | |||
198 | struct ath79_spi *sp; | 212 | struct ath79_spi *sp; |
199 | struct ath79_spi_platform_data *pdata; | 213 | struct ath79_spi_platform_data *pdata; |
200 | struct resource *r; | 214 | struct resource *r; |
215 | unsigned long rate; | ||
201 | int ret; | 216 | int ret; |
202 | 217 | ||
203 | master = spi_alloc_master(&pdev->dev, sizeof(*sp)); | 218 | master = spi_alloc_master(&pdev->dev, sizeof(*sp)); |
@@ -236,12 +251,39 @@ static int ath79_spi_probe(struct platform_device *pdev) | |||
236 | goto err_put_master; | 251 | goto err_put_master; |
237 | } | 252 | } |
238 | 253 | ||
254 | sp->clk = clk_get(&pdev->dev, "ahb"); | ||
255 | if (IS_ERR(sp->clk)) { | ||
256 | ret = PTR_ERR(sp->clk); | ||
257 | goto err_unmap; | ||
258 | } | ||
259 | |||
260 | ret = clk_enable(sp->clk); | ||
261 | if (ret) | ||
262 | goto err_clk_put; | ||
263 | |||
264 | rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ); | ||
265 | if (!rate) { | ||
266 | ret = -EINVAL; | ||
267 | goto err_clk_disable; | ||
268 | } | ||
269 | |||
270 | sp->rrw_delay = ATH79_SPI_RRW_DELAY_FACTOR / rate; | ||
271 | dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n", | ||
272 | sp->rrw_delay); | ||
273 | |||
274 | ath79_spi_enable(sp); | ||
239 | ret = spi_bitbang_start(&sp->bitbang); | 275 | ret = spi_bitbang_start(&sp->bitbang); |
240 | if (ret) | 276 | if (ret) |
241 | goto err_unmap; | 277 | goto err_disable; |
242 | 278 | ||
243 | return 0; | 279 | return 0; |
244 | 280 | ||
281 | err_disable: | ||
282 | ath79_spi_disable(sp); | ||
283 | err_clk_disable: | ||
284 | clk_disable(sp->clk); | ||
285 | err_clk_put: | ||
286 | clk_put(sp->clk); | ||
245 | err_unmap: | 287 | err_unmap: |
246 | iounmap(sp->base); | 288 | iounmap(sp->base); |
247 | err_put_master: | 289 | err_put_master: |
@@ -256,6 +298,9 @@ static int ath79_spi_remove(struct platform_device *pdev) | |||
256 | struct ath79_spi *sp = platform_get_drvdata(pdev); | 298 | struct ath79_spi *sp = platform_get_drvdata(pdev); |
257 | 299 | ||
258 | spi_bitbang_stop(&sp->bitbang); | 300 | spi_bitbang_stop(&sp->bitbang); |
301 | ath79_spi_disable(sp); | ||
302 | clk_disable(sp->clk); | ||
303 | clk_put(sp->clk); | ||
259 | iounmap(sp->base); | 304 | iounmap(sp->base); |
260 | platform_set_drvdata(pdev, NULL); | 305 | platform_set_drvdata(pdev, NULL); |
261 | spi_master_put(sp->bitbang.master); | 306 | spi_master_put(sp->bitbang.master); |
@@ -263,9 +308,15 @@ static int ath79_spi_remove(struct platform_device *pdev) | |||
263 | return 0; | 308 | return 0; |
264 | } | 309 | } |
265 | 310 | ||
311 | static void ath79_spi_shutdown(struct platform_device *pdev) | ||
312 | { | ||
313 | ath79_spi_remove(pdev); | ||
314 | } | ||
315 | |||
266 | static struct platform_driver ath79_spi_driver = { | 316 | static struct platform_driver ath79_spi_driver = { |
267 | .probe = ath79_spi_probe, | 317 | .probe = ath79_spi_probe, |
268 | .remove = ath79_spi_remove, | 318 | .remove = ath79_spi_remove, |
319 | .shutdown = ath79_spi_shutdown, | ||
269 | .driver = { | 320 | .driver = { |
270 | .name = DRV_NAME, | 321 | .name = DRV_NAME, |
271 | .owner = THIS_MODULE, | 322 | .owner = THIS_MODULE, |
diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c index ab34497bcfee..656d137db253 100644 --- a/drivers/spi/spi-atmel.c +++ b/drivers/spi/spi-atmel.c | |||
@@ -1088,7 +1088,7 @@ static struct platform_driver atmel_spi_driver = { | |||
1088 | .suspend = atmel_spi_suspend, | 1088 | .suspend = atmel_spi_suspend, |
1089 | .resume = atmel_spi_resume, | 1089 | .resume = atmel_spi_resume, |
1090 | .probe = atmel_spi_probe, | 1090 | .probe = atmel_spi_probe, |
1091 | .remove = __exit_p(atmel_spi_remove), | 1091 | .remove = atmel_spi_remove, |
1092 | }; | 1092 | }; |
1093 | module_platform_driver(atmel_spi_driver); | 1093 | module_platform_driver(atmel_spi_driver); |
1094 | 1094 | ||
diff --git a/drivers/spi/spi-au1550.c b/drivers/spi/spi-au1550.c index 4de66d1cfe51..44dd34b6ad09 100644 --- a/drivers/spi/spi-au1550.c +++ b/drivers/spi/spi-au1550.c | |||
@@ -717,7 +717,7 @@ static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw) | |||
717 | } | 717 | } |
718 | } | 718 | } |
719 | 719 | ||
720 | static void __init au1550_spi_setup_psc_as_spi(struct au1550_spi *hw) | 720 | static void au1550_spi_setup_psc_as_spi(struct au1550_spi *hw) |
721 | { | 721 | { |
722 | u32 stat, cfg; | 722 | u32 stat, cfg; |
723 | 723 | ||
@@ -766,7 +766,7 @@ static void __init au1550_spi_setup_psc_as_spi(struct au1550_spi *hw) | |||
766 | } | 766 | } |
767 | 767 | ||
768 | 768 | ||
769 | static int __init au1550_spi_probe(struct platform_device *pdev) | 769 | static int au1550_spi_probe(struct platform_device *pdev) |
770 | { | 770 | { |
771 | struct au1550_spi *hw; | 771 | struct au1550_spi *hw; |
772 | struct spi_master *master; | 772 | struct spi_master *master; |
@@ -968,7 +968,7 @@ err_nomem: | |||
968 | return err; | 968 | return err; |
969 | } | 969 | } |
970 | 970 | ||
971 | static int __exit au1550_spi_remove(struct platform_device *pdev) | 971 | static int au1550_spi_remove(struct platform_device *pdev) |
972 | { | 972 | { |
973 | struct au1550_spi *hw = platform_get_drvdata(pdev); | 973 | struct au1550_spi *hw = platform_get_drvdata(pdev); |
974 | 974 | ||
@@ -997,7 +997,7 @@ static int __exit au1550_spi_remove(struct platform_device *pdev) | |||
997 | MODULE_ALIAS("platform:au1550-spi"); | 997 | MODULE_ALIAS("platform:au1550-spi"); |
998 | 998 | ||
999 | static struct platform_driver au1550_spi_drv = { | 999 | static struct platform_driver au1550_spi_drv = { |
1000 | .remove = __exit_p(au1550_spi_remove), | 1000 | .remove = au1550_spi_remove, |
1001 | .driver = { | 1001 | .driver = { |
1002 | .name = "au1550-spi", | 1002 | .name = "au1550-spi", |
1003 | .owner = THIS_MODULE, | 1003 | .owner = THIS_MODULE, |
diff --git a/drivers/spi/spi-bcm63xx.c b/drivers/spi/spi-bcm63xx.c index f44ab5508535..9578af782a77 100644 --- a/drivers/spi/spi-bcm63xx.c +++ b/drivers/spi/spi-bcm63xx.c | |||
@@ -37,6 +37,8 @@ | |||
37 | 37 | ||
38 | #define PFX KBUILD_MODNAME | 38 | #define PFX KBUILD_MODNAME |
39 | 39 | ||
40 | #define BCM63XX_SPI_MAX_PREPEND 15 | ||
41 | |||
40 | struct bcm63xx_spi { | 42 | struct bcm63xx_spi { |
41 | struct completion done; | 43 | struct completion done; |
42 | 44 | ||
@@ -49,16 +51,10 @@ struct bcm63xx_spi { | |||
49 | unsigned int msg_type_shift; | 51 | unsigned int msg_type_shift; |
50 | unsigned int msg_ctl_width; | 52 | unsigned int msg_ctl_width; |
51 | 53 | ||
52 | /* Data buffers */ | ||
53 | const unsigned char *tx_ptr; | ||
54 | unsigned char *rx_ptr; | ||
55 | |||
56 | /* data iomem */ | 54 | /* data iomem */ |
57 | u8 __iomem *tx_io; | 55 | u8 __iomem *tx_io; |
58 | const u8 __iomem *rx_io; | 56 | const u8 __iomem *rx_io; |
59 | 57 | ||
60 | int remaining_bytes; | ||
61 | |||
62 | struct clk *clk; | 58 | struct clk *clk; |
63 | struct platform_device *pdev; | 59 | struct platform_device *pdev; |
64 | }; | 60 | }; |
@@ -175,24 +171,17 @@ static int bcm63xx_spi_setup(struct spi_device *spi) | |||
175 | return 0; | 171 | return 0; |
176 | } | 172 | } |
177 | 173 | ||
178 | /* Fill the TX FIFO with as many bytes as possible */ | 174 | static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *first, |
179 | static void bcm63xx_spi_fill_tx_fifo(struct bcm63xx_spi *bs) | 175 | unsigned int num_transfers) |
180 | { | ||
181 | u8 size; | ||
182 | |||
183 | /* Fill the Tx FIFO with as many bytes as possible */ | ||
184 | size = bs->remaining_bytes < bs->fifo_size ? bs->remaining_bytes : | ||
185 | bs->fifo_size; | ||
186 | memcpy_toio(bs->tx_io, bs->tx_ptr, size); | ||
187 | bs->remaining_bytes -= size; | ||
188 | } | ||
189 | |||
190 | static unsigned int bcm63xx_txrx_bufs(struct spi_device *spi, | ||
191 | struct spi_transfer *t) | ||
192 | { | 176 | { |
193 | struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master); | 177 | struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master); |
194 | u16 msg_ctl; | 178 | u16 msg_ctl; |
195 | u16 cmd; | 179 | u16 cmd; |
180 | u8 rx_tail; | ||
181 | unsigned int i, timeout = 0, prepend_len = 0, len = 0; | ||
182 | struct spi_transfer *t = first; | ||
183 | bool do_rx = false; | ||
184 | bool do_tx = false; | ||
196 | 185 | ||
197 | /* Disable the CMD_DONE interrupt */ | 186 | /* Disable the CMD_DONE interrupt */ |
198 | bcm_spi_writeb(bs, 0, SPI_INT_MASK); | 187 | bcm_spi_writeb(bs, 0, SPI_INT_MASK); |
@@ -200,25 +189,45 @@ static unsigned int bcm63xx_txrx_bufs(struct spi_device *spi, | |||
200 | dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n", | 189 | dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n", |
201 | t->tx_buf, t->rx_buf, t->len); | 190 | t->tx_buf, t->rx_buf, t->len); |
202 | 191 | ||
203 | /* Transmitter is inhibited */ | 192 | if (num_transfers > 1 && t->tx_buf && t->len <= BCM63XX_SPI_MAX_PREPEND) |
204 | bs->tx_ptr = t->tx_buf; | 193 | prepend_len = t->len; |
205 | bs->rx_ptr = t->rx_buf; | ||
206 | 194 | ||
207 | if (t->tx_buf) { | 195 | /* prepare the buffer */ |
208 | bs->remaining_bytes = t->len; | 196 | for (i = 0; i < num_transfers; i++) { |
209 | bcm63xx_spi_fill_tx_fifo(bs); | 197 | if (t->tx_buf) { |
198 | do_tx = true; | ||
199 | memcpy_toio(bs->tx_io + len, t->tx_buf, t->len); | ||
200 | |||
201 | /* don't prepend more than one tx */ | ||
202 | if (t != first) | ||
203 | prepend_len = 0; | ||
204 | } | ||
205 | |||
206 | if (t->rx_buf) { | ||
207 | do_rx = true; | ||
208 | /* prepend is half-duplex write only */ | ||
209 | if (t == first) | ||
210 | prepend_len = 0; | ||
211 | } | ||
212 | |||
213 | len += t->len; | ||
214 | |||
215 | t = list_entry(t->transfer_list.next, struct spi_transfer, | ||
216 | transfer_list); | ||
210 | } | 217 | } |
211 | 218 | ||
219 | len -= prepend_len; | ||
220 | |||
212 | init_completion(&bs->done); | 221 | init_completion(&bs->done); |
213 | 222 | ||
214 | /* Fill in the Message control register */ | 223 | /* Fill in the Message control register */ |
215 | msg_ctl = (t->len << SPI_BYTE_CNT_SHIFT); | 224 | msg_ctl = (len << SPI_BYTE_CNT_SHIFT); |
216 | 225 | ||
217 | if (t->rx_buf && t->tx_buf) | 226 | if (do_rx && do_tx && prepend_len == 0) |
218 | msg_ctl |= (SPI_FD_RW << bs->msg_type_shift); | 227 | msg_ctl |= (SPI_FD_RW << bs->msg_type_shift); |
219 | else if (t->rx_buf) | 228 | else if (do_rx) |
220 | msg_ctl |= (SPI_HD_R << bs->msg_type_shift); | 229 | msg_ctl |= (SPI_HD_R << bs->msg_type_shift); |
221 | else if (t->tx_buf) | 230 | else if (do_tx) |
222 | msg_ctl |= (SPI_HD_W << bs->msg_type_shift); | 231 | msg_ctl |= (SPI_HD_W << bs->msg_type_shift); |
223 | 232 | ||
224 | switch (bs->msg_ctl_width) { | 233 | switch (bs->msg_ctl_width) { |
@@ -232,14 +241,41 @@ static unsigned int bcm63xx_txrx_bufs(struct spi_device *spi, | |||
232 | 241 | ||
233 | /* Issue the transfer */ | 242 | /* Issue the transfer */ |
234 | cmd = SPI_CMD_START_IMMEDIATE; | 243 | cmd = SPI_CMD_START_IMMEDIATE; |
235 | cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT); | 244 | cmd |= (prepend_len << SPI_CMD_PREPEND_BYTE_CNT_SHIFT); |
236 | cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT); | 245 | cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT); |
237 | bcm_spi_writew(bs, cmd, SPI_CMD); | 246 | bcm_spi_writew(bs, cmd, SPI_CMD); |
238 | 247 | ||
239 | /* Enable the CMD_DONE interrupt */ | 248 | /* Enable the CMD_DONE interrupt */ |
240 | bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK); | 249 | bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK); |
241 | 250 | ||
242 | return t->len - bs->remaining_bytes; | 251 | timeout = wait_for_completion_timeout(&bs->done, HZ); |
252 | if (!timeout) | ||
253 | return -ETIMEDOUT; | ||
254 | |||
255 | /* read out all data */ | ||
256 | rx_tail = bcm_spi_readb(bs, SPI_RX_TAIL); | ||
257 | |||
258 | if (do_rx && rx_tail != len) | ||
259 | return -EIO; | ||
260 | |||
261 | if (!rx_tail) | ||
262 | return 0; | ||
263 | |||
264 | len = 0; | ||
265 | t = first; | ||
266 | /* Read out all the data */ | ||
267 | for (i = 0; i < num_transfers; i++) { | ||
268 | if (t->rx_buf) | ||
269 | memcpy_fromio(t->rx_buf, bs->rx_io + len, t->len); | ||
270 | |||
271 | if (t != first || prepend_len == 0) | ||
272 | len += t->len; | ||
273 | |||
274 | t = list_entry(t->transfer_list.next, struct spi_transfer, | ||
275 | transfer_list); | ||
276 | } | ||
277 | |||
278 | return 0; | ||
243 | } | 279 | } |
244 | 280 | ||
245 | static int bcm63xx_spi_prepare_transfer(struct spi_master *master) | 281 | static int bcm63xx_spi_prepare_transfer(struct spi_master *master) |
@@ -264,41 +300,76 @@ static int bcm63xx_spi_transfer_one(struct spi_master *master, | |||
264 | struct spi_message *m) | 300 | struct spi_message *m) |
265 | { | 301 | { |
266 | struct bcm63xx_spi *bs = spi_master_get_devdata(master); | 302 | struct bcm63xx_spi *bs = spi_master_get_devdata(master); |
267 | struct spi_transfer *t; | 303 | struct spi_transfer *t, *first = NULL; |
268 | struct spi_device *spi = m->spi; | 304 | struct spi_device *spi = m->spi; |
269 | int status = 0; | 305 | int status = 0; |
270 | unsigned int timeout = 0; | 306 | unsigned int n_transfers = 0, total_len = 0; |
271 | 307 | bool can_use_prepend = false; | |
308 | |||
309 | /* | ||
310 | * This SPI controller does not support keeping CS active after a | ||
311 | * transfer. | ||
312 | * Work around this by merging as many transfers we can into one big | ||
313 | * full-duplex transfers. | ||
314 | */ | ||
272 | list_for_each_entry(t, &m->transfers, transfer_list) { | 315 | list_for_each_entry(t, &m->transfers, transfer_list) { |
273 | unsigned int len = t->len; | ||
274 | u8 rx_tail; | ||
275 | |||
276 | status = bcm63xx_spi_check_transfer(spi, t); | 316 | status = bcm63xx_spi_check_transfer(spi, t); |
277 | if (status < 0) | 317 | if (status < 0) |
278 | goto exit; | 318 | goto exit; |
279 | 319 | ||
280 | /* configure adapter for a new transfer */ | 320 | if (!first) |
281 | bcm63xx_spi_setup_transfer(spi, t); | 321 | first = t; |
322 | |||
323 | n_transfers++; | ||
324 | total_len += t->len; | ||
325 | |||
326 | if (n_transfers == 2 && !first->rx_buf && !t->tx_buf && | ||
327 | first->len <= BCM63XX_SPI_MAX_PREPEND) | ||
328 | can_use_prepend = true; | ||
329 | else if (can_use_prepend && t->tx_buf) | ||
330 | can_use_prepend = false; | ||
331 | |||
332 | /* we can only transfer one fifo worth of data */ | ||
333 | if ((can_use_prepend && | ||
334 | total_len > (bs->fifo_size + BCM63XX_SPI_MAX_PREPEND)) || | ||
335 | (!can_use_prepend && total_len > bs->fifo_size)) { | ||
336 | dev_err(&spi->dev, "unable to do transfers larger than FIFO size (%i > %i)\n", | ||
337 | total_len, bs->fifo_size); | ||
338 | status = -EINVAL; | ||
339 | goto exit; | ||
340 | } | ||
341 | |||
342 | /* all combined transfers have to have the same speed */ | ||
343 | if (t->speed_hz != first->speed_hz) { | ||
344 | dev_err(&spi->dev, "unable to change speed between transfers\n"); | ||
345 | status = -EINVAL; | ||
346 | goto exit; | ||
347 | } | ||
282 | 348 | ||
283 | while (len) { | 349 | /* CS will be deasserted directly after transfer */ |
284 | /* send the data */ | 350 | if (t->delay_usecs) { |
285 | len -= bcm63xx_txrx_bufs(spi, t); | 351 | dev_err(&spi->dev, "unable to keep CS asserted after transfer\n"); |
352 | status = -EINVAL; | ||
353 | goto exit; | ||
354 | } | ||
355 | |||
356 | if (t->cs_change || | ||
357 | list_is_last(&t->transfer_list, &m->transfers)) { | ||
358 | /* configure adapter for a new transfer */ | ||
359 | bcm63xx_spi_setup_transfer(spi, first); | ||
286 | 360 | ||
287 | timeout = wait_for_completion_timeout(&bs->done, HZ); | 361 | /* send the data */ |
288 | if (!timeout) { | 362 | status = bcm63xx_txrx_bufs(spi, first, n_transfers); |
289 | status = -ETIMEDOUT; | 363 | if (status) |
290 | goto exit; | 364 | goto exit; |
291 | } | ||
292 | 365 | ||
293 | /* read out all data */ | 366 | m->actual_length += total_len; |
294 | rx_tail = bcm_spi_readb(bs, SPI_RX_TAIL); | ||
295 | 367 | ||
296 | /* Read out all the data */ | 368 | first = NULL; |
297 | if (rx_tail) | 369 | n_transfers = 0; |
298 | memcpy_fromio(bs->rx_ptr, bs->rx_io, rx_tail); | 370 | total_len = 0; |
371 | can_use_prepend = false; | ||
299 | } | 372 | } |
300 | |||
301 | m->actual_length += t->len; | ||
302 | } | 373 | } |
303 | exit: | 374 | exit: |
304 | m->status = status; | 375 | m->status = status; |
diff --git a/drivers/spi/spi-bfin-sport.c b/drivers/spi/spi-bfin-sport.c index ac7ffca7ba47..39b0d1711b4e 100644 --- a/drivers/spi/spi-bfin-sport.c +++ b/drivers/spi/spi-bfin-sport.c | |||
@@ -416,8 +416,7 @@ bfin_sport_spi_pump_transfers(unsigned long data) | |||
416 | drv_data->cs_change = transfer->cs_change; | 416 | drv_data->cs_change = transfer->cs_change; |
417 | 417 | ||
418 | /* Bits per word setup */ | 418 | /* Bits per word setup */ |
419 | bits_per_word = transfer->bits_per_word ? : | 419 | bits_per_word = transfer->bits_per_word; |
420 | message->spi->bits_per_word ? : 8; | ||
421 | if (bits_per_word % 16 == 0) | 420 | if (bits_per_word % 16 == 0) |
422 | drv_data->ops = &bfin_sport_transfer_ops_u16; | 421 | drv_data->ops = &bfin_sport_transfer_ops_u16; |
423 | else | 422 | else |
diff --git a/drivers/spi/spi-bfin5xx.c b/drivers/spi/spi-bfin5xx.c index 0429d833f75b..317f564c899c 100644 --- a/drivers/spi/spi-bfin5xx.c +++ b/drivers/spi/spi-bfin5xx.c | |||
@@ -642,8 +642,7 @@ static void bfin_spi_pump_transfers(unsigned long data) | |||
642 | drv_data->cs_change = transfer->cs_change; | 642 | drv_data->cs_change = transfer->cs_change; |
643 | 643 | ||
644 | /* Bits per word setup */ | 644 | /* Bits per word setup */ |
645 | bits_per_word = transfer->bits_per_word ? : | 645 | bits_per_word = transfer->bits_per_word; |
646 | message->spi->bits_per_word ? : 8; | ||
647 | if (bits_per_word % 16 == 0) { | 646 | if (bits_per_word % 16 == 0) { |
648 | drv_data->n_bytes = bits_per_word/8; | 647 | drv_data->n_bytes = bits_per_word/8; |
649 | drv_data->len = (transfer->len) >> 1; | 648 | drv_data->len = (transfer->len) >> 1; |
@@ -1274,7 +1273,7 @@ static int bfin_spi_destroy_queue(struct bfin_spi_master_data *drv_data) | |||
1274 | return 0; | 1273 | return 0; |
1275 | } | 1274 | } |
1276 | 1275 | ||
1277 | static int __init bfin_spi_probe(struct platform_device *pdev) | 1276 | static int bfin_spi_probe(struct platform_device *pdev) |
1278 | { | 1277 | { |
1279 | struct device *dev = &pdev->dev; | 1278 | struct device *dev = &pdev->dev; |
1280 | struct bfin5xx_spi_master *platform_info; | 1279 | struct bfin5xx_spi_master *platform_info; |
diff --git a/drivers/spi/spi-bitbang.c b/drivers/spi/spi-bitbang.c index 8b3d8efafd3c..a63d7da3bfe2 100644 --- a/drivers/spi/spi-bitbang.c +++ b/drivers/spi/spi-bitbang.c | |||
@@ -69,7 +69,7 @@ static unsigned bitbang_txrx_8( | |||
69 | unsigned ns, | 69 | unsigned ns, |
70 | struct spi_transfer *t | 70 | struct spi_transfer *t |
71 | ) { | 71 | ) { |
72 | unsigned bits = t->bits_per_word ? : spi->bits_per_word; | 72 | unsigned bits = t->bits_per_word; |
73 | unsigned count = t->len; | 73 | unsigned count = t->len; |
74 | const u8 *tx = t->tx_buf; | 74 | const u8 *tx = t->tx_buf; |
75 | u8 *rx = t->rx_buf; | 75 | u8 *rx = t->rx_buf; |
@@ -95,7 +95,7 @@ static unsigned bitbang_txrx_16( | |||
95 | unsigned ns, | 95 | unsigned ns, |
96 | struct spi_transfer *t | 96 | struct spi_transfer *t |
97 | ) { | 97 | ) { |
98 | unsigned bits = t->bits_per_word ? : spi->bits_per_word; | 98 | unsigned bits = t->bits_per_word; |
99 | unsigned count = t->len; | 99 | unsigned count = t->len; |
100 | const u16 *tx = t->tx_buf; | 100 | const u16 *tx = t->tx_buf; |
101 | u16 *rx = t->rx_buf; | 101 | u16 *rx = t->rx_buf; |
@@ -121,7 +121,7 @@ static unsigned bitbang_txrx_32( | |||
121 | unsigned ns, | 121 | unsigned ns, |
122 | struct spi_transfer *t | 122 | struct spi_transfer *t |
123 | ) { | 123 | ) { |
124 | unsigned bits = t->bits_per_word ? : spi->bits_per_word; | 124 | unsigned bits = t->bits_per_word; |
125 | unsigned count = t->len; | 125 | unsigned count = t->len; |
126 | const u32 *tx = t->tx_buf; | 126 | const u32 *tx = t->tx_buf; |
127 | u32 *rx = t->rx_buf; | 127 | u32 *rx = t->rx_buf; |
@@ -427,40 +427,41 @@ EXPORT_SYMBOL_GPL(spi_bitbang_transfer); | |||
427 | */ | 427 | */ |
428 | int spi_bitbang_start(struct spi_bitbang *bitbang) | 428 | int spi_bitbang_start(struct spi_bitbang *bitbang) |
429 | { | 429 | { |
430 | int status; | 430 | struct spi_master *master = bitbang->master; |
431 | int status; | ||
431 | 432 | ||
432 | if (!bitbang->master || !bitbang->chipselect) | 433 | if (!master || !bitbang->chipselect) |
433 | return -EINVAL; | 434 | return -EINVAL; |
434 | 435 | ||
435 | INIT_WORK(&bitbang->work, bitbang_work); | 436 | INIT_WORK(&bitbang->work, bitbang_work); |
436 | spin_lock_init(&bitbang->lock); | 437 | spin_lock_init(&bitbang->lock); |
437 | INIT_LIST_HEAD(&bitbang->queue); | 438 | INIT_LIST_HEAD(&bitbang->queue); |
438 | 439 | ||
439 | if (!bitbang->master->mode_bits) | 440 | if (!master->mode_bits) |
440 | bitbang->master->mode_bits = SPI_CPOL | SPI_CPHA | bitbang->flags; | 441 | master->mode_bits = SPI_CPOL | SPI_CPHA | bitbang->flags; |
441 | 442 | ||
442 | if (!bitbang->master->transfer) | 443 | if (!master->transfer) |
443 | bitbang->master->transfer = spi_bitbang_transfer; | 444 | master->transfer = spi_bitbang_transfer; |
444 | if (!bitbang->txrx_bufs) { | 445 | if (!bitbang->txrx_bufs) { |
445 | bitbang->use_dma = 0; | 446 | bitbang->use_dma = 0; |
446 | bitbang->txrx_bufs = spi_bitbang_bufs; | 447 | bitbang->txrx_bufs = spi_bitbang_bufs; |
447 | if (!bitbang->master->setup) { | 448 | if (!master->setup) { |
448 | if (!bitbang->setup_transfer) | 449 | if (!bitbang->setup_transfer) |
449 | bitbang->setup_transfer = | 450 | bitbang->setup_transfer = |
450 | spi_bitbang_setup_transfer; | 451 | spi_bitbang_setup_transfer; |
451 | bitbang->master->setup = spi_bitbang_setup; | 452 | master->setup = spi_bitbang_setup; |
452 | bitbang->master->cleanup = spi_bitbang_cleanup; | 453 | master->cleanup = spi_bitbang_cleanup; |
453 | } | 454 | } |
454 | } else if (!bitbang->master->setup) | 455 | } else if (!master->setup) |
455 | return -EINVAL; | 456 | return -EINVAL; |
456 | if (bitbang->master->transfer == spi_bitbang_transfer && | 457 | if (master->transfer == spi_bitbang_transfer && |
457 | !bitbang->setup_transfer) | 458 | !bitbang->setup_transfer) |
458 | return -EINVAL; | 459 | return -EINVAL; |
459 | 460 | ||
460 | /* this task is the only thing to touch the SPI bits */ | 461 | /* this task is the only thing to touch the SPI bits */ |
461 | bitbang->busy = 0; | 462 | bitbang->busy = 0; |
462 | bitbang->workqueue = create_singlethread_workqueue( | 463 | bitbang->workqueue = create_singlethread_workqueue( |
463 | dev_name(bitbang->master->dev.parent)); | 464 | dev_name(master->dev.parent)); |
464 | if (bitbang->workqueue == NULL) { | 465 | if (bitbang->workqueue == NULL) { |
465 | status = -EBUSY; | 466 | status = -EBUSY; |
466 | goto err1; | 467 | goto err1; |
@@ -469,7 +470,7 @@ int spi_bitbang_start(struct spi_bitbang *bitbang) | |||
469 | /* driver may get busy before register() returns, especially | 470 | /* driver may get busy before register() returns, especially |
470 | * if someone registered boardinfo for devices | 471 | * if someone registered boardinfo for devices |
471 | */ | 472 | */ |
472 | status = spi_register_master(bitbang->master); | 473 | status = spi_register_master(master); |
473 | if (status < 0) | 474 | if (status < 0) |
474 | goto err2; | 475 | goto err2; |
475 | 476 | ||
diff --git a/drivers/spi/spi-clps711x.c b/drivers/spi/spi-clps711x.c index 1366c4620d5d..a11cbf02691a 100644 --- a/drivers/spi/spi-clps711x.c +++ b/drivers/spi/spi-clps711x.c | |||
@@ -68,7 +68,7 @@ static int spi_clps711x_setup_xfer(struct spi_device *spi, | |||
68 | struct spi_transfer *xfer) | 68 | struct spi_transfer *xfer) |
69 | { | 69 | { |
70 | u32 speed = xfer->speed_hz ? : spi->max_speed_hz; | 70 | u32 speed = xfer->speed_hz ? : spi->max_speed_hz; |
71 | u8 bpw = xfer->bits_per_word ? : spi->bits_per_word; | 71 | u8 bpw = xfer->bits_per_word; |
72 | struct spi_clps711x_data *hw = spi_master_get_devdata(spi->master); | 72 | struct spi_clps711x_data *hw = spi_master_get_devdata(spi->master); |
73 | 73 | ||
74 | if (bpw != 8) { | 74 | if (bpw != 8) { |
diff --git a/drivers/spi/spi-coldfire-qspi.c b/drivers/spi/spi-coldfire-qspi.c index 58466b810da4..7b5cc9e4e94d 100644 --- a/drivers/spi/spi-coldfire-qspi.c +++ b/drivers/spi/spi-coldfire-qspi.c | |||
@@ -329,8 +329,7 @@ static int mcfqspi_transfer_one_message(struct spi_master *master, | |||
329 | mcfqspi_cs_select(mcfqspi, spi->chip_select, cs_high); | 329 | mcfqspi_cs_select(mcfqspi, spi->chip_select, cs_high); |
330 | 330 | ||
331 | mcfqspi_wr_qir(mcfqspi, MCFQSPI_QIR_SPIFE); | 331 | mcfqspi_wr_qir(mcfqspi, MCFQSPI_QIR_SPIFE); |
332 | if ((t->bits_per_word ? t->bits_per_word : | 332 | if (t->bits_per_word == 8) |
333 | spi->bits_per_word) == 8) | ||
334 | mcfqspi_transfer_msg8(mcfqspi, t->len, t->tx_buf, | 333 | mcfqspi_transfer_msg8(mcfqspi, t->len, t->tx_buf, |
335 | t->rx_buf); | 334 | t->rx_buf); |
336 | else | 335 | else |
diff --git a/drivers/spi/spi-davinci.c b/drivers/spi/spi-davinci.c index 13661e129d96..8234d2259722 100644 --- a/drivers/spi/spi-davinci.c +++ b/drivers/spi/spi-davinci.c | |||
@@ -28,6 +28,8 @@ | |||
28 | #include <linux/dmaengine.h> | 28 | #include <linux/dmaengine.h> |
29 | #include <linux/dma-mapping.h> | 29 | #include <linux/dma-mapping.h> |
30 | #include <linux/edma.h> | 30 | #include <linux/edma.h> |
31 | #include <linux/of.h> | ||
32 | #include <linux/of_device.h> | ||
31 | #include <linux/spi/spi.h> | 33 | #include <linux/spi/spi.h> |
32 | #include <linux/spi/spi_bitbang.h> | 34 | #include <linux/spi/spi_bitbang.h> |
33 | #include <linux/slab.h> | 35 | #include <linux/slab.h> |
@@ -135,7 +137,7 @@ struct davinci_spi { | |||
135 | int dma_rx_chnum; | 137 | int dma_rx_chnum; |
136 | int dma_tx_chnum; | 138 | int dma_tx_chnum; |
137 | 139 | ||
138 | struct davinci_spi_platform_data *pdata; | 140 | struct davinci_spi_platform_data pdata; |
139 | 141 | ||
140 | void (*get_rx)(u32 rx_data, struct davinci_spi *); | 142 | void (*get_rx)(u32 rx_data, struct davinci_spi *); |
141 | u32 (*get_tx)(struct davinci_spi *); | 143 | u32 (*get_tx)(struct davinci_spi *); |
@@ -213,7 +215,7 @@ static void davinci_spi_chipselect(struct spi_device *spi, int value) | |||
213 | bool gpio_chipsel = false; | 215 | bool gpio_chipsel = false; |
214 | 216 | ||
215 | dspi = spi_master_get_devdata(spi->master); | 217 | dspi = spi_master_get_devdata(spi->master); |
216 | pdata = dspi->pdata; | 218 | pdata = &dspi->pdata; |
217 | 219 | ||
218 | if (pdata->chip_sel && chip_sel < pdata->num_chipselect && | 220 | if (pdata->chip_sel && chip_sel < pdata->num_chipselect && |
219 | pdata->chip_sel[chip_sel] != SPI_INTERN_CS) | 221 | pdata->chip_sel[chip_sel] != SPI_INTERN_CS) |
@@ -392,7 +394,7 @@ static int davinci_spi_setup(struct spi_device *spi) | |||
392 | struct davinci_spi_platform_data *pdata; | 394 | struct davinci_spi_platform_data *pdata; |
393 | 395 | ||
394 | dspi = spi_master_get_devdata(spi->master); | 396 | dspi = spi_master_get_devdata(spi->master); |
395 | pdata = dspi->pdata; | 397 | pdata = &dspi->pdata; |
396 | 398 | ||
397 | /* if bits per word length is zero then set it default 8 */ | 399 | /* if bits per word length is zero then set it default 8 */ |
398 | if (!spi->bits_per_word) | 400 | if (!spi->bits_per_word) |
@@ -534,7 +536,7 @@ static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t) | |||
534 | struct scatterlist sg_rx, sg_tx; | 536 | struct scatterlist sg_rx, sg_tx; |
535 | 537 | ||
536 | dspi = spi_master_get_devdata(spi->master); | 538 | dspi = spi_master_get_devdata(spi->master); |
537 | pdata = dspi->pdata; | 539 | pdata = &dspi->pdata; |
538 | spicfg = (struct davinci_spi_config *)spi->controller_data; | 540 | spicfg = (struct davinci_spi_config *)spi->controller_data; |
539 | if (!spicfg) | 541 | if (!spicfg) |
540 | spicfg = &davinci_spi_default_cfg; | 542 | spicfg = &davinci_spi_default_cfg; |
@@ -700,6 +702,19 @@ err_alloc_dummy_buf: | |||
700 | } | 702 | } |
701 | 703 | ||
702 | /** | 704 | /** |
705 | * dummy_thread_fn - dummy thread function | ||
706 | * @irq: IRQ number for this SPI Master | ||
707 | * @context_data: structure for SPI Master controller davinci_spi | ||
708 | * | ||
709 | * This is to satisfy the request_threaded_irq() API so that the irq | ||
710 | * handler is called in interrupt context. | ||
711 | */ | ||
712 | static irqreturn_t dummy_thread_fn(s32 irq, void *data) | ||
713 | { | ||
714 | return IRQ_HANDLED; | ||
715 | } | ||
716 | |||
717 | /** | ||
703 | * davinci_spi_irq - Interrupt handler for SPI Master Controller | 718 | * davinci_spi_irq - Interrupt handler for SPI Master Controller |
704 | * @irq: IRQ number for this SPI Master | 719 | * @irq: IRQ number for this SPI Master |
705 | * @context_data: structure for SPI Master controller davinci_spi | 720 | * @context_data: structure for SPI Master controller davinci_spi |
@@ -758,6 +773,70 @@ rx_dma_failed: | |||
758 | return r; | 773 | return r; |
759 | } | 774 | } |
760 | 775 | ||
776 | #if defined(CONFIG_OF) | ||
777 | static const struct of_device_id davinci_spi_of_match[] = { | ||
778 | { | ||
779 | .compatible = "ti,dm644x-spi", | ||
780 | }, | ||
781 | { | ||
782 | .compatible = "ti,da8xx-spi", | ||
783 | .data = (void *)SPI_VERSION_2, | ||
784 | }, | ||
785 | { }, | ||
786 | }; | ||
787 | MODULE_DEVICE_TABLE(of, davini_spi_of_match); | ||
788 | |||
789 | /** | ||
790 | * spi_davinci_get_pdata - Get platform data from DTS binding | ||
791 | * @pdev: ptr to platform data | ||
792 | * @dspi: ptr to driver data | ||
793 | * | ||
794 | * Parses and populates pdata in dspi from device tree bindings. | ||
795 | * | ||
796 | * NOTE: Not all platform data params are supported currently. | ||
797 | */ | ||
798 | static int spi_davinci_get_pdata(struct platform_device *pdev, | ||
799 | struct davinci_spi *dspi) | ||
800 | { | ||
801 | struct device_node *node = pdev->dev.of_node; | ||
802 | struct davinci_spi_platform_data *pdata; | ||
803 | unsigned int num_cs, intr_line = 0; | ||
804 | const struct of_device_id *match; | ||
805 | |||
806 | pdata = &dspi->pdata; | ||
807 | |||
808 | pdata->version = SPI_VERSION_1; | ||
809 | match = of_match_device(of_match_ptr(davinci_spi_of_match), | ||
810 | &pdev->dev); | ||
811 | if (!match) | ||
812 | return -ENODEV; | ||
813 | |||
814 | /* match data has the SPI version number for SPI_VERSION_2 */ | ||
815 | if (match->data == (void *)SPI_VERSION_2) | ||
816 | pdata->version = SPI_VERSION_2; | ||
817 | |||
818 | /* | ||
819 | * default num_cs is 1 and all chipsel are internal to the chip | ||
820 | * indicated by chip_sel being NULL. GPIO based CS is not | ||
821 | * supported yet in DT bindings. | ||
822 | */ | ||
823 | num_cs = 1; | ||
824 | of_property_read_u32(node, "num-cs", &num_cs); | ||
825 | pdata->num_chipselect = num_cs; | ||
826 | of_property_read_u32(node, "ti,davinci-spi-intr-line", &intr_line); | ||
827 | pdata->intr_line = intr_line; | ||
828 | return 0; | ||
829 | } | ||
830 | #else | ||
831 | #define davinci_spi_of_match NULL | ||
832 | static struct davinci_spi_platform_data | ||
833 | *spi_davinci_get_pdata(struct platform_device *pdev, | ||
834 | struct davinci_spi *dspi) | ||
835 | { | ||
836 | return -ENODEV; | ||
837 | } | ||
838 | #endif | ||
839 | |||
761 | /** | 840 | /** |
762 | * davinci_spi_probe - probe function for SPI Master Controller | 841 | * davinci_spi_probe - probe function for SPI Master Controller |
763 | * @pdev: platform_device structure which contains plateform specific data | 842 | * @pdev: platform_device structure which contains plateform specific data |
@@ -780,12 +859,6 @@ static int davinci_spi_probe(struct platform_device *pdev) | |||
780 | int i = 0, ret = 0; | 859 | int i = 0, ret = 0; |
781 | u32 spipc0; | 860 | u32 spipc0; |
782 | 861 | ||
783 | pdata = pdev->dev.platform_data; | ||
784 | if (pdata == NULL) { | ||
785 | ret = -ENODEV; | ||
786 | goto err; | ||
787 | } | ||
788 | |||
789 | master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi)); | 862 | master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi)); |
790 | if (master == NULL) { | 863 | if (master == NULL) { |
791 | ret = -ENOMEM; | 864 | ret = -ENOMEM; |
@@ -800,6 +873,19 @@ static int davinci_spi_probe(struct platform_device *pdev) | |||
800 | goto free_master; | 873 | goto free_master; |
801 | } | 874 | } |
802 | 875 | ||
876 | if (pdev->dev.platform_data) { | ||
877 | pdata = pdev->dev.platform_data; | ||
878 | dspi->pdata = *pdata; | ||
879 | } else { | ||
880 | /* update dspi pdata with that from the DT */ | ||
881 | ret = spi_davinci_get_pdata(pdev, dspi); | ||
882 | if (ret < 0) | ||
883 | goto free_master; | ||
884 | } | ||
885 | |||
886 | /* pdata in dspi is now updated and point pdata to that */ | ||
887 | pdata = &dspi->pdata; | ||
888 | |||
803 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 889 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
804 | if (r == NULL) { | 890 | if (r == NULL) { |
805 | ret = -ENOENT; | 891 | ret = -ENOENT; |
@@ -807,7 +893,6 @@ static int davinci_spi_probe(struct platform_device *pdev) | |||
807 | } | 893 | } |
808 | 894 | ||
809 | dspi->pbase = r->start; | 895 | dspi->pbase = r->start; |
810 | dspi->pdata = pdata; | ||
811 | 896 | ||
812 | mem = request_mem_region(r->start, resource_size(r), pdev->name); | 897 | mem = request_mem_region(r->start, resource_size(r), pdev->name); |
813 | if (mem == NULL) { | 898 | if (mem == NULL) { |
@@ -827,8 +912,8 @@ static int davinci_spi_probe(struct platform_device *pdev) | |||
827 | goto unmap_io; | 912 | goto unmap_io; |
828 | } | 913 | } |
829 | 914 | ||
830 | ret = request_irq(dspi->irq, davinci_spi_irq, 0, dev_name(&pdev->dev), | 915 | ret = request_threaded_irq(dspi->irq, davinci_spi_irq, dummy_thread_fn, |
831 | dspi); | 916 | 0, dev_name(&pdev->dev), dspi); |
832 | if (ret) | 917 | if (ret) |
833 | goto unmap_io; | 918 | goto unmap_io; |
834 | 919 | ||
@@ -843,8 +928,9 @@ static int davinci_spi_probe(struct platform_device *pdev) | |||
843 | ret = -ENODEV; | 928 | ret = -ENODEV; |
844 | goto put_master; | 929 | goto put_master; |
845 | } | 930 | } |
846 | clk_enable(dspi->clk); | 931 | clk_prepare_enable(dspi->clk); |
847 | 932 | ||
933 | master->dev.of_node = pdev->dev.of_node; | ||
848 | master->bus_num = pdev->id; | 934 | master->bus_num = pdev->id; |
849 | master->num_chipselect = pdata->num_chipselect; | 935 | master->num_chipselect = pdata->num_chipselect; |
850 | master->setup = davinci_spi_setup; | 936 | master->setup = davinci_spi_setup; |
@@ -927,7 +1013,7 @@ free_dma: | |||
927 | dma_release_channel(dspi->dma_rx); | 1013 | dma_release_channel(dspi->dma_rx); |
928 | dma_release_channel(dspi->dma_tx); | 1014 | dma_release_channel(dspi->dma_tx); |
929 | free_clk: | 1015 | free_clk: |
930 | clk_disable(dspi->clk); | 1016 | clk_disable_unprepare(dspi->clk); |
931 | clk_put(dspi->clk); | 1017 | clk_put(dspi->clk); |
932 | put_master: | 1018 | put_master: |
933 | spi_master_put(master); | 1019 | spi_master_put(master); |
@@ -963,7 +1049,7 @@ static int davinci_spi_remove(struct platform_device *pdev) | |||
963 | 1049 | ||
964 | spi_bitbang_stop(&dspi->bitbang); | 1050 | spi_bitbang_stop(&dspi->bitbang); |
965 | 1051 | ||
966 | clk_disable(dspi->clk); | 1052 | clk_disable_unprepare(dspi->clk); |
967 | clk_put(dspi->clk); | 1053 | clk_put(dspi->clk); |
968 | spi_master_put(master); | 1054 | spi_master_put(master); |
969 | free_irq(dspi->irq, dspi); | 1055 | free_irq(dspi->irq, dspi); |
@@ -978,6 +1064,7 @@ static struct platform_driver davinci_spi_driver = { | |||
978 | .driver = { | 1064 | .driver = { |
979 | .name = "spi_davinci", | 1065 | .name = "spi_davinci", |
980 | .owner = THIS_MODULE, | 1066 | .owner = THIS_MODULE, |
1067 | .of_match_table = davinci_spi_of_match, | ||
981 | }, | 1068 | }, |
982 | .probe = davinci_spi_probe, | 1069 | .probe = davinci_spi_probe, |
983 | .remove = davinci_spi_remove, | 1070 | .remove = davinci_spi_remove, |
diff --git a/drivers/spi/spi-ep93xx.c b/drivers/spi/spi-ep93xx.c index acb1e1935c5a..aecbff16ad60 100644 --- a/drivers/spi/spi-ep93xx.c +++ b/drivers/spi/spi-ep93xx.c | |||
@@ -446,7 +446,7 @@ static inline int bits_per_word(const struct ep93xx_spi *espi) | |||
446 | struct spi_message *msg = espi->current_msg; | 446 | struct spi_message *msg = espi->current_msg; |
447 | struct spi_transfer *t = msg->state; | 447 | struct spi_transfer *t = msg->state; |
448 | 448 | ||
449 | return t->bits_per_word ? t->bits_per_word : msg->spi->bits_per_word; | 449 | return t->bits_per_word; |
450 | } | 450 | } |
451 | 451 | ||
452 | static void ep93xx_do_write(struct ep93xx_spi *espi, struct spi_transfer *t) | 452 | static void ep93xx_do_write(struct ep93xx_spi *espi, struct spi_transfer *t) |
diff --git a/drivers/spi/spi-falcon.c b/drivers/spi/spi-falcon.c index 6a6f62ec2840..c7a74f0ef892 100644 --- a/drivers/spi/spi-falcon.c +++ b/drivers/spi/spi-falcon.c | |||
@@ -398,7 +398,7 @@ static int falcon_sflash_xfer_one(struct spi_master *master, | |||
398 | } | 398 | } |
399 | 399 | ||
400 | m->status = ret; | 400 | m->status = ret; |
401 | m->complete(m->context); | 401 | spi_finalize_current_message(master); |
402 | 402 | ||
403 | return 0; | 403 | return 0; |
404 | } | 404 | } |
@@ -423,6 +423,7 @@ static int falcon_sflash_probe(struct platform_device *pdev) | |||
423 | 423 | ||
424 | master->mode_bits = SPI_MODE_3; | 424 | master->mode_bits = SPI_MODE_3; |
425 | master->num_chipselect = 1; | 425 | master->num_chipselect = 1; |
426 | master->flags = SPI_MASTER_HALF_DUPLEX; | ||
426 | master->bus_num = -1; | 427 | master->bus_num = -1; |
427 | master->setup = falcon_sflash_setup; | 428 | master->setup = falcon_sflash_setup; |
428 | master->prepare_transfer_hardware = falcon_sflash_prepare_xfer; | 429 | master->prepare_transfer_hardware = falcon_sflash_prepare_xfer; |
diff --git a/drivers/spi/spi-fsl-spi.c b/drivers/spi/spi-fsl-spi.c index 1a7f6359d998..086a9eef2e05 100644 --- a/drivers/spi/spi-fsl-spi.c +++ b/drivers/spi/spi-fsl-spi.c | |||
@@ -947,12 +947,12 @@ static int of_fsl_spi_get_chipselects(struct device *dev) | |||
947 | struct device_node *np = dev->of_node; | 947 | struct device_node *np = dev->of_node; |
948 | struct fsl_spi_platform_data *pdata = dev->platform_data; | 948 | struct fsl_spi_platform_data *pdata = dev->platform_data; |
949 | struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata); | 949 | struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata); |
950 | unsigned int ngpios; | 950 | int ngpios; |
951 | int i = 0; | 951 | int i = 0; |
952 | int ret; | 952 | int ret; |
953 | 953 | ||
954 | ngpios = of_gpio_count(np); | 954 | ngpios = of_gpio_count(np); |
955 | if (!ngpios) { | 955 | if (ngpios <= 0) { |
956 | /* | 956 | /* |
957 | * SPI w/o chip-select line. One SPI device is still permitted | 957 | * SPI w/o chip-select line. One SPI device is still permitted |
958 | * though. | 958 | * though. |
diff --git a/drivers/spi/spi-gpio.c b/drivers/spi/spi-gpio.c index c7cf0b7a069b..9ddef55a7165 100644 --- a/drivers/spi/spi-gpio.c +++ b/drivers/spi/spi-gpio.c | |||
@@ -365,9 +365,26 @@ static int spi_gpio_probe_dt(struct platform_device *pdev) | |||
365 | if (!pdata) | 365 | if (!pdata) |
366 | return -ENOMEM; | 366 | return -ENOMEM; |
367 | 367 | ||
368 | pdata->sck = of_get_named_gpio(np, "gpio-sck", 0); | 368 | ret = of_get_named_gpio(np, "gpio-sck", 0); |
369 | pdata->miso = of_get_named_gpio(np, "gpio-miso", 0); | 369 | if (ret < 0) { |
370 | pdata->mosi = of_get_named_gpio(np, "gpio-mosi", 0); | 370 | dev_err(&pdev->dev, "gpio-sck property not found\n"); |
371 | goto error_free; | ||
372 | } | ||
373 | pdata->sck = ret; | ||
374 | |||
375 | ret = of_get_named_gpio(np, "gpio-miso", 0); | ||
376 | if (ret < 0) { | ||
377 | dev_info(&pdev->dev, "gpio-miso property not found, switching to no-rx mode\n"); | ||
378 | pdata->miso = SPI_GPIO_NO_MISO; | ||
379 | } else | ||
380 | pdata->miso = ret; | ||
381 | |||
382 | ret = of_get_named_gpio(np, "gpio-mosi", 0); | ||
383 | if (ret < 0) { | ||
384 | dev_info(&pdev->dev, "gpio-mosi property not found, switching to no-tx mode\n"); | ||
385 | pdata->mosi = SPI_GPIO_NO_MOSI; | ||
386 | } else | ||
387 | pdata->mosi = ret; | ||
371 | 388 | ||
372 | ret = of_property_read_u32(np, "num-chipselects", &tmp); | 389 | ret = of_property_read_u32(np, "num-chipselects", &tmp); |
373 | if (ret < 0) { | 390 | if (ret < 0) { |
diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c index 904913290aa5..0befeeb522f4 100644 --- a/drivers/spi/spi-imx.c +++ b/drivers/spi/spi-imx.c | |||
@@ -949,3 +949,4 @@ module_platform_driver(spi_imx_driver); | |||
949 | MODULE_DESCRIPTION("SPI Master Controller driver"); | 949 | MODULE_DESCRIPTION("SPI Master Controller driver"); |
950 | MODULE_AUTHOR("Sascha Hauer, Pengutronix"); | 950 | MODULE_AUTHOR("Sascha Hauer, Pengutronix"); |
951 | MODULE_LICENSE("GPL"); | 951 | MODULE_LICENSE("GPL"); |
952 | MODULE_ALIAS("platform:" DRIVER_NAME); | ||
diff --git a/drivers/spi/spi-mpc512x-psc.c b/drivers/spi/spi-mpc512x-psc.c index cb3a3106bd4f..89480b281d74 100644 --- a/drivers/spi/spi-mpc512x-psc.c +++ b/drivers/spi/spi-mpc512x-psc.c | |||
@@ -438,6 +438,7 @@ static int mpc512x_psc_spi_do_probe(struct device *dev, u32 regaddr, | |||
438 | master->num_chipselect = pdata->max_chipselect; | 438 | master->num_chipselect = pdata->max_chipselect; |
439 | } | 439 | } |
440 | 440 | ||
441 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST; | ||
441 | master->setup = mpc512x_psc_spi_setup; | 442 | master->setup = mpc512x_psc_spi_setup; |
442 | master->transfer = mpc512x_psc_spi_transfer; | 443 | master->transfer = mpc512x_psc_spi_transfer; |
443 | master->cleanup = mpc512x_psc_spi_cleanup; | 444 | master->cleanup = mpc512x_psc_spi_cleanup; |
@@ -522,17 +523,11 @@ static int mpc512x_psc_spi_of_probe(struct platform_device *op) | |||
522 | regaddr64 = of_translate_address(op->dev.of_node, regaddr_p); | 523 | regaddr64 = of_translate_address(op->dev.of_node, regaddr_p); |
523 | 524 | ||
524 | /* get PSC id (0..11, used by port_config) */ | 525 | /* get PSC id (0..11, used by port_config) */ |
525 | if (op->dev.platform_data == NULL) { | 526 | id = of_alias_get_id(op->dev.of_node, "spi"); |
526 | const u32 *psc_nump; | 527 | if (id < 0) { |
527 | 528 | dev_err(&op->dev, "no alias id for %s\n", | |
528 | psc_nump = of_get_property(op->dev.of_node, "cell-index", NULL); | 529 | op->dev.of_node->full_name); |
529 | if (!psc_nump || *psc_nump > 11) { | 530 | return id; |
530 | dev_err(&op->dev, "mpc512x_psc_spi: Device node %s " | ||
531 | "has invalid cell-index property\n", | ||
532 | op->dev.of_node->full_name); | ||
533 | return -EINVAL; | ||
534 | } | ||
535 | id = *psc_nump; | ||
536 | } | 531 | } |
537 | 532 | ||
538 | return mpc512x_psc_spi_do_probe(&op->dev, (u32) regaddr64, (u32) size64, | 533 | return mpc512x_psc_spi_do_probe(&op->dev, (u32) regaddr64, (u32) size64, |
diff --git a/drivers/spi/spi-mxs.c b/drivers/spi/spi-mxs.c index a3ede249d05d..e3d8b3197d22 100644 --- a/drivers/spi/spi-mxs.c +++ b/drivers/spi/spi-mxs.c | |||
@@ -241,6 +241,7 @@ static int mxs_spi_txrx_dma(struct mxs_spi *spi, int cs, | |||
241 | INIT_COMPLETION(spi->c); | 241 | INIT_COMPLETION(spi->c); |
242 | 242 | ||
243 | ctrl0 = readl(ssp->base + HW_SSP_CTRL0); | 243 | ctrl0 = readl(ssp->base + HW_SSP_CTRL0); |
244 | ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT; | ||
244 | ctrl0 |= BM_SSP_CTRL0_DATA_XFER | mxs_spi_cs_to_reg(cs); | 245 | ctrl0 |= BM_SSP_CTRL0_DATA_XFER | mxs_spi_cs_to_reg(cs); |
245 | 246 | ||
246 | if (*first) | 247 | if (*first) |
@@ -256,8 +257,10 @@ static int mxs_spi_txrx_dma(struct mxs_spi *spi, int cs, | |||
256 | if ((sg_count + 1 == sgs) && *last) | 257 | if ((sg_count + 1 == sgs) && *last) |
257 | ctrl0 |= BM_SSP_CTRL0_IGNORE_CRC; | 258 | ctrl0 |= BM_SSP_CTRL0_IGNORE_CRC; |
258 | 259 | ||
259 | if (ssp->devid == IMX23_SSP) | 260 | if (ssp->devid == IMX23_SSP) { |
261 | ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT; | ||
260 | ctrl0 |= min; | 262 | ctrl0 |= min; |
263 | } | ||
261 | 264 | ||
262 | dma_xfer[sg_count].pio[0] = ctrl0; | 265 | dma_xfer[sg_count].pio[0] = ctrl0; |
263 | dma_xfer[sg_count].pio[3] = min; | 266 | dma_xfer[sg_count].pio[3] = min; |
diff --git a/drivers/spi/spi-oc-tiny.c b/drivers/spi/spi-oc-tiny.c index 432e66ec3088..cb2e284bd814 100644 --- a/drivers/spi/spi-oc-tiny.c +++ b/drivers/spi/spi-oc-tiny.c | |||
@@ -54,7 +54,7 @@ struct tiny_spi { | |||
54 | unsigned int txc, rxc; | 54 | unsigned int txc, rxc; |
55 | const u8 *txp; | 55 | const u8 *txp; |
56 | u8 *rxp; | 56 | u8 *rxp; |
57 | unsigned int gpio_cs_count; | 57 | int gpio_cs_count; |
58 | int *gpio_cs; | 58 | int *gpio_cs; |
59 | }; | 59 | }; |
60 | 60 | ||
@@ -74,7 +74,7 @@ static void tiny_spi_chipselect(struct spi_device *spi, int is_active) | |||
74 | { | 74 | { |
75 | struct tiny_spi *hw = tiny_spi_to_hw(spi); | 75 | struct tiny_spi *hw = tiny_spi_to_hw(spi); |
76 | 76 | ||
77 | if (hw->gpio_cs_count) { | 77 | if (hw->gpio_cs_count > 0) { |
78 | gpio_set_value(hw->gpio_cs[spi->chip_select], | 78 | gpio_set_value(hw->gpio_cs[spi->chip_select], |
79 | (spi->mode & SPI_CS_HIGH) ? is_active : !is_active); | 79 | (spi->mode & SPI_CS_HIGH) ? is_active : !is_active); |
80 | } | 80 | } |
@@ -254,7 +254,7 @@ static int tiny_spi_of_probe(struct platform_device *pdev) | |||
254 | if (!np) | 254 | if (!np) |
255 | return 0; | 255 | return 0; |
256 | hw->gpio_cs_count = of_gpio_count(np); | 256 | hw->gpio_cs_count = of_gpio_count(np); |
257 | if (hw->gpio_cs_count) { | 257 | if (hw->gpio_cs_count > 0) { |
258 | hw->gpio_cs = devm_kzalloc(&pdev->dev, | 258 | hw->gpio_cs = devm_kzalloc(&pdev->dev, |
259 | hw->gpio_cs_count * sizeof(unsigned int), | 259 | hw->gpio_cs_count * sizeof(unsigned int), |
260 | GFP_KERNEL); | 260 | GFP_KERNEL); |
@@ -352,7 +352,7 @@ static int tiny_spi_probe(struct platform_device *pdev) | |||
352 | goto exit_gpio; | 352 | goto exit_gpio; |
353 | gpio_direction_output(hw->gpio_cs[i], 1); | 353 | gpio_direction_output(hw->gpio_cs[i], 1); |
354 | } | 354 | } |
355 | hw->bitbang.master->num_chipselect = max(1U, hw->gpio_cs_count); | 355 | hw->bitbang.master->num_chipselect = max(1, hw->gpio_cs_count); |
356 | 356 | ||
357 | /* register our spi controller */ | 357 | /* register our spi controller */ |
358 | err = spi_bitbang_start(&hw->bitbang); | 358 | err = spi_bitbang_start(&hw->bitbang); |
diff --git a/drivers/spi/spi-omap-100k.c b/drivers/spi/spi-omap-100k.c index 3aef7fa7d5b8..78d29a18dcc4 100644 --- a/drivers/spi/spi-omap-100k.c +++ b/drivers/spi/spi-omap-100k.c | |||
@@ -481,7 +481,7 @@ static int omap1_spi100k_transfer(struct spi_device *spi, struct spi_message *m) | |||
481 | return 0; | 481 | return 0; |
482 | } | 482 | } |
483 | 483 | ||
484 | static int __init omap1_spi100k_reset(struct omap1_spi100k *spi100k) | 484 | static int omap1_spi100k_reset(struct omap1_spi100k *spi100k) |
485 | { | 485 | { |
486 | return 0; | 486 | return 0; |
487 | } | 487 | } |
@@ -560,7 +560,7 @@ err1: | |||
560 | return status; | 560 | return status; |
561 | } | 561 | } |
562 | 562 | ||
563 | static int __exit omap1_spi100k_remove(struct platform_device *pdev) | 563 | static int omap1_spi100k_remove(struct platform_device *pdev) |
564 | { | 564 | { |
565 | struct spi_master *master; | 565 | struct spi_master *master; |
566 | struct omap1_spi100k *spi100k; | 566 | struct omap1_spi100k *spi100k; |
@@ -604,7 +604,7 @@ static struct platform_driver omap1_spi100k_driver = { | |||
604 | .name = "omap1_spi100k", | 604 | .name = "omap1_spi100k", |
605 | .owner = THIS_MODULE, | 605 | .owner = THIS_MODULE, |
606 | }, | 606 | }, |
607 | .remove = __exit_p(omap1_spi100k_remove), | 607 | .remove = omap1_spi100k_remove, |
608 | }; | 608 | }; |
609 | 609 | ||
610 | 610 | ||
diff --git a/drivers/spi/spi-omap-uwire.c b/drivers/spi/spi-omap-uwire.c index 0a94d9dc9c31..102b233b50c4 100644 --- a/drivers/spi/spi-omap-uwire.c +++ b/drivers/spi/spi-omap-uwire.c | |||
@@ -476,7 +476,7 @@ static void uwire_off(struct uwire_spi *uwire) | |||
476 | spi_master_put(uwire->bitbang.master); | 476 | spi_master_put(uwire->bitbang.master); |
477 | } | 477 | } |
478 | 478 | ||
479 | static int __init uwire_probe(struct platform_device *pdev) | 479 | static int uwire_probe(struct platform_device *pdev) |
480 | { | 480 | { |
481 | struct spi_master *master; | 481 | struct spi_master *master; |
482 | struct uwire_spi *uwire; | 482 | struct uwire_spi *uwire; |
@@ -536,7 +536,7 @@ static int __init uwire_probe(struct platform_device *pdev) | |||
536 | return status; | 536 | return status; |
537 | } | 537 | } |
538 | 538 | ||
539 | static int __exit uwire_remove(struct platform_device *pdev) | 539 | static int uwire_remove(struct platform_device *pdev) |
540 | { | 540 | { |
541 | struct uwire_spi *uwire = dev_get_drvdata(&pdev->dev); | 541 | struct uwire_spi *uwire = dev_get_drvdata(&pdev->dev); |
542 | int status; | 542 | int status; |
@@ -557,7 +557,7 @@ static struct platform_driver uwire_driver = { | |||
557 | .name = "omap_uwire", | 557 | .name = "omap_uwire", |
558 | .owner = THIS_MODULE, | 558 | .owner = THIS_MODULE, |
559 | }, | 559 | }, |
560 | .remove = __exit_p(uwire_remove), | 560 | .remove = uwire_remove, |
561 | // suspend ... unuse ck | 561 | // suspend ... unuse ck |
562 | // resume ... use ck | 562 | // resume ... use ck |
563 | }; | 563 | }; |
diff --git a/drivers/spi/spi-omap2-mcspi.c b/drivers/spi/spi-omap2-mcspi.c index b610f522ca44..69945b014c96 100644 --- a/drivers/spi/spi-omap2-mcspi.c +++ b/drivers/spi/spi-omap2-mcspi.c | |||
@@ -298,10 +298,10 @@ static void omap2_mcspi_rx_callback(void *data) | |||
298 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); | 298 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); |
299 | struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | 299 | struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; |
300 | 300 | ||
301 | complete(&mcspi_dma->dma_rx_completion); | ||
302 | |||
303 | /* We must disable the DMA RX request */ | 301 | /* We must disable the DMA RX request */ |
304 | omap2_mcspi_set_dma_req(spi, 1, 0); | 302 | omap2_mcspi_set_dma_req(spi, 1, 0); |
303 | |||
304 | complete(&mcspi_dma->dma_rx_completion); | ||
305 | } | 305 | } |
306 | 306 | ||
307 | static void omap2_mcspi_tx_callback(void *data) | 307 | static void omap2_mcspi_tx_callback(void *data) |
@@ -310,10 +310,10 @@ static void omap2_mcspi_tx_callback(void *data) | |||
310 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); | 310 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); |
311 | struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | 311 | struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; |
312 | 312 | ||
313 | complete(&mcspi_dma->dma_tx_completion); | ||
314 | |||
315 | /* We must disable the DMA TX request */ | 313 | /* We must disable the DMA TX request */ |
316 | omap2_mcspi_set_dma_req(spi, 0, 0); | 314 | omap2_mcspi_set_dma_req(spi, 0, 0); |
315 | |||
316 | complete(&mcspi_dma->dma_tx_completion); | ||
317 | } | 317 | } |
318 | 318 | ||
319 | static void omap2_mcspi_tx_dma(struct spi_device *spi, | 319 | static void omap2_mcspi_tx_dma(struct spi_device *spi, |
@@ -927,6 +927,7 @@ static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m) | |||
927 | 927 | ||
928 | struct spi_device *spi; | 928 | struct spi_device *spi; |
929 | struct spi_transfer *t = NULL; | 929 | struct spi_transfer *t = NULL; |
930 | struct spi_master *master; | ||
930 | int cs_active = 0; | 931 | int cs_active = 0; |
931 | struct omap2_mcspi_cs *cs; | 932 | struct omap2_mcspi_cs *cs; |
932 | struct omap2_mcspi_device_config *cd; | 933 | struct omap2_mcspi_device_config *cd; |
@@ -935,6 +936,7 @@ static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m) | |||
935 | u32 chconf; | 936 | u32 chconf; |
936 | 937 | ||
937 | spi = m->spi; | 938 | spi = m->spi; |
939 | master = spi->master; | ||
938 | cs = spi->controller_state; | 940 | cs = spi->controller_state; |
939 | cd = spi->controller_data; | 941 | cd = spi->controller_data; |
940 | 942 | ||
@@ -952,6 +954,14 @@ static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m) | |||
952 | if (!t->speed_hz && !t->bits_per_word) | 954 | if (!t->speed_hz && !t->bits_per_word) |
953 | par_override = 0; | 955 | par_override = 0; |
954 | } | 956 | } |
957 | if (cd && cd->cs_per_word) { | ||
958 | chconf = mcspi->ctx.modulctrl; | ||
959 | chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE; | ||
960 | mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf); | ||
961 | mcspi->ctx.modulctrl = | ||
962 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL); | ||
963 | } | ||
964 | |||
955 | 965 | ||
956 | if (!cs_active) { | 966 | if (!cs_active) { |
957 | omap2_mcspi_force_cs(spi, 1); | 967 | omap2_mcspi_force_cs(spi, 1); |
@@ -1013,6 +1023,14 @@ static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m) | |||
1013 | if (cs_active) | 1023 | if (cs_active) |
1014 | omap2_mcspi_force_cs(spi, 0); | 1024 | omap2_mcspi_force_cs(spi, 0); |
1015 | 1025 | ||
1026 | if (cd && cd->cs_per_word) { | ||
1027 | chconf = mcspi->ctx.modulctrl; | ||
1028 | chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE; | ||
1029 | mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf); | ||
1030 | mcspi->ctx.modulctrl = | ||
1031 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL); | ||
1032 | } | ||
1033 | |||
1016 | omap2_mcspi_set_enable(spi, 0); | 1034 | omap2_mcspi_set_enable(spi, 0); |
1017 | 1035 | ||
1018 | m->status = status; | 1036 | m->status = status; |
@@ -1020,7 +1038,7 @@ static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m) | |||
1020 | } | 1038 | } |
1021 | 1039 | ||
1022 | static int omap2_mcspi_transfer_one_message(struct spi_master *master, | 1040 | static int omap2_mcspi_transfer_one_message(struct spi_master *master, |
1023 | struct spi_message *m) | 1041 | struct spi_message *m) |
1024 | { | 1042 | { |
1025 | struct omap2_mcspi *mcspi; | 1043 | struct omap2_mcspi *mcspi; |
1026 | struct spi_transfer *t; | 1044 | struct spi_transfer *t; |
@@ -1041,7 +1059,7 @@ static int omap2_mcspi_transfer_one_message(struct spi_master *master, | |||
1041 | || (len && !(rx_buf || tx_buf)) | 1059 | || (len && !(rx_buf || tx_buf)) |
1042 | || (t->bits_per_word && | 1060 | || (t->bits_per_word && |
1043 | ( t->bits_per_word < 4 | 1061 | ( t->bits_per_word < 4 |
1044 | || t->bits_per_word > 32))) { | 1062 | || t->bits_per_word > 32))) { |
1045 | dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n", | 1063 | dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n", |
1046 | t->speed_hz, | 1064 | t->speed_hz, |
1047 | len, | 1065 | len, |
@@ -1052,8 +1070,8 @@ static int omap2_mcspi_transfer_one_message(struct spi_master *master, | |||
1052 | } | 1070 | } |
1053 | if (t->speed_hz && t->speed_hz < (OMAP2_MCSPI_MAX_FREQ >> 15)) { | 1071 | if (t->speed_hz && t->speed_hz < (OMAP2_MCSPI_MAX_FREQ >> 15)) { |
1054 | dev_dbg(mcspi->dev, "speed_hz %d below minimum %d Hz\n", | 1072 | dev_dbg(mcspi->dev, "speed_hz %d below minimum %d Hz\n", |
1055 | t->speed_hz, | 1073 | t->speed_hz, |
1056 | OMAP2_MCSPI_MAX_FREQ >> 15); | 1074 | OMAP2_MCSPI_MAX_FREQ >> 15); |
1057 | return -EINVAL; | 1075 | return -EINVAL; |
1058 | } | 1076 | } |
1059 | 1077 | ||
@@ -1099,7 +1117,7 @@ static int omap2_mcspi_master_setup(struct omap2_mcspi *mcspi) | |||
1099 | return ret; | 1117 | return ret; |
1100 | 1118 | ||
1101 | mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, | 1119 | mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, |
1102 | OMAP2_MCSPI_WAKEUPENABLE_WKEN); | 1120 | OMAP2_MCSPI_WAKEUPENABLE_WKEN); |
1103 | ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN; | 1121 | ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN; |
1104 | 1122 | ||
1105 | omap2_mcspi_set_master_mode(master); | 1123 | omap2_mcspi_set_master_mode(master); |
@@ -1228,7 +1246,7 @@ static int omap2_mcspi_probe(struct platform_device *pdev) | |||
1228 | 1246 | ||
1229 | sprintf(dma_ch_name, "rx%d", i); | 1247 | sprintf(dma_ch_name, "rx%d", i); |
1230 | dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA, | 1248 | dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA, |
1231 | dma_ch_name); | 1249 | dma_ch_name); |
1232 | if (!dma_res) { | 1250 | if (!dma_res) { |
1233 | dev_dbg(&pdev->dev, "cannot get DMA RX channel\n"); | 1251 | dev_dbg(&pdev->dev, "cannot get DMA RX channel\n"); |
1234 | status = -ENODEV; | 1252 | status = -ENODEV; |
@@ -1238,7 +1256,7 @@ static int omap2_mcspi_probe(struct platform_device *pdev) | |||
1238 | mcspi->dma_channels[i].dma_rx_sync_dev = dma_res->start; | 1256 | mcspi->dma_channels[i].dma_rx_sync_dev = dma_res->start; |
1239 | sprintf(dma_ch_name, "tx%d", i); | 1257 | sprintf(dma_ch_name, "tx%d", i); |
1240 | dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA, | 1258 | dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA, |
1241 | dma_ch_name); | 1259 | dma_ch_name); |
1242 | if (!dma_res) { | 1260 | if (!dma_res) { |
1243 | dev_dbg(&pdev->dev, "cannot get DMA TX channel\n"); | 1261 | dev_dbg(&pdev->dev, "cannot get DMA TX channel\n"); |
1244 | status = -ENODEV; | 1262 | status = -ENODEV; |
@@ -1254,7 +1272,7 @@ static int omap2_mcspi_probe(struct platform_device *pdev) | |||
1254 | pinctrl = devm_pinctrl_get_select_default(&pdev->dev); | 1272 | pinctrl = devm_pinctrl_get_select_default(&pdev->dev); |
1255 | if (IS_ERR(pinctrl)) | 1273 | if (IS_ERR(pinctrl)) |
1256 | dev_warn(&pdev->dev, | 1274 | dev_warn(&pdev->dev, |
1257 | "pins are not configured from the driver\n"); | 1275 | "pins are not configured from the driver\n"); |
1258 | 1276 | ||
1259 | pm_runtime_use_autosuspend(&pdev->dev); | 1277 | pm_runtime_use_autosuspend(&pdev->dev); |
1260 | pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); | 1278 | pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); |
diff --git a/drivers/spi/spi-orion.c b/drivers/spi/spi-orion.c index b7e718254b1d..66a5f82cf138 100644 --- a/drivers/spi/spi-orion.c +++ b/drivers/spi/spi-orion.c | |||
@@ -366,7 +366,7 @@ msg_done: | |||
366 | return 0; | 366 | return 0; |
367 | } | 367 | } |
368 | 368 | ||
369 | static int __init orion_spi_reset(struct orion_spi *orion_spi) | 369 | static int orion_spi_reset(struct orion_spi *orion_spi) |
370 | { | 370 | { |
371 | /* Verify that the CS is deasserted */ | 371 | /* Verify that the CS is deasserted */ |
372 | orion_spi_set_cs(orion_spi, 0); | 372 | orion_spi_set_cs(orion_spi, 0); |
@@ -396,7 +396,7 @@ static int orion_spi_setup(struct spi_device *spi) | |||
396 | return 0; | 396 | return 0; |
397 | } | 397 | } |
398 | 398 | ||
399 | static int __init orion_spi_probe(struct platform_device *pdev) | 399 | static int orion_spi_probe(struct platform_device *pdev) |
400 | { | 400 | { |
401 | struct spi_master *master; | 401 | struct spi_master *master; |
402 | struct orion_spi *spi; | 402 | struct orion_spi *spi; |
@@ -479,7 +479,7 @@ out: | |||
479 | } | 479 | } |
480 | 480 | ||
481 | 481 | ||
482 | static int __exit orion_spi_remove(struct platform_device *pdev) | 482 | static int orion_spi_remove(struct platform_device *pdev) |
483 | { | 483 | { |
484 | struct spi_master *master; | 484 | struct spi_master *master; |
485 | struct resource *r; | 485 | struct resource *r; |
@@ -513,20 +513,11 @@ static struct platform_driver orion_spi_driver = { | |||
513 | .owner = THIS_MODULE, | 513 | .owner = THIS_MODULE, |
514 | .of_match_table = of_match_ptr(orion_spi_of_match_table), | 514 | .of_match_table = of_match_ptr(orion_spi_of_match_table), |
515 | }, | 515 | }, |
516 | .remove = __exit_p(orion_spi_remove), | 516 | .probe = orion_spi_probe, |
517 | .remove = orion_spi_remove, | ||
517 | }; | 518 | }; |
518 | 519 | ||
519 | static int __init orion_spi_init(void) | 520 | module_platform_driver(orion_spi_driver); |
520 | { | ||
521 | return platform_driver_probe(&orion_spi_driver, orion_spi_probe); | ||
522 | } | ||
523 | module_init(orion_spi_init); | ||
524 | |||
525 | static void __exit orion_spi_exit(void) | ||
526 | { | ||
527 | platform_driver_unregister(&orion_spi_driver); | ||
528 | } | ||
529 | module_exit(orion_spi_exit); | ||
530 | 521 | ||
531 | MODULE_DESCRIPTION("Orion SPI driver"); | 522 | MODULE_DESCRIPTION("Orion SPI driver"); |
532 | MODULE_AUTHOR("Shadi Ammouri <shadi@marvell.com>"); | 523 | MODULE_AUTHOR("Shadi Ammouri <shadi@marvell.com>"); |
diff --git a/drivers/spi/spi-ppc4xx.c b/drivers/spi/spi-ppc4xx.c index 7a85f22b6474..357f183a4fb7 100644 --- a/drivers/spi/spi-ppc4xx.c +++ b/drivers/spi/spi-ppc4xx.c | |||
@@ -389,7 +389,7 @@ static void free_gpios(struct ppc4xx_spi *hw) | |||
389 | /* | 389 | /* |
390 | * platform_device layer stuff... | 390 | * platform_device layer stuff... |
391 | */ | 391 | */ |
392 | static int __init spi_ppc4xx_of_probe(struct platform_device *op) | 392 | static int spi_ppc4xx_of_probe(struct platform_device *op) |
393 | { | 393 | { |
394 | struct ppc4xx_spi *hw; | 394 | struct ppc4xx_spi *hw; |
395 | struct spi_master *master; | 395 | struct spi_master *master; |
@@ -419,7 +419,7 @@ static int __init spi_ppc4xx_of_probe(struct platform_device *op) | |||
419 | * This includes both "null" gpio's and real ones. | 419 | * This includes both "null" gpio's and real ones. |
420 | */ | 420 | */ |
421 | num_gpios = of_gpio_count(np); | 421 | num_gpios = of_gpio_count(np); |
422 | if (num_gpios) { | 422 | if (num_gpios > 0) { |
423 | int i; | 423 | int i; |
424 | 424 | ||
425 | hw->gpios = kzalloc(sizeof(int) * num_gpios, GFP_KERNEL); | 425 | hw->gpios = kzalloc(sizeof(int) * num_gpios, GFP_KERNEL); |
@@ -471,7 +471,7 @@ static int __init spi_ppc4xx_of_probe(struct platform_device *op) | |||
471 | SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST; | 471 | SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST; |
472 | 472 | ||
473 | /* this many pins in all GPIO controllers */ | 473 | /* this many pins in all GPIO controllers */ |
474 | bbp->master->num_chipselect = num_gpios; | 474 | bbp->master->num_chipselect = num_gpios > 0 ? num_gpios : 0; |
475 | 475 | ||
476 | /* Get the clock for the OPB */ | 476 | /* Get the clock for the OPB */ |
477 | opbnp = of_find_compatible_node(NULL, NULL, "ibm,opb"); | 477 | opbnp = of_find_compatible_node(NULL, NULL, "ibm,opb"); |
@@ -560,7 +560,7 @@ free_master: | |||
560 | return ret; | 560 | return ret; |
561 | } | 561 | } |
562 | 562 | ||
563 | static int __exit spi_ppc4xx_of_remove(struct platform_device *op) | 563 | static int spi_ppc4xx_of_remove(struct platform_device *op) |
564 | { | 564 | { |
565 | struct spi_master *master = dev_get_drvdata(&op->dev); | 565 | struct spi_master *master = dev_get_drvdata(&op->dev); |
566 | struct ppc4xx_spi *hw = spi_master_get_devdata(master); | 566 | struct ppc4xx_spi *hw = spi_master_get_devdata(master); |
@@ -583,7 +583,7 @@ MODULE_DEVICE_TABLE(of, spi_ppc4xx_of_match); | |||
583 | 583 | ||
584 | static struct platform_driver spi_ppc4xx_of_driver = { | 584 | static struct platform_driver spi_ppc4xx_of_driver = { |
585 | .probe = spi_ppc4xx_of_probe, | 585 | .probe = spi_ppc4xx_of_probe, |
586 | .remove = __exit_p(spi_ppc4xx_of_remove), | 586 | .remove = spi_ppc4xx_of_remove, |
587 | .driver = { | 587 | .driver = { |
588 | .name = DRIVER_NAME, | 588 | .name = DRIVER_NAME, |
589 | .owner = THIS_MODULE, | 589 | .owner = THIS_MODULE, |
diff --git a/drivers/spi/spi-pxa2xx-dma.c b/drivers/spi/spi-pxa2xx-dma.c new file mode 100644 index 000000000000..c735c5a008a2 --- /dev/null +++ b/drivers/spi/spi-pxa2xx-dma.c | |||
@@ -0,0 +1,392 @@ | |||
1 | /* | ||
2 | * PXA2xx SPI DMA engine support. | ||
3 | * | ||
4 | * Copyright (C) 2013, Intel Corporation | ||
5 | * Author: Mika Westerberg <mika.westerberg@linux.intel.com> | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License version 2 as | ||
9 | * published by the Free Software Foundation. | ||
10 | */ | ||
11 | |||
12 | #include <linux/init.h> | ||
13 | #include <linux/device.h> | ||
14 | #include <linux/dma-mapping.h> | ||
15 | #include <linux/dmaengine.h> | ||
16 | #include <linux/pxa2xx_ssp.h> | ||
17 | #include <linux/scatterlist.h> | ||
18 | #include <linux/sizes.h> | ||
19 | #include <linux/spi/spi.h> | ||
20 | #include <linux/spi/pxa2xx_spi.h> | ||
21 | |||
22 | #include "spi-pxa2xx.h" | ||
23 | |||
24 | static int pxa2xx_spi_map_dma_buffer(struct driver_data *drv_data, | ||
25 | enum dma_data_direction dir) | ||
26 | { | ||
27 | int i, nents, len = drv_data->len; | ||
28 | struct scatterlist *sg; | ||
29 | struct device *dmadev; | ||
30 | struct sg_table *sgt; | ||
31 | void *buf, *pbuf; | ||
32 | |||
33 | /* | ||
34 | * Some DMA controllers have problems transferring buffers that are | ||
35 | * not multiple of 4 bytes. So we truncate the transfer so that it | ||
36 | * is suitable for such controllers, and handle the trailing bytes | ||
37 | * manually after the DMA completes. | ||
38 | * | ||
39 | * REVISIT: It would be better if this information could be | ||
40 | * retrieved directly from the DMA device in a similar way than | ||
41 | * ->copy_align etc. is done. | ||
42 | */ | ||
43 | len = ALIGN(drv_data->len, 4); | ||
44 | |||
45 | if (dir == DMA_TO_DEVICE) { | ||
46 | dmadev = drv_data->tx_chan->device->dev; | ||
47 | sgt = &drv_data->tx_sgt; | ||
48 | buf = drv_data->tx; | ||
49 | drv_data->tx_map_len = len; | ||
50 | } else { | ||
51 | dmadev = drv_data->rx_chan->device->dev; | ||
52 | sgt = &drv_data->rx_sgt; | ||
53 | buf = drv_data->rx; | ||
54 | drv_data->rx_map_len = len; | ||
55 | } | ||
56 | |||
57 | nents = DIV_ROUND_UP(len, SZ_2K); | ||
58 | if (nents != sgt->nents) { | ||
59 | int ret; | ||
60 | |||
61 | sg_free_table(sgt); | ||
62 | ret = sg_alloc_table(sgt, nents, GFP_KERNEL); | ||
63 | if (ret) | ||
64 | return ret; | ||
65 | } | ||
66 | |||
67 | pbuf = buf; | ||
68 | for_each_sg(sgt->sgl, sg, sgt->nents, i) { | ||
69 | size_t bytes = min_t(size_t, len, SZ_2K); | ||
70 | |||
71 | if (buf) | ||
72 | sg_set_buf(sg, pbuf, bytes); | ||
73 | else | ||
74 | sg_set_buf(sg, drv_data->dummy, bytes); | ||
75 | |||
76 | pbuf += bytes; | ||
77 | len -= bytes; | ||
78 | } | ||
79 | |||
80 | nents = dma_map_sg(dmadev, sgt->sgl, sgt->nents, dir); | ||
81 | if (!nents) | ||
82 | return -ENOMEM; | ||
83 | |||
84 | return nents; | ||
85 | } | ||
86 | |||
87 | static void pxa2xx_spi_unmap_dma_buffer(struct driver_data *drv_data, | ||
88 | enum dma_data_direction dir) | ||
89 | { | ||
90 | struct device *dmadev; | ||
91 | struct sg_table *sgt; | ||
92 | |||
93 | if (dir == DMA_TO_DEVICE) { | ||
94 | dmadev = drv_data->tx_chan->device->dev; | ||
95 | sgt = &drv_data->tx_sgt; | ||
96 | } else { | ||
97 | dmadev = drv_data->rx_chan->device->dev; | ||
98 | sgt = &drv_data->rx_sgt; | ||
99 | } | ||
100 | |||
101 | dma_unmap_sg(dmadev, sgt->sgl, sgt->nents, dir); | ||
102 | } | ||
103 | |||
104 | static void pxa2xx_spi_unmap_dma_buffers(struct driver_data *drv_data) | ||
105 | { | ||
106 | if (!drv_data->dma_mapped) | ||
107 | return; | ||
108 | |||
109 | pxa2xx_spi_unmap_dma_buffer(drv_data, DMA_FROM_DEVICE); | ||
110 | pxa2xx_spi_unmap_dma_buffer(drv_data, DMA_TO_DEVICE); | ||
111 | |||
112 | drv_data->dma_mapped = 0; | ||
113 | } | ||
114 | |||
115 | static void pxa2xx_spi_dma_transfer_complete(struct driver_data *drv_data, | ||
116 | bool error) | ||
117 | { | ||
118 | struct spi_message *msg = drv_data->cur_msg; | ||
119 | |||
120 | /* | ||
121 | * It is possible that one CPU is handling ROR interrupt and other | ||
122 | * just gets DMA completion. Calling pump_transfers() twice for the | ||
123 | * same transfer leads to problems thus we prevent concurrent calls | ||
124 | * by using ->dma_running. | ||
125 | */ | ||
126 | if (atomic_dec_and_test(&drv_data->dma_running)) { | ||
127 | void __iomem *reg = drv_data->ioaddr; | ||
128 | |||
129 | /* | ||
130 | * If the other CPU is still handling the ROR interrupt we | ||
131 | * might not know about the error yet. So we re-check the | ||
132 | * ROR bit here before we clear the status register. | ||
133 | */ | ||
134 | if (!error) { | ||
135 | u32 status = read_SSSR(reg) & drv_data->mask_sr; | ||
136 | error = status & SSSR_ROR; | ||
137 | } | ||
138 | |||
139 | /* Clear status & disable interrupts */ | ||
140 | write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg); | ||
141 | write_SSSR_CS(drv_data, drv_data->clear_sr); | ||
142 | if (!pxa25x_ssp_comp(drv_data)) | ||
143 | write_SSTO(0, reg); | ||
144 | |||
145 | if (!error) { | ||
146 | pxa2xx_spi_unmap_dma_buffers(drv_data); | ||
147 | |||
148 | /* Handle the last bytes of unaligned transfer */ | ||
149 | drv_data->tx += drv_data->tx_map_len; | ||
150 | drv_data->write(drv_data); | ||
151 | |||
152 | drv_data->rx += drv_data->rx_map_len; | ||
153 | drv_data->read(drv_data); | ||
154 | |||
155 | msg->actual_length += drv_data->len; | ||
156 | msg->state = pxa2xx_spi_next_transfer(drv_data); | ||
157 | } else { | ||
158 | /* In case we got an error we disable the SSP now */ | ||
159 | write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); | ||
160 | |||
161 | msg->state = ERROR_STATE; | ||
162 | } | ||
163 | |||
164 | tasklet_schedule(&drv_data->pump_transfers); | ||
165 | } | ||
166 | } | ||
167 | |||
168 | static void pxa2xx_spi_dma_callback(void *data) | ||
169 | { | ||
170 | pxa2xx_spi_dma_transfer_complete(data, false); | ||
171 | } | ||
172 | |||
173 | static struct dma_async_tx_descriptor * | ||
174 | pxa2xx_spi_dma_prepare_one(struct driver_data *drv_data, | ||
175 | enum dma_transfer_direction dir) | ||
176 | { | ||
177 | struct pxa2xx_spi_master *pdata = drv_data->master_info; | ||
178 | struct chip_data *chip = drv_data->cur_chip; | ||
179 | enum dma_slave_buswidth width; | ||
180 | struct dma_slave_config cfg; | ||
181 | struct dma_chan *chan; | ||
182 | struct sg_table *sgt; | ||
183 | int nents, ret; | ||
184 | |||
185 | switch (drv_data->n_bytes) { | ||
186 | case 1: | ||
187 | width = DMA_SLAVE_BUSWIDTH_1_BYTE; | ||
188 | break; | ||
189 | case 2: | ||
190 | width = DMA_SLAVE_BUSWIDTH_2_BYTES; | ||
191 | break; | ||
192 | default: | ||
193 | width = DMA_SLAVE_BUSWIDTH_4_BYTES; | ||
194 | break; | ||
195 | } | ||
196 | |||
197 | memset(&cfg, 0, sizeof(cfg)); | ||
198 | cfg.direction = dir; | ||
199 | |||
200 | if (dir == DMA_MEM_TO_DEV) { | ||
201 | cfg.dst_addr = drv_data->ssdr_physical; | ||
202 | cfg.dst_addr_width = width; | ||
203 | cfg.dst_maxburst = chip->dma_burst_size; | ||
204 | cfg.slave_id = pdata->tx_slave_id; | ||
205 | |||
206 | sgt = &drv_data->tx_sgt; | ||
207 | nents = drv_data->tx_nents; | ||
208 | chan = drv_data->tx_chan; | ||
209 | } else { | ||
210 | cfg.src_addr = drv_data->ssdr_physical; | ||
211 | cfg.src_addr_width = width; | ||
212 | cfg.src_maxburst = chip->dma_burst_size; | ||
213 | cfg.slave_id = pdata->rx_slave_id; | ||
214 | |||
215 | sgt = &drv_data->rx_sgt; | ||
216 | nents = drv_data->rx_nents; | ||
217 | chan = drv_data->rx_chan; | ||
218 | } | ||
219 | |||
220 | ret = dmaengine_slave_config(chan, &cfg); | ||
221 | if (ret) { | ||
222 | dev_warn(&drv_data->pdev->dev, "DMA slave config failed\n"); | ||
223 | return NULL; | ||
224 | } | ||
225 | |||
226 | return dmaengine_prep_slave_sg(chan, sgt->sgl, nents, dir, | ||
227 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | ||
228 | } | ||
229 | |||
230 | static bool pxa2xx_spi_dma_filter(struct dma_chan *chan, void *param) | ||
231 | { | ||
232 | const struct pxa2xx_spi_master *pdata = param; | ||
233 | |||
234 | return chan->chan_id == pdata->tx_chan_id || | ||
235 | chan->chan_id == pdata->rx_chan_id; | ||
236 | } | ||
237 | |||
238 | bool pxa2xx_spi_dma_is_possible(size_t len) | ||
239 | { | ||
240 | return len <= MAX_DMA_LEN; | ||
241 | } | ||
242 | |||
243 | int pxa2xx_spi_map_dma_buffers(struct driver_data *drv_data) | ||
244 | { | ||
245 | const struct chip_data *chip = drv_data->cur_chip; | ||
246 | int ret; | ||
247 | |||
248 | if (!chip->enable_dma) | ||
249 | return 0; | ||
250 | |||
251 | /* Don't bother with DMA if we can't do even a single burst */ | ||
252 | if (drv_data->len < chip->dma_burst_size) | ||
253 | return 0; | ||
254 | |||
255 | ret = pxa2xx_spi_map_dma_buffer(drv_data, DMA_TO_DEVICE); | ||
256 | if (ret <= 0) { | ||
257 | dev_warn(&drv_data->pdev->dev, "failed to DMA map TX\n"); | ||
258 | return 0; | ||
259 | } | ||
260 | |||
261 | drv_data->tx_nents = ret; | ||
262 | |||
263 | ret = pxa2xx_spi_map_dma_buffer(drv_data, DMA_FROM_DEVICE); | ||
264 | if (ret <= 0) { | ||
265 | pxa2xx_spi_unmap_dma_buffer(drv_data, DMA_TO_DEVICE); | ||
266 | dev_warn(&drv_data->pdev->dev, "failed to DMA map RX\n"); | ||
267 | return 0; | ||
268 | } | ||
269 | |||
270 | drv_data->rx_nents = ret; | ||
271 | return 1; | ||
272 | } | ||
273 | |||
274 | irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data) | ||
275 | { | ||
276 | u32 status; | ||
277 | |||
278 | status = read_SSSR(drv_data->ioaddr) & drv_data->mask_sr; | ||
279 | if (status & SSSR_ROR) { | ||
280 | dev_err(&drv_data->pdev->dev, "FIFO overrun\n"); | ||
281 | |||
282 | dmaengine_terminate_all(drv_data->rx_chan); | ||
283 | dmaengine_terminate_all(drv_data->tx_chan); | ||
284 | |||
285 | pxa2xx_spi_dma_transfer_complete(drv_data, true); | ||
286 | return IRQ_HANDLED; | ||
287 | } | ||
288 | |||
289 | return IRQ_NONE; | ||
290 | } | ||
291 | |||
292 | int pxa2xx_spi_dma_prepare(struct driver_data *drv_data, u32 dma_burst) | ||
293 | { | ||
294 | struct dma_async_tx_descriptor *tx_desc, *rx_desc; | ||
295 | |||
296 | tx_desc = pxa2xx_spi_dma_prepare_one(drv_data, DMA_MEM_TO_DEV); | ||
297 | if (!tx_desc) { | ||
298 | dev_err(&drv_data->pdev->dev, | ||
299 | "failed to get DMA TX descriptor\n"); | ||
300 | return -EBUSY; | ||
301 | } | ||
302 | |||
303 | rx_desc = pxa2xx_spi_dma_prepare_one(drv_data, DMA_DEV_TO_MEM); | ||
304 | if (!rx_desc) { | ||
305 | dev_err(&drv_data->pdev->dev, | ||
306 | "failed to get DMA RX descriptor\n"); | ||
307 | return -EBUSY; | ||
308 | } | ||
309 | |||
310 | /* We are ready when RX completes */ | ||
311 | rx_desc->callback = pxa2xx_spi_dma_callback; | ||
312 | rx_desc->callback_param = drv_data; | ||
313 | |||
314 | dmaengine_submit(rx_desc); | ||
315 | dmaengine_submit(tx_desc); | ||
316 | return 0; | ||
317 | } | ||
318 | |||
319 | void pxa2xx_spi_dma_start(struct driver_data *drv_data) | ||
320 | { | ||
321 | dma_async_issue_pending(drv_data->rx_chan); | ||
322 | dma_async_issue_pending(drv_data->tx_chan); | ||
323 | |||
324 | atomic_set(&drv_data->dma_running, 1); | ||
325 | } | ||
326 | |||
327 | int pxa2xx_spi_dma_setup(struct driver_data *drv_data) | ||
328 | { | ||
329 | struct pxa2xx_spi_master *pdata = drv_data->master_info; | ||
330 | dma_cap_mask_t mask; | ||
331 | |||
332 | dma_cap_zero(mask); | ||
333 | dma_cap_set(DMA_SLAVE, mask); | ||
334 | |||
335 | drv_data->dummy = devm_kzalloc(&drv_data->pdev->dev, SZ_2K, GFP_KERNEL); | ||
336 | if (!drv_data->dummy) | ||
337 | return -ENOMEM; | ||
338 | |||
339 | drv_data->tx_chan = dma_request_channel(mask, pxa2xx_spi_dma_filter, | ||
340 | pdata); | ||
341 | if (!drv_data->tx_chan) | ||
342 | return -ENODEV; | ||
343 | |||
344 | drv_data->rx_chan = dma_request_channel(mask, pxa2xx_spi_dma_filter, | ||
345 | pdata); | ||
346 | if (!drv_data->rx_chan) { | ||
347 | dma_release_channel(drv_data->tx_chan); | ||
348 | drv_data->tx_chan = NULL; | ||
349 | return -ENODEV; | ||
350 | } | ||
351 | |||
352 | return 0; | ||
353 | } | ||
354 | |||
355 | void pxa2xx_spi_dma_release(struct driver_data *drv_data) | ||
356 | { | ||
357 | if (drv_data->rx_chan) { | ||
358 | dmaengine_terminate_all(drv_data->rx_chan); | ||
359 | dma_release_channel(drv_data->rx_chan); | ||
360 | sg_free_table(&drv_data->rx_sgt); | ||
361 | drv_data->rx_chan = NULL; | ||
362 | } | ||
363 | if (drv_data->tx_chan) { | ||
364 | dmaengine_terminate_all(drv_data->tx_chan); | ||
365 | dma_release_channel(drv_data->tx_chan); | ||
366 | sg_free_table(&drv_data->tx_sgt); | ||
367 | drv_data->tx_chan = NULL; | ||
368 | } | ||
369 | } | ||
370 | |||
371 | void pxa2xx_spi_dma_resume(struct driver_data *drv_data) | ||
372 | { | ||
373 | } | ||
374 | |||
375 | int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip, | ||
376 | struct spi_device *spi, | ||
377 | u8 bits_per_word, u32 *burst_code, | ||
378 | u32 *threshold) | ||
379 | { | ||
380 | struct pxa2xx_spi_chip *chip_info = spi->controller_data; | ||
381 | |||
382 | /* | ||
383 | * If the DMA burst size is given in chip_info we use that, | ||
384 | * otherwise we use the default. Also we use the default FIFO | ||
385 | * thresholds for now. | ||
386 | */ | ||
387 | *burst_code = chip_info ? chip_info->dma_burst_size : 16; | ||
388 | *threshold = SSCR1_RxTresh(RX_THRESH_DFLT) | ||
389 | | SSCR1_TxTresh(TX_THRESH_DFLT); | ||
390 | |||
391 | return 0; | ||
392 | } | ||
diff --git a/drivers/spi/spi-pxa2xx-pci.c b/drivers/spi/spi-pxa2xx-pci.c index cf95587eefde..364964d2ed04 100644 --- a/drivers/spi/spi-pxa2xx-pci.c +++ b/drivers/spi/spi-pxa2xx-pci.c | |||
@@ -8,147 +8,58 @@ | |||
8 | #include <linux/module.h> | 8 | #include <linux/module.h> |
9 | #include <linux/spi/pxa2xx_spi.h> | 9 | #include <linux/spi/pxa2xx_spi.h> |
10 | 10 | ||
11 | struct ce4100_info { | ||
12 | struct ssp_device ssp; | ||
13 | struct platform_device *spi_pdev; | ||
14 | }; | ||
15 | |||
16 | static DEFINE_MUTEX(ssp_lock); | ||
17 | static LIST_HEAD(ssp_list); | ||
18 | |||
19 | struct ssp_device *pxa_ssp_request(int port, const char *label) | ||
20 | { | ||
21 | struct ssp_device *ssp = NULL; | ||
22 | |||
23 | mutex_lock(&ssp_lock); | ||
24 | |||
25 | list_for_each_entry(ssp, &ssp_list, node) { | ||
26 | if (ssp->port_id == port && ssp->use_count == 0) { | ||
27 | ssp->use_count++; | ||
28 | ssp->label = label; | ||
29 | break; | ||
30 | } | ||
31 | } | ||
32 | |||
33 | mutex_unlock(&ssp_lock); | ||
34 | |||
35 | if (&ssp->node == &ssp_list) | ||
36 | return NULL; | ||
37 | |||
38 | return ssp; | ||
39 | } | ||
40 | EXPORT_SYMBOL_GPL(pxa_ssp_request); | ||
41 | |||
42 | void pxa_ssp_free(struct ssp_device *ssp) | ||
43 | { | ||
44 | mutex_lock(&ssp_lock); | ||
45 | if (ssp->use_count) { | ||
46 | ssp->use_count--; | ||
47 | ssp->label = NULL; | ||
48 | } else | ||
49 | dev_err(&ssp->pdev->dev, "device already free\n"); | ||
50 | mutex_unlock(&ssp_lock); | ||
51 | } | ||
52 | EXPORT_SYMBOL_GPL(pxa_ssp_free); | ||
53 | |||
54 | static int ce4100_spi_probe(struct pci_dev *dev, | 11 | static int ce4100_spi_probe(struct pci_dev *dev, |
55 | const struct pci_device_id *ent) | 12 | const struct pci_device_id *ent) |
56 | { | 13 | { |
14 | struct platform_device_info pi; | ||
57 | int ret; | 15 | int ret; |
58 | resource_size_t phys_beg; | ||
59 | resource_size_t phys_len; | ||
60 | struct ce4100_info *spi_info; | ||
61 | struct platform_device *pdev; | 16 | struct platform_device *pdev; |
62 | struct pxa2xx_spi_master spi_pdata; | 17 | struct pxa2xx_spi_master spi_pdata; |
63 | struct ssp_device *ssp; | 18 | struct ssp_device *ssp; |
64 | 19 | ||
65 | ret = pci_enable_device(dev); | 20 | ret = pcim_enable_device(dev); |
66 | if (ret) | 21 | if (ret) |
67 | return ret; | 22 | return ret; |
68 | 23 | ||
69 | phys_beg = pci_resource_start(dev, 0); | 24 | ret = pcim_iomap_regions(dev, 1 << 0, "PXA2xx SPI"); |
70 | phys_len = pci_resource_len(dev, 0); | 25 | if (!ret) |
71 | |||
72 | if (!request_mem_region(phys_beg, phys_len, | ||
73 | "CE4100 SPI")) { | ||
74 | dev_err(&dev->dev, "Can't request register space.\n"); | ||
75 | ret = -EBUSY; | ||
76 | return ret; | 26 | return ret; |
77 | } | ||
78 | 27 | ||
79 | pdev = platform_device_alloc("pxa2xx-spi", dev->devfn); | ||
80 | spi_info = kzalloc(sizeof(*spi_info), GFP_KERNEL); | ||
81 | if (!pdev || !spi_info ) { | ||
82 | ret = -ENOMEM; | ||
83 | goto err_nomem; | ||
84 | } | ||
85 | memset(&spi_pdata, 0, sizeof(spi_pdata)); | 28 | memset(&spi_pdata, 0, sizeof(spi_pdata)); |
86 | spi_pdata.num_chipselect = dev->devfn; | 29 | spi_pdata.num_chipselect = dev->devfn; |
87 | 30 | ||
88 | ret = platform_device_add_data(pdev, &spi_pdata, sizeof(spi_pdata)); | 31 | ssp = &spi_pdata.ssp; |
89 | if (ret) | ||
90 | goto err_nomem; | ||
91 | |||
92 | pdev->dev.parent = &dev->dev; | ||
93 | pdev->dev.of_node = dev->dev.of_node; | ||
94 | ssp = &spi_info->ssp; | ||
95 | ssp->phys_base = pci_resource_start(dev, 0); | 32 | ssp->phys_base = pci_resource_start(dev, 0); |
96 | ssp->mmio_base = ioremap(phys_beg, phys_len); | 33 | ssp->mmio_base = pcim_iomap_table(dev)[0]; |
97 | if (!ssp->mmio_base) { | 34 | if (!ssp->mmio_base) { |
98 | dev_err(&pdev->dev, "failed to ioremap() registers\n"); | 35 | dev_err(&dev->dev, "failed to ioremap() registers\n"); |
99 | ret = -EIO; | 36 | return -EIO; |
100 | goto err_nomem; | ||
101 | } | 37 | } |
102 | ssp->irq = dev->irq; | 38 | ssp->irq = dev->irq; |
103 | ssp->port_id = pdev->id; | 39 | ssp->port_id = dev->devfn; |
104 | ssp->type = PXA25x_SSP; | 40 | ssp->type = PXA25x_SSP; |
105 | 41 | ||
106 | mutex_lock(&ssp_lock); | 42 | memset(&pi, 0, sizeof(pi)); |
107 | list_add(&ssp->node, &ssp_list); | 43 | pi.parent = &dev->dev; |
108 | mutex_unlock(&ssp_lock); | 44 | pi.name = "pxa2xx-spi"; |
45 | pi.id = ssp->port_id; | ||
46 | pi.data = &spi_pdata; | ||
47 | pi.size_data = sizeof(spi_pdata); | ||
109 | 48 | ||
110 | pci_set_drvdata(dev, spi_info); | 49 | pdev = platform_device_register_full(&pi); |
50 | if (!pdev) | ||
51 | return -ENOMEM; | ||
111 | 52 | ||
112 | ret = platform_device_add(pdev); | 53 | pci_set_drvdata(dev, pdev); |
113 | if (ret) | ||
114 | goto err_dev_add; | ||
115 | 54 | ||
116 | return ret; | 55 | return 0; |
117 | |||
118 | err_dev_add: | ||
119 | pci_set_drvdata(dev, NULL); | ||
120 | mutex_lock(&ssp_lock); | ||
121 | list_del(&ssp->node); | ||
122 | mutex_unlock(&ssp_lock); | ||
123 | iounmap(ssp->mmio_base); | ||
124 | |||
125 | err_nomem: | ||
126 | release_mem_region(phys_beg, phys_len); | ||
127 | platform_device_put(pdev); | ||
128 | kfree(spi_info); | ||
129 | return ret; | ||
130 | } | 56 | } |
131 | 57 | ||
132 | static void ce4100_spi_remove(struct pci_dev *dev) | 58 | static void ce4100_spi_remove(struct pci_dev *dev) |
133 | { | 59 | { |
134 | struct ce4100_info *spi_info; | 60 | struct platform_device *pdev = pci_get_drvdata(dev); |
135 | struct ssp_device *ssp; | ||
136 | |||
137 | spi_info = pci_get_drvdata(dev); | ||
138 | ssp = &spi_info->ssp; | ||
139 | platform_device_unregister(spi_info->spi_pdev); | ||
140 | |||
141 | iounmap(ssp->mmio_base); | ||
142 | release_mem_region(pci_resource_start(dev, 0), | ||
143 | pci_resource_len(dev, 0)); | ||
144 | |||
145 | mutex_lock(&ssp_lock); | ||
146 | list_del(&ssp->node); | ||
147 | mutex_unlock(&ssp_lock); | ||
148 | 61 | ||
149 | pci_set_drvdata(dev, NULL); | 62 | platform_device_unregister(pdev); |
150 | pci_disable_device(dev); | ||
151 | kfree(spi_info); | ||
152 | } | 63 | } |
153 | 64 | ||
154 | static DEFINE_PCI_DEVICE_TABLE(ce4100_spi_devices) = { | 65 | static DEFINE_PCI_DEVICE_TABLE(ce4100_spi_devices) = { |
diff --git a/drivers/spi/spi-pxa2xx-pxadma.c b/drivers/spi/spi-pxa2xx-pxadma.c new file mode 100644 index 000000000000..2916efc7cfe5 --- /dev/null +++ b/drivers/spi/spi-pxa2xx-pxadma.c | |||
@@ -0,0 +1,490 @@ | |||
1 | /* | ||
2 | * PXA2xx SPI private DMA support. | ||
3 | * | ||
4 | * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; either version 2 of the License, or | ||
9 | * (at your option) any later version. | ||
10 | * | ||
11 | * This program is distributed in the hope that it will be useful, | ||
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | * | ||
16 | * You should have received a copy of the GNU General Public License | ||
17 | * along with this program; if not, write to the Free Software | ||
18 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | ||
19 | */ | ||
20 | |||
21 | #include <linux/init.h> | ||
22 | #include <linux/delay.h> | ||
23 | #include <linux/device.h> | ||
24 | #include <linux/dma-mapping.h> | ||
25 | #include <linux/pxa2xx_ssp.h> | ||
26 | #include <linux/spi/spi.h> | ||
27 | #include <linux/spi/pxa2xx_spi.h> | ||
28 | |||
29 | #include "spi-pxa2xx.h" | ||
30 | |||
31 | #define DMA_INT_MASK (DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERR) | ||
32 | #define RESET_DMA_CHANNEL (DCSR_NODESC | DMA_INT_MASK) | ||
33 | |||
34 | bool pxa2xx_spi_dma_is_possible(size_t len) | ||
35 | { | ||
36 | /* Try to map dma buffer and do a dma transfer if successful, but | ||
37 | * only if the length is non-zero and less than MAX_DMA_LEN. | ||
38 | * | ||
39 | * Zero-length non-descriptor DMA is illegal on PXA2xx; force use | ||
40 | * of PIO instead. Care is needed above because the transfer may | ||
41 | * have have been passed with buffers that are already dma mapped. | ||
42 | * A zero-length transfer in PIO mode will not try to write/read | ||
43 | * to/from the buffers | ||
44 | * | ||
45 | * REVISIT large transfers are exactly where we most want to be | ||
46 | * using DMA. If this happens much, split those transfers into | ||
47 | * multiple DMA segments rather than forcing PIO. | ||
48 | */ | ||
49 | return len > 0 && len <= MAX_DMA_LEN; | ||
50 | } | ||
51 | |||
52 | int pxa2xx_spi_map_dma_buffers(struct driver_data *drv_data) | ||
53 | { | ||
54 | struct spi_message *msg = drv_data->cur_msg; | ||
55 | struct device *dev = &msg->spi->dev; | ||
56 | |||
57 | if (!drv_data->cur_chip->enable_dma) | ||
58 | return 0; | ||
59 | |||
60 | if (msg->is_dma_mapped) | ||
61 | return drv_data->rx_dma && drv_data->tx_dma; | ||
62 | |||
63 | if (!IS_DMA_ALIGNED(drv_data->rx) || !IS_DMA_ALIGNED(drv_data->tx)) | ||
64 | return 0; | ||
65 | |||
66 | /* Modify setup if rx buffer is null */ | ||
67 | if (drv_data->rx == NULL) { | ||
68 | *drv_data->null_dma_buf = 0; | ||
69 | drv_data->rx = drv_data->null_dma_buf; | ||
70 | drv_data->rx_map_len = 4; | ||
71 | } else | ||
72 | drv_data->rx_map_len = drv_data->len; | ||
73 | |||
74 | |||
75 | /* Modify setup if tx buffer is null */ | ||
76 | if (drv_data->tx == NULL) { | ||
77 | *drv_data->null_dma_buf = 0; | ||
78 | drv_data->tx = drv_data->null_dma_buf; | ||
79 | drv_data->tx_map_len = 4; | ||
80 | } else | ||
81 | drv_data->tx_map_len = drv_data->len; | ||
82 | |||
83 | /* Stream map the tx buffer. Always do DMA_TO_DEVICE first | ||
84 | * so we flush the cache *before* invalidating it, in case | ||
85 | * the tx and rx buffers overlap. | ||
86 | */ | ||
87 | drv_data->tx_dma = dma_map_single(dev, drv_data->tx, | ||
88 | drv_data->tx_map_len, DMA_TO_DEVICE); | ||
89 | if (dma_mapping_error(dev, drv_data->tx_dma)) | ||
90 | return 0; | ||
91 | |||
92 | /* Stream map the rx buffer */ | ||
93 | drv_data->rx_dma = dma_map_single(dev, drv_data->rx, | ||
94 | drv_data->rx_map_len, DMA_FROM_DEVICE); | ||
95 | if (dma_mapping_error(dev, drv_data->rx_dma)) { | ||
96 | dma_unmap_single(dev, drv_data->tx_dma, | ||
97 | drv_data->tx_map_len, DMA_TO_DEVICE); | ||
98 | return 0; | ||
99 | } | ||
100 | |||
101 | return 1; | ||
102 | } | ||
103 | |||
104 | static void pxa2xx_spi_unmap_dma_buffers(struct driver_data *drv_data) | ||
105 | { | ||
106 | struct device *dev; | ||
107 | |||
108 | if (!drv_data->dma_mapped) | ||
109 | return; | ||
110 | |||
111 | if (!drv_data->cur_msg->is_dma_mapped) { | ||
112 | dev = &drv_data->cur_msg->spi->dev; | ||
113 | dma_unmap_single(dev, drv_data->rx_dma, | ||
114 | drv_data->rx_map_len, DMA_FROM_DEVICE); | ||
115 | dma_unmap_single(dev, drv_data->tx_dma, | ||
116 | drv_data->tx_map_len, DMA_TO_DEVICE); | ||
117 | } | ||
118 | |||
119 | drv_data->dma_mapped = 0; | ||
120 | } | ||
121 | |||
122 | static int wait_ssp_rx_stall(void const __iomem *ioaddr) | ||
123 | { | ||
124 | unsigned long limit = loops_per_jiffy << 1; | ||
125 | |||
126 | while ((read_SSSR(ioaddr) & SSSR_BSY) && --limit) | ||
127 | cpu_relax(); | ||
128 | |||
129 | return limit; | ||
130 | } | ||
131 | |||
132 | static int wait_dma_channel_stop(int channel) | ||
133 | { | ||
134 | unsigned long limit = loops_per_jiffy << 1; | ||
135 | |||
136 | while (!(DCSR(channel) & DCSR_STOPSTATE) && --limit) | ||
137 | cpu_relax(); | ||
138 | |||
139 | return limit; | ||
140 | } | ||
141 | |||
142 | static void pxa2xx_spi_dma_error_stop(struct driver_data *drv_data, | ||
143 | const char *msg) | ||
144 | { | ||
145 | void __iomem *reg = drv_data->ioaddr; | ||
146 | |||
147 | /* Stop and reset */ | ||
148 | DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL; | ||
149 | DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL; | ||
150 | write_SSSR_CS(drv_data, drv_data->clear_sr); | ||
151 | write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg); | ||
152 | if (!pxa25x_ssp_comp(drv_data)) | ||
153 | write_SSTO(0, reg); | ||
154 | pxa2xx_spi_flush(drv_data); | ||
155 | write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); | ||
156 | |||
157 | pxa2xx_spi_unmap_dma_buffers(drv_data); | ||
158 | |||
159 | dev_err(&drv_data->pdev->dev, "%s\n", msg); | ||
160 | |||
161 | drv_data->cur_msg->state = ERROR_STATE; | ||
162 | tasklet_schedule(&drv_data->pump_transfers); | ||
163 | } | ||
164 | |||
165 | static void pxa2xx_spi_dma_transfer_complete(struct driver_data *drv_data) | ||
166 | { | ||
167 | void __iomem *reg = drv_data->ioaddr; | ||
168 | struct spi_message *msg = drv_data->cur_msg; | ||
169 | |||
170 | /* Clear and disable interrupts on SSP and DMA channels*/ | ||
171 | write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg); | ||
172 | write_SSSR_CS(drv_data, drv_data->clear_sr); | ||
173 | DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL; | ||
174 | DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL; | ||
175 | |||
176 | if (wait_dma_channel_stop(drv_data->rx_channel) == 0) | ||
177 | dev_err(&drv_data->pdev->dev, | ||
178 | "dma_handler: dma rx channel stop failed\n"); | ||
179 | |||
180 | if (wait_ssp_rx_stall(drv_data->ioaddr) == 0) | ||
181 | dev_err(&drv_data->pdev->dev, | ||
182 | "dma_transfer: ssp rx stall failed\n"); | ||
183 | |||
184 | pxa2xx_spi_unmap_dma_buffers(drv_data); | ||
185 | |||
186 | /* update the buffer pointer for the amount completed in dma */ | ||
187 | drv_data->rx += drv_data->len - | ||
188 | (DCMD(drv_data->rx_channel) & DCMD_LENGTH); | ||
189 | |||
190 | /* read trailing data from fifo, it does not matter how many | ||
191 | * bytes are in the fifo just read until buffer is full | ||
192 | * or fifo is empty, which ever occurs first */ | ||
193 | drv_data->read(drv_data); | ||
194 | |||
195 | /* return count of what was actually read */ | ||
196 | msg->actual_length += drv_data->len - | ||
197 | (drv_data->rx_end - drv_data->rx); | ||
198 | |||
199 | /* Transfer delays and chip select release are | ||
200 | * handled in pump_transfers or giveback | ||
201 | */ | ||
202 | |||
203 | /* Move to next transfer */ | ||
204 | msg->state = pxa2xx_spi_next_transfer(drv_data); | ||
205 | |||
206 | /* Schedule transfer tasklet */ | ||
207 | tasklet_schedule(&drv_data->pump_transfers); | ||
208 | } | ||
209 | |||
210 | void pxa2xx_spi_dma_handler(int channel, void *data) | ||
211 | { | ||
212 | struct driver_data *drv_data = data; | ||
213 | u32 irq_status = DCSR(channel) & DMA_INT_MASK; | ||
214 | |||
215 | if (irq_status & DCSR_BUSERR) { | ||
216 | |||
217 | if (channel == drv_data->tx_channel) | ||
218 | pxa2xx_spi_dma_error_stop(drv_data, | ||
219 | "dma_handler: bad bus address on tx channel"); | ||
220 | else | ||
221 | pxa2xx_spi_dma_error_stop(drv_data, | ||
222 | "dma_handler: bad bus address on rx channel"); | ||
223 | return; | ||
224 | } | ||
225 | |||
226 | /* PXA255x_SSP has no timeout interrupt, wait for tailing bytes */ | ||
227 | if ((channel == drv_data->tx_channel) | ||
228 | && (irq_status & DCSR_ENDINTR) | ||
229 | && (drv_data->ssp_type == PXA25x_SSP)) { | ||
230 | |||
231 | /* Wait for rx to stall */ | ||
232 | if (wait_ssp_rx_stall(drv_data->ioaddr) == 0) | ||
233 | dev_err(&drv_data->pdev->dev, | ||
234 | "dma_handler: ssp rx stall failed\n"); | ||
235 | |||
236 | /* finish this transfer, start the next */ | ||
237 | pxa2xx_spi_dma_transfer_complete(drv_data); | ||
238 | } | ||
239 | } | ||
240 | |||
241 | irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data) | ||
242 | { | ||
243 | u32 irq_status; | ||
244 | void __iomem *reg = drv_data->ioaddr; | ||
245 | |||
246 | irq_status = read_SSSR(reg) & drv_data->mask_sr; | ||
247 | if (irq_status & SSSR_ROR) { | ||
248 | pxa2xx_spi_dma_error_stop(drv_data, | ||
249 | "dma_transfer: fifo overrun"); | ||
250 | return IRQ_HANDLED; | ||
251 | } | ||
252 | |||
253 | /* Check for false positive timeout */ | ||
254 | if ((irq_status & SSSR_TINT) | ||
255 | && (DCSR(drv_data->tx_channel) & DCSR_RUN)) { | ||
256 | write_SSSR(SSSR_TINT, reg); | ||
257 | return IRQ_HANDLED; | ||
258 | } | ||
259 | |||
260 | if (irq_status & SSSR_TINT || drv_data->rx == drv_data->rx_end) { | ||
261 | |||
262 | /* Clear and disable timeout interrupt, do the rest in | ||
263 | * dma_transfer_complete */ | ||
264 | if (!pxa25x_ssp_comp(drv_data)) | ||
265 | write_SSTO(0, reg); | ||
266 | |||
267 | /* finish this transfer, start the next */ | ||
268 | pxa2xx_spi_dma_transfer_complete(drv_data); | ||
269 | |||
270 | return IRQ_HANDLED; | ||
271 | } | ||
272 | |||
273 | /* Opps problem detected */ | ||
274 | return IRQ_NONE; | ||
275 | } | ||
276 | |||
277 | int pxa2xx_spi_dma_prepare(struct driver_data *drv_data, u32 dma_burst) | ||
278 | { | ||
279 | u32 dma_width; | ||
280 | |||
281 | switch (drv_data->n_bytes) { | ||
282 | case 1: | ||
283 | dma_width = DCMD_WIDTH1; | ||
284 | break; | ||
285 | case 2: | ||
286 | dma_width = DCMD_WIDTH2; | ||
287 | break; | ||
288 | default: | ||
289 | dma_width = DCMD_WIDTH4; | ||
290 | break; | ||
291 | } | ||
292 | |||
293 | /* Setup rx DMA Channel */ | ||
294 | DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL; | ||
295 | DSADR(drv_data->rx_channel) = drv_data->ssdr_physical; | ||
296 | DTADR(drv_data->rx_channel) = drv_data->rx_dma; | ||
297 | if (drv_data->rx == drv_data->null_dma_buf) | ||
298 | /* No target address increment */ | ||
299 | DCMD(drv_data->rx_channel) = DCMD_FLOWSRC | ||
300 | | dma_width | ||
301 | | dma_burst | ||
302 | | drv_data->len; | ||
303 | else | ||
304 | DCMD(drv_data->rx_channel) = DCMD_INCTRGADDR | ||
305 | | DCMD_FLOWSRC | ||
306 | | dma_width | ||
307 | | dma_burst | ||
308 | | drv_data->len; | ||
309 | |||
310 | /* Setup tx DMA Channel */ | ||
311 | DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL; | ||
312 | DSADR(drv_data->tx_channel) = drv_data->tx_dma; | ||
313 | DTADR(drv_data->tx_channel) = drv_data->ssdr_physical; | ||
314 | if (drv_data->tx == drv_data->null_dma_buf) | ||
315 | /* No source address increment */ | ||
316 | DCMD(drv_data->tx_channel) = DCMD_FLOWTRG | ||
317 | | dma_width | ||
318 | | dma_burst | ||
319 | | drv_data->len; | ||
320 | else | ||
321 | DCMD(drv_data->tx_channel) = DCMD_INCSRCADDR | ||
322 | | DCMD_FLOWTRG | ||
323 | | dma_width | ||
324 | | dma_burst | ||
325 | | drv_data->len; | ||
326 | |||
327 | /* Enable dma end irqs on SSP to detect end of transfer */ | ||
328 | if (drv_data->ssp_type == PXA25x_SSP) | ||
329 | DCMD(drv_data->tx_channel) |= DCMD_ENDIRQEN; | ||
330 | |||
331 | return 0; | ||
332 | } | ||
333 | |||
334 | void pxa2xx_spi_dma_start(struct driver_data *drv_data) | ||
335 | { | ||
336 | DCSR(drv_data->rx_channel) |= DCSR_RUN; | ||
337 | DCSR(drv_data->tx_channel) |= DCSR_RUN; | ||
338 | } | ||
339 | |||
340 | int pxa2xx_spi_dma_setup(struct driver_data *drv_data) | ||
341 | { | ||
342 | struct device *dev = &drv_data->pdev->dev; | ||
343 | struct ssp_device *ssp = drv_data->ssp; | ||
344 | |||
345 | /* Get two DMA channels (rx and tx) */ | ||
346 | drv_data->rx_channel = pxa_request_dma("pxa2xx_spi_ssp_rx", | ||
347 | DMA_PRIO_HIGH, | ||
348 | pxa2xx_spi_dma_handler, | ||
349 | drv_data); | ||
350 | if (drv_data->rx_channel < 0) { | ||
351 | dev_err(dev, "problem (%d) requesting rx channel\n", | ||
352 | drv_data->rx_channel); | ||
353 | return -ENODEV; | ||
354 | } | ||
355 | drv_data->tx_channel = pxa_request_dma("pxa2xx_spi_ssp_tx", | ||
356 | DMA_PRIO_MEDIUM, | ||
357 | pxa2xx_spi_dma_handler, | ||
358 | drv_data); | ||
359 | if (drv_data->tx_channel < 0) { | ||
360 | dev_err(dev, "problem (%d) requesting tx channel\n", | ||
361 | drv_data->tx_channel); | ||
362 | pxa_free_dma(drv_data->rx_channel); | ||
363 | return -ENODEV; | ||
364 | } | ||
365 | |||
366 | DRCMR(ssp->drcmr_rx) = DRCMR_MAPVLD | drv_data->rx_channel; | ||
367 | DRCMR(ssp->drcmr_tx) = DRCMR_MAPVLD | drv_data->tx_channel; | ||
368 | |||
369 | return 0; | ||
370 | } | ||
371 | |||
372 | void pxa2xx_spi_dma_release(struct driver_data *drv_data) | ||
373 | { | ||
374 | struct ssp_device *ssp = drv_data->ssp; | ||
375 | |||
376 | DRCMR(ssp->drcmr_rx) = 0; | ||
377 | DRCMR(ssp->drcmr_tx) = 0; | ||
378 | |||
379 | if (drv_data->tx_channel != 0) | ||
380 | pxa_free_dma(drv_data->tx_channel); | ||
381 | if (drv_data->rx_channel != 0) | ||
382 | pxa_free_dma(drv_data->rx_channel); | ||
383 | } | ||
384 | |||
385 | void pxa2xx_spi_dma_resume(struct driver_data *drv_data) | ||
386 | { | ||
387 | if (drv_data->rx_channel != -1) | ||
388 | DRCMR(drv_data->ssp->drcmr_rx) = | ||
389 | DRCMR_MAPVLD | drv_data->rx_channel; | ||
390 | if (drv_data->tx_channel != -1) | ||
391 | DRCMR(drv_data->ssp->drcmr_tx) = | ||
392 | DRCMR_MAPVLD | drv_data->tx_channel; | ||
393 | } | ||
394 | |||
395 | int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip, | ||
396 | struct spi_device *spi, | ||
397 | u8 bits_per_word, u32 *burst_code, | ||
398 | u32 *threshold) | ||
399 | { | ||
400 | struct pxa2xx_spi_chip *chip_info = | ||
401 | (struct pxa2xx_spi_chip *)spi->controller_data; | ||
402 | int bytes_per_word; | ||
403 | int burst_bytes; | ||
404 | int thresh_words; | ||
405 | int req_burst_size; | ||
406 | int retval = 0; | ||
407 | |||
408 | /* Set the threshold (in registers) to equal the same amount of data | ||
409 | * as represented by burst size (in bytes). The computation below | ||
410 | * is (burst_size rounded up to nearest 8 byte, word or long word) | ||
411 | * divided by (bytes/register); the tx threshold is the inverse of | ||
412 | * the rx, so that there will always be enough data in the rx fifo | ||
413 | * to satisfy a burst, and there will always be enough space in the | ||
414 | * tx fifo to accept a burst (a tx burst will overwrite the fifo if | ||
415 | * there is not enough space), there must always remain enough empty | ||
416 | * space in the rx fifo for any data loaded to the tx fifo. | ||
417 | * Whenever burst_size (in bytes) equals bits/word, the fifo threshold | ||
418 | * will be 8, or half the fifo; | ||
419 | * The threshold can only be set to 2, 4 or 8, but not 16, because | ||
420 | * to burst 16 to the tx fifo, the fifo would have to be empty; | ||
421 | * however, the minimum fifo trigger level is 1, and the tx will | ||
422 | * request service when the fifo is at this level, with only 15 spaces. | ||
423 | */ | ||
424 | |||
425 | /* find bytes/word */ | ||
426 | if (bits_per_word <= 8) | ||
427 | bytes_per_word = 1; | ||
428 | else if (bits_per_word <= 16) | ||
429 | bytes_per_word = 2; | ||
430 | else | ||
431 | bytes_per_word = 4; | ||
432 | |||
433 | /* use struct pxa2xx_spi_chip->dma_burst_size if available */ | ||
434 | if (chip_info) | ||
435 | req_burst_size = chip_info->dma_burst_size; | ||
436 | else { | ||
437 | switch (chip->dma_burst_size) { | ||
438 | default: | ||
439 | /* if the default burst size is not set, | ||
440 | * do it now */ | ||
441 | chip->dma_burst_size = DCMD_BURST8; | ||
442 | case DCMD_BURST8: | ||
443 | req_burst_size = 8; | ||
444 | break; | ||
445 | case DCMD_BURST16: | ||
446 | req_burst_size = 16; | ||
447 | break; | ||
448 | case DCMD_BURST32: | ||
449 | req_burst_size = 32; | ||
450 | break; | ||
451 | } | ||
452 | } | ||
453 | if (req_burst_size <= 8) { | ||
454 | *burst_code = DCMD_BURST8; | ||
455 | burst_bytes = 8; | ||
456 | } else if (req_burst_size <= 16) { | ||
457 | if (bytes_per_word == 1) { | ||
458 | /* don't burst more than 1/2 the fifo */ | ||
459 | *burst_code = DCMD_BURST8; | ||
460 | burst_bytes = 8; | ||
461 | retval = 1; | ||
462 | } else { | ||
463 | *burst_code = DCMD_BURST16; | ||
464 | burst_bytes = 16; | ||
465 | } | ||
466 | } else { | ||
467 | if (bytes_per_word == 1) { | ||
468 | /* don't burst more than 1/2 the fifo */ | ||
469 | *burst_code = DCMD_BURST8; | ||
470 | burst_bytes = 8; | ||
471 | retval = 1; | ||
472 | } else if (bytes_per_word == 2) { | ||
473 | /* don't burst more than 1/2 the fifo */ | ||
474 | *burst_code = DCMD_BURST16; | ||
475 | burst_bytes = 16; | ||
476 | retval = 1; | ||
477 | } else { | ||
478 | *burst_code = DCMD_BURST32; | ||
479 | burst_bytes = 32; | ||
480 | } | ||
481 | } | ||
482 | |||
483 | thresh_words = burst_bytes / bytes_per_word; | ||
484 | |||
485 | /* thresh_words will be between 2 and 8 */ | ||
486 | *threshold = (SSCR1_RxTresh(thresh_words) & SSCR1_RFT) | ||
487 | | (SSCR1_TxTresh(16-thresh_words) & SSCR1_TFT); | ||
488 | |||
489 | return retval; | ||
490 | } | ||
diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c index 5c8c4f5883c4..90b27a3508a6 100644 --- a/drivers/spi/spi-pxa2xx.c +++ b/drivers/spi/spi-pxa2xx.c | |||
@@ -1,5 +1,6 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs | 2 | * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs |
3 | * Copyright (C) 2013, Intel Corporation | ||
3 | * | 4 | * |
4 | * This program is free software; you can redistribute it and/or modify | 5 | * This program is free software; you can redistribute it and/or modify |
5 | * it under the terms of the GNU General Public License as published by | 6 | * it under the terms of the GNU General Public License as published by |
@@ -24,17 +25,20 @@ | |||
24 | #include <linux/interrupt.h> | 25 | #include <linux/interrupt.h> |
25 | #include <linux/platform_device.h> | 26 | #include <linux/platform_device.h> |
26 | #include <linux/spi/pxa2xx_spi.h> | 27 | #include <linux/spi/pxa2xx_spi.h> |
27 | #include <linux/dma-mapping.h> | ||
28 | #include <linux/spi/spi.h> | 28 | #include <linux/spi/spi.h> |
29 | #include <linux/workqueue.h> | 29 | #include <linux/workqueue.h> |
30 | #include <linux/delay.h> | 30 | #include <linux/delay.h> |
31 | #include <linux/gpio.h> | 31 | #include <linux/gpio.h> |
32 | #include <linux/slab.h> | 32 | #include <linux/slab.h> |
33 | #include <linux/clk.h> | ||
34 | #include <linux/pm_runtime.h> | ||
35 | #include <linux/acpi.h> | ||
33 | 36 | ||
34 | #include <asm/io.h> | 37 | #include <asm/io.h> |
35 | #include <asm/irq.h> | 38 | #include <asm/irq.h> |
36 | #include <asm/delay.h> | 39 | #include <asm/delay.h> |
37 | 40 | ||
41 | #include "spi-pxa2xx.h" | ||
38 | 42 | ||
39 | MODULE_AUTHOR("Stephen Street"); | 43 | MODULE_AUTHOR("Stephen Street"); |
40 | MODULE_DESCRIPTION("PXA2xx SSP SPI Controller"); | 44 | MODULE_DESCRIPTION("PXA2xx SSP SPI Controller"); |
@@ -45,12 +49,6 @@ MODULE_ALIAS("platform:pxa2xx-spi"); | |||
45 | 49 | ||
46 | #define TIMOUT_DFLT 1000 | 50 | #define TIMOUT_DFLT 1000 |
47 | 51 | ||
48 | #define DMA_INT_MASK (DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERR) | ||
49 | #define RESET_DMA_CHANNEL (DCSR_NODESC | DMA_INT_MASK) | ||
50 | #define IS_DMA_ALIGNED(x) ((((u32)(x)) & 0x07) == 0) | ||
51 | #define MAX_DMA_LEN 8191 | ||
52 | #define DMA_ALIGNMENT 8 | ||
53 | |||
54 | /* | 52 | /* |
55 | * for testing SSCR1 changes that require SSP restart, basically | 53 | * for testing SSCR1 changes that require SSP restart, basically |
56 | * everything except the service and interrupt enables, the pxa270 developer | 54 | * everything except the service and interrupt enables, the pxa270 developer |
@@ -65,115 +63,97 @@ MODULE_ALIAS("platform:pxa2xx-spi"); | |||
65 | | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \ | 63 | | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \ |
66 | | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) | 64 | | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) |
67 | 65 | ||
68 | #define DEFINE_SSP_REG(reg, off) \ | 66 | #define LPSS_RX_THRESH_DFLT 64 |
69 | static inline u32 read_##reg(void const __iomem *p) \ | 67 | #define LPSS_TX_LOTHRESH_DFLT 160 |
70 | { return __raw_readl(p + (off)); } \ | 68 | #define LPSS_TX_HITHRESH_DFLT 224 |
71 | \ | ||
72 | static inline void write_##reg(u32 v, void __iomem *p) \ | ||
73 | { __raw_writel(v, p + (off)); } | ||
74 | |||
75 | DEFINE_SSP_REG(SSCR0, 0x00) | ||
76 | DEFINE_SSP_REG(SSCR1, 0x04) | ||
77 | DEFINE_SSP_REG(SSSR, 0x08) | ||
78 | DEFINE_SSP_REG(SSITR, 0x0c) | ||
79 | DEFINE_SSP_REG(SSDR, 0x10) | ||
80 | DEFINE_SSP_REG(SSTO, 0x28) | ||
81 | DEFINE_SSP_REG(SSPSP, 0x2c) | ||
82 | |||
83 | #define START_STATE ((void*)0) | ||
84 | #define RUNNING_STATE ((void*)1) | ||
85 | #define DONE_STATE ((void*)2) | ||
86 | #define ERROR_STATE ((void*)-1) | ||
87 | |||
88 | #define QUEUE_RUNNING 0 | ||
89 | #define QUEUE_STOPPED 1 | ||
90 | |||
91 | struct driver_data { | ||
92 | /* Driver model hookup */ | ||
93 | struct platform_device *pdev; | ||
94 | |||
95 | /* SSP Info */ | ||
96 | struct ssp_device *ssp; | ||
97 | 69 | ||
98 | /* SPI framework hookup */ | 70 | /* Offset from drv_data->lpss_base */ |
99 | enum pxa_ssp_type ssp_type; | 71 | #define SPI_CS_CONTROL 0x18 |
100 | struct spi_master *master; | 72 | #define SPI_CS_CONTROL_SW_MODE BIT(0) |
73 | #define SPI_CS_CONTROL_CS_HIGH BIT(1) | ||
101 | 74 | ||
102 | /* PXA hookup */ | 75 | static bool is_lpss_ssp(const struct driver_data *drv_data) |
103 | struct pxa2xx_spi_master *master_info; | 76 | { |
104 | 77 | return drv_data->ssp_type == LPSS_SSP; | |
105 | /* DMA setup stuff */ | 78 | } |
106 | int rx_channel; | ||
107 | int tx_channel; | ||
108 | u32 *null_dma_buf; | ||
109 | |||
110 | /* SSP register addresses */ | ||
111 | void __iomem *ioaddr; | ||
112 | u32 ssdr_physical; | ||
113 | |||
114 | /* SSP masks*/ | ||
115 | u32 dma_cr1; | ||
116 | u32 int_cr1; | ||
117 | u32 clear_sr; | ||
118 | u32 mask_sr; | ||
119 | |||
120 | /* Driver message queue */ | ||
121 | struct workqueue_struct *workqueue; | ||
122 | struct work_struct pump_messages; | ||
123 | spinlock_t lock; | ||
124 | struct list_head queue; | ||
125 | int busy; | ||
126 | int run; | ||
127 | |||
128 | /* Message Transfer pump */ | ||
129 | struct tasklet_struct pump_transfers; | ||
130 | |||
131 | /* Current message transfer state info */ | ||
132 | struct spi_message* cur_msg; | ||
133 | struct spi_transfer* cur_transfer; | ||
134 | struct chip_data *cur_chip; | ||
135 | size_t len; | ||
136 | void *tx; | ||
137 | void *tx_end; | ||
138 | void *rx; | ||
139 | void *rx_end; | ||
140 | int dma_mapped; | ||
141 | dma_addr_t rx_dma; | ||
142 | dma_addr_t tx_dma; | ||
143 | size_t rx_map_len; | ||
144 | size_t tx_map_len; | ||
145 | u8 n_bytes; | ||
146 | u32 dma_width; | ||
147 | int (*write)(struct driver_data *drv_data); | ||
148 | int (*read)(struct driver_data *drv_data); | ||
149 | irqreturn_t (*transfer_handler)(struct driver_data *drv_data); | ||
150 | void (*cs_control)(u32 command); | ||
151 | }; | ||
152 | 79 | ||
153 | struct chip_data { | 80 | /* |
154 | u32 cr0; | 81 | * Read and write LPSS SSP private registers. Caller must first check that |
155 | u32 cr1; | 82 | * is_lpss_ssp() returns true before these can be called. |
156 | u32 psp; | 83 | */ |
157 | u32 timeout; | 84 | static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset) |
158 | u8 n_bytes; | 85 | { |
159 | u32 dma_width; | 86 | WARN_ON(!drv_data->lpss_base); |
160 | u32 dma_burst_size; | 87 | return readl(drv_data->lpss_base + offset); |
161 | u32 threshold; | 88 | } |
162 | u32 dma_threshold; | ||
163 | u8 enable_dma; | ||
164 | u8 bits_per_word; | ||
165 | u32 speed_hz; | ||
166 | union { | ||
167 | int gpio_cs; | ||
168 | unsigned int frm; | ||
169 | }; | ||
170 | int gpio_cs_inverted; | ||
171 | int (*write)(struct driver_data *drv_data); | ||
172 | int (*read)(struct driver_data *drv_data); | ||
173 | void (*cs_control)(u32 command); | ||
174 | }; | ||
175 | 89 | ||
176 | static void pump_messages(struct work_struct *work); | 90 | static void __lpss_ssp_write_priv(struct driver_data *drv_data, |
91 | unsigned offset, u32 value) | ||
92 | { | ||
93 | WARN_ON(!drv_data->lpss_base); | ||
94 | writel(value, drv_data->lpss_base + offset); | ||
95 | } | ||
96 | |||
97 | /* | ||
98 | * lpss_ssp_setup - perform LPSS SSP specific setup | ||
99 | * @drv_data: pointer to the driver private data | ||
100 | * | ||
101 | * Perform LPSS SSP specific setup. This function must be called first if | ||
102 | * one is going to use LPSS SSP private registers. | ||
103 | */ | ||
104 | static void lpss_ssp_setup(struct driver_data *drv_data) | ||
105 | { | ||
106 | unsigned offset = 0x400; | ||
107 | u32 value, orig; | ||
108 | |||
109 | if (!is_lpss_ssp(drv_data)) | ||
110 | return; | ||
111 | |||
112 | /* | ||
113 | * Perform auto-detection of the LPSS SSP private registers. They | ||
114 | * can be either at 1k or 2k offset from the base address. | ||
115 | */ | ||
116 | orig = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); | ||
117 | |||
118 | value = orig | SPI_CS_CONTROL_SW_MODE; | ||
119 | writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL); | ||
120 | value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); | ||
121 | if (value != (orig | SPI_CS_CONTROL_SW_MODE)) { | ||
122 | offset = 0x800; | ||
123 | goto detection_done; | ||
124 | } | ||
125 | |||
126 | value &= ~SPI_CS_CONTROL_SW_MODE; | ||
127 | writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL); | ||
128 | value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); | ||
129 | if (value != orig) { | ||
130 | offset = 0x800; | ||
131 | goto detection_done; | ||
132 | } | ||
133 | |||
134 | detection_done: | ||
135 | /* Now set the LPSS base */ | ||
136 | drv_data->lpss_base = drv_data->ioaddr + offset; | ||
137 | |||
138 | /* Enable software chip select control */ | ||
139 | value = SPI_CS_CONTROL_SW_MODE | SPI_CS_CONTROL_CS_HIGH; | ||
140 | __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value); | ||
141 | } | ||
142 | |||
143 | static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable) | ||
144 | { | ||
145 | u32 value; | ||
146 | |||
147 | if (!is_lpss_ssp(drv_data)) | ||
148 | return; | ||
149 | |||
150 | value = __lpss_ssp_read_priv(drv_data, SPI_CS_CONTROL); | ||
151 | if (enable) | ||
152 | value &= ~SPI_CS_CONTROL_CS_HIGH; | ||
153 | else | ||
154 | value |= SPI_CS_CONTROL_CS_HIGH; | ||
155 | __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value); | ||
156 | } | ||
177 | 157 | ||
178 | static void cs_assert(struct driver_data *drv_data) | 158 | static void cs_assert(struct driver_data *drv_data) |
179 | { | 159 | { |
@@ -189,8 +169,12 @@ static void cs_assert(struct driver_data *drv_data) | |||
189 | return; | 169 | return; |
190 | } | 170 | } |
191 | 171 | ||
192 | if (gpio_is_valid(chip->gpio_cs)) | 172 | if (gpio_is_valid(chip->gpio_cs)) { |
193 | gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted); | 173 | gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted); |
174 | return; | ||
175 | } | ||
176 | |||
177 | lpss_ssp_cs_control(drv_data, true); | ||
194 | } | 178 | } |
195 | 179 | ||
196 | static void cs_deassert(struct driver_data *drv_data) | 180 | static void cs_deassert(struct driver_data *drv_data) |
@@ -205,30 +189,15 @@ static void cs_deassert(struct driver_data *drv_data) | |||
205 | return; | 189 | return; |
206 | } | 190 | } |
207 | 191 | ||
208 | if (gpio_is_valid(chip->gpio_cs)) | 192 | if (gpio_is_valid(chip->gpio_cs)) { |
209 | gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted); | 193 | gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted); |
210 | } | 194 | return; |
211 | 195 | } | |
212 | static void write_SSSR_CS(struct driver_data *drv_data, u32 val) | ||
213 | { | ||
214 | void __iomem *reg = drv_data->ioaddr; | ||
215 | |||
216 | if (drv_data->ssp_type == CE4100_SSP) | ||
217 | val |= read_SSSR(reg) & SSSR_ALT_FRM_MASK; | ||
218 | |||
219 | write_SSSR(val, reg); | ||
220 | } | ||
221 | 196 | ||
222 | static int pxa25x_ssp_comp(struct driver_data *drv_data) | 197 | lpss_ssp_cs_control(drv_data, false); |
223 | { | ||
224 | if (drv_data->ssp_type == PXA25x_SSP) | ||
225 | return 1; | ||
226 | if (drv_data->ssp_type == CE4100_SSP) | ||
227 | return 1; | ||
228 | return 0; | ||
229 | } | 198 | } |
230 | 199 | ||
231 | static int flush(struct driver_data *drv_data) | 200 | int pxa2xx_spi_flush(struct driver_data *drv_data) |
232 | { | 201 | { |
233 | unsigned long limit = loops_per_jiffy << 1; | 202 | unsigned long limit = loops_per_jiffy << 1; |
234 | 203 | ||
@@ -354,7 +323,7 @@ static int u32_reader(struct driver_data *drv_data) | |||
354 | return drv_data->rx == drv_data->rx_end; | 323 | return drv_data->rx == drv_data->rx_end; |
355 | } | 324 | } |
356 | 325 | ||
357 | static void *next_transfer(struct driver_data *drv_data) | 326 | void *pxa2xx_spi_next_transfer(struct driver_data *drv_data) |
358 | { | 327 | { |
359 | struct spi_message *msg = drv_data->cur_msg; | 328 | struct spi_message *msg = drv_data->cur_msg; |
360 | struct spi_transfer *trans = drv_data->cur_transfer; | 329 | struct spi_transfer *trans = drv_data->cur_transfer; |
@@ -370,89 +339,15 @@ static void *next_transfer(struct driver_data *drv_data) | |||
370 | return DONE_STATE; | 339 | return DONE_STATE; |
371 | } | 340 | } |
372 | 341 | ||
373 | static int map_dma_buffers(struct driver_data *drv_data) | ||
374 | { | ||
375 | struct spi_message *msg = drv_data->cur_msg; | ||
376 | struct device *dev = &msg->spi->dev; | ||
377 | |||
378 | if (!drv_data->cur_chip->enable_dma) | ||
379 | return 0; | ||
380 | |||
381 | if (msg->is_dma_mapped) | ||
382 | return drv_data->rx_dma && drv_data->tx_dma; | ||
383 | |||
384 | if (!IS_DMA_ALIGNED(drv_data->rx) || !IS_DMA_ALIGNED(drv_data->tx)) | ||
385 | return 0; | ||
386 | |||
387 | /* Modify setup if rx buffer is null */ | ||
388 | if (drv_data->rx == NULL) { | ||
389 | *drv_data->null_dma_buf = 0; | ||
390 | drv_data->rx = drv_data->null_dma_buf; | ||
391 | drv_data->rx_map_len = 4; | ||
392 | } else | ||
393 | drv_data->rx_map_len = drv_data->len; | ||
394 | |||
395 | |||
396 | /* Modify setup if tx buffer is null */ | ||
397 | if (drv_data->tx == NULL) { | ||
398 | *drv_data->null_dma_buf = 0; | ||
399 | drv_data->tx = drv_data->null_dma_buf; | ||
400 | drv_data->tx_map_len = 4; | ||
401 | } else | ||
402 | drv_data->tx_map_len = drv_data->len; | ||
403 | |||
404 | /* Stream map the tx buffer. Always do DMA_TO_DEVICE first | ||
405 | * so we flush the cache *before* invalidating it, in case | ||
406 | * the tx and rx buffers overlap. | ||
407 | */ | ||
408 | drv_data->tx_dma = dma_map_single(dev, drv_data->tx, | ||
409 | drv_data->tx_map_len, DMA_TO_DEVICE); | ||
410 | if (dma_mapping_error(dev, drv_data->tx_dma)) | ||
411 | return 0; | ||
412 | |||
413 | /* Stream map the rx buffer */ | ||
414 | drv_data->rx_dma = dma_map_single(dev, drv_data->rx, | ||
415 | drv_data->rx_map_len, DMA_FROM_DEVICE); | ||
416 | if (dma_mapping_error(dev, drv_data->rx_dma)) { | ||
417 | dma_unmap_single(dev, drv_data->tx_dma, | ||
418 | drv_data->tx_map_len, DMA_TO_DEVICE); | ||
419 | return 0; | ||
420 | } | ||
421 | |||
422 | return 1; | ||
423 | } | ||
424 | |||
425 | static void unmap_dma_buffers(struct driver_data *drv_data) | ||
426 | { | ||
427 | struct device *dev; | ||
428 | |||
429 | if (!drv_data->dma_mapped) | ||
430 | return; | ||
431 | |||
432 | if (!drv_data->cur_msg->is_dma_mapped) { | ||
433 | dev = &drv_data->cur_msg->spi->dev; | ||
434 | dma_unmap_single(dev, drv_data->rx_dma, | ||
435 | drv_data->rx_map_len, DMA_FROM_DEVICE); | ||
436 | dma_unmap_single(dev, drv_data->tx_dma, | ||
437 | drv_data->tx_map_len, DMA_TO_DEVICE); | ||
438 | } | ||
439 | |||
440 | drv_data->dma_mapped = 0; | ||
441 | } | ||
442 | |||
443 | /* caller already set message->status; dma and pio irqs are blocked */ | 342 | /* caller already set message->status; dma and pio irqs are blocked */ |
444 | static void giveback(struct driver_data *drv_data) | 343 | static void giveback(struct driver_data *drv_data) |
445 | { | 344 | { |
446 | struct spi_transfer* last_transfer; | 345 | struct spi_transfer* last_transfer; |
447 | unsigned long flags; | ||
448 | struct spi_message *msg; | 346 | struct spi_message *msg; |
449 | 347 | ||
450 | spin_lock_irqsave(&drv_data->lock, flags); | ||
451 | msg = drv_data->cur_msg; | 348 | msg = drv_data->cur_msg; |
452 | drv_data->cur_msg = NULL; | 349 | drv_data->cur_msg = NULL; |
453 | drv_data->cur_transfer = NULL; | 350 | drv_data->cur_transfer = NULL; |
454 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | ||
455 | spin_unlock_irqrestore(&drv_data->lock, flags); | ||
456 | 351 | ||
457 | last_transfer = list_entry(msg->transfers.prev, | 352 | last_transfer = list_entry(msg->transfers.prev, |
458 | struct spi_transfer, | 353 | struct spi_transfer, |
@@ -481,13 +376,7 @@ static void giveback(struct driver_data *drv_data) | |||
481 | */ | 376 | */ |
482 | 377 | ||
483 | /* get a pointer to the next message, if any */ | 378 | /* get a pointer to the next message, if any */ |
484 | spin_lock_irqsave(&drv_data->lock, flags); | 379 | next_msg = spi_get_next_queued_message(drv_data->master); |
485 | if (list_empty(&drv_data->queue)) | ||
486 | next_msg = NULL; | ||
487 | else | ||
488 | next_msg = list_entry(drv_data->queue.next, | ||
489 | struct spi_message, queue); | ||
490 | spin_unlock_irqrestore(&drv_data->lock, flags); | ||
491 | 380 | ||
492 | /* see if the next and current messages point | 381 | /* see if the next and current messages point |
493 | * to the same chip | 382 | * to the same chip |
@@ -498,168 +387,10 @@ static void giveback(struct driver_data *drv_data) | |||
498 | cs_deassert(drv_data); | 387 | cs_deassert(drv_data); |
499 | } | 388 | } |
500 | 389 | ||
501 | msg->state = NULL; | 390 | spi_finalize_current_message(drv_data->master); |
502 | if (msg->complete) | ||
503 | msg->complete(msg->context); | ||
504 | |||
505 | drv_data->cur_chip = NULL; | 391 | drv_data->cur_chip = NULL; |
506 | } | 392 | } |
507 | 393 | ||
508 | static int wait_ssp_rx_stall(void const __iomem *ioaddr) | ||
509 | { | ||
510 | unsigned long limit = loops_per_jiffy << 1; | ||
511 | |||
512 | while ((read_SSSR(ioaddr) & SSSR_BSY) && --limit) | ||
513 | cpu_relax(); | ||
514 | |||
515 | return limit; | ||
516 | } | ||
517 | |||
518 | static int wait_dma_channel_stop(int channel) | ||
519 | { | ||
520 | unsigned long limit = loops_per_jiffy << 1; | ||
521 | |||
522 | while (!(DCSR(channel) & DCSR_STOPSTATE) && --limit) | ||
523 | cpu_relax(); | ||
524 | |||
525 | return limit; | ||
526 | } | ||
527 | |||
528 | static void dma_error_stop(struct driver_data *drv_data, const char *msg) | ||
529 | { | ||
530 | void __iomem *reg = drv_data->ioaddr; | ||
531 | |||
532 | /* Stop and reset */ | ||
533 | DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL; | ||
534 | DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL; | ||
535 | write_SSSR_CS(drv_data, drv_data->clear_sr); | ||
536 | write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg); | ||
537 | if (!pxa25x_ssp_comp(drv_data)) | ||
538 | write_SSTO(0, reg); | ||
539 | flush(drv_data); | ||
540 | write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); | ||
541 | |||
542 | unmap_dma_buffers(drv_data); | ||
543 | |||
544 | dev_err(&drv_data->pdev->dev, "%s\n", msg); | ||
545 | |||
546 | drv_data->cur_msg->state = ERROR_STATE; | ||
547 | tasklet_schedule(&drv_data->pump_transfers); | ||
548 | } | ||
549 | |||
550 | static void dma_transfer_complete(struct driver_data *drv_data) | ||
551 | { | ||
552 | void __iomem *reg = drv_data->ioaddr; | ||
553 | struct spi_message *msg = drv_data->cur_msg; | ||
554 | |||
555 | /* Clear and disable interrupts on SSP and DMA channels*/ | ||
556 | write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg); | ||
557 | write_SSSR_CS(drv_data, drv_data->clear_sr); | ||
558 | DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL; | ||
559 | DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL; | ||
560 | |||
561 | if (wait_dma_channel_stop(drv_data->rx_channel) == 0) | ||
562 | dev_err(&drv_data->pdev->dev, | ||
563 | "dma_handler: dma rx channel stop failed\n"); | ||
564 | |||
565 | if (wait_ssp_rx_stall(drv_data->ioaddr) == 0) | ||
566 | dev_err(&drv_data->pdev->dev, | ||
567 | "dma_transfer: ssp rx stall failed\n"); | ||
568 | |||
569 | unmap_dma_buffers(drv_data); | ||
570 | |||
571 | /* update the buffer pointer for the amount completed in dma */ | ||
572 | drv_data->rx += drv_data->len - | ||
573 | (DCMD(drv_data->rx_channel) & DCMD_LENGTH); | ||
574 | |||
575 | /* read trailing data from fifo, it does not matter how many | ||
576 | * bytes are in the fifo just read until buffer is full | ||
577 | * or fifo is empty, which ever occurs first */ | ||
578 | drv_data->read(drv_data); | ||
579 | |||
580 | /* return count of what was actually read */ | ||
581 | msg->actual_length += drv_data->len - | ||
582 | (drv_data->rx_end - drv_data->rx); | ||
583 | |||
584 | /* Transfer delays and chip select release are | ||
585 | * handled in pump_transfers or giveback | ||
586 | */ | ||
587 | |||
588 | /* Move to next transfer */ | ||
589 | msg->state = next_transfer(drv_data); | ||
590 | |||
591 | /* Schedule transfer tasklet */ | ||
592 | tasklet_schedule(&drv_data->pump_transfers); | ||
593 | } | ||
594 | |||
595 | static void dma_handler(int channel, void *data) | ||
596 | { | ||
597 | struct driver_data *drv_data = data; | ||
598 | u32 irq_status = DCSR(channel) & DMA_INT_MASK; | ||
599 | |||
600 | if (irq_status & DCSR_BUSERR) { | ||
601 | |||
602 | if (channel == drv_data->tx_channel) | ||
603 | dma_error_stop(drv_data, | ||
604 | "dma_handler: " | ||
605 | "bad bus address on tx channel"); | ||
606 | else | ||
607 | dma_error_stop(drv_data, | ||
608 | "dma_handler: " | ||
609 | "bad bus address on rx channel"); | ||
610 | return; | ||
611 | } | ||
612 | |||
613 | /* PXA255x_SSP has no timeout interrupt, wait for tailing bytes */ | ||
614 | if ((channel == drv_data->tx_channel) | ||
615 | && (irq_status & DCSR_ENDINTR) | ||
616 | && (drv_data->ssp_type == PXA25x_SSP)) { | ||
617 | |||
618 | /* Wait for rx to stall */ | ||
619 | if (wait_ssp_rx_stall(drv_data->ioaddr) == 0) | ||
620 | dev_err(&drv_data->pdev->dev, | ||
621 | "dma_handler: ssp rx stall failed\n"); | ||
622 | |||
623 | /* finish this transfer, start the next */ | ||
624 | dma_transfer_complete(drv_data); | ||
625 | } | ||
626 | } | ||
627 | |||
628 | static irqreturn_t dma_transfer(struct driver_data *drv_data) | ||
629 | { | ||
630 | u32 irq_status; | ||
631 | void __iomem *reg = drv_data->ioaddr; | ||
632 | |||
633 | irq_status = read_SSSR(reg) & drv_data->mask_sr; | ||
634 | if (irq_status & SSSR_ROR) { | ||
635 | dma_error_stop(drv_data, "dma_transfer: fifo overrun"); | ||
636 | return IRQ_HANDLED; | ||
637 | } | ||
638 | |||
639 | /* Check for false positive timeout */ | ||
640 | if ((irq_status & SSSR_TINT) | ||
641 | && (DCSR(drv_data->tx_channel) & DCSR_RUN)) { | ||
642 | write_SSSR(SSSR_TINT, reg); | ||
643 | return IRQ_HANDLED; | ||
644 | } | ||
645 | |||
646 | if (irq_status & SSSR_TINT || drv_data->rx == drv_data->rx_end) { | ||
647 | |||
648 | /* Clear and disable timeout interrupt, do the rest in | ||
649 | * dma_transfer_complete */ | ||
650 | if (!pxa25x_ssp_comp(drv_data)) | ||
651 | write_SSTO(0, reg); | ||
652 | |||
653 | /* finish this transfer, start the next */ | ||
654 | dma_transfer_complete(drv_data); | ||
655 | |||
656 | return IRQ_HANDLED; | ||
657 | } | ||
658 | |||
659 | /* Opps problem detected */ | ||
660 | return IRQ_NONE; | ||
661 | } | ||
662 | |||
663 | static void reset_sccr1(struct driver_data *drv_data) | 394 | static void reset_sccr1(struct driver_data *drv_data) |
664 | { | 395 | { |
665 | void __iomem *reg = drv_data->ioaddr; | 396 | void __iomem *reg = drv_data->ioaddr; |
@@ -681,7 +412,7 @@ static void int_error_stop(struct driver_data *drv_data, const char* msg) | |||
681 | reset_sccr1(drv_data); | 412 | reset_sccr1(drv_data); |
682 | if (!pxa25x_ssp_comp(drv_data)) | 413 | if (!pxa25x_ssp_comp(drv_data)) |
683 | write_SSTO(0, reg); | 414 | write_SSTO(0, reg); |
684 | flush(drv_data); | 415 | pxa2xx_spi_flush(drv_data); |
685 | write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); | 416 | write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); |
686 | 417 | ||
687 | dev_err(&drv_data->pdev->dev, "%s\n", msg); | 418 | dev_err(&drv_data->pdev->dev, "%s\n", msg); |
@@ -709,7 +440,7 @@ static void int_transfer_complete(struct driver_data *drv_data) | |||
709 | */ | 440 | */ |
710 | 441 | ||
711 | /* Move to next transfer */ | 442 | /* Move to next transfer */ |
712 | drv_data->cur_msg->state = next_transfer(drv_data); | 443 | drv_data->cur_msg->state = pxa2xx_spi_next_transfer(drv_data); |
713 | 444 | ||
714 | /* Schedule transfer tasklet */ | 445 | /* Schedule transfer tasklet */ |
715 | tasklet_schedule(&drv_data->pump_transfers); | 446 | tasklet_schedule(&drv_data->pump_transfers); |
@@ -789,10 +520,20 @@ static irqreturn_t ssp_int(int irq, void *dev_id) | |||
789 | { | 520 | { |
790 | struct driver_data *drv_data = dev_id; | 521 | struct driver_data *drv_data = dev_id; |
791 | void __iomem *reg = drv_data->ioaddr; | 522 | void __iomem *reg = drv_data->ioaddr; |
792 | u32 sccr1_reg = read_SSCR1(reg); | 523 | u32 sccr1_reg; |
793 | u32 mask = drv_data->mask_sr; | 524 | u32 mask = drv_data->mask_sr; |
794 | u32 status; | 525 | u32 status; |
795 | 526 | ||
527 | /* | ||
528 | * The IRQ might be shared with other peripherals so we must first | ||
529 | * check that are we RPM suspended or not. If we are we assume that | ||
530 | * the IRQ was not for us (we shouldn't be RPM suspended when the | ||
531 | * interrupt is enabled). | ||
532 | */ | ||
533 | if (pm_runtime_suspended(&drv_data->pdev->dev)) | ||
534 | return IRQ_NONE; | ||
535 | |||
536 | sccr1_reg = read_SSCR1(reg); | ||
796 | status = read_SSSR(reg); | 537 | status = read_SSSR(reg); |
797 | 538 | ||
798 | /* Ignore possible writes if we don't need to write */ | 539 | /* Ignore possible writes if we don't need to write */ |
@@ -820,106 +561,12 @@ static irqreturn_t ssp_int(int irq, void *dev_id) | |||
820 | return drv_data->transfer_handler(drv_data); | 561 | return drv_data->transfer_handler(drv_data); |
821 | } | 562 | } |
822 | 563 | ||
823 | static int set_dma_burst_and_threshold(struct chip_data *chip, | 564 | static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate) |
824 | struct spi_device *spi, | ||
825 | u8 bits_per_word, u32 *burst_code, | ||
826 | u32 *threshold) | ||
827 | { | 565 | { |
828 | struct pxa2xx_spi_chip *chip_info = | 566 | unsigned long ssp_clk = drv_data->max_clk_rate; |
829 | (struct pxa2xx_spi_chip *)spi->controller_data; | 567 | const struct ssp_device *ssp = drv_data->ssp; |
830 | int bytes_per_word; | ||
831 | int burst_bytes; | ||
832 | int thresh_words; | ||
833 | int req_burst_size; | ||
834 | int retval = 0; | ||
835 | |||
836 | /* Set the threshold (in registers) to equal the same amount of data | ||
837 | * as represented by burst size (in bytes). The computation below | ||
838 | * is (burst_size rounded up to nearest 8 byte, word or long word) | ||
839 | * divided by (bytes/register); the tx threshold is the inverse of | ||
840 | * the rx, so that there will always be enough data in the rx fifo | ||
841 | * to satisfy a burst, and there will always be enough space in the | ||
842 | * tx fifo to accept a burst (a tx burst will overwrite the fifo if | ||
843 | * there is not enough space), there must always remain enough empty | ||
844 | * space in the rx fifo for any data loaded to the tx fifo. | ||
845 | * Whenever burst_size (in bytes) equals bits/word, the fifo threshold | ||
846 | * will be 8, or half the fifo; | ||
847 | * The threshold can only be set to 2, 4 or 8, but not 16, because | ||
848 | * to burst 16 to the tx fifo, the fifo would have to be empty; | ||
849 | * however, the minimum fifo trigger level is 1, and the tx will | ||
850 | * request service when the fifo is at this level, with only 15 spaces. | ||
851 | */ | ||
852 | 568 | ||
853 | /* find bytes/word */ | 569 | rate = min_t(int, ssp_clk, rate); |
854 | if (bits_per_word <= 8) | ||
855 | bytes_per_word = 1; | ||
856 | else if (bits_per_word <= 16) | ||
857 | bytes_per_word = 2; | ||
858 | else | ||
859 | bytes_per_word = 4; | ||
860 | |||
861 | /* use struct pxa2xx_spi_chip->dma_burst_size if available */ | ||
862 | if (chip_info) | ||
863 | req_burst_size = chip_info->dma_burst_size; | ||
864 | else { | ||
865 | switch (chip->dma_burst_size) { | ||
866 | default: | ||
867 | /* if the default burst size is not set, | ||
868 | * do it now */ | ||
869 | chip->dma_burst_size = DCMD_BURST8; | ||
870 | case DCMD_BURST8: | ||
871 | req_burst_size = 8; | ||
872 | break; | ||
873 | case DCMD_BURST16: | ||
874 | req_burst_size = 16; | ||
875 | break; | ||
876 | case DCMD_BURST32: | ||
877 | req_burst_size = 32; | ||
878 | break; | ||
879 | } | ||
880 | } | ||
881 | if (req_burst_size <= 8) { | ||
882 | *burst_code = DCMD_BURST8; | ||
883 | burst_bytes = 8; | ||
884 | } else if (req_burst_size <= 16) { | ||
885 | if (bytes_per_word == 1) { | ||
886 | /* don't burst more than 1/2 the fifo */ | ||
887 | *burst_code = DCMD_BURST8; | ||
888 | burst_bytes = 8; | ||
889 | retval = 1; | ||
890 | } else { | ||
891 | *burst_code = DCMD_BURST16; | ||
892 | burst_bytes = 16; | ||
893 | } | ||
894 | } else { | ||
895 | if (bytes_per_word == 1) { | ||
896 | /* don't burst more than 1/2 the fifo */ | ||
897 | *burst_code = DCMD_BURST8; | ||
898 | burst_bytes = 8; | ||
899 | retval = 1; | ||
900 | } else if (bytes_per_word == 2) { | ||
901 | /* don't burst more than 1/2 the fifo */ | ||
902 | *burst_code = DCMD_BURST16; | ||
903 | burst_bytes = 16; | ||
904 | retval = 1; | ||
905 | } else { | ||
906 | *burst_code = DCMD_BURST32; | ||
907 | burst_bytes = 32; | ||
908 | } | ||
909 | } | ||
910 | |||
911 | thresh_words = burst_bytes / bytes_per_word; | ||
912 | |||
913 | /* thresh_words will be between 2 and 8 */ | ||
914 | *threshold = (SSCR1_RxTresh(thresh_words) & SSCR1_RFT) | ||
915 | | (SSCR1_TxTresh(16-thresh_words) & SSCR1_TFT); | ||
916 | |||
917 | return retval; | ||
918 | } | ||
919 | |||
920 | static unsigned int ssp_get_clk_div(struct ssp_device *ssp, int rate) | ||
921 | { | ||
922 | unsigned long ssp_clk = clk_get_rate(ssp->clk); | ||
923 | 570 | ||
924 | if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP) | 571 | if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP) |
925 | return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8; | 572 | return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8; |
@@ -934,7 +581,6 @@ static void pump_transfers(unsigned long data) | |||
934 | struct spi_transfer *transfer = NULL; | 581 | struct spi_transfer *transfer = NULL; |
935 | struct spi_transfer *previous = NULL; | 582 | struct spi_transfer *previous = NULL; |
936 | struct chip_data *chip = NULL; | 583 | struct chip_data *chip = NULL; |
937 | struct ssp_device *ssp = drv_data->ssp; | ||
938 | void __iomem *reg = drv_data->ioaddr; | 584 | void __iomem *reg = drv_data->ioaddr; |
939 | u32 clk_div = 0; | 585 | u32 clk_div = 0; |
940 | u8 bits = 0; | 586 | u8 bits = 0; |
@@ -976,8 +622,8 @@ static void pump_transfers(unsigned long data) | |||
976 | cs_deassert(drv_data); | 622 | cs_deassert(drv_data); |
977 | } | 623 | } |
978 | 624 | ||
979 | /* Check for transfers that need multiple DMA segments */ | 625 | /* Check if we can DMA this transfer */ |
980 | if (transfer->len > MAX_DMA_LEN && chip->enable_dma) { | 626 | if (!pxa2xx_spi_dma_is_possible(transfer->len) && chip->enable_dma) { |
981 | 627 | ||
982 | /* reject already-mapped transfers; PIO won't always work */ | 628 | /* reject already-mapped transfers; PIO won't always work */ |
983 | if (message->is_dma_mapped | 629 | if (message->is_dma_mapped |
@@ -1000,21 +646,20 @@ static void pump_transfers(unsigned long data) | |||
1000 | } | 646 | } |
1001 | 647 | ||
1002 | /* Setup the transfer state based on the type of transfer */ | 648 | /* Setup the transfer state based on the type of transfer */ |
1003 | if (flush(drv_data) == 0) { | 649 | if (pxa2xx_spi_flush(drv_data) == 0) { |
1004 | dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); | 650 | dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); |
1005 | message->status = -EIO; | 651 | message->status = -EIO; |
1006 | giveback(drv_data); | 652 | giveback(drv_data); |
1007 | return; | 653 | return; |
1008 | } | 654 | } |
1009 | drv_data->n_bytes = chip->n_bytes; | 655 | drv_data->n_bytes = chip->n_bytes; |
1010 | drv_data->dma_width = chip->dma_width; | ||
1011 | drv_data->tx = (void *)transfer->tx_buf; | 656 | drv_data->tx = (void *)transfer->tx_buf; |
1012 | drv_data->tx_end = drv_data->tx + transfer->len; | 657 | drv_data->tx_end = drv_data->tx + transfer->len; |
1013 | drv_data->rx = transfer->rx_buf; | 658 | drv_data->rx = transfer->rx_buf; |
1014 | drv_data->rx_end = drv_data->rx + transfer->len; | 659 | drv_data->rx_end = drv_data->rx + transfer->len; |
1015 | drv_data->rx_dma = transfer->rx_dma; | 660 | drv_data->rx_dma = transfer->rx_dma; |
1016 | drv_data->tx_dma = transfer->tx_dma; | 661 | drv_data->tx_dma = transfer->tx_dma; |
1017 | drv_data->len = transfer->len & DCMD_LENGTH; | 662 | drv_data->len = transfer->len; |
1018 | drv_data->write = drv_data->tx ? chip->write : null_writer; | 663 | drv_data->write = drv_data->tx ? chip->write : null_writer; |
1019 | drv_data->read = drv_data->rx ? chip->read : null_reader; | 664 | drv_data->read = drv_data->rx ? chip->read : null_reader; |
1020 | 665 | ||
@@ -1031,25 +676,22 @@ static void pump_transfers(unsigned long data) | |||
1031 | if (transfer->bits_per_word) | 676 | if (transfer->bits_per_word) |
1032 | bits = transfer->bits_per_word; | 677 | bits = transfer->bits_per_word; |
1033 | 678 | ||
1034 | clk_div = ssp_get_clk_div(ssp, speed); | 679 | clk_div = ssp_get_clk_div(drv_data, speed); |
1035 | 680 | ||
1036 | if (bits <= 8) { | 681 | if (bits <= 8) { |
1037 | drv_data->n_bytes = 1; | 682 | drv_data->n_bytes = 1; |
1038 | drv_data->dma_width = DCMD_WIDTH1; | ||
1039 | drv_data->read = drv_data->read != null_reader ? | 683 | drv_data->read = drv_data->read != null_reader ? |
1040 | u8_reader : null_reader; | 684 | u8_reader : null_reader; |
1041 | drv_data->write = drv_data->write != null_writer ? | 685 | drv_data->write = drv_data->write != null_writer ? |
1042 | u8_writer : null_writer; | 686 | u8_writer : null_writer; |
1043 | } else if (bits <= 16) { | 687 | } else if (bits <= 16) { |
1044 | drv_data->n_bytes = 2; | 688 | drv_data->n_bytes = 2; |
1045 | drv_data->dma_width = DCMD_WIDTH2; | ||
1046 | drv_data->read = drv_data->read != null_reader ? | 689 | drv_data->read = drv_data->read != null_reader ? |
1047 | u16_reader : null_reader; | 690 | u16_reader : null_reader; |
1048 | drv_data->write = drv_data->write != null_writer ? | 691 | drv_data->write = drv_data->write != null_writer ? |
1049 | u16_writer : null_writer; | 692 | u16_writer : null_writer; |
1050 | } else if (bits <= 32) { | 693 | } else if (bits <= 32) { |
1051 | drv_data->n_bytes = 4; | 694 | drv_data->n_bytes = 4; |
1052 | drv_data->dma_width = DCMD_WIDTH4; | ||
1053 | drv_data->read = drv_data->read != null_reader ? | 695 | drv_data->read = drv_data->read != null_reader ? |
1054 | u32_reader : null_reader; | 696 | u32_reader : null_reader; |
1055 | drv_data->write = drv_data->write != null_writer ? | 697 | drv_data->write = drv_data->write != null_writer ? |
@@ -1058,7 +700,8 @@ static void pump_transfers(unsigned long data) | |||
1058 | /* if bits/word is changed in dma mode, then must check the | 700 | /* if bits/word is changed in dma mode, then must check the |
1059 | * thresholds and burst also */ | 701 | * thresholds and burst also */ |
1060 | if (chip->enable_dma) { | 702 | if (chip->enable_dma) { |
1061 | if (set_dma_burst_and_threshold(chip, message->spi, | 703 | if (pxa2xx_spi_set_dma_burst_and_threshold(chip, |
704 | message->spi, | ||
1062 | bits, &dma_burst, | 705 | bits, &dma_burst, |
1063 | &dma_thresh)) | 706 | &dma_thresh)) |
1064 | if (printk_ratelimit()) | 707 | if (printk_ratelimit()) |
@@ -1077,70 +720,21 @@ static void pump_transfers(unsigned long data) | |||
1077 | 720 | ||
1078 | message->state = RUNNING_STATE; | 721 | message->state = RUNNING_STATE; |
1079 | 722 | ||
1080 | /* Try to map dma buffer and do a dma transfer if successful, but | ||
1081 | * only if the length is non-zero and less than MAX_DMA_LEN. | ||
1082 | * | ||
1083 | * Zero-length non-descriptor DMA is illegal on PXA2xx; force use | ||
1084 | * of PIO instead. Care is needed above because the transfer may | ||
1085 | * have have been passed with buffers that are already dma mapped. | ||
1086 | * A zero-length transfer in PIO mode will not try to write/read | ||
1087 | * to/from the buffers | ||
1088 | * | ||
1089 | * REVISIT large transfers are exactly where we most want to be | ||
1090 | * using DMA. If this happens much, split those transfers into | ||
1091 | * multiple DMA segments rather than forcing PIO. | ||
1092 | */ | ||
1093 | drv_data->dma_mapped = 0; | 723 | drv_data->dma_mapped = 0; |
1094 | if (drv_data->len > 0 && drv_data->len <= MAX_DMA_LEN) | 724 | if (pxa2xx_spi_dma_is_possible(drv_data->len)) |
1095 | drv_data->dma_mapped = map_dma_buffers(drv_data); | 725 | drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data); |
1096 | if (drv_data->dma_mapped) { | 726 | if (drv_data->dma_mapped) { |
1097 | 727 | ||
1098 | /* Ensure we have the correct interrupt handler */ | 728 | /* Ensure we have the correct interrupt handler */ |
1099 | drv_data->transfer_handler = dma_transfer; | 729 | drv_data->transfer_handler = pxa2xx_spi_dma_transfer; |
1100 | 730 | ||
1101 | /* Setup rx DMA Channel */ | 731 | pxa2xx_spi_dma_prepare(drv_data, dma_burst); |
1102 | DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL; | ||
1103 | DSADR(drv_data->rx_channel) = drv_data->ssdr_physical; | ||
1104 | DTADR(drv_data->rx_channel) = drv_data->rx_dma; | ||
1105 | if (drv_data->rx == drv_data->null_dma_buf) | ||
1106 | /* No target address increment */ | ||
1107 | DCMD(drv_data->rx_channel) = DCMD_FLOWSRC | ||
1108 | | drv_data->dma_width | ||
1109 | | dma_burst | ||
1110 | | drv_data->len; | ||
1111 | else | ||
1112 | DCMD(drv_data->rx_channel) = DCMD_INCTRGADDR | ||
1113 | | DCMD_FLOWSRC | ||
1114 | | drv_data->dma_width | ||
1115 | | dma_burst | ||
1116 | | drv_data->len; | ||
1117 | |||
1118 | /* Setup tx DMA Channel */ | ||
1119 | DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL; | ||
1120 | DSADR(drv_data->tx_channel) = drv_data->tx_dma; | ||
1121 | DTADR(drv_data->tx_channel) = drv_data->ssdr_physical; | ||
1122 | if (drv_data->tx == drv_data->null_dma_buf) | ||
1123 | /* No source address increment */ | ||
1124 | DCMD(drv_data->tx_channel) = DCMD_FLOWTRG | ||
1125 | | drv_data->dma_width | ||
1126 | | dma_burst | ||
1127 | | drv_data->len; | ||
1128 | else | ||
1129 | DCMD(drv_data->tx_channel) = DCMD_INCSRCADDR | ||
1130 | | DCMD_FLOWTRG | ||
1131 | | drv_data->dma_width | ||
1132 | | dma_burst | ||
1133 | | drv_data->len; | ||
1134 | |||
1135 | /* Enable dma end irqs on SSP to detect end of transfer */ | ||
1136 | if (drv_data->ssp_type == PXA25x_SSP) | ||
1137 | DCMD(drv_data->tx_channel) |= DCMD_ENDIRQEN; | ||
1138 | 732 | ||
1139 | /* Clear status and start DMA engine */ | 733 | /* Clear status and start DMA engine */ |
1140 | cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; | 734 | cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; |
1141 | write_SSSR(drv_data->clear_sr, reg); | 735 | write_SSSR(drv_data->clear_sr, reg); |
1142 | DCSR(drv_data->rx_channel) |= DCSR_RUN; | 736 | |
1143 | DCSR(drv_data->tx_channel) |= DCSR_RUN; | 737 | pxa2xx_spi_dma_start(drv_data); |
1144 | } else { | 738 | } else { |
1145 | /* Ensure we have the correct interrupt handler */ | 739 | /* Ensure we have the correct interrupt handler */ |
1146 | drv_data->transfer_handler = interrupt_transfer; | 740 | drv_data->transfer_handler = interrupt_transfer; |
@@ -1150,6 +744,13 @@ static void pump_transfers(unsigned long data) | |||
1150 | write_SSSR_CS(drv_data, drv_data->clear_sr); | 744 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
1151 | } | 745 | } |
1152 | 746 | ||
747 | if (is_lpss_ssp(drv_data)) { | ||
748 | if ((read_SSIRF(reg) & 0xff) != chip->lpss_rx_threshold) | ||
749 | write_SSIRF(chip->lpss_rx_threshold, reg); | ||
750 | if ((read_SSITF(reg) & 0xffff) != chip->lpss_tx_threshold) | ||
751 | write_SSITF(chip->lpss_tx_threshold, reg); | ||
752 | } | ||
753 | |||
1153 | /* see if we need to reload the config registers */ | 754 | /* see if we need to reload the config registers */ |
1154 | if ((read_SSCR0(reg) != cr0) | 755 | if ((read_SSCR0(reg) != cr0) |
1155 | || (read_SSCR1(reg) & SSCR1_CHANGE_MASK) != | 756 | || (read_SSCR1(reg) & SSCR1_CHANGE_MASK) != |
@@ -1176,31 +777,12 @@ static void pump_transfers(unsigned long data) | |||
1176 | write_SSCR1(cr1, reg); | 777 | write_SSCR1(cr1, reg); |
1177 | } | 778 | } |
1178 | 779 | ||
1179 | static void pump_messages(struct work_struct *work) | 780 | static int pxa2xx_spi_transfer_one_message(struct spi_master *master, |
781 | struct spi_message *msg) | ||
1180 | { | 782 | { |
1181 | struct driver_data *drv_data = | 783 | struct driver_data *drv_data = spi_master_get_devdata(master); |
1182 | container_of(work, struct driver_data, pump_messages); | ||
1183 | unsigned long flags; | ||
1184 | |||
1185 | /* Lock queue and check for queue work */ | ||
1186 | spin_lock_irqsave(&drv_data->lock, flags); | ||
1187 | if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) { | ||
1188 | drv_data->busy = 0; | ||
1189 | spin_unlock_irqrestore(&drv_data->lock, flags); | ||
1190 | return; | ||
1191 | } | ||
1192 | |||
1193 | /* Make sure we are not already running a message */ | ||
1194 | if (drv_data->cur_msg) { | ||
1195 | spin_unlock_irqrestore(&drv_data->lock, flags); | ||
1196 | return; | ||
1197 | } | ||
1198 | |||
1199 | /* Extract head of queue */ | ||
1200 | drv_data->cur_msg = list_entry(drv_data->queue.next, | ||
1201 | struct spi_message, queue); | ||
1202 | list_del_init(&drv_data->cur_msg->queue); | ||
1203 | 784 | ||
785 | drv_data->cur_msg = msg; | ||
1204 | /* Initial message state*/ | 786 | /* Initial message state*/ |
1205 | drv_data->cur_msg->state = START_STATE; | 787 | drv_data->cur_msg->state = START_STATE; |
1206 | drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, | 788 | drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, |
@@ -1213,34 +795,27 @@ static void pump_messages(struct work_struct *work) | |||
1213 | 795 | ||
1214 | /* Mark as busy and launch transfers */ | 796 | /* Mark as busy and launch transfers */ |
1215 | tasklet_schedule(&drv_data->pump_transfers); | 797 | tasklet_schedule(&drv_data->pump_transfers); |
1216 | 798 | return 0; | |
1217 | drv_data->busy = 1; | ||
1218 | spin_unlock_irqrestore(&drv_data->lock, flags); | ||
1219 | } | 799 | } |
1220 | 800 | ||
1221 | static int transfer(struct spi_device *spi, struct spi_message *msg) | 801 | static int pxa2xx_spi_prepare_transfer(struct spi_master *master) |
1222 | { | 802 | { |
1223 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); | 803 | struct driver_data *drv_data = spi_master_get_devdata(master); |
1224 | unsigned long flags; | ||
1225 | |||
1226 | spin_lock_irqsave(&drv_data->lock, flags); | ||
1227 | |||
1228 | if (drv_data->run == QUEUE_STOPPED) { | ||
1229 | spin_unlock_irqrestore(&drv_data->lock, flags); | ||
1230 | return -ESHUTDOWN; | ||
1231 | } | ||
1232 | |||
1233 | msg->actual_length = 0; | ||
1234 | msg->status = -EINPROGRESS; | ||
1235 | msg->state = START_STATE; | ||
1236 | 804 | ||
1237 | list_add_tail(&msg->queue, &drv_data->queue); | 805 | pm_runtime_get_sync(&drv_data->pdev->dev); |
806 | return 0; | ||
807 | } | ||
1238 | 808 | ||
1239 | if (drv_data->run == QUEUE_RUNNING && !drv_data->busy) | 809 | static int pxa2xx_spi_unprepare_transfer(struct spi_master *master) |
1240 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | 810 | { |
811 | struct driver_data *drv_data = spi_master_get_devdata(master); | ||
1241 | 812 | ||
1242 | spin_unlock_irqrestore(&drv_data->lock, flags); | 813 | /* Disable the SSP now */ |
814 | write_SSCR0(read_SSCR0(drv_data->ioaddr) & ~SSCR0_SSE, | ||
815 | drv_data->ioaddr); | ||
1243 | 816 | ||
817 | pm_runtime_mark_last_busy(&drv_data->pdev->dev); | ||
818 | pm_runtime_put_autosuspend(&drv_data->pdev->dev); | ||
1244 | return 0; | 819 | return 0; |
1245 | } | 820 | } |
1246 | 821 | ||
@@ -1287,10 +862,18 @@ static int setup(struct spi_device *spi) | |||
1287 | struct pxa2xx_spi_chip *chip_info = NULL; | 862 | struct pxa2xx_spi_chip *chip_info = NULL; |
1288 | struct chip_data *chip; | 863 | struct chip_data *chip; |
1289 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); | 864 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); |
1290 | struct ssp_device *ssp = drv_data->ssp; | ||
1291 | unsigned int clk_div; | 865 | unsigned int clk_div; |
1292 | uint tx_thres = TX_THRESH_DFLT; | 866 | uint tx_thres, tx_hi_thres, rx_thres; |
1293 | uint rx_thres = RX_THRESH_DFLT; | 867 | |
868 | if (is_lpss_ssp(drv_data)) { | ||
869 | tx_thres = LPSS_TX_LOTHRESH_DFLT; | ||
870 | tx_hi_thres = LPSS_TX_HITHRESH_DFLT; | ||
871 | rx_thres = LPSS_RX_THRESH_DFLT; | ||
872 | } else { | ||
873 | tx_thres = TX_THRESH_DFLT; | ||
874 | tx_hi_thres = 0; | ||
875 | rx_thres = RX_THRESH_DFLT; | ||
876 | } | ||
1294 | 877 | ||
1295 | if (!pxa25x_ssp_comp(drv_data) | 878 | if (!pxa25x_ssp_comp(drv_data) |
1296 | && (spi->bits_per_word < 4 || spi->bits_per_word > 32)) { | 879 | && (spi->bits_per_word < 4 || spi->bits_per_word > 32)) { |
@@ -1330,8 +913,6 @@ static int setup(struct spi_device *spi) | |||
1330 | chip->gpio_cs = -1; | 913 | chip->gpio_cs = -1; |
1331 | chip->enable_dma = 0; | 914 | chip->enable_dma = 0; |
1332 | chip->timeout = TIMOUT_DFLT; | 915 | chip->timeout = TIMOUT_DFLT; |
1333 | chip->dma_burst_size = drv_data->master_info->enable_dma ? | ||
1334 | DCMD_BURST8 : 0; | ||
1335 | } | 916 | } |
1336 | 917 | ||
1337 | /* protocol drivers may change the chip settings, so... | 918 | /* protocol drivers may change the chip settings, so... |
@@ -1345,23 +926,37 @@ static int setup(struct spi_device *spi) | |||
1345 | chip->timeout = chip_info->timeout; | 926 | chip->timeout = chip_info->timeout; |
1346 | if (chip_info->tx_threshold) | 927 | if (chip_info->tx_threshold) |
1347 | tx_thres = chip_info->tx_threshold; | 928 | tx_thres = chip_info->tx_threshold; |
929 | if (chip_info->tx_hi_threshold) | ||
930 | tx_hi_thres = chip_info->tx_hi_threshold; | ||
1348 | if (chip_info->rx_threshold) | 931 | if (chip_info->rx_threshold) |
1349 | rx_thres = chip_info->rx_threshold; | 932 | rx_thres = chip_info->rx_threshold; |
1350 | chip->enable_dma = drv_data->master_info->enable_dma; | 933 | chip->enable_dma = drv_data->master_info->enable_dma; |
1351 | chip->dma_threshold = 0; | 934 | chip->dma_threshold = 0; |
1352 | if (chip_info->enable_loopback) | 935 | if (chip_info->enable_loopback) |
1353 | chip->cr1 = SSCR1_LBM; | 936 | chip->cr1 = SSCR1_LBM; |
937 | } else if (ACPI_HANDLE(&spi->dev)) { | ||
938 | /* | ||
939 | * Slave devices enumerated from ACPI namespace don't | ||
940 | * usually have chip_info but we still might want to use | ||
941 | * DMA with them. | ||
942 | */ | ||
943 | chip->enable_dma = drv_data->master_info->enable_dma; | ||
1354 | } | 944 | } |
1355 | 945 | ||
1356 | chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) | | 946 | chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) | |
1357 | (SSCR1_TxTresh(tx_thres) & SSCR1_TFT); | 947 | (SSCR1_TxTresh(tx_thres) & SSCR1_TFT); |
1358 | 948 | ||
949 | chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres); | ||
950 | chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres) | ||
951 | | SSITF_TxHiThresh(tx_hi_thres); | ||
952 | |||
1359 | /* set dma burst and threshold outside of chip_info path so that if | 953 | /* set dma burst and threshold outside of chip_info path so that if |
1360 | * chip_info goes away after setting chip->enable_dma, the | 954 | * chip_info goes away after setting chip->enable_dma, the |
1361 | * burst and threshold can still respond to changes in bits_per_word */ | 955 | * burst and threshold can still respond to changes in bits_per_word */ |
1362 | if (chip->enable_dma) { | 956 | if (chip->enable_dma) { |
1363 | /* set up legal burst and threshold for dma */ | 957 | /* set up legal burst and threshold for dma */ |
1364 | if (set_dma_burst_and_threshold(chip, spi, spi->bits_per_word, | 958 | if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi, |
959 | spi->bits_per_word, | ||
1365 | &chip->dma_burst_size, | 960 | &chip->dma_burst_size, |
1366 | &chip->dma_threshold)) { | 961 | &chip->dma_threshold)) { |
1367 | dev_warn(&spi->dev, "in setup: DMA burst size reduced " | 962 | dev_warn(&spi->dev, "in setup: DMA burst size reduced " |
@@ -1369,7 +964,7 @@ static int setup(struct spi_device *spi) | |||
1369 | } | 964 | } |
1370 | } | 965 | } |
1371 | 966 | ||
1372 | clk_div = ssp_get_clk_div(ssp, spi->max_speed_hz); | 967 | clk_div = ssp_get_clk_div(drv_data, spi->max_speed_hz); |
1373 | chip->speed_hz = spi->max_speed_hz; | 968 | chip->speed_hz = spi->max_speed_hz; |
1374 | 969 | ||
1375 | chip->cr0 = clk_div | 970 | chip->cr0 = clk_div |
@@ -1382,32 +977,32 @@ static int setup(struct spi_device *spi) | |||
1382 | chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0) | 977 | chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0) |
1383 | | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0); | 978 | | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0); |
1384 | 979 | ||
980 | if (spi->mode & SPI_LOOP) | ||
981 | chip->cr1 |= SSCR1_LBM; | ||
982 | |||
1385 | /* NOTE: PXA25x_SSP _could_ use external clocking ... */ | 983 | /* NOTE: PXA25x_SSP _could_ use external clocking ... */ |
1386 | if (!pxa25x_ssp_comp(drv_data)) | 984 | if (!pxa25x_ssp_comp(drv_data)) |
1387 | dev_dbg(&spi->dev, "%ld Hz actual, %s\n", | 985 | dev_dbg(&spi->dev, "%ld Hz actual, %s\n", |
1388 | clk_get_rate(ssp->clk) | 986 | drv_data->max_clk_rate |
1389 | / (1 + ((chip->cr0 & SSCR0_SCR(0xfff)) >> 8)), | 987 | / (1 + ((chip->cr0 & SSCR0_SCR(0xfff)) >> 8)), |
1390 | chip->enable_dma ? "DMA" : "PIO"); | 988 | chip->enable_dma ? "DMA" : "PIO"); |
1391 | else | 989 | else |
1392 | dev_dbg(&spi->dev, "%ld Hz actual, %s\n", | 990 | dev_dbg(&spi->dev, "%ld Hz actual, %s\n", |
1393 | clk_get_rate(ssp->clk) / 2 | 991 | drv_data->max_clk_rate / 2 |
1394 | / (1 + ((chip->cr0 & SSCR0_SCR(0x0ff)) >> 8)), | 992 | / (1 + ((chip->cr0 & SSCR0_SCR(0x0ff)) >> 8)), |
1395 | chip->enable_dma ? "DMA" : "PIO"); | 993 | chip->enable_dma ? "DMA" : "PIO"); |
1396 | 994 | ||
1397 | if (spi->bits_per_word <= 8) { | 995 | if (spi->bits_per_word <= 8) { |
1398 | chip->n_bytes = 1; | 996 | chip->n_bytes = 1; |
1399 | chip->dma_width = DCMD_WIDTH1; | ||
1400 | chip->read = u8_reader; | 997 | chip->read = u8_reader; |
1401 | chip->write = u8_writer; | 998 | chip->write = u8_writer; |
1402 | } else if (spi->bits_per_word <= 16) { | 999 | } else if (spi->bits_per_word <= 16) { |
1403 | chip->n_bytes = 2; | 1000 | chip->n_bytes = 2; |
1404 | chip->dma_width = DCMD_WIDTH2; | ||
1405 | chip->read = u16_reader; | 1001 | chip->read = u16_reader; |
1406 | chip->write = u16_writer; | 1002 | chip->write = u16_writer; |
1407 | } else if (spi->bits_per_word <= 32) { | 1003 | } else if (spi->bits_per_word <= 32) { |
1408 | chip->cr0 |= SSCR0_EDSS; | 1004 | chip->cr0 |= SSCR0_EDSS; |
1409 | chip->n_bytes = 4; | 1005 | chip->n_bytes = 4; |
1410 | chip->dma_width = DCMD_WIDTH4; | ||
1411 | chip->read = u32_reader; | 1006 | chip->read = u32_reader; |
1412 | chip->write = u32_writer; | 1007 | chip->write = u32_writer; |
1413 | } else { | 1008 | } else { |
@@ -1438,93 +1033,98 @@ static void cleanup(struct spi_device *spi) | |||
1438 | kfree(chip); | 1033 | kfree(chip); |
1439 | } | 1034 | } |
1440 | 1035 | ||
1441 | static int init_queue(struct driver_data *drv_data) | 1036 | #ifdef CONFIG_ACPI |
1037 | static int pxa2xx_spi_acpi_add_dma(struct acpi_resource *res, void *data) | ||
1442 | { | 1038 | { |
1443 | INIT_LIST_HEAD(&drv_data->queue); | 1039 | struct pxa2xx_spi_master *pdata = data; |
1444 | spin_lock_init(&drv_data->lock); | 1040 | |
1445 | 1041 | if (res->type == ACPI_RESOURCE_TYPE_FIXED_DMA) { | |
1446 | drv_data->run = QUEUE_STOPPED; | 1042 | const struct acpi_resource_fixed_dma *dma; |
1447 | drv_data->busy = 0; | 1043 | |
1448 | 1044 | dma = &res->data.fixed_dma; | |
1449 | tasklet_init(&drv_data->pump_transfers, | 1045 | if (pdata->tx_slave_id < 0) { |
1450 | pump_transfers, (unsigned long)drv_data); | 1046 | pdata->tx_slave_id = dma->request_lines; |
1451 | 1047 | pdata->tx_chan_id = dma->channels; | |
1452 | INIT_WORK(&drv_data->pump_messages, pump_messages); | 1048 | } else if (pdata->rx_slave_id < 0) { |
1453 | drv_data->workqueue = create_singlethread_workqueue( | 1049 | pdata->rx_slave_id = dma->request_lines; |
1454 | dev_name(drv_data->master->dev.parent)); | 1050 | pdata->rx_chan_id = dma->channels; |
1455 | if (drv_data->workqueue == NULL) | 1051 | } |
1456 | return -EBUSY; | 1052 | } |
1457 | 1053 | ||
1458 | return 0; | 1054 | /* Tell the ACPI core to skip this resource */ |
1055 | return 1; | ||
1459 | } | 1056 | } |
1460 | 1057 | ||
1461 | static int start_queue(struct driver_data *drv_data) | 1058 | static struct pxa2xx_spi_master * |
1059 | pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev) | ||
1462 | { | 1060 | { |
1463 | unsigned long flags; | 1061 | struct pxa2xx_spi_master *pdata; |
1464 | 1062 | struct list_head resource_list; | |
1465 | spin_lock_irqsave(&drv_data->lock, flags); | 1063 | struct acpi_device *adev; |
1466 | 1064 | struct ssp_device *ssp; | |
1467 | if (drv_data->run == QUEUE_RUNNING || drv_data->busy) { | 1065 | struct resource *res; |
1468 | spin_unlock_irqrestore(&drv_data->lock, flags); | 1066 | int devid; |
1469 | return -EBUSY; | 1067 | |
1068 | if (!ACPI_HANDLE(&pdev->dev) || | ||
1069 | acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev)) | ||
1070 | return NULL; | ||
1071 | |||
1072 | pdata = devm_kzalloc(&pdev->dev, sizeof(*ssp), GFP_KERNEL); | ||
1073 | if (!pdata) { | ||
1074 | dev_err(&pdev->dev, | ||
1075 | "failed to allocate memory for platform data\n"); | ||
1076 | return NULL; | ||
1470 | } | 1077 | } |
1471 | 1078 | ||
1472 | drv_data->run = QUEUE_RUNNING; | 1079 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1473 | drv_data->cur_msg = NULL; | 1080 | if (!res) |
1474 | drv_data->cur_transfer = NULL; | 1081 | return NULL; |
1475 | drv_data->cur_chip = NULL; | ||
1476 | spin_unlock_irqrestore(&drv_data->lock, flags); | ||
1477 | |||
1478 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | ||
1479 | 1082 | ||
1480 | return 0; | 1083 | ssp = &pdata->ssp; |
1481 | } | ||
1482 | 1084 | ||
1483 | static int stop_queue(struct driver_data *drv_data) | 1085 | ssp->phys_base = res->start; |
1484 | { | 1086 | ssp->mmio_base = devm_request_and_ioremap(&pdev->dev, res); |
1485 | unsigned long flags; | 1087 | if (!ssp->mmio_base) { |
1486 | unsigned limit = 500; | 1088 | dev_err(&pdev->dev, "failed to ioremap mmio_base\n"); |
1487 | int status = 0; | 1089 | return NULL; |
1488 | |||
1489 | spin_lock_irqsave(&drv_data->lock, flags); | ||
1490 | |||
1491 | /* This is a bit lame, but is optimized for the common execution path. | ||
1492 | * A wait_queue on the drv_data->busy could be used, but then the common | ||
1493 | * execution path (pump_messages) would be required to call wake_up or | ||
1494 | * friends on every SPI message. Do this instead */ | ||
1495 | drv_data->run = QUEUE_STOPPED; | ||
1496 | while ((!list_empty(&drv_data->queue) || drv_data->busy) && limit--) { | ||
1497 | spin_unlock_irqrestore(&drv_data->lock, flags); | ||
1498 | msleep(10); | ||
1499 | spin_lock_irqsave(&drv_data->lock, flags); | ||
1500 | } | 1090 | } |
1501 | 1091 | ||
1502 | if (!list_empty(&drv_data->queue) || drv_data->busy) | 1092 | ssp->clk = devm_clk_get(&pdev->dev, NULL); |
1503 | status = -EBUSY; | 1093 | ssp->irq = platform_get_irq(pdev, 0); |
1094 | ssp->type = LPSS_SSP; | ||
1095 | ssp->pdev = pdev; | ||
1504 | 1096 | ||
1505 | spin_unlock_irqrestore(&drv_data->lock, flags); | 1097 | ssp->port_id = -1; |
1098 | if (adev->pnp.unique_id && !kstrtoint(adev->pnp.unique_id, 0, &devid)) | ||
1099 | ssp->port_id = devid; | ||
1506 | 1100 | ||
1507 | return status; | 1101 | pdata->num_chipselect = 1; |
1508 | } | 1102 | pdata->rx_slave_id = -1; |
1103 | pdata->tx_slave_id = -1; | ||
1509 | 1104 | ||
1510 | static int destroy_queue(struct driver_data *drv_data) | 1105 | INIT_LIST_HEAD(&resource_list); |
1511 | { | 1106 | acpi_dev_get_resources(adev, &resource_list, pxa2xx_spi_acpi_add_dma, |
1512 | int status; | 1107 | pdata); |
1108 | acpi_dev_free_resource_list(&resource_list); | ||
1513 | 1109 | ||
1514 | status = stop_queue(drv_data); | 1110 | pdata->enable_dma = pdata->rx_slave_id >= 0 && pdata->tx_slave_id >= 0; |
1515 | /* we are unloading the module or failing to load (only two calls | ||
1516 | * to this routine), and neither call can handle a return value. | ||
1517 | * However, destroy_workqueue calls flush_workqueue, and that will | ||
1518 | * block until all work is done. If the reason that stop_queue | ||
1519 | * timed out is that the work will never finish, then it does no | ||
1520 | * good to call destroy_workqueue, so return anyway. */ | ||
1521 | if (status != 0) | ||
1522 | return status; | ||
1523 | 1111 | ||
1524 | destroy_workqueue(drv_data->workqueue); | 1112 | return pdata; |
1113 | } | ||
1525 | 1114 | ||
1526 | return 0; | 1115 | static struct acpi_device_id pxa2xx_spi_acpi_match[] = { |
1116 | { "INT33C0", 0 }, | ||
1117 | { "INT33C1", 0 }, | ||
1118 | { }, | ||
1119 | }; | ||
1120 | MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match); | ||
1121 | #else | ||
1122 | static inline struct pxa2xx_spi_master * | ||
1123 | pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev) | ||
1124 | { | ||
1125 | return NULL; | ||
1527 | } | 1126 | } |
1127 | #endif | ||
1528 | 1128 | ||
1529 | static int pxa2xx_spi_probe(struct platform_device *pdev) | 1129 | static int pxa2xx_spi_probe(struct platform_device *pdev) |
1530 | { | 1130 | { |
@@ -1535,11 +1135,21 @@ static int pxa2xx_spi_probe(struct platform_device *pdev) | |||
1535 | struct ssp_device *ssp; | 1135 | struct ssp_device *ssp; |
1536 | int status; | 1136 | int status; |
1537 | 1137 | ||
1538 | platform_info = dev->platform_data; | 1138 | platform_info = dev_get_platdata(dev); |
1139 | if (!platform_info) { | ||
1140 | platform_info = pxa2xx_spi_acpi_get_pdata(pdev); | ||
1141 | if (!platform_info) { | ||
1142 | dev_err(&pdev->dev, "missing platform data\n"); | ||
1143 | return -ENODEV; | ||
1144 | } | ||
1145 | } | ||
1539 | 1146 | ||
1540 | ssp = pxa_ssp_request(pdev->id, pdev->name); | 1147 | ssp = pxa_ssp_request(pdev->id, pdev->name); |
1541 | if (ssp == NULL) { | 1148 | if (!ssp) |
1542 | dev_err(&pdev->dev, "failed to request SSP%d\n", pdev->id); | 1149 | ssp = &platform_info->ssp; |
1150 | |||
1151 | if (!ssp->mmio_base) { | ||
1152 | dev_err(&pdev->dev, "failed to get ssp\n"); | ||
1543 | return -ENODEV; | 1153 | return -ENODEV; |
1544 | } | 1154 | } |
1545 | 1155 | ||
@@ -1558,19 +1168,21 @@ static int pxa2xx_spi_probe(struct platform_device *pdev) | |||
1558 | 1168 | ||
1559 | master->dev.parent = &pdev->dev; | 1169 | master->dev.parent = &pdev->dev; |
1560 | master->dev.of_node = pdev->dev.of_node; | 1170 | master->dev.of_node = pdev->dev.of_node; |
1171 | ACPI_HANDLE_SET(&master->dev, ACPI_HANDLE(&pdev->dev)); | ||
1561 | /* the spi->mode bits understood by this driver: */ | 1172 | /* the spi->mode bits understood by this driver: */ |
1562 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; | 1173 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; |
1563 | 1174 | ||
1564 | master->bus_num = pdev->id; | 1175 | master->bus_num = ssp->port_id; |
1565 | master->num_chipselect = platform_info->num_chipselect; | 1176 | master->num_chipselect = platform_info->num_chipselect; |
1566 | master->dma_alignment = DMA_ALIGNMENT; | 1177 | master->dma_alignment = DMA_ALIGNMENT; |
1567 | master->cleanup = cleanup; | 1178 | master->cleanup = cleanup; |
1568 | master->setup = setup; | 1179 | master->setup = setup; |
1569 | master->transfer = transfer; | 1180 | master->transfer_one_message = pxa2xx_spi_transfer_one_message; |
1181 | master->prepare_transfer_hardware = pxa2xx_spi_prepare_transfer; | ||
1182 | master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer; | ||
1570 | 1183 | ||
1571 | drv_data->ssp_type = ssp->type; | 1184 | drv_data->ssp_type = ssp->type; |
1572 | drv_data->null_dma_buf = (u32 *)ALIGN((u32)(drv_data + | 1185 | drv_data->null_dma_buf = (u32 *)PTR_ALIGN(&drv_data[1], DMA_ALIGNMENT); |
1573 | sizeof(struct driver_data)), 8); | ||
1574 | 1186 | ||
1575 | drv_data->ioaddr = ssp->mmio_base; | 1187 | drv_data->ioaddr = ssp->mmio_base; |
1576 | drv_data->ssdr_physical = ssp->phys_base + SSDR; | 1188 | drv_data->ssdr_physical = ssp->phys_base + SSDR; |
@@ -1581,7 +1193,7 @@ static int pxa2xx_spi_probe(struct platform_device *pdev) | |||
1581 | drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR; | 1193 | drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR; |
1582 | } else { | 1194 | } else { |
1583 | drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; | 1195 | drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; |
1584 | drv_data->dma_cr1 = SSCR1_TSRE | SSCR1_RSRE | SSCR1_TINTE; | 1196 | drv_data->dma_cr1 = DEFAULT_DMA_CR1; |
1585 | drv_data->clear_sr = SSSR_ROR | SSSR_TINT; | 1197 | drv_data->clear_sr = SSSR_ROR | SSSR_TINT; |
1586 | drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR; | 1198 | drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR; |
1587 | } | 1199 | } |
@@ -1597,35 +1209,17 @@ static int pxa2xx_spi_probe(struct platform_device *pdev) | |||
1597 | drv_data->tx_channel = -1; | 1209 | drv_data->tx_channel = -1; |
1598 | drv_data->rx_channel = -1; | 1210 | drv_data->rx_channel = -1; |
1599 | if (platform_info->enable_dma) { | 1211 | if (platform_info->enable_dma) { |
1600 | 1212 | status = pxa2xx_spi_dma_setup(drv_data); | |
1601 | /* Get two DMA channels (rx and tx) */ | 1213 | if (status) { |
1602 | drv_data->rx_channel = pxa_request_dma("pxa2xx_spi_ssp_rx", | 1214 | dev_warn(dev, "failed to setup DMA, using PIO\n"); |
1603 | DMA_PRIO_HIGH, | 1215 | platform_info->enable_dma = false; |
1604 | dma_handler, | ||
1605 | drv_data); | ||
1606 | if (drv_data->rx_channel < 0) { | ||
1607 | dev_err(dev, "problem (%d) requesting rx channel\n", | ||
1608 | drv_data->rx_channel); | ||
1609 | status = -ENODEV; | ||
1610 | goto out_error_irq_alloc; | ||
1611 | } | 1216 | } |
1612 | drv_data->tx_channel = pxa_request_dma("pxa2xx_spi_ssp_tx", | ||
1613 | DMA_PRIO_MEDIUM, | ||
1614 | dma_handler, | ||
1615 | drv_data); | ||
1616 | if (drv_data->tx_channel < 0) { | ||
1617 | dev_err(dev, "problem (%d) requesting tx channel\n", | ||
1618 | drv_data->tx_channel); | ||
1619 | status = -ENODEV; | ||
1620 | goto out_error_dma_alloc; | ||
1621 | } | ||
1622 | |||
1623 | DRCMR(ssp->drcmr_rx) = DRCMR_MAPVLD | drv_data->rx_channel; | ||
1624 | DRCMR(ssp->drcmr_tx) = DRCMR_MAPVLD | drv_data->tx_channel; | ||
1625 | } | 1217 | } |
1626 | 1218 | ||
1627 | /* Enable SOC clock */ | 1219 | /* Enable SOC clock */ |
1628 | clk_enable(ssp->clk); | 1220 | clk_prepare_enable(ssp->clk); |
1221 | |||
1222 | drv_data->max_clk_rate = clk_get_rate(ssp->clk); | ||
1629 | 1223 | ||
1630 | /* Load default SSP configuration */ | 1224 | /* Load default SSP configuration */ |
1631 | write_SSCR0(0, drv_data->ioaddr); | 1225 | write_SSCR0(0, drv_data->ioaddr); |
@@ -1640,41 +1234,29 @@ static int pxa2xx_spi_probe(struct platform_device *pdev) | |||
1640 | write_SSTO(0, drv_data->ioaddr); | 1234 | write_SSTO(0, drv_data->ioaddr); |
1641 | write_SSPSP(0, drv_data->ioaddr); | 1235 | write_SSPSP(0, drv_data->ioaddr); |
1642 | 1236 | ||
1643 | /* Initial and start queue */ | 1237 | lpss_ssp_setup(drv_data); |
1644 | status = init_queue(drv_data); | 1238 | |
1645 | if (status != 0) { | 1239 | tasklet_init(&drv_data->pump_transfers, pump_transfers, |
1646 | dev_err(&pdev->dev, "problem initializing queue\n"); | 1240 | (unsigned long)drv_data); |
1647 | goto out_error_clock_enabled; | ||
1648 | } | ||
1649 | status = start_queue(drv_data); | ||
1650 | if (status != 0) { | ||
1651 | dev_err(&pdev->dev, "problem starting queue\n"); | ||
1652 | goto out_error_clock_enabled; | ||
1653 | } | ||
1654 | 1241 | ||
1655 | /* Register with the SPI framework */ | 1242 | /* Register with the SPI framework */ |
1656 | platform_set_drvdata(pdev, drv_data); | 1243 | platform_set_drvdata(pdev, drv_data); |
1657 | status = spi_register_master(master); | 1244 | status = spi_register_master(master); |
1658 | if (status != 0) { | 1245 | if (status != 0) { |
1659 | dev_err(&pdev->dev, "problem registering spi master\n"); | 1246 | dev_err(&pdev->dev, "problem registering spi master\n"); |
1660 | goto out_error_queue_alloc; | 1247 | goto out_error_clock_enabled; |
1661 | } | 1248 | } |
1662 | 1249 | ||
1663 | return status; | 1250 | pm_runtime_set_autosuspend_delay(&pdev->dev, 50); |
1251 | pm_runtime_use_autosuspend(&pdev->dev); | ||
1252 | pm_runtime_set_active(&pdev->dev); | ||
1253 | pm_runtime_enable(&pdev->dev); | ||
1664 | 1254 | ||
1665 | out_error_queue_alloc: | 1255 | return status; |
1666 | destroy_queue(drv_data); | ||
1667 | 1256 | ||
1668 | out_error_clock_enabled: | 1257 | out_error_clock_enabled: |
1669 | clk_disable(ssp->clk); | 1258 | clk_disable_unprepare(ssp->clk); |
1670 | 1259 | pxa2xx_spi_dma_release(drv_data); | |
1671 | out_error_dma_alloc: | ||
1672 | if (drv_data->tx_channel != -1) | ||
1673 | pxa_free_dma(drv_data->tx_channel); | ||
1674 | if (drv_data->rx_channel != -1) | ||
1675 | pxa_free_dma(drv_data->rx_channel); | ||
1676 | |||
1677 | out_error_irq_alloc: | ||
1678 | free_irq(ssp->irq, drv_data); | 1260 | free_irq(ssp->irq, drv_data); |
1679 | 1261 | ||
1680 | out_error_master_alloc: | 1262 | out_error_master_alloc: |
@@ -1687,37 +1269,23 @@ static int pxa2xx_spi_remove(struct platform_device *pdev) | |||
1687 | { | 1269 | { |
1688 | struct driver_data *drv_data = platform_get_drvdata(pdev); | 1270 | struct driver_data *drv_data = platform_get_drvdata(pdev); |
1689 | struct ssp_device *ssp; | 1271 | struct ssp_device *ssp; |
1690 | int status = 0; | ||
1691 | 1272 | ||
1692 | if (!drv_data) | 1273 | if (!drv_data) |
1693 | return 0; | 1274 | return 0; |
1694 | ssp = drv_data->ssp; | 1275 | ssp = drv_data->ssp; |
1695 | 1276 | ||
1696 | /* Remove the queue */ | 1277 | pm_runtime_get_sync(&pdev->dev); |
1697 | status = destroy_queue(drv_data); | ||
1698 | if (status != 0) | ||
1699 | /* the kernel does not check the return status of this | ||
1700 | * this routine (mod->exit, within the kernel). Therefore | ||
1701 | * nothing is gained by returning from here, the module is | ||
1702 | * going away regardless, and we should not leave any more | ||
1703 | * resources allocated than necessary. We cannot free the | ||
1704 | * message memory in drv_data->queue, but we can release the | ||
1705 | * resources below. I think the kernel should honor -EBUSY | ||
1706 | * returns but... */ | ||
1707 | dev_err(&pdev->dev, "pxa2xx_spi_remove: workqueue will not " | ||
1708 | "complete, message memory not freed\n"); | ||
1709 | 1278 | ||
1710 | /* Disable the SSP at the peripheral and SOC level */ | 1279 | /* Disable the SSP at the peripheral and SOC level */ |
1711 | write_SSCR0(0, drv_data->ioaddr); | 1280 | write_SSCR0(0, drv_data->ioaddr); |
1712 | clk_disable(ssp->clk); | 1281 | clk_disable_unprepare(ssp->clk); |
1713 | 1282 | ||
1714 | /* Release DMA */ | 1283 | /* Release DMA */ |
1715 | if (drv_data->master_info->enable_dma) { | 1284 | if (drv_data->master_info->enable_dma) |
1716 | DRCMR(ssp->drcmr_rx) = 0; | 1285 | pxa2xx_spi_dma_release(drv_data); |
1717 | DRCMR(ssp->drcmr_tx) = 0; | 1286 | |
1718 | pxa_free_dma(drv_data->tx_channel); | 1287 | pm_runtime_put_noidle(&pdev->dev); |
1719 | pxa_free_dma(drv_data->rx_channel); | 1288 | pm_runtime_disable(&pdev->dev); |
1720 | } | ||
1721 | 1289 | ||
1722 | /* Release IRQ */ | 1290 | /* Release IRQ */ |
1723 | free_irq(ssp->irq, drv_data); | 1291 | free_irq(ssp->irq, drv_data); |
@@ -1749,11 +1317,11 @@ static int pxa2xx_spi_suspend(struct device *dev) | |||
1749 | struct ssp_device *ssp = drv_data->ssp; | 1317 | struct ssp_device *ssp = drv_data->ssp; |
1750 | int status = 0; | 1318 | int status = 0; |
1751 | 1319 | ||
1752 | status = stop_queue(drv_data); | 1320 | status = spi_master_suspend(drv_data->master); |
1753 | if (status != 0) | 1321 | if (status != 0) |
1754 | return status; | 1322 | return status; |
1755 | write_SSCR0(0, drv_data->ioaddr); | 1323 | write_SSCR0(0, drv_data->ioaddr); |
1756 | clk_disable(ssp->clk); | 1324 | clk_disable_unprepare(ssp->clk); |
1757 | 1325 | ||
1758 | return 0; | 1326 | return 0; |
1759 | } | 1327 | } |
@@ -1764,18 +1332,13 @@ static int pxa2xx_spi_resume(struct device *dev) | |||
1764 | struct ssp_device *ssp = drv_data->ssp; | 1332 | struct ssp_device *ssp = drv_data->ssp; |
1765 | int status = 0; | 1333 | int status = 0; |
1766 | 1334 | ||
1767 | if (drv_data->rx_channel != -1) | 1335 | pxa2xx_spi_dma_resume(drv_data); |
1768 | DRCMR(drv_data->ssp->drcmr_rx) = | ||
1769 | DRCMR_MAPVLD | drv_data->rx_channel; | ||
1770 | if (drv_data->tx_channel != -1) | ||
1771 | DRCMR(drv_data->ssp->drcmr_tx) = | ||
1772 | DRCMR_MAPVLD | drv_data->tx_channel; | ||
1773 | 1336 | ||
1774 | /* Enable the SSP clock */ | 1337 | /* Enable the SSP clock */ |
1775 | clk_enable(ssp->clk); | 1338 | clk_prepare_enable(ssp->clk); |
1776 | 1339 | ||
1777 | /* Start the queue running */ | 1340 | /* Start the queue running */ |
1778 | status = start_queue(drv_data); | 1341 | status = spi_master_resume(drv_data->master); |
1779 | if (status != 0) { | 1342 | if (status != 0) { |
1780 | dev_err(dev, "problem starting queue (%d)\n", status); | 1343 | dev_err(dev, "problem starting queue (%d)\n", status); |
1781 | return status; | 1344 | return status; |
@@ -1783,20 +1346,38 @@ static int pxa2xx_spi_resume(struct device *dev) | |||
1783 | 1346 | ||
1784 | return 0; | 1347 | return 0; |
1785 | } | 1348 | } |
1349 | #endif | ||
1350 | |||
1351 | #ifdef CONFIG_PM_RUNTIME | ||
1352 | static int pxa2xx_spi_runtime_suspend(struct device *dev) | ||
1353 | { | ||
1354 | struct driver_data *drv_data = dev_get_drvdata(dev); | ||
1355 | |||
1356 | clk_disable_unprepare(drv_data->ssp->clk); | ||
1357 | return 0; | ||
1358 | } | ||
1359 | |||
1360 | static int pxa2xx_spi_runtime_resume(struct device *dev) | ||
1361 | { | ||
1362 | struct driver_data *drv_data = dev_get_drvdata(dev); | ||
1363 | |||
1364 | clk_prepare_enable(drv_data->ssp->clk); | ||
1365 | return 0; | ||
1366 | } | ||
1367 | #endif | ||
1786 | 1368 | ||
1787 | static const struct dev_pm_ops pxa2xx_spi_pm_ops = { | 1369 | static const struct dev_pm_ops pxa2xx_spi_pm_ops = { |
1788 | .suspend = pxa2xx_spi_suspend, | 1370 | SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume) |
1789 | .resume = pxa2xx_spi_resume, | 1371 | SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend, |
1372 | pxa2xx_spi_runtime_resume, NULL) | ||
1790 | }; | 1373 | }; |
1791 | #endif | ||
1792 | 1374 | ||
1793 | static struct platform_driver driver = { | 1375 | static struct platform_driver driver = { |
1794 | .driver = { | 1376 | .driver = { |
1795 | .name = "pxa2xx-spi", | 1377 | .name = "pxa2xx-spi", |
1796 | .owner = THIS_MODULE, | 1378 | .owner = THIS_MODULE, |
1797 | #ifdef CONFIG_PM | ||
1798 | .pm = &pxa2xx_spi_pm_ops, | 1379 | .pm = &pxa2xx_spi_pm_ops, |
1799 | #endif | 1380 | .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match), |
1800 | }, | 1381 | }, |
1801 | .probe = pxa2xx_spi_probe, | 1382 | .probe = pxa2xx_spi_probe, |
1802 | .remove = pxa2xx_spi_remove, | 1383 | .remove = pxa2xx_spi_remove, |
diff --git a/drivers/spi/spi-pxa2xx.h b/drivers/spi/spi-pxa2xx.h new file mode 100644 index 000000000000..5adc2a11c7bc --- /dev/null +++ b/drivers/spi/spi-pxa2xx.h | |||
@@ -0,0 +1,221 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs | ||
3 | * Copyright (C) 2013, Intel Corporation | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify | ||
6 | * it under the terms of the GNU General Public License version 2 as | ||
7 | * published by the Free Software Foundation. | ||
8 | */ | ||
9 | |||
10 | #ifndef SPI_PXA2XX_H | ||
11 | #define SPI_PXA2XX_H | ||
12 | |||
13 | #include <linux/atomic.h> | ||
14 | #include <linux/dmaengine.h> | ||
15 | #include <linux/errno.h> | ||
16 | #include <linux/io.h> | ||
17 | #include <linux/interrupt.h> | ||
18 | #include <linux/platform_device.h> | ||
19 | #include <linux/pxa2xx_ssp.h> | ||
20 | #include <linux/scatterlist.h> | ||
21 | #include <linux/sizes.h> | ||
22 | #include <linux/spi/spi.h> | ||
23 | #include <linux/spi/pxa2xx_spi.h> | ||
24 | |||
25 | struct driver_data { | ||
26 | /* Driver model hookup */ | ||
27 | struct platform_device *pdev; | ||
28 | |||
29 | /* SSP Info */ | ||
30 | struct ssp_device *ssp; | ||
31 | |||
32 | /* SPI framework hookup */ | ||
33 | enum pxa_ssp_type ssp_type; | ||
34 | struct spi_master *master; | ||
35 | |||
36 | /* PXA hookup */ | ||
37 | struct pxa2xx_spi_master *master_info; | ||
38 | |||
39 | /* PXA private DMA setup stuff */ | ||
40 | int rx_channel; | ||
41 | int tx_channel; | ||
42 | u32 *null_dma_buf; | ||
43 | |||
44 | /* SSP register addresses */ | ||
45 | void __iomem *ioaddr; | ||
46 | u32 ssdr_physical; | ||
47 | |||
48 | /* SSP masks*/ | ||
49 | u32 dma_cr1; | ||
50 | u32 int_cr1; | ||
51 | u32 clear_sr; | ||
52 | u32 mask_sr; | ||
53 | |||
54 | /* Maximun clock rate */ | ||
55 | unsigned long max_clk_rate; | ||
56 | |||
57 | /* Message Transfer pump */ | ||
58 | struct tasklet_struct pump_transfers; | ||
59 | |||
60 | /* DMA engine support */ | ||
61 | struct dma_chan *rx_chan; | ||
62 | struct dma_chan *tx_chan; | ||
63 | struct sg_table rx_sgt; | ||
64 | struct sg_table tx_sgt; | ||
65 | int rx_nents; | ||
66 | int tx_nents; | ||
67 | void *dummy; | ||
68 | atomic_t dma_running; | ||
69 | |||
70 | /* Current message transfer state info */ | ||
71 | struct spi_message *cur_msg; | ||
72 | struct spi_transfer *cur_transfer; | ||
73 | struct chip_data *cur_chip; | ||
74 | size_t len; | ||
75 | void *tx; | ||
76 | void *tx_end; | ||
77 | void *rx; | ||
78 | void *rx_end; | ||
79 | int dma_mapped; | ||
80 | dma_addr_t rx_dma; | ||
81 | dma_addr_t tx_dma; | ||
82 | size_t rx_map_len; | ||
83 | size_t tx_map_len; | ||
84 | u8 n_bytes; | ||
85 | int (*write)(struct driver_data *drv_data); | ||
86 | int (*read)(struct driver_data *drv_data); | ||
87 | irqreturn_t (*transfer_handler)(struct driver_data *drv_data); | ||
88 | void (*cs_control)(u32 command); | ||
89 | |||
90 | void __iomem *lpss_base; | ||
91 | }; | ||
92 | |||
93 | struct chip_data { | ||
94 | u32 cr0; | ||
95 | u32 cr1; | ||
96 | u32 psp; | ||
97 | u32 timeout; | ||
98 | u8 n_bytes; | ||
99 | u32 dma_burst_size; | ||
100 | u32 threshold; | ||
101 | u32 dma_threshold; | ||
102 | u16 lpss_rx_threshold; | ||
103 | u16 lpss_tx_threshold; | ||
104 | u8 enable_dma; | ||
105 | u8 bits_per_word; | ||
106 | u32 speed_hz; | ||
107 | union { | ||
108 | int gpio_cs; | ||
109 | unsigned int frm; | ||
110 | }; | ||
111 | int gpio_cs_inverted; | ||
112 | int (*write)(struct driver_data *drv_data); | ||
113 | int (*read)(struct driver_data *drv_data); | ||
114 | void (*cs_control)(u32 command); | ||
115 | }; | ||
116 | |||
117 | #define DEFINE_SSP_REG(reg, off) \ | ||
118 | static inline u32 read_##reg(void const __iomem *p) \ | ||
119 | { return __raw_readl(p + (off)); } \ | ||
120 | \ | ||
121 | static inline void write_##reg(u32 v, void __iomem *p) \ | ||
122 | { __raw_writel(v, p + (off)); } | ||
123 | |||
124 | DEFINE_SSP_REG(SSCR0, 0x00) | ||
125 | DEFINE_SSP_REG(SSCR1, 0x04) | ||
126 | DEFINE_SSP_REG(SSSR, 0x08) | ||
127 | DEFINE_SSP_REG(SSITR, 0x0c) | ||
128 | DEFINE_SSP_REG(SSDR, 0x10) | ||
129 | DEFINE_SSP_REG(SSTO, 0x28) | ||
130 | DEFINE_SSP_REG(SSPSP, 0x2c) | ||
131 | DEFINE_SSP_REG(SSITF, SSITF) | ||
132 | DEFINE_SSP_REG(SSIRF, SSIRF) | ||
133 | |||
134 | #define START_STATE ((void *)0) | ||
135 | #define RUNNING_STATE ((void *)1) | ||
136 | #define DONE_STATE ((void *)2) | ||
137 | #define ERROR_STATE ((void *)-1) | ||
138 | |||
139 | #define IS_DMA_ALIGNED(x) IS_ALIGNED((unsigned long)(x), DMA_ALIGNMENT) | ||
140 | #define DMA_ALIGNMENT 8 | ||
141 | |||
142 | static inline int pxa25x_ssp_comp(struct driver_data *drv_data) | ||
143 | { | ||
144 | if (drv_data->ssp_type == PXA25x_SSP) | ||
145 | return 1; | ||
146 | if (drv_data->ssp_type == CE4100_SSP) | ||
147 | return 1; | ||
148 | return 0; | ||
149 | } | ||
150 | |||
151 | static inline void write_SSSR_CS(struct driver_data *drv_data, u32 val) | ||
152 | { | ||
153 | void __iomem *reg = drv_data->ioaddr; | ||
154 | |||
155 | if (drv_data->ssp_type == CE4100_SSP) | ||
156 | val |= read_SSSR(reg) & SSSR_ALT_FRM_MASK; | ||
157 | |||
158 | write_SSSR(val, reg); | ||
159 | } | ||
160 | |||
161 | extern int pxa2xx_spi_flush(struct driver_data *drv_data); | ||
162 | extern void *pxa2xx_spi_next_transfer(struct driver_data *drv_data); | ||
163 | |||
164 | /* | ||
165 | * Select the right DMA implementation. | ||
166 | */ | ||
167 | #if defined(CONFIG_SPI_PXA2XX_PXADMA) | ||
168 | #define SPI_PXA2XX_USE_DMA 1 | ||
169 | #define MAX_DMA_LEN 8191 | ||
170 | #define DEFAULT_DMA_CR1 (SSCR1_TSRE | SSCR1_RSRE | SSCR1_TINTE) | ||
171 | #elif defined(CONFIG_SPI_PXA2XX_DMA) | ||
172 | #define SPI_PXA2XX_USE_DMA 1 | ||
173 | #define MAX_DMA_LEN SZ_64K | ||
174 | #define DEFAULT_DMA_CR1 (SSCR1_TSRE | SSCR1_RSRE | SSCR1_TRAIL) | ||
175 | #else | ||
176 | #undef SPI_PXA2XX_USE_DMA | ||
177 | #define MAX_DMA_LEN 0 | ||
178 | #define DEFAULT_DMA_CR1 0 | ||
179 | #endif | ||
180 | |||
181 | #ifdef SPI_PXA2XX_USE_DMA | ||
182 | extern bool pxa2xx_spi_dma_is_possible(size_t len); | ||
183 | extern int pxa2xx_spi_map_dma_buffers(struct driver_data *drv_data); | ||
184 | extern irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data); | ||
185 | extern int pxa2xx_spi_dma_prepare(struct driver_data *drv_data, u32 dma_burst); | ||
186 | extern void pxa2xx_spi_dma_start(struct driver_data *drv_data); | ||
187 | extern int pxa2xx_spi_dma_setup(struct driver_data *drv_data); | ||
188 | extern void pxa2xx_spi_dma_release(struct driver_data *drv_data); | ||
189 | extern void pxa2xx_spi_dma_resume(struct driver_data *drv_data); | ||
190 | extern int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip, | ||
191 | struct spi_device *spi, | ||
192 | u8 bits_per_word, | ||
193 | u32 *burst_code, | ||
194 | u32 *threshold); | ||
195 | #else | ||
196 | static inline bool pxa2xx_spi_dma_is_possible(size_t len) { return false; } | ||
197 | static inline int pxa2xx_spi_map_dma_buffers(struct driver_data *drv_data) | ||
198 | { | ||
199 | return 0; | ||
200 | } | ||
201 | #define pxa2xx_spi_dma_transfer NULL | ||
202 | static inline void pxa2xx_spi_dma_prepare(struct driver_data *drv_data, | ||
203 | u32 dma_burst) {} | ||
204 | static inline void pxa2xx_spi_dma_start(struct driver_data *drv_data) {} | ||
205 | static inline int pxa2xx_spi_dma_setup(struct driver_data *drv_data) | ||
206 | { | ||
207 | return 0; | ||
208 | } | ||
209 | static inline void pxa2xx_spi_dma_release(struct driver_data *drv_data) {} | ||
210 | static inline void pxa2xx_spi_dma_resume(struct driver_data *drv_data) {} | ||
211 | static inline int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip, | ||
212 | struct spi_device *spi, | ||
213 | u8 bits_per_word, | ||
214 | u32 *burst_code, | ||
215 | u32 *threshold) | ||
216 | { | ||
217 | return -ENODEV; | ||
218 | } | ||
219 | #endif | ||
220 | |||
221 | #endif /* SPI_PXA2XX_H */ | ||
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 51a8c4216ebb..7cfbe9d3381f 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c | |||
@@ -62,7 +62,7 @@ | |||
62 | #define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9) | 62 | #define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9) |
63 | #define S3C64XX_SPI_CLKSEL_SRCSHFT 9 | 63 | #define S3C64XX_SPI_CLKSEL_SRCSHFT 9 |
64 | #define S3C64XX_SPI_ENCLK_ENABLE (1<<8) | 64 | #define S3C64XX_SPI_ENCLK_ENABLE (1<<8) |
65 | #define S3C64XX_SPI_PSR_MASK 0xff | 65 | #define S3C64XX_SPI_PSR_MASK 0xff |
66 | 66 | ||
67 | #define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29) | 67 | #define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29) |
68 | #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29) | 68 | #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29) |
@@ -695,7 +695,7 @@ static int s3c64xx_spi_transfer_one_message(struct spi_master *master, | |||
695 | INIT_COMPLETION(sdd->xfer_completion); | 695 | INIT_COMPLETION(sdd->xfer_completion); |
696 | 696 | ||
697 | /* Only BPW and Speed may change across transfers */ | 697 | /* Only BPW and Speed may change across transfers */ |
698 | bpw = xfer->bits_per_word ? : spi->bits_per_word; | 698 | bpw = xfer->bits_per_word; |
699 | speed = xfer->speed_hz ? : spi->max_speed_hz; | 699 | speed = xfer->speed_hz ? : spi->max_speed_hz; |
700 | 700 | ||
701 | if (xfer->len % (bpw / 8)) { | 701 | if (xfer->len % (bpw / 8)) { |
@@ -741,8 +741,7 @@ static int s3c64xx_spi_transfer_one_message(struct spi_master *master, | |||
741 | sdd->regs + S3C64XX_SPI_SLAVE_SEL); | 741 | sdd->regs + S3C64XX_SPI_SLAVE_SEL); |
742 | 742 | ||
743 | if (status) { | 743 | if (status) { |
744 | dev_err(&spi->dev, "I/O Error: " | 744 | dev_err(&spi->dev, "I/O Error: rx-%d tx-%d res:rx-%c tx-%c len-%d\n", |
745 | "rx-%d tx-%d res:rx-%c tx-%c len-%d\n", | ||
746 | xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0, | 745 | xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0, |
747 | (sdd->state & RXBUSY) ? 'f' : 'p', | 746 | (sdd->state & RXBUSY) ? 'f' : 'p', |
748 | (sdd->state & TXBUSY) ? 'f' : 'p', | 747 | (sdd->state & TXBUSY) ? 'f' : 'p', |
@@ -797,7 +796,7 @@ static int s3c64xx_spi_prepare_transfer(struct spi_master *spi) | |||
797 | 796 | ||
798 | /* Acquire DMA channels */ | 797 | /* Acquire DMA channels */ |
799 | while (!acquire_dma(sdd)) | 798 | while (!acquire_dma(sdd)) |
800 | msleep(10); | 799 | usleep_range(10000, 11000); |
801 | 800 | ||
802 | pm_runtime_get_sync(&sdd->pdev->dev); | 801 | pm_runtime_get_sync(&sdd->pdev->dev); |
803 | 802 | ||
@@ -839,16 +838,14 @@ static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata( | |||
839 | 838 | ||
840 | cs = kzalloc(sizeof(*cs), GFP_KERNEL); | 839 | cs = kzalloc(sizeof(*cs), GFP_KERNEL); |
841 | if (!cs) { | 840 | if (!cs) { |
842 | dev_err(&spi->dev, "could not allocate memory for controller" | 841 | dev_err(&spi->dev, "could not allocate memory for controller data\n"); |
843 | " data\n"); | ||
844 | of_node_put(data_np); | 842 | of_node_put(data_np); |
845 | return ERR_PTR(-ENOMEM); | 843 | return ERR_PTR(-ENOMEM); |
846 | } | 844 | } |
847 | 845 | ||
848 | cs->line = of_get_named_gpio(data_np, "cs-gpio", 0); | 846 | cs->line = of_get_named_gpio(data_np, "cs-gpio", 0); |
849 | if (!gpio_is_valid(cs->line)) { | 847 | if (!gpio_is_valid(cs->line)) { |
850 | dev_err(&spi->dev, "chip select gpio is not specified or " | 848 | dev_err(&spi->dev, "chip select gpio is not specified or invalid\n"); |
851 | "invalid\n"); | ||
852 | kfree(cs); | 849 | kfree(cs); |
853 | of_node_put(data_np); | 850 | of_node_put(data_np); |
854 | return ERR_PTR(-EINVAL); | 851 | return ERR_PTR(-EINVAL); |
@@ -955,6 +952,8 @@ static int s3c64xx_spi_setup(struct spi_device *spi) | |||
955 | if (spi->max_speed_hz >= speed) { | 952 | if (spi->max_speed_hz >= speed) { |
956 | spi->max_speed_hz = speed; | 953 | spi->max_speed_hz = speed; |
957 | } else { | 954 | } else { |
955 | dev_err(&spi->dev, "Can't set %dHz transfer speed\n", | ||
956 | spi->max_speed_hz); | ||
958 | err = -EINVAL; | 957 | err = -EINVAL; |
959 | goto setup_exit; | 958 | goto setup_exit; |
960 | } | 959 | } |
@@ -1088,8 +1087,7 @@ static void s3c64xx_spi_dt_gpio_free(struct s3c64xx_spi_driver_data *sdd) | |||
1088 | gpio_free(sdd->gpios[idx]); | 1087 | gpio_free(sdd->gpios[idx]); |
1089 | } | 1088 | } |
1090 | 1089 | ||
1091 | static struct s3c64xx_spi_info * s3c64xx_spi_parse_dt( | 1090 | static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev) |
1092 | struct device *dev) | ||
1093 | { | 1091 | { |
1094 | struct s3c64xx_spi_info *sci; | 1092 | struct s3c64xx_spi_info *sci; |
1095 | u32 temp; | 1093 | u32 temp; |
@@ -1101,16 +1099,14 @@ static struct s3c64xx_spi_info * s3c64xx_spi_parse_dt( | |||
1101 | } | 1099 | } |
1102 | 1100 | ||
1103 | if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) { | 1101 | if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) { |
1104 | dev_warn(dev, "spi bus clock parent not specified, using " | 1102 | dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n"); |
1105 | "clock at index 0 as parent\n"); | ||
1106 | sci->src_clk_nr = 0; | 1103 | sci->src_clk_nr = 0; |
1107 | } else { | 1104 | } else { |
1108 | sci->src_clk_nr = temp; | 1105 | sci->src_clk_nr = temp; |
1109 | } | 1106 | } |
1110 | 1107 | ||
1111 | if (of_property_read_u32(dev->of_node, "num-cs", &temp)) { | 1108 | if (of_property_read_u32(dev->of_node, "num-cs", &temp)) { |
1112 | dev_warn(dev, "number of chip select lines not specified, " | 1109 | dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n"); |
1113 | "assuming 1 chip select line\n"); | ||
1114 | sci->num_cs = 1; | 1110 | sci->num_cs = 1; |
1115 | } else { | 1111 | } else { |
1116 | sci->num_cs = temp; | 1112 | sci->num_cs = temp; |
@@ -1150,7 +1146,7 @@ static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config( | |||
1150 | platform_get_device_id(pdev)->driver_data; | 1146 | platform_get_device_id(pdev)->driver_data; |
1151 | } | 1147 | } |
1152 | 1148 | ||
1153 | static int __init s3c64xx_spi_probe(struct platform_device *pdev) | 1149 | static int s3c64xx_spi_probe(struct platform_device *pdev) |
1154 | { | 1150 | { |
1155 | struct resource *mem_res; | 1151 | struct resource *mem_res; |
1156 | struct resource *res; | 1152 | struct resource *res; |
@@ -1201,8 +1197,8 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev) | |||
1201 | if (pdev->dev.of_node) { | 1197 | if (pdev->dev.of_node) { |
1202 | ret = of_alias_get_id(pdev->dev.of_node, "spi"); | 1198 | ret = of_alias_get_id(pdev->dev.of_node, "spi"); |
1203 | if (ret < 0) { | 1199 | if (ret < 0) { |
1204 | dev_err(&pdev->dev, "failed to get alias id, " | 1200 | dev_err(&pdev->dev, "failed to get alias id, errno %d\n", |
1205 | "errno %d\n", ret); | 1201 | ret); |
1206 | goto err0; | 1202 | goto err0; |
1207 | } | 1203 | } |
1208 | sdd->port_id = ret; | 1204 | sdd->port_id = ret; |
@@ -1249,7 +1245,7 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev) | |||
1249 | if (sdd->regs == NULL) { | 1245 | if (sdd->regs == NULL) { |
1250 | dev_err(&pdev->dev, "Unable to remap IO\n"); | 1246 | dev_err(&pdev->dev, "Unable to remap IO\n"); |
1251 | ret = -ENXIO; | 1247 | ret = -ENXIO; |
1252 | goto err1; | 1248 | goto err0; |
1253 | } | 1249 | } |
1254 | 1250 | ||
1255 | if (!sci->cfg_gpio && pdev->dev.of_node) { | 1251 | if (!sci->cfg_gpio && pdev->dev.of_node) { |
@@ -1258,36 +1254,36 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev) | |||
1258 | } else if (sci->cfg_gpio == NULL || sci->cfg_gpio()) { | 1254 | } else if (sci->cfg_gpio == NULL || sci->cfg_gpio()) { |
1259 | dev_err(&pdev->dev, "Unable to config gpio\n"); | 1255 | dev_err(&pdev->dev, "Unable to config gpio\n"); |
1260 | ret = -EBUSY; | 1256 | ret = -EBUSY; |
1261 | goto err2; | 1257 | goto err0; |
1262 | } | 1258 | } |
1263 | 1259 | ||
1264 | /* Setup clocks */ | 1260 | /* Setup clocks */ |
1265 | sdd->clk = clk_get(&pdev->dev, "spi"); | 1261 | sdd->clk = devm_clk_get(&pdev->dev, "spi"); |
1266 | if (IS_ERR(sdd->clk)) { | 1262 | if (IS_ERR(sdd->clk)) { |
1267 | dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n"); | 1263 | dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n"); |
1268 | ret = PTR_ERR(sdd->clk); | 1264 | ret = PTR_ERR(sdd->clk); |
1269 | goto err3; | 1265 | goto err1; |
1270 | } | 1266 | } |
1271 | 1267 | ||
1272 | if (clk_prepare_enable(sdd->clk)) { | 1268 | if (clk_prepare_enable(sdd->clk)) { |
1273 | dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n"); | 1269 | dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n"); |
1274 | ret = -EBUSY; | 1270 | ret = -EBUSY; |
1275 | goto err4; | 1271 | goto err1; |
1276 | } | 1272 | } |
1277 | 1273 | ||
1278 | sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr); | 1274 | sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr); |
1279 | sdd->src_clk = clk_get(&pdev->dev, clk_name); | 1275 | sdd->src_clk = devm_clk_get(&pdev->dev, clk_name); |
1280 | if (IS_ERR(sdd->src_clk)) { | 1276 | if (IS_ERR(sdd->src_clk)) { |
1281 | dev_err(&pdev->dev, | 1277 | dev_err(&pdev->dev, |
1282 | "Unable to acquire clock '%s'\n", clk_name); | 1278 | "Unable to acquire clock '%s'\n", clk_name); |
1283 | ret = PTR_ERR(sdd->src_clk); | 1279 | ret = PTR_ERR(sdd->src_clk); |
1284 | goto err5; | 1280 | goto err2; |
1285 | } | 1281 | } |
1286 | 1282 | ||
1287 | if (clk_prepare_enable(sdd->src_clk)) { | 1283 | if (clk_prepare_enable(sdd->src_clk)) { |
1288 | dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name); | 1284 | dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name); |
1289 | ret = -EBUSY; | 1285 | ret = -EBUSY; |
1290 | goto err6; | 1286 | goto err2; |
1291 | } | 1287 | } |
1292 | 1288 | ||
1293 | /* Setup Deufult Mode */ | 1289 | /* Setup Deufult Mode */ |
@@ -1297,11 +1293,12 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev) | |||
1297 | init_completion(&sdd->xfer_completion); | 1293 | init_completion(&sdd->xfer_completion); |
1298 | INIT_LIST_HEAD(&sdd->queue); | 1294 | INIT_LIST_HEAD(&sdd->queue); |
1299 | 1295 | ||
1300 | ret = request_irq(irq, s3c64xx_spi_irq, 0, "spi-s3c64xx", sdd); | 1296 | ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0, |
1297 | "spi-s3c64xx", sdd); | ||
1301 | if (ret != 0) { | 1298 | if (ret != 0) { |
1302 | dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n", | 1299 | dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n", |
1303 | irq, ret); | 1300 | irq, ret); |
1304 | goto err7; | 1301 | goto err3; |
1305 | } | 1302 | } |
1306 | 1303 | ||
1307 | writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN | | 1304 | writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN | |
@@ -1311,11 +1308,10 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev) | |||
1311 | if (spi_register_master(master)) { | 1308 | if (spi_register_master(master)) { |
1312 | dev_err(&pdev->dev, "cannot register SPI master\n"); | 1309 | dev_err(&pdev->dev, "cannot register SPI master\n"); |
1313 | ret = -EBUSY; | 1310 | ret = -EBUSY; |
1314 | goto err8; | 1311 | goto err3; |
1315 | } | 1312 | } |
1316 | 1313 | ||
1317 | dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d " | 1314 | dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n", |
1318 | "with %d Slaves attached\n", | ||
1319 | sdd->port_id, master->num_chipselect); | 1315 | sdd->port_id, master->num_chipselect); |
1320 | dev_dbg(&pdev->dev, "\tIOmem=[0x%x-0x%x]\tDMA=[Rx-%d, Tx-%d]\n", | 1316 | dev_dbg(&pdev->dev, "\tIOmem=[0x%x-0x%x]\tDMA=[Rx-%d, Tx-%d]\n", |
1321 | mem_res->end, mem_res->start, | 1317 | mem_res->end, mem_res->start, |
@@ -1325,21 +1321,13 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev) | |||
1325 | 1321 | ||
1326 | return 0; | 1322 | return 0; |
1327 | 1323 | ||
1328 | err8: | 1324 | err3: |
1329 | free_irq(irq, sdd); | ||
1330 | err7: | ||
1331 | clk_disable_unprepare(sdd->src_clk); | 1325 | clk_disable_unprepare(sdd->src_clk); |
1332 | err6: | 1326 | err2: |
1333 | clk_put(sdd->src_clk); | ||
1334 | err5: | ||
1335 | clk_disable_unprepare(sdd->clk); | 1327 | clk_disable_unprepare(sdd->clk); |
1336 | err4: | 1328 | err1: |
1337 | clk_put(sdd->clk); | ||
1338 | err3: | ||
1339 | if (!sdd->cntrlr_info->cfg_gpio && pdev->dev.of_node) | 1329 | if (!sdd->cntrlr_info->cfg_gpio && pdev->dev.of_node) |
1340 | s3c64xx_spi_dt_gpio_free(sdd); | 1330 | s3c64xx_spi_dt_gpio_free(sdd); |
1341 | err2: | ||
1342 | err1: | ||
1343 | err0: | 1331 | err0: |
1344 | platform_set_drvdata(pdev, NULL); | 1332 | platform_set_drvdata(pdev, NULL); |
1345 | spi_master_put(master); | 1333 | spi_master_put(master); |
@@ -1358,13 +1346,9 @@ static int s3c64xx_spi_remove(struct platform_device *pdev) | |||
1358 | 1346 | ||
1359 | writel(0, sdd->regs + S3C64XX_SPI_INT_EN); | 1347 | writel(0, sdd->regs + S3C64XX_SPI_INT_EN); |
1360 | 1348 | ||
1361 | free_irq(platform_get_irq(pdev, 0), sdd); | ||
1362 | |||
1363 | clk_disable_unprepare(sdd->src_clk); | 1349 | clk_disable_unprepare(sdd->src_clk); |
1364 | clk_put(sdd->src_clk); | ||
1365 | 1350 | ||
1366 | clk_disable_unprepare(sdd->clk); | 1351 | clk_disable_unprepare(sdd->clk); |
1367 | clk_put(sdd->clk); | ||
1368 | 1352 | ||
1369 | if (!sdd->cntrlr_info->cfg_gpio && pdev->dev.of_node) | 1353 | if (!sdd->cntrlr_info->cfg_gpio && pdev->dev.of_node) |
1370 | s3c64xx_spi_dt_gpio_free(sdd); | 1354 | s3c64xx_spi_dt_gpio_free(sdd); |
diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c index 96358d0eabb7..8b40d0884f8b 100644 --- a/drivers/spi/spi-sh-msiof.c +++ b/drivers/spi/spi-sh-msiof.c | |||
@@ -20,6 +20,7 @@ | |||
20 | #include <linux/io.h> | 20 | #include <linux/io.h> |
21 | #include <linux/kernel.h> | 21 | #include <linux/kernel.h> |
22 | #include <linux/module.h> | 22 | #include <linux/module.h> |
23 | #include <linux/of.h> | ||
23 | #include <linux/platform_device.h> | 24 | #include <linux/platform_device.h> |
24 | #include <linux/pm_runtime.h> | 25 | #include <linux/pm_runtime.h> |
25 | 26 | ||
@@ -592,6 +593,37 @@ static u32 sh_msiof_spi_txrx_word(struct spi_device *spi, unsigned nsecs, | |||
592 | return 0; | 593 | return 0; |
593 | } | 594 | } |
594 | 595 | ||
596 | #ifdef CONFIG_OF | ||
597 | static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev) | ||
598 | { | ||
599 | struct sh_msiof_spi_info *info; | ||
600 | struct device_node *np = dev->of_node; | ||
601 | u32 num_cs = 0; | ||
602 | |||
603 | info = devm_kzalloc(dev, sizeof(struct sh_msiof_spi_info), GFP_KERNEL); | ||
604 | if (!info) { | ||
605 | dev_err(dev, "failed to allocate setup data\n"); | ||
606 | return NULL; | ||
607 | } | ||
608 | |||
609 | /* Parse the MSIOF properties */ | ||
610 | of_property_read_u32(np, "num-cs", &num_cs); | ||
611 | of_property_read_u32(np, "renesas,tx-fifo-size", | ||
612 | &info->tx_fifo_override); | ||
613 | of_property_read_u32(np, "renesas,rx-fifo-size", | ||
614 | &info->rx_fifo_override); | ||
615 | |||
616 | info->num_chipselect = num_cs; | ||
617 | |||
618 | return info; | ||
619 | } | ||
620 | #else | ||
621 | static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev) | ||
622 | { | ||
623 | return NULL; | ||
624 | } | ||
625 | #endif | ||
626 | |||
595 | static int sh_msiof_spi_probe(struct platform_device *pdev) | 627 | static int sh_msiof_spi_probe(struct platform_device *pdev) |
596 | { | 628 | { |
597 | struct resource *r; | 629 | struct resource *r; |
@@ -610,7 +642,17 @@ static int sh_msiof_spi_probe(struct platform_device *pdev) | |||
610 | p = spi_master_get_devdata(master); | 642 | p = spi_master_get_devdata(master); |
611 | 643 | ||
612 | platform_set_drvdata(pdev, p); | 644 | platform_set_drvdata(pdev, p); |
613 | p->info = pdev->dev.platform_data; | 645 | if (pdev->dev.of_node) |
646 | p->info = sh_msiof_spi_parse_dt(&pdev->dev); | ||
647 | else | ||
648 | p->info = pdev->dev.platform_data; | ||
649 | |||
650 | if (!p->info) { | ||
651 | dev_err(&pdev->dev, "failed to obtain device info\n"); | ||
652 | ret = -ENXIO; | ||
653 | goto err1; | ||
654 | } | ||
655 | |||
614 | init_completion(&p->done); | 656 | init_completion(&p->done); |
615 | 657 | ||
616 | p->clk = clk_get(&pdev->dev, NULL); | 658 | p->clk = clk_get(&pdev->dev, NULL); |
@@ -715,6 +757,17 @@ static int sh_msiof_spi_runtime_nop(struct device *dev) | |||
715 | return 0; | 757 | return 0; |
716 | } | 758 | } |
717 | 759 | ||
760 | #ifdef CONFIG_OF | ||
761 | static const struct of_device_id sh_msiof_match[] = { | ||
762 | { .compatible = "renesas,sh-msiof", }, | ||
763 | { .compatible = "renesas,sh-mobile-msiof", }, | ||
764 | {}, | ||
765 | }; | ||
766 | MODULE_DEVICE_TABLE(of, sh_msiof_match); | ||
767 | #else | ||
768 | #define sh_msiof_match NULL | ||
769 | #endif | ||
770 | |||
718 | static struct dev_pm_ops sh_msiof_spi_dev_pm_ops = { | 771 | static struct dev_pm_ops sh_msiof_spi_dev_pm_ops = { |
719 | .runtime_suspend = sh_msiof_spi_runtime_nop, | 772 | .runtime_suspend = sh_msiof_spi_runtime_nop, |
720 | .runtime_resume = sh_msiof_spi_runtime_nop, | 773 | .runtime_resume = sh_msiof_spi_runtime_nop, |
@@ -727,6 +780,7 @@ static struct platform_driver sh_msiof_spi_drv = { | |||
727 | .name = "spi_sh_msiof", | 780 | .name = "spi_sh_msiof", |
728 | .owner = THIS_MODULE, | 781 | .owner = THIS_MODULE, |
729 | .pm = &sh_msiof_spi_dev_pm_ops, | 782 | .pm = &sh_msiof_spi_dev_pm_ops, |
783 | .of_match_table = sh_msiof_match, | ||
730 | }, | 784 | }, |
731 | }; | 785 | }; |
732 | module_platform_driver(sh_msiof_spi_drv); | 786 | module_platform_driver(sh_msiof_spi_drv); |
diff --git a/drivers/spi/spi-sirf.c b/drivers/spi/spi-sirf.c index e0f43a512e84..6a5626d146b7 100644 --- a/drivers/spi/spi-sirf.c +++ b/drivers/spi/spi-sirf.c | |||
@@ -382,8 +382,7 @@ spi_sirfsoc_setup_transfer(struct spi_device *spi, struct spi_transfer *t) | |||
382 | 382 | ||
383 | sspi = spi_master_get_devdata(spi->master); | 383 | sspi = spi_master_get_devdata(spi->master); |
384 | 384 | ||
385 | bits_per_word = t && t->bits_per_word ? t->bits_per_word : | 385 | bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word; |
386 | spi->bits_per_word; | ||
387 | hz = t && t->speed_hz ? t->speed_hz : spi->max_speed_hz; | 386 | hz = t && t->speed_hz ? t->speed_hz : spi->max_speed_hz; |
388 | 387 | ||
389 | /* Enable IO mode for RX, TX */ | 388 | /* Enable IO mode for RX, TX */ |
@@ -570,7 +569,7 @@ static int spi_sirfsoc_probe(struct platform_device *pdev) | |||
570 | ret = -EINVAL; | 569 | ret = -EINVAL; |
571 | goto free_pin; | 570 | goto free_pin; |
572 | } | 571 | } |
573 | clk_enable(sspi->clk); | 572 | clk_prepare_enable(sspi->clk); |
574 | sspi->ctrl_freq = clk_get_rate(sspi->clk); | 573 | sspi->ctrl_freq = clk_get_rate(sspi->clk); |
575 | 574 | ||
576 | init_completion(&sspi->done); | 575 | init_completion(&sspi->done); |
@@ -594,7 +593,7 @@ static int spi_sirfsoc_probe(struct platform_device *pdev) | |||
594 | return 0; | 593 | return 0; |
595 | 594 | ||
596 | free_clk: | 595 | free_clk: |
597 | clk_disable(sspi->clk); | 596 | clk_disable_unprepare(sspi->clk); |
598 | clk_put(sspi->clk); | 597 | clk_put(sspi->clk); |
599 | free_pin: | 598 | free_pin: |
600 | pinctrl_put(sspi->p); | 599 | pinctrl_put(sspi->p); |
@@ -618,7 +617,7 @@ static int spi_sirfsoc_remove(struct platform_device *pdev) | |||
618 | if (sspi->chipselect[i] > 0) | 617 | if (sspi->chipselect[i] > 0) |
619 | gpio_free(sspi->chipselect[i]); | 618 | gpio_free(sspi->chipselect[i]); |
620 | } | 619 | } |
621 | clk_disable(sspi->clk); | 620 | clk_disable_unprepare(sspi->clk); |
622 | clk_put(sspi->clk); | 621 | clk_put(sspi->clk); |
623 | pinctrl_put(sspi->p); | 622 | pinctrl_put(sspi->p); |
624 | spi_master_put(master); | 623 | spi_master_put(master); |
@@ -659,6 +658,7 @@ static const struct dev_pm_ops spi_sirfsoc_pm_ops = { | |||
659 | 658 | ||
660 | static const struct of_device_id spi_sirfsoc_of_match[] = { | 659 | static const struct of_device_id spi_sirfsoc_of_match[] = { |
661 | { .compatible = "sirf,prima2-spi", }, | 660 | { .compatible = "sirf,prima2-spi", }, |
661 | { .compatible = "sirf,marco-spi", }, | ||
662 | {} | 662 | {} |
663 | }; | 663 | }; |
664 | MODULE_DEVICE_TABLE(of, sirfsoc_spi_of_match); | 664 | MODULE_DEVICE_TABLE(of, sirfsoc_spi_of_match); |
diff --git a/drivers/spi/spi-tegra20-sflash.c b/drivers/spi/spi-tegra20-sflash.c index 448a8cc71df3..9a42c158e245 100644 --- a/drivers/spi/spi-tegra20-sflash.c +++ b/drivers/spi/spi-tegra20-sflash.c | |||
@@ -269,9 +269,7 @@ static int tegra_sflash_start_transfer_one(struct spi_device *spi, | |||
269 | u32 speed; | 269 | u32 speed; |
270 | unsigned long command; | 270 | unsigned long command; |
271 | 271 | ||
272 | speed = t->speed_hz ? t->speed_hz : spi->max_speed_hz; | 272 | speed = t->speed_hz; |
273 | if (!speed) | ||
274 | speed = tsd->spi_max_frequency; | ||
275 | if (speed != tsd->cur_speed) { | 273 | if (speed != tsd->cur_speed) { |
276 | clk_set_rate(tsd->clk, speed); | 274 | clk_set_rate(tsd->clk, speed); |
277 | tsd->cur_speed = speed; | 275 | tsd->cur_speed = speed; |
@@ -319,6 +317,15 @@ static int tegra_sflash_start_transfer_one(struct spi_device *spi, | |||
319 | return tegra_sflash_start_cpu_based_transfer(tsd, t); | 317 | return tegra_sflash_start_cpu_based_transfer(tsd, t); |
320 | } | 318 | } |
321 | 319 | ||
320 | static int tegra_sflash_setup(struct spi_device *spi) | ||
321 | { | ||
322 | struct tegra_sflash_data *tsd = spi_master_get_devdata(spi->master); | ||
323 | |||
324 | /* Set speed to the spi max fequency if spi device has not set */ | ||
325 | spi->max_speed_hz = spi->max_speed_hz ? : tsd->spi_max_frequency; | ||
326 | return 0; | ||
327 | } | ||
328 | |||
322 | static int tegra_sflash_transfer_one_message(struct spi_master *master, | 329 | static int tegra_sflash_transfer_one_message(struct spi_master *master, |
323 | struct spi_message *msg) | 330 | struct spi_message *msg) |
324 | { | 331 | { |
@@ -492,6 +499,7 @@ static int tegra_sflash_probe(struct platform_device *pdev) | |||
492 | 499 | ||
493 | /* the spi->mode bits understood by this driver: */ | 500 | /* the spi->mode bits understood by this driver: */ |
494 | master->mode_bits = SPI_CPOL | SPI_CPHA; | 501 | master->mode_bits = SPI_CPOL | SPI_CPHA; |
502 | master->setup = tegra_sflash_setup; | ||
495 | master->transfer_one_message = tegra_sflash_transfer_one_message; | 503 | master->transfer_one_message = tegra_sflash_transfer_one_message; |
496 | master->num_chipselect = MAX_CHIP_SELECT; | 504 | master->num_chipselect = MAX_CHIP_SELECT; |
497 | master->bus_num = -1; | 505 | master->bus_num = -1; |
diff --git a/drivers/spi/spi-tegra20-slink.c b/drivers/spi/spi-tegra20-slink.c index 651167f2e0af..8d51db8dea6d 100644 --- a/drivers/spi/spi-tegra20-slink.c +++ b/drivers/spi/spi-tegra20-slink.c | |||
@@ -284,8 +284,7 @@ static unsigned tegra_slink_calculate_curr_xfer_param( | |||
284 | unsigned max_len; | 284 | unsigned max_len; |
285 | unsigned total_fifo_words; | 285 | unsigned total_fifo_words; |
286 | 286 | ||
287 | bits_per_word = t->bits_per_word ? t->bits_per_word : | 287 | bits_per_word = t->bits_per_word; |
288 | spi->bits_per_word; | ||
289 | tspi->bytes_per_word = (bits_per_word - 1) / 8 + 1; | 288 | tspi->bytes_per_word = (bits_per_word - 1) / 8 + 1; |
290 | 289 | ||
291 | if (bits_per_word == 8 || bits_per_word == 16) { | 290 | if (bits_per_word == 8 || bits_per_word == 16) { |
@@ -378,8 +377,7 @@ static unsigned int tegra_slink_read_rx_fifo_to_client_rxbuf( | |||
378 | } else { | 377 | } else { |
379 | unsigned int bits_per_word; | 378 | unsigned int bits_per_word; |
380 | 379 | ||
381 | bits_per_word = t->bits_per_word ? t->bits_per_word : | 380 | bits_per_word = t->bits_per_word; |
382 | tspi->cur_spi->bits_per_word; | ||
383 | for (count = 0; count < rx_full_count; count++) { | 381 | for (count = 0; count < rx_full_count; count++) { |
384 | x = tegra_slink_readl(tspi, SLINK_RX_FIFO); | 382 | x = tegra_slink_readl(tspi, SLINK_RX_FIFO); |
385 | for (i = 0; (i < tspi->bytes_per_word); i++) | 383 | for (i = 0; (i < tspi->bytes_per_word); i++) |
@@ -444,8 +442,7 @@ static void tegra_slink_copy_spi_rxbuf_to_client_rxbuf( | |||
444 | unsigned int x; | 442 | unsigned int x; |
445 | unsigned int rx_mask, bits_per_word; | 443 | unsigned int rx_mask, bits_per_word; |
446 | 444 | ||
447 | bits_per_word = t->bits_per_word ? t->bits_per_word : | 445 | bits_per_word = t->bits_per_word; |
448 | tspi->cur_spi->bits_per_word; | ||
449 | rx_mask = (1 << bits_per_word) - 1; | 446 | rx_mask = (1 << bits_per_word) - 1; |
450 | for (count = 0; count < tspi->curr_dma_words; count++) { | 447 | for (count = 0; count < tspi->curr_dma_words; count++) { |
451 | x = tspi->rx_dma_buf[count]; | 448 | x = tspi->rx_dma_buf[count]; |
@@ -728,9 +725,7 @@ static int tegra_slink_start_transfer_one(struct spi_device *spi, | |||
728 | unsigned long command2; | 725 | unsigned long command2; |
729 | 726 | ||
730 | bits_per_word = t->bits_per_word; | 727 | bits_per_word = t->bits_per_word; |
731 | speed = t->speed_hz ? t->speed_hz : spi->max_speed_hz; | 728 | speed = t->speed_hz; |
732 | if (!speed) | ||
733 | speed = tspi->spi_max_frequency; | ||
734 | if (speed != tspi->cur_speed) { | 729 | if (speed != tspi->cur_speed) { |
735 | clk_set_rate(tspi->clk, speed * 4); | 730 | clk_set_rate(tspi->clk, speed * 4); |
736 | tspi->cur_speed = speed; | 731 | tspi->cur_speed = speed; |
@@ -841,6 +836,8 @@ static int tegra_slink_setup(struct spi_device *spi) | |||
841 | 836 | ||
842 | BUG_ON(spi->chip_select >= MAX_CHIP_SELECT); | 837 | BUG_ON(spi->chip_select >= MAX_CHIP_SELECT); |
843 | 838 | ||
839 | /* Set speed to the spi max fequency if spi device has not set */ | ||
840 | spi->max_speed_hz = spi->max_speed_hz ? : tspi->spi_max_frequency; | ||
844 | ret = pm_runtime_get_sync(tspi->dev); | 841 | ret = pm_runtime_get_sync(tspi->dev); |
845 | if (ret < 0) { | 842 | if (ret < 0) { |
846 | dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret); | 843 | dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret); |
diff --git a/drivers/spi/spi-txx9.c b/drivers/spi/spi-txx9.c index d5a3cbb646cb..adb853047926 100644 --- a/drivers/spi/spi-txx9.c +++ b/drivers/spi/spi-txx9.c | |||
@@ -189,9 +189,8 @@ static void txx9spi_work_one(struct txx9spi *c, struct spi_message *m) | |||
189 | unsigned int len = t->len; | 189 | unsigned int len = t->len; |
190 | unsigned int wsize; | 190 | unsigned int wsize; |
191 | u32 speed_hz = t->speed_hz ? : spi->max_speed_hz; | 191 | u32 speed_hz = t->speed_hz ? : spi->max_speed_hz; |
192 | u8 bits_per_word = t->bits_per_word ? : spi->bits_per_word; | 192 | u8 bits_per_word = t->bits_per_word; |
193 | 193 | ||
194 | bits_per_word = bits_per_word ? : 8; | ||
195 | wsize = bits_per_word >> 3; /* in bytes */ | 194 | wsize = bits_per_word >> 3; /* in bytes */ |
196 | 195 | ||
197 | if (prev_speed_hz != speed_hz | 196 | if (prev_speed_hz != speed_hz |
@@ -316,9 +315,8 @@ static int txx9spi_transfer(struct spi_device *spi, struct spi_message *m) | |||
316 | /* check each transfer's parameters */ | 315 | /* check each transfer's parameters */ |
317 | list_for_each_entry (t, &m->transfers, transfer_list) { | 316 | list_for_each_entry (t, &m->transfers, transfer_list) { |
318 | u32 speed_hz = t->speed_hz ? : spi->max_speed_hz; | 317 | u32 speed_hz = t->speed_hz ? : spi->max_speed_hz; |
319 | u8 bits_per_word = t->bits_per_word ? : spi->bits_per_word; | 318 | u8 bits_per_word = t->bits_per_word; |
320 | 319 | ||
321 | bits_per_word = bits_per_word ? : 8; | ||
322 | if (!t->tx_buf && !t->rx_buf && t->len) | 320 | if (!t->tx_buf && !t->rx_buf && t->len) |
323 | return -EINVAL; | 321 | return -EINVAL; |
324 | if (bits_per_word != 8 && bits_per_word != 16) | 322 | if (bits_per_word != 8 && bits_per_word != 16) |
@@ -337,7 +335,7 @@ static int txx9spi_transfer(struct spi_device *spi, struct spi_message *m) | |||
337 | return 0; | 335 | return 0; |
338 | } | 336 | } |
339 | 337 | ||
340 | static int __init txx9spi_probe(struct platform_device *dev) | 338 | static int txx9spi_probe(struct platform_device *dev) |
341 | { | 339 | { |
342 | struct spi_master *master; | 340 | struct spi_master *master; |
343 | struct txx9spi *c; | 341 | struct txx9spi *c; |
@@ -432,7 +430,7 @@ exit: | |||
432 | return ret; | 430 | return ret; |
433 | } | 431 | } |
434 | 432 | ||
435 | static int __exit txx9spi_remove(struct platform_device *dev) | 433 | static int txx9spi_remove(struct platform_device *dev) |
436 | { | 434 | { |
437 | struct spi_master *master = spi_master_get(platform_get_drvdata(dev)); | 435 | struct spi_master *master = spi_master_get(platform_get_drvdata(dev)); |
438 | struct txx9spi *c = spi_master_get_devdata(master); | 436 | struct txx9spi *c = spi_master_get_devdata(master); |
@@ -450,7 +448,7 @@ static int __exit txx9spi_remove(struct platform_device *dev) | |||
450 | MODULE_ALIAS("platform:spi_txx9"); | 448 | MODULE_ALIAS("platform:spi_txx9"); |
451 | 449 | ||
452 | static struct platform_driver txx9spi_driver = { | 450 | static struct platform_driver txx9spi_driver = { |
453 | .remove = __exit_p(txx9spi_remove), | 451 | .remove = txx9spi_remove, |
454 | .driver = { | 452 | .driver = { |
455 | .name = "spi_txx9", | 453 | .name = "spi_txx9", |
456 | .owner = THIS_MODULE, | 454 | .owner = THIS_MODULE, |
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index 19ee901577da..6f193b02a9e8 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c | |||
@@ -33,7 +33,7 @@ | |||
33 | #include <linux/of_gpio.h> | 33 | #include <linux/of_gpio.h> |
34 | #include <linux/pm_runtime.h> | 34 | #include <linux/pm_runtime.h> |
35 | #include <linux/export.h> | 35 | #include <linux/export.h> |
36 | #include <linux/sched.h> | 36 | #include <linux/sched/rt.h> |
37 | #include <linux/delay.h> | 37 | #include <linux/delay.h> |
38 | #include <linux/kthread.h> | 38 | #include <linux/kthread.h> |
39 | #include <linux/ioport.h> | 39 | #include <linux/ioport.h> |
@@ -1059,15 +1059,14 @@ EXPORT_SYMBOL_GPL(spi_alloc_master); | |||
1059 | #ifdef CONFIG_OF | 1059 | #ifdef CONFIG_OF |
1060 | static int of_spi_register_master(struct spi_master *master) | 1060 | static int of_spi_register_master(struct spi_master *master) |
1061 | { | 1061 | { |
1062 | u16 nb; | 1062 | int nb, i, *cs; |
1063 | int i, *cs; | ||
1064 | struct device_node *np = master->dev.of_node; | 1063 | struct device_node *np = master->dev.of_node; |
1065 | 1064 | ||
1066 | if (!np) | 1065 | if (!np) |
1067 | return 0; | 1066 | return 0; |
1068 | 1067 | ||
1069 | nb = of_gpio_named_count(np, "cs-gpios"); | 1068 | nb = of_gpio_named_count(np, "cs-gpios"); |
1070 | master->num_chipselect = max(nb, master->num_chipselect); | 1069 | master->num_chipselect = max(nb, (int)master->num_chipselect); |
1071 | 1070 | ||
1072 | if (nb < 1) | 1071 | if (nb < 1) |
1073 | return 0; | 1072 | return 0; |
@@ -1080,7 +1079,8 @@ static int of_spi_register_master(struct spi_master *master) | |||
1080 | if (!master->cs_gpios) | 1079 | if (!master->cs_gpios) |
1081 | return -ENOMEM; | 1080 | return -ENOMEM; |
1082 | 1081 | ||
1083 | memset(cs, -EINVAL, master->num_chipselect); | 1082 | for (i = 0; i < master->num_chipselect; i++) |
1083 | cs[i] = -EINVAL; | ||
1084 | 1084 | ||
1085 | for (i = 0; i < nb; i++) | 1085 | for (i = 0; i < nb; i++) |
1086 | cs[i] = of_get_named_gpio(np, "cs-gpios", i); | 1086 | cs[i] = of_get_named_gpio(np, "cs-gpios", i); |
@@ -1135,6 +1135,9 @@ int spi_register_master(struct spi_master *master) | |||
1135 | if (master->num_chipselect == 0) | 1135 | if (master->num_chipselect == 0) |
1136 | return -EINVAL; | 1136 | return -EINVAL; |
1137 | 1137 | ||
1138 | if ((master->bus_num < 0) && master->dev.of_node) | ||
1139 | master->bus_num = of_alias_get_id(master->dev.of_node, "spi"); | ||
1140 | |||
1138 | /* convention: dynamically assigned bus IDs count down from the max */ | 1141 | /* convention: dynamically assigned bus IDs count down from the max */ |
1139 | if (master->bus_num < 0) { | 1142 | if (master->bus_num < 0) { |
1140 | /* FIXME switch to an IDR based scheme, something like | 1143 | /* FIXME switch to an IDR based scheme, something like |
@@ -1366,12 +1369,14 @@ static int __spi_async(struct spi_device *spi, struct spi_message *message) | |||
1366 | } | 1369 | } |
1367 | 1370 | ||
1368 | /** | 1371 | /** |
1369 | * Set transfer bits_per_word as spi device default if it is not | 1372 | * Set transfer bits_per_word and max speed as spi device default if |
1370 | * set for this transfer. | 1373 | * it is not set for this transfer. |
1371 | */ | 1374 | */ |
1372 | list_for_each_entry(xfer, &message->transfers, transfer_list) { | 1375 | list_for_each_entry(xfer, &message->transfers, transfer_list) { |
1373 | if (!xfer->bits_per_word) | 1376 | if (!xfer->bits_per_word) |
1374 | xfer->bits_per_word = spi->bits_per_word; | 1377 | xfer->bits_per_word = spi->bits_per_word; |
1378 | if (!xfer->speed_hz) | ||
1379 | xfer->speed_hz = spi->max_speed_hz; | ||
1375 | } | 1380 | } |
1376 | 1381 | ||
1377 | message->spi = spi; | 1382 | message->spi = spi; |
@@ -1656,7 +1661,8 @@ int spi_write_then_read(struct spi_device *spi, | |||
1656 | * using the pre-allocated buffer or the transfer is too large. | 1661 | * using the pre-allocated buffer or the transfer is too large. |
1657 | */ | 1662 | */ |
1658 | if ((n_tx + n_rx) > SPI_BUFSIZ || !mutex_trylock(&lock)) { | 1663 | if ((n_tx + n_rx) > SPI_BUFSIZ || !mutex_trylock(&lock)) { |
1659 | local_buf = kmalloc(max((unsigned)SPI_BUFSIZ, n_tx + n_rx), GFP_KERNEL); | 1664 | local_buf = kmalloc(max((unsigned)SPI_BUFSIZ, n_tx + n_rx), |
1665 | GFP_KERNEL | GFP_DMA); | ||
1660 | if (!local_buf) | 1666 | if (!local_buf) |
1661 | return -ENOMEM; | 1667 | return -ENOMEM; |
1662 | } else { | 1668 | } else { |