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-rw-r--r--drivers/spi/Kconfig21
-rw-r--r--drivers/spi/Makefile1
-rw-r--r--drivers/spi/spi-altera.c7
-rw-r--r--drivers/spi/spi-ath79.c5
-rw-r--r--drivers/spi/spi-atmel.c51
-rw-r--r--drivers/spi/spi-au1550.c30
-rw-r--r--drivers/spi/spi-bcm2835.c1
-rw-r--r--drivers/spi/spi-bcm63xx-hsspi.c8
-rw-r--r--drivers/spi/spi-bcm63xx.c6
-rw-r--r--drivers/spi/spi-bfin-sport.c1
-rw-r--r--drivers/spi/spi-bfin-v3.c3
-rw-r--r--drivers/spi/spi-bfin5xx.c8
-rw-r--r--drivers/spi/spi-bitbang.c5
-rw-r--r--drivers/spi/spi-butterfly.c3
-rw-r--r--drivers/spi/spi-clps711x.c227
-rw-r--r--drivers/spi/spi-coldfire-qspi.c118
-rw-r--r--drivers/spi/spi-davinci.c14
-rw-r--r--drivers/spi/spi-dw-mmio.c2
-rw-r--r--drivers/spi/spi-dw.c17
-rw-r--r--drivers/spi/spi-efm32.c46
-rw-r--r--drivers/spi/spi-ep93xx.c21
-rw-r--r--drivers/spi/spi-falcon.c5
-rw-r--r--drivers/spi/spi-fsl-dspi.c100
-rw-r--r--drivers/spi/spi-fsl-espi.c5
-rw-r--r--drivers/spi/spi-fsl-lib.c14
-rw-r--r--drivers/spi/spi-fsl-spi.c30
-rw-r--r--drivers/spi/spi-gpio.c8
-rw-r--r--drivers/spi/spi-imx.c11
-rw-r--r--drivers/spi/spi-mpc512x-psc.c17
-rw-r--r--drivers/spi/spi-mpc52xx-psc.c1
-rw-r--r--drivers/spi/spi-mpc52xx.c17
-rw-r--r--drivers/spi/spi-mxs.c7
-rw-r--r--drivers/spi/spi-nuc900.c28
-rw-r--r--drivers/spi/spi-oc-tiny.c3
-rw-r--r--drivers/spi/spi-octeon.c80
-rw-r--r--drivers/spi/spi-omap-100k.c52
-rw-r--r--drivers/spi/spi-omap-uwire.c34
-rw-r--r--drivers/spi/spi-omap2-mcspi.c65
-rw-r--r--drivers/spi/spi-orion.c80
-rw-r--r--drivers/spi/spi-pl022.c5
-rw-r--r--drivers/spi/spi-ppc4xx.c1
-rw-r--r--drivers/spi/spi-pxa2xx-dma.c1
-rw-r--r--drivers/spi/spi-pxa2xx-pxadma.c1
-rw-r--r--drivers/spi/spi-pxa2xx.c3
-rw-r--r--drivers/spi/spi-qup.c779
-rw-r--r--drivers/spi/spi-rspi.c842
-rw-r--r--drivers/spi/spi-s3c24xx.c19
-rw-r--r--drivers/spi/spi-s3c64xx.c207
-rw-r--r--drivers/spi/spi-sh-hspi.c1
-rw-r--r--drivers/spi/spi-sh-msiof.c1
-rw-r--r--drivers/spi/spi-sh-sci.c1
-rw-r--r--drivers/spi/spi-tegra114.c23
-rw-r--r--drivers/spi/spi-tegra20-sflash.c26
-rw-r--r--drivers/spi/spi-tegra20-slink.c20
-rw-r--r--drivers/spi/spi-ti-qspi.c4
-rw-r--r--drivers/spi/spi-topcliff-pch.c15
-rw-r--r--drivers/spi/spi-xcomm.c1
-rw-r--r--drivers/spi/spi-xilinx.c1
-rw-r--r--drivers/spi/spi.c235
59 files changed, 2128 insertions, 1210 deletions
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 581ee2a8856b..5dea67c798d5 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -150,7 +150,7 @@ config SPI_BUTTERFLY
150 150
151config SPI_CLPS711X 151config SPI_CLPS711X
152 tristate "CLPS711X host SPI controller" 152 tristate "CLPS711X host SPI controller"
153 depends on ARCH_CLPS711X 153 depends on ARCH_CLPS711X || COMPILE_TEST
154 help 154 help
155 This enables dedicated general purpose SPI/Microwire1-compatible 155 This enables dedicated general purpose SPI/Microwire1-compatible
156 master mode interface (SSI1) for CLPS711X-based CPUs. 156 master mode interface (SSI1) for CLPS711X-based CPUs.
@@ -212,7 +212,6 @@ config SPI_IMX
212 tristate "Freescale i.MX SPI controllers" 212 tristate "Freescale i.MX SPI controllers"
213 depends on ARCH_MXC || COMPILE_TEST 213 depends on ARCH_MXC || COMPILE_TEST
214 select SPI_BITBANG 214 select SPI_BITBANG
215 default m if IMX_HAVE_PLATFORM_SPI_IMX
216 help 215 help
217 This enables using the Freescale i.MX SPI controllers in master 216 This enables using the Freescale i.MX SPI controllers in master
218 mode. 217 mode.
@@ -270,6 +269,7 @@ config SPI_FSL_SPI
270config SPI_FSL_DSPI 269config SPI_FSL_DSPI
271 tristate "Freescale DSPI controller" 270 tristate "Freescale DSPI controller"
272 select SPI_BITBANG 271 select SPI_BITBANG
272 select REGMAP_MMIO
273 depends on SOC_VF610 || COMPILE_TEST 273 depends on SOC_VF610 || COMPILE_TEST
274 help 274 help
275 This enables support for the Freescale DSPI controller in master 275 This enables support for the Freescale DSPI controller in master
@@ -307,7 +307,7 @@ config SPI_OMAP_UWIRE
307 307
308config SPI_OMAP24XX 308config SPI_OMAP24XX
309 tristate "McSPI driver for OMAP" 309 tristate "McSPI driver for OMAP"
310 depends on ARM || ARM64 || AVR32 || HEXAGON || MIPS || SH 310 depends on ARM || ARM64 || AVR32 || HEXAGON || MIPS || SUPERH
311 depends on ARCH_OMAP2PLUS || COMPILE_TEST 311 depends on ARCH_OMAP2PLUS || COMPILE_TEST
312 help 312 help
313 SPI master controller for OMAP24XX and later Multichannel SPI 313 SPI master controller for OMAP24XX and later Multichannel SPI
@@ -381,6 +381,19 @@ config SPI_RSPI
381 help 381 help
382 SPI driver for Renesas RSPI and QSPI blocks. 382 SPI driver for Renesas RSPI and QSPI blocks.
383 383
384config SPI_QUP
385 tristate "Qualcomm SPI controller with QUP interface"
386 depends on ARCH_MSM_DT || (ARM && COMPILE_TEST)
387 help
388 Qualcomm Universal Peripheral (QUP) core is an AHB slave that
389 provides a common data path (an output FIFO and an input FIFO)
390 for serial peripheral interface (SPI) mini-core. SPI in master
391 mode supports up to 50MHz, up to four chip selects, programmable
392 data path from 4 bits to 32 bits and numerous protocol variants.
393
394 This driver can also be built as a module. If so, the module
395 will be called spi_qup.
396
384config SPI_S3C24XX 397config SPI_S3C24XX
385 tristate "Samsung S3C24XX series SPI" 398 tristate "Samsung S3C24XX series SPI"
386 depends on ARCH_S3C24XX 399 depends on ARCH_S3C24XX
@@ -546,7 +559,7 @@ config SPI_DW_MID_DMA
546 559
547config SPI_DW_MMIO 560config SPI_DW_MMIO
548 tristate "Memory-mapped io interface driver for DW SPI core" 561 tristate "Memory-mapped io interface driver for DW SPI core"
549 depends on SPI_DESIGNWARE && HAVE_CLK 562 depends on SPI_DESIGNWARE
550 563
551# 564#
552# There are lots of SPI device types, with sensors and memory 565# There are lots of SPI device types, with sensors and memory
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 95af48d2d360..e598147b06ef 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -59,6 +59,7 @@ spi-pxa2xx-platform-$(CONFIG_SPI_PXA2XX_PXADMA) += spi-pxa2xx-pxadma.o
59spi-pxa2xx-platform-$(CONFIG_SPI_PXA2XX_DMA) += spi-pxa2xx-dma.o 59spi-pxa2xx-platform-$(CONFIG_SPI_PXA2XX_DMA) += spi-pxa2xx-dma.o
60obj-$(CONFIG_SPI_PXA2XX) += spi-pxa2xx-platform.o 60obj-$(CONFIG_SPI_PXA2XX) += spi-pxa2xx-platform.o
61obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa2xx-pci.o 61obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa2xx-pci.o
62obj-$(CONFIG_SPI_QUP) += spi-qup.o
62obj-$(CONFIG_SPI_RSPI) += spi-rspi.o 63obj-$(CONFIG_SPI_RSPI) += spi-rspi.o
63obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o 64obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o
64spi-s3c24xx-hw-y := spi-s3c24xx.o 65spi-s3c24xx-hw-y := spi-s3c24xx.o
diff --git a/drivers/spi/spi-altera.c b/drivers/spi/spi-altera.c
index 5d7deaf62867..5b5709a5c957 100644
--- a/drivers/spi/spi-altera.c
+++ b/drivers/spi/spi-altera.c
@@ -13,7 +13,6 @@
13 * published by the Free Software Foundation. 13 * published by the Free Software Foundation.
14 */ 14 */
15 15
16#include <linux/init.h>
17#include <linux/interrupt.h> 16#include <linux/interrupt.h>
18#include <linux/errno.h> 17#include <linux/errno.h>
19#include <linux/module.h> 18#include <linux/module.h>
@@ -200,7 +199,6 @@ static irqreturn_t altera_spi_irq(int irq, void *dev)
200 199
201static int altera_spi_probe(struct platform_device *pdev) 200static int altera_spi_probe(struct platform_device *pdev)
202{ 201{
203 struct altera_spi_platform_data *platp = dev_get_platdata(&pdev->dev);
204 struct altera_spi *hw; 202 struct altera_spi *hw;
205 struct spi_master *master; 203 struct spi_master *master;
206 struct resource *res; 204 struct resource *res;
@@ -214,6 +212,8 @@ static int altera_spi_probe(struct platform_device *pdev)
214 master->bus_num = pdev->id; 212 master->bus_num = pdev->id;
215 master->num_chipselect = 16; 213 master->num_chipselect = 16;
216 master->mode_bits = SPI_CS_HIGH; 214 master->mode_bits = SPI_CS_HIGH;
215 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 16);
216 master->dev.of_node = pdev->dev.of_node;
217 217
218 hw = spi_master_get_devdata(master); 218 hw = spi_master_get_devdata(master);
219 platform_set_drvdata(pdev, hw); 219 platform_set_drvdata(pdev, hw);
@@ -245,9 +245,6 @@ static int altera_spi_probe(struct platform_device *pdev)
245 if (err) 245 if (err)
246 goto exit; 246 goto exit;
247 } 247 }
248 /* find platform data */
249 if (!platp)
250 hw->bitbang.master->dev.of_node = pdev->dev.of_node;
251 248
252 /* register our spi controller */ 249 /* register our spi controller */
253 err = spi_bitbang_start(&hw->bitbang); 250 err = spi_bitbang_start(&hw->bitbang);
diff --git a/drivers/spi/spi-ath79.c b/drivers/spi/spi-ath79.c
index 31534b51715a..3898b0b9ee77 100644
--- a/drivers/spi/spi-ath79.c
+++ b/drivers/spi/spi-ath79.c
@@ -14,7 +14,6 @@
14 14
15#include <linux/kernel.h> 15#include <linux/kernel.h>
16#include <linux/module.h> 16#include <linux/module.h>
17#include <linux/init.h>
18#include <linux/delay.h> 17#include <linux/delay.h>
19#include <linux/spinlock.h> 18#include <linux/spinlock.h>
20#include <linux/workqueue.h> 19#include <linux/workqueue.h>
@@ -132,9 +131,9 @@ static int ath79_spi_setup_cs(struct spi_device *spi)
132 131
133 flags = GPIOF_DIR_OUT; 132 flags = GPIOF_DIR_OUT;
134 if (spi->mode & SPI_CS_HIGH) 133 if (spi->mode & SPI_CS_HIGH)
135 flags |= GPIOF_INIT_HIGH;
136 else
137 flags |= GPIOF_INIT_LOW; 134 flags |= GPIOF_INIT_LOW;
135 else
136 flags |= GPIOF_INIT_HIGH;
138 137
139 status = gpio_request_one(cdata->gpio, flags, 138 status = gpio_request_one(cdata->gpio, flags,
140 dev_name(&spi->dev)); 139 dev_name(&spi->dev));
diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
index b0842f751016..8005f9869481 100644
--- a/drivers/spi/spi-atmel.c
+++ b/drivers/spi/spi-atmel.c
@@ -9,7 +9,6 @@
9 */ 9 */
10 10
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/clk.h> 12#include <linux/clk.h>
14#include <linux/module.h> 13#include <linux/module.h>
15#include <linux/platform_device.h> 14#include <linux/platform_device.h>
@@ -26,6 +25,7 @@
26 25
27#include <linux/io.h> 26#include <linux/io.h>
28#include <linux/gpio.h> 27#include <linux/gpio.h>
28#include <linux/pinctrl/consumer.h>
29 29
30/* SPI register offsets */ 30/* SPI register offsets */
31#define SPI_CR 0x0000 31#define SPI_CR 0x0000
@@ -993,13 +993,6 @@ static int atmel_spi_setup(struct spi_device *spi)
993 993
994 as = spi_master_get_devdata(spi->master); 994 as = spi_master_get_devdata(spi->master);
995 995
996 if (spi->chip_select > spi->master->num_chipselect) {
997 dev_dbg(&spi->dev,
998 "setup: invalid chipselect %u (%u defined)\n",
999 spi->chip_select, spi->master->num_chipselect);
1000 return -EINVAL;
1001 }
1002
1003 /* see notes above re chipselect */ 996 /* see notes above re chipselect */
1004 if (!atmel_spi_is_v2(as) 997 if (!atmel_spi_is_v2(as)
1005 && spi->chip_select == 0 998 && spi->chip_select == 0
@@ -1087,14 +1080,6 @@ static int atmel_spi_one_transfer(struct spi_master *master,
1087 } 1080 }
1088 } 1081 }
1089 1082
1090 if (xfer->bits_per_word > 8) {
1091 if (xfer->len % 2) {
1092 dev_dbg(&spi->dev,
1093 "buffer len should be 16 bits aligned\n");
1094 return -EINVAL;
1095 }
1096 }
1097
1098 /* 1083 /*
1099 * DMA map early, for performance (empties dcache ASAP) and 1084 * DMA map early, for performance (empties dcache ASAP) and
1100 * better fault reporting. 1085 * better fault reporting.
@@ -1221,9 +1206,6 @@ static int atmel_spi_transfer_one_message(struct spi_master *master,
1221 dev_dbg(&spi->dev, "new message %p submitted for %s\n", 1206 dev_dbg(&spi->dev, "new message %p submitted for %s\n",
1222 msg, dev_name(&spi->dev)); 1207 msg, dev_name(&spi->dev));
1223 1208
1224 if (unlikely(list_empty(&msg->transfers)))
1225 return -EINVAL;
1226
1227 atmel_spi_lock(as); 1209 atmel_spi_lock(as);
1228 cs_activate(as, spi); 1210 cs_activate(as, spi);
1229 1211
@@ -1244,10 +1226,10 @@ static int atmel_spi_transfer_one_message(struct spi_master *master,
1244 1226
1245 list_for_each_entry(xfer, &msg->transfers, transfer_list) { 1227 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1246 dev_dbg(&spi->dev, 1228 dev_dbg(&spi->dev,
1247 " xfer %p: len %u tx %p/%08x rx %p/%08x\n", 1229 " xfer %p: len %u tx %p/%pad rx %p/%pad\n",
1248 xfer, xfer->len, 1230 xfer, xfer->len,
1249 xfer->tx_buf, xfer->tx_dma, 1231 xfer->tx_buf, &xfer->tx_dma,
1250 xfer->rx_buf, xfer->rx_dma); 1232 xfer->rx_buf, &xfer->rx_dma);
1251 } 1233 }
1252 1234
1253msg_done: 1235msg_done:
@@ -1303,6 +1285,9 @@ static int atmel_spi_probe(struct platform_device *pdev)
1303 struct spi_master *master; 1285 struct spi_master *master;
1304 struct atmel_spi *as; 1286 struct atmel_spi *as;
1305 1287
1288 /* Select default pin state */
1289 pinctrl_pm_select_default_state(&pdev->dev);
1290
1306 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1291 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1307 if (!regs) 1292 if (!regs)
1308 return -ENXIO; 1293 return -ENXIO;
@@ -1455,8 +1440,19 @@ static int atmel_spi_suspend(struct device *dev)
1455{ 1440{
1456 struct spi_master *master = dev_get_drvdata(dev); 1441 struct spi_master *master = dev_get_drvdata(dev);
1457 struct atmel_spi *as = spi_master_get_devdata(master); 1442 struct atmel_spi *as = spi_master_get_devdata(master);
1443 int ret;
1444
1445 /* Stop the queue running */
1446 ret = spi_master_suspend(master);
1447 if (ret) {
1448 dev_warn(dev, "cannot suspend master\n");
1449 return ret;
1450 }
1458 1451
1459 clk_disable_unprepare(as->clk); 1452 clk_disable_unprepare(as->clk);
1453
1454 pinctrl_pm_select_sleep_state(dev);
1455
1460 return 0; 1456 return 0;
1461} 1457}
1462 1458
@@ -1464,9 +1460,18 @@ static int atmel_spi_resume(struct device *dev)
1464{ 1460{
1465 struct spi_master *master = dev_get_drvdata(dev); 1461 struct spi_master *master = dev_get_drvdata(dev);
1466 struct atmel_spi *as = spi_master_get_devdata(master); 1462 struct atmel_spi *as = spi_master_get_devdata(master);
1463 int ret;
1464
1465 pinctrl_pm_select_default_state(dev);
1467 1466
1468 clk_prepare_enable(as->clk); 1467 clk_prepare_enable(as->clk);
1469 return 0; 1468
1469 /* Start the queue running */
1470 ret = spi_master_resume(master);
1471 if (ret)
1472 dev_err(dev, "problem starting queue (%d)\n", ret);
1473
1474 return ret;
1470} 1475}
1471 1476
1472static SIMPLE_DEV_PM_OPS(atmel_spi_pm_ops, atmel_spi_suspend, atmel_spi_resume); 1477static SIMPLE_DEV_PM_OPS(atmel_spi_pm_ops, atmel_spi_suspend, atmel_spi_resume);
diff --git a/drivers/spi/spi-au1550.c b/drivers/spi/spi-au1550.c
index c4141c92bcff..aafb812d7ea6 100644
--- a/drivers/spi/spi-au1550.c
+++ b/drivers/spi/spi-au1550.c
@@ -55,8 +55,6 @@ struct au1550_spi {
55 55
56 volatile psc_spi_t __iomem *regs; 56 volatile psc_spi_t __iomem *regs;
57 int irq; 57 int irq;
58 unsigned freq_max;
59 unsigned freq_min;
60 58
61 unsigned len; 59 unsigned len;
62 unsigned tx_count; 60 unsigned tx_count;
@@ -248,11 +246,8 @@ static int au1550_spi_setupxfer(struct spi_device *spi, struct spi_transfer *t)
248 hz = t->speed_hz; 246 hz = t->speed_hz;
249 } 247 }
250 248
251 if (hz > spi->max_speed_hz || hz > hw->freq_max || hz < hw->freq_min) { 249 if (!hz)
252 dev_err(&spi->dev, "setupxfer: clock rate=%d out of range\n",
253 hz);
254 return -EINVAL; 250 return -EINVAL;
255 }
256 251
257 au1550_spi_bits_handlers_set(hw, spi->bits_per_word); 252 au1550_spi_bits_handlers_set(hw, spi->bits_per_word);
258 253
@@ -287,23 +282,6 @@ static int au1550_spi_setupxfer(struct spi_device *spi, struct spi_transfer *t)
287 return 0; 282 return 0;
288} 283}
289 284
290static int au1550_spi_setup(struct spi_device *spi)
291{
292 struct au1550_spi *hw = spi_master_get_devdata(spi->master);
293
294 if (spi->max_speed_hz == 0)
295 spi->max_speed_hz = hw->freq_max;
296 if (spi->max_speed_hz > hw->freq_max
297 || spi->max_speed_hz < hw->freq_min)
298 return -EINVAL;
299 /*
300 * NOTE: cannot change speed and other hw settings immediately,
301 * otherwise sharing of spi bus is not possible,
302 * so do not call setupxfer(spi, NULL) here
303 */
304 return 0;
305}
306
307/* 285/*
308 * for dma spi transfers, we have to setup rx channel, otherwise there is 286 * for dma spi transfers, we have to setup rx channel, otherwise there is
309 * no reliable way how to recognize that spi transfer is done 287 * no reliable way how to recognize that spi transfer is done
@@ -838,7 +816,6 @@ static int au1550_spi_probe(struct platform_device *pdev)
838 hw->bitbang.master = hw->master; 816 hw->bitbang.master = hw->master;
839 hw->bitbang.setup_transfer = au1550_spi_setupxfer; 817 hw->bitbang.setup_transfer = au1550_spi_setupxfer;
840 hw->bitbang.chipselect = au1550_spi_chipsel; 818 hw->bitbang.chipselect = au1550_spi_chipsel;
841 hw->bitbang.master->setup = au1550_spi_setup;
842 hw->bitbang.txrx_bufs = au1550_spi_txrx_bufs; 819 hw->bitbang.txrx_bufs = au1550_spi_txrx_bufs;
843 820
844 if (hw->usedma) { 821 if (hw->usedma) {
@@ -909,8 +886,9 @@ static int au1550_spi_probe(struct platform_device *pdev)
909 { 886 {
910 int min_div = (2 << 0) * (2 * (4 + 1)); 887 int min_div = (2 << 0) * (2 * (4 + 1));
911 int max_div = (2 << 3) * (2 * (63 + 1)); 888 int max_div = (2 << 3) * (2 * (63 + 1));
912 hw->freq_max = hw->pdata->mainclk_hz / min_div; 889 master->max_speed_hz = hw->pdata->mainclk_hz / min_div;
913 hw->freq_min = hw->pdata->mainclk_hz / (max_div + 1) + 1; 890 master->min_speed_hz =
891 hw->pdata->mainclk_hz / (max_div + 1) + 1;
914 } 892 }
915 893
916 au1550_spi_setup_psc_as_spi(hw); 894 au1550_spi_setup_psc_as_spi(hw);
diff --git a/drivers/spi/spi-bcm2835.c b/drivers/spi/spi-bcm2835.c
index 8a89dd1f2654..69167456ec1e 100644
--- a/drivers/spi/spi-bcm2835.c
+++ b/drivers/spi/spi-bcm2835.c
@@ -315,7 +315,6 @@ static int bcm2835_spi_probe(struct platform_device *pdev)
315 315
316 master->mode_bits = BCM2835_SPI_MODE_BITS; 316 master->mode_bits = BCM2835_SPI_MODE_BITS;
317 master->bits_per_word_mask = SPI_BPW_MASK(8); 317 master->bits_per_word_mask = SPI_BPW_MASK(8);
318 master->bus_num = -1;
319 master->num_chipselect = 3; 318 master->num_chipselect = 3;
320 master->transfer_one_message = bcm2835_spi_transfer_one; 319 master->transfer_one_message = bcm2835_spi_transfer_one;
321 master->dev.of_node = pdev->dev.of_node; 320 master->dev.of_node = pdev->dev.of_node;
diff --git a/drivers/spi/spi-bcm63xx-hsspi.c b/drivers/spi/spi-bcm63xx-hsspi.c
index b528f9fc8bc0..5a211e98383b 100644
--- a/drivers/spi/spi-bcm63xx-hsspi.c
+++ b/drivers/spi/spi-bcm63xx-hsspi.c
@@ -180,7 +180,7 @@ static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t)
180 while (pending > 0) { 180 while (pending > 0) {
181 int curr_step = min_t(int, step_size, pending); 181 int curr_step = min_t(int, step_size, pending);
182 182
183 init_completion(&bs->done); 183 reinit_completion(&bs->done);
184 if (tx) { 184 if (tx) {
185 memcpy_toio(bs->fifo + HSSPI_OPCODE_LEN, tx, curr_step); 185 memcpy_toio(bs->fifo + HSSPI_OPCODE_LEN, tx, curr_step);
186 tx += curr_step; 186 tx += curr_step;
@@ -369,6 +369,7 @@ static int bcm63xx_hsspi_probe(struct platform_device *pdev)
369 bs->fifo = (u8 __iomem *)(bs->regs + HSSPI_FIFO_REG(0)); 369 bs->fifo = (u8 __iomem *)(bs->regs + HSSPI_FIFO_REG(0));
370 370
371 mutex_init(&bs->bus_mutex); 371 mutex_init(&bs->bus_mutex);
372 init_completion(&bs->done);
372 373
373 master->bus_num = HSSPI_BUS_NUM; 374 master->bus_num = HSSPI_BUS_NUM;
374 master->num_chipselect = 8; 375 master->num_chipselect = 8;
@@ -453,9 +454,8 @@ static int bcm63xx_hsspi_resume(struct device *dev)
453} 454}
454#endif 455#endif
455 456
456static const struct dev_pm_ops bcm63xx_hsspi_pm_ops = { 457static SIMPLE_DEV_PM_OPS(bcm63xx_hsspi_pm_ops, bcm63xx_hsspi_suspend,
457 SET_SYSTEM_SLEEP_PM_OPS(bcm63xx_hsspi_suspend, bcm63xx_hsspi_resume) 458 bcm63xx_hsspi_resume);
458};
459 459
460static struct platform_driver bcm63xx_hsspi_driver = { 460static struct platform_driver bcm63xx_hsspi_driver = {
461 .driver = { 461 .driver = {
diff --git a/drivers/spi/spi-bcm63xx.c b/drivers/spi/spi-bcm63xx.c
index 77286aef2adf..0250fa721cea 100644
--- a/drivers/spi/spi-bcm63xx.c
+++ b/drivers/spi/spi-bcm63xx.c
@@ -20,7 +20,6 @@
20 */ 20 */
21 21
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/init.h>
24#include <linux/clk.h> 23#include <linux/clk.h>
25#include <linux/io.h> 24#include <linux/io.h>
26#include <linux/module.h> 25#include <linux/module.h>
@@ -35,8 +34,6 @@
35 34
36#include <bcm63xx_dev_spi.h> 35#include <bcm63xx_dev_spi.h>
37 36
38#define PFX KBUILD_MODNAME
39
40#define BCM63XX_SPI_MAX_PREPEND 15 37#define BCM63XX_SPI_MAX_PREPEND 15
41 38
42struct bcm63xx_spi { 39struct bcm63xx_spi {
@@ -169,7 +166,7 @@ static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *first,
169 transfer_list); 166 transfer_list);
170 } 167 }
171 168
172 init_completion(&bs->done); 169 reinit_completion(&bs->done);
173 170
174 /* Fill in the Message control register */ 171 /* Fill in the Message control register */
175 msg_ctl = (len << SPI_BYTE_CNT_SHIFT); 172 msg_ctl = (len << SPI_BYTE_CNT_SHIFT);
@@ -353,6 +350,7 @@ static int bcm63xx_spi_probe(struct platform_device *pdev)
353 } 350 }
354 351
355 bs = spi_master_get_devdata(master); 352 bs = spi_master_get_devdata(master);
353 init_completion(&bs->done);
356 354
357 platform_set_drvdata(pdev, master); 355 platform_set_drvdata(pdev, master);
358 bs->pdev = pdev; 356 bs->pdev = pdev;
diff --git a/drivers/spi/spi-bfin-sport.c b/drivers/spi/spi-bfin-sport.c
index 38941e5920b5..f515c5e9db57 100644
--- a/drivers/spi/spi-bfin-sport.c
+++ b/drivers/spi/spi-bfin-sport.c
@@ -8,7 +8,6 @@
8 * Licensed under the GPL-2 or later. 8 * Licensed under the GPL-2 or later.
9 */ 9 */
10 10
11#include <linux/init.h>
12#include <linux/module.h> 11#include <linux/module.h>
13#include <linux/delay.h> 12#include <linux/delay.h>
14#include <linux/device.h> 13#include <linux/device.h>
diff --git a/drivers/spi/spi-bfin-v3.c b/drivers/spi/spi-bfin-v3.c
index 8f8598834b30..4089d0e0d84e 100644
--- a/drivers/spi/spi-bfin-v3.c
+++ b/drivers/spi/spi-bfin-v3.c
@@ -822,7 +822,8 @@ static int bfin_spi_probe(struct platform_device *pdev)
822 master->cleanup = bfin_spi_cleanup; 822 master->cleanup = bfin_spi_cleanup;
823 master->setup = bfin_spi_setup; 823 master->setup = bfin_spi_setup;
824 master->transfer_one_message = bfin_spi_transfer_one_message; 824 master->transfer_one_message = bfin_spi_transfer_one_message;
825 master->bits_per_word_mask = BIT(32 - 1) | BIT(16 - 1) | BIT(8 - 1); 825 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
826 SPI_BPW_MASK(8);
826 827
827 drv_data = spi_master_get_devdata(master); 828 drv_data = spi_master_get_devdata(master);
828 drv_data->master = master; 829 drv_data->master = master;
diff --git a/drivers/spi/spi-bfin5xx.c b/drivers/spi/spi-bfin5xx.c
index f0f195af75d4..55e57c3eb9bd 100644
--- a/drivers/spi/spi-bfin5xx.c
+++ b/drivers/spi/spi-bfin5xx.c
@@ -350,7 +350,6 @@ static void *bfin_spi_next_transfer(struct bfin_spi_master_data *drv_data)
350static void bfin_spi_giveback(struct bfin_spi_master_data *drv_data) 350static void bfin_spi_giveback(struct bfin_spi_master_data *drv_data)
351{ 351{
352 struct bfin_spi_slave_data *chip = drv_data->cur_chip; 352 struct bfin_spi_slave_data *chip = drv_data->cur_chip;
353 struct spi_transfer *last_transfer;
354 unsigned long flags; 353 unsigned long flags;
355 struct spi_message *msg; 354 struct spi_message *msg;
356 355
@@ -362,9 +361,6 @@ static void bfin_spi_giveback(struct bfin_spi_master_data *drv_data)
362 queue_work(drv_data->workqueue, &drv_data->pump_messages); 361 queue_work(drv_data->workqueue, &drv_data->pump_messages);
363 spin_unlock_irqrestore(&drv_data->lock, flags); 362 spin_unlock_irqrestore(&drv_data->lock, flags);
364 363
365 last_transfer = list_entry(msg->transfers.prev,
366 struct spi_transfer, transfer_list);
367
368 msg->state = NULL; 364 msg->state = NULL;
369 365
370 if (!drv_data->cs_change) 366 if (!drv_data->cs_change)
@@ -1030,10 +1026,6 @@ static int bfin_spi_setup(struct spi_device *spi)
1030 } 1026 }
1031 1027
1032 /* translate common spi framework into our register */ 1028 /* translate common spi framework into our register */
1033 if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) {
1034 dev_err(&spi->dev, "unsupported spi modes detected\n");
1035 goto error;
1036 }
1037 if (spi->mode & SPI_CPOL) 1029 if (spi->mode & SPI_CPOL)
1038 chip->ctl_reg |= BIT_CTL_CPOL; 1030 chip->ctl_reg |= BIT_CTL_CPOL;
1039 if (spi->mode & SPI_CPHA) 1031 if (spi->mode & SPI_CPHA)
diff --git a/drivers/spi/spi-bitbang.c b/drivers/spi/spi-bitbang.c
index bd222f6b677d..dc7d2c2d643e 100644
--- a/drivers/spi/spi-bitbang.c
+++ b/drivers/spi/spi-bitbang.c
@@ -16,7 +16,6 @@
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */ 17 */
18 18
19#include <linux/init.h>
20#include <linux/spinlock.h> 19#include <linux/spinlock.h>
21#include <linux/workqueue.h> 20#include <linux/workqueue.h>
22#include <linux/interrupt.h> 21#include <linux/interrupt.h>
@@ -467,11 +466,9 @@ EXPORT_SYMBOL_GPL(spi_bitbang_start);
467/** 466/**
468 * spi_bitbang_stop - stops the task providing spi communication 467 * spi_bitbang_stop - stops the task providing spi communication
469 */ 468 */
470int spi_bitbang_stop(struct spi_bitbang *bitbang) 469void spi_bitbang_stop(struct spi_bitbang *bitbang)
471{ 470{
472 spi_unregister_master(bitbang->master); 471 spi_unregister_master(bitbang->master);
473
474 return 0;
475} 472}
476EXPORT_SYMBOL_GPL(spi_bitbang_stop); 473EXPORT_SYMBOL_GPL(spi_bitbang_stop);
477 474
diff --git a/drivers/spi/spi-butterfly.c b/drivers/spi/spi-butterfly.c
index 8081f96bd1d5..ee4f91ccd8fd 100644
--- a/drivers/spi/spi-butterfly.c
+++ b/drivers/spi/spi-butterfly.c
@@ -309,7 +309,6 @@ done:
309static void butterfly_detach(struct parport *p) 309static void butterfly_detach(struct parport *p)
310{ 310{
311 struct butterfly *pp; 311 struct butterfly *pp;
312 int status;
313 312
314 /* FIXME this global is ugly ... but, how to quickly get from 313 /* FIXME this global is ugly ... but, how to quickly get from
315 * the parport to the "struct butterfly" associated with it? 314 * the parport to the "struct butterfly" associated with it?
@@ -321,7 +320,7 @@ static void butterfly_detach(struct parport *p)
321 butterfly = NULL; 320 butterfly = NULL;
322 321
323 /* stop() unregisters child devices too */ 322 /* stop() unregisters child devices too */
324 status = spi_bitbang_stop(&pp->bitbang); 323 spi_bitbang_stop(&pp->bitbang);
325 324
326 /* turn off VCC */ 325 /* turn off VCC */
327 parport_write_data(pp->port, 0); 326 parport_write_data(pp->port, 0);
diff --git a/drivers/spi/spi-clps711x.c b/drivers/spi/spi-clps711x.c
index 374ba4a48a9e..4cd62f636547 100644
--- a/drivers/spi/spi-clps711x.c
+++ b/drivers/spi/spi-clps711x.c
@@ -11,158 +11,125 @@
11 11
12#include <linux/io.h> 12#include <linux/io.h>
13#include <linux/clk.h> 13#include <linux/clk.h>
14#include <linux/init.h>
15#include <linux/gpio.h> 14#include <linux/gpio.h>
16#include <linux/delay.h> 15#include <linux/delay.h>
17#include <linux/module.h> 16#include <linux/module.h>
18#include <linux/interrupt.h> 17#include <linux/interrupt.h>
19#include <linux/platform_device.h> 18#include <linux/platform_device.h>
19#include <linux/regmap.h>
20#include <linux/mfd/syscon.h>
21#include <linux/mfd/syscon/clps711x.h>
20#include <linux/spi/spi.h> 22#include <linux/spi/spi.h>
21#include <linux/platform_data/spi-clps711x.h> 23#include <linux/platform_data/spi-clps711x.h>
22 24
23#include <mach/hardware.h>
24
25#define DRIVER_NAME "spi-clps711x" 25#define DRIVER_NAME "spi-clps711x"
26 26
27struct spi_clps711x_data { 27#define SYNCIO_FRMLEN(x) ((x) << 8)
28 struct completion done; 28#define SYNCIO_TXFRMEN (1 << 14)
29 29
30struct spi_clps711x_data {
31 void __iomem *syncio;
32 struct regmap *syscon;
33 struct regmap *syscon1;
30 struct clk *spi_clk; 34 struct clk *spi_clk;
31 u32 max_speed_hz;
32 35
33 u8 *tx_buf; 36 u8 *tx_buf;
34 u8 *rx_buf; 37 u8 *rx_buf;
35 int count; 38 unsigned int bpw;
36 int len; 39 int len;
37
38 int chipselect[0];
39}; 40};
40 41
41static int spi_clps711x_setup(struct spi_device *spi) 42static int spi_clps711x_setup(struct spi_device *spi)
42{ 43{
43 struct spi_clps711x_data *hw = spi_master_get_devdata(spi->master);
44
45 /* We are expect that SPI-device is not selected */ 44 /* We are expect that SPI-device is not selected */
46 gpio_direction_output(hw->chipselect[spi->chip_select], 45 gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
47 !(spi->mode & SPI_CS_HIGH));
48 46
49 return 0; 47 return 0;
50} 48}
51 49
52static void spi_clps711x_setup_mode(struct spi_device *spi) 50static void spi_clps711x_setup_xfer(struct spi_device *spi,
53{ 51 struct spi_transfer *xfer)
54 /* Setup edge for transfer */
55 if (spi->mode & SPI_CPHA)
56 clps_writew(clps_readw(SYSCON3) | SYSCON3_ADCCKNSEN, SYSCON3);
57 else
58 clps_writew(clps_readw(SYSCON3) & ~SYSCON3_ADCCKNSEN, SYSCON3);
59}
60
61static int spi_clps711x_setup_xfer(struct spi_device *spi,
62 struct spi_transfer *xfer)
63{ 52{
64 u32 speed = xfer->speed_hz ? : spi->max_speed_hz; 53 struct spi_master *master = spi->master;
65 u8 bpw = xfer->bits_per_word; 54 struct spi_clps711x_data *hw = spi_master_get_devdata(master);
66 struct spi_clps711x_data *hw = spi_master_get_devdata(spi->master);
67
68 if (bpw != 8) {
69 dev_err(&spi->dev, "Unsupported master bus width %i\n", bpw);
70 return -EINVAL;
71 }
72 55
73 /* Setup SPI frequency divider */ 56 /* Setup SPI frequency divider */
74 if (!speed || (speed >= hw->max_speed_hz)) 57 if (xfer->speed_hz >= master->max_speed_hz)
75 clps_writel((clps_readl(SYSCON1) & ~SYSCON1_ADCKSEL_MASK) | 58 regmap_update_bits(hw->syscon1, SYSCON_OFFSET,
76 SYSCON1_ADCKSEL(3), SYSCON1); 59 SYSCON1_ADCKSEL_MASK, SYSCON1_ADCKSEL(3));
77 else if (speed >= (hw->max_speed_hz / 2)) 60 else if (xfer->speed_hz >= (master->max_speed_hz / 2))
78 clps_writel((clps_readl(SYSCON1) & ~SYSCON1_ADCKSEL_MASK) | 61 regmap_update_bits(hw->syscon1, SYSCON_OFFSET,
79 SYSCON1_ADCKSEL(2), SYSCON1); 62 SYSCON1_ADCKSEL_MASK, SYSCON1_ADCKSEL(2));
80 else if (speed >= (hw->max_speed_hz / 8)) 63 else if (xfer->speed_hz >= (master->max_speed_hz / 8))
81 clps_writel((clps_readl(SYSCON1) & ~SYSCON1_ADCKSEL_MASK) | 64 regmap_update_bits(hw->syscon1, SYSCON_OFFSET,
82 SYSCON1_ADCKSEL(1), SYSCON1); 65 SYSCON1_ADCKSEL_MASK, SYSCON1_ADCKSEL(1));
83 else 66 else
84 clps_writel((clps_readl(SYSCON1) & ~SYSCON1_ADCKSEL_MASK) | 67 regmap_update_bits(hw->syscon1, SYSCON_OFFSET,
85 SYSCON1_ADCKSEL(0), SYSCON1); 68 SYSCON1_ADCKSEL_MASK, SYSCON1_ADCKSEL(0));
86
87 return 0;
88} 69}
89 70
90static int spi_clps711x_transfer_one_message(struct spi_master *master, 71static int spi_clps711x_prepare_message(struct spi_master *master,
91 struct spi_message *msg) 72 struct spi_message *msg)
92{ 73{
93 struct spi_clps711x_data *hw = spi_master_get_devdata(master); 74 struct spi_clps711x_data *hw = spi_master_get_devdata(master);
94 struct spi_transfer *xfer; 75 struct spi_device *spi = msg->spi;
95 int status = 0, cs = hw->chipselect[msg->spi->chip_select];
96 u32 data;
97
98 spi_clps711x_setup_mode(msg->spi);
99
100 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
101 if (spi_clps711x_setup_xfer(msg->spi, xfer)) {
102 status = -EINVAL;
103 goto out_xfr;
104 }
105 76
106 gpio_set_value(cs, !!(msg->spi->mode & SPI_CS_HIGH)); 77 /* Setup mode for transfer */
107 78 return regmap_update_bits(hw->syscon, SYSCON_OFFSET, SYSCON3_ADCCKNSEN,
108 reinit_completion(&hw->done); 79 (spi->mode & SPI_CPHA) ?
109 80 SYSCON3_ADCCKNSEN : 0);
110 hw->count = 0; 81}
111 hw->len = xfer->len;
112 hw->tx_buf = (u8 *)xfer->tx_buf;
113 hw->rx_buf = (u8 *)xfer->rx_buf;
114
115 /* Initiate transfer */
116 data = hw->tx_buf ? hw->tx_buf[hw->count] : 0;
117 clps_writel(data | SYNCIO_FRMLEN(8) | SYNCIO_TXFRMEN, SYNCIO);
118
119 wait_for_completion(&hw->done);
120 82
121 if (xfer->delay_usecs) 83static int spi_clps711x_transfer_one(struct spi_master *master,
122 udelay(xfer->delay_usecs); 84 struct spi_device *spi,
85 struct spi_transfer *xfer)
86{
87 struct spi_clps711x_data *hw = spi_master_get_devdata(master);
88 u8 data;
123 89
124 if (xfer->cs_change || 90 spi_clps711x_setup_xfer(spi, xfer);
125 list_is_last(&xfer->transfer_list, &msg->transfers))
126 gpio_set_value(cs, !(msg->spi->mode & SPI_CS_HIGH));
127 91
128 msg->actual_length += xfer->len; 92 hw->len = xfer->len;
129 } 93 hw->bpw = xfer->bits_per_word;
94 hw->tx_buf = (u8 *)xfer->tx_buf;
95 hw->rx_buf = (u8 *)xfer->rx_buf;
130 96
131out_xfr: 97 /* Initiate transfer */
132 msg->status = status; 98 data = hw->tx_buf ? *hw->tx_buf++ : 0;
133 spi_finalize_current_message(master); 99 writel(data | SYNCIO_FRMLEN(hw->bpw) | SYNCIO_TXFRMEN, hw->syncio);
134 100
135 return 0; 101 return 1;
136} 102}
137 103
138static irqreturn_t spi_clps711x_isr(int irq, void *dev_id) 104static irqreturn_t spi_clps711x_isr(int irq, void *dev_id)
139{ 105{
140 struct spi_clps711x_data *hw = (struct spi_clps711x_data *)dev_id; 106 struct spi_master *master = dev_id;
141 u32 data; 107 struct spi_clps711x_data *hw = spi_master_get_devdata(master);
108 u8 data;
142 109
143 /* Handle RX */ 110 /* Handle RX */
144 data = clps_readb(SYNCIO); 111 data = readb(hw->syncio);
145 if (hw->rx_buf) 112 if (hw->rx_buf)
146 hw->rx_buf[hw->count] = (u8)data; 113 *hw->rx_buf++ = data;
147
148 hw->count++;
149 114
150 /* Handle TX */ 115 /* Handle TX */
151 if (hw->count < hw->len) { 116 if (--hw->len > 0) {
152 data = hw->tx_buf ? hw->tx_buf[hw->count] : 0; 117 data = hw->tx_buf ? *hw->tx_buf++ : 0;
153 clps_writel(data | SYNCIO_FRMLEN(8) | SYNCIO_TXFRMEN, SYNCIO); 118 writel(data | SYNCIO_FRMLEN(hw->bpw) | SYNCIO_TXFRMEN,
119 hw->syncio);
154 } else 120 } else
155 complete(&hw->done); 121 spi_finalize_current_transfer(master);
156 122
157 return IRQ_HANDLED; 123 return IRQ_HANDLED;
158} 124}
159 125
160static int spi_clps711x_probe(struct platform_device *pdev) 126static int spi_clps711x_probe(struct platform_device *pdev)
161{ 127{
162 int i, ret;
163 struct spi_master *master;
164 struct spi_clps711x_data *hw; 128 struct spi_clps711x_data *hw;
165 struct spi_clps711x_pdata *pdata = dev_get_platdata(&pdev->dev); 129 struct spi_clps711x_pdata *pdata = dev_get_platdata(&pdev->dev);
130 struct spi_master *master;
131 struct resource *res;
132 int i, irq, ret;
166 133
167 if (!pdata) { 134 if (!pdata) {
168 dev_err(&pdev->dev, "No platform data supplied\n"); 135 dev_err(&pdev->dev, "No platform data supplied\n");
@@ -174,33 +141,37 @@ static int spi_clps711x_probe(struct platform_device *pdev)
174 return -EINVAL; 141 return -EINVAL;
175 } 142 }
176 143
177 master = spi_alloc_master(&pdev->dev, 144 irq = platform_get_irq(pdev, 0);
178 sizeof(struct spi_clps711x_data) + 145 if (irq < 0)
179 sizeof(int) * pdata->num_chipselect); 146 return irq;
180 if (!master) { 147
181 dev_err(&pdev->dev, "SPI allocating memory error\n"); 148 master = spi_alloc_master(&pdev->dev, sizeof(*hw));
149 if (!master)
182 return -ENOMEM; 150 return -ENOMEM;
151
152 master->cs_gpios = devm_kzalloc(&pdev->dev, sizeof(int) *
153 pdata->num_chipselect, GFP_KERNEL);
154 if (!master->cs_gpios) {
155 ret = -ENOMEM;
156 goto err_out;
183 } 157 }
184 158
185 master->bus_num = pdev->id; 159 master->bus_num = pdev->id;
186 master->mode_bits = SPI_CPHA | SPI_CS_HIGH; 160 master->mode_bits = SPI_CPHA | SPI_CS_HIGH;
187 master->bits_per_word_mask = SPI_BPW_MASK(8); 161 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 8);
188 master->num_chipselect = pdata->num_chipselect; 162 master->num_chipselect = pdata->num_chipselect;
189 master->setup = spi_clps711x_setup; 163 master->setup = spi_clps711x_setup;
190 master->transfer_one_message = spi_clps711x_transfer_one_message; 164 master->prepare_message = spi_clps711x_prepare_message;
165 master->transfer_one = spi_clps711x_transfer_one;
191 166
192 hw = spi_master_get_devdata(master); 167 hw = spi_master_get_devdata(master);
193 168
194 for (i = 0; i < master->num_chipselect; i++) { 169 for (i = 0; i < master->num_chipselect; i++) {
195 hw->chipselect[i] = pdata->chipselect[i]; 170 master->cs_gpios[i] = pdata->chipselect[i];
196 if (!gpio_is_valid(hw->chipselect[i])) { 171 ret = devm_gpio_request(&pdev->dev, master->cs_gpios[i],
197 dev_err(&pdev->dev, "Invalid CS GPIO %i\n", i); 172 DRIVER_NAME);
198 ret = -EINVAL; 173 if (ret) {
199 goto err_out;
200 }
201 if (devm_gpio_request(&pdev->dev, hw->chipselect[i], NULL)) {
202 dev_err(&pdev->dev, "Can't get CS GPIO %i\n", i); 174 dev_err(&pdev->dev, "Can't get CS GPIO %i\n", i);
203 ret = -EINVAL;
204 goto err_out; 175 goto err_out;
205 } 176 }
206 } 177 }
@@ -211,29 +182,45 @@ static int spi_clps711x_probe(struct platform_device *pdev)
211 ret = PTR_ERR(hw->spi_clk); 182 ret = PTR_ERR(hw->spi_clk);
212 goto err_out; 183 goto err_out;
213 } 184 }
214 hw->max_speed_hz = clk_get_rate(hw->spi_clk); 185 master->max_speed_hz = clk_get_rate(hw->spi_clk);
215 186
216 init_completion(&hw->done);
217 platform_set_drvdata(pdev, master); 187 platform_set_drvdata(pdev, master);
218 188
189 hw->syscon = syscon_regmap_lookup_by_pdevname("syscon.3");
190 if (IS_ERR(hw->syscon)) {
191 ret = PTR_ERR(hw->syscon);
192 goto err_out;
193 }
194
195 hw->syscon1 = syscon_regmap_lookup_by_pdevname("syscon.1");
196 if (IS_ERR(hw->syscon1)) {
197 ret = PTR_ERR(hw->syscon1);
198 goto err_out;
199 }
200
201 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
202 hw->syncio = devm_ioremap_resource(&pdev->dev, res);
203 if (IS_ERR(hw->syncio)) {
204 ret = PTR_ERR(hw->syncio);
205 goto err_out;
206 }
207
219 /* Disable extended mode due hardware problems */ 208 /* Disable extended mode due hardware problems */
220 clps_writew(clps_readw(SYSCON3) & ~SYSCON3_ADCCON, SYSCON3); 209 regmap_update_bits(hw->syscon, SYSCON_OFFSET, SYSCON3_ADCCON, 0);
221 210
222 /* Clear possible pending interrupt */ 211 /* Clear possible pending interrupt */
223 clps_readl(SYNCIO); 212 readl(hw->syncio);
224 213
225 ret = devm_request_irq(&pdev->dev, IRQ_SSEOTI, spi_clps711x_isr, 0, 214 ret = devm_request_irq(&pdev->dev, irq, spi_clps711x_isr, 0,
226 dev_name(&pdev->dev), hw); 215 dev_name(&pdev->dev), master);
227 if (ret) { 216 if (ret)
228 dev_err(&pdev->dev, "Can't request IRQ\n");
229 goto err_out; 217 goto err_out;
230 }
231 218
232 ret = devm_spi_register_master(&pdev->dev, master); 219 ret = devm_spi_register_master(&pdev->dev, master);
233 if (!ret) { 220 if (!ret) {
234 dev_info(&pdev->dev, 221 dev_info(&pdev->dev,
235 "SPI bus driver initialized. Master clock %u Hz\n", 222 "SPI bus driver initialized. Master clock %u Hz\n",
236 hw->max_speed_hz); 223 master->max_speed_hz);
237 return 0; 224 return 0;
238 } 225 }
239 226
diff --git a/drivers/spi/spi-coldfire-qspi.c b/drivers/spi/spi-coldfire-qspi.c
index cabed8f9119e..e2fa628e55e7 100644
--- a/drivers/spi/spi-coldfire-qspi.c
+++ b/drivers/spi/spi-coldfire-qspi.c
@@ -77,8 +77,6 @@ struct mcfqspi {
77 struct mcfqspi_cs_control *cs_control; 77 struct mcfqspi_cs_control *cs_control;
78 78
79 wait_queue_head_t waitq; 79 wait_queue_head_t waitq;
80
81 struct device *dev;
82}; 80};
83 81
84static void mcfqspi_wr_qmr(struct mcfqspi *mcfqspi, u16 val) 82static void mcfqspi_wr_qmr(struct mcfqspi *mcfqspi, u16 val)
@@ -135,13 +133,13 @@ static void mcfqspi_cs_deselect(struct mcfqspi *mcfqspi, u8 chip_select,
135 133
136static int mcfqspi_cs_setup(struct mcfqspi *mcfqspi) 134static int mcfqspi_cs_setup(struct mcfqspi *mcfqspi)
137{ 135{
138 return (mcfqspi->cs_control && mcfqspi->cs_control->setup) ? 136 return (mcfqspi->cs_control->setup) ?
139 mcfqspi->cs_control->setup(mcfqspi->cs_control) : 0; 137 mcfqspi->cs_control->setup(mcfqspi->cs_control) : 0;
140} 138}
141 139
142static void mcfqspi_cs_teardown(struct mcfqspi *mcfqspi) 140static void mcfqspi_cs_teardown(struct mcfqspi *mcfqspi)
143{ 141{
144 if (mcfqspi->cs_control && mcfqspi->cs_control->teardown) 142 if (mcfqspi->cs_control->teardown)
145 mcfqspi->cs_control->teardown(mcfqspi->cs_control); 143 mcfqspi->cs_control->teardown(mcfqspi->cs_control);
146} 144}
147 145
@@ -300,68 +298,45 @@ static void mcfqspi_transfer_msg16(struct mcfqspi *mcfqspi, unsigned count,
300 } 298 }
301} 299}
302 300
303static int mcfqspi_transfer_one_message(struct spi_master *master, 301static void mcfqspi_set_cs(struct spi_device *spi, bool enable)
304 struct spi_message *msg)
305{ 302{
306 struct mcfqspi *mcfqspi = spi_master_get_devdata(master); 303 struct mcfqspi *mcfqspi = spi_master_get_devdata(spi->master);
307 struct spi_device *spi = msg->spi; 304 bool cs_high = spi->mode & SPI_CS_HIGH;
308 struct spi_transfer *t;
309 int status = 0;
310
311 list_for_each_entry(t, &msg->transfers, transfer_list) {
312 bool cs_high = spi->mode & SPI_CS_HIGH;
313 u16 qmr = MCFQSPI_QMR_MSTR;
314
315 qmr |= t->bits_per_word << 10;
316 if (spi->mode & SPI_CPHA)
317 qmr |= MCFQSPI_QMR_CPHA;
318 if (spi->mode & SPI_CPOL)
319 qmr |= MCFQSPI_QMR_CPOL;
320 if (t->speed_hz)
321 qmr |= mcfqspi_qmr_baud(t->speed_hz);
322 else
323 qmr |= mcfqspi_qmr_baud(spi->max_speed_hz);
324 mcfqspi_wr_qmr(mcfqspi, qmr);
325 305
306 if (enable)
326 mcfqspi_cs_select(mcfqspi, spi->chip_select, cs_high); 307 mcfqspi_cs_select(mcfqspi, spi->chip_select, cs_high);
308 else
309 mcfqspi_cs_deselect(mcfqspi, spi->chip_select, cs_high);
310}
327 311
328 mcfqspi_wr_qir(mcfqspi, MCFQSPI_QIR_SPIFE); 312static int mcfqspi_transfer_one(struct spi_master *master,
329 if (t->bits_per_word == 8) 313 struct spi_device *spi,
330 mcfqspi_transfer_msg8(mcfqspi, t->len, t->tx_buf, 314 struct spi_transfer *t)
331 t->rx_buf); 315{
332 else 316 struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
333 mcfqspi_transfer_msg16(mcfqspi, t->len / 2, t->tx_buf, 317 u16 qmr = MCFQSPI_QMR_MSTR;
334 t->rx_buf); 318
335 mcfqspi_wr_qir(mcfqspi, 0); 319 qmr |= t->bits_per_word << 10;
336 320 if (spi->mode & SPI_CPHA)
337 if (t->delay_usecs) 321 qmr |= MCFQSPI_QMR_CPHA;
338 udelay(t->delay_usecs); 322 if (spi->mode & SPI_CPOL)
339 if (t->cs_change) { 323 qmr |= MCFQSPI_QMR_CPOL;
340 if (!list_is_last(&t->transfer_list, &msg->transfers)) 324 qmr |= mcfqspi_qmr_baud(t->speed_hz);
341 mcfqspi_cs_deselect(mcfqspi, spi->chip_select, 325 mcfqspi_wr_qmr(mcfqspi, qmr);
342 cs_high); 326
343 } else { 327 mcfqspi_wr_qir(mcfqspi, MCFQSPI_QIR_SPIFE);
344 if (list_is_last(&t->transfer_list, &msg->transfers)) 328 if (t->bits_per_word == 8)
345 mcfqspi_cs_deselect(mcfqspi, spi->chip_select, 329 mcfqspi_transfer_msg8(mcfqspi, t->len, t->tx_buf, t->rx_buf);
346 cs_high); 330 else
347 } 331 mcfqspi_transfer_msg16(mcfqspi, t->len / 2, t->tx_buf,
348 msg->actual_length += t->len; 332 t->rx_buf);
349 } 333 mcfqspi_wr_qir(mcfqspi, 0);
350 msg->status = status;
351 spi_finalize_current_message(master);
352
353 return status;
354 334
335 return 0;
355} 336}
356 337
357static int mcfqspi_setup(struct spi_device *spi) 338static int mcfqspi_setup(struct spi_device *spi)
358{ 339{
359 if (spi->chip_select >= spi->master->num_chipselect) {
360 dev_dbg(&spi->dev, "%d chip select is out of range\n",
361 spi->chip_select);
362 return -EINVAL;
363 }
364
365 mcfqspi_cs_deselect(spi_master_get_devdata(spi->master), 340 mcfqspi_cs_deselect(spi_master_get_devdata(spi->master),
366 spi->chip_select, spi->mode & SPI_CS_HIGH); 341 spi->chip_select, spi->mode & SPI_CS_HIGH);
367 342
@@ -388,6 +363,11 @@ static int mcfqspi_probe(struct platform_device *pdev)
388 return -ENOENT; 363 return -ENOENT;
389 } 364 }
390 365
366 if (!pdata->cs_control) {
367 dev_dbg(&pdev->dev, "pdata->cs_control is NULL\n");
368 return -EINVAL;
369 }
370
391 master = spi_alloc_master(&pdev->dev, sizeof(*mcfqspi)); 371 master = spi_alloc_master(&pdev->dev, sizeof(*mcfqspi));
392 if (master == NULL) { 372 if (master == NULL) {
393 dev_dbg(&pdev->dev, "spi_alloc_master failed\n"); 373 dev_dbg(&pdev->dev, "spi_alloc_master failed\n");
@@ -436,12 +416,12 @@ static int mcfqspi_probe(struct platform_device *pdev)
436 } 416 }
437 417
438 init_waitqueue_head(&mcfqspi->waitq); 418 init_waitqueue_head(&mcfqspi->waitq);
439 mcfqspi->dev = &pdev->dev;
440 419
441 master->mode_bits = SPI_CS_HIGH | SPI_CPOL | SPI_CPHA; 420 master->mode_bits = SPI_CS_HIGH | SPI_CPOL | SPI_CPHA;
442 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16); 421 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16);
443 master->setup = mcfqspi_setup; 422 master->setup = mcfqspi_setup;
444 master->transfer_one_message = mcfqspi_transfer_one_message; 423 master->set_cs = mcfqspi_set_cs;
424 master->transfer_one = mcfqspi_transfer_one;
445 master->auto_runtime_pm = true; 425 master->auto_runtime_pm = true;
446 426
447 platform_set_drvdata(pdev, master); 427 platform_set_drvdata(pdev, master);
@@ -451,7 +431,7 @@ static int mcfqspi_probe(struct platform_device *pdev)
451 dev_dbg(&pdev->dev, "spi_register_master failed\n"); 431 dev_dbg(&pdev->dev, "spi_register_master failed\n");
452 goto fail2; 432 goto fail2;
453 } 433 }
454 pm_runtime_enable(mcfqspi->dev); 434 pm_runtime_enable(&pdev->dev);
455 435
456 dev_info(&pdev->dev, "Coldfire QSPI bus driver\n"); 436 dev_info(&pdev->dev, "Coldfire QSPI bus driver\n");
457 437
@@ -473,9 +453,8 @@ static int mcfqspi_remove(struct platform_device *pdev)
473{ 453{
474 struct spi_master *master = platform_get_drvdata(pdev); 454 struct spi_master *master = platform_get_drvdata(pdev);
475 struct mcfqspi *mcfqspi = spi_master_get_devdata(master); 455 struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
476 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
477 456
478 pm_runtime_disable(mcfqspi->dev); 457 pm_runtime_disable(&pdev->dev);
479 /* disable the hardware (set the baud rate to 0) */ 458 /* disable the hardware (set the baud rate to 0) */
480 mcfqspi_wr_qmr(mcfqspi, MCFQSPI_QMR_MSTR); 459 mcfqspi_wr_qmr(mcfqspi, MCFQSPI_QMR_MSTR);
481 460
@@ -490,8 +469,11 @@ static int mcfqspi_suspend(struct device *dev)
490{ 469{
491 struct spi_master *master = dev_get_drvdata(dev); 470 struct spi_master *master = dev_get_drvdata(dev);
492 struct mcfqspi *mcfqspi = spi_master_get_devdata(master); 471 struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
472 int ret;
493 473
494 spi_master_suspend(master); 474 ret = spi_master_suspend(master);
475 if (ret)
476 return ret;
495 477
496 clk_disable(mcfqspi->clk); 478 clk_disable(mcfqspi->clk);
497 479
@@ -503,18 +485,17 @@ static int mcfqspi_resume(struct device *dev)
503 struct spi_master *master = dev_get_drvdata(dev); 485 struct spi_master *master = dev_get_drvdata(dev);
504 struct mcfqspi *mcfqspi = spi_master_get_devdata(master); 486 struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
505 487
506 spi_master_resume(master);
507
508 clk_enable(mcfqspi->clk); 488 clk_enable(mcfqspi->clk);
509 489
510 return 0; 490 return spi_master_resume(master);
511} 491}
512#endif 492#endif
513 493
514#ifdef CONFIG_PM_RUNTIME 494#ifdef CONFIG_PM_RUNTIME
515static int mcfqspi_runtime_suspend(struct device *dev) 495static int mcfqspi_runtime_suspend(struct device *dev)
516{ 496{
517 struct mcfqspi *mcfqspi = dev_get_drvdata(dev); 497 struct spi_master *master = dev_get_drvdata(dev);
498 struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
518 499
519 clk_disable(mcfqspi->clk); 500 clk_disable(mcfqspi->clk);
520 501
@@ -523,7 +504,8 @@ static int mcfqspi_runtime_suspend(struct device *dev)
523 504
524static int mcfqspi_runtime_resume(struct device *dev) 505static int mcfqspi_runtime_resume(struct device *dev)
525{ 506{
526 struct mcfqspi *mcfqspi = dev_get_drvdata(dev); 507 struct spi_master *master = dev_get_drvdata(dev);
508 struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
527 509
528 clk_enable(mcfqspi->clk); 510 clk_enable(mcfqspi->clk);
529 511
diff --git a/drivers/spi/spi-davinci.c b/drivers/spi/spi-davinci.c
index 5e7389faa2a0..50f750989258 100644
--- a/drivers/spi/spi-davinci.c
+++ b/drivers/spi/spi-davinci.c
@@ -802,8 +802,7 @@ static int spi_davinci_get_pdata(struct platform_device *pdev,
802 pdata = &dspi->pdata; 802 pdata = &dspi->pdata;
803 803
804 pdata->version = SPI_VERSION_1; 804 pdata->version = SPI_VERSION_1;
805 match = of_match_device(of_match_ptr(davinci_spi_of_match), 805 match = of_match_device(davinci_spi_of_match, &pdev->dev);
806 &pdev->dev);
807 if (!match) 806 if (!match)
808 return -ENODEV; 807 return -ENODEV;
809 808
@@ -824,7 +823,6 @@ static int spi_davinci_get_pdata(struct platform_device *pdev,
824 return 0; 823 return 0;
825} 824}
826#else 825#else
827#define davinci_spi_of_match NULL
828static struct davinci_spi_platform_data 826static struct davinci_spi_platform_data
829 *spi_davinci_get_pdata(struct platform_device *pdev, 827 *spi_davinci_get_pdata(struct platform_device *pdev,
830 struct davinci_spi *dspi) 828 struct davinci_spi *dspi)
@@ -864,10 +862,6 @@ static int davinci_spi_probe(struct platform_device *pdev)
864 platform_set_drvdata(pdev, master); 862 platform_set_drvdata(pdev, master);
865 863
866 dspi = spi_master_get_devdata(master); 864 dspi = spi_master_get_devdata(master);
867 if (dspi == NULL) {
868 ret = -ENOENT;
869 goto free_master;
870 }
871 865
872 if (dev_get_platdata(&pdev->dev)) { 866 if (dev_get_platdata(&pdev->dev)) {
873 pdata = dev_get_platdata(&pdev->dev); 867 pdata = dev_get_platdata(&pdev->dev);
@@ -908,10 +902,6 @@ static int davinci_spi_probe(struct platform_device *pdev)
908 goto free_master; 902 goto free_master;
909 903
910 dspi->bitbang.master = master; 904 dspi->bitbang.master = master;
911 if (dspi->bitbang.master == NULL) {
912 ret = -ENODEV;
913 goto free_master;
914 }
915 905
916 dspi->clk = devm_clk_get(&pdev->dev, NULL); 906 dspi->clk = devm_clk_get(&pdev->dev, NULL);
917 if (IS_ERR(dspi->clk)) { 907 if (IS_ERR(dspi->clk)) {
@@ -1040,7 +1030,7 @@ static struct platform_driver davinci_spi_driver = {
1040 .driver = { 1030 .driver = {
1041 .name = "spi_davinci", 1031 .name = "spi_davinci",
1042 .owner = THIS_MODULE, 1032 .owner = THIS_MODULE,
1043 .of_match_table = davinci_spi_of_match, 1033 .of_match_table = of_match_ptr(davinci_spi_of_match),
1044 }, 1034 },
1045 .probe = davinci_spi_probe, 1035 .probe = davinci_spi_probe,
1046 .remove = davinci_spi_remove, 1036 .remove = davinci_spi_remove,
diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c
index 9af56cdf1540..1492f5ee9aaa 100644
--- a/drivers/spi/spi-dw-mmio.c
+++ b/drivers/spi/spi-dw-mmio.c
@@ -66,7 +66,7 @@ static int dw_spi_mmio_probe(struct platform_device *pdev)
66 if (ret) 66 if (ret)
67 return ret; 67 return ret;
68 68
69 dws->bus_num = 0; 69 dws->bus_num = pdev->id;
70 dws->num_cs = 4; 70 dws->num_cs = 4;
71 dws->max_freq = clk_get_rate(dwsmmio->clk); 71 dws->max_freq = clk_get_rate(dwsmmio->clk);
72 72
diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c
index bf98d63d92b3..712ac5629cd4 100644
--- a/drivers/spi/spi-dw.c
+++ b/drivers/spi/spi-dw.c
@@ -276,8 +276,7 @@ static void giveback(struct dw_spi *dws)
276 queue_work(dws->workqueue, &dws->pump_messages); 276 queue_work(dws->workqueue, &dws->pump_messages);
277 spin_unlock_irqrestore(&dws->lock, flags); 277 spin_unlock_irqrestore(&dws->lock, flags);
278 278
279 last_transfer = list_entry(msg->transfers.prev, 279 last_transfer = list_last_entry(&msg->transfers, struct spi_transfer,
280 struct spi_transfer,
281 transfer_list); 280 transfer_list);
282 281
283 if (!last_transfer->cs_change && dws->cs_control) 282 if (!last_transfer->cs_change && dws->cs_control)
@@ -439,12 +438,6 @@ static void pump_transfers(unsigned long data)
439 438
440 if (transfer->speed_hz != speed) { 439 if (transfer->speed_hz != speed) {
441 speed = transfer->speed_hz; 440 speed = transfer->speed_hz;
442 if (speed > dws->max_freq) {
443 printk(KERN_ERR "MRST SPI0: unsupported"
444 "freq: %dHz\n", speed);
445 message->status = -EIO;
446 goto early_exit;
447 }
448 441
449 /* clk_div doesn't support odd number */ 442 /* clk_div doesn't support odd number */
450 clk_div = dws->max_freq / speed; 443 clk_div = dws->max_freq / speed;
@@ -671,12 +664,6 @@ static int dw_spi_setup(struct spi_device *spi)
671 return 0; 664 return 0;
672} 665}
673 666
674static void dw_spi_cleanup(struct spi_device *spi)
675{
676 struct chip_data *chip = spi_get_ctldata(spi);
677 kfree(chip);
678}
679
680static int init_queue(struct dw_spi *dws) 667static int init_queue(struct dw_spi *dws)
681{ 668{
682 INIT_LIST_HEAD(&dws->queue); 669 INIT_LIST_HEAD(&dws->queue);
@@ -806,9 +793,9 @@ int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
806 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16); 793 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
807 master->bus_num = dws->bus_num; 794 master->bus_num = dws->bus_num;
808 master->num_chipselect = dws->num_cs; 795 master->num_chipselect = dws->num_cs;
809 master->cleanup = dw_spi_cleanup;
810 master->setup = dw_spi_setup; 796 master->setup = dw_spi_setup;
811 master->transfer = dw_spi_transfer; 797 master->transfer = dw_spi_transfer;
798 master->max_speed_hz = dws->max_freq;
812 799
813 /* Basic HW init */ 800 /* Basic HW init */
814 spi_hw_init(dws); 801 spi_hw_init(dws);
diff --git a/drivers/spi/spi-efm32.c b/drivers/spi/spi-efm32.c
index d4d3cc534792..be44a3eeb5e8 100644
--- a/drivers/spi/spi-efm32.c
+++ b/drivers/spi/spi-efm32.c
@@ -198,7 +198,7 @@ static int efm32_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
198 198
199 efm32_spi_filltx(ddata); 199 efm32_spi_filltx(ddata);
200 200
201 init_completion(&ddata->done); 201 reinit_completion(&ddata->done);
202 202
203 efm32_spi_write32(ddata, REG_IF_TXBL | REG_IF_RXDATAV, REG_IEN); 203 efm32_spi_write32(ddata, REG_IF_TXBL | REG_IF_RXDATAV, REG_IEN);
204 204
@@ -287,17 +287,17 @@ static u32 efm32_spi_get_configured_location(struct efm32_spi_ddata *ddata)
287 return (reg & REG_ROUTE_LOCATION__MASK) >> __ffs(REG_ROUTE_LOCATION__MASK); 287 return (reg & REG_ROUTE_LOCATION__MASK) >> __ffs(REG_ROUTE_LOCATION__MASK);
288} 288}
289 289
290static int efm32_spi_probe_dt(struct platform_device *pdev, 290static void efm32_spi_probe_dt(struct platform_device *pdev,
291 struct spi_master *master, struct efm32_spi_ddata *ddata) 291 struct spi_master *master, struct efm32_spi_ddata *ddata)
292{ 292{
293 struct device_node *np = pdev->dev.of_node; 293 struct device_node *np = pdev->dev.of_node;
294 u32 location; 294 u32 location;
295 int ret; 295 int ret;
296 296
297 if (!np) 297 ret = of_property_read_u32(np, "efm32,location", &location);
298 return 1; 298 if (ret)
299 299 /* fall back to old and (wrongly) generic property "location" */
300 ret = of_property_read_u32(np, "location", &location); 300 ret = of_property_read_u32(np, "location", &location);
301 if (!ret) { 301 if (!ret) {
302 dev_dbg(&pdev->dev, "using location %u\n", location); 302 dev_dbg(&pdev->dev, "using location %u\n", location);
303 } else { 303 } else {
@@ -308,11 +308,6 @@ static int efm32_spi_probe_dt(struct platform_device *pdev,
308 } 308 }
309 309
310 ddata->pdata.location = location; 310 ddata->pdata.location = location;
311
312 /* spi core takes care about the bus number using an alias */
313 master->bus_num = -1;
314
315 return 0;
316} 311}
317 312
318static int efm32_spi_probe(struct platform_device *pdev) 313static int efm32_spi_probe(struct platform_device *pdev)
@@ -322,9 +317,14 @@ static int efm32_spi_probe(struct platform_device *pdev)
322 int ret; 317 int ret;
323 struct spi_master *master; 318 struct spi_master *master;
324 struct device_node *np = pdev->dev.of_node; 319 struct device_node *np = pdev->dev.of_node;
325 unsigned int num_cs, i; 320 int num_cs, i;
321
322 if (!np)
323 return -EINVAL;
326 324
327 num_cs = of_gpio_named_count(np, "cs-gpios"); 325 num_cs = of_gpio_named_count(np, "cs-gpios");
326 if (num_cs < 0)
327 return num_cs;
328 328
329 master = spi_alloc_master(&pdev->dev, 329 master = spi_alloc_master(&pdev->dev,
330 sizeof(*ddata) + num_cs * sizeof(unsigned)); 330 sizeof(*ddata) + num_cs * sizeof(unsigned));
@@ -349,6 +349,7 @@ static int efm32_spi_probe(struct platform_device *pdev)
349 ddata->bitbang.txrx_bufs = efm32_spi_txrx_bufs; 349 ddata->bitbang.txrx_bufs = efm32_spi_txrx_bufs;
350 350
351 spin_lock_init(&ddata->lock); 351 spin_lock_init(&ddata->lock);
352 init_completion(&ddata->done);
352 353
353 ddata->clk = devm_clk_get(&pdev->dev, NULL); 354 ddata->clk = devm_clk_get(&pdev->dev, NULL);
354 if (IS_ERR(ddata->clk)) { 355 if (IS_ERR(ddata->clk)) {
@@ -415,23 +416,7 @@ static int efm32_spi_probe(struct platform_device *pdev)
415 goto err; 416 goto err;
416 } 417 }
417 418
418 ret = efm32_spi_probe_dt(pdev, master, ddata); 419 efm32_spi_probe_dt(pdev, master, ddata);
419 if (ret > 0) {
420 /* not created by device tree */
421 const struct efm32_spi_pdata *pdata =
422 dev_get_platdata(&pdev->dev);
423
424 if (pdata)
425 ddata->pdata = *pdata;
426 else
427 ddata->pdata.location =
428 efm32_spi_get_configured_location(ddata);
429
430 master->bus_num = pdev->id;
431
432 } else if (ret < 0) {
433 goto err_disable_clk;
434 }
435 420
436 efm32_spi_write32(ddata, 0, REG_IEN); 421 efm32_spi_write32(ddata, 0, REG_IEN);
437 efm32_spi_write32(ddata, REG_ROUTE_TXPEN | REG_ROUTE_RXPEN | 422 efm32_spi_write32(ddata, REG_ROUTE_TXPEN | REG_ROUTE_RXPEN |
@@ -487,6 +472,9 @@ static int efm32_spi_remove(struct platform_device *pdev)
487 472
488static const struct of_device_id efm32_spi_dt_ids[] = { 473static const struct of_device_id efm32_spi_dt_ids[] = {
489 { 474 {
475 .compatible = "energymicro,efm32-spi",
476 }, {
477 /* doesn't follow the "vendor,device" scheme, don't use */
490 .compatible = "efm32,spi", 478 .compatible = "efm32,spi",
491 }, { 479 }, {
492 /* sentinel */ 480 /* sentinel */
diff --git a/drivers/spi/spi-ep93xx.c b/drivers/spi/spi-ep93xx.c
index 1bfaed6e4073..2f675d32df0e 100644
--- a/drivers/spi/spi-ep93xx.c
+++ b/drivers/spi/spi-ep93xx.c
@@ -73,8 +73,6 @@
73 * @clk: clock for the controller 73 * @clk: clock for the controller
74 * @regs_base: pointer to ioremap()'d registers 74 * @regs_base: pointer to ioremap()'d registers
75 * @sspdr_phys: physical address of the SSPDR register 75 * @sspdr_phys: physical address of the SSPDR register
76 * @min_rate: minimum clock rate (in Hz) supported by the controller
77 * @max_rate: maximum clock rate (in Hz) supported by the controller
78 * @wait: wait here until given transfer is completed 76 * @wait: wait here until given transfer is completed
79 * @current_msg: message that is currently processed (or %NULL if none) 77 * @current_msg: message that is currently processed (or %NULL if none)
80 * @tx: current byte in transfer to transmit 78 * @tx: current byte in transfer to transmit
@@ -95,8 +93,6 @@ struct ep93xx_spi {
95 struct clk *clk; 93 struct clk *clk;
96 void __iomem *regs_base; 94 void __iomem *regs_base;
97 unsigned long sspdr_phys; 95 unsigned long sspdr_phys;
98 unsigned long min_rate;
99 unsigned long max_rate;
100 struct completion wait; 96 struct completion wait;
101 struct spi_message *current_msg; 97 struct spi_message *current_msg;
102 size_t tx; 98 size_t tx;
@@ -199,9 +195,9 @@ static void ep93xx_spi_disable_interrupts(const struct ep93xx_spi *espi)
199 * @div_scr: pointer to return the scr divider 195 * @div_scr: pointer to return the scr divider
200 */ 196 */
201static int ep93xx_spi_calc_divisors(const struct ep93xx_spi *espi, 197static int ep93xx_spi_calc_divisors(const struct ep93xx_spi *espi,
202 unsigned long rate, 198 u32 rate, u8 *div_cpsr, u8 *div_scr)
203 u8 *div_cpsr, u8 *div_scr)
204{ 199{
200 struct spi_master *master = platform_get_drvdata(espi->pdev);
205 unsigned long spi_clk_rate = clk_get_rate(espi->clk); 201 unsigned long spi_clk_rate = clk_get_rate(espi->clk);
206 int cpsr, scr; 202 int cpsr, scr;
207 203
@@ -210,7 +206,7 @@ static int ep93xx_spi_calc_divisors(const struct ep93xx_spi *espi,
210 * controller. Note that minimum value is already checked in 206 * controller. Note that minimum value is already checked in
211 * ep93xx_spi_transfer_one_message(). 207 * ep93xx_spi_transfer_one_message().
212 */ 208 */
213 rate = clamp(rate, espi->min_rate, espi->max_rate); 209 rate = clamp(rate, master->min_speed_hz, master->max_speed_hz);
214 210
215 /* 211 /*
216 * Calculate divisors so that we can get speed according the 212 * Calculate divisors so that we can get speed according the
@@ -735,13 +731,6 @@ static int ep93xx_spi_transfer_one_message(struct spi_master *master,
735 struct spi_message *msg) 731 struct spi_message *msg)
736{ 732{
737 struct ep93xx_spi *espi = spi_master_get_devdata(master); 733 struct ep93xx_spi *espi = spi_master_get_devdata(master);
738 struct spi_transfer *t;
739
740 /* first validate each transfer */
741 list_for_each_entry(t, &msg->transfers, transfer_list) {
742 if (t->speed_hz < espi->min_rate)
743 return -EINVAL;
744 }
745 734
746 msg->state = NULL; 735 msg->state = NULL;
747 msg->status = 0; 736 msg->status = 0;
@@ -917,8 +906,8 @@ static int ep93xx_spi_probe(struct platform_device *pdev)
917 * Calculate maximum and minimum supported clock rates 906 * Calculate maximum and minimum supported clock rates
918 * for the controller. 907 * for the controller.
919 */ 908 */
920 espi->max_rate = clk_get_rate(espi->clk) / 2; 909 master->max_speed_hz = clk_get_rate(espi->clk) / 2;
921 espi->min_rate = clk_get_rate(espi->clk) / (254 * 256); 910 master->min_speed_hz = clk_get_rate(espi->clk) / (254 * 256);
922 espi->pdev = pdev; 911 espi->pdev = pdev;
923 912
924 espi->sspdr_phys = res->start + SSPDR; 913 espi->sspdr_phys = res->start + SSPDR;
diff --git a/drivers/spi/spi-falcon.c b/drivers/spi/spi-falcon.c
index dd5bd468e962..09965f069a1c 100644
--- a/drivers/spi/spi-falcon.c
+++ b/drivers/spi/spi-falcon.c
@@ -312,9 +312,6 @@ static int falcon_sflash_setup(struct spi_device *spi)
312 unsigned int i; 312 unsigned int i;
313 unsigned long flags; 313 unsigned long flags;
314 314
315 if (spi->chip_select > 0)
316 return -ENODEV;
317
318 spin_lock_irqsave(&ebu_lock, flags); 315 spin_lock_irqsave(&ebu_lock, flags);
319 316
320 if (spi->max_speed_hz >= CLOCK_100M) { 317 if (spi->max_speed_hz >= CLOCK_100M) {
@@ -422,9 +419,7 @@ static int falcon_sflash_probe(struct platform_device *pdev)
422 priv->master = master; 419 priv->master = master;
423 420
424 master->mode_bits = SPI_MODE_3; 421 master->mode_bits = SPI_MODE_3;
425 master->num_chipselect = 1;
426 master->flags = SPI_MASTER_HALF_DUPLEX; 422 master->flags = SPI_MASTER_HALF_DUPLEX;
427 master->bus_num = -1;
428 master->setup = falcon_sflash_setup; 423 master->setup = falcon_sflash_setup;
429 master->prepare_transfer_hardware = falcon_sflash_prepare_xfer; 424 master->prepare_transfer_hardware = falcon_sflash_prepare_xfer;
430 master->transfer_one_message = falcon_sflash_xfer_one; 425 master->transfer_one_message = falcon_sflash_xfer_one;
diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c
index ec79f726672a..d565eeee3bd8 100644
--- a/drivers/spi/spi-fsl-dspi.c
+++ b/drivers/spi/spi-fsl-dspi.c
@@ -18,6 +18,7 @@
18#include <linux/interrupt.h> 18#include <linux/interrupt.h>
19#include <linux/errno.h> 19#include <linux/errno.h>
20#include <linux/platform_device.h> 20#include <linux/platform_device.h>
21#include <linux/regmap.h>
21#include <linux/sched.h> 22#include <linux/sched.h>
22#include <linux/delay.h> 23#include <linux/delay.h>
23#include <linux/io.h> 24#include <linux/io.h>
@@ -108,11 +109,11 @@ struct fsl_dspi {
108 struct spi_bitbang bitbang; 109 struct spi_bitbang bitbang;
109 struct platform_device *pdev; 110 struct platform_device *pdev;
110 111
111 void __iomem *base; 112 struct regmap *regmap;
112 int irq; 113 int irq;
113 struct clk *clk; 114 struct clk *clk;
114 115
115 struct spi_transfer *cur_transfer; 116 struct spi_transfer *cur_transfer;
116 struct chip_data *cur_chip; 117 struct chip_data *cur_chip;
117 size_t len; 118 size_t len;
118 void *tx; 119 void *tx;
@@ -123,24 +124,17 @@ struct fsl_dspi {
123 u8 cs; 124 u8 cs;
124 u16 void_write_data; 125 u16 void_write_data;
125 126
126 wait_queue_head_t waitq; 127 wait_queue_head_t waitq;
127 u32 waitflags; 128 u32 waitflags;
128}; 129};
129 130
130static inline int is_double_byte_mode(struct fsl_dspi *dspi) 131static inline int is_double_byte_mode(struct fsl_dspi *dspi)
131{ 132{
132 return ((readl(dspi->base + SPI_CTAR(dspi->cs)) & SPI_FRAME_BITS_MASK) 133 unsigned int val;
133 == SPI_FRAME_BITS(8)) ? 0 : 1;
134}
135 134
136static void set_bit_mode(struct fsl_dspi *dspi, unsigned char bits) 135 regmap_read(dspi->regmap, SPI_CTAR(dspi->cs), &val);
137{
138 u32 temp;
139 136
140 temp = readl(dspi->base + SPI_CTAR(dspi->cs)); 137 return ((val & SPI_FRAME_BITS_MASK) == SPI_FRAME_BITS(8)) ? 0 : 1;
141 temp &= ~SPI_FRAME_BITS_MASK;
142 temp |= SPI_FRAME_BITS(bits);
143 writel(temp, dspi->base + SPI_CTAR(dspi->cs));
144} 138}
145 139
146static void hz_to_spi_baud(char *pbr, char *br, int speed_hz, 140static void hz_to_spi_baud(char *pbr, char *br, int speed_hz,
@@ -188,7 +182,8 @@ static int dspi_transfer_write(struct fsl_dspi *dspi)
188 */ 182 */
189 if (tx_word && (dspi->len == 1)) { 183 if (tx_word && (dspi->len == 1)) {
190 dspi->dataflags |= TRAN_STATE_WORD_ODD_NUM; 184 dspi->dataflags |= TRAN_STATE_WORD_ODD_NUM;
191 set_bit_mode(dspi, 8); 185 regmap_update_bits(dspi->regmap, SPI_CTAR(dspi->cs),
186 SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(8));
192 tx_word = 0; 187 tx_word = 0;
193 } 188 }
194 189
@@ -238,7 +233,8 @@ static int dspi_transfer_write(struct fsl_dspi *dspi)
238 dspi_pushr |= SPI_PUSHR_CTCNT; /* clear counter */ 233 dspi_pushr |= SPI_PUSHR_CTCNT; /* clear counter */
239 } 234 }
240 235
241 writel(dspi_pushr, dspi->base + SPI_PUSHR); 236 regmap_write(dspi->regmap, SPI_PUSHR, dspi_pushr);
237
242 tx_count++; 238 tx_count++;
243 } 239 }
244 240
@@ -253,17 +249,23 @@ static int dspi_transfer_read(struct fsl_dspi *dspi)
253 while ((dspi->rx < dspi->rx_end) 249 while ((dspi->rx < dspi->rx_end)
254 && (rx_count < DSPI_FIFO_SIZE)) { 250 && (rx_count < DSPI_FIFO_SIZE)) {
255 if (rx_word) { 251 if (rx_word) {
252 unsigned int val;
253
256 if ((dspi->rx_end - dspi->rx) == 1) 254 if ((dspi->rx_end - dspi->rx) == 1)
257 break; 255 break;
258 256
259 d = SPI_POPR_RXDATA(readl(dspi->base + SPI_POPR)); 257 regmap_read(dspi->regmap, SPI_POPR, &val);
258 d = SPI_POPR_RXDATA(val);
260 259
261 if (!(dspi->dataflags & TRAN_STATE_RX_VOID)) 260 if (!(dspi->dataflags & TRAN_STATE_RX_VOID))
262 *(u16 *)dspi->rx = d; 261 *(u16 *)dspi->rx = d;
263 dspi->rx += 2; 262 dspi->rx += 2;
264 263
265 } else { 264 } else {
266 d = SPI_POPR_RXDATA(readl(dspi->base + SPI_POPR)); 265 unsigned int val;
266
267 regmap_read(dspi->regmap, SPI_POPR, &val);
268 d = SPI_POPR_RXDATA(val);
267 if (!(dspi->dataflags & TRAN_STATE_RX_VOID)) 269 if (!(dspi->dataflags & TRAN_STATE_RX_VOID))
268 *(u8 *)dspi->rx = d; 270 *(u8 *)dspi->rx = d;
269 dspi->rx++; 271 dspi->rx++;
@@ -295,13 +297,13 @@ static int dspi_txrx_transfer(struct spi_device *spi, struct spi_transfer *t)
295 if (!dspi->tx) 297 if (!dspi->tx)
296 dspi->dataflags |= TRAN_STATE_TX_VOID; 298 dspi->dataflags |= TRAN_STATE_TX_VOID;
297 299
298 writel(dspi->cur_chip->mcr_val, dspi->base + SPI_MCR); 300 regmap_write(dspi->regmap, SPI_MCR, dspi->cur_chip->mcr_val);
299 writel(dspi->cur_chip->ctar_val, dspi->base + SPI_CTAR(dspi->cs)); 301 regmap_write(dspi->regmap, SPI_CTAR(dspi->cs), dspi->cur_chip->ctar_val);
300 writel(SPI_RSER_EOQFE, dspi->base + SPI_RSER); 302 regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_EOQFE);
301 303
302 if (t->speed_hz) 304 if (t->speed_hz)
303 writel(dspi->cur_chip->ctar_val, 305 regmap_write(dspi->regmap, SPI_CTAR(dspi->cs),
304 dspi->base + SPI_CTAR(dspi->cs)); 306 dspi->cur_chip->ctar_val);
305 307
306 dspi_transfer_write(dspi); 308 dspi_transfer_write(dspi);
307 309
@@ -315,7 +317,9 @@ static int dspi_txrx_transfer(struct spi_device *spi, struct spi_transfer *t)
315static void dspi_chipselect(struct spi_device *spi, int value) 317static void dspi_chipselect(struct spi_device *spi, int value)
316{ 318{
317 struct fsl_dspi *dspi = spi_master_get_devdata(spi->master); 319 struct fsl_dspi *dspi = spi_master_get_devdata(spi->master);
318 u32 pushr = readl(dspi->base + SPI_PUSHR); 320 unsigned int pushr;
321
322 regmap_read(dspi->regmap, SPI_PUSHR, &pushr);
319 323
320 switch (value) { 324 switch (value) {
321 case BITBANG_CS_ACTIVE: 325 case BITBANG_CS_ACTIVE:
@@ -326,7 +330,7 @@ static void dspi_chipselect(struct spi_device *spi, int value)
326 break; 330 break;
327 } 331 }
328 332
329 writel(pushr, dspi->base + SPI_PUSHR); 333 regmap_write(dspi->regmap, SPI_PUSHR, pushr);
330} 334}
331 335
332static int dspi_setup_transfer(struct spi_device *spi, struct spi_transfer *t) 336static int dspi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
@@ -338,7 +342,8 @@ static int dspi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
338 /* Only alloc on first setup */ 342 /* Only alloc on first setup */
339 chip = spi_get_ctldata(spi); 343 chip = spi_get_ctldata(spi);
340 if (chip == NULL) { 344 if (chip == NULL) {
341 chip = kcalloc(1, sizeof(struct chip_data), GFP_KERNEL); 345 chip = devm_kzalloc(&spi->dev, sizeof(struct chip_data),
346 GFP_KERNEL);
342 if (!chip) 347 if (!chip)
343 return -ENOMEM; 348 return -ENOMEM;
344 } 349 }
@@ -349,7 +354,6 @@ static int dspi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
349 fmsz = spi->bits_per_word - 1; 354 fmsz = spi->bits_per_word - 1;
350 } else { 355 } else {
351 pr_err("Invalid wordsize\n"); 356 pr_err("Invalid wordsize\n");
352 kfree(chip);
353 return -ENODEV; 357 return -ENODEV;
354 } 358 }
355 359
@@ -382,13 +386,15 @@ static irqreturn_t dspi_interrupt(int irq, void *dev_id)
382{ 386{
383 struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id; 387 struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id;
384 388
385 writel(SPI_SR_EOQF, dspi->base + SPI_SR); 389 regmap_write(dspi->regmap, SPI_SR, SPI_SR_EOQF);
386 390
387 dspi_transfer_read(dspi); 391 dspi_transfer_read(dspi);
388 392
389 if (!dspi->len) { 393 if (!dspi->len) {
390 if (dspi->dataflags & TRAN_STATE_WORD_ODD_NUM) 394 if (dspi->dataflags & TRAN_STATE_WORD_ODD_NUM)
391 set_bit_mode(dspi, 16); 395 regmap_update_bits(dspi->regmap, SPI_CTAR(dspi->cs),
396 SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(16));
397
392 dspi->waitflags = 1; 398 dspi->waitflags = 1;
393 wake_up_interruptible(&dspi->waitq); 399 wake_up_interruptible(&dspi->waitq);
394 } else { 400 } else {
@@ -420,7 +426,6 @@ static int dspi_suspend(struct device *dev)
420 426
421static int dspi_resume(struct device *dev) 427static int dspi_resume(struct device *dev)
422{ 428{
423
424 struct spi_master *master = dev_get_drvdata(dev); 429 struct spi_master *master = dev_get_drvdata(dev);
425 struct fsl_dspi *dspi = spi_master_get_devdata(master); 430 struct fsl_dspi *dspi = spi_master_get_devdata(master);
426 431
@@ -431,8 +436,13 @@ static int dspi_resume(struct device *dev)
431} 436}
432#endif /* CONFIG_PM_SLEEP */ 437#endif /* CONFIG_PM_SLEEP */
433 438
434static const struct dev_pm_ops dspi_pm = { 439static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume);
435 SET_SYSTEM_SLEEP_PM_OPS(dspi_suspend, dspi_resume) 440
441static struct regmap_config dspi_regmap_config = {
442 .reg_bits = 32,
443 .val_bits = 32,
444 .reg_stride = 4,
445 .max_register = 0x88,
436}; 446};
437 447
438static int dspi_probe(struct platform_device *pdev) 448static int dspi_probe(struct platform_device *pdev)
@@ -441,6 +451,7 @@ static int dspi_probe(struct platform_device *pdev)
441 struct spi_master *master; 451 struct spi_master *master;
442 struct fsl_dspi *dspi; 452 struct fsl_dspi *dspi;
443 struct resource *res; 453 struct resource *res;
454 void __iomem *base;
444 int ret = 0, cs_num, bus_num; 455 int ret = 0, cs_num, bus_num;
445 456
446 master = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi)); 457 master = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi));
@@ -475,12 +486,24 @@ static int dspi_probe(struct platform_device *pdev)
475 master->bus_num = bus_num; 486 master->bus_num = bus_num;
476 487
477 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 488 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
478 dspi->base = devm_ioremap_resource(&pdev->dev, res); 489 base = devm_ioremap_resource(&pdev->dev, res);
479 if (IS_ERR(dspi->base)) { 490 if (IS_ERR(base)) {
480 ret = PTR_ERR(dspi->base); 491 ret = PTR_ERR(base);
481 goto out_master_put; 492 goto out_master_put;
482 } 493 }
483 494
495 dspi_regmap_config.lock_arg = dspi;
496 dspi_regmap_config.val_format_endian =
497 of_property_read_bool(np, "big-endian")
498 ? REGMAP_ENDIAN_BIG : REGMAP_ENDIAN_DEFAULT;
499 dspi->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "dspi", base,
500 &dspi_regmap_config);
501 if (IS_ERR(dspi->regmap)) {
502 dev_err(&pdev->dev, "failed to init regmap: %ld\n",
503 PTR_ERR(dspi->regmap));
504 return PTR_ERR(dspi->regmap);
505 }
506
484 dspi->irq = platform_get_irq(pdev, 0); 507 dspi->irq = platform_get_irq(pdev, 0);
485 if (dspi->irq < 0) { 508 if (dspi->irq < 0) {
486 dev_err(&pdev->dev, "can't get platform irq\n"); 509 dev_err(&pdev->dev, "can't get platform irq\n");
@@ -504,7 +527,7 @@ static int dspi_probe(struct platform_device *pdev)
504 clk_prepare_enable(dspi->clk); 527 clk_prepare_enable(dspi->clk);
505 528
506 init_waitqueue_head(&dspi->waitq); 529 init_waitqueue_head(&dspi->waitq);
507 platform_set_drvdata(pdev, dspi); 530 platform_set_drvdata(pdev, master);
508 531
509 ret = spi_bitbang_start(&dspi->bitbang); 532 ret = spi_bitbang_start(&dspi->bitbang);
510 if (ret != 0) { 533 if (ret != 0) {
@@ -525,7 +548,8 @@ out_master_put:
525 548
526static int dspi_remove(struct platform_device *pdev) 549static int dspi_remove(struct platform_device *pdev)
527{ 550{
528 struct fsl_dspi *dspi = platform_get_drvdata(pdev); 551 struct spi_master *master = platform_get_drvdata(pdev);
552 struct fsl_dspi *dspi = spi_master_get_devdata(master);
529 553
530 /* Disconnect from the SPI framework */ 554 /* Disconnect from the SPI framework */
531 spi_bitbang_stop(&dspi->bitbang); 555 spi_bitbang_stop(&dspi->bitbang);
diff --git a/drivers/spi/spi-fsl-espi.c b/drivers/spi/spi-fsl-espi.c
index 428dc7a6b62e..6fb2b75df821 100644
--- a/drivers/spi/spi-fsl-espi.c
+++ b/drivers/spi/spi-fsl-espi.c
@@ -219,13 +219,8 @@ static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t)
219 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); 219 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
220 struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base; 220 struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base;
221 unsigned int len = t->len; 221 unsigned int len = t->len;
222 u8 bits_per_word;
223 int ret; 222 int ret;
224 223
225 bits_per_word = spi->bits_per_word;
226 if (t->bits_per_word)
227 bits_per_word = t->bits_per_word;
228
229 mpc8xxx_spi->len = t->len; 224 mpc8xxx_spi->len = t->len;
230 len = roundup(len, 4) / 4; 225 len = roundup(len, 4) / 4;
231 226
diff --git a/drivers/spi/spi-fsl-lib.c b/drivers/spi/spi-fsl-lib.c
index 0b75f26158ab..e5d45fca3551 100644
--- a/drivers/spi/spi-fsl-lib.c
+++ b/drivers/spi/spi-fsl-lib.c
@@ -200,7 +200,7 @@ int of_mpc8xxx_spi_probe(struct platform_device *ofdev)
200 const void *prop; 200 const void *prop;
201 int ret = -ENOMEM; 201 int ret = -ENOMEM;
202 202
203 pinfo = kzalloc(sizeof(*pinfo), GFP_KERNEL); 203 pinfo = devm_kzalloc(&ofdev->dev, sizeof(*pinfo), GFP_KERNEL);
204 if (!pinfo) 204 if (!pinfo)
205 return -ENOMEM; 205 return -ENOMEM;
206 206
@@ -215,15 +215,13 @@ int of_mpc8xxx_spi_probe(struct platform_device *ofdev)
215 pdata->sysclk = get_brgfreq(); 215 pdata->sysclk = get_brgfreq();
216 if (pdata->sysclk == -1) { 216 if (pdata->sysclk == -1) {
217 pdata->sysclk = fsl_get_sys_freq(); 217 pdata->sysclk = fsl_get_sys_freq();
218 if (pdata->sysclk == -1) { 218 if (pdata->sysclk == -1)
219 ret = -ENODEV; 219 return -ENODEV;
220 goto err;
221 }
222 } 220 }
223#else 221#else
224 ret = of_property_read_u32(np, "clock-frequency", &pdata->sysclk); 222 ret = of_property_read_u32(np, "clock-frequency", &pdata->sysclk);
225 if (ret) 223 if (ret)
226 goto err; 224 return ret;
227#endif 225#endif
228 226
229 prop = of_get_property(np, "mode", NULL); 227 prop = of_get_property(np, "mode", NULL);
@@ -237,8 +235,4 @@ int of_mpc8xxx_spi_probe(struct platform_device *ofdev)
237 pdata->flags = SPI_CPM_MODE | SPI_CPM1; 235 pdata->flags = SPI_CPM_MODE | SPI_CPM1;
238 236
239 return 0; 237 return 0;
240
241err:
242 kfree(pinfo);
243 return ret;
244} 238}
diff --git a/drivers/spi/spi-fsl-spi.c b/drivers/spi/spi-fsl-spi.c
index 119f7af94537..f35488ed62a9 100644
--- a/drivers/spi/spi-fsl-spi.c
+++ b/drivers/spi/spi-fsl-spi.c
@@ -239,12 +239,6 @@ static int fsl_spi_setup_transfer(struct spi_device *spi,
239 if (!bits_per_word) 239 if (!bits_per_word)
240 bits_per_word = spi->bits_per_word; 240 bits_per_word = spi->bits_per_word;
241 241
242 /* Make sure its a bit width we support [4..16, 32] */
243 if ((bits_per_word < 4)
244 || ((bits_per_word > 16) && (bits_per_word != 32))
245 || (bits_per_word > mpc8xxx_spi->max_bits_per_word))
246 return -EINVAL;
247
248 if (!hz) 242 if (!hz)
249 hz = spi->max_speed_hz; 243 hz = spi->max_speed_hz;
250 244
@@ -362,18 +356,28 @@ static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t,
362static void fsl_spi_do_one_msg(struct spi_message *m) 356static void fsl_spi_do_one_msg(struct spi_message *m)
363{ 357{
364 struct spi_device *spi = m->spi; 358 struct spi_device *spi = m->spi;
365 struct spi_transfer *t; 359 struct spi_transfer *t, *first;
366 unsigned int cs_change; 360 unsigned int cs_change;
367 const int nsecs = 50; 361 const int nsecs = 50;
368 int status; 362 int status;
369 363
370 cs_change = 1; 364 /* Don't allow changes if CS is active */
371 status = 0; 365 first = list_first_entry(&m->transfers, struct spi_transfer,
366 transfer_list);
372 list_for_each_entry(t, &m->transfers, transfer_list) { 367 list_for_each_entry(t, &m->transfers, transfer_list) {
373 if (t->bits_per_word || t->speed_hz) { 368 if ((first->bits_per_word != t->bits_per_word) ||
374 /* Don't allow changes if CS is active */ 369 (first->speed_hz != t->speed_hz)) {
375 status = -EINVAL; 370 status = -EINVAL;
371 dev_err(&spi->dev,
372 "bits_per_word/speed_hz should be same for the same SPI transfer\n");
373 return;
374 }
375 }
376 376
377 cs_change = 1;
378 status = -EINVAL;
379 list_for_each_entry(t, &m->transfers, transfer_list) {
380 if (t->bits_per_word || t->speed_hz) {
377 if (cs_change) 381 if (cs_change)
378 status = fsl_spi_setup_transfer(spi, t); 382 status = fsl_spi_setup_transfer(spi, t);
379 if (status < 0) 383 if (status < 0)
@@ -641,6 +645,10 @@ static struct spi_master * fsl_spi_probe(struct device *dev,
641 if (mpc8xxx_spi->type == TYPE_GRLIB) 645 if (mpc8xxx_spi->type == TYPE_GRLIB)
642 fsl_spi_grlib_probe(dev); 646 fsl_spi_grlib_probe(dev);
643 647
648 master->bits_per_word_mask =
649 (SPI_BPW_RANGE_MASK(4, 16) | SPI_BPW_MASK(32)) &
650 SPI_BPW_RANGE_MASK(1, mpc8xxx_spi->max_bits_per_word);
651
644 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) 652 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
645 mpc8xxx_spi->set_shifts = fsl_spi_qe_cpu_set_shifts; 653 mpc8xxx_spi->set_shifts = fsl_spi_qe_cpu_set_shifts;
646 654
diff --git a/drivers/spi/spi-gpio.c b/drivers/spi/spi-gpio.c
index 7beeb29472ac..09823076df88 100644
--- a/drivers/spi/spi-gpio.c
+++ b/drivers/spi/spi-gpio.c
@@ -19,7 +19,6 @@
19 */ 19 */
20#include <linux/kernel.h> 20#include <linux/kernel.h>
21#include <linux/module.h> 21#include <linux/module.h>
22#include <linux/init.h>
23#include <linux/platform_device.h> 22#include <linux/platform_device.h>
24#include <linux/gpio.h> 23#include <linux/gpio.h>
25#include <linux/of.h> 24#include <linux/of.h>
@@ -250,7 +249,7 @@ static int spi_gpio_setup(struct spi_device *spi)
250 /* 249 /*
251 * ... otherwise, take it from spi->controller_data 250 * ... otherwise, take it from spi->controller_data
252 */ 251 */
253 cs = (unsigned int) spi->controller_data; 252 cs = (unsigned int)(uintptr_t) spi->controller_data;
254 } 253 }
255 254
256 if (!spi->controller_state) { 255 if (!spi->controller_state) {
@@ -503,13 +502,12 @@ static int spi_gpio_remove(struct platform_device *pdev)
503{ 502{
504 struct spi_gpio *spi_gpio; 503 struct spi_gpio *spi_gpio;
505 struct spi_gpio_platform_data *pdata; 504 struct spi_gpio_platform_data *pdata;
506 int status;
507 505
508 spi_gpio = platform_get_drvdata(pdev); 506 spi_gpio = platform_get_drvdata(pdev);
509 pdata = dev_get_platdata(&pdev->dev); 507 pdata = dev_get_platdata(&pdev->dev);
510 508
511 /* stop() unregisters child devices too */ 509 /* stop() unregisters child devices too */
512 status = spi_bitbang_stop(&spi_gpio->bitbang); 510 spi_bitbang_stop(&spi_gpio->bitbang);
513 511
514 if (SPI_MISO_GPIO != SPI_GPIO_NO_MISO) 512 if (SPI_MISO_GPIO != SPI_GPIO_NO_MISO)
515 gpio_free(SPI_MISO_GPIO); 513 gpio_free(SPI_MISO_GPIO);
@@ -518,7 +516,7 @@ static int spi_gpio_remove(struct platform_device *pdev)
518 gpio_free(SPI_SCK_GPIO); 516 gpio_free(SPI_SCK_GPIO);
519 spi_master_put(spi_gpio->bitbang.master); 517 spi_master_put(spi_gpio->bitbang.master);
520 518
521 return status; 519 return 0;
522} 520}
523 521
524MODULE_ALIAS("platform:" DRIVER_NAME); 522MODULE_ALIAS("platform:" DRIVER_NAME);
diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
index a5474ef9d2a0..5daff2054ae4 100644
--- a/drivers/spi/spi-imx.c
+++ b/drivers/spi/spi-imx.c
@@ -23,7 +23,6 @@
23#include <linux/delay.h> 23#include <linux/delay.h>
24#include <linux/err.h> 24#include <linux/err.h>
25#include <linux/gpio.h> 25#include <linux/gpio.h>
26#include <linux/init.h>
27#include <linux/interrupt.h> 26#include <linux/interrupt.h>
28#include <linux/io.h> 27#include <linux/io.h>
29#include <linux/irq.h> 28#include <linux/irq.h>
@@ -741,7 +740,7 @@ static int spi_imx_transfer(struct spi_device *spi,
741 spi_imx->count = transfer->len; 740 spi_imx->count = transfer->len;
742 spi_imx->txfifo = 0; 741 spi_imx->txfifo = 0;
743 742
744 init_completion(&spi_imx->xfer_done); 743 reinit_completion(&spi_imx->xfer_done);
745 744
746 spi_imx_push(spi_imx); 745 spi_imx_push(spi_imx);
747 746
@@ -880,12 +879,12 @@ static int spi_imx_probe(struct platform_device *pdev)
880 879
881 spi_imx->irq = platform_get_irq(pdev, 0); 880 spi_imx->irq = platform_get_irq(pdev, 0);
882 if (spi_imx->irq < 0) { 881 if (spi_imx->irq < 0) {
883 ret = -EINVAL; 882 ret = spi_imx->irq;
884 goto out_master_put; 883 goto out_master_put;
885 } 884 }
886 885
887 ret = devm_request_irq(&pdev->dev, spi_imx->irq, spi_imx_isr, 0, 886 ret = devm_request_irq(&pdev->dev, spi_imx->irq, spi_imx_isr, 0,
888 DRIVER_NAME, spi_imx); 887 dev_name(&pdev->dev), spi_imx);
889 if (ret) { 888 if (ret) {
890 dev_err(&pdev->dev, "can't get irq%d: %d\n", spi_imx->irq, ret); 889 dev_err(&pdev->dev, "can't get irq%d: %d\n", spi_imx->irq, ret);
891 goto out_master_put; 890 goto out_master_put;
@@ -948,8 +947,8 @@ static int spi_imx_remove(struct platform_device *pdev)
948 spi_bitbang_stop(&spi_imx->bitbang); 947 spi_bitbang_stop(&spi_imx->bitbang);
949 948
950 writel(0, spi_imx->base + MXC_CSPICTRL); 949 writel(0, spi_imx->base + MXC_CSPICTRL);
951 clk_disable_unprepare(spi_imx->clk_ipg); 950 clk_unprepare(spi_imx->clk_ipg);
952 clk_disable_unprepare(spi_imx->clk_per); 951 clk_unprepare(spi_imx->clk_per);
953 spi_master_put(master); 952 spi_master_put(master);
954 953
955 return 0; 954 return 0;
diff --git a/drivers/spi/spi-mpc512x-psc.c b/drivers/spi/spi-mpc512x-psc.c
index 5032141eeeec..3822eef2ef9d 100644
--- a/drivers/spi/spi-mpc512x-psc.c
+++ b/drivers/spi/spi-mpc512x-psc.c
@@ -16,7 +16,6 @@
16 16
17#include <linux/module.h> 17#include <linux/module.h>
18#include <linux/kernel.h> 18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/errno.h> 19#include <linux/errno.h>
21#include <linux/interrupt.h> 20#include <linux/interrupt.h>
22#include <linux/of_address.h> 21#include <linux/of_address.h>
@@ -466,10 +465,8 @@ static void mpc512x_spi_cs_control(struct spi_device *spi, bool onoff)
466 gpio_set_value(spi->cs_gpio, onoff); 465 gpio_set_value(spi->cs_gpio, onoff);
467} 466}
468 467
469/* bus_num is used only for the case dev->platform_data == NULL */
470static int mpc512x_psc_spi_do_probe(struct device *dev, u32 regaddr, 468static int mpc512x_psc_spi_do_probe(struct device *dev, u32 regaddr,
471 u32 size, unsigned int irq, 469 u32 size, unsigned int irq)
472 s16 bus_num)
473{ 470{
474 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); 471 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
475 struct mpc512x_psc_spi *mps; 472 struct mpc512x_psc_spi *mps;
@@ -488,7 +485,6 @@ static int mpc512x_psc_spi_do_probe(struct device *dev, u32 regaddr,
488 485
489 if (pdata == NULL) { 486 if (pdata == NULL) {
490 mps->cs_control = mpc512x_spi_cs_control; 487 mps->cs_control = mpc512x_spi_cs_control;
491 master->bus_num = bus_num;
492 } else { 488 } else {
493 mps->cs_control = pdata->cs_control; 489 mps->cs_control = pdata->cs_control;
494 master->bus_num = pdata->bus_num; 490 master->bus_num = pdata->bus_num;
@@ -574,7 +570,6 @@ static int mpc512x_psc_spi_of_probe(struct platform_device *op)
574{ 570{
575 const u32 *regaddr_p; 571 const u32 *regaddr_p;
576 u64 regaddr64, size64; 572 u64 regaddr64, size64;
577 s16 id = -1;
578 573
579 regaddr_p = of_get_address(op->dev.of_node, 0, &size64, NULL); 574 regaddr_p = of_get_address(op->dev.of_node, 0, &size64, NULL);
580 if (!regaddr_p) { 575 if (!regaddr_p) {
@@ -583,16 +578,8 @@ static int mpc512x_psc_spi_of_probe(struct platform_device *op)
583 } 578 }
584 regaddr64 = of_translate_address(op->dev.of_node, regaddr_p); 579 regaddr64 = of_translate_address(op->dev.of_node, regaddr_p);
585 580
586 /* get PSC id (0..11, used by port_config) */
587 id = of_alias_get_id(op->dev.of_node, "spi");
588 if (id < 0) {
589 dev_err(&op->dev, "no alias id for %s\n",
590 op->dev.of_node->full_name);
591 return id;
592 }
593
594 return mpc512x_psc_spi_do_probe(&op->dev, (u32) regaddr64, (u32) size64, 581 return mpc512x_psc_spi_do_probe(&op->dev, (u32) regaddr64, (u32) size64,
595 irq_of_parse_and_map(op->dev.of_node, 0), id); 582 irq_of_parse_and_map(op->dev.of_node, 0));
596} 583}
597 584
598static int mpc512x_psc_spi_of_remove(struct platform_device *op) 585static int mpc512x_psc_spi_of_remove(struct platform_device *op)
diff --git a/drivers/spi/spi-mpc52xx-psc.c b/drivers/spi/spi-mpc52xx-psc.c
index 00ba910ab302..3d18d9351185 100644
--- a/drivers/spi/spi-mpc52xx-psc.c
+++ b/drivers/spi/spi-mpc52xx-psc.c
@@ -12,7 +12,6 @@
12 */ 12 */
13 13
14#include <linux/module.h> 14#include <linux/module.h>
15#include <linux/init.h>
16#include <linux/types.h> 15#include <linux/types.h>
17#include <linux/errno.h> 16#include <linux/errno.h>
18#include <linux/interrupt.h> 17#include <linux/interrupt.h>
diff --git a/drivers/spi/spi-mpc52xx.c b/drivers/spi/spi-mpc52xx.c
index 7c675fe83101..aac2a5ddd964 100644
--- a/drivers/spi/spi-mpc52xx.c
+++ b/drivers/spi/spi-mpc52xx.c
@@ -12,7 +12,6 @@
12 */ 12 */
13 13
14#include <linux/module.h> 14#include <linux/module.h>
15#include <linux/init.h>
16#include <linux/errno.h> 15#include <linux/errno.h>
17#include <linux/of_platform.h> 16#include <linux/of_platform.h>
18#include <linux/interrupt.h> 17#include <linux/interrupt.h>
@@ -357,20 +356,6 @@ static void mpc52xx_spi_wq(struct work_struct *work)
357 * spi_master ops 356 * spi_master ops
358 */ 357 */
359 358
360static int mpc52xx_spi_setup(struct spi_device *spi)
361{
362 if (spi->bits_per_word % 8)
363 return -EINVAL;
364
365 if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST))
366 return -EINVAL;
367
368 if (spi->chip_select >= spi->master->num_chipselect)
369 return -EINVAL;
370
371 return 0;
372}
373
374static int mpc52xx_spi_transfer(struct spi_device *spi, struct spi_message *m) 359static int mpc52xx_spi_transfer(struct spi_device *spi, struct spi_message *m)
375{ 360{
376 struct mpc52xx_spi *ms = spi_master_get_devdata(spi->master); 361 struct mpc52xx_spi *ms = spi_master_get_devdata(spi->master);
@@ -433,9 +418,9 @@ static int mpc52xx_spi_probe(struct platform_device *op)
433 goto err_alloc; 418 goto err_alloc;
434 } 419 }
435 420
436 master->setup = mpc52xx_spi_setup;
437 master->transfer = mpc52xx_spi_transfer; 421 master->transfer = mpc52xx_spi_transfer;
438 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; 422 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
423 master->bits_per_word_mask = SPI_BPW_MASK(8);
439 master->dev.of_node = op->dev.of_node; 424 master->dev.of_node = op->dev.of_node;
440 425
441 platform_set_drvdata(op, master); 426 platform_set_drvdata(op, master);
diff --git a/drivers/spi/spi-mxs.c b/drivers/spi/spi-mxs.c
index 79e5aa2250c8..2884f0c2f5f0 100644
--- a/drivers/spi/spi-mxs.c
+++ b/drivers/spi/spi-mxs.c
@@ -29,7 +29,6 @@
29 */ 29 */
30 30
31#include <linux/kernel.h> 31#include <linux/kernel.h>
32#include <linux/init.h>
33#include <linux/ioport.h> 32#include <linux/ioport.h>
34#include <linux/of.h> 33#include <linux/of.h>
35#include <linux/of_device.h> 34#include <linux/of_device.h>
@@ -371,7 +370,7 @@ static int mxs_spi_transfer_one(struct spi_master *master,
371{ 370{
372 struct mxs_spi *spi = spi_master_get_devdata(master); 371 struct mxs_spi *spi = spi_master_get_devdata(master);
373 struct mxs_ssp *ssp = &spi->ssp; 372 struct mxs_ssp *ssp = &spi->ssp;
374 struct spi_transfer *t, *tmp_t; 373 struct spi_transfer *t;
375 unsigned int flag; 374 unsigned int flag;
376 int status = 0; 375 int status = 0;
377 376
@@ -381,7 +380,7 @@ static int mxs_spi_transfer_one(struct spi_master *master,
381 writel(mxs_spi_cs_to_reg(m->spi->chip_select), 380 writel(mxs_spi_cs_to_reg(m->spi->chip_select),
382 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); 381 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
383 382
384 list_for_each_entry_safe(t, tmp_t, &m->transfers, transfer_list) { 383 list_for_each_entry(t, &m->transfers, transfer_list) {
385 384
386 status = mxs_spi_setup_transfer(m->spi, t); 385 status = mxs_spi_setup_transfer(m->spi, t);
387 if (status) 386 if (status)
@@ -473,7 +472,7 @@ static int mxs_spi_probe(struct platform_device *pdev)
473 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 472 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
474 irq_err = platform_get_irq(pdev, 0); 473 irq_err = platform_get_irq(pdev, 0);
475 if (irq_err < 0) 474 if (irq_err < 0)
476 return -EINVAL; 475 return irq_err;
477 476
478 base = devm_ioremap_resource(&pdev->dev, iores); 477 base = devm_ioremap_resource(&pdev->dev, iores);
479 if (IS_ERR(base)) 478 if (IS_ERR(base))
diff --git a/drivers/spi/spi-nuc900.c b/drivers/spi/spi-nuc900.c
index bae97ffec4b9..16e30de650b0 100644
--- a/drivers/spi/spi-nuc900.c
+++ b/drivers/spi/spi-nuc900.c
@@ -9,7 +9,6 @@
9 */ 9 */
10 10
11#include <linux/module.h> 11#include <linux/module.h>
12#include <linux/init.h>
13#include <linux/spinlock.h> 12#include <linux/spinlock.h>
14#include <linux/workqueue.h> 13#include <linux/workqueue.h>
15#include <linux/interrupt.h> 14#include <linux/interrupt.h>
@@ -38,7 +37,9 @@
38/* usi register bit */ 37/* usi register bit */
39#define ENINT (0x01 << 17) 38#define ENINT (0x01 << 17)
40#define ENFLG (0x01 << 16) 39#define ENFLG (0x01 << 16)
40#define SLEEP (0x0f << 12)
41#define TXNUM (0x03 << 8) 41#define TXNUM (0x03 << 8)
42#define TXBITLEN (0x1f << 3)
42#define TXNEG (0x01 << 2) 43#define TXNEG (0x01 << 2)
43#define RXNEG (0x01 << 1) 44#define RXNEG (0x01 << 1)
44#define LSB (0x01 << 10) 45#define LSB (0x01 << 10)
@@ -58,11 +59,8 @@ struct nuc900_spi {
58 unsigned char *rx; 59 unsigned char *rx;
59 struct clk *clk; 60 struct clk *clk;
60 struct spi_master *master; 61 struct spi_master *master;
61 struct spi_device *curdev;
62 struct device *dev;
63 struct nuc900_spi_info *pdata; 62 struct nuc900_spi_info *pdata;
64 spinlock_t lock; 63 spinlock_t lock;
65 struct resource *res;
66}; 64};
67 65
68static inline struct nuc900_spi *to_hw(struct spi_device *sdev) 66static inline struct nuc900_spi *to_hw(struct spi_device *sdev)
@@ -119,19 +117,16 @@ static void nuc900_spi_chipsel(struct spi_device *spi, int value)
119 } 117 }
120} 118}
121 119
122static void nuc900_spi_setup_txnum(struct nuc900_spi *hw, 120static void nuc900_spi_setup_txnum(struct nuc900_spi *hw, unsigned int txnum)
123 unsigned int txnum)
124{ 121{
125 unsigned int val; 122 unsigned int val;
126 unsigned long flags; 123 unsigned long flags;
127 124
128 spin_lock_irqsave(&hw->lock, flags); 125 spin_lock_irqsave(&hw->lock, flags);
129 126
130 val = __raw_readl(hw->regs + USI_CNT); 127 val = __raw_readl(hw->regs + USI_CNT) & ~TXNUM;
131 128
132 if (!txnum) 129 if (txnum)
133 val &= ~TXNUM;
134 else
135 val |= txnum << 0x08; 130 val |= txnum << 0x08;
136 131
137 __raw_writel(val, hw->regs + USI_CNT); 132 __raw_writel(val, hw->regs + USI_CNT);
@@ -148,7 +143,7 @@ static void nuc900_spi_setup_txbitlen(struct nuc900_spi *hw,
148 143
149 spin_lock_irqsave(&hw->lock, flags); 144 spin_lock_irqsave(&hw->lock, flags);
150 145
151 val = __raw_readl(hw->regs + USI_CNT); 146 val = __raw_readl(hw->regs + USI_CNT) & ~TXBITLEN;
152 147
153 val |= (txbitlen << 0x03); 148 val |= (txbitlen << 0x03);
154 149
@@ -287,12 +282,11 @@ static void nuc900_set_sleep(struct nuc900_spi *hw, unsigned int sleep)
287 282
288 spin_lock_irqsave(&hw->lock, flags); 283 spin_lock_irqsave(&hw->lock, flags);
289 284
290 val = __raw_readl(hw->regs + USI_CNT); 285 val = __raw_readl(hw->regs + USI_CNT) & ~SLEEP;
291 286
292 if (sleep) 287 if (sleep)
293 val |= (sleep << 12); 288 val |= (sleep << 12);
294 else 289
295 val &= ~(0x0f << 12);
296 __raw_writel(val, hw->regs + USI_CNT); 290 __raw_writel(val, hw->regs + USI_CNT);
297 291
298 spin_unlock_irqrestore(&hw->lock, flags); 292 spin_unlock_irqrestore(&hw->lock, flags);
@@ -338,6 +332,7 @@ static int nuc900_spi_probe(struct platform_device *pdev)
338{ 332{
339 struct nuc900_spi *hw; 333 struct nuc900_spi *hw;
340 struct spi_master *master; 334 struct spi_master *master;
335 struct resource *res;
341 int err = 0; 336 int err = 0;
342 337
343 master = spi_alloc_master(&pdev->dev, sizeof(struct nuc900_spi)); 338 master = spi_alloc_master(&pdev->dev, sizeof(struct nuc900_spi));
@@ -349,7 +344,6 @@ static int nuc900_spi_probe(struct platform_device *pdev)
349 hw = spi_master_get_devdata(master); 344 hw = spi_master_get_devdata(master);
350 hw->master = master; 345 hw->master = master;
351 hw->pdata = dev_get_platdata(&pdev->dev); 346 hw->pdata = dev_get_platdata(&pdev->dev);
352 hw->dev = &pdev->dev;
353 347
354 if (hw->pdata == NULL) { 348 if (hw->pdata == NULL) {
355 dev_err(&pdev->dev, "No platform data supplied\n"); 349 dev_err(&pdev->dev, "No platform data supplied\n");
@@ -369,8 +363,8 @@ static int nuc900_spi_probe(struct platform_device *pdev)
369 hw->bitbang.chipselect = nuc900_spi_chipsel; 363 hw->bitbang.chipselect = nuc900_spi_chipsel;
370 hw->bitbang.txrx_bufs = nuc900_spi_txrx; 364 hw->bitbang.txrx_bufs = nuc900_spi_txrx;
371 365
372 hw->res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 366 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
373 hw->regs = devm_ioremap_resource(&pdev->dev, hw->res); 367 hw->regs = devm_ioremap_resource(&pdev->dev, res);
374 if (IS_ERR(hw->regs)) { 368 if (IS_ERR(hw->regs)) {
375 err = PTR_ERR(hw->regs); 369 err = PTR_ERR(hw->regs);
376 goto err_pdata; 370 goto err_pdata;
diff --git a/drivers/spi/spi-oc-tiny.c b/drivers/spi/spi-oc-tiny.c
index f7c896e2981e..8998d11c7238 100644
--- a/drivers/spi/spi-oc-tiny.c
+++ b/drivers/spi/spi-oc-tiny.c
@@ -15,7 +15,6 @@
15 * published by the Free Software Foundation. 15 * published by the Free Software Foundation.
16 */ 16 */
17 17
18#include <linux/init.h>
19#include <linux/interrupt.h> 18#include <linux/interrupt.h>
20#include <linux/errno.h> 19#include <linux/errno.h>
21#include <linux/module.h> 20#include <linux/module.h>
@@ -267,8 +266,6 @@ static int tiny_spi_probe(struct platform_device *pdev)
267 266
268 /* setup the state for the bitbang driver */ 267 /* setup the state for the bitbang driver */
269 hw->bitbang.master = master; 268 hw->bitbang.master = master;
270 if (!hw->bitbang.master)
271 return err;
272 hw->bitbang.setup_transfer = tiny_spi_setup_transfer; 269 hw->bitbang.setup_transfer = tiny_spi_setup_transfer;
273 hw->bitbang.chipselect = tiny_spi_chipselect; 270 hw->bitbang.chipselect = tiny_spi_chipselect;
274 hw->bitbang.txrx_bufs = tiny_spi_txrx_bufs; 271 hw->bitbang.txrx_bufs = tiny_spi_txrx_bufs;
diff --git a/drivers/spi/spi-octeon.c b/drivers/spi/spi-octeon.c
index 67249a48b391..c5e2f718eebd 100644
--- a/drivers/spi/spi-octeon.c
+++ b/drivers/spi/spi-octeon.c
@@ -11,7 +11,6 @@
11#include <linux/spi/spi.h> 11#include <linux/spi/spi.h>
12#include <linux/module.h> 12#include <linux/module.h>
13#include <linux/delay.h> 13#include <linux/delay.h>
14#include <linux/init.h>
15#include <linux/io.h> 14#include <linux/io.h>
16#include <linux/of.h> 15#include <linux/of.h>
17 16
@@ -33,13 +32,6 @@ struct octeon_spi {
33 u64 cs_enax; 32 u64 cs_enax;
34}; 33};
35 34
36struct octeon_spi_setup {
37 u32 max_speed_hz;
38 u8 chip_select;
39 u8 mode;
40 u8 bits_per_word;
41};
42
43static void octeon_spi_wait_ready(struct octeon_spi *p) 35static void octeon_spi_wait_ready(struct octeon_spi *p)
44{ 36{
45 union cvmx_mpi_sts mpi_sts; 37 union cvmx_mpi_sts mpi_sts;
@@ -57,6 +49,7 @@ static int octeon_spi_do_transfer(struct octeon_spi *p,
57 struct spi_transfer *xfer, 49 struct spi_transfer *xfer,
58 bool last_xfer) 50 bool last_xfer)
59{ 51{
52 struct spi_device *spi = msg->spi;
60 union cvmx_mpi_cfg mpi_cfg; 53 union cvmx_mpi_cfg mpi_cfg;
61 union cvmx_mpi_tx mpi_tx; 54 union cvmx_mpi_tx mpi_tx;
62 unsigned int clkdiv; 55 unsigned int clkdiv;
@@ -68,18 +61,11 @@ static int octeon_spi_do_transfer(struct octeon_spi *p,
68 int len; 61 int len;
69 int i; 62 int i;
70 63
71 struct octeon_spi_setup *msg_setup = spi_get_ctldata(msg->spi); 64 mode = spi->mode;
72
73 speed_hz = msg_setup->max_speed_hz;
74 mode = msg_setup->mode;
75 cpha = mode & SPI_CPHA; 65 cpha = mode & SPI_CPHA;
76 cpol = mode & SPI_CPOL; 66 cpol = mode & SPI_CPOL;
77 67
78 if (xfer->speed_hz) 68 speed_hz = xfer->speed_hz ? : spi->max_speed_hz;
79 speed_hz = xfer->speed_hz;
80
81 if (speed_hz > OCTEON_SPI_MAX_CLOCK_HZ)
82 speed_hz = OCTEON_SPI_MAX_CLOCK_HZ;
83 69
84 clkdiv = octeon_get_io_clock_rate() / (2 * speed_hz); 70 clkdiv = octeon_get_io_clock_rate() / (2 * speed_hz);
85 71
@@ -93,8 +79,8 @@ static int octeon_spi_do_transfer(struct octeon_spi *p,
93 mpi_cfg.s.cslate = cpha ? 1 : 0; 79 mpi_cfg.s.cslate = cpha ? 1 : 0;
94 mpi_cfg.s.enable = 1; 80 mpi_cfg.s.enable = 1;
95 81
96 if (msg_setup->chip_select < 4) 82 if (spi->chip_select < 4)
97 p->cs_enax |= 1ull << (12 + msg_setup->chip_select); 83 p->cs_enax |= 1ull << (12 + spi->chip_select);
98 mpi_cfg.u64 |= p->cs_enax; 84 mpi_cfg.u64 |= p->cs_enax;
99 85
100 if (mpi_cfg.u64 != p->last_cfg) { 86 if (mpi_cfg.u64 != p->last_cfg) {
@@ -114,7 +100,7 @@ static int octeon_spi_do_transfer(struct octeon_spi *p,
114 cvmx_write_csr(p->register_base + OCTEON_SPI_DAT0 + (8 * i), d); 100 cvmx_write_csr(p->register_base + OCTEON_SPI_DAT0 + (8 * i), d);
115 } 101 }
116 mpi_tx.u64 = 0; 102 mpi_tx.u64 = 0;
117 mpi_tx.s.csid = msg_setup->chip_select; 103 mpi_tx.s.csid = spi->chip_select;
118 mpi_tx.s.leavecs = 1; 104 mpi_tx.s.leavecs = 1;
119 mpi_tx.s.txnum = tx_buf ? OCTEON_SPI_MAX_BYTES : 0; 105 mpi_tx.s.txnum = tx_buf ? OCTEON_SPI_MAX_BYTES : 0;
120 mpi_tx.s.totnum = OCTEON_SPI_MAX_BYTES; 106 mpi_tx.s.totnum = OCTEON_SPI_MAX_BYTES;
@@ -139,7 +125,7 @@ static int octeon_spi_do_transfer(struct octeon_spi *p,
139 } 125 }
140 126
141 mpi_tx.u64 = 0; 127 mpi_tx.u64 = 0;
142 mpi_tx.s.csid = msg_setup->chip_select; 128 mpi_tx.s.csid = spi->chip_select;
143 if (last_xfer) 129 if (last_xfer)
144 mpi_tx.s.leavecs = xfer->cs_change; 130 mpi_tx.s.leavecs = xfer->cs_change;
145 else 131 else
@@ -169,17 +155,9 @@ static int octeon_spi_transfer_one_message(struct spi_master *master,
169 int status = 0; 155 int status = 0;
170 struct spi_transfer *xfer; 156 struct spi_transfer *xfer;
171 157
172 /*
173 * We better have set the configuration via a call to .setup
174 * before we get here.
175 */
176 if (spi_get_ctldata(msg->spi) == NULL) {
177 status = -EINVAL;
178 goto err;
179 }
180
181 list_for_each_entry(xfer, &msg->transfers, transfer_list) { 158 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
182 bool last_xfer = &xfer->transfer_list == msg->transfers.prev; 159 bool last_xfer = list_is_last(&xfer->transfer_list,
160 &msg->transfers);
183 int r = octeon_spi_do_transfer(p, msg, xfer, last_xfer); 161 int r = octeon_spi_do_transfer(p, msg, xfer, last_xfer);
184 if (r < 0) { 162 if (r < 0) {
185 status = r; 163 status = r;
@@ -194,41 +172,6 @@ err:
194 return status; 172 return status;
195} 173}
196 174
197static struct octeon_spi_setup *octeon_spi_new_setup(struct spi_device *spi)
198{
199 struct octeon_spi_setup *setup = kzalloc(sizeof(*setup), GFP_KERNEL);
200 if (!setup)
201 return NULL;
202
203 setup->max_speed_hz = spi->max_speed_hz;
204 setup->chip_select = spi->chip_select;
205 setup->mode = spi->mode;
206 setup->bits_per_word = spi->bits_per_word;
207 return setup;
208}
209
210static int octeon_spi_setup(struct spi_device *spi)
211{
212 struct octeon_spi_setup *new_setup;
213 struct octeon_spi_setup *old_setup = spi_get_ctldata(spi);
214
215 new_setup = octeon_spi_new_setup(spi);
216 if (!new_setup)
217 return -ENOMEM;
218
219 spi_set_ctldata(spi, new_setup);
220 kfree(old_setup);
221
222 return 0;
223}
224
225static void octeon_spi_cleanup(struct spi_device *spi)
226{
227 struct octeon_spi_setup *old_setup = spi_get_ctldata(spi);
228 spi_set_ctldata(spi, NULL);
229 kfree(old_setup);
230}
231
232static int octeon_spi_probe(struct platform_device *pdev) 175static int octeon_spi_probe(struct platform_device *pdev)
233{ 176{
234 struct resource *res_mem; 177 struct resource *res_mem;
@@ -257,8 +200,6 @@ static int octeon_spi_probe(struct platform_device *pdev)
257 p->register_base = (u64)devm_ioremap(&pdev->dev, res_mem->start, 200 p->register_base = (u64)devm_ioremap(&pdev->dev, res_mem->start,
258 resource_size(res_mem)); 201 resource_size(res_mem));
259 202
260 /* Dynamic bus numbering */
261 master->bus_num = -1;
262 master->num_chipselect = 4; 203 master->num_chipselect = 4;
263 master->mode_bits = SPI_CPHA | 204 master->mode_bits = SPI_CPHA |
264 SPI_CPOL | 205 SPI_CPOL |
@@ -266,10 +207,9 @@ static int octeon_spi_probe(struct platform_device *pdev)
266 SPI_LSB_FIRST | 207 SPI_LSB_FIRST |
267 SPI_3WIRE; 208 SPI_3WIRE;
268 209
269 master->setup = octeon_spi_setup;
270 master->cleanup = octeon_spi_cleanup;
271 master->transfer_one_message = octeon_spi_transfer_one_message; 210 master->transfer_one_message = octeon_spi_transfer_one_message;
272 master->bits_per_word_mask = SPI_BPW_MASK(8); 211 master->bits_per_word_mask = SPI_BPW_MASK(8);
212 master->max_speed_hz = OCTEON_SPI_MAX_CLOCK_HZ;
273 213
274 master->dev.of_node = pdev->dev.of_node; 214 master->dev.of_node = pdev->dev.of_node;
275 err = devm_spi_register_master(&pdev->dev, master); 215 err = devm_spi_register_master(&pdev->dev, master);
diff --git a/drivers/spi/spi-omap-100k.c b/drivers/spi/spi-omap-100k.c
index 0d32054bfc0d..e7ffcded4e14 100644
--- a/drivers/spi/spi-omap-100k.c
+++ b/drivers/spi/spi-omap-100k.c
@@ -83,15 +83,11 @@
83#define SPI_SHUTDOWN 1 83#define SPI_SHUTDOWN 1
84 84
85struct omap1_spi100k { 85struct omap1_spi100k {
86 struct spi_master *master;
87 struct clk *ick; 86 struct clk *ick;
88 struct clk *fck; 87 struct clk *fck;
89 88
90 /* Virtual base address of the controller */ 89 /* Virtual base address of the controller */
91 void __iomem *base; 90 void __iomem *base;
92
93 /* State of the SPI */
94 unsigned int state;
95}; 91};
96 92
97struct omap1_spi100k_cs { 93struct omap1_spi100k_cs {
@@ -99,13 +95,6 @@ struct omap1_spi100k_cs {
99 int word_len; 95 int word_len;
100}; 96};
101 97
102#define MOD_REG_BIT(val, mask, set) do { \
103 if (set) \
104 val |= mask; \
105 else \
106 val &= ~mask; \
107} while (0)
108
109static void spi100k_enable_clock(struct spi_master *master) 98static void spi100k_enable_clock(struct spi_master *master)
110{ 99{
111 unsigned int val; 100 unsigned int val;
@@ -139,7 +128,7 @@ static void spi100k_write_data(struct spi_master *master, int len, int data)
139 } 128 }
140 129
141 spi100k_enable_clock(master); 130 spi100k_enable_clock(master);
142 writew( data , spi100k->base + SPI_TX_MSB); 131 writew(data , spi100k->base + SPI_TX_MSB);
143 132
144 writew(SPI_CTRL_SEN(0) | 133 writew(SPI_CTRL_SEN(0) |
145 SPI_CTRL_WORD_SIZE(len) | 134 SPI_CTRL_WORD_SIZE(len) |
@@ -147,7 +136,8 @@ static void spi100k_write_data(struct spi_master *master, int len, int data)
147 spi100k->base + SPI_CTRL); 136 spi100k->base + SPI_CTRL);
148 137
149 /* Wait for bit ack send change */ 138 /* Wait for bit ack send change */
150 while((readw(spi100k->base + SPI_STATUS) & SPI_STATUS_WE) != SPI_STATUS_WE); 139 while ((readw(spi100k->base + SPI_STATUS) & SPI_STATUS_WE) != SPI_STATUS_WE)
140 ;
151 udelay(1000); 141 udelay(1000);
152 142
153 spi100k_disable_clock(master); 143 spi100k_disable_clock(master);
@@ -155,7 +145,7 @@ static void spi100k_write_data(struct spi_master *master, int len, int data)
155 145
156static int spi100k_read_data(struct spi_master *master, int len) 146static int spi100k_read_data(struct spi_master *master, int len)
157{ 147{
158 int dataH,dataL; 148 int dataH, dataL;
159 struct omap1_spi100k *spi100k = spi_master_get_devdata(master); 149 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
160 150
161 /* Always do at least 16 bits */ 151 /* Always do at least 16 bits */
@@ -168,7 +158,8 @@ static int spi100k_read_data(struct spi_master *master, int len)
168 SPI_CTRL_RD, 158 SPI_CTRL_RD,
169 spi100k->base + SPI_CTRL); 159 spi100k->base + SPI_CTRL);
170 160
171 while((readw(spi100k->base + SPI_STATUS) & SPI_STATUS_RD) != SPI_STATUS_RD); 161 while ((readw(spi100k->base + SPI_STATUS) & SPI_STATUS_RD) != SPI_STATUS_RD)
162 ;
172 udelay(1000); 163 udelay(1000);
173 164
174 dataL = readw(spi100k->base + SPI_RX_LSB); 165 dataL = readw(spi100k->base + SPI_RX_LSB);
@@ -204,12 +195,10 @@ static void omap1_spi100k_force_cs(struct omap1_spi100k *spi100k, int enable)
204static unsigned 195static unsigned
205omap1_spi100k_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer) 196omap1_spi100k_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
206{ 197{
207 struct omap1_spi100k *spi100k;
208 struct omap1_spi100k_cs *cs = spi->controller_state; 198 struct omap1_spi100k_cs *cs = spi->controller_state;
209 unsigned int count, c; 199 unsigned int count, c;
210 int word_len; 200 int word_len;
211 201
212 spi100k = spi_master_get_devdata(spi->master);
213 count = xfer->len; 202 count = xfer->len;
214 c = count; 203 c = count;
215 word_len = cs->word_len; 204 word_len = cs->word_len;
@@ -221,12 +210,12 @@ omap1_spi100k_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
221 rx = xfer->rx_buf; 210 rx = xfer->rx_buf;
222 tx = xfer->tx_buf; 211 tx = xfer->tx_buf;
223 do { 212 do {
224 c-=1; 213 c -= 1;
225 if (xfer->tx_buf != NULL) 214 if (xfer->tx_buf != NULL)
226 spi100k_write_data(spi->master, word_len, *tx++); 215 spi100k_write_data(spi->master, word_len, *tx++);
227 if (xfer->rx_buf != NULL) 216 if (xfer->rx_buf != NULL)
228 *rx++ = spi100k_read_data(spi->master, word_len); 217 *rx++ = spi100k_read_data(spi->master, word_len);
229 } while(c); 218 } while (c);
230 } else if (word_len <= 16) { 219 } else if (word_len <= 16) {
231 u16 *rx; 220 u16 *rx;
232 const u16 *tx; 221 const u16 *tx;
@@ -234,12 +223,12 @@ omap1_spi100k_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
234 rx = xfer->rx_buf; 223 rx = xfer->rx_buf;
235 tx = xfer->tx_buf; 224 tx = xfer->tx_buf;
236 do { 225 do {
237 c-=2; 226 c -= 2;
238 if (xfer->tx_buf != NULL) 227 if (xfer->tx_buf != NULL)
239 spi100k_write_data(spi->master,word_len, *tx++); 228 spi100k_write_data(spi->master, word_len, *tx++);
240 if (xfer->rx_buf != NULL) 229 if (xfer->rx_buf != NULL)
241 *rx++ = spi100k_read_data(spi->master,word_len); 230 *rx++ = spi100k_read_data(spi->master, word_len);
242 } while(c); 231 } while (c);
243 } else if (word_len <= 32) { 232 } else if (word_len <= 32) {
244 u32 *rx; 233 u32 *rx;
245 const u32 *tx; 234 const u32 *tx;
@@ -247,12 +236,12 @@ omap1_spi100k_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
247 rx = xfer->rx_buf; 236 rx = xfer->rx_buf;
248 tx = xfer->tx_buf; 237 tx = xfer->tx_buf;
249 do { 238 do {
250 c-=4; 239 c -= 4;
251 if (xfer->tx_buf != NULL) 240 if (xfer->tx_buf != NULL)
252 spi100k_write_data(spi->master,word_len, *tx); 241 spi100k_write_data(spi->master, word_len, *tx);
253 if (xfer->rx_buf != NULL) 242 if (xfer->rx_buf != NULL)
254 *rx = spi100k_read_data(spi->master,word_len); 243 *rx = spi100k_read_data(spi->master, word_len);
255 } while(c); 244 } while (c);
256 } 245 }
257 return count - c; 246 return count - c;
258} 247}
@@ -294,7 +283,7 @@ static int omap1_spi100k_setup(struct spi_device *spi)
294 spi100k = spi_master_get_devdata(spi->master); 283 spi100k = spi_master_get_devdata(spi->master);
295 284
296 if (!cs) { 285 if (!cs) {
297 cs = kzalloc(sizeof *cs, GFP_KERNEL); 286 cs = devm_kzalloc(&spi->dev, sizeof(*cs), GFP_KERNEL);
298 if (!cs) 287 if (!cs)
299 return -ENOMEM; 288 return -ENOMEM;
300 cs->base = spi100k->base + spi->chip_select * 0x14; 289 cs->base = spi100k->base + spi->chip_select * 0x14;
@@ -411,14 +400,14 @@ static int omap1_spi100k_probe(struct platform_device *pdev)
411 if (!pdev->id) 400 if (!pdev->id)
412 return -EINVAL; 401 return -EINVAL;
413 402
414 master = spi_alloc_master(&pdev->dev, sizeof *spi100k); 403 master = spi_alloc_master(&pdev->dev, sizeof(*spi100k));
415 if (master == NULL) { 404 if (master == NULL) {
416 dev_dbg(&pdev->dev, "master allocation failed\n"); 405 dev_dbg(&pdev->dev, "master allocation failed\n");
417 return -ENOMEM; 406 return -ENOMEM;
418 } 407 }
419 408
420 if (pdev->id != -1) 409 if (pdev->id != -1)
421 master->bus_num = pdev->id; 410 master->bus_num = pdev->id;
422 411
423 master->setup = omap1_spi100k_setup; 412 master->setup = omap1_spi100k_setup;
424 master->transfer_one_message = omap1_spi100k_transfer_one_message; 413 master->transfer_one_message = omap1_spi100k_transfer_one_message;
@@ -434,7 +423,6 @@ static int omap1_spi100k_probe(struct platform_device *pdev)
434 platform_set_drvdata(pdev, master); 423 platform_set_drvdata(pdev, master);
435 424
436 spi100k = spi_master_get_devdata(master); 425 spi100k = spi_master_get_devdata(master);
437 spi100k->master = master;
438 426
439 /* 427 /*
440 * The memory region base address is taken as the platform_data. 428 * The memory region base address is taken as the platform_data.
@@ -461,8 +449,6 @@ static int omap1_spi100k_probe(struct platform_device *pdev)
461 if (status < 0) 449 if (status < 0)
462 goto err; 450 goto err;
463 451
464 spi100k->state = SPI_RUNNING;
465
466 return status; 452 return status;
467 453
468err: 454err:
diff --git a/drivers/spi/spi-omap-uwire.c b/drivers/spi/spi-omap-uwire.c
index 9313fd3b413d..be2a2e108e2f 100644
--- a/drivers/spi/spi-omap-uwire.c
+++ b/drivers/spi/spi-omap-uwire.c
@@ -99,7 +99,6 @@ struct uwire_spi {
99}; 99};
100 100
101struct uwire_state { 101struct uwire_state {
102 unsigned bits_per_word;
103 unsigned div1_idx; 102 unsigned div1_idx;
104}; 103};
105 104
@@ -210,9 +209,8 @@ static void uwire_chipselect(struct spi_device *spi, int value)
210 209
211static int uwire_txrx(struct spi_device *spi, struct spi_transfer *t) 210static int uwire_txrx(struct spi_device *spi, struct spi_transfer *t)
212{ 211{
213 struct uwire_state *ust = spi->controller_state;
214 unsigned len = t->len; 212 unsigned len = t->len;
215 unsigned bits = ust->bits_per_word; 213 unsigned bits = t->bits_per_word ? : spi->bits_per_word;
216 unsigned bytes; 214 unsigned bytes;
217 u16 val, w; 215 u16 val, w;
218 int status = 0; 216 int status = 0;
@@ -220,10 +218,6 @@ static int uwire_txrx(struct spi_device *spi, struct spi_transfer *t)
220 if (!t->tx_buf && !t->rx_buf) 218 if (!t->tx_buf && !t->rx_buf)
221 return 0; 219 return 0;
222 220
223 /* Microwire doesn't read and write concurrently */
224 if (t->tx_buf && t->rx_buf)
225 return -EPERM;
226
227 w = spi->chip_select << 10; 221 w = spi->chip_select << 10;
228 w |= CS_CMD; 222 w |= CS_CMD;
229 223
@@ -322,7 +316,6 @@ static int uwire_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
322 struct uwire_state *ust = spi->controller_state; 316 struct uwire_state *ust = spi->controller_state;
323 struct uwire_spi *uwire; 317 struct uwire_spi *uwire;
324 unsigned flags = 0; 318 unsigned flags = 0;
325 unsigned bits;
326 unsigned hz; 319 unsigned hz;
327 unsigned long rate; 320 unsigned long rate;
328 int div1_idx; 321 int div1_idx;
@@ -332,23 +325,6 @@ static int uwire_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
332 325
333 uwire = spi_master_get_devdata(spi->master); 326 uwire = spi_master_get_devdata(spi->master);
334 327
335 if (spi->chip_select > 3) {
336 pr_debug("%s: cs%d?\n", dev_name(&spi->dev), spi->chip_select);
337 status = -ENODEV;
338 goto done;
339 }
340
341 bits = spi->bits_per_word;
342 if (t != NULL && t->bits_per_word)
343 bits = t->bits_per_word;
344
345 if (bits > 16) {
346 pr_debug("%s: wordsize %d?\n", dev_name(&spi->dev), bits);
347 status = -ENODEV;
348 goto done;
349 }
350 ust->bits_per_word = bits;
351
352 /* mode 0..3, clock inverted separately; 328 /* mode 0..3, clock inverted separately;
353 * standard nCS signaling; 329 * standard nCS signaling;
354 * don't treat DI=high as "not ready" 330 * don't treat DI=high as "not ready"
@@ -502,6 +478,7 @@ static int uwire_probe(struct platform_device *pdev)
502 status = PTR_ERR(uwire->ck); 478 status = PTR_ERR(uwire->ck);
503 dev_dbg(&pdev->dev, "no functional clock?\n"); 479 dev_dbg(&pdev->dev, "no functional clock?\n");
504 spi_master_put(master); 480 spi_master_put(master);
481 iounmap(uwire_base);
505 return status; 482 return status;
506 } 483 }
507 clk_enable(uwire->ck); 484 clk_enable(uwire->ck);
@@ -515,7 +492,7 @@ static int uwire_probe(struct platform_device *pdev)
515 492
516 /* the spi->mode bits understood by this driver: */ 493 /* the spi->mode bits understood by this driver: */
517 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 494 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
518 495 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 16);
519 master->flags = SPI_MASTER_HALF_DUPLEX; 496 master->flags = SPI_MASTER_HALF_DUPLEX;
520 497
521 master->bus_num = 2; /* "official" */ 498 master->bus_num = 2; /* "official" */
@@ -539,14 +516,13 @@ static int uwire_probe(struct platform_device *pdev)
539static int uwire_remove(struct platform_device *pdev) 516static int uwire_remove(struct platform_device *pdev)
540{ 517{
541 struct uwire_spi *uwire = platform_get_drvdata(pdev); 518 struct uwire_spi *uwire = platform_get_drvdata(pdev);
542 int status;
543 519
544 // FIXME remove all child devices, somewhere ... 520 // FIXME remove all child devices, somewhere ...
545 521
546 status = spi_bitbang_stop(&uwire->bitbang); 522 spi_bitbang_stop(&uwire->bitbang);
547 uwire_off(uwire); 523 uwire_off(uwire);
548 iounmap(uwire_base); 524 iounmap(uwire_base);
549 return status; 525 return 0;
550} 526}
551 527
552/* work with hotplug and coldplug */ 528/* work with hotplug and coldplug */
diff --git a/drivers/spi/spi-omap2-mcspi.c b/drivers/spi/spi-omap2-mcspi.c
index a72127f08e39..2941c5b96ebc 100644
--- a/drivers/spi/spi-omap2-mcspi.c
+++ b/drivers/spi/spi-omap2-mcspi.c
@@ -22,7 +22,6 @@
22 */ 22 */
23 23
24#include <linux/kernel.h> 24#include <linux/kernel.h>
25#include <linux/init.h>
26#include <linux/interrupt.h> 25#include <linux/interrupt.h>
27#include <linux/module.h> 26#include <linux/module.h>
28#include <linux/device.h> 27#include <linux/device.h>
@@ -45,6 +44,7 @@
45#include <linux/platform_data/spi-omap2-mcspi.h> 44#include <linux/platform_data/spi-omap2-mcspi.h>
46 45
47#define OMAP2_MCSPI_MAX_FREQ 48000000 46#define OMAP2_MCSPI_MAX_FREQ 48000000
47#define OMAP2_MCSPI_MAX_DIVIDER 4096
48#define OMAP2_MCSPI_MAX_FIFODEPTH 64 48#define OMAP2_MCSPI_MAX_FIFODEPTH 64
49#define OMAP2_MCSPI_MAX_FIFOWCNT 0xFFFF 49#define OMAP2_MCSPI_MAX_FIFOWCNT 0xFFFF
50#define SPI_AUTOSUSPEND_TIMEOUT 2000 50#define SPI_AUTOSUSPEND_TIMEOUT 2000
@@ -89,6 +89,7 @@
89#define OMAP2_MCSPI_CHCONF_FORCE BIT(20) 89#define OMAP2_MCSPI_CHCONF_FORCE BIT(20)
90#define OMAP2_MCSPI_CHCONF_FFET BIT(27) 90#define OMAP2_MCSPI_CHCONF_FFET BIT(27)
91#define OMAP2_MCSPI_CHCONF_FFER BIT(28) 91#define OMAP2_MCSPI_CHCONF_FFER BIT(28)
92#define OMAP2_MCSPI_CHCONF_CLKG BIT(29)
92 93
93#define OMAP2_MCSPI_CHSTAT_RXS BIT(0) 94#define OMAP2_MCSPI_CHSTAT_RXS BIT(0)
94#define OMAP2_MCSPI_CHSTAT_TXS BIT(1) 95#define OMAP2_MCSPI_CHSTAT_TXS BIT(1)
@@ -96,6 +97,7 @@
96#define OMAP2_MCSPI_CHSTAT_TXFFE BIT(3) 97#define OMAP2_MCSPI_CHSTAT_TXFFE BIT(3)
97 98
98#define OMAP2_MCSPI_CHCTRL_EN BIT(0) 99#define OMAP2_MCSPI_CHCTRL_EN BIT(0)
100#define OMAP2_MCSPI_CHCTRL_EXTCLK_MASK (0xff << 8)
99 101
100#define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0) 102#define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0)
101 103
@@ -149,7 +151,7 @@ struct omap2_mcspi_cs {
149 int word_len; 151 int word_len;
150 struct list_head node; 152 struct list_head node;
151 /* Context save and restore shadow register */ 153 /* Context save and restore shadow register */
152 u32 chconf0; 154 u32 chconf0, chctrl0;
153}; 155};
154 156
155static inline void mcspi_write_reg(struct spi_master *master, 157static inline void mcspi_write_reg(struct spi_master *master,
@@ -230,10 +232,16 @@ static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
230 232
231static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable) 233static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
232{ 234{
235 struct omap2_mcspi_cs *cs = spi->controller_state;
233 u32 l; 236 u32 l;
234 237
235 l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0; 238 l = cs->chctrl0;
236 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l); 239 if (enable)
240 l |= OMAP2_MCSPI_CHCTRL_EN;
241 else
242 l &= ~OMAP2_MCSPI_CHCTRL_EN;
243 cs->chctrl0 = l;
244 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
237 /* Flash post-writes */ 245 /* Flash post-writes */
238 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0); 246 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
239} 247}
@@ -840,7 +848,7 @@ static int omap2_mcspi_setup_transfer(struct spi_device *spi,
840 struct omap2_mcspi_cs *cs = spi->controller_state; 848 struct omap2_mcspi_cs *cs = spi->controller_state;
841 struct omap2_mcspi *mcspi; 849 struct omap2_mcspi *mcspi;
842 struct spi_master *spi_cntrl; 850 struct spi_master *spi_cntrl;
843 u32 l = 0, div = 0; 851 u32 l = 0, clkd = 0, div, extclk = 0, clkg = 0;
844 u8 word_len = spi->bits_per_word; 852 u8 word_len = spi->bits_per_word;
845 u32 speed_hz = spi->max_speed_hz; 853 u32 speed_hz = spi->max_speed_hz;
846 854
@@ -856,7 +864,17 @@ static int omap2_mcspi_setup_transfer(struct spi_device *spi,
856 speed_hz = t->speed_hz; 864 speed_hz = t->speed_hz;
857 865
858 speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ); 866 speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ);
859 div = omap2_mcspi_calc_divisor(speed_hz); 867 if (speed_hz < (OMAP2_MCSPI_MAX_FREQ / OMAP2_MCSPI_MAX_DIVIDER)) {
868 clkd = omap2_mcspi_calc_divisor(speed_hz);
869 speed_hz = OMAP2_MCSPI_MAX_FREQ >> clkd;
870 clkg = 0;
871 } else {
872 div = (OMAP2_MCSPI_MAX_FREQ + speed_hz - 1) / speed_hz;
873 speed_hz = OMAP2_MCSPI_MAX_FREQ / div;
874 clkd = (div - 1) & 0xf;
875 extclk = (div - 1) >> 4;
876 clkg = OMAP2_MCSPI_CHCONF_CLKG;
877 }
860 878
861 l = mcspi_cached_chconf0(spi); 879 l = mcspi_cached_chconf0(spi);
862 880
@@ -885,7 +903,16 @@ static int omap2_mcspi_setup_transfer(struct spi_device *spi,
885 903
886 /* set clock divisor */ 904 /* set clock divisor */
887 l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK; 905 l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
888 l |= div << 2; 906 l |= clkd << 2;
907
908 /* set clock granularity */
909 l &= ~OMAP2_MCSPI_CHCONF_CLKG;
910 l |= clkg;
911 if (clkg) {
912 cs->chctrl0 &= ~OMAP2_MCSPI_CHCTRL_EXTCLK_MASK;
913 cs->chctrl0 |= extclk << 8;
914 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
915 }
889 916
890 /* set SPI mode 0..3 */ 917 /* set SPI mode 0..3 */
891 if (spi->mode & SPI_CPOL) 918 if (spi->mode & SPI_CPOL)
@@ -900,7 +927,7 @@ static int omap2_mcspi_setup_transfer(struct spi_device *spi,
900 mcspi_write_chconf0(spi, l); 927 mcspi_write_chconf0(spi, l);
901 928
902 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n", 929 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
903 OMAP2_MCSPI_MAX_FREQ >> div, 930 speed_hz,
904 (spi->mode & SPI_CPHA) ? "trailing" : "leading", 931 (spi->mode & SPI_CPHA) ? "trailing" : "leading",
905 (spi->mode & SPI_CPOL) ? "inverted" : "normal"); 932 (spi->mode & SPI_CPOL) ? "inverted" : "normal");
906 933
@@ -972,6 +999,7 @@ static int omap2_mcspi_setup(struct spi_device *spi)
972 cs->base = mcspi->base + spi->chip_select * 0x14; 999 cs->base = mcspi->base + spi->chip_select * 0x14;
973 cs->phys = mcspi->phys + spi->chip_select * 0x14; 1000 cs->phys = mcspi->phys + spi->chip_select * 0x14;
974 cs->chconf0 = 0; 1001 cs->chconf0 = 0;
1002 cs->chctrl0 = 0;
975 spi->controller_state = cs; 1003 spi->controller_state = cs;
976 /* Link this to context save list */ 1004 /* Link this to context save list */
977 list_add_tail(&cs->node, &ctx->cs); 1005 list_add_tail(&cs->node, &ctx->cs);
@@ -1057,12 +1085,15 @@ static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m)
1057 status = -EINVAL; 1085 status = -EINVAL;
1058 break; 1086 break;
1059 } 1087 }
1060 if (par_override || t->speed_hz || t->bits_per_word) { 1088 if (par_override ||
1089 (t->speed_hz != spi->max_speed_hz) ||
1090 (t->bits_per_word != spi->bits_per_word)) {
1061 par_override = 1; 1091 par_override = 1;
1062 status = omap2_mcspi_setup_transfer(spi, t); 1092 status = omap2_mcspi_setup_transfer(spi, t);
1063 if (status < 0) 1093 if (status < 0)
1064 break; 1094 break;
1065 if (!t->speed_hz && !t->bits_per_word) 1095 if (t->speed_hz == spi->max_speed_hz &&
1096 t->bits_per_word == spi->bits_per_word)
1066 par_override = 0; 1097 par_override = 0;
1067 } 1098 }
1068 if (cd && cd->cs_per_word) { 1099 if (cd && cd->cs_per_word) {
@@ -1176,16 +1207,12 @@ static int omap2_mcspi_transfer_one_message(struct spi_master *master,
1176 m->actual_length = 0; 1207 m->actual_length = 0;
1177 m->status = 0; 1208 m->status = 0;
1178 1209
1179 /* reject invalid messages and transfers */
1180 if (list_empty(&m->transfers))
1181 return -EINVAL;
1182 list_for_each_entry(t, &m->transfers, transfer_list) { 1210 list_for_each_entry(t, &m->transfers, transfer_list) {
1183 const void *tx_buf = t->tx_buf; 1211 const void *tx_buf = t->tx_buf;
1184 void *rx_buf = t->rx_buf; 1212 void *rx_buf = t->rx_buf;
1185 unsigned len = t->len; 1213 unsigned len = t->len;
1186 1214
1187 if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ 1215 if ((len && !(rx_buf || tx_buf))) {
1188 || (len && !(rx_buf || tx_buf))) {
1189 dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n", 1216 dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
1190 t->speed_hz, 1217 t->speed_hz,
1191 len, 1218 len,
@@ -1194,12 +1221,6 @@ static int omap2_mcspi_transfer_one_message(struct spi_master *master,
1194 t->bits_per_word); 1221 t->bits_per_word);
1195 return -EINVAL; 1222 return -EINVAL;
1196 } 1223 }
1197 if (t->speed_hz && t->speed_hz < (OMAP2_MCSPI_MAX_FREQ >> 15)) {
1198 dev_dbg(mcspi->dev, "speed_hz %d below minimum %d Hz\n",
1199 t->speed_hz,
1200 OMAP2_MCSPI_MAX_FREQ >> 15);
1201 return -EINVAL;
1202 }
1203 1224
1204 if (m->is_dma_mapped || len < DMA_MIN_BYTES) 1225 if (m->is_dma_mapped || len < DMA_MIN_BYTES)
1205 continue; 1226 continue;
@@ -1311,6 +1332,8 @@ static int omap2_mcspi_probe(struct platform_device *pdev)
1311 master->transfer_one_message = omap2_mcspi_transfer_one_message; 1332 master->transfer_one_message = omap2_mcspi_transfer_one_message;
1312 master->cleanup = omap2_mcspi_cleanup; 1333 master->cleanup = omap2_mcspi_cleanup;
1313 master->dev.of_node = node; 1334 master->dev.of_node = node;
1335 master->max_speed_hz = OMAP2_MCSPI_MAX_FREQ;
1336 master->min_speed_hz = OMAP2_MCSPI_MAX_FREQ >> 15;
1314 1337
1315 platform_set_drvdata(pdev, master); 1338 platform_set_drvdata(pdev, master);
1316 1339
diff --git a/drivers/spi/spi-orion.c b/drivers/spi/spi-orion.c
index 7f2121fe2622..d018a4aac3a1 100644
--- a/drivers/spi/spi-orion.c
+++ b/drivers/spi/spi-orion.c
@@ -9,7 +9,6 @@
9 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10 */ 10 */
11 11
12#include <linux/init.h>
13#include <linux/interrupt.h> 12#include <linux/interrupt.h>
14#include <linux/delay.h> 13#include <linux/delay.h>
15#include <linux/platform_device.h> 14#include <linux/platform_device.h>
@@ -43,8 +42,6 @@
43struct orion_spi { 42struct orion_spi {
44 struct spi_master *master; 43 struct spi_master *master;
45 void __iomem *base; 44 void __iomem *base;
46 unsigned int max_speed;
47 unsigned int min_speed;
48 struct clk *clk; 45 struct clk *clk;
49}; 46};
50 47
@@ -75,23 +72,6 @@ orion_spi_clrbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
75 writel(val, reg_addr); 72 writel(val, reg_addr);
76} 73}
77 74
78static int orion_spi_set_transfer_size(struct orion_spi *orion_spi, int size)
79{
80 if (size == 16) {
81 orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
82 ORION_SPI_IF_8_16_BIT_MODE);
83 } else if (size == 8) {
84 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
85 ORION_SPI_IF_8_16_BIT_MODE);
86 } else {
87 pr_debug("Bad bits per word value %d (only 8 or 16 are allowed).\n",
88 size);
89 return -EINVAL;
90 }
91
92 return 0;
93}
94
95static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed) 75static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
96{ 76{
97 u32 tclk_hz; 77 u32 tclk_hz;
@@ -170,7 +150,14 @@ orion_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
170 if (rc) 150 if (rc)
171 return rc; 151 return rc;
172 152
173 return orion_spi_set_transfer_size(orion_spi, bits_per_word); 153 if (bits_per_word == 16)
154 orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
155 ORION_SPI_IF_8_16_BIT_MODE);
156 else
157 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
158 ORION_SPI_IF_8_16_BIT_MODE);
159
160 return 0;
174} 161}
175 162
176static void orion_spi_set_cs(struct orion_spi *orion_spi, int enable) 163static void orion_spi_set_cs(struct orion_spi *orion_spi, int enable)
@@ -260,11 +247,9 @@ orion_spi_write_read_16bit(struct spi_device *spi,
260static unsigned int 247static unsigned int
261orion_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer) 248orion_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
262{ 249{
263 struct orion_spi *orion_spi;
264 unsigned int count; 250 unsigned int count;
265 int word_len; 251 int word_len;
266 252
267 orion_spi = spi_master_get_devdata(spi->master);
268 word_len = spi->bits_per_word; 253 word_len = spi->bits_per_word;
269 count = xfer->len; 254 count = xfer->len;
270 255
@@ -310,27 +295,6 @@ static int orion_spi_transfer_one_message(struct spi_master *master,
310 goto msg_done; 295 goto msg_done;
311 296
312 list_for_each_entry(t, &m->transfers, transfer_list) { 297 list_for_each_entry(t, &m->transfers, transfer_list) {
313 /* make sure buffer length is even when working in 16
314 * bit mode*/
315 if ((t->bits_per_word == 16) && (t->len & 1)) {
316 dev_err(&spi->dev,
317 "message rejected : "
318 "odd data length %d while in 16 bit mode\n",
319 t->len);
320 status = -EIO;
321 goto msg_done;
322 }
323
324 if (t->speed_hz && t->speed_hz < orion_spi->min_speed) {
325 dev_err(&spi->dev,
326 "message rejected : "
327 "device min speed (%d Hz) exceeds "
328 "required transfer speed (%d Hz)\n",
329 orion_spi->min_speed, t->speed_hz);
330 status = -EIO;
331 goto msg_done;
332 }
333
334 if (par_override || t->speed_hz || t->bits_per_word) { 298 if (par_override || t->speed_hz || t->bits_per_word) {
335 par_override = 1; 299 par_override = 1;
336 status = orion_spi_setup_transfer(spi, t); 300 status = orion_spi_setup_transfer(spi, t);
@@ -375,28 +339,6 @@ static int orion_spi_reset(struct orion_spi *orion_spi)
375 return 0; 339 return 0;
376} 340}
377 341
378static int orion_spi_setup(struct spi_device *spi)
379{
380 struct orion_spi *orion_spi;
381
382 orion_spi = spi_master_get_devdata(spi->master);
383
384 if ((spi->max_speed_hz == 0)
385 || (spi->max_speed_hz > orion_spi->max_speed))
386 spi->max_speed_hz = orion_spi->max_speed;
387
388 if (spi->max_speed_hz < orion_spi->min_speed) {
389 dev_err(&spi->dev, "setup: requested speed too low %d Hz\n",
390 spi->max_speed_hz);
391 return -EINVAL;
392 }
393
394 /*
395 * baudrate & width will be set orion_spi_setup_transfer
396 */
397 return 0;
398}
399
400static int orion_spi_probe(struct platform_device *pdev) 342static int orion_spi_probe(struct platform_device *pdev)
401{ 343{
402 struct spi_master *master; 344 struct spi_master *master;
@@ -425,9 +367,9 @@ static int orion_spi_probe(struct platform_device *pdev)
425 /* we support only mode 0, and no options */ 367 /* we support only mode 0, and no options */
426 master->mode_bits = SPI_CPHA | SPI_CPOL; 368 master->mode_bits = SPI_CPHA | SPI_CPOL;
427 369
428 master->setup = orion_spi_setup;
429 master->transfer_one_message = orion_spi_transfer_one_message; 370 master->transfer_one_message = orion_spi_transfer_one_message;
430 master->num_chipselect = ORION_NUM_CHIPSELECTS; 371 master->num_chipselect = ORION_NUM_CHIPSELECTS;
372 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
431 373
432 platform_set_drvdata(pdev, master); 374 platform_set_drvdata(pdev, master);
433 375
@@ -443,8 +385,8 @@ static int orion_spi_probe(struct platform_device *pdev)
443 clk_prepare(spi->clk); 385 clk_prepare(spi->clk);
444 clk_enable(spi->clk); 386 clk_enable(spi->clk);
445 tclk_hz = clk_get_rate(spi->clk); 387 tclk_hz = clk_get_rate(spi->clk);
446 spi->max_speed = DIV_ROUND_UP(tclk_hz, 4); 388 master->max_speed_hz = DIV_ROUND_UP(tclk_hz, 4);
447 spi->min_speed = DIV_ROUND_UP(tclk_hz, 30); 389 master->min_speed_hz = DIV_ROUND_UP(tclk_hz, 30);
448 390
449 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 391 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
450 spi->base = devm_ioremap_resource(&pdev->dev, r); 392 spi->base = devm_ioremap_resource(&pdev->dev, r);
diff --git a/drivers/spi/spi-pl022.c b/drivers/spi/spi-pl022.c
index d37e840944d6..51d99779682f 100644
--- a/drivers/spi/spi-pl022.c
+++ b/drivers/spi/spi-pl022.c
@@ -459,9 +459,8 @@ static void giveback(struct pl022 *pl022)
459 struct spi_transfer *last_transfer; 459 struct spi_transfer *last_transfer;
460 pl022->next_msg_cs_active = false; 460 pl022->next_msg_cs_active = false;
461 461
462 last_transfer = list_entry(pl022->cur_msg->transfers.prev, 462 last_transfer = list_last_entry(&pl022->cur_msg->transfers,
463 struct spi_transfer, 463 struct spi_transfer, transfer_list);
464 transfer_list);
465 464
466 /* Delay if requested before any change in chip select */ 465 /* Delay if requested before any change in chip select */
467 if (last_transfer->delay_usecs) 466 if (last_transfer->delay_usecs)
diff --git a/drivers/spi/spi-ppc4xx.c b/drivers/spi/spi-ppc4xx.c
index 5ee56726f8d0..80b8408ac3e3 100644
--- a/drivers/spi/spi-ppc4xx.c
+++ b/drivers/spi/spi-ppc4xx.c
@@ -24,7 +24,6 @@
24 */ 24 */
25 25
26#include <linux/module.h> 26#include <linux/module.h>
27#include <linux/init.h>
28#include <linux/sched.h> 27#include <linux/sched.h>
29#include <linux/slab.h> 28#include <linux/slab.h>
30#include <linux/errno.h> 29#include <linux/errno.h>
diff --git a/drivers/spi/spi-pxa2xx-dma.c b/drivers/spi/spi-pxa2xx-dma.c
index 3c0b55125f1e..713af4806f26 100644
--- a/drivers/spi/spi-pxa2xx-dma.c
+++ b/drivers/spi/spi-pxa2xx-dma.c
@@ -9,7 +9,6 @@
9 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10 */ 10 */
11 11
12#include <linux/init.h>
13#include <linux/device.h> 12#include <linux/device.h>
14#include <linux/dma-mapping.h> 13#include <linux/dma-mapping.h>
15#include <linux/dmaengine.h> 14#include <linux/dmaengine.h>
diff --git a/drivers/spi/spi-pxa2xx-pxadma.c b/drivers/spi/spi-pxa2xx-pxadma.c
index 2916efc7cfe5..e8a26f25d5c0 100644
--- a/drivers/spi/spi-pxa2xx-pxadma.c
+++ b/drivers/spi/spi-pxa2xx-pxadma.c
@@ -18,7 +18,6 @@
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */ 19 */
20 20
21#include <linux/init.h>
22#include <linux/delay.h> 21#include <linux/delay.h>
23#include <linux/device.h> 22#include <linux/device.h>
24#include <linux/dma-mapping.h> 23#include <linux/dma-mapping.h>
diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c
index c702fc536a77..41185d0557fa 100644
--- a/drivers/spi/spi-pxa2xx.c
+++ b/drivers/spi/spi-pxa2xx.c
@@ -362,8 +362,7 @@ static void giveback(struct driver_data *drv_data)
362 drv_data->cur_msg = NULL; 362 drv_data->cur_msg = NULL;
363 drv_data->cur_transfer = NULL; 363 drv_data->cur_transfer = NULL;
364 364
365 last_transfer = list_entry(msg->transfers.prev, 365 last_transfer = list_last_entry(&msg->transfers, struct spi_transfer,
366 struct spi_transfer,
367 transfer_list); 366 transfer_list);
368 367
369 /* Delay if requested before any change in chip select */ 368 /* Delay if requested before any change in chip select */
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
new file mode 100644
index 000000000000..b032e8885e24
--- /dev/null
+++ b/drivers/spi/spi-qup.c
@@ -0,0 +1,779 @@
1/*
2 * Copyright (c) 2008-2014, The Linux foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License rev 2 and
6 * only rev 2 as published by the free Software foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or fITNESS fOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/clk.h>
15#include <linux/delay.h>
16#include <linux/err.h>
17#include <linux/interrupt.h>
18#include <linux/io.h>
19#include <linux/list.h>
20#include <linux/module.h>
21#include <linux/of.h>
22#include <linux/platform_device.h>
23#include <linux/pm_runtime.h>
24#include <linux/spi/spi.h>
25
26#define QUP_CONFIG 0x0000
27#define QUP_STATE 0x0004
28#define QUP_IO_M_MODES 0x0008
29#define QUP_SW_RESET 0x000c
30#define QUP_OPERATIONAL 0x0018
31#define QUP_ERROR_FLAGS 0x001c
32#define QUP_ERROR_FLAGS_EN 0x0020
33#define QUP_OPERATIONAL_MASK 0x0028
34#define QUP_HW_VERSION 0x0030
35#define QUP_MX_OUTPUT_CNT 0x0100
36#define QUP_OUTPUT_FIFO 0x0110
37#define QUP_MX_WRITE_CNT 0x0150
38#define QUP_MX_INPUT_CNT 0x0200
39#define QUP_MX_READ_CNT 0x0208
40#define QUP_INPUT_FIFO 0x0218
41
42#define SPI_CONFIG 0x0300
43#define SPI_IO_CONTROL 0x0304
44#define SPI_ERROR_FLAGS 0x0308
45#define SPI_ERROR_FLAGS_EN 0x030c
46
47/* QUP_CONFIG fields */
48#define QUP_CONFIG_SPI_MODE (1 << 8)
49#define QUP_CONFIG_CLOCK_AUTO_GATE BIT(13)
50#define QUP_CONFIG_NO_INPUT BIT(7)
51#define QUP_CONFIG_NO_OUTPUT BIT(6)
52#define QUP_CONFIG_N 0x001f
53
54/* QUP_STATE fields */
55#define QUP_STATE_VALID BIT(2)
56#define QUP_STATE_RESET 0
57#define QUP_STATE_RUN 1
58#define QUP_STATE_PAUSE 3
59#define QUP_STATE_MASK 3
60#define QUP_STATE_CLEAR 2
61
62#define QUP_HW_VERSION_2_1_1 0x20010001
63
64/* QUP_IO_M_MODES fields */
65#define QUP_IO_M_PACK_EN BIT(15)
66#define QUP_IO_M_UNPACK_EN BIT(14)
67#define QUP_IO_M_INPUT_MODE_MASK_SHIFT 12
68#define QUP_IO_M_OUTPUT_MODE_MASK_SHIFT 10
69#define QUP_IO_M_INPUT_MODE_MASK (3 << QUP_IO_M_INPUT_MODE_MASK_SHIFT)
70#define QUP_IO_M_OUTPUT_MODE_MASK (3 << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT)
71
72#define QUP_IO_M_OUTPUT_BLOCK_SIZE(x) (((x) & (0x03 << 0)) >> 0)
73#define QUP_IO_M_OUTPUT_FIFO_SIZE(x) (((x) & (0x07 << 2)) >> 2)
74#define QUP_IO_M_INPUT_BLOCK_SIZE(x) (((x) & (0x03 << 5)) >> 5)
75#define QUP_IO_M_INPUT_FIFO_SIZE(x) (((x) & (0x07 << 7)) >> 7)
76
77#define QUP_IO_M_MODE_FIFO 0
78#define QUP_IO_M_MODE_BLOCK 1
79#define QUP_IO_M_MODE_DMOV 2
80#define QUP_IO_M_MODE_BAM 3
81
82/* QUP_OPERATIONAL fields */
83#define QUP_OP_MAX_INPUT_DONE_FLAG BIT(11)
84#define QUP_OP_MAX_OUTPUT_DONE_FLAG BIT(10)
85#define QUP_OP_IN_SERVICE_FLAG BIT(9)
86#define QUP_OP_OUT_SERVICE_FLAG BIT(8)
87#define QUP_OP_IN_FIFO_FULL BIT(7)
88#define QUP_OP_OUT_FIFO_FULL BIT(6)
89#define QUP_OP_IN_FIFO_NOT_EMPTY BIT(5)
90#define QUP_OP_OUT_FIFO_NOT_EMPTY BIT(4)
91
92/* QUP_ERROR_FLAGS and QUP_ERROR_FLAGS_EN fields */
93#define QUP_ERROR_OUTPUT_OVER_RUN BIT(5)
94#define QUP_ERROR_INPUT_UNDER_RUN BIT(4)
95#define QUP_ERROR_OUTPUT_UNDER_RUN BIT(3)
96#define QUP_ERROR_INPUT_OVER_RUN BIT(2)
97
98/* SPI_CONFIG fields */
99#define SPI_CONFIG_HS_MODE BIT(10)
100#define SPI_CONFIG_INPUT_FIRST BIT(9)
101#define SPI_CONFIG_LOOPBACK BIT(8)
102
103/* SPI_IO_CONTROL fields */
104#define SPI_IO_C_FORCE_CS BIT(11)
105#define SPI_IO_C_CLK_IDLE_HIGH BIT(10)
106#define SPI_IO_C_MX_CS_MODE BIT(8)
107#define SPI_IO_C_CS_N_POLARITY_0 BIT(4)
108#define SPI_IO_C_CS_SELECT(x) (((x) & 3) << 2)
109#define SPI_IO_C_CS_SELECT_MASK 0x000c
110#define SPI_IO_C_TRISTATE_CS BIT(1)
111#define SPI_IO_C_NO_TRI_STATE BIT(0)
112
113/* SPI_ERROR_FLAGS and SPI_ERROR_FLAGS_EN fields */
114#define SPI_ERROR_CLK_OVER_RUN BIT(1)
115#define SPI_ERROR_CLK_UNDER_RUN BIT(0)
116
117#define SPI_NUM_CHIPSELECTS 4
118
119/* high speed mode is when bus rate is greater then 26MHz */
120#define SPI_HS_MIN_RATE 26000000
121#define SPI_MAX_RATE 50000000
122
123#define SPI_DELAY_THRESHOLD 1
124#define SPI_DELAY_RETRY 10
125
126struct spi_qup {
127 void __iomem *base;
128 struct device *dev;
129 struct clk *cclk; /* core clock */
130 struct clk *iclk; /* interface clock */
131 int irq;
132 spinlock_t lock;
133
134 int in_fifo_sz;
135 int out_fifo_sz;
136 int in_blk_sz;
137 int out_blk_sz;
138
139 struct spi_transfer *xfer;
140 struct completion done;
141 int error;
142 int w_size; /* bytes per SPI word */
143 int tx_bytes;
144 int rx_bytes;
145};
146
147
148static inline bool spi_qup_is_valid_state(struct spi_qup *controller)
149{
150 u32 opstate = readl_relaxed(controller->base + QUP_STATE);
151
152 return opstate & QUP_STATE_VALID;
153}
154
155static int spi_qup_set_state(struct spi_qup *controller, u32 state)
156{
157 unsigned long loop;
158 u32 cur_state;
159
160 loop = 0;
161 while (!spi_qup_is_valid_state(controller)) {
162
163 usleep_range(SPI_DELAY_THRESHOLD, SPI_DELAY_THRESHOLD * 2);
164
165 if (++loop > SPI_DELAY_RETRY)
166 return -EIO;
167 }
168
169 if (loop)
170 dev_dbg(controller->dev, "invalid state for %ld,us %d\n",
171 loop, state);
172
173 cur_state = readl_relaxed(controller->base + QUP_STATE);
174 /*
175 * Per spec: for PAUSE_STATE to RESET_STATE, two writes
176 * of (b10) are required
177 */
178 if (((cur_state & QUP_STATE_MASK) == QUP_STATE_PAUSE) &&
179 (state == QUP_STATE_RESET)) {
180 writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE);
181 writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE);
182 } else {
183 cur_state &= ~QUP_STATE_MASK;
184 cur_state |= state;
185 writel_relaxed(cur_state, controller->base + QUP_STATE);
186 }
187
188 loop = 0;
189 while (!spi_qup_is_valid_state(controller)) {
190
191 usleep_range(SPI_DELAY_THRESHOLD, SPI_DELAY_THRESHOLD * 2);
192
193 if (++loop > SPI_DELAY_RETRY)
194 return -EIO;
195 }
196
197 return 0;
198}
199
200
201static void spi_qup_fifo_read(struct spi_qup *controller,
202 struct spi_transfer *xfer)
203{
204 u8 *rx_buf = xfer->rx_buf;
205 u32 word, state;
206 int idx, shift, w_size;
207
208 w_size = controller->w_size;
209
210 while (controller->rx_bytes < xfer->len) {
211
212 state = readl_relaxed(controller->base + QUP_OPERATIONAL);
213 if (0 == (state & QUP_OP_IN_FIFO_NOT_EMPTY))
214 break;
215
216 word = readl_relaxed(controller->base + QUP_INPUT_FIFO);
217
218 if (!rx_buf) {
219 controller->rx_bytes += w_size;
220 continue;
221 }
222
223 for (idx = 0; idx < w_size; idx++, controller->rx_bytes++) {
224 /*
225 * The data format depends on bytes per SPI word:
226 * 4 bytes: 0x12345678
227 * 2 bytes: 0x00001234
228 * 1 byte : 0x00000012
229 */
230 shift = BITS_PER_BYTE;
231 shift *= (w_size - idx - 1);
232 rx_buf[controller->rx_bytes] = word >> shift;
233 }
234 }
235}
236
237static void spi_qup_fifo_write(struct spi_qup *controller,
238 struct spi_transfer *xfer)
239{
240 const u8 *tx_buf = xfer->tx_buf;
241 u32 word, state, data;
242 int idx, w_size;
243
244 w_size = controller->w_size;
245
246 while (controller->tx_bytes < xfer->len) {
247
248 state = readl_relaxed(controller->base + QUP_OPERATIONAL);
249 if (state & QUP_OP_OUT_FIFO_FULL)
250 break;
251
252 word = 0;
253 for (idx = 0; idx < w_size; idx++, controller->tx_bytes++) {
254
255 if (!tx_buf) {
256 controller->tx_bytes += w_size;
257 break;
258 }
259
260 data = tx_buf[controller->tx_bytes];
261 word |= data << (BITS_PER_BYTE * (3 - idx));
262 }
263
264 writel_relaxed(word, controller->base + QUP_OUTPUT_FIFO);
265 }
266}
267
268static irqreturn_t spi_qup_qup_irq(int irq, void *dev_id)
269{
270 struct spi_qup *controller = dev_id;
271 struct spi_transfer *xfer;
272 u32 opflags, qup_err, spi_err;
273 unsigned long flags;
274 int error = 0;
275
276 spin_lock_irqsave(&controller->lock, flags);
277 xfer = controller->xfer;
278 controller->xfer = NULL;
279 spin_unlock_irqrestore(&controller->lock, flags);
280
281 qup_err = readl_relaxed(controller->base + QUP_ERROR_FLAGS);
282 spi_err = readl_relaxed(controller->base + SPI_ERROR_FLAGS);
283 opflags = readl_relaxed(controller->base + QUP_OPERATIONAL);
284
285 writel_relaxed(qup_err, controller->base + QUP_ERROR_FLAGS);
286 writel_relaxed(spi_err, controller->base + SPI_ERROR_FLAGS);
287 writel_relaxed(opflags, controller->base + QUP_OPERATIONAL);
288
289 if (!xfer) {
290 dev_err_ratelimited(controller->dev, "unexpected irq %x08 %x08 %x08\n",
291 qup_err, spi_err, opflags);
292 return IRQ_HANDLED;
293 }
294
295 if (qup_err) {
296 if (qup_err & QUP_ERROR_OUTPUT_OVER_RUN)
297 dev_warn(controller->dev, "OUTPUT_OVER_RUN\n");
298 if (qup_err & QUP_ERROR_INPUT_UNDER_RUN)
299 dev_warn(controller->dev, "INPUT_UNDER_RUN\n");
300 if (qup_err & QUP_ERROR_OUTPUT_UNDER_RUN)
301 dev_warn(controller->dev, "OUTPUT_UNDER_RUN\n");
302 if (qup_err & QUP_ERROR_INPUT_OVER_RUN)
303 dev_warn(controller->dev, "INPUT_OVER_RUN\n");
304
305 error = -EIO;
306 }
307
308 if (spi_err) {
309 if (spi_err & SPI_ERROR_CLK_OVER_RUN)
310 dev_warn(controller->dev, "CLK_OVER_RUN\n");
311 if (spi_err & SPI_ERROR_CLK_UNDER_RUN)
312 dev_warn(controller->dev, "CLK_UNDER_RUN\n");
313
314 error = -EIO;
315 }
316
317 if (opflags & QUP_OP_IN_SERVICE_FLAG)
318 spi_qup_fifo_read(controller, xfer);
319
320 if (opflags & QUP_OP_OUT_SERVICE_FLAG)
321 spi_qup_fifo_write(controller, xfer);
322
323 spin_lock_irqsave(&controller->lock, flags);
324 controller->error = error;
325 controller->xfer = xfer;
326 spin_unlock_irqrestore(&controller->lock, flags);
327
328 if (controller->rx_bytes == xfer->len || error)
329 complete(&controller->done);
330
331 return IRQ_HANDLED;
332}
333
334
335/* set clock freq ... bits per word */
336static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
337{
338 struct spi_qup *controller = spi_master_get_devdata(spi->master);
339 u32 config, iomode, mode;
340 int ret, n_words, w_size;
341
342 if (spi->mode & SPI_LOOP && xfer->len > controller->in_fifo_sz) {
343 dev_err(controller->dev, "too big size for loopback %d > %d\n",
344 xfer->len, controller->in_fifo_sz);
345 return -EIO;
346 }
347
348 ret = clk_set_rate(controller->cclk, xfer->speed_hz);
349 if (ret) {
350 dev_err(controller->dev, "fail to set frequency %d",
351 xfer->speed_hz);
352 return -EIO;
353 }
354
355 if (spi_qup_set_state(controller, QUP_STATE_RESET)) {
356 dev_err(controller->dev, "cannot set RESET state\n");
357 return -EIO;
358 }
359
360 w_size = 4;
361 if (xfer->bits_per_word <= 8)
362 w_size = 1;
363 else if (xfer->bits_per_word <= 16)
364 w_size = 2;
365
366 n_words = xfer->len / w_size;
367 controller->w_size = w_size;
368
369 if (n_words <= controller->in_fifo_sz) {
370 mode = QUP_IO_M_MODE_FIFO;
371 writel_relaxed(n_words, controller->base + QUP_MX_READ_CNT);
372 writel_relaxed(n_words, controller->base + QUP_MX_WRITE_CNT);
373 /* must be zero for FIFO */
374 writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT);
375 writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
376 } else {
377 mode = QUP_IO_M_MODE_BLOCK;
378 writel_relaxed(n_words, controller->base + QUP_MX_INPUT_CNT);
379 writel_relaxed(n_words, controller->base + QUP_MX_OUTPUT_CNT);
380 /* must be zero for BLOCK and BAM */
381 writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
382 writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
383 }
384
385 iomode = readl_relaxed(controller->base + QUP_IO_M_MODES);
386 /* Set input and output transfer mode */
387 iomode &= ~(QUP_IO_M_INPUT_MODE_MASK | QUP_IO_M_OUTPUT_MODE_MASK);
388 iomode &= ~(QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN);
389 iomode |= (mode << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT);
390 iomode |= (mode << QUP_IO_M_INPUT_MODE_MASK_SHIFT);
391
392 writel_relaxed(iomode, controller->base + QUP_IO_M_MODES);
393
394 config = readl_relaxed(controller->base + SPI_CONFIG);
395
396 if (spi->mode & SPI_LOOP)
397 config |= SPI_CONFIG_LOOPBACK;
398 else
399 config &= ~SPI_CONFIG_LOOPBACK;
400
401 if (spi->mode & SPI_CPHA)
402 config &= ~SPI_CONFIG_INPUT_FIRST;
403 else
404 config |= SPI_CONFIG_INPUT_FIRST;
405
406 /*
407 * HS_MODE improves signal stability for spi-clk high rates,
408 * but is invalid in loop back mode.
409 */
410 if ((xfer->speed_hz >= SPI_HS_MIN_RATE) && !(spi->mode & SPI_LOOP))
411 config |= SPI_CONFIG_HS_MODE;
412 else
413 config &= ~SPI_CONFIG_HS_MODE;
414
415 writel_relaxed(config, controller->base + SPI_CONFIG);
416
417 config = readl_relaxed(controller->base + QUP_CONFIG);
418 config &= ~(QUP_CONFIG_NO_INPUT | QUP_CONFIG_NO_OUTPUT | QUP_CONFIG_N);
419 config |= xfer->bits_per_word - 1;
420 config |= QUP_CONFIG_SPI_MODE;
421 writel_relaxed(config, controller->base + QUP_CONFIG);
422
423 writel_relaxed(0, controller->base + QUP_OPERATIONAL_MASK);
424 return 0;
425}
426
427static void spi_qup_set_cs(struct spi_device *spi, bool enable)
428{
429 struct spi_qup *controller = spi_master_get_devdata(spi->master);
430
431 u32 iocontol, mask;
432
433 iocontol = readl_relaxed(controller->base + SPI_IO_CONTROL);
434
435 /* Disable auto CS toggle and use manual */
436 iocontol &= ~SPI_IO_C_MX_CS_MODE;
437 iocontol |= SPI_IO_C_FORCE_CS;
438
439 iocontol &= ~SPI_IO_C_CS_SELECT_MASK;
440 iocontol |= SPI_IO_C_CS_SELECT(spi->chip_select);
441
442 mask = SPI_IO_C_CS_N_POLARITY_0 << spi->chip_select;
443
444 if (enable)
445 iocontol |= mask;
446 else
447 iocontol &= ~mask;
448
449 writel_relaxed(iocontol, controller->base + SPI_IO_CONTROL);
450}
451
452static int spi_qup_transfer_one(struct spi_master *master,
453 struct spi_device *spi,
454 struct spi_transfer *xfer)
455{
456 struct spi_qup *controller = spi_master_get_devdata(master);
457 unsigned long timeout, flags;
458 int ret = -EIO;
459
460 ret = spi_qup_io_config(spi, xfer);
461 if (ret)
462 return ret;
463
464 timeout = DIV_ROUND_UP(xfer->speed_hz, MSEC_PER_SEC);
465 timeout = DIV_ROUND_UP(xfer->len * 8, timeout);
466 timeout = 100 * msecs_to_jiffies(timeout);
467
468 reinit_completion(&controller->done);
469
470 spin_lock_irqsave(&controller->lock, flags);
471 controller->xfer = xfer;
472 controller->error = 0;
473 controller->rx_bytes = 0;
474 controller->tx_bytes = 0;
475 spin_unlock_irqrestore(&controller->lock, flags);
476
477 if (spi_qup_set_state(controller, QUP_STATE_RUN)) {
478 dev_warn(controller->dev, "cannot set RUN state\n");
479 goto exit;
480 }
481
482 if (spi_qup_set_state(controller, QUP_STATE_PAUSE)) {
483 dev_warn(controller->dev, "cannot set PAUSE state\n");
484 goto exit;
485 }
486
487 spi_qup_fifo_write(controller, xfer);
488
489 if (spi_qup_set_state(controller, QUP_STATE_RUN)) {
490 dev_warn(controller->dev, "cannot set EXECUTE state\n");
491 goto exit;
492 }
493
494 if (!wait_for_completion_timeout(&controller->done, timeout))
495 ret = -ETIMEDOUT;
496exit:
497 spi_qup_set_state(controller, QUP_STATE_RESET);
498 spin_lock_irqsave(&controller->lock, flags);
499 controller->xfer = NULL;
500 if (!ret)
501 ret = controller->error;
502 spin_unlock_irqrestore(&controller->lock, flags);
503 return ret;
504}
505
506static int spi_qup_probe(struct platform_device *pdev)
507{
508 struct spi_master *master;
509 struct clk *iclk, *cclk;
510 struct spi_qup *controller;
511 struct resource *res;
512 struct device *dev;
513 void __iomem *base;
514 u32 data, max_freq, iomode;
515 int ret, irq, size;
516
517 dev = &pdev->dev;
518 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
519 base = devm_ioremap_resource(dev, res);
520 if (IS_ERR(base))
521 return PTR_ERR(base);
522
523 irq = platform_get_irq(pdev, 0);
524 if (irq < 0)
525 return irq;
526
527 cclk = devm_clk_get(dev, "core");
528 if (IS_ERR(cclk))
529 return PTR_ERR(cclk);
530
531 iclk = devm_clk_get(dev, "iface");
532 if (IS_ERR(iclk))
533 return PTR_ERR(iclk);
534
535 /* This is optional parameter */
536 if (of_property_read_u32(dev->of_node, "spi-max-frequency", &max_freq))
537 max_freq = SPI_MAX_RATE;
538
539 if (!max_freq || max_freq > SPI_MAX_RATE) {
540 dev_err(dev, "invalid clock frequency %d\n", max_freq);
541 return -ENXIO;
542 }
543
544 ret = clk_prepare_enable(cclk);
545 if (ret) {
546 dev_err(dev, "cannot enable core clock\n");
547 return ret;
548 }
549
550 ret = clk_prepare_enable(iclk);
551 if (ret) {
552 clk_disable_unprepare(cclk);
553 dev_err(dev, "cannot enable iface clock\n");
554 return ret;
555 }
556
557 data = readl_relaxed(base + QUP_HW_VERSION);
558
559 if (data < QUP_HW_VERSION_2_1_1) {
560 clk_disable_unprepare(cclk);
561 clk_disable_unprepare(iclk);
562 dev_err(dev, "v.%08x is not supported\n", data);
563 return -ENXIO;
564 }
565
566 master = spi_alloc_master(dev, sizeof(struct spi_qup));
567 if (!master) {
568 clk_disable_unprepare(cclk);
569 clk_disable_unprepare(iclk);
570 dev_err(dev, "cannot allocate master\n");
571 return -ENOMEM;
572 }
573
574 master->bus_num = pdev->id;
575 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
576 master->num_chipselect = SPI_NUM_CHIPSELECTS;
577 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
578 master->max_speed_hz = max_freq;
579 master->set_cs = spi_qup_set_cs;
580 master->transfer_one = spi_qup_transfer_one;
581 master->dev.of_node = pdev->dev.of_node;
582 master->auto_runtime_pm = true;
583
584 platform_set_drvdata(pdev, master);
585
586 controller = spi_master_get_devdata(master);
587
588 controller->dev = dev;
589 controller->base = base;
590 controller->iclk = iclk;
591 controller->cclk = cclk;
592 controller->irq = irq;
593
594 spin_lock_init(&controller->lock);
595 init_completion(&controller->done);
596
597 iomode = readl_relaxed(base + QUP_IO_M_MODES);
598
599 size = QUP_IO_M_OUTPUT_BLOCK_SIZE(iomode);
600 if (size)
601 controller->out_blk_sz = size * 16;
602 else
603 controller->out_blk_sz = 4;
604
605 size = QUP_IO_M_INPUT_BLOCK_SIZE(iomode);
606 if (size)
607 controller->in_blk_sz = size * 16;
608 else
609 controller->in_blk_sz = 4;
610
611 size = QUP_IO_M_OUTPUT_FIFO_SIZE(iomode);
612 controller->out_fifo_sz = controller->out_blk_sz * (2 << size);
613
614 size = QUP_IO_M_INPUT_FIFO_SIZE(iomode);
615 controller->in_fifo_sz = controller->in_blk_sz * (2 << size);
616
617 dev_info(dev, "v.%08x IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n",
618 data, controller->in_blk_sz, controller->in_fifo_sz,
619 controller->out_blk_sz, controller->out_fifo_sz);
620
621 writel_relaxed(1, base + QUP_SW_RESET);
622
623 ret = spi_qup_set_state(controller, QUP_STATE_RESET);
624 if (ret) {
625 dev_err(dev, "cannot set RESET state\n");
626 goto error;
627 }
628
629 writel_relaxed(0, base + QUP_OPERATIONAL);
630 writel_relaxed(0, base + QUP_IO_M_MODES);
631 writel_relaxed(0, base + QUP_OPERATIONAL_MASK);
632 writel_relaxed(SPI_ERROR_CLK_UNDER_RUN | SPI_ERROR_CLK_OVER_RUN,
633 base + SPI_ERROR_FLAGS_EN);
634
635 writel_relaxed(0, base + SPI_CONFIG);
636 writel_relaxed(SPI_IO_C_NO_TRI_STATE, base + SPI_IO_CONTROL);
637
638 ret = devm_request_irq(dev, irq, spi_qup_qup_irq,
639 IRQF_TRIGGER_HIGH, pdev->name, controller);
640 if (ret)
641 goto error;
642
643 ret = devm_spi_register_master(dev, master);
644 if (ret)
645 goto error;
646
647 pm_runtime_set_autosuspend_delay(dev, MSEC_PER_SEC);
648 pm_runtime_use_autosuspend(dev);
649 pm_runtime_set_active(dev);
650 pm_runtime_enable(dev);
651 return 0;
652
653error:
654 clk_disable_unprepare(cclk);
655 clk_disable_unprepare(iclk);
656 spi_master_put(master);
657 return ret;
658}
659
660#ifdef CONFIG_PM_RUNTIME
661static int spi_qup_pm_suspend_runtime(struct device *device)
662{
663 struct spi_master *master = dev_get_drvdata(device);
664 struct spi_qup *controller = spi_master_get_devdata(master);
665 u32 config;
666
667 /* Enable clocks auto gaiting */
668 config = readl(controller->base + QUP_CONFIG);
669 config |= QUP_CONFIG_CLOCK_AUTO_GATE;
670 writel_relaxed(config, controller->base + QUP_CONFIG);
671 return 0;
672}
673
674static int spi_qup_pm_resume_runtime(struct device *device)
675{
676 struct spi_master *master = dev_get_drvdata(device);
677 struct spi_qup *controller = spi_master_get_devdata(master);
678 u32 config;
679
680 /* Disable clocks auto gaiting */
681 config = readl_relaxed(controller->base + QUP_CONFIG);
682 config &= ~QUP_CONFIG_CLOCK_AUTO_GATE;
683 writel_relaxed(config, controller->base + QUP_CONFIG);
684 return 0;
685}
686#endif /* CONFIG_PM_RUNTIME */
687
688#ifdef CONFIG_PM_SLEEP
689static int spi_qup_suspend(struct device *device)
690{
691 struct spi_master *master = dev_get_drvdata(device);
692 struct spi_qup *controller = spi_master_get_devdata(master);
693 int ret;
694
695 ret = spi_master_suspend(master);
696 if (ret)
697 return ret;
698
699 ret = spi_qup_set_state(controller, QUP_STATE_RESET);
700 if (ret)
701 return ret;
702
703 clk_disable_unprepare(controller->cclk);
704 clk_disable_unprepare(controller->iclk);
705 return 0;
706}
707
708static int spi_qup_resume(struct device *device)
709{
710 struct spi_master *master = dev_get_drvdata(device);
711 struct spi_qup *controller = spi_master_get_devdata(master);
712 int ret;
713
714 ret = clk_prepare_enable(controller->iclk);
715 if (ret)
716 return ret;
717
718 ret = clk_prepare_enable(controller->cclk);
719 if (ret)
720 return ret;
721
722 ret = spi_qup_set_state(controller, QUP_STATE_RESET);
723 if (ret)
724 return ret;
725
726 return spi_master_resume(master);
727}
728#endif /* CONFIG_PM_SLEEP */
729
730static int spi_qup_remove(struct platform_device *pdev)
731{
732 struct spi_master *master = dev_get_drvdata(&pdev->dev);
733 struct spi_qup *controller = spi_master_get_devdata(master);
734 int ret;
735
736 ret = pm_runtime_get_sync(&pdev->dev);
737 if (ret)
738 return ret;
739
740 ret = spi_qup_set_state(controller, QUP_STATE_RESET);
741 if (ret)
742 return ret;
743
744 clk_disable_unprepare(controller->cclk);
745 clk_disable_unprepare(controller->iclk);
746
747 pm_runtime_put_noidle(&pdev->dev);
748 pm_runtime_disable(&pdev->dev);
749 return 0;
750}
751
752static struct of_device_id spi_qup_dt_match[] = {
753 { .compatible = "qcom,spi-qup-v2.1.1", },
754 { .compatible = "qcom,spi-qup-v2.2.1", },
755 { }
756};
757MODULE_DEVICE_TABLE(of, spi_qup_dt_match);
758
759static const struct dev_pm_ops spi_qup_dev_pm_ops = {
760 SET_SYSTEM_SLEEP_PM_OPS(spi_qup_suspend, spi_qup_resume)
761 SET_RUNTIME_PM_OPS(spi_qup_pm_suspend_runtime,
762 spi_qup_pm_resume_runtime,
763 NULL)
764};
765
766static struct platform_driver spi_qup_driver = {
767 .driver = {
768 .name = "spi_qup",
769 .owner = THIS_MODULE,
770 .pm = &spi_qup_dev_pm_ops,
771 .of_match_table = spi_qup_dt_match,
772 },
773 .probe = spi_qup_probe,
774 .remove = spi_qup_remove,
775};
776module_platform_driver(spi_qup_driver);
777
778MODULE_LICENSE("GPL v2");
779MODULE_ALIAS("platform:spi_qup");
diff --git a/drivers/spi/spi-rspi.c b/drivers/spi/spi-rspi.c
index 28987d9fcfe5..1fb0ad213324 100644
--- a/drivers/spi/spi-rspi.c
+++ b/drivers/spi/spi-rspi.c
@@ -1,7 +1,8 @@
1/* 1/*
2 * SH RSPI driver 2 * SH RSPI driver
3 * 3 *
4 * Copyright (C) 2012 Renesas Solutions Corp. 4 * Copyright (C) 2012, 2013 Renesas Solutions Corp.
5 * Copyright (C) 2014 Glider bvba
5 * 6 *
6 * Based on spi-sh.c: 7 * Based on spi-sh.c:
7 * Copyright (C) 2011 Renesas Solutions Corp. 8 * Copyright (C) 2011 Renesas Solutions Corp.
@@ -25,14 +26,14 @@
25#include <linux/kernel.h> 26#include <linux/kernel.h>
26#include <linux/sched.h> 27#include <linux/sched.h>
27#include <linux/errno.h> 28#include <linux/errno.h>
28#include <linux/list.h>
29#include <linux/workqueue.h>
30#include <linux/interrupt.h> 29#include <linux/interrupt.h>
31#include <linux/platform_device.h> 30#include <linux/platform_device.h>
32#include <linux/io.h> 31#include <linux/io.h>
33#include <linux/clk.h> 32#include <linux/clk.h>
34#include <linux/dmaengine.h> 33#include <linux/dmaengine.h>
35#include <linux/dma-mapping.h> 34#include <linux/dma-mapping.h>
35#include <linux/of_device.h>
36#include <linux/pm_runtime.h>
36#include <linux/sh_dma.h> 37#include <linux/sh_dma.h>
37#include <linux/spi/spi.h> 38#include <linux/spi/spi.h>
38#include <linux/spi/rspi.h> 39#include <linux/spi/rspi.h>
@@ -49,7 +50,7 @@
49#define RSPI_SPCKD 0x0c /* Clock Delay Register */ 50#define RSPI_SPCKD 0x0c /* Clock Delay Register */
50#define RSPI_SSLND 0x0d /* Slave Select Negation Delay Register */ 51#define RSPI_SSLND 0x0d /* Slave Select Negation Delay Register */
51#define RSPI_SPND 0x0e /* Next-Access Delay Register */ 52#define RSPI_SPND 0x0e /* Next-Access Delay Register */
52#define RSPI_SPCR2 0x0f /* Control Register 2 */ 53#define RSPI_SPCR2 0x0f /* Control Register 2 (SH only) */
53#define RSPI_SPCMD0 0x10 /* Command Register 0 */ 54#define RSPI_SPCMD0 0x10 /* Command Register 0 */
54#define RSPI_SPCMD1 0x12 /* Command Register 1 */ 55#define RSPI_SPCMD1 0x12 /* Command Register 1 */
55#define RSPI_SPCMD2 0x14 /* Command Register 2 */ 56#define RSPI_SPCMD2 0x14 /* Command Register 2 */
@@ -58,16 +59,23 @@
58#define RSPI_SPCMD5 0x1a /* Command Register 5 */ 59#define RSPI_SPCMD5 0x1a /* Command Register 5 */
59#define RSPI_SPCMD6 0x1c /* Command Register 6 */ 60#define RSPI_SPCMD6 0x1c /* Command Register 6 */
60#define RSPI_SPCMD7 0x1e /* Command Register 7 */ 61#define RSPI_SPCMD7 0x1e /* Command Register 7 */
62#define RSPI_SPCMD(i) (RSPI_SPCMD0 + (i) * 2)
63#define RSPI_NUM_SPCMD 8
64#define RSPI_RZ_NUM_SPCMD 4
65#define QSPI_NUM_SPCMD 4
66
67/* RSPI on RZ only */
61#define RSPI_SPBFCR 0x20 /* Buffer Control Register */ 68#define RSPI_SPBFCR 0x20 /* Buffer Control Register */
62#define RSPI_SPBFDR 0x22 /* Buffer Data Count Setting Register */ 69#define RSPI_SPBFDR 0x22 /* Buffer Data Count Setting Register */
63 70
64/*qspi only */ 71/* QSPI only */
65#define QSPI_SPBFCR 0x18 /* Buffer Control Register */ 72#define QSPI_SPBFCR 0x18 /* Buffer Control Register */
66#define QSPI_SPBDCR 0x1a /* Buffer Data Count Register */ 73#define QSPI_SPBDCR 0x1a /* Buffer Data Count Register */
67#define QSPI_SPBMUL0 0x1c /* Transfer Data Length Multiplier Setting Register 0 */ 74#define QSPI_SPBMUL0 0x1c /* Transfer Data Length Multiplier Setting Register 0 */
68#define QSPI_SPBMUL1 0x20 /* Transfer Data Length Multiplier Setting Register 1 */ 75#define QSPI_SPBMUL1 0x20 /* Transfer Data Length Multiplier Setting Register 1 */
69#define QSPI_SPBMUL2 0x24 /* Transfer Data Length Multiplier Setting Register 2 */ 76#define QSPI_SPBMUL2 0x24 /* Transfer Data Length Multiplier Setting Register 2 */
70#define QSPI_SPBMUL3 0x28 /* Transfer Data Length Multiplier Setting Register 3 */ 77#define QSPI_SPBMUL3 0x28 /* Transfer Data Length Multiplier Setting Register 3 */
78#define QSPI_SPBMUL(i) (QSPI_SPBMUL0 + (i) * 4)
71 79
72/* SPCR - Control Register */ 80/* SPCR - Control Register */
73#define SPCR_SPRIE 0x80 /* Receive Interrupt Enable */ 81#define SPCR_SPRIE 0x80 /* Receive Interrupt Enable */
@@ -104,7 +112,7 @@
104#define SPSR_PERF 0x08 /* Parity Error Flag */ 112#define SPSR_PERF 0x08 /* Parity Error Flag */
105#define SPSR_MODF 0x04 /* Mode Fault Error Flag */ 113#define SPSR_MODF 0x04 /* Mode Fault Error Flag */
106#define SPSR_IDLNF 0x02 /* RSPI Idle Flag */ 114#define SPSR_IDLNF 0x02 /* RSPI Idle Flag */
107#define SPSR_OVRF 0x01 /* Overrun Error Flag */ 115#define SPSR_OVRF 0x01 /* Overrun Error Flag (RSPI only) */
108 116
109/* SPSCR - Sequence Control Register */ 117/* SPSCR - Sequence Control Register */
110#define SPSCR_SPSLN_MASK 0x07 /* Sequence Length Specification */ 118#define SPSCR_SPSLN_MASK 0x07 /* Sequence Length Specification */
@@ -121,13 +129,13 @@
121#define SPDCR_SPLWORD SPDCR_SPLW1 129#define SPDCR_SPLWORD SPDCR_SPLW1
122#define SPDCR_SPLBYTE SPDCR_SPLW0 130#define SPDCR_SPLBYTE SPDCR_SPLW0
123#define SPDCR_SPLW 0x20 /* Access Width Specification (SH) */ 131#define SPDCR_SPLW 0x20 /* Access Width Specification (SH) */
124#define SPDCR_SPRDTD 0x10 /* Receive Transmit Data Select */ 132#define SPDCR_SPRDTD 0x10 /* Receive Transmit Data Select (SH) */
125#define SPDCR_SLSEL1 0x08 133#define SPDCR_SLSEL1 0x08
126#define SPDCR_SLSEL0 0x04 134#define SPDCR_SLSEL0 0x04
127#define SPDCR_SLSEL_MASK 0x0c /* SSL1 Output Select */ 135#define SPDCR_SLSEL_MASK 0x0c /* SSL1 Output Select (SH) */
128#define SPDCR_SPFC1 0x02 136#define SPDCR_SPFC1 0x02
129#define SPDCR_SPFC0 0x01 137#define SPDCR_SPFC0 0x01
130#define SPDCR_SPFC_MASK 0x03 /* Frame Count Setting (1-4) */ 138#define SPDCR_SPFC_MASK 0x03 /* Frame Count Setting (1-4) (SH) */
131 139
132/* SPCKD - Clock Delay Register */ 140/* SPCKD - Clock Delay Register */
133#define SPCKD_SCKDL_MASK 0x07 /* Clock Delay Setting (1-8) */ 141#define SPCKD_SCKDL_MASK 0x07 /* Clock Delay Setting (1-8) */
@@ -151,7 +159,7 @@
151#define SPCMD_LSBF 0x1000 /* LSB First */ 159#define SPCMD_LSBF 0x1000 /* LSB First */
152#define SPCMD_SPB_MASK 0x0f00 /* Data Length Setting */ 160#define SPCMD_SPB_MASK 0x0f00 /* Data Length Setting */
153#define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK) 161#define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK)
154#define SPCMD_SPB_8BIT 0x0000 /* qspi only */ 162#define SPCMD_SPB_8BIT 0x0000 /* QSPI only */
155#define SPCMD_SPB_16BIT 0x0100 163#define SPCMD_SPB_16BIT 0x0100
156#define SPCMD_SPB_20BIT 0x0000 164#define SPCMD_SPB_20BIT 0x0000
157#define SPCMD_SPB_24BIT 0x0100 165#define SPCMD_SPB_24BIT 0x0100
@@ -170,8 +178,8 @@
170#define SPCMD_CPHA 0x0001 /* Clock Phase Setting */ 178#define SPCMD_CPHA 0x0001 /* Clock Phase Setting */
171 179
172/* SPBFCR - Buffer Control Register */ 180/* SPBFCR - Buffer Control Register */
173#define SPBFCR_TXRST 0x80 /* Transmit Buffer Data Reset (qspi only) */ 181#define SPBFCR_TXRST 0x80 /* Transmit Buffer Data Reset */
174#define SPBFCR_RXRST 0x40 /* Receive Buffer Data Reset (qspi only) */ 182#define SPBFCR_RXRST 0x40 /* Receive Buffer Data Reset */
175#define SPBFCR_TXTRG_MASK 0x30 /* Transmit Buffer Data Triggering Number */ 183#define SPBFCR_TXTRG_MASK 0x30 /* Transmit Buffer Data Triggering Number */
176#define SPBFCR_RXTRG_MASK 0x07 /* Receive Buffer Data Triggering Number */ 184#define SPBFCR_RXTRG_MASK 0x07 /* Receive Buffer Data Triggering Number */
177 185
@@ -181,22 +189,21 @@ struct rspi_data {
181 void __iomem *addr; 189 void __iomem *addr;
182 u32 max_speed_hz; 190 u32 max_speed_hz;
183 struct spi_master *master; 191 struct spi_master *master;
184 struct list_head queue;
185 struct work_struct ws;
186 wait_queue_head_t wait; 192 wait_queue_head_t wait;
187 spinlock_t lock;
188 struct clk *clk; 193 struct clk *clk;
189 u8 spsr;
190 u16 spcmd; 194 u16 spcmd;
195 u8 spsr;
196 u8 sppcr;
197 int rx_irq, tx_irq;
191 const struct spi_ops *ops; 198 const struct spi_ops *ops;
192 199
193 /* for dmaengine */ 200 /* for dmaengine */
194 struct dma_chan *chan_tx; 201 struct dma_chan *chan_tx;
195 struct dma_chan *chan_rx; 202 struct dma_chan *chan_rx;
196 int irq;
197 203
198 unsigned dma_width_16bit:1; 204 unsigned dma_width_16bit:1;
199 unsigned dma_callbacked:1; 205 unsigned dma_callbacked:1;
206 unsigned byte_access:1;
200}; 207};
201 208
202static void rspi_write8(const struct rspi_data *rspi, u8 data, u16 offset) 209static void rspi_write8(const struct rspi_data *rspi, u8 data, u16 offset)
@@ -224,34 +231,47 @@ static u16 rspi_read16(const struct rspi_data *rspi, u16 offset)
224 return ioread16(rspi->addr + offset); 231 return ioread16(rspi->addr + offset);
225} 232}
226 233
234static void rspi_write_data(const struct rspi_data *rspi, u16 data)
235{
236 if (rspi->byte_access)
237 rspi_write8(rspi, data, RSPI_SPDR);
238 else /* 16 bit */
239 rspi_write16(rspi, data, RSPI_SPDR);
240}
241
242static u16 rspi_read_data(const struct rspi_data *rspi)
243{
244 if (rspi->byte_access)
245 return rspi_read8(rspi, RSPI_SPDR);
246 else /* 16 bit */
247 return rspi_read16(rspi, RSPI_SPDR);
248}
249
227/* optional functions */ 250/* optional functions */
228struct spi_ops { 251struct spi_ops {
229 int (*set_config_register)(const struct rspi_data *rspi, 252 int (*set_config_register)(struct rspi_data *rspi, int access_size);
230 int access_size); 253 int (*transfer_one)(struct spi_master *master, struct spi_device *spi,
231 int (*send_pio)(struct rspi_data *rspi, struct spi_message *mesg, 254 struct spi_transfer *xfer);
232 struct spi_transfer *t); 255 u16 mode_bits;
233 int (*receive_pio)(struct rspi_data *rspi, struct spi_message *mesg,
234 struct spi_transfer *t);
235
236}; 256};
237 257
238/* 258/*
239 * functions for RSPI 259 * functions for RSPI on legacy SH
240 */ 260 */
241static int rspi_set_config_register(const struct rspi_data *rspi, 261static int rspi_set_config_register(struct rspi_data *rspi, int access_size)
242 int access_size)
243{ 262{
244 int spbr; 263 int spbr;
245 264
246 /* Sets output mode(CMOS) and MOSI signal(from previous transfer) */ 265 /* Sets output mode, MOSI signal, and (optionally) loopback */
247 rspi_write8(rspi, 0x00, RSPI_SPPCR); 266 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
248 267
249 /* Sets transfer bit rate */ 268 /* Sets transfer bit rate */
250 spbr = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz) - 1; 269 spbr = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz) - 1;
251 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); 270 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
252 271
253 /* Sets number of frames to be used: 1 frame */ 272 /* Disable dummy transmission, set 16-bit word access, 1 frame */
254 rspi_write8(rspi, 0x00, RSPI_SPDCR); 273 rspi_write8(rspi, 0, RSPI_SPDCR);
274 rspi->byte_access = 0;
255 275
256 /* Sets RSPCK, SSL, next-access delay value */ 276 /* Sets RSPCK, SSL, next-access delay value */
257 rspi_write8(rspi, 0x00, RSPI_SPCKD); 277 rspi_write8(rspi, 0x00, RSPI_SPCKD);
@@ -262,8 +282,41 @@ static int rspi_set_config_register(const struct rspi_data *rspi,
262 rspi_write8(rspi, 0x00, RSPI_SPCR2); 282 rspi_write8(rspi, 0x00, RSPI_SPCR2);
263 283
264 /* Sets SPCMD */ 284 /* Sets SPCMD */
265 rspi_write16(rspi, SPCMD_SPB_8_TO_16(access_size) | rspi->spcmd, 285 rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);
266 RSPI_SPCMD0); 286 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
287
288 /* Sets RSPI mode */
289 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
290
291 return 0;
292}
293
294/*
295 * functions for RSPI on RZ
296 */
297static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size)
298{
299 int spbr;
300
301 /* Sets output mode, MOSI signal, and (optionally) loopback */
302 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
303
304 /* Sets transfer bit rate */
305 spbr = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz) - 1;
306 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
307
308 /* Disable dummy transmission, set byte access */
309 rspi_write8(rspi, SPDCR_SPLBYTE, RSPI_SPDCR);
310 rspi->byte_access = 1;
311
312 /* Sets RSPCK, SSL, next-access delay value */
313 rspi_write8(rspi, 0x00, RSPI_SPCKD);
314 rspi_write8(rspi, 0x00, RSPI_SSLND);
315 rspi_write8(rspi, 0x00, RSPI_SPND);
316
317 /* Sets SPCMD */
318 rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);
319 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
267 320
268 /* Sets RSPI mode */ 321 /* Sets RSPI mode */
269 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR); 322 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
@@ -274,21 +327,20 @@ static int rspi_set_config_register(const struct rspi_data *rspi,
274/* 327/*
275 * functions for QSPI 328 * functions for QSPI
276 */ 329 */
277static int qspi_set_config_register(const struct rspi_data *rspi, 330static int qspi_set_config_register(struct rspi_data *rspi, int access_size)
278 int access_size)
279{ 331{
280 u16 spcmd;
281 int spbr; 332 int spbr;
282 333
283 /* Sets output mode(CMOS) and MOSI signal(from previous transfer) */ 334 /* Sets output mode, MOSI signal, and (optionally) loopback */
284 rspi_write8(rspi, 0x00, RSPI_SPPCR); 335 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
285 336
286 /* Sets transfer bit rate */ 337 /* Sets transfer bit rate */
287 spbr = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz); 338 spbr = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz);
288 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); 339 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
289 340
290 /* Sets number of frames to be used: 1 frame */ 341 /* Disable dummy transmission, set byte access */
291 rspi_write8(rspi, 0x00, RSPI_SPDCR); 342 rspi_write8(rspi, 0, RSPI_SPDCR);
343 rspi->byte_access = 1;
292 344
293 /* Sets RSPCK, SSL, next-access delay value */ 345 /* Sets RSPCK, SSL, next-access delay value */
294 rspi_write8(rspi, 0x00, RSPI_SPCKD); 346 rspi_write8(rspi, 0x00, RSPI_SPCKD);
@@ -297,13 +349,13 @@ static int qspi_set_config_register(const struct rspi_data *rspi,
297 349
298 /* Data Length Setting */ 350 /* Data Length Setting */
299 if (access_size == 8) 351 if (access_size == 8)
300 spcmd = SPCMD_SPB_8BIT; 352 rspi->spcmd |= SPCMD_SPB_8BIT;
301 else if (access_size == 16) 353 else if (access_size == 16)
302 spcmd = SPCMD_SPB_16BIT; 354 rspi->spcmd |= SPCMD_SPB_16BIT;
303 else 355 else
304 spcmd = SPCMD_SPB_32BIT; 356 rspi->spcmd |= SPCMD_SPB_32BIT;
305 357
306 spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | rspi->spcmd | SPCMD_SPNDEN; 358 rspi->spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | SPCMD_SPNDEN;
307 359
308 /* Resets transfer data length */ 360 /* Resets transfer data length */
309 rspi_write32(rspi, 0, QSPI_SPBMUL0); 361 rspi_write32(rspi, 0, QSPI_SPBMUL0);
@@ -314,9 +366,9 @@ static int qspi_set_config_register(const struct rspi_data *rspi,
314 rspi_write8(rspi, 0x00, QSPI_SPBFCR); 366 rspi_write8(rspi, 0x00, QSPI_SPBFCR);
315 367
316 /* Sets SPCMD */ 368 /* Sets SPCMD */
317 rspi_write16(rspi, spcmd, RSPI_SPCMD0); 369 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
318 370
319 /* Enables SPI function in a master mode */ 371 /* Enables SPI function in master mode */
320 rspi_write8(rspi, SPCR_SPE | SPCR_MSTR, RSPI_SPCR); 372 rspi_write8(rspi, SPCR_SPE | SPCR_MSTR, RSPI_SPCR);
321 373
322 return 0; 374 return 0;
@@ -340,6 +392,9 @@ static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask,
340 int ret; 392 int ret;
341 393
342 rspi->spsr = rspi_read8(rspi, RSPI_SPSR); 394 rspi->spsr = rspi_read8(rspi, RSPI_SPSR);
395 if (rspi->spsr & wait_mask)
396 return 0;
397
343 rspi_enable_irq(rspi, enable_bit); 398 rspi_enable_irq(rspi, enable_bit);
344 ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ); 399 ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ);
345 if (ret == 0 && !(rspi->spsr & wait_mask)) 400 if (ret == 0 && !(rspi->spsr & wait_mask))
@@ -348,78 +403,39 @@ static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask,
348 return 0; 403 return 0;
349} 404}
350 405
351static void rspi_assert_ssl(const struct rspi_data *rspi) 406static int rspi_data_out(struct rspi_data *rspi, u8 data)
352{
353 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR);
354}
355
356static void rspi_negate_ssl(const struct rspi_data *rspi)
357{ 407{
358 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR); 408 if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) {
409 dev_err(&rspi->master->dev, "transmit timeout\n");
410 return -ETIMEDOUT;
411 }
412 rspi_write_data(rspi, data);
413 return 0;
359} 414}
360 415
361static int rspi_send_pio(struct rspi_data *rspi, struct spi_message *mesg, 416static int rspi_data_in(struct rspi_data *rspi)
362 struct spi_transfer *t)
363{ 417{
364 int remain = t->len; 418 u8 data;
365 const u8 *data = t->tx_buf;
366 while (remain > 0) {
367 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_TXMD,
368 RSPI_SPCR);
369
370 if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) {
371 dev_err(&rspi->master->dev,
372 "%s: tx empty timeout\n", __func__);
373 return -ETIMEDOUT;
374 }
375 419
376 rspi_write16(rspi, *data, RSPI_SPDR); 420 if (rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE) < 0) {
377 data++; 421 dev_err(&rspi->master->dev, "receive timeout\n");
378 remain--; 422 return -ETIMEDOUT;
379 } 423 }
380 424 data = rspi_read_data(rspi);
381 /* Waiting for the last transmission */ 425 return data;
382 rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
383
384 return 0;
385} 426}
386 427
387static int qspi_send_pio(struct rspi_data *rspi, struct spi_message *mesg, 428static int rspi_data_out_in(struct rspi_data *rspi, u8 data)
388 struct spi_transfer *t)
389{ 429{
390 int remain = t->len; 430 int ret;
391 const u8 *data = t->tx_buf;
392
393 rspi_write8(rspi, SPBFCR_TXRST, QSPI_SPBFCR);
394 rspi_write8(rspi, 0x00, QSPI_SPBFCR);
395
396 while (remain > 0) {
397
398 if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) {
399 dev_err(&rspi->master->dev,
400 "%s: tx empty timeout\n", __func__);
401 return -ETIMEDOUT;
402 }
403 rspi_write8(rspi, *data++, RSPI_SPDR);
404
405 if (rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE) < 0) {
406 dev_err(&rspi->master->dev,
407 "%s: receive timeout\n", __func__);
408 return -ETIMEDOUT;
409 }
410 rspi_read8(rspi, RSPI_SPDR);
411
412 remain--;
413 }
414 431
415 /* Waiting for the last transmission */ 432 ret = rspi_data_out(rspi, data);
416 rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE); 433 if (ret < 0)
434 return ret;
417 435
418 return 0; 436 return rspi_data_in(rspi);
419} 437}
420 438
421#define send_pio(spi, mesg, t) spi->ops->send_pio(spi, mesg, t)
422
423static void rspi_dma_complete(void *arg) 439static void rspi_dma_complete(void *arg)
424{ 440{
425 struct rspi_data *rspi = arg; 441 struct rspi_data *rspi = arg;
@@ -471,7 +487,7 @@ static int rspi_send_dma(struct rspi_data *rspi, struct spi_transfer *t)
471 struct scatterlist sg; 487 struct scatterlist sg;
472 const void *buf = NULL; 488 const void *buf = NULL;
473 struct dma_async_tx_descriptor *desc; 489 struct dma_async_tx_descriptor *desc;
474 unsigned len; 490 unsigned int len;
475 int ret = 0; 491 int ret = 0;
476 492
477 if (rspi->dma_width_16bit) { 493 if (rspi->dma_width_16bit) {
@@ -509,7 +525,7 @@ static int rspi_send_dma(struct rspi_data *rspi, struct spi_transfer *t)
509 * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be 525 * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be
510 * called. So, this driver disables the IRQ while DMA transfer. 526 * called. So, this driver disables the IRQ while DMA transfer.
511 */ 527 */
512 disable_irq(rspi->irq); 528 disable_irq(rspi->tx_irq);
513 529
514 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_TXMD, RSPI_SPCR); 530 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_TXMD, RSPI_SPCR);
515 rspi_enable_irq(rspi, SPCR_SPTIE); 531 rspi_enable_irq(rspi, SPCR_SPTIE);
@@ -528,7 +544,7 @@ static int rspi_send_dma(struct rspi_data *rspi, struct spi_transfer *t)
528 ret = -ETIMEDOUT; 544 ret = -ETIMEDOUT;
529 rspi_disable_irq(rspi, SPCR_SPTIE); 545 rspi_disable_irq(rspi, SPCR_SPTIE);
530 546
531 enable_irq(rspi->irq); 547 enable_irq(rspi->tx_irq);
532 548
533end: 549end:
534 rspi_dma_unmap_sg(&sg, rspi->chan_tx, DMA_TO_DEVICE); 550 rspi_dma_unmap_sg(&sg, rspi->chan_tx, DMA_TO_DEVICE);
@@ -545,46 +561,17 @@ static void rspi_receive_init(const struct rspi_data *rspi)
545 561
546 spsr = rspi_read8(rspi, RSPI_SPSR); 562 spsr = rspi_read8(rspi, RSPI_SPSR);
547 if (spsr & SPSR_SPRF) 563 if (spsr & SPSR_SPRF)
548 rspi_read16(rspi, RSPI_SPDR); /* dummy read */ 564 rspi_read_data(rspi); /* dummy read */
549 if (spsr & SPSR_OVRF) 565 if (spsr & SPSR_OVRF)
550 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF, 566 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF,
551 RSPI_SPSR); 567 RSPI_SPSR);
552} 568}
553 569
554static int rspi_receive_pio(struct rspi_data *rspi, struct spi_message *mesg, 570static void rspi_rz_receive_init(const struct rspi_data *rspi)
555 struct spi_transfer *t)
556{ 571{
557 int remain = t->len;
558 u8 *data;
559
560 rspi_receive_init(rspi); 572 rspi_receive_init(rspi);
561 573 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, RSPI_SPBFCR);
562 data = t->rx_buf; 574 rspi_write8(rspi, 0, RSPI_SPBFCR);
563 while (remain > 0) {
564 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_TXMD,
565 RSPI_SPCR);
566
567 if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) {
568 dev_err(&rspi->master->dev,
569 "%s: tx empty timeout\n", __func__);
570 return -ETIMEDOUT;
571 }
572 /* dummy write for generate clock */
573 rspi_write16(rspi, DUMMY_DATA, RSPI_SPDR);
574
575 if (rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE) < 0) {
576 dev_err(&rspi->master->dev,
577 "%s: receive timeout\n", __func__);
578 return -ETIMEDOUT;
579 }
580 /* SPDR allows 16 or 32-bit access only */
581 *data = (u8)rspi_read16(rspi, RSPI_SPDR);
582
583 data++;
584 remain--;
585 }
586
587 return 0;
588} 575}
589 576
590static void qspi_receive_init(const struct rspi_data *rspi) 577static void qspi_receive_init(const struct rspi_data *rspi)
@@ -593,51 +580,17 @@ static void qspi_receive_init(const struct rspi_data *rspi)
593 580
594 spsr = rspi_read8(rspi, RSPI_SPSR); 581 spsr = rspi_read8(rspi, RSPI_SPSR);
595 if (spsr & SPSR_SPRF) 582 if (spsr & SPSR_SPRF)
596 rspi_read8(rspi, RSPI_SPDR); /* dummy read */ 583 rspi_read_data(rspi); /* dummy read */
597 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR); 584 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR);
598 rspi_write8(rspi, 0x00, QSPI_SPBFCR); 585 rspi_write8(rspi, 0, QSPI_SPBFCR);
599} 586}
600 587
601static int qspi_receive_pio(struct rspi_data *rspi, struct spi_message *mesg,
602 struct spi_transfer *t)
603{
604 int remain = t->len;
605 u8 *data;
606
607 qspi_receive_init(rspi);
608
609 data = t->rx_buf;
610 while (remain > 0) {
611
612 if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) {
613 dev_err(&rspi->master->dev,
614 "%s: tx empty timeout\n", __func__);
615 return -ETIMEDOUT;
616 }
617 /* dummy write for generate clock */
618 rspi_write8(rspi, DUMMY_DATA, RSPI_SPDR);
619
620 if (rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE) < 0) {
621 dev_err(&rspi->master->dev,
622 "%s: receive timeout\n", __func__);
623 return -ETIMEDOUT;
624 }
625 /* SPDR allows 8, 16 or 32-bit access */
626 *data++ = rspi_read8(rspi, RSPI_SPDR);
627 remain--;
628 }
629
630 return 0;
631}
632
633#define receive_pio(spi, mesg, t) spi->ops->receive_pio(spi, mesg, t)
634
635static int rspi_receive_dma(struct rspi_data *rspi, struct spi_transfer *t) 588static int rspi_receive_dma(struct rspi_data *rspi, struct spi_transfer *t)
636{ 589{
637 struct scatterlist sg, sg_dummy; 590 struct scatterlist sg, sg_dummy;
638 void *dummy = NULL, *rx_buf = NULL; 591 void *dummy = NULL, *rx_buf = NULL;
639 struct dma_async_tx_descriptor *desc, *desc_dummy; 592 struct dma_async_tx_descriptor *desc, *desc_dummy;
640 unsigned len; 593 unsigned int len;
641 int ret = 0; 594 int ret = 0;
642 595
643 if (rspi->dma_width_16bit) { 596 if (rspi->dma_width_16bit) {
@@ -695,7 +648,9 @@ static int rspi_receive_dma(struct rspi_data *rspi, struct spi_transfer *t)
695 * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be 648 * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be
696 * called. So, this driver disables the IRQ while DMA transfer. 649 * called. So, this driver disables the IRQ while DMA transfer.
697 */ 650 */
698 disable_irq(rspi->irq); 651 disable_irq(rspi->tx_irq);
652 if (rspi->rx_irq != rspi->tx_irq)
653 disable_irq(rspi->rx_irq);
699 654
700 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_TXMD, RSPI_SPCR); 655 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_TXMD, RSPI_SPCR);
701 rspi_enable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE); 656 rspi_enable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE);
@@ -718,7 +673,9 @@ static int rspi_receive_dma(struct rspi_data *rspi, struct spi_transfer *t)
718 ret = -ETIMEDOUT; 673 ret = -ETIMEDOUT;
719 rspi_disable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE); 674 rspi_disable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE);
720 675
721 enable_irq(rspi->irq); 676 enable_irq(rspi->tx_irq);
677 if (rspi->rx_irq != rspi->tx_irq)
678 enable_irq(rspi->rx_irq);
722 679
723end: 680end:
724 rspi_dma_unmap_sg(&sg, rspi->chan_rx, DMA_FROM_DEVICE); 681 rspi_dma_unmap_sg(&sg, rspi->chan_rx, DMA_FROM_DEVICE);
@@ -746,56 +703,175 @@ static int rspi_is_dma(const struct rspi_data *rspi, struct spi_transfer *t)
746 return 0; 703 return 0;
747} 704}
748 705
749static void rspi_work(struct work_struct *work) 706static int rspi_transfer_out_in(struct rspi_data *rspi,
707 struct spi_transfer *xfer)
750{ 708{
751 struct rspi_data *rspi = container_of(work, struct rspi_data, ws); 709 int remain = xfer->len, ret;
752 struct spi_message *mesg; 710 const u8 *tx_buf = xfer->tx_buf;
753 struct spi_transfer *t; 711 u8 *rx_buf = xfer->rx_buf;
754 unsigned long flags; 712 u8 spcr, data;
755 int ret;
756 713
757 while (1) { 714 rspi_receive_init(rspi);
758 spin_lock_irqsave(&rspi->lock, flags); 715
759 if (list_empty(&rspi->queue)) { 716 spcr = rspi_read8(rspi, RSPI_SPCR);
760 spin_unlock_irqrestore(&rspi->lock, flags); 717 if (rx_buf)
761 break; 718 spcr &= ~SPCR_TXMD;
762 } 719 else
763 mesg = list_entry(rspi->queue.next, struct spi_message, queue); 720 spcr |= SPCR_TXMD;
764 list_del_init(&mesg->queue); 721 rspi_write8(rspi, spcr, RSPI_SPCR);
765 spin_unlock_irqrestore(&rspi->lock, flags); 722
766 723 while (remain > 0) {
767 rspi_assert_ssl(rspi); 724 data = tx_buf ? *tx_buf++ : DUMMY_DATA;
768 725 ret = rspi_data_out(rspi, data);
769 list_for_each_entry(t, &mesg->transfers, transfer_list) { 726 if (ret < 0)
770 if (t->tx_buf) { 727 return ret;
771 if (rspi_is_dma(rspi, t)) 728 if (rx_buf) {
772 ret = rspi_send_dma(rspi, t); 729 ret = rspi_data_in(rspi);
773 else 730 if (ret < 0)
774 ret = send_pio(rspi, mesg, t); 731 return ret;
775 if (ret < 0) 732 *rx_buf++ = ret;
776 goto error;
777 }
778 if (t->rx_buf) {
779 if (rspi_is_dma(rspi, t))
780 ret = rspi_receive_dma(rspi, t);
781 else
782 ret = receive_pio(rspi, mesg, t);
783 if (ret < 0)
784 goto error;
785 }
786 mesg->actual_length += t->len;
787 } 733 }
788 rspi_negate_ssl(rspi); 734 remain--;
735 }
736
737 /* Wait for the last transmission */
738 rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
739
740 return 0;
741}
742
743static int rspi_transfer_one(struct spi_master *master, struct spi_device *spi,
744 struct spi_transfer *xfer)
745{
746 struct rspi_data *rspi = spi_master_get_devdata(master);
747 int ret;
748
749 if (!rspi_is_dma(rspi, xfer))
750 return rspi_transfer_out_in(rspi, xfer);
751
752 if (xfer->tx_buf) {
753 ret = rspi_send_dma(rspi, xfer);
754 if (ret < 0)
755 return ret;
756 }
757 if (xfer->rx_buf)
758 return rspi_receive_dma(rspi, xfer);
759
760 return 0;
761}
762
763static int rspi_rz_transfer_out_in(struct rspi_data *rspi,
764 struct spi_transfer *xfer)
765{
766 int remain = xfer->len, ret;
767 const u8 *tx_buf = xfer->tx_buf;
768 u8 *rx_buf = xfer->rx_buf;
769 u8 data;
770
771 rspi_rz_receive_init(rspi);
772
773 while (remain > 0) {
774 data = tx_buf ? *tx_buf++ : DUMMY_DATA;
775 ret = rspi_data_out_in(rspi, data);
776 if (ret < 0)
777 return ret;
778 if (rx_buf)
779 *rx_buf++ = ret;
780 remain--;
781 }
782
783 /* Wait for the last transmission */
784 rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
785
786 return 0;
787}
788
789static int rspi_rz_transfer_one(struct spi_master *master,
790 struct spi_device *spi,
791 struct spi_transfer *xfer)
792{
793 struct rspi_data *rspi = spi_master_get_devdata(master);
794
795 return rspi_rz_transfer_out_in(rspi, xfer);
796}
797
798static int qspi_transfer_out_in(struct rspi_data *rspi,
799 struct spi_transfer *xfer)
800{
801 int remain = xfer->len, ret;
802 const u8 *tx_buf = xfer->tx_buf;
803 u8 *rx_buf = xfer->rx_buf;
804 u8 data;
789 805
790 mesg->status = 0; 806 qspi_receive_init(rspi);
791 mesg->complete(mesg->context); 807
808 while (remain > 0) {
809 data = tx_buf ? *tx_buf++ : DUMMY_DATA;
810 ret = rspi_data_out_in(rspi, data);
811 if (ret < 0)
812 return ret;
813 if (rx_buf)
814 *rx_buf++ = ret;
815 remain--;
816 }
817
818 /* Wait for the last transmission */
819 rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
820
821 return 0;
822}
823
824static int qspi_transfer_out(struct rspi_data *rspi, struct spi_transfer *xfer)
825{
826 const u8 *buf = xfer->tx_buf;
827 unsigned int i;
828 int ret;
829
830 for (i = 0; i < xfer->len; i++) {
831 ret = rspi_data_out(rspi, *buf++);
832 if (ret < 0)
833 return ret;
792 } 834 }
793 835
794 return; 836 /* Wait for the last transmission */
837 rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
795 838
796error: 839 return 0;
797 mesg->status = ret; 840}
798 mesg->complete(mesg->context); 841
842static int qspi_transfer_in(struct rspi_data *rspi, struct spi_transfer *xfer)
843{
844 u8 *buf = xfer->rx_buf;
845 unsigned int i;
846 int ret;
847
848 for (i = 0; i < xfer->len; i++) {
849 ret = rspi_data_in(rspi);
850 if (ret < 0)
851 return ret;
852 *buf++ = ret;
853 }
854
855 return 0;
856}
857
858static int qspi_transfer_one(struct spi_master *master, struct spi_device *spi,
859 struct spi_transfer *xfer)
860{
861 struct rspi_data *rspi = spi_master_get_devdata(master);
862
863 if (spi->mode & SPI_LOOP) {
864 return qspi_transfer_out_in(rspi, xfer);
865 } else if (xfer->tx_buf && xfer->tx_nbits > SPI_NBITS_SINGLE) {
866 /* Quad or Dual SPI Write */
867 return qspi_transfer_out(rspi, xfer);
868 } else if (xfer->rx_buf && xfer->rx_nbits > SPI_NBITS_SINGLE) {
869 /* Quad or Dual SPI Read */
870 return qspi_transfer_in(rspi, xfer);
871 } else {
872 /* Single SPI Transfer */
873 return qspi_transfer_out_in(rspi, xfer);
874 }
799} 875}
800 876
801static int rspi_setup(struct spi_device *spi) 877static int rspi_setup(struct spi_device *spi)
@@ -810,32 +886,115 @@ static int rspi_setup(struct spi_device *spi)
810 if (spi->mode & SPI_CPHA) 886 if (spi->mode & SPI_CPHA)
811 rspi->spcmd |= SPCMD_CPHA; 887 rspi->spcmd |= SPCMD_CPHA;
812 888
889 /* CMOS output mode and MOSI signal from previous transfer */
890 rspi->sppcr = 0;
891 if (spi->mode & SPI_LOOP)
892 rspi->sppcr |= SPPCR_SPLP;
893
813 set_config_register(rspi, 8); 894 set_config_register(rspi, 8);
814 895
815 return 0; 896 return 0;
816} 897}
817 898
818static int rspi_transfer(struct spi_device *spi, struct spi_message *mesg) 899static u16 qspi_transfer_mode(const struct spi_transfer *xfer)
819{ 900{
820 struct rspi_data *rspi = spi_master_get_devdata(spi->master); 901 if (xfer->tx_buf)
821 unsigned long flags; 902 switch (xfer->tx_nbits) {
903 case SPI_NBITS_QUAD:
904 return SPCMD_SPIMOD_QUAD;
905 case SPI_NBITS_DUAL:
906 return SPCMD_SPIMOD_DUAL;
907 default:
908 return 0;
909 }
910 if (xfer->rx_buf)
911 switch (xfer->rx_nbits) {
912 case SPI_NBITS_QUAD:
913 return SPCMD_SPIMOD_QUAD | SPCMD_SPRW;
914 case SPI_NBITS_DUAL:
915 return SPCMD_SPIMOD_DUAL | SPCMD_SPRW;
916 default:
917 return 0;
918 }
919
920 return 0;
921}
822 922
823 mesg->actual_length = 0; 923static int qspi_setup_sequencer(struct rspi_data *rspi,
824 mesg->status = -EINPROGRESS; 924 const struct spi_message *msg)
925{
926 const struct spi_transfer *xfer;
927 unsigned int i = 0, len = 0;
928 u16 current_mode = 0xffff, mode;
929
930 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
931 mode = qspi_transfer_mode(xfer);
932 if (mode == current_mode) {
933 len += xfer->len;
934 continue;
935 }
936
937 /* Transfer mode change */
938 if (i) {
939 /* Set transfer data length of previous transfer */
940 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1));
941 }
825 942
826 spin_lock_irqsave(&rspi->lock, flags); 943 if (i >= QSPI_NUM_SPCMD) {
827 list_add_tail(&mesg->queue, &rspi->queue); 944 dev_err(&msg->spi->dev,
828 schedule_work(&rspi->ws); 945 "Too many different transfer modes");
829 spin_unlock_irqrestore(&rspi->lock, flags); 946 return -EINVAL;
947 }
948
949 /* Program transfer mode for this transfer */
950 rspi_write16(rspi, rspi->spcmd | mode, RSPI_SPCMD(i));
951 current_mode = mode;
952 len = xfer->len;
953 i++;
954 }
955 if (i) {
956 /* Set final transfer data length and sequence length */
957 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1));
958 rspi_write8(rspi, i - 1, RSPI_SPSCR);
959 }
830 960
831 return 0; 961 return 0;
832} 962}
833 963
834static void rspi_cleanup(struct spi_device *spi) 964static int rspi_prepare_message(struct spi_master *master,
965 struct spi_message *msg)
835{ 966{
967 struct rspi_data *rspi = spi_master_get_devdata(master);
968 int ret;
969
970 if (msg->spi->mode &
971 (SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD)) {
972 /* Setup sequencer for messages with multiple transfer modes */
973 ret = qspi_setup_sequencer(rspi, msg);
974 if (ret < 0)
975 return ret;
976 }
977
978 /* Enable SPI function in master mode */
979 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR);
980 return 0;
836} 981}
837 982
838static irqreturn_t rspi_irq(int irq, void *_sr) 983static int rspi_unprepare_message(struct spi_master *master,
984 struct spi_message *msg)
985{
986 struct rspi_data *rspi = spi_master_get_devdata(master);
987
988 /* Disable SPI function */
989 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR);
990
991 /* Reset sequencer for Single SPI Transfers */
992 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
993 rspi_write8(rspi, 0, RSPI_SPSCR);
994 return 0;
995}
996
997static irqreturn_t rspi_irq_mux(int irq, void *_sr)
839{ 998{
840 struct rspi_data *rspi = _sr; 999 struct rspi_data *rspi = _sr;
841 u8 spsr; 1000 u8 spsr;
@@ -857,6 +1016,36 @@ static irqreturn_t rspi_irq(int irq, void *_sr)
857 return ret; 1016 return ret;
858} 1017}
859 1018
1019static irqreturn_t rspi_irq_rx(int irq, void *_sr)
1020{
1021 struct rspi_data *rspi = _sr;
1022 u8 spsr;
1023
1024 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
1025 if (spsr & SPSR_SPRF) {
1026 rspi_disable_irq(rspi, SPCR_SPRIE);
1027 wake_up(&rspi->wait);
1028 return IRQ_HANDLED;
1029 }
1030
1031 return 0;
1032}
1033
1034static irqreturn_t rspi_irq_tx(int irq, void *_sr)
1035{
1036 struct rspi_data *rspi = _sr;
1037 u8 spsr;
1038
1039 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
1040 if (spsr & SPSR_SPTEF) {
1041 rspi_disable_irq(rspi, SPCR_SPTIE);
1042 wake_up(&rspi->wait);
1043 return IRQ_HANDLED;
1044 }
1045
1046 return 0;
1047}
1048
860static int rspi_request_dma(struct rspi_data *rspi, 1049static int rspi_request_dma(struct rspi_data *rspi,
861 struct platform_device *pdev) 1050 struct platform_device *pdev)
862{ 1051{
@@ -923,34 +1112,89 @@ static int rspi_remove(struct platform_device *pdev)
923 struct rspi_data *rspi = platform_get_drvdata(pdev); 1112 struct rspi_data *rspi = platform_get_drvdata(pdev);
924 1113
925 rspi_release_dma(rspi); 1114 rspi_release_dma(rspi);
926 clk_disable(rspi->clk); 1115 pm_runtime_disable(&pdev->dev);
927 1116
928 return 0; 1117 return 0;
929} 1118}
930 1119
1120static const struct spi_ops rspi_ops = {
1121 .set_config_register = rspi_set_config_register,
1122 .transfer_one = rspi_transfer_one,
1123 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP,
1124};
1125
1126static const struct spi_ops rspi_rz_ops = {
1127 .set_config_register = rspi_rz_set_config_register,
1128 .transfer_one = rspi_rz_transfer_one,
1129 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP,
1130};
1131
1132static const struct spi_ops qspi_ops = {
1133 .set_config_register = qspi_set_config_register,
1134 .transfer_one = qspi_transfer_one,
1135 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP |
1136 SPI_TX_DUAL | SPI_TX_QUAD |
1137 SPI_RX_DUAL | SPI_RX_QUAD,
1138};
1139
1140#ifdef CONFIG_OF
1141static const struct of_device_id rspi_of_match[] = {
1142 /* RSPI on legacy SH */
1143 { .compatible = "renesas,rspi", .data = &rspi_ops },
1144 /* RSPI on RZ/A1H */
1145 { .compatible = "renesas,rspi-rz", .data = &rspi_rz_ops },
1146 /* QSPI on R-Car Gen2 */
1147 { .compatible = "renesas,qspi", .data = &qspi_ops },
1148 { /* sentinel */ }
1149};
1150
1151MODULE_DEVICE_TABLE(of, rspi_of_match);
1152
1153static int rspi_parse_dt(struct device *dev, struct spi_master *master)
1154{
1155 u32 num_cs;
1156 int error;
1157
1158 /* Parse DT properties */
1159 error = of_property_read_u32(dev->of_node, "num-cs", &num_cs);
1160 if (error) {
1161 dev_err(dev, "of_property_read_u32 num-cs failed %d\n", error);
1162 return error;
1163 }
1164
1165 master->num_chipselect = num_cs;
1166 return 0;
1167}
1168#else
1169#define rspi_of_match NULL
1170static inline int rspi_parse_dt(struct device *dev, struct spi_master *master)
1171{
1172 return -EINVAL;
1173}
1174#endif /* CONFIG_OF */
1175
1176static int rspi_request_irq(struct device *dev, unsigned int irq,
1177 irq_handler_t handler, const char *suffix,
1178 void *dev_id)
1179{
1180 const char *base = dev_name(dev);
1181 size_t len = strlen(base) + strlen(suffix) + 2;
1182 char *name = devm_kzalloc(dev, len, GFP_KERNEL);
1183 if (!name)
1184 return -ENOMEM;
1185 snprintf(name, len, "%s:%s", base, suffix);
1186 return devm_request_irq(dev, irq, handler, 0, name, dev_id);
1187}
1188
931static int rspi_probe(struct platform_device *pdev) 1189static int rspi_probe(struct platform_device *pdev)
932{ 1190{
933 struct resource *res; 1191 struct resource *res;
934 struct spi_master *master; 1192 struct spi_master *master;
935 struct rspi_data *rspi; 1193 struct rspi_data *rspi;
936 int ret, irq; 1194 int ret;
937 char clk_name[16]; 1195 const struct of_device_id *of_id;
938 const struct rspi_plat_data *rspi_pd = dev_get_platdata(&pdev->dev); 1196 const struct rspi_plat_data *rspi_pd;
939 const struct spi_ops *ops; 1197 const struct spi_ops *ops;
940 const struct platform_device_id *id_entry = pdev->id_entry;
941
942 ops = (struct spi_ops *)id_entry->driver_data;
943 /* ops parameter check */
944 if (!ops->set_config_register) {
945 dev_err(&pdev->dev, "there is no set_config_register\n");
946 return -ENODEV;
947 }
948
949 irq = platform_get_irq(pdev, 0);
950 if (irq < 0) {
951 dev_err(&pdev->dev, "platform_get_irq error\n");
952 return -ENODEV;
953 }
954 1198
955 master = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data)); 1199 master = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data));
956 if (master == NULL) { 1200 if (master == NULL) {
@@ -958,6 +1202,28 @@ static int rspi_probe(struct platform_device *pdev)
958 return -ENOMEM; 1202 return -ENOMEM;
959 } 1203 }
960 1204
1205 of_id = of_match_device(rspi_of_match, &pdev->dev);
1206 if (of_id) {
1207 ops = of_id->data;
1208 ret = rspi_parse_dt(&pdev->dev, master);
1209 if (ret)
1210 goto error1;
1211 } else {
1212 ops = (struct spi_ops *)pdev->id_entry->driver_data;
1213 rspi_pd = dev_get_platdata(&pdev->dev);
1214 if (rspi_pd && rspi_pd->num_chipselect)
1215 master->num_chipselect = rspi_pd->num_chipselect;
1216 else
1217 master->num_chipselect = 2; /* default */
1218 };
1219
1220 /* ops parameter check */
1221 if (!ops->set_config_register) {
1222 dev_err(&pdev->dev, "there is no set_config_register\n");
1223 ret = -ENODEV;
1224 goto error1;
1225 }
1226
961 rspi = spi_master_get_devdata(master); 1227 rspi = spi_master_get_devdata(master);
962 platform_set_drvdata(pdev, rspi); 1228 platform_set_drvdata(pdev, rspi);
963 rspi->ops = ops; 1229 rspi->ops = ops;
@@ -970,39 +1236,61 @@ static int rspi_probe(struct platform_device *pdev)
970 goto error1; 1236 goto error1;
971 } 1237 }
972 1238
973 snprintf(clk_name, sizeof(clk_name), "%s%d", id_entry->name, pdev->id); 1239 rspi->clk = devm_clk_get(&pdev->dev, NULL);
974 rspi->clk = devm_clk_get(&pdev->dev, clk_name);
975 if (IS_ERR(rspi->clk)) { 1240 if (IS_ERR(rspi->clk)) {
976 dev_err(&pdev->dev, "cannot get clock\n"); 1241 dev_err(&pdev->dev, "cannot get clock\n");
977 ret = PTR_ERR(rspi->clk); 1242 ret = PTR_ERR(rspi->clk);
978 goto error1; 1243 goto error1;
979 } 1244 }
980 clk_enable(rspi->clk);
981 1245
982 INIT_LIST_HEAD(&rspi->queue); 1246 pm_runtime_enable(&pdev->dev);
983 spin_lock_init(&rspi->lock);
984 INIT_WORK(&rspi->ws, rspi_work);
985 init_waitqueue_head(&rspi->wait);
986 1247
987 if (rspi_pd && rspi_pd->num_chipselect) 1248 init_waitqueue_head(&rspi->wait);
988 master->num_chipselect = rspi_pd->num_chipselect;
989 else
990 master->num_chipselect = 2; /* default */
991 1249
992 master->bus_num = pdev->id; 1250 master->bus_num = pdev->id;
993 master->setup = rspi_setup; 1251 master->setup = rspi_setup;
994 master->transfer = rspi_transfer; 1252 master->auto_runtime_pm = true;
995 master->cleanup = rspi_cleanup; 1253 master->transfer_one = ops->transfer_one;
996 master->mode_bits = SPI_CPHA | SPI_CPOL; 1254 master->prepare_message = rspi_prepare_message;
1255 master->unprepare_message = rspi_unprepare_message;
1256 master->mode_bits = ops->mode_bits;
1257 master->dev.of_node = pdev->dev.of_node;
1258
1259 ret = platform_get_irq_byname(pdev, "rx");
1260 if (ret < 0) {
1261 ret = platform_get_irq_byname(pdev, "mux");
1262 if (ret < 0)
1263 ret = platform_get_irq(pdev, 0);
1264 if (ret >= 0)
1265 rspi->rx_irq = rspi->tx_irq = ret;
1266 } else {
1267 rspi->rx_irq = ret;
1268 ret = platform_get_irq_byname(pdev, "tx");
1269 if (ret >= 0)
1270 rspi->tx_irq = ret;
1271 }
1272 if (ret < 0) {
1273 dev_err(&pdev->dev, "platform_get_irq error\n");
1274 goto error2;
1275 }
997 1276
998 ret = devm_request_irq(&pdev->dev, irq, rspi_irq, 0, 1277 if (rspi->rx_irq == rspi->tx_irq) {
999 dev_name(&pdev->dev), rspi); 1278 /* Single multiplexed interrupt */
1279 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_mux,
1280 "mux", rspi);
1281 } else {
1282 /* Multi-interrupt mode, only SPRI and SPTI are used */
1283 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_rx,
1284 "rx", rspi);
1285 if (!ret)
1286 ret = rspi_request_irq(&pdev->dev, rspi->tx_irq,
1287 rspi_irq_tx, "tx", rspi);
1288 }
1000 if (ret < 0) { 1289 if (ret < 0) {
1001 dev_err(&pdev->dev, "request_irq error\n"); 1290 dev_err(&pdev->dev, "request_irq error\n");
1002 goto error2; 1291 goto error2;
1003 } 1292 }
1004 1293
1005 rspi->irq = irq;
1006 ret = rspi_request_dma(rspi, pdev); 1294 ret = rspi_request_dma(rspi, pdev);
1007 if (ret < 0) { 1295 if (ret < 0) {
1008 dev_err(&pdev->dev, "rspi_request_dma failed.\n"); 1296 dev_err(&pdev->dev, "rspi_request_dma failed.\n");
@@ -1022,27 +1310,16 @@ static int rspi_probe(struct platform_device *pdev)
1022error3: 1310error3:
1023 rspi_release_dma(rspi); 1311 rspi_release_dma(rspi);
1024error2: 1312error2:
1025 clk_disable(rspi->clk); 1313 pm_runtime_disable(&pdev->dev);
1026error1: 1314error1:
1027 spi_master_put(master); 1315 spi_master_put(master);
1028 1316
1029 return ret; 1317 return ret;
1030} 1318}
1031 1319
1032static struct spi_ops rspi_ops = {
1033 .set_config_register = rspi_set_config_register,
1034 .send_pio = rspi_send_pio,
1035 .receive_pio = rspi_receive_pio,
1036};
1037
1038static struct spi_ops qspi_ops = {
1039 .set_config_register = qspi_set_config_register,
1040 .send_pio = qspi_send_pio,
1041 .receive_pio = qspi_receive_pio,
1042};
1043
1044static struct platform_device_id spi_driver_ids[] = { 1320static struct platform_device_id spi_driver_ids[] = {
1045 { "rspi", (kernel_ulong_t)&rspi_ops }, 1321 { "rspi", (kernel_ulong_t)&rspi_ops },
1322 { "rspi-rz", (kernel_ulong_t)&rspi_rz_ops },
1046 { "qspi", (kernel_ulong_t)&qspi_ops }, 1323 { "qspi", (kernel_ulong_t)&qspi_ops },
1047 {}, 1324 {},
1048}; 1325};
@@ -1056,6 +1333,7 @@ static struct platform_driver rspi_driver = {
1056 .driver = { 1333 .driver = {
1057 .name = "renesas_spi", 1334 .name = "renesas_spi",
1058 .owner = THIS_MODULE, 1335 .owner = THIS_MODULE,
1336 .of_match_table = of_match_ptr(rspi_of_match),
1059 }, 1337 },
1060}; 1338};
1061module_platform_driver(rspi_driver); 1339module_platform_driver(rspi_driver);
diff --git a/drivers/spi/spi-s3c24xx.c b/drivers/spi/spi-s3c24xx.c
index 746424aa5353..bed23384dfab 100644
--- a/drivers/spi/spi-s3c24xx.c
+++ b/drivers/spi/spi-s3c24xx.c
@@ -9,7 +9,6 @@
9 * 9 *
10*/ 10*/
11 11
12#include <linux/init.h>
13#include <linux/spinlock.h> 12#include <linux/spinlock.h>
14#include <linux/workqueue.h> 13#include <linux/workqueue.h>
15#include <linux/interrupt.h> 14#include <linux/interrupt.h>
@@ -123,25 +122,15 @@ static int s3c24xx_spi_update_state(struct spi_device *spi,
123{ 122{
124 struct s3c24xx_spi *hw = to_hw(spi); 123 struct s3c24xx_spi *hw = to_hw(spi);
125 struct s3c24xx_spi_devstate *cs = spi->controller_state; 124 struct s3c24xx_spi_devstate *cs = spi->controller_state;
126 unsigned int bpw;
127 unsigned int hz; 125 unsigned int hz;
128 unsigned int div; 126 unsigned int div;
129 unsigned long clk; 127 unsigned long clk;
130 128
131 bpw = t ? t->bits_per_word : spi->bits_per_word;
132 hz = t ? t->speed_hz : spi->max_speed_hz; 129 hz = t ? t->speed_hz : spi->max_speed_hz;
133 130
134 if (!bpw)
135 bpw = 8;
136
137 if (!hz) 131 if (!hz)
138 hz = spi->max_speed_hz; 132 hz = spi->max_speed_hz;
139 133
140 if (bpw != 8) {
141 dev_err(&spi->dev, "invalid bits-per-word (%d)\n", bpw);
142 return -EINVAL;
143 }
144
145 if (spi->mode != cs->mode) { 134 if (spi->mode != cs->mode) {
146 u8 spcon = SPCON_DEFAULT | S3C2410_SPCON_ENSCK; 135 u8 spcon = SPCON_DEFAULT | S3C2410_SPCON_ENSCK;
147 136
@@ -544,6 +533,7 @@ static int s3c24xx_spi_probe(struct platform_device *pdev)
544 533
545 master->num_chipselect = hw->pdata->num_cs; 534 master->num_chipselect = hw->pdata->num_cs;
546 master->bus_num = pdata->bus_num; 535 master->bus_num = pdata->bus_num;
536 master->bits_per_word_mask = SPI_BPW_MASK(8);
547 537
548 /* setup the state for the bitbang driver */ 538 /* setup the state for the bitbang driver */
549 539
@@ -643,6 +633,11 @@ static int s3c24xx_spi_remove(struct platform_device *dev)
643static int s3c24xx_spi_suspend(struct device *dev) 633static int s3c24xx_spi_suspend(struct device *dev)
644{ 634{
645 struct s3c24xx_spi *hw = dev_get_drvdata(dev); 635 struct s3c24xx_spi *hw = dev_get_drvdata(dev);
636 int ret;
637
638 ret = spi_master_suspend(hw->master);
639 if (ret)
640 return ret;
646 641
647 if (hw->pdata && hw->pdata->gpio_setup) 642 if (hw->pdata && hw->pdata->gpio_setup)
648 hw->pdata->gpio_setup(hw->pdata, 0); 643 hw->pdata->gpio_setup(hw->pdata, 0);
@@ -656,7 +651,7 @@ static int s3c24xx_spi_resume(struct device *dev)
656 struct s3c24xx_spi *hw = dev_get_drvdata(dev); 651 struct s3c24xx_spi *hw = dev_get_drvdata(dev);
657 652
658 s3c24xx_spi_initialsetup(hw); 653 s3c24xx_spi_initialsetup(hw);
659 return 0; 654 return spi_master_resume(hw->master);
660} 655}
661 656
662static const struct dev_pm_ops s3c24xx_spi_pmops = { 657static const struct dev_pm_ops s3c24xx_spi_pmops = {
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index ae907dde1371..25c9bd409a87 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -381,7 +381,7 @@ static void s3c64xx_spi_dma_stop(struct s3c64xx_spi_driver_data *sdd,
381#else 381#else
382 382
383static void prepare_dma(struct s3c64xx_spi_dma_data *dma, 383static void prepare_dma(struct s3c64xx_spi_dma_data *dma,
384 unsigned len, dma_addr_t buf) 384 struct sg_table *sgt)
385{ 385{
386 struct s3c64xx_spi_driver_data *sdd; 386 struct s3c64xx_spi_driver_data *sdd;
387 struct dma_slave_config config; 387 struct dma_slave_config config;
@@ -407,8 +407,8 @@ static void prepare_dma(struct s3c64xx_spi_dma_data *dma,
407 dmaengine_slave_config(dma->ch, &config); 407 dmaengine_slave_config(dma->ch, &config);
408 } 408 }
409 409
410 desc = dmaengine_prep_slave_single(dma->ch, buf, len, 410 desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents,
411 dma->direction, DMA_PREP_INTERRUPT); 411 dma->direction, DMA_PREP_INTERRUPT);
412 412
413 desc->callback = s3c64xx_spi_dmacb; 413 desc->callback = s3c64xx_spi_dmacb;
414 desc->callback_param = dma; 414 desc->callback_param = dma;
@@ -515,7 +515,11 @@ static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
515 chcfg |= S3C64XX_SPI_CH_TXCH_ON; 515 chcfg |= S3C64XX_SPI_CH_TXCH_ON;
516 if (dma_mode) { 516 if (dma_mode) {
517 modecfg |= S3C64XX_SPI_MODE_TXDMA_ON; 517 modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
518#ifndef CONFIG_S3C_DMA
519 prepare_dma(&sdd->tx_dma, &xfer->tx_sg);
520#else
518 prepare_dma(&sdd->tx_dma, xfer->len, xfer->tx_dma); 521 prepare_dma(&sdd->tx_dma, xfer->len, xfer->tx_dma);
522#endif
519 } else { 523 } else {
520 switch (sdd->cur_bpw) { 524 switch (sdd->cur_bpw) {
521 case 32: 525 case 32:
@@ -547,7 +551,11 @@ static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
547 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) 551 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
548 | S3C64XX_SPI_PACKET_CNT_EN, 552 | S3C64XX_SPI_PACKET_CNT_EN,
549 regs + S3C64XX_SPI_PACKET_CNT); 553 regs + S3C64XX_SPI_PACKET_CNT);
554#ifndef CONFIG_S3C_DMA
555 prepare_dma(&sdd->rx_dma, &xfer->rx_sg);
556#else
550 prepare_dma(&sdd->rx_dma, xfer->len, xfer->rx_dma); 557 prepare_dma(&sdd->rx_dma, xfer->len, xfer->rx_dma);
558#endif
551 } 559 }
552 } 560 }
553 561
@@ -555,23 +563,6 @@ static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
555 writel(chcfg, regs + S3C64XX_SPI_CH_CFG); 563 writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
556} 564}
557 565
558static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd,
559 struct spi_device *spi)
560{
561 if (sdd->tgl_spi != NULL) { /* If last device toggled after mssg */
562 if (sdd->tgl_spi != spi) { /* if last mssg on diff device */
563 /* Deselect the last toggled device */
564 if (spi->cs_gpio >= 0)
565 gpio_set_value(spi->cs_gpio,
566 spi->mode & SPI_CS_HIGH ? 0 : 1);
567 }
568 sdd->tgl_spi = NULL;
569 }
570
571 if (spi->cs_gpio >= 0)
572 gpio_set_value(spi->cs_gpio, spi->mode & SPI_CS_HIGH ? 1 : 0);
573}
574
575static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd, 566static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd,
576 int timeout_ms) 567 int timeout_ms)
577{ 568{
@@ -593,112 +584,111 @@ static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd,
593 return RX_FIFO_LVL(status, sdd); 584 return RX_FIFO_LVL(status, sdd);
594} 585}
595 586
596static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd, 587static int wait_for_dma(struct s3c64xx_spi_driver_data *sdd,
597 struct spi_transfer *xfer, int dma_mode) 588 struct spi_transfer *xfer)
598{ 589{
599 void __iomem *regs = sdd->regs; 590 void __iomem *regs = sdd->regs;
600 unsigned long val; 591 unsigned long val;
592 u32 status;
601 int ms; 593 int ms;
602 594
603 /* millisecs to xfer 'len' bytes @ 'cur_speed' */ 595 /* millisecs to xfer 'len' bytes @ 'cur_speed' */
604 ms = xfer->len * 8 * 1000 / sdd->cur_speed; 596 ms = xfer->len * 8 * 1000 / sdd->cur_speed;
605 ms += 10; /* some tolerance */ 597 ms += 10; /* some tolerance */
606 598
607 if (dma_mode) { 599 val = msecs_to_jiffies(ms) + 10;
608 val = msecs_to_jiffies(ms) + 10; 600 val = wait_for_completion_timeout(&sdd->xfer_completion, val);
609 val = wait_for_completion_timeout(&sdd->xfer_completion, val); 601
610 } else { 602 /*
611 u32 status; 603 * If the previous xfer was completed within timeout, then
612 val = msecs_to_loops(ms); 604 * proceed further else return -EIO.
613 do { 605 * DmaTx returns after simply writing data in the FIFO,
606 * w/o waiting for real transmission on the bus to finish.
607 * DmaRx returns only after Dma read data from FIFO which
608 * needs bus transmission to finish, so we don't worry if
609 * Xfer involved Rx(with or without Tx).
610 */
611 if (val && !xfer->rx_buf) {
612 val = msecs_to_loops(10);
613 status = readl(regs + S3C64XX_SPI_STATUS);
614 while ((TX_FIFO_LVL(status, sdd)
615 || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
616 && --val) {
617 cpu_relax();
614 status = readl(regs + S3C64XX_SPI_STATUS); 618 status = readl(regs + S3C64XX_SPI_STATUS);
615 } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val); 619 }
620
616 } 621 }
617 622
618 if (dma_mode) { 623 /* If timed out while checking rx/tx status return error */
619 u32 status; 624 if (!val)
620 625 return -EIO;
621 /*
622 * If the previous xfer was completed within timeout, then
623 * proceed further else return -EIO.
624 * DmaTx returns after simply writing data in the FIFO,
625 * w/o waiting for real transmission on the bus to finish.
626 * DmaRx returns only after Dma read data from FIFO which
627 * needs bus transmission to finish, so we don't worry if
628 * Xfer involved Rx(with or without Tx).
629 */
630 if (val && !xfer->rx_buf) {
631 val = msecs_to_loops(10);
632 status = readl(regs + S3C64XX_SPI_STATUS);
633 while ((TX_FIFO_LVL(status, sdd)
634 || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
635 && --val) {
636 cpu_relax();
637 status = readl(regs + S3C64XX_SPI_STATUS);
638 }
639 626
640 } 627 return 0;
628}
641 629
642 /* If timed out while checking rx/tx status return error */ 630static int wait_for_pio(struct s3c64xx_spi_driver_data *sdd,
643 if (!val) 631 struct spi_transfer *xfer)
644 return -EIO; 632{
645 } else { 633 void __iomem *regs = sdd->regs;
646 int loops; 634 unsigned long val;
647 u32 cpy_len; 635 u32 status;
648 u8 *buf; 636 int loops;
649 637 u32 cpy_len;
650 /* If it was only Tx */ 638 u8 *buf;
651 if (!xfer->rx_buf) { 639 int ms;
652 sdd->state &= ~TXBUSY;
653 return 0;
654 }
655 640
656 /* 641 /* millisecs to xfer 'len' bytes @ 'cur_speed' */
657 * If the receive length is bigger than the controller fifo 642 ms = xfer->len * 8 * 1000 / sdd->cur_speed;
658 * size, calculate the loops and read the fifo as many times. 643 ms += 10; /* some tolerance */
659 * loops = length / max fifo size (calculated by using the
660 * fifo mask).
661 * For any size less than the fifo size the below code is
662 * executed atleast once.
663 */
664 loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1);
665 buf = xfer->rx_buf;
666 do {
667 /* wait for data to be received in the fifo */
668 cpy_len = s3c64xx_spi_wait_for_timeout(sdd,
669 (loops ? ms : 0));
670 644
671 switch (sdd->cur_bpw) { 645 val = msecs_to_loops(ms);
672 case 32: 646 do {
673 ioread32_rep(regs + S3C64XX_SPI_RX_DATA, 647 status = readl(regs + S3C64XX_SPI_STATUS);
674 buf, cpy_len / 4); 648 } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
675 break;
676 case 16:
677 ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
678 buf, cpy_len / 2);
679 break;
680 default:
681 ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
682 buf, cpy_len);
683 break;
684 }
685 649
686 buf = buf + cpy_len; 650
687 } while (loops--); 651 /* If it was only Tx */
688 sdd->state &= ~RXBUSY; 652 if (!xfer->rx_buf) {
653 sdd->state &= ~TXBUSY;
654 return 0;
689 } 655 }
690 656
691 return 0; 657 /*
692} 658 * If the receive length is bigger than the controller fifo
659 * size, calculate the loops and read the fifo as many times.
660 * loops = length / max fifo size (calculated by using the
661 * fifo mask).
662 * For any size less than the fifo size the below code is
663 * executed atleast once.
664 */
665 loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1);
666 buf = xfer->rx_buf;
667 do {
668 /* wait for data to be received in the fifo */
669 cpy_len = s3c64xx_spi_wait_for_timeout(sdd,
670 (loops ? ms : 0));
671
672 switch (sdd->cur_bpw) {
673 case 32:
674 ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
675 buf, cpy_len / 4);
676 break;
677 case 16:
678 ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
679 buf, cpy_len / 2);
680 break;
681 default:
682 ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
683 buf, cpy_len);
684 break;
685 }
693 686
694static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd, 687 buf = buf + cpy_len;
695 struct spi_device *spi) 688 } while (loops--);
696{ 689 sdd->state &= ~RXBUSY;
697 if (sdd->tgl_spi == spi)
698 sdd->tgl_spi = NULL;
699 690
700 if (spi->cs_gpio >= 0) 691 return 0;
701 gpio_set_value(spi->cs_gpio, spi->mode & SPI_CS_HIGH ? 0 : 1);
702} 692}
703 693
704static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) 694static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
@@ -929,7 +919,10 @@ static int s3c64xx_spi_transfer_one(struct spi_master *master,
929 919
930 spin_unlock_irqrestore(&sdd->lock, flags); 920 spin_unlock_irqrestore(&sdd->lock, flags);
931 921
932 status = wait_for_xfer(sdd, xfer, use_dma); 922 if (use_dma)
923 status = wait_for_dma(sdd, xfer);
924 else
925 status = wait_for_pio(sdd, xfer);
933 926
934 if (status) { 927 if (status) {
935 dev_err(&spi->dev, "I/O Error: rx-%d tx-%d res:rx-%c tx-%c len-%d\n", 928 dev_err(&spi->dev, "I/O Error: rx-%d tx-%d res:rx-%c tx-%c len-%d\n",
@@ -1092,14 +1085,12 @@ static int s3c64xx_spi_setup(struct spi_device *spi)
1092 1085
1093 pm_runtime_put(&sdd->pdev->dev); 1086 pm_runtime_put(&sdd->pdev->dev);
1094 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL); 1087 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
1095 disable_cs(sdd, spi);
1096 return 0; 1088 return 0;
1097 1089
1098setup_exit: 1090setup_exit:
1099 pm_runtime_put(&sdd->pdev->dev); 1091 pm_runtime_put(&sdd->pdev->dev);
1100 /* setup() returns with device de-selected */ 1092 /* setup() returns with device de-selected */
1101 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL); 1093 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
1102 disable_cs(sdd, spi);
1103 1094
1104 gpio_free(cs->line); 1095 gpio_free(cs->line);
1105 spi_set_ctldata(spi, NULL); 1096 spi_set_ctldata(spi, NULL);
diff --git a/drivers/spi/spi-sh-hspi.c b/drivers/spi/spi-sh-hspi.c
index 82d2f922ffa0..755d7cc9e72f 100644
--- a/drivers/spi/spi-sh-hspi.c
+++ b/drivers/spi/spi-sh-hspi.c
@@ -298,7 +298,6 @@ static int hspi_probe(struct platform_device *pdev)
298 298
299 pm_runtime_enable(&pdev->dev); 299 pm_runtime_enable(&pdev->dev);
300 300
301 master->num_chipselect = 1;
302 master->bus_num = pdev->id; 301 master->bus_num = pdev->id;
303 master->setup = hspi_setup; 302 master->setup = hspi_setup;
304 master->cleanup = hspi_cleanup; 303 master->cleanup = hspi_cleanup;
diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c
index 81cc02f5f9b0..33474061b742 100644
--- a/drivers/spi/spi-sh-msiof.c
+++ b/drivers/spi/spi-sh-msiof.c
@@ -15,7 +15,6 @@
15#include <linux/delay.h> 15#include <linux/delay.h>
16#include <linux/err.h> 16#include <linux/err.h>
17#include <linux/gpio.h> 17#include <linux/gpio.h>
18#include <linux/init.h>
19#include <linux/interrupt.h> 18#include <linux/interrupt.h>
20#include <linux/io.h> 19#include <linux/io.h>
21#include <linux/kernel.h> 20#include <linux/kernel.h>
diff --git a/drivers/spi/spi-sh-sci.c b/drivers/spi/spi-sh-sci.c
index 38eb24df796c..85c2efd57c80 100644
--- a/drivers/spi/spi-sh-sci.c
+++ b/drivers/spi/spi-sh-sci.c
@@ -14,7 +14,6 @@
14 */ 14 */
15 15
16#include <linux/kernel.h> 16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/delay.h> 17#include <linux/delay.h>
19#include <linux/spinlock.h> 18#include <linux/spinlock.h>
20#include <linux/workqueue.h> 19#include <linux/workqueue.h>
diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c
index 413c71843492..6be661e4c6e1 100644
--- a/drivers/spi/spi-tegra114.c
+++ b/drivers/spi/spi-tegra114.c
@@ -23,7 +23,6 @@
23#include <linux/dma-mapping.h> 23#include <linux/dma-mapping.h>
24#include <linux/dmapool.h> 24#include <linux/dmapool.h>
25#include <linux/err.h> 25#include <linux/err.h>
26#include <linux/init.h>
27#include <linux/interrupt.h> 26#include <linux/interrupt.h>
28#include <linux/io.h> 27#include <linux/io.h>
29#include <linux/kernel.h> 28#include <linux/kernel.h>
@@ -172,7 +171,6 @@ struct tegra_spi_data {
172 void __iomem *base; 171 void __iomem *base;
173 phys_addr_t phys; 172 phys_addr_t phys;
174 unsigned irq; 173 unsigned irq;
175 u32 spi_max_frequency;
176 u32 cur_speed; 174 u32 cur_speed;
177 175
178 struct spi_device *cur_spi; 176 struct spi_device *cur_spi;
@@ -761,11 +759,6 @@ static int tegra_spi_setup(struct spi_device *spi)
761 spi->mode & SPI_CPHA ? "" : "~", 759 spi->mode & SPI_CPHA ? "" : "~",
762 spi->max_speed_hz); 760 spi->max_speed_hz);
763 761
764 BUG_ON(spi->chip_select >= MAX_CHIP_SELECT);
765
766 /* Set speed to the spi max fequency if spi device has not set */
767 spi->max_speed_hz = spi->max_speed_hz ? : tspi->spi_max_frequency;
768
769 ret = pm_runtime_get_sync(tspi->dev); 762 ret = pm_runtime_get_sync(tspi->dev);
770 if (ret < 0) { 763 if (ret < 0) {
771 dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret); 764 dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret);
@@ -1019,16 +1012,6 @@ static irqreturn_t tegra_spi_isr(int irq, void *context_data)
1019 return IRQ_WAKE_THREAD; 1012 return IRQ_WAKE_THREAD;
1020} 1013}
1021 1014
1022static void tegra_spi_parse_dt(struct platform_device *pdev,
1023 struct tegra_spi_data *tspi)
1024{
1025 struct device_node *np = pdev->dev.of_node;
1026
1027 if (of_property_read_u32(np, "spi-max-frequency",
1028 &tspi->spi_max_frequency))
1029 tspi->spi_max_frequency = 25000000; /* 25MHz */
1030}
1031
1032static struct of_device_id tegra_spi_of_match[] = { 1015static struct of_device_id tegra_spi_of_match[] = {
1033 { .compatible = "nvidia,tegra114-spi", }, 1016 { .compatible = "nvidia,tegra114-spi", },
1034 {} 1017 {}
@@ -1050,15 +1033,15 @@ static int tegra_spi_probe(struct platform_device *pdev)
1050 platform_set_drvdata(pdev, master); 1033 platform_set_drvdata(pdev, master);
1051 tspi = spi_master_get_devdata(master); 1034 tspi = spi_master_get_devdata(master);
1052 1035
1053 /* Parse DT */ 1036 if (of_property_read_u32(pdev->dev.of_node, "spi-max-frequency",
1054 tegra_spi_parse_dt(pdev, tspi); 1037 &master->max_speed_hz))
1038 master->max_speed_hz = 25000000; /* 25MHz */
1055 1039
1056 /* the spi->mode bits understood by this driver: */ 1040 /* the spi->mode bits understood by this driver: */
1057 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 1041 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1058 master->setup = tegra_spi_setup; 1042 master->setup = tegra_spi_setup;
1059 master->transfer_one_message = tegra_spi_transfer_one_message; 1043 master->transfer_one_message = tegra_spi_transfer_one_message;
1060 master->num_chipselect = MAX_CHIP_SELECT; 1044 master->num_chipselect = MAX_CHIP_SELECT;
1061 master->bus_num = -1;
1062 master->auto_runtime_pm = true; 1045 master->auto_runtime_pm = true;
1063 1046
1064 tspi->master = master; 1047 tspi->master = master;
diff --git a/drivers/spi/spi-tegra20-sflash.c b/drivers/spi/spi-tegra20-sflash.c
index 08794977f21a..47869ea636e1 100644
--- a/drivers/spi/spi-tegra20-sflash.c
+++ b/drivers/spi/spi-tegra20-sflash.c
@@ -22,7 +22,6 @@
22#include <linux/completion.h> 22#include <linux/completion.h>
23#include <linux/delay.h> 23#include <linux/delay.h>
24#include <linux/err.h> 24#include <linux/err.h>
25#include <linux/init.h>
26#include <linux/interrupt.h> 25#include <linux/interrupt.h>
27#include <linux/io.h> 26#include <linux/io.h>
28#include <linux/kernel.h> 27#include <linux/kernel.h>
@@ -121,7 +120,6 @@ struct tegra_sflash_data {
121 struct reset_control *rst; 120 struct reset_control *rst;
122 void __iomem *base; 121 void __iomem *base;
123 unsigned irq; 122 unsigned irq;
124 u32 spi_max_frequency;
125 u32 cur_speed; 123 u32 cur_speed;
126 124
127 struct spi_device *cur_spi; 125 struct spi_device *cur_spi;
@@ -315,15 +313,6 @@ static int tegra_sflash_start_transfer_one(struct spi_device *spi,
315 return tegra_sflash_start_cpu_based_transfer(tsd, t); 313 return tegra_sflash_start_cpu_based_transfer(tsd, t);
316} 314}
317 315
318static int tegra_sflash_setup(struct spi_device *spi)
319{
320 struct tegra_sflash_data *tsd = spi_master_get_devdata(spi->master);
321
322 /* Set speed to the spi max fequency if spi device has not set */
323 spi->max_speed_hz = spi->max_speed_hz ? : tsd->spi_max_frequency;
324 return 0;
325}
326
327static int tegra_sflash_transfer_one_message(struct spi_master *master, 316static int tegra_sflash_transfer_one_message(struct spi_master *master,
328 struct spi_message *msg) 317 struct spi_message *msg)
329{ 318{
@@ -430,15 +419,6 @@ static irqreturn_t tegra_sflash_isr(int irq, void *context_data)
430 return handle_cpu_based_xfer(tsd); 419 return handle_cpu_based_xfer(tsd);
431} 420}
432 421
433static void tegra_sflash_parse_dt(struct tegra_sflash_data *tsd)
434{
435 struct device_node *np = tsd->dev->of_node;
436
437 if (of_property_read_u32(np, "spi-max-frequency",
438 &tsd->spi_max_frequency))
439 tsd->spi_max_frequency = 25000000; /* 25MHz */
440}
441
442static struct of_device_id tegra_sflash_of_match[] = { 422static struct of_device_id tegra_sflash_of_match[] = {
443 { .compatible = "nvidia,tegra20-sflash", }, 423 { .compatible = "nvidia,tegra20-sflash", },
444 {} 424 {}
@@ -467,11 +447,9 @@ static int tegra_sflash_probe(struct platform_device *pdev)
467 447
468 /* the spi->mode bits understood by this driver: */ 448 /* the spi->mode bits understood by this driver: */
469 master->mode_bits = SPI_CPOL | SPI_CPHA; 449 master->mode_bits = SPI_CPOL | SPI_CPHA;
470 master->setup = tegra_sflash_setup;
471 master->transfer_one_message = tegra_sflash_transfer_one_message; 450 master->transfer_one_message = tegra_sflash_transfer_one_message;
472 master->auto_runtime_pm = true; 451 master->auto_runtime_pm = true;
473 master->num_chipselect = MAX_CHIP_SELECT; 452 master->num_chipselect = MAX_CHIP_SELECT;
474 master->bus_num = -1;
475 453
476 platform_set_drvdata(pdev, master); 454 platform_set_drvdata(pdev, master);
477 tsd = spi_master_get_devdata(master); 455 tsd = spi_master_get_devdata(master);
@@ -479,7 +457,9 @@ static int tegra_sflash_probe(struct platform_device *pdev)
479 tsd->dev = &pdev->dev; 457 tsd->dev = &pdev->dev;
480 spin_lock_init(&tsd->lock); 458 spin_lock_init(&tsd->lock);
481 459
482 tegra_sflash_parse_dt(tsd); 460 if (of_property_read_u32(tsd->dev->of_node, "spi-max-frequency",
461 &master->max_speed_hz))
462 master->max_speed_hz = 25000000; /* 25MHz */
483 463
484 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 464 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
485 tsd->base = devm_ioremap_resource(&pdev->dev, r); 465 tsd->base = devm_ioremap_resource(&pdev->dev, r);
diff --git a/drivers/spi/spi-tegra20-slink.c b/drivers/spi/spi-tegra20-slink.c
index be3a069879c3..e3c1b93e45d1 100644
--- a/drivers/spi/spi-tegra20-slink.c
+++ b/drivers/spi/spi-tegra20-slink.c
@@ -23,7 +23,6 @@
23#include <linux/dma-mapping.h> 23#include <linux/dma-mapping.h>
24#include <linux/dmapool.h> 24#include <linux/dmapool.h>
25#include <linux/err.h> 25#include <linux/err.h>
26#include <linux/init.h>
27#include <linux/interrupt.h> 26#include <linux/interrupt.h>
28#include <linux/io.h> 27#include <linux/io.h>
29#include <linux/kernel.h> 28#include <linux/kernel.h>
@@ -171,7 +170,6 @@ struct tegra_slink_data {
171 void __iomem *base; 170 void __iomem *base;
172 phys_addr_t phys; 171 phys_addr_t phys;
173 unsigned irq; 172 unsigned irq;
174 u32 spi_max_frequency;
175 u32 cur_speed; 173 u32 cur_speed;
176 174
177 struct spi_device *cur_spi; 175 struct spi_device *cur_spi;
@@ -761,10 +759,6 @@ static int tegra_slink_setup(struct spi_device *spi)
761 spi->mode & SPI_CPHA ? "" : "~", 759 spi->mode & SPI_CPHA ? "" : "~",
762 spi->max_speed_hz); 760 spi->max_speed_hz);
763 761
764 BUG_ON(spi->chip_select >= MAX_CHIP_SELECT);
765
766 /* Set speed to the spi max fequency if spi device has not set */
767 spi->max_speed_hz = spi->max_speed_hz ? : tspi->spi_max_frequency;
768 ret = pm_runtime_get_sync(tspi->dev); 762 ret = pm_runtime_get_sync(tspi->dev);
769 if (ret < 0) { 763 if (ret < 0) {
770 dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret); 764 dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret);
@@ -999,15 +993,6 @@ static irqreturn_t tegra_slink_isr(int irq, void *context_data)
999 return IRQ_WAKE_THREAD; 993 return IRQ_WAKE_THREAD;
1000} 994}
1001 995
1002static void tegra_slink_parse_dt(struct tegra_slink_data *tspi)
1003{
1004 struct device_node *np = tspi->dev->of_node;
1005
1006 if (of_property_read_u32(np, "spi-max-frequency",
1007 &tspi->spi_max_frequency))
1008 tspi->spi_max_frequency = 25000000; /* 25MHz */
1009}
1010
1011static const struct tegra_slink_chip_data tegra30_spi_cdata = { 996static const struct tegra_slink_chip_data tegra30_spi_cdata = {
1012 .cs_hold_time = true, 997 .cs_hold_time = true,
1013}; 998};
@@ -1053,7 +1038,6 @@ static int tegra_slink_probe(struct platform_device *pdev)
1053 master->unprepare_message = tegra_slink_unprepare_message; 1038 master->unprepare_message = tegra_slink_unprepare_message;
1054 master->auto_runtime_pm = true; 1039 master->auto_runtime_pm = true;
1055 master->num_chipselect = MAX_CHIP_SELECT; 1040 master->num_chipselect = MAX_CHIP_SELECT;
1056 master->bus_num = -1;
1057 1041
1058 platform_set_drvdata(pdev, master); 1042 platform_set_drvdata(pdev, master);
1059 tspi = spi_master_get_devdata(master); 1043 tspi = spi_master_get_devdata(master);
@@ -1062,7 +1046,9 @@ static int tegra_slink_probe(struct platform_device *pdev)
1062 tspi->chip_data = cdata; 1046 tspi->chip_data = cdata;
1063 spin_lock_init(&tspi->lock); 1047 spin_lock_init(&tspi->lock);
1064 1048
1065 tegra_slink_parse_dt(tspi); 1049 if (of_property_read_u32(tspi->dev->of_node, "spi-max-frequency",
1050 &master->max_speed_hz))
1051 master->max_speed_hz = 25000000; /* 25MHz */
1066 1052
1067 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1053 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1068 if (!r) { 1054 if (!r) {
diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
index 3d09265b5133..49ddfc7f12b1 100644
--- a/drivers/spi/spi-ti-qspi.c
+++ b/drivers/spi/spi-ti-qspi.c
@@ -429,13 +429,13 @@ static int ti_qspi_probe(struct platform_device *pdev)
429 429
430 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD; 430 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD;
431 431
432 master->bus_num = -1;
433 master->flags = SPI_MASTER_HALF_DUPLEX; 432 master->flags = SPI_MASTER_HALF_DUPLEX;
434 master->setup = ti_qspi_setup; 433 master->setup = ti_qspi_setup;
435 master->auto_runtime_pm = true; 434 master->auto_runtime_pm = true;
436 master->transfer_one_message = ti_qspi_start_transfer_one; 435 master->transfer_one_message = ti_qspi_start_transfer_one;
437 master->dev.of_node = pdev->dev.of_node; 436 master->dev.of_node = pdev->dev.of_node;
438 master->bits_per_word_mask = BIT(32 - 1) | BIT(16 - 1) | BIT(8 - 1); 437 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
438 SPI_BPW_MASK(8);
439 439
440 if (!of_property_read_u32(np, "num-cs", &num_cs)) 440 if (!of_property_read_u32(np, "num-cs", &num_cs))
441 master->num_chipselect = num_cs; 441 master->num_chipselect = num_cs;
diff --git a/drivers/spi/spi-topcliff-pch.c b/drivers/spi/spi-topcliff-pch.c
index 2e7f38c7a961..88eb57e858b3 100644
--- a/drivers/spi/spi-topcliff-pch.c
+++ b/drivers/spi/spi-topcliff-pch.c
@@ -915,7 +915,7 @@ static void pch_spi_request_dma(struct pch_spi_data *data, int bpw)
915 /* Set Tx DMA */ 915 /* Set Tx DMA */
916 param = &dma->param_tx; 916 param = &dma->param_tx;
917 param->dma_dev = &dma_dev->dev; 917 param->dma_dev = &dma_dev->dev;
918 param->chan_id = data->master->bus_num * 2; /* Tx = 0, 2 */ 918 param->chan_id = data->ch * 2; /* Tx = 0, 2 */;
919 param->tx_reg = data->io_base_addr + PCH_SPDWR; 919 param->tx_reg = data->io_base_addr + PCH_SPDWR;
920 param->width = width; 920 param->width = width;
921 chan = dma_request_channel(mask, pch_spi_filter, param); 921 chan = dma_request_channel(mask, pch_spi_filter, param);
@@ -930,7 +930,7 @@ static void pch_spi_request_dma(struct pch_spi_data *data, int bpw)
930 /* Set Rx DMA */ 930 /* Set Rx DMA */
931 param = &dma->param_rx; 931 param = &dma->param_rx;
932 param->dma_dev = &dma_dev->dev; 932 param->dma_dev = &dma_dev->dev;
933 param->chan_id = data->master->bus_num * 2 + 1; /* Rx = Tx + 1 */ 933 param->chan_id = data->ch * 2 + 1; /* Rx = Tx + 1 */;
934 param->rx_reg = data->io_base_addr + PCH_SPDRR; 934 param->rx_reg = data->io_base_addr + PCH_SPDRR;
935 param->width = width; 935 param->width = width;
936 chan = dma_request_channel(mask, pch_spi_filter, param); 936 chan = dma_request_channel(mask, pch_spi_filter, param);
@@ -1452,6 +1452,11 @@ static int pch_spi_pd_probe(struct platform_device *plat_dev)
1452 1452
1453 pch_spi_set_master_mode(master); 1453 pch_spi_set_master_mode(master);
1454 1454
1455 if (use_dma) {
1456 dev_info(&plat_dev->dev, "Use DMA for data transfers\n");
1457 pch_alloc_dma_buf(board_dat, data);
1458 }
1459
1455 ret = spi_register_master(master); 1460 ret = spi_register_master(master);
1456 if (ret != 0) { 1461 if (ret != 0) {
1457 dev_err(&plat_dev->dev, 1462 dev_err(&plat_dev->dev,
@@ -1459,14 +1464,10 @@ static int pch_spi_pd_probe(struct platform_device *plat_dev)
1459 goto err_spi_register_master; 1464 goto err_spi_register_master;
1460 } 1465 }
1461 1466
1462 if (use_dma) {
1463 dev_info(&plat_dev->dev, "Use DMA for data transfers\n");
1464 pch_alloc_dma_buf(board_dat, data);
1465 }
1466
1467 return 0; 1467 return 0;
1468 1468
1469err_spi_register_master: 1469err_spi_register_master:
1470 pch_free_dma_buf(board_dat, data);
1470 free_irq(board_dat->pdev->irq, data); 1471 free_irq(board_dat->pdev->irq, data);
1471err_request_irq: 1472err_request_irq:
1472 pch_spi_free_resources(board_dat, data); 1473 pch_spi_free_resources(board_dat, data);
diff --git a/drivers/spi/spi-xcomm.c b/drivers/spi/spi-xcomm.c
index 24c40b13dab1..350a76b7e8d4 100644
--- a/drivers/spi/spi-xcomm.c
+++ b/drivers/spi/spi-xcomm.c
@@ -8,7 +8,6 @@
8 */ 8 */
9 9
10#include <linux/kernel.h> 10#include <linux/kernel.h>
11#include <linux/init.h>
12#include <linux/module.h> 11#include <linux/module.h>
13#include <linux/delay.h> 12#include <linux/delay.h>
14#include <linux/i2c.h> 13#include <linux/i2c.h>
diff --git a/drivers/spi/spi-xilinx.c b/drivers/spi/spi-xilinx.c
index 6d4ce4615163..e6cd1112ae40 100644
--- a/drivers/spi/spi-xilinx.c
+++ b/drivers/spi/spi-xilinx.c
@@ -14,7 +14,6 @@
14 */ 14 */
15 15
16#include <linux/module.h> 16#include <linux/module.h>
17#include <linux/init.h>
18#include <linux/interrupt.h> 17#include <linux/interrupt.h>
19#include <linux/of.h> 18#include <linux/of.h>
20#include <linux/platform_device.h> 19#include <linux/platform_device.h>
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index d0b28bba38be..ffc1a2ebc4ca 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -24,6 +24,8 @@
24#include <linux/device.h> 24#include <linux/device.h>
25#include <linux/init.h> 25#include <linux/init.h>
26#include <linux/cache.h> 26#include <linux/cache.h>
27#include <linux/dma-mapping.h>
28#include <linux/dmaengine.h>
27#include <linux/mutex.h> 29#include <linux/mutex.h>
28#include <linux/of_device.h> 30#include <linux/of_device.h>
29#include <linux/of_irq.h> 31#include <linux/of_irq.h>
@@ -255,13 +257,12 @@ EXPORT_SYMBOL_GPL(spi_bus_type);
255static int spi_drv_probe(struct device *dev) 257static int spi_drv_probe(struct device *dev)
256{ 258{
257 const struct spi_driver *sdrv = to_spi_driver(dev->driver); 259 const struct spi_driver *sdrv = to_spi_driver(dev->driver);
258 struct spi_device *spi = to_spi_device(dev);
259 int ret; 260 int ret;
260 261
261 acpi_dev_pm_attach(&spi->dev, true); 262 acpi_dev_pm_attach(dev, true);
262 ret = sdrv->probe(spi); 263 ret = sdrv->probe(to_spi_device(dev));
263 if (ret) 264 if (ret)
264 acpi_dev_pm_detach(&spi->dev, true); 265 acpi_dev_pm_detach(dev, true);
265 266
266 return ret; 267 return ret;
267} 268}
@@ -269,11 +270,10 @@ static int spi_drv_probe(struct device *dev)
269static int spi_drv_remove(struct device *dev) 270static int spi_drv_remove(struct device *dev)
270{ 271{
271 const struct spi_driver *sdrv = to_spi_driver(dev->driver); 272 const struct spi_driver *sdrv = to_spi_driver(dev->driver);
272 struct spi_device *spi = to_spi_device(dev);
273 int ret; 273 int ret;
274 274
275 ret = sdrv->remove(spi); 275 ret = sdrv->remove(to_spi_device(dev));
276 acpi_dev_pm_detach(&spi->dev, true); 276 acpi_dev_pm_detach(dev, true);
277 277
278 return ret; 278 return ret;
279} 279}
@@ -580,6 +580,169 @@ static void spi_set_cs(struct spi_device *spi, bool enable)
580 spi->master->set_cs(spi, !enable); 580 spi->master->set_cs(spi, !enable);
581} 581}
582 582
583static int spi_map_buf(struct spi_master *master, struct device *dev,
584 struct sg_table *sgt, void *buf, size_t len,
585 enum dma_data_direction dir)
586{
587 const bool vmalloced_buf = is_vmalloc_addr(buf);
588 const int desc_len = vmalloced_buf ? PAGE_SIZE : master->max_dma_len;
589 const int sgs = DIV_ROUND_UP(len, desc_len);
590 struct page *vm_page;
591 void *sg_buf;
592 size_t min;
593 int i, ret;
594
595 ret = sg_alloc_table(sgt, sgs, GFP_KERNEL);
596 if (ret != 0)
597 return ret;
598
599 for (i = 0; i < sgs; i++) {
600 min = min_t(size_t, len, desc_len);
601
602 if (vmalloced_buf) {
603 vm_page = vmalloc_to_page(buf);
604 if (!vm_page) {
605 sg_free_table(sgt);
606 return -ENOMEM;
607 }
608 sg_buf = page_address(vm_page) +
609 ((size_t)buf & ~PAGE_MASK);
610 } else {
611 sg_buf = buf;
612 }
613
614 sg_set_buf(&sgt->sgl[i], sg_buf, min);
615
616 buf += min;
617 len -= min;
618 }
619
620 ret = dma_map_sg(dev, sgt->sgl, sgt->nents, dir);
621 if (ret < 0) {
622 sg_free_table(sgt);
623 return ret;
624 }
625
626 sgt->nents = ret;
627
628 return 0;
629}
630
631static void spi_unmap_buf(struct spi_master *master, struct device *dev,
632 struct sg_table *sgt, enum dma_data_direction dir)
633{
634 if (sgt->orig_nents) {
635 dma_unmap_sg(dev, sgt->sgl, sgt->orig_nents, dir);
636 sg_free_table(sgt);
637 }
638}
639
640static int spi_map_msg(struct spi_master *master, struct spi_message *msg)
641{
642 struct device *tx_dev, *rx_dev;
643 struct spi_transfer *xfer;
644 void *tmp;
645 unsigned int max_tx, max_rx;
646 int ret;
647
648 if (master->flags & (SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX)) {
649 max_tx = 0;
650 max_rx = 0;
651
652 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
653 if ((master->flags & SPI_MASTER_MUST_TX) &&
654 !xfer->tx_buf)
655 max_tx = max(xfer->len, max_tx);
656 if ((master->flags & SPI_MASTER_MUST_RX) &&
657 !xfer->rx_buf)
658 max_rx = max(xfer->len, max_rx);
659 }
660
661 if (max_tx) {
662 tmp = krealloc(master->dummy_tx, max_tx,
663 GFP_KERNEL | GFP_DMA);
664 if (!tmp)
665 return -ENOMEM;
666 master->dummy_tx = tmp;
667 memset(tmp, 0, max_tx);
668 }
669
670 if (max_rx) {
671 tmp = krealloc(master->dummy_rx, max_rx,
672 GFP_KERNEL | GFP_DMA);
673 if (!tmp)
674 return -ENOMEM;
675 master->dummy_rx = tmp;
676 }
677
678 if (max_tx || max_rx) {
679 list_for_each_entry(xfer, &msg->transfers,
680 transfer_list) {
681 if (!xfer->tx_buf)
682 xfer->tx_buf = master->dummy_tx;
683 if (!xfer->rx_buf)
684 xfer->rx_buf = master->dummy_rx;
685 }
686 }
687 }
688
689 if (!master->can_dma)
690 return 0;
691
692 tx_dev = &master->dma_tx->dev->device;
693 rx_dev = &master->dma_rx->dev->device;
694
695 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
696 if (!master->can_dma(master, msg->spi, xfer))
697 continue;
698
699 if (xfer->tx_buf != NULL) {
700 ret = spi_map_buf(master, tx_dev, &xfer->tx_sg,
701 (void *)xfer->tx_buf, xfer->len,
702 DMA_TO_DEVICE);
703 if (ret != 0)
704 return ret;
705 }
706
707 if (xfer->rx_buf != NULL) {
708 ret = spi_map_buf(master, rx_dev, &xfer->rx_sg,
709 xfer->rx_buf, xfer->len,
710 DMA_FROM_DEVICE);
711 if (ret != 0) {
712 spi_unmap_buf(master, tx_dev, &xfer->tx_sg,
713 DMA_TO_DEVICE);
714 return ret;
715 }
716 }
717 }
718
719 master->cur_msg_mapped = true;
720
721 return 0;
722}
723
724static int spi_unmap_msg(struct spi_master *master, struct spi_message *msg)
725{
726 struct spi_transfer *xfer;
727 struct device *tx_dev, *rx_dev;
728
729 if (!master->cur_msg_mapped || !master->can_dma)
730 return 0;
731
732 tx_dev = &master->dma_tx->dev->device;
733 rx_dev = &master->dma_rx->dev->device;
734
735 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
736 if (!master->can_dma(master, msg->spi, xfer))
737 continue;
738
739 spi_unmap_buf(master, rx_dev, &xfer->rx_sg, DMA_FROM_DEVICE);
740 spi_unmap_buf(master, tx_dev, &xfer->tx_sg, DMA_TO_DEVICE);
741 }
742
743 return 0;
744}
745
583/* 746/*
584 * spi_transfer_one_message - Default implementation of transfer_one_message() 747 * spi_transfer_one_message - Default implementation of transfer_one_message()
585 * 748 *
@@ -591,7 +754,6 @@ static int spi_transfer_one_message(struct spi_master *master,
591 struct spi_message *msg) 754 struct spi_message *msg)
592{ 755{
593 struct spi_transfer *xfer; 756 struct spi_transfer *xfer;
594 bool cur_cs = true;
595 bool keep_cs = false; 757 bool keep_cs = false;
596 int ret = 0; 758 int ret = 0;
597 759
@@ -627,8 +789,9 @@ static int spi_transfer_one_message(struct spi_master *master,
627 &msg->transfers)) { 789 &msg->transfers)) {
628 keep_cs = true; 790 keep_cs = true;
629 } else { 791 } else {
630 cur_cs = !cur_cs; 792 spi_set_cs(msg->spi, false);
631 spi_set_cs(msg->spi, cur_cs); 793 udelay(10);
794 spi_set_cs(msg->spi, true);
632 } 795 }
633 } 796 }
634 797
@@ -686,6 +849,10 @@ static void spi_pump_messages(struct kthread_work *work)
686 } 849 }
687 master->busy = false; 850 master->busy = false;
688 spin_unlock_irqrestore(&master->queue_lock, flags); 851 spin_unlock_irqrestore(&master->queue_lock, flags);
852 kfree(master->dummy_rx);
853 master->dummy_rx = NULL;
854 kfree(master->dummy_tx);
855 master->dummy_tx = NULL;
689 if (master->unprepare_transfer_hardware && 856 if (master->unprepare_transfer_hardware &&
690 master->unprepare_transfer_hardware(master)) 857 master->unprepare_transfer_hardware(master))
691 dev_err(&master->dev, 858 dev_err(&master->dev,
@@ -752,6 +919,13 @@ static void spi_pump_messages(struct kthread_work *work)
752 master->cur_msg_prepared = true; 919 master->cur_msg_prepared = true;
753 } 920 }
754 921
922 ret = spi_map_msg(master, master->cur_msg);
923 if (ret) {
924 master->cur_msg->status = ret;
925 spi_finalize_current_message(master);
926 return;
927 }
928
755 ret = master->transfer_one_message(master, master->cur_msg); 929 ret = master->transfer_one_message(master, master->cur_msg);
756 if (ret) { 930 if (ret) {
757 dev_err(&master->dev, 931 dev_err(&master->dev,
@@ -839,6 +1013,8 @@ void spi_finalize_current_message(struct spi_master *master)
839 queue_kthread_work(&master->kworker, &master->pump_messages); 1013 queue_kthread_work(&master->kworker, &master->pump_messages);
840 spin_unlock_irqrestore(&master->queue_lock, flags); 1014 spin_unlock_irqrestore(&master->queue_lock, flags);
841 1015
1016 spi_unmap_msg(master, mesg);
1017
842 if (master->cur_msg_prepared && master->unprepare_message) { 1018 if (master->cur_msg_prepared && master->unprepare_message) {
843 ret = master->unprepare_message(master, mesg); 1019 ret = master->unprepare_message(master, mesg);
844 if (ret) { 1020 if (ret) {
@@ -892,7 +1068,7 @@ static int spi_stop_queue(struct spi_master *master)
892 */ 1068 */
893 while ((!list_empty(&master->queue) || master->busy) && limit--) { 1069 while ((!list_empty(&master->queue) || master->busy) && limit--) {
894 spin_unlock_irqrestore(&master->queue_lock, flags); 1070 spin_unlock_irqrestore(&master->queue_lock, flags);
895 msleep(10); 1071 usleep_range(10000, 11000);
896 spin_lock_irqsave(&master->queue_lock, flags); 1072 spin_lock_irqsave(&master->queue_lock, flags);
897 } 1073 }
898 1074
@@ -1372,6 +1548,8 @@ int spi_register_master(struct spi_master *master)
1372 mutex_init(&master->bus_lock_mutex); 1548 mutex_init(&master->bus_lock_mutex);
1373 master->bus_lock_flag = 0; 1549 master->bus_lock_flag = 0;
1374 init_completion(&master->xfer_completion); 1550 init_completion(&master->xfer_completion);
1551 if (!master->max_dma_len)
1552 master->max_dma_len = INT_MAX;
1375 1553
1376 /* register the device, then userspace will see it. 1554 /* register the device, then userspace will see it.
1377 * registration fails if the bus ID is in use. 1555 * registration fails if the bus ID is in use.
@@ -1597,6 +1775,9 @@ int spi_setup(struct spi_device *spi)
1597 if (!spi->bits_per_word) 1775 if (!spi->bits_per_word)
1598 spi->bits_per_word = 8; 1776 spi->bits_per_word = 8;
1599 1777
1778 if (!spi->max_speed_hz)
1779 spi->max_speed_hz = spi->master->max_speed_hz;
1780
1600 if (spi->master->setup) 1781 if (spi->master->setup)
1601 status = spi->master->setup(spi); 1782 status = spi->master->setup(spi);
1602 1783
@@ -1617,11 +1798,10 @@ static int __spi_validate(struct spi_device *spi, struct spi_message *message)
1617{ 1798{
1618 struct spi_master *master = spi->master; 1799 struct spi_master *master = spi->master;
1619 struct spi_transfer *xfer; 1800 struct spi_transfer *xfer;
1801 int w_size;
1620 1802
1621 if (list_empty(&message->transfers)) 1803 if (list_empty(&message->transfers))
1622 return -EINVAL; 1804 return -EINVAL;
1623 if (!message->complete)
1624 return -EINVAL;
1625 1805
1626 /* Half-duplex links include original MicroWire, and ones with 1806 /* Half-duplex links include original MicroWire, and ones with
1627 * only one data pin like SPI_3WIRE (switches direction) or where 1807 * only one data pin like SPI_3WIRE (switches direction) or where
@@ -1652,12 +1832,13 @@ static int __spi_validate(struct spi_device *spi, struct spi_message *message)
1652 message->frame_length += xfer->len; 1832 message->frame_length += xfer->len;
1653 if (!xfer->bits_per_word) 1833 if (!xfer->bits_per_word)
1654 xfer->bits_per_word = spi->bits_per_word; 1834 xfer->bits_per_word = spi->bits_per_word;
1655 if (!xfer->speed_hz) { 1835
1836 if (!xfer->speed_hz)
1656 xfer->speed_hz = spi->max_speed_hz; 1837 xfer->speed_hz = spi->max_speed_hz;
1657 if (master->max_speed_hz && 1838
1658 xfer->speed_hz > master->max_speed_hz) 1839 if (master->max_speed_hz &&
1659 xfer->speed_hz = master->max_speed_hz; 1840 xfer->speed_hz > master->max_speed_hz)
1660 } 1841 xfer->speed_hz = master->max_speed_hz;
1661 1842
1662 if (master->bits_per_word_mask) { 1843 if (master->bits_per_word_mask) {
1663 /* Only 32 bits fit in the mask */ 1844 /* Only 32 bits fit in the mask */
@@ -1668,12 +1849,24 @@ static int __spi_validate(struct spi_device *spi, struct spi_message *message)
1668 return -EINVAL; 1849 return -EINVAL;
1669 } 1850 }
1670 1851
1852 /*
1853 * SPI transfer length should be multiple of SPI word size
1854 * where SPI word size should be power-of-two multiple
1855 */
1856 if (xfer->bits_per_word <= 8)
1857 w_size = 1;
1858 else if (xfer->bits_per_word <= 16)
1859 w_size = 2;
1860 else
1861 w_size = 4;
1862
1863 /* No partial transfers accepted */
1864 if (xfer->len % w_size)
1865 return -EINVAL;
1866
1671 if (xfer->speed_hz && master->min_speed_hz && 1867 if (xfer->speed_hz && master->min_speed_hz &&
1672 xfer->speed_hz < master->min_speed_hz) 1868 xfer->speed_hz < master->min_speed_hz)
1673 return -EINVAL; 1869 return -EINVAL;
1674 if (xfer->speed_hz && master->max_speed_hz &&
1675 xfer->speed_hz > master->max_speed_hz)
1676 return -EINVAL;
1677 1870
1678 if (xfer->tx_buf && !xfer->tx_nbits) 1871 if (xfer->tx_buf && !xfer->tx_nbits)
1679 xfer->tx_nbits = SPI_NBITS_SINGLE; 1872 xfer->tx_nbits = SPI_NBITS_SINGLE;
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-11 07:20:55 -0500