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-rw-r--r--drivers/spi/Kconfig45
-rw-r--r--drivers/spi/au1550_spi.c207
-rw-r--r--drivers/spi/spi.c4
-rw-r--r--drivers/spi/spi_mpc83xx.c29
-rw-r--r--drivers/spi/spidev.c19
-rw-r--r--drivers/spi/xilinx_spi.c5
6 files changed, 181 insertions, 128 deletions
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 66ec5d8808de..2303521b4f09 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -49,25 +49,26 @@ config SPI_MASTER
49 controller and the protocol drivers for the SPI slave chips 49 controller and the protocol drivers for the SPI slave chips
50 that are connected. 50 that are connected.
51 51
52if SPI_MASTER
53
52comment "SPI Master Controller Drivers" 54comment "SPI Master Controller Drivers"
53 depends on SPI_MASTER
54 55
55config SPI_ATMEL 56config SPI_ATMEL
56 tristate "Atmel SPI Controller" 57 tristate "Atmel SPI Controller"
57 depends on (ARCH_AT91 || AVR32) && SPI_MASTER 58 depends on (ARCH_AT91 || AVR32)
58 help 59 help
59 This selects a driver for the Atmel SPI Controller, present on 60 This selects a driver for the Atmel SPI Controller, present on
60 many AT32 (AVR32) and AT91 (ARM) chips. 61 many AT32 (AVR32) and AT91 (ARM) chips.
61 62
62config SPI_BFIN 63config SPI_BFIN
63 tristate "SPI controller driver for ADI Blackfin5xx" 64 tristate "SPI controller driver for ADI Blackfin5xx"
64 depends on SPI_MASTER && BLACKFIN 65 depends on BLACKFIN
65 help 66 help
66 This is the SPI controller master driver for Blackfin 5xx processor. 67 This is the SPI controller master driver for Blackfin 5xx processor.
67 68
68config SPI_AU1550 69config SPI_AU1550
69 tristate "Au1550/Au12x0 SPI Controller" 70 tristate "Au1550/Au12x0 SPI Controller"
70 depends on SPI_MASTER && (SOC_AU1550 || SOC_AU1200) && EXPERIMENTAL 71 depends on (SOC_AU1550 || SOC_AU1200) && EXPERIMENTAL
71 select SPI_BITBANG 72 select SPI_BITBANG
72 help 73 help
73 If you say yes to this option, support will be included for the 74 If you say yes to this option, support will be included for the
@@ -78,7 +79,6 @@ config SPI_AU1550
78 79
79config SPI_BITBANG 80config SPI_BITBANG
80 tristate "Bitbanging SPI master" 81 tristate "Bitbanging SPI master"
81 depends on SPI_MASTER && EXPERIMENTAL
82 help 82 help
83 With a few GPIO pins, your system can bitbang the SPI protocol. 83 With a few GPIO pins, your system can bitbang the SPI protocol.
84 Select this to get SPI support through I/O pins (GPIO, parallel 84 Select this to get SPI support through I/O pins (GPIO, parallel
@@ -92,7 +92,7 @@ config SPI_BITBANG
92 92
93config SPI_BUTTERFLY 93config SPI_BUTTERFLY
94 tristate "Parallel port adapter for AVR Butterfly (DEVELOPMENT)" 94 tristate "Parallel port adapter for AVR Butterfly (DEVELOPMENT)"
95 depends on SPI_MASTER && PARPORT && EXPERIMENTAL 95 depends on PARPORT
96 select SPI_BITBANG 96 select SPI_BITBANG
97 help 97 help
98 This uses a custom parallel port cable to connect to an AVR 98 This uses a custom parallel port cable to connect to an AVR
@@ -102,14 +102,14 @@ config SPI_BUTTERFLY
102 102
103config SPI_IMX 103config SPI_IMX
104 tristate "Freescale iMX SPI controller" 104 tristate "Freescale iMX SPI controller"
105 depends on SPI_MASTER && ARCH_IMX && EXPERIMENTAL 105 depends on ARCH_IMX && EXPERIMENTAL
106 help 106 help
107 This enables using the Freescale iMX SPI controller in master 107 This enables using the Freescale iMX SPI controller in master
108 mode. 108 mode.
109 109
110config SPI_LM70_LLP 110config SPI_LM70_LLP
111 tristate "Parallel port adapter for LM70 eval board (DEVELOPMENT)" 111 tristate "Parallel port adapter for LM70 eval board (DEVELOPMENT)"
112 depends on SPI_MASTER && PARPORT && EXPERIMENTAL 112 depends on PARPORT && EXPERIMENTAL
113 select SPI_BITBANG 113 select SPI_BITBANG
114 help 114 help
115 This driver supports the NS LM70 LLP Evaluation Board, 115 This driver supports the NS LM70 LLP Evaluation Board,
@@ -118,14 +118,14 @@ config SPI_LM70_LLP
118 118
119config SPI_MPC52xx_PSC 119config SPI_MPC52xx_PSC
120 tristate "Freescale MPC52xx PSC SPI controller" 120 tristate "Freescale MPC52xx PSC SPI controller"
121 depends on SPI_MASTER && PPC_MPC52xx && EXPERIMENTAL 121 depends on PPC_MPC52xx && EXPERIMENTAL
122 help 122 help
123 This enables using the Freescale MPC52xx Programmable Serial 123 This enables using the Freescale MPC52xx Programmable Serial
124 Controller in master SPI mode. 124 Controller in master SPI mode.
125 125
126config SPI_MPC83xx 126config SPI_MPC83xx
127 tristate "Freescale MPC83xx/QUICC Engine SPI controller" 127 tristate "Freescale MPC83xx/QUICC Engine SPI controller"
128 depends on SPI_MASTER && (PPC_83xx || QUICC_ENGINE) && EXPERIMENTAL 128 depends on (PPC_83xx || QUICC_ENGINE) && EXPERIMENTAL
129 help 129 help
130 This enables using the Freescale MPC83xx and QUICC Engine SPI 130 This enables using the Freescale MPC83xx and QUICC Engine SPI
131 controllers in master mode. 131 controllers in master mode.
@@ -137,21 +137,21 @@ config SPI_MPC83xx
137 137
138config SPI_OMAP_UWIRE 138config SPI_OMAP_UWIRE
139 tristate "OMAP1 MicroWire" 139 tristate "OMAP1 MicroWire"
140 depends on SPI_MASTER && ARCH_OMAP1 140 depends on ARCH_OMAP1
141 select SPI_BITBANG 141 select SPI_BITBANG
142 help 142 help
143 This hooks up to the MicroWire controller on OMAP1 chips. 143 This hooks up to the MicroWire controller on OMAP1 chips.
144 144
145config SPI_OMAP24XX 145config SPI_OMAP24XX
146 tristate "McSPI driver for OMAP24xx/OMAP34xx" 146 tristate "McSPI driver for OMAP24xx/OMAP34xx"
147 depends on SPI_MASTER && (ARCH_OMAP24XX || ARCH_OMAP34XX) 147 depends on ARCH_OMAP24XX || ARCH_OMAP34XX
148 help 148 help
149 SPI master controller for OMAP24xx/OMAP34xx Multichannel SPI 149 SPI master controller for OMAP24xx/OMAP34xx Multichannel SPI
150 (McSPI) modules. 150 (McSPI) modules.
151 151
152config SPI_PXA2XX 152config SPI_PXA2XX
153 tristate "PXA2xx SSP SPI master" 153 tristate "PXA2xx SSP SPI master"
154 depends on SPI_MASTER && ARCH_PXA && EXPERIMENTAL 154 depends on ARCH_PXA && EXPERIMENTAL
155 select PXA_SSP 155 select PXA_SSP
156 help 156 help
157 This enables using a PXA2xx SSP port as a SPI master controller. 157 This enables using a PXA2xx SSP port as a SPI master controller.
@@ -160,14 +160,14 @@ config SPI_PXA2XX
160 160
161config SPI_S3C24XX 161config SPI_S3C24XX
162 tristate "Samsung S3C24XX series SPI" 162 tristate "Samsung S3C24XX series SPI"
163 depends on SPI_MASTER && ARCH_S3C2410 && EXPERIMENTAL 163 depends on ARCH_S3C2410 && EXPERIMENTAL
164 select SPI_BITBANG 164 select SPI_BITBANG
165 help 165 help
166 SPI driver for Samsung S3C24XX series ARM SoCs 166 SPI driver for Samsung S3C24XX series ARM SoCs
167 167
168config SPI_S3C24XX_GPIO 168config SPI_S3C24XX_GPIO
169 tristate "Samsung S3C24XX series SPI by GPIO" 169 tristate "Samsung S3C24XX series SPI by GPIO"
170 depends on SPI_MASTER && ARCH_S3C2410 && EXPERIMENTAL 170 depends on ARCH_S3C2410 && EXPERIMENTAL
171 select SPI_BITBANG 171 select SPI_BITBANG
172 help 172 help
173 SPI driver for Samsung S3C24XX series ARM SoCs using 173 SPI driver for Samsung S3C24XX series ARM SoCs using
@@ -177,20 +177,20 @@ config SPI_S3C24XX_GPIO
177 177
178config SPI_SH_SCI 178config SPI_SH_SCI
179 tristate "SuperH SCI SPI controller" 179 tristate "SuperH SCI SPI controller"
180 depends on SPI_MASTER && SUPERH 180 depends on SUPERH
181 select SPI_BITBANG 181 select SPI_BITBANG
182 help 182 help
183 SPI driver for SuperH SCI blocks. 183 SPI driver for SuperH SCI blocks.
184 184
185config SPI_TXX9 185config SPI_TXX9
186 tristate "Toshiba TXx9 SPI controller" 186 tristate "Toshiba TXx9 SPI controller"
187 depends on SPI_MASTER && GENERIC_GPIO && CPU_TX49XX 187 depends on GENERIC_GPIO && CPU_TX49XX
188 help 188 help
189 SPI driver for Toshiba TXx9 MIPS SoCs 189 SPI driver for Toshiba TXx9 MIPS SoCs
190 190
191config SPI_XILINX 191config SPI_XILINX
192 tristate "Xilinx SPI controller" 192 tristate "Xilinx SPI controller"
193 depends on SPI_MASTER && XILINX_VIRTEX && EXPERIMENTAL 193 depends on XILINX_VIRTEX && EXPERIMENTAL
194 select SPI_BITBANG 194 select SPI_BITBANG
195 help 195 help
196 This exposes the SPI controller IP from the Xilinx EDK. 196 This exposes the SPI controller IP from the Xilinx EDK.
@@ -207,11 +207,10 @@ config SPI_XILINX
207# being probably the most widely used ones. 207# being probably the most widely used ones.
208# 208#
209comment "SPI Protocol Masters" 209comment "SPI Protocol Masters"
210 depends on SPI_MASTER
211 210
212config SPI_AT25 211config SPI_AT25
213 tristate "SPI EEPROMs from most vendors" 212 tristate "SPI EEPROMs from most vendors"
214 depends on SPI_MASTER && SYSFS 213 depends on SYSFS
215 help 214 help
216 Enable this driver to get read/write support to most SPI EEPROMs, 215 Enable this driver to get read/write support to most SPI EEPROMs,
217 after you configure the board init code to know about each eeprom 216 after you configure the board init code to know about each eeprom
@@ -222,7 +221,7 @@ config SPI_AT25
222 221
223config SPI_SPIDEV 222config SPI_SPIDEV
224 tristate "User mode SPI device driver support" 223 tristate "User mode SPI device driver support"
225 depends on SPI_MASTER && EXPERIMENTAL 224 depends on EXPERIMENTAL
226 help 225 help
227 This supports user mode SPI protocol drivers. 226 This supports user mode SPI protocol drivers.
228 227
@@ -231,7 +230,7 @@ config SPI_SPIDEV
231 230
232config SPI_TLE62X0 231config SPI_TLE62X0
233 tristate "Infineon TLE62X0 (for power switching)" 232 tristate "Infineon TLE62X0 (for power switching)"
234 depends on SPI_MASTER && SYSFS 233 depends on SYSFS
235 help 234 help
236 SPI driver for Infineon TLE62X0 series line driver chips, 235 SPI driver for Infineon TLE62X0 series line driver chips,
237 such as the TLE6220, TLE6230 and TLE6240. This provides a 236 such as the TLE6220, TLE6230 and TLE6240. This provides a
@@ -242,6 +241,8 @@ config SPI_TLE62X0
242# Add new SPI protocol masters in alphabetical order above this line 241# Add new SPI protocol masters in alphabetical order above this line
243# 242#
244 243
244endif # SPI_MASTER
245
245# (slave support would go here) 246# (slave support would go here)
246 247
247endif # SPI 248endif # SPI
diff --git a/drivers/spi/au1550_spi.c b/drivers/spi/au1550_spi.c
index 072c4a595334..9149689c79d9 100644
--- a/drivers/spi/au1550_spi.c
+++ b/drivers/spi/au1550_spi.c
@@ -26,6 +26,7 @@
26#include <linux/errno.h> 26#include <linux/errno.h>
27#include <linux/device.h> 27#include <linux/device.h>
28#include <linux/platform_device.h> 28#include <linux/platform_device.h>
29#include <linux/resource.h>
29#include <linux/spi/spi.h> 30#include <linux/spi/spi.h>
30#include <linux/spi/spi_bitbang.h> 31#include <linux/spi/spi_bitbang.h>
31#include <linux/dma-mapping.h> 32#include <linux/dma-mapping.h>
@@ -81,6 +82,7 @@ struct au1550_spi {
81 struct spi_master *master; 82 struct spi_master *master;
82 struct device *dev; 83 struct device *dev;
83 struct au1550_spi_info *pdata; 84 struct au1550_spi_info *pdata;
85 struct resource *ioarea;
84}; 86};
85 87
86 88
@@ -96,6 +98,8 @@ static dbdev_tab_t au1550_spi_mem_dbdev =
96 .dev_intpolarity = 0 98 .dev_intpolarity = 0
97}; 99};
98 100
101static int ddma_memid; /* id to above mem dma device */
102
99static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw); 103static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw);
100 104
101 105
@@ -480,9 +484,13 @@ static irqreturn_t au1550_spi_dma_irq_callback(struct au1550_spi *hw)
480 au1xxx_dbdma_reset(hw->dma_tx_ch); 484 au1xxx_dbdma_reset(hw->dma_tx_ch);
481 au1550_spi_reset_fifos(hw); 485 au1550_spi_reset_fifos(hw);
482 486
483 dev_err(hw->dev, 487 if (evnt == PSC_SPIEVNT_RO)
484 "Unexpected SPI error: event=0x%x stat=0x%x!\n", 488 dev_err(hw->dev,
485 evnt, stat); 489 "dma transfer: receive FIFO overflow!\n");
490 else
491 dev_err(hw->dev,
492 "dma transfer: unexpected SPI error "
493 "(event=0x%x stat=0x%x)!\n", evnt, stat);
486 494
487 complete(&hw->master_done); 495 complete(&hw->master_done);
488 return IRQ_HANDLED; 496 return IRQ_HANDLED;
@@ -592,17 +600,17 @@ static irqreturn_t au1550_spi_pio_irq_callback(struct au1550_spi *hw)
592 600
593 if ((evnt & (PSC_SPIEVNT_MM | PSC_SPIEVNT_RO 601 if ((evnt & (PSC_SPIEVNT_MM | PSC_SPIEVNT_RO
594 | PSC_SPIEVNT_RU | PSC_SPIEVNT_TO 602 | PSC_SPIEVNT_RU | PSC_SPIEVNT_TO
595 | PSC_SPIEVNT_TU | PSC_SPIEVNT_SD)) 603 | PSC_SPIEVNT_SD))
596 != 0) { 604 != 0) {
597 dev_err(hw->dev,
598 "Unexpected SPI error: event=0x%x stat=0x%x!\n",
599 evnt, stat);
600 /* 605 /*
601 * due to an error we consider transfer as done, 606 * due to an error we consider transfer as done,
602 * so mask all events until before next transfer start 607 * so mask all events until before next transfer start
603 */ 608 */
604 au1550_spi_mask_ack_all(hw); 609 au1550_spi_mask_ack_all(hw);
605 au1550_spi_reset_fifos(hw); 610 au1550_spi_reset_fifos(hw);
611 dev_err(hw->dev,
612 "pio transfer: unexpected SPI error "
613 "(event=0x%x stat=0x%x)!\n", evnt, stat);
606 complete(&hw->master_done); 614 complete(&hw->master_done);
607 return IRQ_HANDLED; 615 return IRQ_HANDLED;
608 } 616 }
@@ -616,27 +624,50 @@ static irqreturn_t au1550_spi_pio_irq_callback(struct au1550_spi *hw)
616 stat = hw->regs->psc_spistat; 624 stat = hw->regs->psc_spistat;
617 au_sync(); 625 au_sync();
618 626
619 if ((stat & PSC_SPISTAT_RE) == 0 && hw->rx_count < hw->len) { 627 /*
628 * Take care to not let the Rx FIFO overflow.
629 *
630 * We only write a byte if we have read one at least. Initially,
631 * the write fifo is full, so we should read from the read fifo
632 * first.
633 * In case we miss a word from the read fifo, we should get a
634 * RO event and should back out.
635 */
636 if (!(stat & PSC_SPISTAT_RE) && hw->rx_count < hw->len) {
620 hw->rx_word(hw); 637 hw->rx_word(hw);
621 /* ack the receive request event */
622 hw->regs->psc_spievent = PSC_SPIEVNT_RR;
623 au_sync();
624 busy = 1; 638 busy = 1;
625 }
626 639
627 if ((stat & PSC_SPISTAT_TF) == 0 && hw->tx_count < hw->len) { 640 if (!(stat & PSC_SPISTAT_TF) && hw->tx_count < hw->len)
628 hw->tx_word(hw); 641 hw->tx_word(hw);
629 /* ack the transmit request event */
630 hw->regs->psc_spievent = PSC_SPIEVNT_TR;
631 au_sync();
632 busy = 1;
633 } 642 }
634 } while (busy); 643 } while (busy);
635 644
636 evnt = hw->regs->psc_spievent; 645 hw->regs->psc_spievent = PSC_SPIEVNT_RR | PSC_SPIEVNT_TR;
637 au_sync(); 646 au_sync();
638 647
639 if (hw->rx_count >= hw->len || (evnt & PSC_SPIEVNT_MD) != 0) { 648 /*
649 * Restart the SPI transmission in case of a transmit underflow.
650 * This seems to work despite the notes in the Au1550 data book
651 * of Figure 8-4 with flowchart for SPI master operation:
652 *
653 * """Note 1: An XFR Error Interrupt occurs, unless masked,
654 * for any of the following events: Tx FIFO Underflow,
655 * Rx FIFO Overflow, or Multiple-master Error
656 * Note 2: In case of a Tx Underflow Error, all zeroes are
657 * transmitted."""
658 *
659 * By simply restarting the spi transfer on Tx Underflow Error,
660 * we assume that spi transfer was paused instead of zeroes
661 * transmittion mentioned in the Note 2 of Au1550 data book.
662 */
663 if (evnt & PSC_SPIEVNT_TU) {
664 hw->regs->psc_spievent = PSC_SPIEVNT_TU | PSC_SPIEVNT_MD;
665 au_sync();
666 hw->regs->psc_spipcr = PSC_SPIPCR_MS;
667 au_sync();
668 }
669
670 if (hw->rx_count >= hw->len) {
640 /* transfer completed successfully */ 671 /* transfer completed successfully */
641 au1550_spi_mask_ack_all(hw); 672 au1550_spi_mask_ack_all(hw);
642 complete(&hw->master_done); 673 complete(&hw->master_done);
@@ -725,6 +756,8 @@ static void __init au1550_spi_setup_psc_as_spi(struct au1550_spi *hw)
725 stat = hw->regs->psc_spistat; 756 stat = hw->regs->psc_spistat;
726 au_sync(); 757 au_sync();
727 } while ((stat & PSC_SPISTAT_DR) == 0); 758 } while ((stat & PSC_SPISTAT_DR) == 0);
759
760 au1550_spi_reset_fifos(hw);
728} 761}
729 762
730 763
@@ -732,6 +765,7 @@ static int __init au1550_spi_probe(struct platform_device *pdev)
732{ 765{
733 struct au1550_spi *hw; 766 struct au1550_spi *hw;
734 struct spi_master *master; 767 struct spi_master *master;
768 struct resource *r;
735 int err = 0; 769 int err = 0;
736 770
737 master = spi_alloc_master(&pdev->dev, sizeof(struct au1550_spi)); 771 master = spi_alloc_master(&pdev->dev, sizeof(struct au1550_spi));
@@ -753,76 +787,64 @@ static int __init au1550_spi_probe(struct platform_device *pdev)
753 goto err_no_pdata; 787 goto err_no_pdata;
754 } 788 }
755 789
756 platform_set_drvdata(pdev, hw); 790 r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
757 791 if (!r) {
758 init_completion(&hw->master_done); 792 dev_err(&pdev->dev, "no IRQ\n");
759 793 err = -ENODEV;
760 hw->bitbang.master = hw->master; 794 goto err_no_iores;
761 hw->bitbang.setup_transfer = au1550_spi_setupxfer; 795 }
762 hw->bitbang.chipselect = au1550_spi_chipsel; 796 hw->irq = r->start;
763 hw->bitbang.master->setup = au1550_spi_setup; 797
764 hw->bitbang.txrx_bufs = au1550_spi_txrx_bufs; 798 hw->usedma = 0;
799 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
800 if (r) {
801 hw->dma_tx_id = r->start;
802 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
803 if (r) {
804 hw->dma_rx_id = r->start;
805 if (usedma && ddma_memid) {
806 if (pdev->dev.dma_mask == NULL)
807 dev_warn(&pdev->dev, "no dma mask\n");
808 else
809 hw->usedma = 1;
810 }
811 }
812 }
765 813
766 switch (hw->pdata->bus_num) { 814 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
767 case 0: 815 if (!r) {
768 hw->irq = AU1550_PSC0_INT; 816 dev_err(&pdev->dev, "no mmio resource\n");
769 hw->regs = (volatile psc_spi_t *)PSC0_BASE_ADDR; 817 err = -ENODEV;
770 hw->dma_rx_id = DSCR_CMD0_PSC0_RX; 818 goto err_no_iores;
771 hw->dma_tx_id = DSCR_CMD0_PSC0_TX;
772 break;
773 case 1:
774 hw->irq = AU1550_PSC1_INT;
775 hw->regs = (volatile psc_spi_t *)PSC1_BASE_ADDR;
776 hw->dma_rx_id = DSCR_CMD0_PSC1_RX;
777 hw->dma_tx_id = DSCR_CMD0_PSC1_TX;
778 break;
779 case 2:
780 hw->irq = AU1550_PSC2_INT;
781 hw->regs = (volatile psc_spi_t *)PSC2_BASE_ADDR;
782 hw->dma_rx_id = DSCR_CMD0_PSC2_RX;
783 hw->dma_tx_id = DSCR_CMD0_PSC2_TX;
784 break;
785 case 3:
786 hw->irq = AU1550_PSC3_INT;
787 hw->regs = (volatile psc_spi_t *)PSC3_BASE_ADDR;
788 hw->dma_rx_id = DSCR_CMD0_PSC3_RX;
789 hw->dma_tx_id = DSCR_CMD0_PSC3_TX;
790 break;
791 default:
792 dev_err(&pdev->dev, "Wrong bus_num of SPI\n");
793 err = -ENOENT;
794 goto err_no_pdata;
795 } 819 }
796 820
797 if (request_mem_region((unsigned long)hw->regs, sizeof(psc_spi_t), 821 hw->ioarea = request_mem_region(r->start, sizeof(psc_spi_t),
798 pdev->name) == NULL) { 822 pdev->name);
823 if (!hw->ioarea) {
799 dev_err(&pdev->dev, "Cannot reserve iomem region\n"); 824 dev_err(&pdev->dev, "Cannot reserve iomem region\n");
800 err = -ENXIO; 825 err = -ENXIO;
801 goto err_no_iores; 826 goto err_no_iores;
802 } 827 }
803 828
804 829 hw->regs = (psc_spi_t __iomem *)ioremap(r->start, sizeof(psc_spi_t));
805 if (usedma) { 830 if (!hw->regs) {
806 if (pdev->dev.dma_mask == NULL) 831 dev_err(&pdev->dev, "cannot ioremap\n");
807 dev_warn(&pdev->dev, "no dma mask\n"); 832 err = -ENXIO;
808 else 833 goto err_ioremap;
809 hw->usedma = 1;
810 } 834 }
811 835
812 if (hw->usedma) { 836 platform_set_drvdata(pdev, hw);
813 /* 837
814 * create memory device with 8 bits dev_devwidth 838 init_completion(&hw->master_done);
815 * needed for proper byte ordering to spi fifo 839
816 */ 840 hw->bitbang.master = hw->master;
817 int memid = au1xxx_ddma_add_device(&au1550_spi_mem_dbdev); 841 hw->bitbang.setup_transfer = au1550_spi_setupxfer;
818 if (!memid) { 842 hw->bitbang.chipselect = au1550_spi_chipsel;
819 dev_err(&pdev->dev, 843 hw->bitbang.master->setup = au1550_spi_setup;
820 "Cannot create dma 8 bit mem device\n"); 844 hw->bitbang.txrx_bufs = au1550_spi_txrx_bufs;
821 err = -ENXIO;
822 goto err_dma_add_dev;
823 }
824 845
825 hw->dma_tx_ch = au1xxx_dbdma_chan_alloc(memid, 846 if (hw->usedma) {
847 hw->dma_tx_ch = au1xxx_dbdma_chan_alloc(ddma_memid,
826 hw->dma_tx_id, NULL, (void *)hw); 848 hw->dma_tx_id, NULL, (void *)hw);
827 if (hw->dma_tx_ch == 0) { 849 if (hw->dma_tx_ch == 0) {
828 dev_err(&pdev->dev, 850 dev_err(&pdev->dev,
@@ -841,7 +863,7 @@ static int __init au1550_spi_probe(struct platform_device *pdev)
841 863
842 864
843 hw->dma_rx_ch = au1xxx_dbdma_chan_alloc(hw->dma_rx_id, 865 hw->dma_rx_ch = au1xxx_dbdma_chan_alloc(hw->dma_rx_id,
844 memid, NULL, (void *)hw); 866 ddma_memid, NULL, (void *)hw);
845 if (hw->dma_rx_ch == 0) { 867 if (hw->dma_rx_ch == 0) {
846 dev_err(&pdev->dev, 868 dev_err(&pdev->dev,
847 "Cannot allocate rx dma channel\n"); 869 "Cannot allocate rx dma channel\n");
@@ -874,7 +896,7 @@ static int __init au1550_spi_probe(struct platform_device *pdev)
874 goto err_no_irq; 896 goto err_no_irq;
875 } 897 }
876 898
877 master->bus_num = hw->pdata->bus_num; 899 master->bus_num = pdev->id;
878 master->num_chipselect = hw->pdata->num_chipselect; 900 master->num_chipselect = hw->pdata->num_chipselect;
879 901
880 /* 902 /*
@@ -924,8 +946,11 @@ err_no_txdma_descr:
924 au1xxx_dbdma_chan_free(hw->dma_tx_ch); 946 au1xxx_dbdma_chan_free(hw->dma_tx_ch);
925 947
926err_no_txdma: 948err_no_txdma:
927err_dma_add_dev: 949 iounmap((void __iomem *)hw->regs);
928 release_mem_region((unsigned long)hw->regs, sizeof(psc_spi_t)); 950
951err_ioremap:
952 release_resource(hw->ioarea);
953 kfree(hw->ioarea);
929 954
930err_no_iores: 955err_no_iores:
931err_no_pdata: 956err_no_pdata:
@@ -944,7 +969,9 @@ static int __exit au1550_spi_remove(struct platform_device *pdev)
944 969
945 spi_bitbang_stop(&hw->bitbang); 970 spi_bitbang_stop(&hw->bitbang);
946 free_irq(hw->irq, hw); 971 free_irq(hw->irq, hw);
947 release_mem_region((unsigned long)hw->regs, sizeof(psc_spi_t)); 972 iounmap((void __iomem *)hw->regs);
973 release_resource(hw->ioarea);
974 kfree(hw->ioarea);
948 975
949 if (hw->usedma) { 976 if (hw->usedma) {
950 au1550_spi_dma_rxtmp_free(hw); 977 au1550_spi_dma_rxtmp_free(hw);
@@ -971,12 +998,24 @@ static struct platform_driver au1550_spi_drv = {
971 998
972static int __init au1550_spi_init(void) 999static int __init au1550_spi_init(void)
973{ 1000{
1001 /*
1002 * create memory device with 8 bits dev_devwidth
1003 * needed for proper byte ordering to spi fifo
1004 */
1005 if (usedma) {
1006 ddma_memid = au1xxx_ddma_add_device(&au1550_spi_mem_dbdev);
1007 if (!ddma_memid)
1008 printk(KERN_ERR "au1550-spi: cannot add memory"
1009 "dbdma device\n");
1010 }
974 return platform_driver_probe(&au1550_spi_drv, au1550_spi_probe); 1011 return platform_driver_probe(&au1550_spi_drv, au1550_spi_probe);
975} 1012}
976module_init(au1550_spi_init); 1013module_init(au1550_spi_init);
977 1014
978static void __exit au1550_spi_exit(void) 1015static void __exit au1550_spi_exit(void)
979{ 1016{
1017 if (usedma && ddma_memid)
1018 au1xxx_ddma_del_device(ddma_memid);
980 platform_driver_unregister(&au1550_spi_drv); 1019 platform_driver_unregister(&au1550_spi_drv);
981} 1020}
982module_exit(au1550_spi_exit); 1021module_exit(au1550_spi_exit);
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index 1771b2456bfa..ecca4a6a6f94 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -218,6 +218,8 @@ struct spi_device *spi_new_device(struct spi_master *master,
218 if (!spi_master_get(master)) 218 if (!spi_master_get(master))
219 return NULL; 219 return NULL;
220 220
221 WARN_ON(strlen(chip->modalias) >= sizeof(proxy->modalias));
222
221 proxy = kzalloc(sizeof *proxy, GFP_KERNEL); 223 proxy = kzalloc(sizeof *proxy, GFP_KERNEL);
222 if (!proxy) { 224 if (!proxy) {
223 dev_err(dev, "can't alloc dev for cs%d\n", 225 dev_err(dev, "can't alloc dev for cs%d\n",
@@ -229,7 +231,7 @@ struct spi_device *spi_new_device(struct spi_master *master,
229 proxy->max_speed_hz = chip->max_speed_hz; 231 proxy->max_speed_hz = chip->max_speed_hz;
230 proxy->mode = chip->mode; 232 proxy->mode = chip->mode;
231 proxy->irq = chip->irq; 233 proxy->irq = chip->irq;
232 proxy->modalias = chip->modalias; 234 strlcpy(proxy->modalias, chip->modalias, sizeof(proxy->modalias));
233 235
234 snprintf(proxy->dev.bus_id, sizeof proxy->dev.bus_id, 236 snprintf(proxy->dev.bus_id, sizeof proxy->dev.bus_id,
235 "%s.%u", master->dev.bus_id, 237 "%s.%u", master->dev.bus_id,
diff --git a/drivers/spi/spi_mpc83xx.c b/drivers/spi/spi_mpc83xx.c
index 6832da6f7109..070c6219e2d6 100644
--- a/drivers/spi/spi_mpc83xx.c
+++ b/drivers/spi/spi_mpc83xx.c
@@ -266,21 +266,24 @@ int mpc83xx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
266 266
267 cs->hw_mode |= SPMODE_LEN(bits_per_word); 267 cs->hw_mode |= SPMODE_LEN(bits_per_word);
268 268
269 if ((mpc83xx_spi->spibrg / hz) >= 64) { 269 if ((mpc83xx_spi->spibrg / hz) > 64) {
270 pm = mpc83xx_spi->spibrg / (hz * 64) - 1; 270 pm = mpc83xx_spi->spibrg / (hz * 64);
271 if (pm > 0x0f) { 271 if (pm > 16) {
272 dev_err(&spi->dev, "Requested speed is too " 272 cs->hw_mode |= SPMODE_DIV16;
273 "low: %d Hz. Will use %d Hz instead.\n", 273 pm /= 16;
274 hz, mpc83xx_spi->spibrg / 1024); 274 if (pm > 16) {
275 pm = 0x0f; 275 dev_err(&spi->dev, "Requested speed is too "
276 "low: %d Hz. Will use %d Hz instead.\n",
277 hz, mpc83xx_spi->spibrg / 1024);
278 pm = 16;
279 }
276 } 280 }
277 cs->hw_mode |= SPMODE_PM(pm) | SPMODE_DIV16; 281 } else
278 } else {
279 pm = mpc83xx_spi->spibrg / (hz * 4); 282 pm = mpc83xx_spi->spibrg / (hz * 4);
280 if (pm) 283 if (pm)
281 pm--; 284 pm--;
282 cs->hw_mode |= SPMODE_PM(pm); 285
283 } 286 cs->hw_mode |= SPMODE_PM(pm);
284 regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode); 287 regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
285 if (cs->hw_mode != regval) { 288 if (cs->hw_mode != regval) {
286 unsigned long flags; 289 unsigned long flags;
diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c
index 2833fd772a24..e5e0cfed5e3b 100644
--- a/drivers/spi/spidev.c
+++ b/drivers/spi/spidev.c
@@ -228,7 +228,6 @@ static int spidev_message(struct spidev_data *spidev,
228 * We walk the array of user-provided transfers, using each one 228 * We walk the array of user-provided transfers, using each one
229 * to initialize a kernel version of the same transfer. 229 * to initialize a kernel version of the same transfer.
230 */ 230 */
231 mutex_lock(&spidev->buf_lock);
232 buf = spidev->buffer; 231 buf = spidev->buffer;
233 total = 0; 232 total = 0;
234 for (n = n_xfers, k_tmp = k_xfers, u_tmp = u_xfers; 233 for (n = n_xfers, k_tmp = k_xfers, u_tmp = u_xfers;
@@ -296,14 +295,12 @@ static int spidev_message(struct spidev_data *spidev,
296 status = total; 295 status = total;
297 296
298done: 297done:
299 mutex_unlock(&spidev->buf_lock);
300 kfree(k_xfers); 298 kfree(k_xfers);
301 return status; 299 return status;
302} 300}
303 301
304static int 302static long
305spidev_ioctl(struct inode *inode, struct file *filp, 303spidev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
306 unsigned int cmd, unsigned long arg)
307{ 304{
308 int err = 0; 305 int err = 0;
309 int retval = 0; 306 int retval = 0;
@@ -341,6 +338,14 @@ spidev_ioctl(struct inode *inode, struct file *filp,
341 if (spi == NULL) 338 if (spi == NULL)
342 return -ESHUTDOWN; 339 return -ESHUTDOWN;
343 340
341 /* use the buffer lock here for triple duty:
342 * - prevent I/O (from us) so calling spi_setup() is safe;
343 * - prevent concurrent SPI_IOC_WR_* from morphing
344 * data fields while SPI_IOC_RD_* reads them;
345 * - SPI_IOC_MESSAGE needs the buffer locked "normally".
346 */
347 mutex_lock(&spidev->buf_lock);
348
344 switch (cmd) { 349 switch (cmd) {
345 /* read requests */ 350 /* read requests */
346 case SPI_IOC_RD_MODE: 351 case SPI_IOC_RD_MODE:
@@ -456,6 +461,8 @@ spidev_ioctl(struct inode *inode, struct file *filp,
456 kfree(ioc); 461 kfree(ioc);
457 break; 462 break;
458 } 463 }
464
465 mutex_unlock(&spidev->buf_lock);
459 spi_dev_put(spi); 466 spi_dev_put(spi);
460 return retval; 467 return retval;
461} 468}
@@ -533,7 +540,7 @@ static struct file_operations spidev_fops = {
533 */ 540 */
534 .write = spidev_write, 541 .write = spidev_write,
535 .read = spidev_read, 542 .read = spidev_read,
536 .ioctl = spidev_ioctl, 543 .unlocked_ioctl = spidev_ioctl,
537 .open = spidev_open, 544 .open = spidev_open,
538 .release = spidev_release, 545 .release = spidev_release,
539}; 546};
diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
index 113a0468ffcb..68d6f4988fb5 100644
--- a/drivers/spi/xilinx_spi.c
+++ b/drivers/spi/xilinx_spi.c
@@ -353,11 +353,12 @@ static int __init xilinx_spi_probe(struct platform_device *dev)
353 goto put_master; 353 goto put_master;
354 } 354 }
355 355
356 xspi->irq = platform_get_irq(dev, 0); 356 ret = platform_get_irq(dev, 0);
357 if (xspi->irq < 0) { 357 if (ret < 0) {
358 ret = -ENXIO; 358 ret = -ENXIO;
359 goto unmap_io; 359 goto unmap_io;
360 } 360 }
361 xspi->irq = ret;
361 362
362 master->bus_num = pdata->bus_num; 363 master->bus_num = pdata->bus_num;
363 master->num_chipselect = pdata->num_chipselect; 364 master->num_chipselect = pdata->num_chipselect;