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-rw-r--r--drivers/spi/Kconfig5
-rw-r--r--drivers/spi/spi-atmel.c20
-rw-r--r--drivers/spi/spi-bcm2835.c391
-rw-r--r--drivers/spi/spi-bcm53xx.c4
-rw-r--r--drivers/spi/spi-bfin5xx.c3
-rw-r--r--drivers/spi/spi-bitbang-txrx.h18
-rw-r--r--drivers/spi/spi-dw-mid.c179
-rw-r--r--drivers/spi/spi-dw-pci.c4
-rw-r--r--drivers/spi/spi-dw.c310
-rw-r--r--drivers/spi/spi-dw.h70
-rw-r--r--drivers/spi/spi-fsl-dspi.c97
-rw-r--r--drivers/spi/spi-img-spfi.c196
-rw-r--r--drivers/spi/spi-imx.c8
-rw-r--r--drivers/spi/spi-mpc512x-psc.c2
-rw-r--r--drivers/spi/spi-octeon.c2
-rw-r--r--drivers/spi/spi-omap-100k.c101
-rw-r--r--drivers/spi/spi-omap-uwire.c1
-rw-r--r--drivers/spi/spi-pl022.c16
-rw-r--r--drivers/spi/spi-pxa2xx.c192
-rw-r--r--drivers/spi/spi-qup.c345
-rw-r--r--drivers/spi/spi-rockchip.c38
-rw-r--r--drivers/spi/spi-rspi.c124
-rw-r--r--drivers/spi/spi-s3c64xx.c4
-rw-r--r--drivers/spi/spi-sc18is602.c2
-rw-r--r--drivers/spi/spi-st-ssc4.c2
-rw-r--r--drivers/spi/spi-ti-qspi.c22
-rw-r--r--drivers/spi/spi.c126
27 files changed, 1411 insertions, 871 deletions
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index ab8dfbef6f1b..198f96b7fb45 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -159,10 +159,9 @@ config SPI_BUTTERFLY
159 159
160config SPI_CADENCE 160config SPI_CADENCE
161 tristate "Cadence SPI controller" 161 tristate "Cadence SPI controller"
162 depends on ARM
163 help 162 help
164 This selects the Cadence SPI controller master driver 163 This selects the Cadence SPI controller master driver
165 used by Xilinx Zynq. 164 used by Xilinx Zynq and ZynqMP.
166 165
167config SPI_CLPS711X 166config SPI_CLPS711X
168 tristate "CLPS711X host SPI controller" 167 tristate "CLPS711X host SPI controller"
@@ -632,7 +631,7 @@ config SPI_DW_PCI
632 631
633config SPI_DW_MID_DMA 632config SPI_DW_MID_DMA
634 bool "DMA support for DW SPI controller on Intel MID platform" 633 bool "DMA support for DW SPI controller on Intel MID platform"
635 depends on SPI_DW_PCI && INTEL_MID_DMAC 634 depends on SPI_DW_PCI && DW_DMAC_PCI
636 635
637config SPI_DW_MMIO 636config SPI_DW_MMIO
638 tristate "Memory-mapped io interface driver for DW SPI core" 637 tristate "Memory-mapped io interface driver for DW SPI core"
diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
index 9af7841f2e8c..a2f40b1b2225 100644
--- a/drivers/spi/spi-atmel.c
+++ b/drivers/spi/spi-atmel.c
@@ -180,11 +180,17 @@
180 | SPI_BF(name, value)) 180 | SPI_BF(name, value))
181 181
182/* Register access macros */ 182/* Register access macros */
183#ifdef CONFIG_AVR32
183#define spi_readl(port, reg) \ 184#define spi_readl(port, reg) \
184 __raw_readl((port)->regs + SPI_##reg) 185 __raw_readl((port)->regs + SPI_##reg)
185#define spi_writel(port, reg, value) \ 186#define spi_writel(port, reg, value) \
186 __raw_writel((value), (port)->regs + SPI_##reg) 187 __raw_writel((value), (port)->regs + SPI_##reg)
187 188#else
189#define spi_readl(port, reg) \
190 readl_relaxed((port)->regs + SPI_##reg)
191#define spi_writel(port, reg, value) \
192 writel_relaxed((value), (port)->regs + SPI_##reg)
193#endif
188/* use PIO for small transfers, avoiding DMA setup/teardown overhead and 194/* use PIO for small transfers, avoiding DMA setup/teardown overhead and
189 * cache operations; better heuristics consider wordsize and bitrate. 195 * cache operations; better heuristics consider wordsize and bitrate.
190 */ 196 */
@@ -764,17 +770,17 @@ static void atmel_spi_pdc_next_xfer(struct spi_master *master,
764 (unsigned long long)xfer->rx_dma); 770 (unsigned long long)xfer->rx_dma);
765 } 771 }
766 772
767 /* REVISIT: We're waiting for ENDRX before we start the next 773 /* REVISIT: We're waiting for RXBUFF before we start the next
768 * transfer because we need to handle some difficult timing 774 * transfer because we need to handle some difficult timing
769 * issues otherwise. If we wait for ENDTX in one transfer and 775 * issues otherwise. If we wait for TXBUFE in one transfer and
770 * then starts waiting for ENDRX in the next, it's difficult 776 * then starts waiting for RXBUFF in the next, it's difficult
771 * to tell the difference between the ENDRX interrupt we're 777 * to tell the difference between the RXBUFF interrupt we're
772 * actually waiting for and the ENDRX interrupt of the 778 * actually waiting for and the RXBUFF interrupt of the
773 * previous transfer. 779 * previous transfer.
774 * 780 *
775 * It should be doable, though. Just not now... 781 * It should be doable, though. Just not now...
776 */ 782 */
777 spi_writel(as, IER, SPI_BIT(ENDRX) | SPI_BIT(OVRES)); 783 spi_writel(as, IER, SPI_BIT(RXBUFF) | SPI_BIT(OVRES));
778 spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN)); 784 spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
779} 785}
780 786
diff --git a/drivers/spi/spi-bcm2835.c b/drivers/spi/spi-bcm2835.c
index 419a782ab6d5..f63864a893c5 100644
--- a/drivers/spi/spi-bcm2835.c
+++ b/drivers/spi/spi-bcm2835.c
@@ -3,6 +3,7 @@
3 * 3 *
4 * Copyright (C) 2012 Chris Boot 4 * Copyright (C) 2012 Chris Boot
5 * Copyright (C) 2013 Stephen Warren 5 * Copyright (C) 2013 Stephen Warren
6 * Copyright (C) 2015 Martin Sperl
6 * 7 *
7 * This driver is inspired by: 8 * This driver is inspired by:
8 * spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org> 9 * spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
@@ -29,6 +30,7 @@
29#include <linux/module.h> 30#include <linux/module.h>
30#include <linux/of.h> 31#include <linux/of.h>
31#include <linux/of_irq.h> 32#include <linux/of_irq.h>
33#include <linux/of_gpio.h>
32#include <linux/of_device.h> 34#include <linux/of_device.h>
33#include <linux/spi/spi.h> 35#include <linux/spi/spi.h>
34 36
@@ -66,8 +68,10 @@
66#define BCM2835_SPI_CS_CS_10 0x00000002 68#define BCM2835_SPI_CS_CS_10 0x00000002
67#define BCM2835_SPI_CS_CS_01 0x00000001 69#define BCM2835_SPI_CS_CS_01 0x00000001
68 70
69#define BCM2835_SPI_TIMEOUT_MS 30000 71#define BCM2835_SPI_POLLING_LIMIT_US 30
70#define BCM2835_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_NO_CS) 72#define BCM2835_SPI_TIMEOUT_MS 30000
73#define BCM2835_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
74 | SPI_NO_CS | SPI_3WIRE)
71 75
72#define DRV_NAME "spi-bcm2835" 76#define DRV_NAME "spi-bcm2835"
73 77
@@ -75,10 +79,10 @@ struct bcm2835_spi {
75 void __iomem *regs; 79 void __iomem *regs;
76 struct clk *clk; 80 struct clk *clk;
77 int irq; 81 int irq;
78 struct completion done;
79 const u8 *tx_buf; 82 const u8 *tx_buf;
80 u8 *rx_buf; 83 u8 *rx_buf;
81 int len; 84 int tx_len;
85 int rx_len;
82}; 86};
83 87
84static inline u32 bcm2835_rd(struct bcm2835_spi *bs, unsigned reg) 88static inline u32 bcm2835_rd(struct bcm2835_spi *bs, unsigned reg)
@@ -91,205 +95,315 @@ static inline void bcm2835_wr(struct bcm2835_spi *bs, unsigned reg, u32 val)
91 writel(val, bs->regs + reg); 95 writel(val, bs->regs + reg);
92} 96}
93 97
94static inline void bcm2835_rd_fifo(struct bcm2835_spi *bs, int len) 98static inline void bcm2835_rd_fifo(struct bcm2835_spi *bs)
95{ 99{
96 u8 byte; 100 u8 byte;
97 101
98 while (len--) { 102 while ((bs->rx_len) &&
103 (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_RXD)) {
99 byte = bcm2835_rd(bs, BCM2835_SPI_FIFO); 104 byte = bcm2835_rd(bs, BCM2835_SPI_FIFO);
100 if (bs->rx_buf) 105 if (bs->rx_buf)
101 *bs->rx_buf++ = byte; 106 *bs->rx_buf++ = byte;
107 bs->rx_len--;
102 } 108 }
103} 109}
104 110
105static inline void bcm2835_wr_fifo(struct bcm2835_spi *bs, int len) 111static inline void bcm2835_wr_fifo(struct bcm2835_spi *bs)
106{ 112{
107 u8 byte; 113 u8 byte;
108 114
109 if (len > bs->len) 115 while ((bs->tx_len) &&
110 len = bs->len; 116 (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_TXD)) {
111
112 while (len--) {
113 byte = bs->tx_buf ? *bs->tx_buf++ : 0; 117 byte = bs->tx_buf ? *bs->tx_buf++ : 0;
114 bcm2835_wr(bs, BCM2835_SPI_FIFO, byte); 118 bcm2835_wr(bs, BCM2835_SPI_FIFO, byte);
115 bs->len--; 119 bs->tx_len--;
116 } 120 }
117} 121}
118 122
123static void bcm2835_spi_reset_hw(struct spi_master *master)
124{
125 struct bcm2835_spi *bs = spi_master_get_devdata(master);
126 u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
127
128 /* Disable SPI interrupts and transfer */
129 cs &= ~(BCM2835_SPI_CS_INTR |
130 BCM2835_SPI_CS_INTD |
131 BCM2835_SPI_CS_TA);
132 /* and reset RX/TX FIFOS */
133 cs |= BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX;
134
135 /* and reset the SPI_HW */
136 bcm2835_wr(bs, BCM2835_SPI_CS, cs);
137}
138
119static irqreturn_t bcm2835_spi_interrupt(int irq, void *dev_id) 139static irqreturn_t bcm2835_spi_interrupt(int irq, void *dev_id)
120{ 140{
121 struct spi_master *master = dev_id; 141 struct spi_master *master = dev_id;
122 struct bcm2835_spi *bs = spi_master_get_devdata(master); 142 struct bcm2835_spi *bs = spi_master_get_devdata(master);
123 u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
124 143
125 /* 144 /* Read as many bytes as possible from FIFO */
126 * RXR - RX needs Reading. This means 12 (or more) bytes have been 145 bcm2835_rd_fifo(bs);
127 * transmitted and hence 12 (or more) bytes have been received. 146 /* Write as many bytes as possible to FIFO */
128 * 147 bcm2835_wr_fifo(bs);
129 * The FIFO is 16-bytes deep. We check for this interrupt to keep the 148
130 * FIFO full; we have a 4-byte-time buffer for IRQ latency. We check 149 /* based on flags decide if we can finish the transfer */
131 * this before DONE (TX empty) just in case we delayed processing this 150 if (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_DONE) {
132 * interrupt for some reason. 151 /* Transfer complete - reset SPI HW */
133 * 152 bcm2835_spi_reset_hw(master);
134 * We only check for this case if we have more bytes to TX; at the end 153 /* wake up the framework */
135 * of the transfer, we ignore this pipelining optimization, and let 154 complete(&master->xfer_completion);
136 * bcm2835_spi_finish_transfer() drain the RX FIFO. 155 }
156
157 return IRQ_HANDLED;
158}
159
160static int bcm2835_spi_transfer_one_poll(struct spi_master *master,
161 struct spi_device *spi,
162 struct spi_transfer *tfr,
163 u32 cs,
164 unsigned long xfer_time_us)
165{
166 struct bcm2835_spi *bs = spi_master_get_devdata(master);
167 unsigned long timeout = jiffies +
168 max(4 * xfer_time_us * HZ / 1000000, 2uL);
169
170 /* enable HW block without interrupts */
171 bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA);
172
173 /* set timeout to 4x the expected time, or 2 jiffies */
174 /* loop until finished the transfer */
175 while (bs->rx_len) {
176 /* read from fifo as much as possible */
177 bcm2835_rd_fifo(bs);
178 /* fill in tx fifo as much as possible */
179 bcm2835_wr_fifo(bs);
180 /* if we still expect some data after the read,
181 * check for a possible timeout
182 */
183 if (bs->rx_len && time_after(jiffies, timeout)) {
184 /* Transfer complete - reset SPI HW */
185 bcm2835_spi_reset_hw(master);
186 /* and return timeout */
187 return -ETIMEDOUT;
188 }
189 }
190
191 /* Transfer complete - reset SPI HW */
192 bcm2835_spi_reset_hw(master);
193 /* and return without waiting for completion */
194 return 0;
195}
196
197static int bcm2835_spi_transfer_one_irq(struct spi_master *master,
198 struct spi_device *spi,
199 struct spi_transfer *tfr,
200 u32 cs)
201{
202 struct bcm2835_spi *bs = spi_master_get_devdata(master);
203
204 /* fill in fifo if we have gpio-cs
205 * note that there have been rare events where the native-CS
206 * flapped for <1us which may change the behaviour
207 * with gpio-cs this does not happen, so it is implemented
208 * only for this case
137 */ 209 */
138 if (bs->len && (cs & BCM2835_SPI_CS_RXR)) { 210 if (gpio_is_valid(spi->cs_gpio)) {
139 /* Read 12 bytes of data */ 211 /* enable HW block, but without interrupts enabled
140 bcm2835_rd_fifo(bs, 12); 212 * this would triggern an immediate interrupt
141
142 /* Write up to 12 bytes */
143 bcm2835_wr_fifo(bs, 12);
144
145 /*
146 * We must have written something to the TX FIFO due to the
147 * bs->len check above, so cannot be DONE. Hence, return
148 * early. Note that DONE could also be set if we serviced an
149 * RXR interrupt really late.
150 */ 213 */
151 return IRQ_HANDLED; 214 bcm2835_wr(bs, BCM2835_SPI_CS,
215 cs | BCM2835_SPI_CS_TA);
216 /* fill in tx fifo as much as possible */
217 bcm2835_wr_fifo(bs);
152 } 218 }
153 219
154 /* 220 /*
155 * DONE - TX empty. This occurs when we first enable the transfer 221 * Enable the HW block. This will immediately trigger a DONE (TX
156 * since we do not pre-fill the TX FIFO. At any other time, given that 222 * empty) interrupt, upon which we will fill the TX FIFO with the
157 * we refill the TX FIFO above based on RXR, and hence ignore DONE if 223 * first TX bytes. Pre-filling the TX FIFO here to avoid the
158 * RXR is set, DONE really does mean end-of-transfer. 224 * interrupt doesn't work:-(
159 */ 225 */
160 if (cs & BCM2835_SPI_CS_DONE) { 226 cs |= BCM2835_SPI_CS_INTR | BCM2835_SPI_CS_INTD | BCM2835_SPI_CS_TA;
161 if (bs->len) { /* First interrupt in a transfer */ 227 bcm2835_wr(bs, BCM2835_SPI_CS, cs);
162 bcm2835_wr_fifo(bs, 16);
163 } else { /* Transfer complete */
164 /* Disable SPI interrupts */
165 cs &= ~(BCM2835_SPI_CS_INTR | BCM2835_SPI_CS_INTD);
166 bcm2835_wr(bs, BCM2835_SPI_CS, cs);
167
168 /*
169 * Wake up bcm2835_spi_transfer_one(), which will call
170 * bcm2835_spi_finish_transfer(), to drain the RX FIFO.
171 */
172 complete(&bs->done);
173 }
174
175 return IRQ_HANDLED;
176 }
177 228
178 return IRQ_NONE; 229 /* signal that we need to wait for completion */
230 return 1;
179} 231}
180 232
181static int bcm2835_spi_start_transfer(struct spi_device *spi, 233static int bcm2835_spi_transfer_one(struct spi_master *master,
182 struct spi_transfer *tfr) 234 struct spi_device *spi,
235 struct spi_transfer *tfr)
183{ 236{
184 struct bcm2835_spi *bs = spi_master_get_devdata(spi->master); 237 struct bcm2835_spi *bs = spi_master_get_devdata(master);
185 unsigned long spi_hz, clk_hz, cdiv; 238 unsigned long spi_hz, clk_hz, cdiv;
186 u32 cs = BCM2835_SPI_CS_INTR | BCM2835_SPI_CS_INTD | BCM2835_SPI_CS_TA; 239 unsigned long spi_used_hz, xfer_time_us;
240 u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
187 241
242 /* set clock */
188 spi_hz = tfr->speed_hz; 243 spi_hz = tfr->speed_hz;
189 clk_hz = clk_get_rate(bs->clk); 244 clk_hz = clk_get_rate(bs->clk);
190 245
191 if (spi_hz >= clk_hz / 2) { 246 if (spi_hz >= clk_hz / 2) {
192 cdiv = 2; /* clk_hz/2 is the fastest we can go */ 247 cdiv = 2; /* clk_hz/2 is the fastest we can go */
193 } else if (spi_hz) { 248 } else if (spi_hz) {
194 /* CDIV must be a power of two */ 249 /* CDIV must be a multiple of two */
195 cdiv = roundup_pow_of_two(DIV_ROUND_UP(clk_hz, spi_hz)); 250 cdiv = DIV_ROUND_UP(clk_hz, spi_hz);
251 cdiv += (cdiv % 2);
196 252
197 if (cdiv >= 65536) 253 if (cdiv >= 65536)
198 cdiv = 0; /* 0 is the slowest we can go */ 254 cdiv = 0; /* 0 is the slowest we can go */
199 } else 255 } else {
200 cdiv = 0; /* 0 is the slowest we can go */ 256 cdiv = 0; /* 0 is the slowest we can go */
257 }
258 spi_used_hz = cdiv ? (clk_hz / cdiv) : (clk_hz / 65536);
259 bcm2835_wr(bs, BCM2835_SPI_CLK, cdiv);
201 260
261 /* handle all the modes */
262 if ((spi->mode & SPI_3WIRE) && (tfr->rx_buf))
263 cs |= BCM2835_SPI_CS_REN;
202 if (spi->mode & SPI_CPOL) 264 if (spi->mode & SPI_CPOL)
203 cs |= BCM2835_SPI_CS_CPOL; 265 cs |= BCM2835_SPI_CS_CPOL;
204 if (spi->mode & SPI_CPHA) 266 if (spi->mode & SPI_CPHA)
205 cs |= BCM2835_SPI_CS_CPHA; 267 cs |= BCM2835_SPI_CS_CPHA;
206 268
207 if (!(spi->mode & SPI_NO_CS)) { 269 /* for gpio_cs set dummy CS so that no HW-CS get changed
208 if (spi->mode & SPI_CS_HIGH) { 270 * we can not run this in bcm2835_spi_set_cs, as it does
209 cs |= BCM2835_SPI_CS_CSPOL; 271 * not get called for cs_gpio cases, so we need to do it here
210 cs |= BCM2835_SPI_CS_CSPOL0 << spi->chip_select; 272 */
211 } 273 if (gpio_is_valid(spi->cs_gpio) || (spi->mode & SPI_NO_CS))
212 274 cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01;
213 cs |= spi->chip_select;
214 }
215 275
216 reinit_completion(&bs->done); 276 /* set transmit buffers and length */
217 bs->tx_buf = tfr->tx_buf; 277 bs->tx_buf = tfr->tx_buf;
218 bs->rx_buf = tfr->rx_buf; 278 bs->rx_buf = tfr->rx_buf;
219 bs->len = tfr->len; 279 bs->tx_len = tfr->len;
280 bs->rx_len = tfr->len;
220 281
221 bcm2835_wr(bs, BCM2835_SPI_CLK, cdiv); 282 /* calculate the estimated time in us the transfer runs */
222 /* 283 xfer_time_us = tfr->len
223 * Enable the HW block. This will immediately trigger a DONE (TX 284 * 9 /* clocks/byte - SPI-HW waits 1 clock after each byte */
224 * empty) interrupt, upon which we will fill the TX FIFO with the 285 * 1000000 / spi_used_hz;
225 * first TX bytes. Pre-filling the TX FIFO here to avoid the
226 * interrupt doesn't work:-(
227 */
228 bcm2835_wr(bs, BCM2835_SPI_CS, cs);
229 286
230 return 0; 287 /* for short requests run polling*/
288 if (xfer_time_us <= BCM2835_SPI_POLLING_LIMIT_US)
289 return bcm2835_spi_transfer_one_poll(master, spi, tfr,
290 cs, xfer_time_us);
291
292 return bcm2835_spi_transfer_one_irq(master, spi, tfr, cs);
231} 293}
232 294
233static int bcm2835_spi_finish_transfer(struct spi_device *spi, 295static void bcm2835_spi_handle_err(struct spi_master *master,
234 struct spi_transfer *tfr, bool cs_change) 296 struct spi_message *msg)
235{ 297{
236 struct bcm2835_spi *bs = spi_master_get_devdata(spi->master); 298 bcm2835_spi_reset_hw(master);
237 u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS); 299}
300
301static void bcm2835_spi_set_cs(struct spi_device *spi, bool gpio_level)
302{
303 /*
304 * we can assume that we are "native" as per spi_set_cs
305 * calling us ONLY when cs_gpio is not set
306 * we can also assume that we are CS < 3 as per bcm2835_spi_setup
307 * we would not get called because of error handling there.
308 * the level passed is the electrical level not enabled/disabled
309 * so it has to get translated back to enable/disable
310 * see spi_set_cs in spi.c for the implementation
311 */
238 312
239 /* Drain RX FIFO */ 313 struct spi_master *master = spi->master;
240 while (cs & BCM2835_SPI_CS_RXD) { 314 struct bcm2835_spi *bs = spi_master_get_devdata(master);
241 bcm2835_rd_fifo(bs, 1); 315 u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
242 cs = bcm2835_rd(bs, BCM2835_SPI_CS); 316 bool enable;
317
318 /* calculate the enable flag from the passed gpio_level */
319 enable = (spi->mode & SPI_CS_HIGH) ? gpio_level : !gpio_level;
320
321 /* set flags for "reverse" polarity in the registers */
322 if (spi->mode & SPI_CS_HIGH) {
323 /* set the correct CS-bits */
324 cs |= BCM2835_SPI_CS_CSPOL;
325 cs |= BCM2835_SPI_CS_CSPOL0 << spi->chip_select;
326 } else {
327 /* clean the CS-bits */
328 cs &= ~BCM2835_SPI_CS_CSPOL;
329 cs &= ~(BCM2835_SPI_CS_CSPOL0 << spi->chip_select);
243 } 330 }
244 331
245 if (tfr->delay_usecs) 332 /* select the correct chip_select depending on disabled/enabled */
246 udelay(tfr->delay_usecs); 333 if (enable) {
334 /* set cs correctly */
335 if (spi->mode & SPI_NO_CS) {
336 /* use the "undefined" chip-select */
337 cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01;
338 } else {
339 /* set the chip select */
340 cs &= ~(BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01);
341 cs |= spi->chip_select;
342 }
343 } else {
344 /* disable CSPOL which puts HW-CS into deselected state */
345 cs &= ~BCM2835_SPI_CS_CSPOL;
346 /* use the "undefined" chip-select as precaution */
347 cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01;
348 }
247 349
248 if (cs_change) 350 /* finally set the calculated flags in SPI_CS */
249 /* Clear TA flag */ 351 bcm2835_wr(bs, BCM2835_SPI_CS, cs);
250 bcm2835_wr(bs, BCM2835_SPI_CS, cs & ~BCM2835_SPI_CS_TA); 352}
251 353
252 return 0; 354static int chip_match_name(struct gpio_chip *chip, void *data)
355{
356 return !strcmp(chip->label, data);
253} 357}
254 358
255static int bcm2835_spi_transfer_one(struct spi_master *master, 359static int bcm2835_spi_setup(struct spi_device *spi)
256 struct spi_message *mesg)
257{ 360{
258 struct bcm2835_spi *bs = spi_master_get_devdata(master); 361 int err;
259 struct spi_transfer *tfr; 362 struct gpio_chip *chip;
260 struct spi_device *spi = mesg->spi; 363 /*
261 int err = 0; 364 * sanity checking the native-chipselects
262 unsigned int timeout; 365 */
263 bool cs_change; 366 if (spi->mode & SPI_NO_CS)
264 367 return 0;
265 list_for_each_entry(tfr, &mesg->transfers, transfer_list) { 368 if (gpio_is_valid(spi->cs_gpio))
266 err = bcm2835_spi_start_transfer(spi, tfr); 369 return 0;
267 if (err) 370 if (spi->chip_select > 1) {
268 goto out; 371 /* error in the case of native CS requested with CS > 1
269 372 * officially there is a CS2, but it is not documented
270 timeout = wait_for_completion_timeout(&bs->done, 373 * which GPIO is connected with that...
271 msecs_to_jiffies(BCM2835_SPI_TIMEOUT_MS)); 374 */
272 if (!timeout) { 375 dev_err(&spi->dev,
273 err = -ETIMEDOUT; 376 "setup: only two native chip-selects are supported\n");
274 goto out; 377 return -EINVAL;
275 } 378 }
379 /* now translate native cs to GPIO */
276 380
277 cs_change = tfr->cs_change || 381 /* get the gpio chip for the base */
278 list_is_last(&tfr->transfer_list, &mesg->transfers); 382 chip = gpiochip_find("pinctrl-bcm2835", chip_match_name);
383 if (!chip)
384 return 0;
279 385
280 err = bcm2835_spi_finish_transfer(spi, tfr, cs_change); 386 /* and calculate the real CS */
281 if (err) 387 spi->cs_gpio = chip->base + 8 - spi->chip_select;
282 goto out;
283 388
284 mesg->actual_length += (tfr->len - bs->len); 389 /* and set up the "mode" and level */
285 } 390 dev_info(&spi->dev, "setting up native-CS%i as GPIO %i\n",
391 spi->chip_select, spi->cs_gpio);
286 392
287out: 393 /* set up GPIO as output and pull to the correct level */
288 /* Clear FIFOs, and disable the HW block */ 394 err = gpio_direction_output(spi->cs_gpio,
289 bcm2835_wr(bs, BCM2835_SPI_CS, 395 (spi->mode & SPI_CS_HIGH) ? 0 : 1);
290 BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX); 396 if (err) {
291 mesg->status = err; 397 dev_err(&spi->dev,
292 spi_finalize_current_message(master); 398 "could not set CS%i gpio %i as output: %i",
399 spi->chip_select, spi->cs_gpio, err);
400 return err;
401 }
402 /* the implementation of pinctrl-bcm2835 currently does not
403 * set the GPIO value when using gpio_direction_output
404 * so we are setting it here explicitly
405 */
406 gpio_set_value(spi->cs_gpio, (spi->mode & SPI_CS_HIGH) ? 0 : 1);
293 407
294 return 0; 408 return 0;
295} 409}
@@ -312,13 +426,14 @@ static int bcm2835_spi_probe(struct platform_device *pdev)
312 master->mode_bits = BCM2835_SPI_MODE_BITS; 426 master->mode_bits = BCM2835_SPI_MODE_BITS;
313 master->bits_per_word_mask = SPI_BPW_MASK(8); 427 master->bits_per_word_mask = SPI_BPW_MASK(8);
314 master->num_chipselect = 3; 428 master->num_chipselect = 3;
315 master->transfer_one_message = bcm2835_spi_transfer_one; 429 master->setup = bcm2835_spi_setup;
430 master->set_cs = bcm2835_spi_set_cs;
431 master->transfer_one = bcm2835_spi_transfer_one;
432 master->handle_err = bcm2835_spi_handle_err;
316 master->dev.of_node = pdev->dev.of_node; 433 master->dev.of_node = pdev->dev.of_node;
317 434
318 bs = spi_master_get_devdata(master); 435 bs = spi_master_get_devdata(master);
319 436
320 init_completion(&bs->done);
321
322 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 437 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
323 bs->regs = devm_ioremap_resource(&pdev->dev, res); 438 bs->regs = devm_ioremap_resource(&pdev->dev, res);
324 if (IS_ERR(bs->regs)) { 439 if (IS_ERR(bs->regs)) {
@@ -343,13 +458,13 @@ static int bcm2835_spi_probe(struct platform_device *pdev)
343 clk_prepare_enable(bs->clk); 458 clk_prepare_enable(bs->clk);
344 459
345 err = devm_request_irq(&pdev->dev, bs->irq, bcm2835_spi_interrupt, 0, 460 err = devm_request_irq(&pdev->dev, bs->irq, bcm2835_spi_interrupt, 0,
346 dev_name(&pdev->dev), master); 461 dev_name(&pdev->dev), master);
347 if (err) { 462 if (err) {
348 dev_err(&pdev->dev, "could not request IRQ: %d\n", err); 463 dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
349 goto out_clk_disable; 464 goto out_clk_disable;
350 } 465 }
351 466
352 /* initialise the hardware */ 467 /* initialise the hardware with the default polarities */
353 bcm2835_wr(bs, BCM2835_SPI_CS, 468 bcm2835_wr(bs, BCM2835_SPI_CS,
354 BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX); 469 BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);
355 470
diff --git a/drivers/spi/spi-bcm53xx.c b/drivers/spi/spi-bcm53xx.c
index 3fb91c81015a..1520554978a3 100644
--- a/drivers/spi/spi-bcm53xx.c
+++ b/drivers/spi/spi-bcm53xx.c
@@ -44,7 +44,7 @@ static int bcm53xxspi_wait(struct bcm53xxspi *b53spi, unsigned int timeout_ms)
44 u32 tmp; 44 u32 tmp;
45 45
46 /* SPE bit has to be 0 before we read MSPI STATUS */ 46 /* SPE bit has to be 0 before we read MSPI STATUS */
47 deadline = jiffies + BCM53XXSPI_SPE_TIMEOUT_MS * HZ / 1000; 47 deadline = jiffies + msecs_to_jiffies(BCM53XXSPI_SPE_TIMEOUT_MS);
48 do { 48 do {
49 tmp = bcm53xxspi_read(b53spi, B53SPI_MSPI_SPCR2); 49 tmp = bcm53xxspi_read(b53spi, B53SPI_MSPI_SPCR2);
50 if (!(tmp & B53SPI_MSPI_SPCR2_SPE)) 50 if (!(tmp & B53SPI_MSPI_SPCR2_SPE))
@@ -56,7 +56,7 @@ static int bcm53xxspi_wait(struct bcm53xxspi *b53spi, unsigned int timeout_ms)
56 goto spi_timeout; 56 goto spi_timeout;
57 57
58 /* Check status */ 58 /* Check status */
59 deadline = jiffies + timeout_ms * HZ / 1000; 59 deadline = jiffies + msecs_to_jiffies(timeout_ms);
60 do { 60 do {
61 tmp = bcm53xxspi_read(b53spi, B53SPI_MSPI_MSPI_STATUS); 61 tmp = bcm53xxspi_read(b53spi, B53SPI_MSPI_MSPI_STATUS);
62 if (tmp & B53SPI_MSPI_MSPI_STATUS_SPIF) { 62 if (tmp & B53SPI_MSPI_MSPI_STATUS_SPIF) {
diff --git a/drivers/spi/spi-bfin5xx.c b/drivers/spi/spi-bfin5xx.c
index 37079937d2f7..a3d65b4f4944 100644
--- a/drivers/spi/spi-bfin5xx.c
+++ b/drivers/spi/spi-bfin5xx.c
@@ -559,7 +559,7 @@ static void bfin_spi_pump_transfers(unsigned long data)
559 struct spi_transfer *previous = NULL; 559 struct spi_transfer *previous = NULL;
560 struct bfin_spi_slave_data *chip = NULL; 560 struct bfin_spi_slave_data *chip = NULL;
561 unsigned int bits_per_word; 561 unsigned int bits_per_word;
562 u16 cr, cr_width, dma_width, dma_config; 562 u16 cr, cr_width = 0, dma_width, dma_config;
563 u32 tranf_success = 1; 563 u32 tranf_success = 1;
564 u8 full_duplex = 0; 564 u8 full_duplex = 0;
565 565
@@ -648,7 +648,6 @@ static void bfin_spi_pump_transfers(unsigned long data)
648 } else if (bits_per_word == 8) { 648 } else if (bits_per_word == 8) {
649 drv_data->n_bytes = bits_per_word/8; 649 drv_data->n_bytes = bits_per_word/8;
650 drv_data->len = transfer->len; 650 drv_data->len = transfer->len;
651 cr_width = 0;
652 drv_data->ops = &bfin_bfin_spi_transfer_ops_u8; 651 drv_data->ops = &bfin_bfin_spi_transfer_ops_u8;
653 } 652 }
654 cr = bfin_read(&drv_data->regs->ctl) & ~(BIT_CTL_TIMOD | BIT_CTL_WORDSIZE); 653 cr = bfin_read(&drv_data->regs->ctl) & ~(BIT_CTL_TIMOD | BIT_CTL_WORDSIZE);
diff --git a/drivers/spi/spi-bitbang-txrx.h b/drivers/spi/spi-bitbang-txrx.h
index c616e41521be..06b34e5bcfa3 100644
--- a/drivers/spi/spi-bitbang-txrx.h
+++ b/drivers/spi/spi-bitbang-txrx.h
@@ -49,12 +49,17 @@ bitbang_txrx_be_cpha0(struct spi_device *spi,
49{ 49{
50 /* if (cpol == 0) this is SPI_MODE_0; else this is SPI_MODE_2 */ 50 /* if (cpol == 0) this is SPI_MODE_0; else this is SPI_MODE_2 */
51 51
52 bool oldbit = !(word & 1);
52 /* clock starts at inactive polarity */ 53 /* clock starts at inactive polarity */
53 for (word <<= (32 - bits); likely(bits); bits--) { 54 for (word <<= (32 - bits); likely(bits); bits--) {
54 55
55 /* setup MSB (to slave) on trailing edge */ 56 /* setup MSB (to slave) on trailing edge */
56 if ((flags & SPI_MASTER_NO_TX) == 0) 57 if ((flags & SPI_MASTER_NO_TX) == 0) {
57 setmosi(spi, word & (1 << 31)); 58 if ((word & (1 << 31)) != oldbit) {
59 setmosi(spi, word & (1 << 31));
60 oldbit = word & (1 << 31);
61 }
62 }
58 spidelay(nsecs); /* T(setup) */ 63 spidelay(nsecs); /* T(setup) */
59 64
60 setsck(spi, !cpol); 65 setsck(spi, !cpol);
@@ -76,13 +81,18 @@ bitbang_txrx_be_cpha1(struct spi_device *spi,
76{ 81{
77 /* if (cpol == 0) this is SPI_MODE_1; else this is SPI_MODE_3 */ 82 /* if (cpol == 0) this is SPI_MODE_1; else this is SPI_MODE_3 */
78 83
84 bool oldbit = !(word & (1 << 31));
79 /* clock starts at inactive polarity */ 85 /* clock starts at inactive polarity */
80 for (word <<= (32 - bits); likely(bits); bits--) { 86 for (word <<= (32 - bits); likely(bits); bits--) {
81 87
82 /* setup MSB (to slave) on leading edge */ 88 /* setup MSB (to slave) on leading edge */
83 setsck(spi, !cpol); 89 setsck(spi, !cpol);
84 if ((flags & SPI_MASTER_NO_TX) == 0) 90 if ((flags & SPI_MASTER_NO_TX) == 0) {
85 setmosi(spi, word & (1 << 31)); 91 if ((word & (1 << 31)) != oldbit) {
92 setmosi(spi, word & (1 << 31));
93 oldbit = word & (1 << 31);
94 }
95 }
86 spidelay(nsecs); /* T(setup) */ 96 spidelay(nsecs); /* T(setup) */
87 97
88 setsck(spi, cpol); 98 setsck(spi, cpol);
diff --git a/drivers/spi/spi-dw-mid.c b/drivers/spi/spi-dw-mid.c
index a0197fd4e95c..bb1052e748f2 100644
--- a/drivers/spi/spi-dw-mid.c
+++ b/drivers/spi/spi-dw-mid.c
@@ -23,29 +23,31 @@
23#include "spi-dw.h" 23#include "spi-dw.h"
24 24
25#ifdef CONFIG_SPI_DW_MID_DMA 25#ifdef CONFIG_SPI_DW_MID_DMA
26#include <linux/intel_mid_dma.h>
27#include <linux/pci.h> 26#include <linux/pci.h>
27#include <linux/platform_data/dma-dw.h>
28 28
29#define RX_BUSY 0 29#define RX_BUSY 0
30#define TX_BUSY 1 30#define TX_BUSY 1
31 31
32struct mid_dma { 32static struct dw_dma_slave mid_dma_tx = { .dst_id = 1 };
33 struct intel_mid_dma_slave dmas_tx; 33static struct dw_dma_slave mid_dma_rx = { .src_id = 0 };
34 struct intel_mid_dma_slave dmas_rx;
35};
36 34
37static bool mid_spi_dma_chan_filter(struct dma_chan *chan, void *param) 35static bool mid_spi_dma_chan_filter(struct dma_chan *chan, void *param)
38{ 36{
39 struct dw_spi *dws = param; 37 struct dw_dma_slave *s = param;
38
39 if (s->dma_dev != chan->device->dev)
40 return false;
40 41
41 return dws->dma_dev == chan->device->dev; 42 chan->private = s;
43 return true;
42} 44}
43 45
44static int mid_spi_dma_init(struct dw_spi *dws) 46static int mid_spi_dma_init(struct dw_spi *dws)
45{ 47{
46 struct mid_dma *dw_dma = dws->dma_priv;
47 struct pci_dev *dma_dev; 48 struct pci_dev *dma_dev;
48 struct intel_mid_dma_slave *rxs, *txs; 49 struct dw_dma_slave *tx = dws->dma_tx;
50 struct dw_dma_slave *rx = dws->dma_rx;
49 dma_cap_mask_t mask; 51 dma_cap_mask_t mask;
50 52
51 /* 53 /*
@@ -56,28 +58,22 @@ static int mid_spi_dma_init(struct dw_spi *dws)
56 if (!dma_dev) 58 if (!dma_dev)
57 return -ENODEV; 59 return -ENODEV;
58 60
59 dws->dma_dev = &dma_dev->dev;
60
61 dma_cap_zero(mask); 61 dma_cap_zero(mask);
62 dma_cap_set(DMA_SLAVE, mask); 62 dma_cap_set(DMA_SLAVE, mask);
63 63
64 /* 1. Init rx channel */ 64 /* 1. Init rx channel */
65 dws->rxchan = dma_request_channel(mask, mid_spi_dma_chan_filter, dws); 65 rx->dma_dev = &dma_dev->dev;
66 dws->rxchan = dma_request_channel(mask, mid_spi_dma_chan_filter, rx);
66 if (!dws->rxchan) 67 if (!dws->rxchan)
67 goto err_exit; 68 goto err_exit;
68 rxs = &dw_dma->dmas_rx; 69 dws->master->dma_rx = dws->rxchan;
69 rxs->hs_mode = LNW_DMA_HW_HS;
70 rxs->cfg_mode = LNW_DMA_PER_TO_MEM;
71 dws->rxchan->private = rxs;
72 70
73 /* 2. Init tx channel */ 71 /* 2. Init tx channel */
74 dws->txchan = dma_request_channel(mask, mid_spi_dma_chan_filter, dws); 72 tx->dma_dev = &dma_dev->dev;
73 dws->txchan = dma_request_channel(mask, mid_spi_dma_chan_filter, tx);
75 if (!dws->txchan) 74 if (!dws->txchan)
76 goto free_rxchan; 75 goto free_rxchan;
77 txs = &dw_dma->dmas_tx; 76 dws->master->dma_tx = dws->txchan;
78 txs->hs_mode = LNW_DMA_HW_HS;
79 txs->cfg_mode = LNW_DMA_MEM_TO_PER;
80 dws->txchan->private = txs;
81 77
82 dws->dma_inited = 1; 78 dws->dma_inited = 1;
83 return 0; 79 return 0;
@@ -100,6 +96,42 @@ static void mid_spi_dma_exit(struct dw_spi *dws)
100 dma_release_channel(dws->rxchan); 96 dma_release_channel(dws->rxchan);
101} 97}
102 98
99static irqreturn_t dma_transfer(struct dw_spi *dws)
100{
101 u16 irq_status = dw_readl(dws, DW_SPI_ISR);
102
103 if (!irq_status)
104 return IRQ_NONE;
105
106 dw_readl(dws, DW_SPI_ICR);
107 spi_reset_chip(dws);
108
109 dev_err(&dws->master->dev, "%s: FIFO overrun/underrun\n", __func__);
110 dws->master->cur_msg->status = -EIO;
111 spi_finalize_current_transfer(dws->master);
112 return IRQ_HANDLED;
113}
114
115static bool mid_spi_can_dma(struct spi_master *master, struct spi_device *spi,
116 struct spi_transfer *xfer)
117{
118 struct dw_spi *dws = spi_master_get_devdata(master);
119
120 if (!dws->dma_inited)
121 return false;
122
123 return xfer->len > dws->fifo_len;
124}
125
126static enum dma_slave_buswidth convert_dma_width(u32 dma_width) {
127 if (dma_width == 1)
128 return DMA_SLAVE_BUSWIDTH_1_BYTE;
129 else if (dma_width == 2)
130 return DMA_SLAVE_BUSWIDTH_2_BYTES;
131
132 return DMA_SLAVE_BUSWIDTH_UNDEFINED;
133}
134
103/* 135/*
104 * dws->dma_chan_busy is set before the dma transfer starts, callback for tx 136 * dws->dma_chan_busy is set before the dma transfer starts, callback for tx
105 * channel will clear a corresponding bit. 137 * channel will clear a corresponding bit.
@@ -108,37 +140,38 @@ static void dw_spi_dma_tx_done(void *arg)
108{ 140{
109 struct dw_spi *dws = arg; 141 struct dw_spi *dws = arg;
110 142
111 if (test_and_clear_bit(TX_BUSY, &dws->dma_chan_busy) & BIT(RX_BUSY)) 143 clear_bit(TX_BUSY, &dws->dma_chan_busy);
144 if (test_bit(RX_BUSY, &dws->dma_chan_busy))
112 return; 145 return;
113 dw_spi_xfer_done(dws); 146 spi_finalize_current_transfer(dws->master);
114} 147}
115 148
116static struct dma_async_tx_descriptor *dw_spi_dma_prepare_tx(struct dw_spi *dws) 149static struct dma_async_tx_descriptor *dw_spi_dma_prepare_tx(struct dw_spi *dws,
150 struct spi_transfer *xfer)
117{ 151{
118 struct dma_slave_config txconf; 152 struct dma_slave_config txconf;
119 struct dma_async_tx_descriptor *txdesc; 153 struct dma_async_tx_descriptor *txdesc;
120 154
121 if (!dws->tx_dma) 155 if (!xfer->tx_buf)
122 return NULL; 156 return NULL;
123 157
124 txconf.direction = DMA_MEM_TO_DEV; 158 txconf.direction = DMA_MEM_TO_DEV;
125 txconf.dst_addr = dws->dma_addr; 159 txconf.dst_addr = dws->dma_addr;
126 txconf.dst_maxburst = LNW_DMA_MSIZE_16; 160 txconf.dst_maxburst = 16;
127 txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 161 txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
128 txconf.dst_addr_width = dws->dma_width; 162 txconf.dst_addr_width = convert_dma_width(dws->dma_width);
129 txconf.device_fc = false; 163 txconf.device_fc = false;
130 164
131 dmaengine_slave_config(dws->txchan, &txconf); 165 dmaengine_slave_config(dws->txchan, &txconf);
132 166
133 memset(&dws->tx_sgl, 0, sizeof(dws->tx_sgl));
134 dws->tx_sgl.dma_address = dws->tx_dma;
135 dws->tx_sgl.length = dws->len;
136
137 txdesc = dmaengine_prep_slave_sg(dws->txchan, 167 txdesc = dmaengine_prep_slave_sg(dws->txchan,
138 &dws->tx_sgl, 168 xfer->tx_sg.sgl,
139 1, 169 xfer->tx_sg.nents,
140 DMA_MEM_TO_DEV, 170 DMA_MEM_TO_DEV,
141 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 171 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
172 if (!txdesc)
173 return NULL;
174
142 txdesc->callback = dw_spi_dma_tx_done; 175 txdesc->callback = dw_spi_dma_tx_done;
143 txdesc->callback_param = dws; 176 txdesc->callback_param = dws;
144 177
@@ -153,74 +186,74 @@ static void dw_spi_dma_rx_done(void *arg)
153{ 186{
154 struct dw_spi *dws = arg; 187 struct dw_spi *dws = arg;
155 188
156 if (test_and_clear_bit(RX_BUSY, &dws->dma_chan_busy) & BIT(TX_BUSY)) 189 clear_bit(RX_BUSY, &dws->dma_chan_busy);
190 if (test_bit(TX_BUSY, &dws->dma_chan_busy))
157 return; 191 return;
158 dw_spi_xfer_done(dws); 192 spi_finalize_current_transfer(dws->master);
159} 193}
160 194
161static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws) 195static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws,
196 struct spi_transfer *xfer)
162{ 197{
163 struct dma_slave_config rxconf; 198 struct dma_slave_config rxconf;
164 struct dma_async_tx_descriptor *rxdesc; 199 struct dma_async_tx_descriptor *rxdesc;
165 200
166 if (!dws->rx_dma) 201 if (!xfer->rx_buf)
167 return NULL; 202 return NULL;
168 203
169 rxconf.direction = DMA_DEV_TO_MEM; 204 rxconf.direction = DMA_DEV_TO_MEM;
170 rxconf.src_addr = dws->dma_addr; 205 rxconf.src_addr = dws->dma_addr;
171 rxconf.src_maxburst = LNW_DMA_MSIZE_16; 206 rxconf.src_maxburst = 16;
172 rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 207 rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
173 rxconf.src_addr_width = dws->dma_width; 208 rxconf.src_addr_width = convert_dma_width(dws->dma_width);
174 rxconf.device_fc = false; 209 rxconf.device_fc = false;
175 210
176 dmaengine_slave_config(dws->rxchan, &rxconf); 211 dmaengine_slave_config(dws->rxchan, &rxconf);
177 212
178 memset(&dws->rx_sgl, 0, sizeof(dws->rx_sgl));
179 dws->rx_sgl.dma_address = dws->rx_dma;
180 dws->rx_sgl.length = dws->len;
181
182 rxdesc = dmaengine_prep_slave_sg(dws->rxchan, 213 rxdesc = dmaengine_prep_slave_sg(dws->rxchan,
183 &dws->rx_sgl, 214 xfer->rx_sg.sgl,
184 1, 215 xfer->rx_sg.nents,
185 DMA_DEV_TO_MEM, 216 DMA_DEV_TO_MEM,
186 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 217 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
218 if (!rxdesc)
219 return NULL;
220
187 rxdesc->callback = dw_spi_dma_rx_done; 221 rxdesc->callback = dw_spi_dma_rx_done;
188 rxdesc->callback_param = dws; 222 rxdesc->callback_param = dws;
189 223
190 return rxdesc; 224 return rxdesc;
191} 225}
192 226
193static void dw_spi_dma_setup(struct dw_spi *dws) 227static int mid_spi_dma_setup(struct dw_spi *dws, struct spi_transfer *xfer)
194{ 228{
195 u16 dma_ctrl = 0; 229 u16 dma_ctrl = 0;
196 230
197 spi_enable_chip(dws, 0); 231 dw_writel(dws, DW_SPI_DMARDLR, 0xf);
198 232 dw_writel(dws, DW_SPI_DMATDLR, 0x10);
199 dw_writew(dws, DW_SPI_DMARDLR, 0xf);
200 dw_writew(dws, DW_SPI_DMATDLR, 0x10);
201 233
202 if (dws->tx_dma) 234 if (xfer->tx_buf)
203 dma_ctrl |= SPI_DMA_TDMAE; 235 dma_ctrl |= SPI_DMA_TDMAE;
204 if (dws->rx_dma) 236 if (xfer->rx_buf)
205 dma_ctrl |= SPI_DMA_RDMAE; 237 dma_ctrl |= SPI_DMA_RDMAE;
206 dw_writew(dws, DW_SPI_DMACR, dma_ctrl); 238 dw_writel(dws, DW_SPI_DMACR, dma_ctrl);
239
240 /* Set the interrupt mask */
241 spi_umask_intr(dws, SPI_INT_TXOI | SPI_INT_RXUI | SPI_INT_RXOI);
242
243 dws->transfer_handler = dma_transfer;
207 244
208 spi_enable_chip(dws, 1); 245 return 0;
209} 246}
210 247
211static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change) 248static int mid_spi_dma_transfer(struct dw_spi *dws, struct spi_transfer *xfer)
212{ 249{
213 struct dma_async_tx_descriptor *txdesc, *rxdesc; 250 struct dma_async_tx_descriptor *txdesc, *rxdesc;
214 251
215 /* 1. setup DMA related registers */ 252 /* Prepare the TX dma transfer */
216 if (cs_change) 253 txdesc = dw_spi_dma_prepare_tx(dws, xfer);
217 dw_spi_dma_setup(dws);
218
219 /* 2. Prepare the TX dma transfer */
220 txdesc = dw_spi_dma_prepare_tx(dws);
221 254
222 /* 3. Prepare the RX dma transfer */ 255 /* Prepare the RX dma transfer */
223 rxdesc = dw_spi_dma_prepare_rx(dws); 256 rxdesc = dw_spi_dma_prepare_rx(dws, xfer);
224 257
225 /* rx must be started before tx due to spi instinct */ 258 /* rx must be started before tx due to spi instinct */
226 if (rxdesc) { 259 if (rxdesc) {
@@ -238,10 +271,25 @@ static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change)
238 return 0; 271 return 0;
239} 272}
240 273
274static void mid_spi_dma_stop(struct dw_spi *dws)
275{
276 if (test_bit(TX_BUSY, &dws->dma_chan_busy)) {
277 dmaengine_terminate_all(dws->txchan);
278 clear_bit(TX_BUSY, &dws->dma_chan_busy);
279 }
280 if (test_bit(RX_BUSY, &dws->dma_chan_busy)) {
281 dmaengine_terminate_all(dws->rxchan);
282 clear_bit(RX_BUSY, &dws->dma_chan_busy);
283 }
284}
285
241static struct dw_spi_dma_ops mid_dma_ops = { 286static struct dw_spi_dma_ops mid_dma_ops = {
242 .dma_init = mid_spi_dma_init, 287 .dma_init = mid_spi_dma_init,
243 .dma_exit = mid_spi_dma_exit, 288 .dma_exit = mid_spi_dma_exit,
289 .dma_setup = mid_spi_dma_setup,
290 .can_dma = mid_spi_can_dma,
244 .dma_transfer = mid_spi_dma_transfer, 291 .dma_transfer = mid_spi_dma_transfer,
292 .dma_stop = mid_spi_dma_stop,
245}; 293};
246#endif 294#endif
247 295
@@ -274,9 +322,8 @@ int dw_spi_mid_init(struct dw_spi *dws)
274 iounmap(clk_reg); 322 iounmap(clk_reg);
275 323
276#ifdef CONFIG_SPI_DW_MID_DMA 324#ifdef CONFIG_SPI_DW_MID_DMA
277 dws->dma_priv = kzalloc(sizeof(struct mid_dma), GFP_KERNEL); 325 dws->dma_tx = &mid_dma_tx;
278 if (!dws->dma_priv) 326 dws->dma_rx = &mid_dma_rx;
279 return -ENOMEM;
280 dws->dma_ops = &mid_dma_ops; 327 dws->dma_ops = &mid_dma_ops;
281#endif 328#endif
282 return 0; 329 return 0;
diff --git a/drivers/spi/spi-dw-pci.c b/drivers/spi/spi-dw-pci.c
index 5ba331047cbe..6d331e0db331 100644
--- a/drivers/spi/spi-dw-pci.c
+++ b/drivers/spi/spi-dw-pci.c
@@ -36,13 +36,13 @@ struct spi_pci_desc {
36 36
37static struct spi_pci_desc spi_pci_mid_desc_1 = { 37static struct spi_pci_desc spi_pci_mid_desc_1 = {
38 .setup = dw_spi_mid_init, 38 .setup = dw_spi_mid_init,
39 .num_cs = 32, 39 .num_cs = 5,
40 .bus_num = 0, 40 .bus_num = 0,
41}; 41};
42 42
43static struct spi_pci_desc spi_pci_mid_desc_2 = { 43static struct spi_pci_desc spi_pci_mid_desc_2 = {
44 .setup = dw_spi_mid_init, 44 .setup = dw_spi_mid_init,
45 .num_cs = 4, 45 .num_cs = 2,
46 .bus_num = 1, 46 .bus_num = 1,
47}; 47};
48 48
diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c
index 5a97a62b298a..8d67d03c71eb 100644
--- a/drivers/spi/spi-dw.c
+++ b/drivers/spi/spi-dw.c
@@ -28,11 +28,6 @@
28#include <linux/debugfs.h> 28#include <linux/debugfs.h>
29#endif 29#endif
30 30
31#define START_STATE ((void *)0)
32#define RUNNING_STATE ((void *)1)
33#define DONE_STATE ((void *)2)
34#define ERROR_STATE ((void *)-1)
35
36/* Slave spi_dev related */ 31/* Slave spi_dev related */
37struct chip_data { 32struct chip_data {
38 u16 cr0; 33 u16 cr0;
@@ -143,13 +138,26 @@ static inline void dw_spi_debugfs_remove(struct dw_spi *dws)
143} 138}
144#endif /* CONFIG_DEBUG_FS */ 139#endif /* CONFIG_DEBUG_FS */
145 140
141static void dw_spi_set_cs(struct spi_device *spi, bool enable)
142{
143 struct dw_spi *dws = spi_master_get_devdata(spi->master);
144 struct chip_data *chip = spi_get_ctldata(spi);
145
146 /* Chip select logic is inverted from spi_set_cs() */
147 if (chip && chip->cs_control)
148 chip->cs_control(!enable);
149
150 if (!enable)
151 dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select));
152}
153
146/* Return the max entries we can fill into tx fifo */ 154/* Return the max entries we can fill into tx fifo */
147static inline u32 tx_max(struct dw_spi *dws) 155static inline u32 tx_max(struct dw_spi *dws)
148{ 156{
149 u32 tx_left, tx_room, rxtx_gap; 157 u32 tx_left, tx_room, rxtx_gap;
150 158
151 tx_left = (dws->tx_end - dws->tx) / dws->n_bytes; 159 tx_left = (dws->tx_end - dws->tx) / dws->n_bytes;
152 tx_room = dws->fifo_len - dw_readw(dws, DW_SPI_TXFLR); 160 tx_room = dws->fifo_len - dw_readl(dws, DW_SPI_TXFLR);
153 161
154 /* 162 /*
155 * Another concern is about the tx/rx mismatch, we 163 * Another concern is about the tx/rx mismatch, we
@@ -170,7 +178,7 @@ static inline u32 rx_max(struct dw_spi *dws)
170{ 178{
171 u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes; 179 u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes;
172 180
173 return min_t(u32, rx_left, dw_readw(dws, DW_SPI_RXFLR)); 181 return min_t(u32, rx_left, dw_readl(dws, DW_SPI_RXFLR));
174} 182}
175 183
176static void dw_writer(struct dw_spi *dws) 184static void dw_writer(struct dw_spi *dws)
@@ -186,7 +194,7 @@ static void dw_writer(struct dw_spi *dws)
186 else 194 else
187 txw = *(u16 *)(dws->tx); 195 txw = *(u16 *)(dws->tx);
188 } 196 }
189 dw_writew(dws, DW_SPI_DR, txw); 197 dw_writel(dws, DW_SPI_DR, txw);
190 dws->tx += dws->n_bytes; 198 dws->tx += dws->n_bytes;
191 } 199 }
192} 200}
@@ -197,7 +205,7 @@ static void dw_reader(struct dw_spi *dws)
197 u16 rxw; 205 u16 rxw;
198 206
199 while (max--) { 207 while (max--) {
200 rxw = dw_readw(dws, DW_SPI_DR); 208 rxw = dw_readl(dws, DW_SPI_DR);
201 /* Care rx only if the transfer's original "rx" is not null */ 209 /* Care rx only if the transfer's original "rx" is not null */
202 if (dws->rx_end - dws->len) { 210 if (dws->rx_end - dws->len) {
203 if (dws->n_bytes == 1) 211 if (dws->n_bytes == 1)
@@ -209,103 +217,22 @@ static void dw_reader(struct dw_spi *dws)
209 } 217 }
210} 218}
211 219
212static void *next_transfer(struct dw_spi *dws)
213{
214 struct spi_message *msg = dws->cur_msg;
215 struct spi_transfer *trans = dws->cur_transfer;
216
217 /* Move to next transfer */
218 if (trans->transfer_list.next != &msg->transfers) {
219 dws->cur_transfer =
220 list_entry(trans->transfer_list.next,
221 struct spi_transfer,
222 transfer_list);
223 return RUNNING_STATE;
224 }
225
226 return DONE_STATE;
227}
228
229/*
230 * Note: first step is the protocol driver prepares
231 * a dma-capable memory, and this func just need translate
232 * the virt addr to physical
233 */
234static int map_dma_buffers(struct dw_spi *dws)
235{
236 if (!dws->cur_msg->is_dma_mapped
237 || !dws->dma_inited
238 || !dws->cur_chip->enable_dma
239 || !dws->dma_ops)
240 return 0;
241
242 if (dws->cur_transfer->tx_dma)
243 dws->tx_dma = dws->cur_transfer->tx_dma;
244
245 if (dws->cur_transfer->rx_dma)
246 dws->rx_dma = dws->cur_transfer->rx_dma;
247
248 return 1;
249}
250
251/* Caller already set message->status; dma and pio irqs are blocked */
252static void giveback(struct dw_spi *dws)
253{
254 struct spi_transfer *last_transfer;
255 struct spi_message *msg;
256
257 msg = dws->cur_msg;
258 dws->cur_msg = NULL;
259 dws->cur_transfer = NULL;
260 dws->prev_chip = dws->cur_chip;
261 dws->cur_chip = NULL;
262 dws->dma_mapped = 0;
263
264 last_transfer = list_last_entry(&msg->transfers, struct spi_transfer,
265 transfer_list);
266
267 if (!last_transfer->cs_change)
268 spi_chip_sel(dws, msg->spi, 0);
269
270 spi_finalize_current_message(dws->master);
271}
272
273static void int_error_stop(struct dw_spi *dws, const char *msg) 220static void int_error_stop(struct dw_spi *dws, const char *msg)
274{ 221{
275 /* Stop the hw */ 222 spi_reset_chip(dws);
276 spi_enable_chip(dws, 0);
277 223
278 dev_err(&dws->master->dev, "%s\n", msg); 224 dev_err(&dws->master->dev, "%s\n", msg);
279 dws->cur_msg->state = ERROR_STATE; 225 dws->master->cur_msg->status = -EIO;
280 tasklet_schedule(&dws->pump_transfers); 226 spi_finalize_current_transfer(dws->master);
281} 227}
282 228
283void dw_spi_xfer_done(struct dw_spi *dws)
284{
285 /* Update total byte transferred return count actual bytes read */
286 dws->cur_msg->actual_length += dws->len;
287
288 /* Move to next transfer */
289 dws->cur_msg->state = next_transfer(dws);
290
291 /* Handle end of message */
292 if (dws->cur_msg->state == DONE_STATE) {
293 dws->cur_msg->status = 0;
294 giveback(dws);
295 } else
296 tasklet_schedule(&dws->pump_transfers);
297}
298EXPORT_SYMBOL_GPL(dw_spi_xfer_done);
299
300static irqreturn_t interrupt_transfer(struct dw_spi *dws) 229static irqreturn_t interrupt_transfer(struct dw_spi *dws)
301{ 230{
302 u16 irq_status = dw_readw(dws, DW_SPI_ISR); 231 u16 irq_status = dw_readl(dws, DW_SPI_ISR);
303 232
304 /* Error handling */ 233 /* Error handling */
305 if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) { 234 if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
306 dw_readw(dws, DW_SPI_TXOICR); 235 dw_readl(dws, DW_SPI_ICR);
307 dw_readw(dws, DW_SPI_RXOICR);
308 dw_readw(dws, DW_SPI_RXUICR);
309 int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun"); 236 int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun");
310 return IRQ_HANDLED; 237 return IRQ_HANDLED;
311 } 238 }
@@ -313,7 +240,7 @@ static irqreturn_t interrupt_transfer(struct dw_spi *dws)
313 dw_reader(dws); 240 dw_reader(dws);
314 if (dws->rx_end == dws->rx) { 241 if (dws->rx_end == dws->rx) {
315 spi_mask_intr(dws, SPI_INT_TXEI); 242 spi_mask_intr(dws, SPI_INT_TXEI);
316 dw_spi_xfer_done(dws); 243 spi_finalize_current_transfer(dws->master);
317 return IRQ_HANDLED; 244 return IRQ_HANDLED;
318 } 245 }
319 if (irq_status & SPI_INT_TXEI) { 246 if (irq_status & SPI_INT_TXEI) {
@@ -328,13 +255,14 @@ static irqreturn_t interrupt_transfer(struct dw_spi *dws)
328 255
329static irqreturn_t dw_spi_irq(int irq, void *dev_id) 256static irqreturn_t dw_spi_irq(int irq, void *dev_id)
330{ 257{
331 struct dw_spi *dws = dev_id; 258 struct spi_master *master = dev_id;
332 u16 irq_status = dw_readw(dws, DW_SPI_ISR) & 0x3f; 259 struct dw_spi *dws = spi_master_get_devdata(master);
260 u16 irq_status = dw_readl(dws, DW_SPI_ISR) & 0x3f;
333 261
334 if (!irq_status) 262 if (!irq_status)
335 return IRQ_NONE; 263 return IRQ_NONE;
336 264
337 if (!dws->cur_msg) { 265 if (!master->cur_msg) {
338 spi_mask_intr(dws, SPI_INT_TXEI); 266 spi_mask_intr(dws, SPI_INT_TXEI);
339 return IRQ_HANDLED; 267 return IRQ_HANDLED;
340 } 268 }
@@ -343,7 +271,7 @@ static irqreturn_t dw_spi_irq(int irq, void *dev_id)
343} 271}
344 272
345/* Must be called inside pump_transfers() */ 273/* Must be called inside pump_transfers() */
346static void poll_transfer(struct dw_spi *dws) 274static int poll_transfer(struct dw_spi *dws)
347{ 275{
348 do { 276 do {
349 dw_writer(dws); 277 dw_writer(dws);
@@ -351,64 +279,32 @@ static void poll_transfer(struct dw_spi *dws)
351 cpu_relax(); 279 cpu_relax();
352 } while (dws->rx_end > dws->rx); 280 } while (dws->rx_end > dws->rx);
353 281
354 dw_spi_xfer_done(dws); 282 return 0;
355} 283}
356 284
357static void pump_transfers(unsigned long data) 285static int dw_spi_transfer_one(struct spi_master *master,
286 struct spi_device *spi, struct spi_transfer *transfer)
358{ 287{
359 struct dw_spi *dws = (struct dw_spi *)data; 288 struct dw_spi *dws = spi_master_get_devdata(master);
360 struct spi_message *message = NULL; 289 struct chip_data *chip = spi_get_ctldata(spi);
361 struct spi_transfer *transfer = NULL;
362 struct spi_transfer *previous = NULL;
363 struct spi_device *spi = NULL;
364 struct chip_data *chip = NULL;
365 u8 bits = 0;
366 u8 imask = 0; 290 u8 imask = 0;
367 u8 cs_change = 0; 291 u16 txlevel = 0;
368 u16 txint_level = 0;
369 u16 clk_div = 0; 292 u16 clk_div = 0;
370 u32 speed = 0; 293 u32 speed = 0;
371 u32 cr0 = 0; 294 u32 cr0 = 0;
295 int ret;
372 296
373 /* Get current state information */ 297 dws->dma_mapped = 0;
374 message = dws->cur_msg;
375 transfer = dws->cur_transfer;
376 chip = dws->cur_chip;
377 spi = message->spi;
378
379 if (message->state == ERROR_STATE) {
380 message->status = -EIO;
381 goto early_exit;
382 }
383
384 /* Handle end of message */
385 if (message->state == DONE_STATE) {
386 message->status = 0;
387 goto early_exit;
388 }
389
390 /* Delay if requested at end of transfer */
391 if (message->state == RUNNING_STATE) {
392 previous = list_entry(transfer->transfer_list.prev,
393 struct spi_transfer,
394 transfer_list);
395 if (previous->delay_usecs)
396 udelay(previous->delay_usecs);
397 }
398
399 dws->n_bytes = chip->n_bytes; 298 dws->n_bytes = chip->n_bytes;
400 dws->dma_width = chip->dma_width; 299 dws->dma_width = chip->dma_width;
401 dws->cs_control = chip->cs_control;
402 300
403 dws->rx_dma = transfer->rx_dma;
404 dws->tx_dma = transfer->tx_dma;
405 dws->tx = (void *)transfer->tx_buf; 301 dws->tx = (void *)transfer->tx_buf;
406 dws->tx_end = dws->tx + transfer->len; 302 dws->tx_end = dws->tx + transfer->len;
407 dws->rx = transfer->rx_buf; 303 dws->rx = transfer->rx_buf;
408 dws->rx_end = dws->rx + transfer->len; 304 dws->rx_end = dws->rx + transfer->len;
409 dws->len = dws->cur_transfer->len; 305 dws->len = transfer->len;
410 if (chip != dws->prev_chip) 306
411 cs_change = 1; 307 spi_enable_chip(dws, 0);
412 308
413 cr0 = chip->cr0; 309 cr0 = chip->cr0;
414 310
@@ -416,32 +312,37 @@ static void pump_transfers(unsigned long data)
416 if (transfer->speed_hz) { 312 if (transfer->speed_hz) {
417 speed = chip->speed_hz; 313 speed = chip->speed_hz;
418 314
419 if ((transfer->speed_hz != speed) || (!chip->clk_div)) { 315 if ((transfer->speed_hz != speed) || !chip->clk_div) {
420 speed = transfer->speed_hz; 316 speed = transfer->speed_hz;
421 317
422 /* clk_div doesn't support odd number */ 318 /* clk_div doesn't support odd number */
423 clk_div = dws->max_freq / speed; 319 clk_div = (dws->max_freq / speed + 1) & 0xfffe;
424 clk_div = (clk_div + 1) & 0xfffe;
425 320
426 chip->speed_hz = speed; 321 chip->speed_hz = speed;
427 chip->clk_div = clk_div; 322 chip->clk_div = clk_div;
323
324 spi_set_clk(dws, chip->clk_div);
428 } 325 }
429 } 326 }
430 if (transfer->bits_per_word) { 327 if (transfer->bits_per_word) {
431 bits = transfer->bits_per_word; 328 if (transfer->bits_per_word == 8) {
432 dws->n_bytes = dws->dma_width = bits >> 3; 329 dws->n_bytes = 1;
433 cr0 = (bits - 1) 330 dws->dma_width = 1;
331 } else if (transfer->bits_per_word == 16) {
332 dws->n_bytes = 2;
333 dws->dma_width = 2;
334 }
335 cr0 = (transfer->bits_per_word - 1)
434 | (chip->type << SPI_FRF_OFFSET) 336 | (chip->type << SPI_FRF_OFFSET)
435 | (spi->mode << SPI_MODE_OFFSET) 337 | (spi->mode << SPI_MODE_OFFSET)
436 | (chip->tmode << SPI_TMOD_OFFSET); 338 | (chip->tmode << SPI_TMOD_OFFSET);
437 } 339 }
438 message->state = RUNNING_STATE;
439 340
440 /* 341 /*
441 * Adjust transfer mode if necessary. Requires platform dependent 342 * Adjust transfer mode if necessary. Requires platform dependent
442 * chipselect mechanism. 343 * chipselect mechanism.
443 */ 344 */
444 if (dws->cs_control) { 345 if (chip->cs_control) {
445 if (dws->rx && dws->tx) 346 if (dws->rx && dws->tx)
446 chip->tmode = SPI_TMOD_TR; 347 chip->tmode = SPI_TMOD_TR;
447 else if (dws->rx) 348 else if (dws->rx)
@@ -453,80 +354,60 @@ static void pump_transfers(unsigned long data)
453 cr0 |= (chip->tmode << SPI_TMOD_OFFSET); 354 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
454 } 355 }
455 356
357 dw_writel(dws, DW_SPI_CTRL0, cr0);
358
456 /* Check if current transfer is a DMA transaction */ 359 /* Check if current transfer is a DMA transaction */
457 dws->dma_mapped = map_dma_buffers(dws); 360 if (master->can_dma && master->can_dma(master, spi, transfer))
361 dws->dma_mapped = master->cur_msg_mapped;
362
363 /* For poll mode just disable all interrupts */
364 spi_mask_intr(dws, 0xff);
458 365
459 /* 366 /*
460 * Interrupt mode 367 * Interrupt mode
461 * we only need set the TXEI IRQ, as TX/RX always happen syncronizely 368 * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
462 */ 369 */
463 if (!dws->dma_mapped && !chip->poll_mode) { 370 if (dws->dma_mapped) {
464 int templen = dws->len / dws->n_bytes; 371 ret = dws->dma_ops->dma_setup(dws, transfer);
465 372 if (ret < 0) {
466 txint_level = dws->fifo_len / 2; 373 spi_enable_chip(dws, 1);
467 txint_level = (templen > txint_level) ? txint_level : templen; 374 return ret;
375 }
376 } else if (!chip->poll_mode) {
377 txlevel = min_t(u16, dws->fifo_len / 2, dws->len / dws->n_bytes);
378 dw_writel(dws, DW_SPI_TXFLTR, txlevel);
468 379
380 /* Set the interrupt mask */
469 imask |= SPI_INT_TXEI | SPI_INT_TXOI | 381 imask |= SPI_INT_TXEI | SPI_INT_TXOI |
470 SPI_INT_RXUI | SPI_INT_RXOI; 382 SPI_INT_RXUI | SPI_INT_RXOI;
383 spi_umask_intr(dws, imask);
384
471 dws->transfer_handler = interrupt_transfer; 385 dws->transfer_handler = interrupt_transfer;
472 } 386 }
473 387
474 /* 388 spi_enable_chip(dws, 1);
475 * Reprogram registers only if
476 * 1. chip select changes
477 * 2. clk_div is changed
478 * 3. control value changes
479 */
480 if (dw_readw(dws, DW_SPI_CTRL0) != cr0 || cs_change || clk_div || imask) {
481 spi_enable_chip(dws, 0);
482
483 if (dw_readw(dws, DW_SPI_CTRL0) != cr0)
484 dw_writew(dws, DW_SPI_CTRL0, cr0);
485
486 spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);
487 spi_chip_sel(dws, spi, 1);
488
489 /* Set the interrupt mask, for poll mode just disable all int */
490 spi_mask_intr(dws, 0xff);
491 if (imask)
492 spi_umask_intr(dws, imask);
493 if (txint_level)
494 dw_writew(dws, DW_SPI_TXFLTR, txint_level);
495 389
496 spi_enable_chip(dws, 1); 390 if (dws->dma_mapped) {
497 if (cs_change) 391 ret = dws->dma_ops->dma_transfer(dws, transfer);
498 dws->prev_chip = chip; 392 if (ret < 0)
393 return ret;
499 } 394 }
500 395
501 if (dws->dma_mapped)
502 dws->dma_ops->dma_transfer(dws, cs_change);
503
504 if (chip->poll_mode) 396 if (chip->poll_mode)
505 poll_transfer(dws); 397 return poll_transfer(dws);
506
507 return;
508 398
509early_exit: 399 return 1;
510 giveback(dws);
511} 400}
512 401
513static int dw_spi_transfer_one_message(struct spi_master *master, 402static void dw_spi_handle_err(struct spi_master *master,
514 struct spi_message *msg) 403 struct spi_message *msg)
515{ 404{
516 struct dw_spi *dws = spi_master_get_devdata(master); 405 struct dw_spi *dws = spi_master_get_devdata(master);
517 406
518 dws->cur_msg = msg; 407 if (dws->dma_mapped)
519 /* Initial message state */ 408 dws->dma_ops->dma_stop(dws);
520 dws->cur_msg->state = START_STATE;
521 dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,
522 struct spi_transfer,
523 transfer_list);
524 dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);
525
526 /* Launch transfers */
527 tasklet_schedule(&dws->pump_transfers);
528 409
529 return 0; 410 spi_reset_chip(dws);
530} 411}
531 412
532/* This may be called twice for each spi dev */ 413/* This may be called twice for each spi dev */
@@ -561,8 +442,6 @@ static int dw_spi_setup(struct spi_device *spi)
561 442
562 chip->rx_threshold = 0; 443 chip->rx_threshold = 0;
563 chip->tx_threshold = 0; 444 chip->tx_threshold = 0;
564
565 chip->enable_dma = chip_info->enable_dma;
566 } 445 }
567 446
568 if (spi->bits_per_word == 8) { 447 if (spi->bits_per_word == 8) {
@@ -610,9 +489,7 @@ static void dw_spi_cleanup(struct spi_device *spi)
610/* Restart the controller, disable all interrupts, clean rx fifo */ 489/* Restart the controller, disable all interrupts, clean rx fifo */
611static void spi_hw_init(struct device *dev, struct dw_spi *dws) 490static void spi_hw_init(struct device *dev, struct dw_spi *dws)
612{ 491{
613 spi_enable_chip(dws, 0); 492 spi_reset_chip(dws);
614 spi_mask_intr(dws, 0xff);
615 spi_enable_chip(dws, 1);
616 493
617 /* 494 /*
618 * Try to detect the FIFO depth if not set by interface driver, 495 * Try to detect the FIFO depth if not set by interface driver,
@@ -621,14 +498,14 @@ static void spi_hw_init(struct device *dev, struct dw_spi *dws)
621 if (!dws->fifo_len) { 498 if (!dws->fifo_len) {
622 u32 fifo; 499 u32 fifo;
623 500
624 for (fifo = 2; fifo <= 256; fifo++) { 501 for (fifo = 1; fifo < 256; fifo++) {
625 dw_writew(dws, DW_SPI_TXFLTR, fifo); 502 dw_writel(dws, DW_SPI_TXFLTR, fifo);
626 if (fifo != dw_readw(dws, DW_SPI_TXFLTR)) 503 if (fifo != dw_readl(dws, DW_SPI_TXFLTR))
627 break; 504 break;
628 } 505 }
629 dw_writew(dws, DW_SPI_TXFLTR, 0); 506 dw_writel(dws, DW_SPI_TXFLTR, 0);
630 507
631 dws->fifo_len = (fifo == 2) ? 0 : fifo - 1; 508 dws->fifo_len = (fifo == 1) ? 0 : fifo;
632 dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len); 509 dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len);
633 } 510 }
634} 511}
@@ -646,13 +523,12 @@ int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
646 523
647 dws->master = master; 524 dws->master = master;
648 dws->type = SSI_MOTO_SPI; 525 dws->type = SSI_MOTO_SPI;
649 dws->prev_chip = NULL;
650 dws->dma_inited = 0; 526 dws->dma_inited = 0;
651 dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60); 527 dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60);
652 snprintf(dws->name, sizeof(dws->name), "dw_spi%d", dws->bus_num); 528 snprintf(dws->name, sizeof(dws->name), "dw_spi%d", dws->bus_num);
653 529
654 ret = devm_request_irq(dev, dws->irq, dw_spi_irq, IRQF_SHARED, 530 ret = devm_request_irq(dev, dws->irq, dw_spi_irq, IRQF_SHARED,
655 dws->name, dws); 531 dws->name, master);
656 if (ret < 0) { 532 if (ret < 0) {
657 dev_err(&master->dev, "can not get IRQ\n"); 533 dev_err(&master->dev, "can not get IRQ\n");
658 goto err_free_master; 534 goto err_free_master;
@@ -664,7 +540,9 @@ int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
664 master->num_chipselect = dws->num_cs; 540 master->num_chipselect = dws->num_cs;
665 master->setup = dw_spi_setup; 541 master->setup = dw_spi_setup;
666 master->cleanup = dw_spi_cleanup; 542 master->cleanup = dw_spi_cleanup;
667 master->transfer_one_message = dw_spi_transfer_one_message; 543 master->set_cs = dw_spi_set_cs;
544 master->transfer_one = dw_spi_transfer_one;
545 master->handle_err = dw_spi_handle_err;
668 master->max_speed_hz = dws->max_freq; 546 master->max_speed_hz = dws->max_freq;
669 master->dev.of_node = dev->of_node; 547 master->dev.of_node = dev->of_node;
670 548
@@ -676,11 +554,11 @@ int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
676 if (ret) { 554 if (ret) {
677 dev_warn(dev, "DMA init failed\n"); 555 dev_warn(dev, "DMA init failed\n");
678 dws->dma_inited = 0; 556 dws->dma_inited = 0;
557 } else {
558 master->can_dma = dws->dma_ops->can_dma;
679 } 559 }
680 } 560 }
681 561
682 tasklet_init(&dws->pump_transfers, pump_transfers, (unsigned long)dws);
683
684 spi_master_set_devdata(master, dws); 562 spi_master_set_devdata(master, dws);
685 ret = devm_spi_register_master(dev, master); 563 ret = devm_spi_register_master(dev, master);
686 if (ret) { 564 if (ret) {
diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
index 3d32be68c142..6c91391c1a4f 100644
--- a/drivers/spi/spi-dw.h
+++ b/drivers/spi/spi-dw.h
@@ -91,12 +91,15 @@ struct dw_spi;
91struct dw_spi_dma_ops { 91struct dw_spi_dma_ops {
92 int (*dma_init)(struct dw_spi *dws); 92 int (*dma_init)(struct dw_spi *dws);
93 void (*dma_exit)(struct dw_spi *dws); 93 void (*dma_exit)(struct dw_spi *dws);
94 int (*dma_transfer)(struct dw_spi *dws, int cs_change); 94 int (*dma_setup)(struct dw_spi *dws, struct spi_transfer *xfer);
95 bool (*can_dma)(struct spi_master *master, struct spi_device *spi,
96 struct spi_transfer *xfer);
97 int (*dma_transfer)(struct dw_spi *dws, struct spi_transfer *xfer);
98 void (*dma_stop)(struct dw_spi *dws);
95}; 99};
96 100
97struct dw_spi { 101struct dw_spi {
98 struct spi_master *master; 102 struct spi_master *master;
99 struct spi_device *cur_dev;
100 enum dw_ssi_type type; 103 enum dw_ssi_type type;
101 char name[16]; 104 char name[16];
102 105
@@ -109,41 +112,26 @@ struct dw_spi {
109 u16 bus_num; 112 u16 bus_num;
110 u16 num_cs; /* supported slave numbers */ 113 u16 num_cs; /* supported slave numbers */
111 114
112 /* Message Transfer pump */
113 struct tasklet_struct pump_transfers;
114
115 /* Current message transfer state info */ 115 /* Current message transfer state info */
116 struct spi_message *cur_msg;
117 struct spi_transfer *cur_transfer;
118 struct chip_data *cur_chip;
119 struct chip_data *prev_chip;
120 size_t len; 116 size_t len;
121 void *tx; 117 void *tx;
122 void *tx_end; 118 void *tx_end;
123 void *rx; 119 void *rx;
124 void *rx_end; 120 void *rx_end;
125 int dma_mapped; 121 int dma_mapped;
126 dma_addr_t rx_dma;
127 dma_addr_t tx_dma;
128 size_t rx_map_len;
129 size_t tx_map_len;
130 u8 n_bytes; /* current is a 1/2 bytes op */ 122 u8 n_bytes; /* current is a 1/2 bytes op */
131 u8 max_bits_per_word; /* maxim is 16b */
132 u32 dma_width; 123 u32 dma_width;
133 irqreturn_t (*transfer_handler)(struct dw_spi *dws); 124 irqreturn_t (*transfer_handler)(struct dw_spi *dws);
134 void (*cs_control)(u32 command);
135 125
136 /* Dma info */ 126 /* DMA info */
137 int dma_inited; 127 int dma_inited;
138 struct dma_chan *txchan; 128 struct dma_chan *txchan;
139 struct scatterlist tx_sgl;
140 struct dma_chan *rxchan; 129 struct dma_chan *rxchan;
141 struct scatterlist rx_sgl;
142 unsigned long dma_chan_busy; 130 unsigned long dma_chan_busy;
143 struct device *dma_dev;
144 dma_addr_t dma_addr; /* phy address of the Data register */ 131 dma_addr_t dma_addr; /* phy address of the Data register */
145 struct dw_spi_dma_ops *dma_ops; 132 struct dw_spi_dma_ops *dma_ops;
146 void *dma_priv; /* platform relate info */ 133 void *dma_tx;
134 void *dma_rx;
147 135
148 /* Bus interface info */ 136 /* Bus interface info */
149 void *priv; 137 void *priv;
@@ -162,16 +150,6 @@ static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val)
162 __raw_writel(val, dws->regs + offset); 150 __raw_writel(val, dws->regs + offset);
163} 151}
164 152
165static inline u16 dw_readw(struct dw_spi *dws, u32 offset)
166{
167 return __raw_readw(dws->regs + offset);
168}
169
170static inline void dw_writew(struct dw_spi *dws, u32 offset, u16 val)
171{
172 __raw_writew(val, dws->regs + offset);
173}
174
175static inline void spi_enable_chip(struct dw_spi *dws, int enable) 153static inline void spi_enable_chip(struct dw_spi *dws, int enable)
176{ 154{
177 dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0)); 155 dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0));
@@ -182,22 +160,6 @@ static inline void spi_set_clk(struct dw_spi *dws, u16 div)
182 dw_writel(dws, DW_SPI_BAUDR, div); 160 dw_writel(dws, DW_SPI_BAUDR, div);
183} 161}
184 162
185static inline void spi_chip_sel(struct dw_spi *dws, struct spi_device *spi,
186 int active)
187{
188 u16 cs = spi->chip_select;
189 int gpio_val = active ? (spi->mode & SPI_CS_HIGH) :
190 !(spi->mode & SPI_CS_HIGH);
191
192 if (dws->cs_control)
193 dws->cs_control(active);
194 if (gpio_is_valid(spi->cs_gpio))
195 gpio_set_value(spi->cs_gpio, gpio_val);
196
197 if (active)
198 dw_writel(dws, DW_SPI_SER, 1 << cs);
199}
200
201/* Disable IRQ bits */ 163/* Disable IRQ bits */
202static inline void spi_mask_intr(struct dw_spi *dws, u32 mask) 164static inline void spi_mask_intr(struct dw_spi *dws, u32 mask)
203{ 165{
@@ -217,15 +179,26 @@ static inline void spi_umask_intr(struct dw_spi *dws, u32 mask)
217} 179}
218 180
219/* 181/*
182 * This does disable the SPI controller, interrupts, and re-enable the
183 * controller back. Transmit and receive FIFO buffers are cleared when the
184 * device is disabled.
185 */
186static inline void spi_reset_chip(struct dw_spi *dws)
187{
188 spi_enable_chip(dws, 0);
189 spi_mask_intr(dws, 0xff);
190 spi_enable_chip(dws, 1);
191}
192
193/*
220 * Each SPI slave device to work with dw_api controller should 194 * Each SPI slave device to work with dw_api controller should
221 * has such a structure claiming its working mode (PIO/DMA etc), 195 * has such a structure claiming its working mode (poll or PIO/DMA),
222 * which can be save in the "controller_data" member of the 196 * which can be save in the "controller_data" member of the
223 * struct spi_device. 197 * struct spi_device.
224 */ 198 */
225struct dw_spi_chip { 199struct dw_spi_chip {
226 u8 poll_mode; /* 1 for controller polling mode */ 200 u8 poll_mode; /* 1 for controller polling mode */
227 u8 type; /* SPI/SSP/MicroWire */ 201 u8 type; /* SPI/SSP/MicroWire */
228 u8 enable_dma;
229 void (*cs_control)(u32 command); 202 void (*cs_control)(u32 command);
230}; 203};
231 204
@@ -233,7 +206,6 @@ extern int dw_spi_add_host(struct device *dev, struct dw_spi *dws);
233extern void dw_spi_remove_host(struct dw_spi *dws); 206extern void dw_spi_remove_host(struct dw_spi *dws);
234extern int dw_spi_suspend_host(struct dw_spi *dws); 207extern int dw_spi_suspend_host(struct dw_spi *dws);
235extern int dw_spi_resume_host(struct dw_spi *dws); 208extern int dw_spi_resume_host(struct dw_spi *dws);
236extern void dw_spi_xfer_done(struct dw_spi *dws);
237 209
238/* platform related setup */ 210/* platform related setup */
239extern int dw_spi_mid_init(struct dw_spi *dws); /* Intel MID platforms */ 211extern int dw_spi_mid_init(struct dw_spi *dws); /* Intel MID platforms */
diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c
index d1a39249704a..5fe54cda309f 100644
--- a/drivers/spi/spi-fsl-dspi.c
+++ b/drivers/spi/spi-fsl-dspi.c
@@ -20,6 +20,7 @@
20#include <linux/interrupt.h> 20#include <linux/interrupt.h>
21#include <linux/io.h> 21#include <linux/io.h>
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/math64.h>
23#include <linux/module.h> 24#include <linux/module.h>
24#include <linux/of.h> 25#include <linux/of.h>
25#include <linux/of_device.h> 26#include <linux/of_device.h>
@@ -29,6 +30,7 @@
29#include <linux/sched.h> 30#include <linux/sched.h>
30#include <linux/spi/spi.h> 31#include <linux/spi/spi.h>
31#include <linux/spi/spi_bitbang.h> 32#include <linux/spi/spi_bitbang.h>
33#include <linux/time.h>
32 34
33#define DRIVER_NAME "fsl-dspi" 35#define DRIVER_NAME "fsl-dspi"
34 36
@@ -51,7 +53,7 @@
51#define SPI_CTAR_CPOL(x) ((x) << 26) 53#define SPI_CTAR_CPOL(x) ((x) << 26)
52#define SPI_CTAR_CPHA(x) ((x) << 25) 54#define SPI_CTAR_CPHA(x) ((x) << 25)
53#define SPI_CTAR_LSBFE(x) ((x) << 24) 55#define SPI_CTAR_LSBFE(x) ((x) << 24)
54#define SPI_CTAR_PCSSCR(x) (((x) & 0x00000003) << 22) 56#define SPI_CTAR_PCSSCK(x) (((x) & 0x00000003) << 22)
55#define SPI_CTAR_PASC(x) (((x) & 0x00000003) << 20) 57#define SPI_CTAR_PASC(x) (((x) & 0x00000003) << 20)
56#define SPI_CTAR_PDT(x) (((x) & 0x00000003) << 18) 58#define SPI_CTAR_PDT(x) (((x) & 0x00000003) << 18)
57#define SPI_CTAR_PBR(x) (((x) & 0x00000003) << 16) 59#define SPI_CTAR_PBR(x) (((x) & 0x00000003) << 16)
@@ -59,6 +61,7 @@
59#define SPI_CTAR_ASC(x) (((x) & 0x0000000f) << 8) 61#define SPI_CTAR_ASC(x) (((x) & 0x0000000f) << 8)
60#define SPI_CTAR_DT(x) (((x) & 0x0000000f) << 4) 62#define SPI_CTAR_DT(x) (((x) & 0x0000000f) << 4)
61#define SPI_CTAR_BR(x) ((x) & 0x0000000f) 63#define SPI_CTAR_BR(x) ((x) & 0x0000000f)
64#define SPI_CTAR_SCALE_BITS 0xf
62 65
63#define SPI_CTAR0_SLAVE 0x0c 66#define SPI_CTAR0_SLAVE 0x0c
64 67
@@ -148,23 +151,66 @@ static void hz_to_spi_baud(char *pbr, char *br, int speed_hz,
148 16, 32, 64, 128, 151 16, 32, 64, 128,
149 256, 512, 1024, 2048, 152 256, 512, 1024, 2048,
150 4096, 8192, 16384, 32768 }; 153 4096, 8192, 16384, 32768 };
151 int temp, i = 0, j = 0; 154 int scale_needed, scale, minscale = INT_MAX;
155 int i, j;
156
157 scale_needed = clkrate / speed_hz;
158 if (clkrate % speed_hz)
159 scale_needed++;
160
161 for (i = 0; i < ARRAY_SIZE(brs); i++)
162 for (j = 0; j < ARRAY_SIZE(pbr_tbl); j++) {
163 scale = brs[i] * pbr_tbl[j];
164 if (scale >= scale_needed) {
165 if (scale < minscale) {
166 minscale = scale;
167 *br = i;
168 *pbr = j;
169 }
170 break;
171 }
172 }
152 173
153 temp = clkrate / 2 / speed_hz; 174 if (minscale == INT_MAX) {
175 pr_warn("Can not find valid baud rate,speed_hz is %d,clkrate is %ld, we use the max prescaler value.\n",
176 speed_hz, clkrate);
177 *pbr = ARRAY_SIZE(pbr_tbl) - 1;
178 *br = ARRAY_SIZE(brs) - 1;
179 }
180}
154 181
155 for (i = 0; i < ARRAY_SIZE(pbr_tbl); i++) 182static void ns_delay_scale(char *psc, char *sc, int delay_ns,
156 for (j = 0; j < ARRAY_SIZE(brs); j++) { 183 unsigned long clkrate)
157 if (pbr_tbl[i] * brs[j] >= temp) { 184{
158 *pbr = i; 185 int pscale_tbl[4] = {1, 3, 5, 7};
159 *br = j; 186 int scale_needed, scale, minscale = INT_MAX;
160 return; 187 int i, j;
188 u32 remainder;
189
190 scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC,
191 &remainder);
192 if (remainder)
193 scale_needed++;
194
195 for (i = 0; i < ARRAY_SIZE(pscale_tbl); i++)
196 for (j = 0; j <= SPI_CTAR_SCALE_BITS; j++) {
197 scale = pscale_tbl[i] * (2 << j);
198 if (scale >= scale_needed) {
199 if (scale < minscale) {
200 minscale = scale;
201 *psc = i;
202 *sc = j;
203 }
204 break;
161 } 205 }
162 } 206 }
163 207
164 pr_warn("Can not find valid baud rate,speed_hz is %d,clkrate is %ld\ 208 if (minscale == INT_MAX) {
165 ,we use the max prescaler value.\n", speed_hz, clkrate); 209 pr_warn("Cannot find correct scale values for %dns delay at clkrate %ld, using max prescaler value",
166 *pbr = ARRAY_SIZE(pbr_tbl) - 1; 210 delay_ns, clkrate);
167 *br = ARRAY_SIZE(brs) - 1; 211 *psc = ARRAY_SIZE(pscale_tbl) - 1;
212 *sc = SPI_CTAR_SCALE_BITS;
213 }
168} 214}
169 215
170static int dspi_transfer_write(struct fsl_dspi *dspi) 216static int dspi_transfer_write(struct fsl_dspi *dspi)
@@ -345,7 +391,10 @@ static int dspi_setup(struct spi_device *spi)
345{ 391{
346 struct chip_data *chip; 392 struct chip_data *chip;
347 struct fsl_dspi *dspi = spi_master_get_devdata(spi->master); 393 struct fsl_dspi *dspi = spi_master_get_devdata(spi->master);
348 unsigned char br = 0, pbr = 0, fmsz = 0; 394 u32 cs_sck_delay = 0, sck_cs_delay = 0;
395 unsigned char br = 0, pbr = 0, pcssck = 0, cssck = 0;
396 unsigned char pasc = 0, asc = 0, fmsz = 0;
397 unsigned long clkrate;
349 398
350 if ((spi->bits_per_word >= 4) && (spi->bits_per_word <= 16)) { 399 if ((spi->bits_per_word >= 4) && (spi->bits_per_word <= 16)) {
351 fmsz = spi->bits_per_word - 1; 400 fmsz = spi->bits_per_word - 1;
@@ -362,18 +411,34 @@ static int dspi_setup(struct spi_device *spi)
362 return -ENOMEM; 411 return -ENOMEM;
363 } 412 }
364 413
414 of_property_read_u32(spi->dev.of_node, "fsl,spi-cs-sck-delay",
415 &cs_sck_delay);
416
417 of_property_read_u32(spi->dev.of_node, "fsl,spi-sck-cs-delay",
418 &sck_cs_delay);
419
365 chip->mcr_val = SPI_MCR_MASTER | SPI_MCR_PCSIS | 420 chip->mcr_val = SPI_MCR_MASTER | SPI_MCR_PCSIS |
366 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF; 421 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF;
367 422
368 chip->void_write_data = 0; 423 chip->void_write_data = 0;
369 424
370 hz_to_spi_baud(&pbr, &br, 425 clkrate = clk_get_rate(dspi->clk);
371 spi->max_speed_hz, clk_get_rate(dspi->clk)); 426 hz_to_spi_baud(&pbr, &br, spi->max_speed_hz, clkrate);
427
428 /* Set PCS to SCK delay scale values */
429 ns_delay_scale(&pcssck, &cssck, cs_sck_delay, clkrate);
430
431 /* Set After SCK delay scale values */
432 ns_delay_scale(&pasc, &asc, sck_cs_delay, clkrate);
372 433
373 chip->ctar_val = SPI_CTAR_FMSZ(fmsz) 434 chip->ctar_val = SPI_CTAR_FMSZ(fmsz)
374 | SPI_CTAR_CPOL(spi->mode & SPI_CPOL ? 1 : 0) 435 | SPI_CTAR_CPOL(spi->mode & SPI_CPOL ? 1 : 0)
375 | SPI_CTAR_CPHA(spi->mode & SPI_CPHA ? 1 : 0) 436 | SPI_CTAR_CPHA(spi->mode & SPI_CPHA ? 1 : 0)
376 | SPI_CTAR_LSBFE(spi->mode & SPI_LSB_FIRST ? 1 : 0) 437 | SPI_CTAR_LSBFE(spi->mode & SPI_LSB_FIRST ? 1 : 0)
438 | SPI_CTAR_PCSSCK(pcssck)
439 | SPI_CTAR_CSSCK(cssck)
440 | SPI_CTAR_PASC(pasc)
441 | SPI_CTAR_ASC(asc)
377 | SPI_CTAR_PBR(pbr) 442 | SPI_CTAR_PBR(pbr)
378 | SPI_CTAR_BR(br); 443 | SPI_CTAR_BR(br);
379 444
diff --git a/drivers/spi/spi-img-spfi.c b/drivers/spi/spi-img-spfi.c
index c01567d53581..788e2b176a4f 100644
--- a/drivers/spi/spi-img-spfi.c
+++ b/drivers/spi/spi-img-spfi.c
@@ -12,6 +12,7 @@
12#include <linux/clk.h> 12#include <linux/clk.h>
13#include <linux/delay.h> 13#include <linux/delay.h>
14#include <linux/dmaengine.h> 14#include <linux/dmaengine.h>
15#include <linux/gpio.h>
15#include <linux/interrupt.h> 16#include <linux/interrupt.h>
16#include <linux/io.h> 17#include <linux/io.h>
17#include <linux/irq.h> 18#include <linux/irq.h>
@@ -122,36 +123,31 @@ static inline void spfi_start(struct img_spfi *spfi)
122 spfi_writel(spfi, val, SPFI_CONTROL); 123 spfi_writel(spfi, val, SPFI_CONTROL);
123} 124}
124 125
125static inline void spfi_stop(struct img_spfi *spfi)
126{
127 u32 val;
128
129 val = spfi_readl(spfi, SPFI_CONTROL);
130 val &= ~SPFI_CONTROL_SPFI_EN;
131 spfi_writel(spfi, val, SPFI_CONTROL);
132}
133
134static inline void spfi_reset(struct img_spfi *spfi) 126static inline void spfi_reset(struct img_spfi *spfi)
135{ 127{
136 spfi_writel(spfi, SPFI_CONTROL_SOFT_RESET, SPFI_CONTROL); 128 spfi_writel(spfi, SPFI_CONTROL_SOFT_RESET, SPFI_CONTROL);
137 udelay(1);
138 spfi_writel(spfi, 0, SPFI_CONTROL); 129 spfi_writel(spfi, 0, SPFI_CONTROL);
139} 130}
140 131
141static void spfi_flush_tx_fifo(struct img_spfi *spfi) 132static int spfi_wait_all_done(struct img_spfi *spfi)
142{ 133{
143 unsigned long timeout = jiffies + msecs_to_jiffies(10); 134 unsigned long timeout = jiffies + msecs_to_jiffies(50);
144 135
145 spfi_writel(spfi, SPFI_INTERRUPT_SDE, SPFI_INTERRUPT_CLEAR);
146 while (time_before(jiffies, timeout)) { 136 while (time_before(jiffies, timeout)) {
147 if (spfi_readl(spfi, SPFI_INTERRUPT_STATUS) & 137 u32 status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS);
148 SPFI_INTERRUPT_SDE) 138
149 return; 139 if (status & SPFI_INTERRUPT_ALLDONETRIG) {
140 spfi_writel(spfi, SPFI_INTERRUPT_ALLDONETRIG,
141 SPFI_INTERRUPT_CLEAR);
142 return 0;
143 }
150 cpu_relax(); 144 cpu_relax();
151 } 145 }
152 146
153 dev_err(spfi->dev, "Timed out waiting for FIFO to drain\n"); 147 dev_err(spfi->dev, "Timed out waiting for transaction to complete\n");
154 spfi_reset(spfi); 148 spfi_reset(spfi);
149
150 return -ETIMEDOUT;
155} 151}
156 152
157static unsigned int spfi_pio_write32(struct img_spfi *spfi, const u32 *buf, 153static unsigned int spfi_pio_write32(struct img_spfi *spfi, const u32 *buf,
@@ -237,6 +233,7 @@ static int img_spfi_start_pio(struct spi_master *master,
237 const void *tx_buf = xfer->tx_buf; 233 const void *tx_buf = xfer->tx_buf;
238 void *rx_buf = xfer->rx_buf; 234 void *rx_buf = xfer->rx_buf;
239 unsigned long timeout; 235 unsigned long timeout;
236 int ret;
240 237
241 if (tx_buf) 238 if (tx_buf)
242 tx_bytes = xfer->len; 239 tx_bytes = xfer->len;
@@ -269,16 +266,15 @@ static int img_spfi_start_pio(struct spi_master *master,
269 cpu_relax(); 266 cpu_relax();
270 } 267 }
271 268
269 ret = spfi_wait_all_done(spfi);
270 if (ret < 0)
271 return ret;
272
272 if (rx_bytes > 0 || tx_bytes > 0) { 273 if (rx_bytes > 0 || tx_bytes > 0) {
273 dev_err(spfi->dev, "PIO transfer timed out\n"); 274 dev_err(spfi->dev, "PIO transfer timed out\n");
274 spfi_reset(spfi);
275 return -ETIMEDOUT; 275 return -ETIMEDOUT;
276 } 276 }
277 277
278 if (tx_buf)
279 spfi_flush_tx_fifo(spfi);
280 spfi_stop(spfi);
281
282 return 0; 278 return 0;
283} 279}
284 280
@@ -287,14 +283,12 @@ static void img_spfi_dma_rx_cb(void *data)
287 struct img_spfi *spfi = data; 283 struct img_spfi *spfi = data;
288 unsigned long flags; 284 unsigned long flags;
289 285
290 spin_lock_irqsave(&spfi->lock, flags); 286 spfi_wait_all_done(spfi);
291 287
288 spin_lock_irqsave(&spfi->lock, flags);
292 spfi->rx_dma_busy = false; 289 spfi->rx_dma_busy = false;
293 if (!spfi->tx_dma_busy) { 290 if (!spfi->tx_dma_busy)
294 spfi_stop(spfi);
295 spi_finalize_current_transfer(spfi->master); 291 spi_finalize_current_transfer(spfi->master);
296 }
297
298 spin_unlock_irqrestore(&spfi->lock, flags); 292 spin_unlock_irqrestore(&spfi->lock, flags);
299} 293}
300 294
@@ -303,16 +297,12 @@ static void img_spfi_dma_tx_cb(void *data)
303 struct img_spfi *spfi = data; 297 struct img_spfi *spfi = data;
304 unsigned long flags; 298 unsigned long flags;
305 299
306 spfi_flush_tx_fifo(spfi); 300 spfi_wait_all_done(spfi);
307 301
308 spin_lock_irqsave(&spfi->lock, flags); 302 spin_lock_irqsave(&spfi->lock, flags);
309
310 spfi->tx_dma_busy = false; 303 spfi->tx_dma_busy = false;
311 if (!spfi->rx_dma_busy) { 304 if (!spfi->rx_dma_busy)
312 spfi_stop(spfi);
313 spi_finalize_current_transfer(spfi->master); 305 spi_finalize_current_transfer(spfi->master);
314 }
315
316 spin_unlock_irqrestore(&spfi->lock, flags); 306 spin_unlock_irqrestore(&spfi->lock, flags);
317} 307}
318 308
@@ -397,6 +387,75 @@ stop_dma:
397 return -EIO; 387 return -EIO;
398} 388}
399 389
390static void img_spfi_handle_err(struct spi_master *master,
391 struct spi_message *msg)
392{
393 struct img_spfi *spfi = spi_master_get_devdata(master);
394 unsigned long flags;
395
396 /*
397 * Stop all DMA and reset the controller if the previous transaction
398 * timed-out and never completed it's DMA.
399 */
400 spin_lock_irqsave(&spfi->lock, flags);
401 if (spfi->tx_dma_busy || spfi->rx_dma_busy) {
402 spfi->tx_dma_busy = false;
403 spfi->rx_dma_busy = false;
404
405 dmaengine_terminate_all(spfi->tx_ch);
406 dmaengine_terminate_all(spfi->rx_ch);
407 }
408 spin_unlock_irqrestore(&spfi->lock, flags);
409}
410
411static int img_spfi_prepare(struct spi_master *master, struct spi_message *msg)
412{
413 struct img_spfi *spfi = spi_master_get_devdata(master);
414 u32 val;
415
416 val = spfi_readl(spfi, SPFI_PORT_STATE);
417 if (msg->spi->mode & SPI_CPHA)
418 val |= SPFI_PORT_STATE_CK_PHASE(msg->spi->chip_select);
419 else
420 val &= ~SPFI_PORT_STATE_CK_PHASE(msg->spi->chip_select);
421 if (msg->spi->mode & SPI_CPOL)
422 val |= SPFI_PORT_STATE_CK_POL(msg->spi->chip_select);
423 else
424 val &= ~SPFI_PORT_STATE_CK_POL(msg->spi->chip_select);
425 spfi_writel(spfi, val, SPFI_PORT_STATE);
426
427 return 0;
428}
429
430static int img_spfi_unprepare(struct spi_master *master,
431 struct spi_message *msg)
432{
433 struct img_spfi *spfi = spi_master_get_devdata(master);
434
435 spfi_reset(spfi);
436
437 return 0;
438}
439
440static int img_spfi_setup(struct spi_device *spi)
441{
442 int ret;
443
444 ret = gpio_request_one(spi->cs_gpio, (spi->mode & SPI_CS_HIGH) ?
445 GPIOF_OUT_INIT_LOW : GPIOF_OUT_INIT_HIGH,
446 dev_name(&spi->dev));
447 if (ret)
448 dev_err(&spi->dev, "can't request chipselect gpio %d\n",
449 spi->cs_gpio);
450
451 return ret;
452}
453
454static void img_spfi_cleanup(struct spi_device *spi)
455{
456 gpio_free(spi->cs_gpio);
457}
458
400static void img_spfi_config(struct spi_master *master, struct spi_device *spi, 459static void img_spfi_config(struct spi_master *master, struct spi_device *spi,
401 struct spi_transfer *xfer) 460 struct spi_transfer *xfer)
402{ 461{
@@ -405,10 +464,10 @@ static void img_spfi_config(struct spi_master *master, struct spi_device *spi,
405 464
406 /* 465 /*
407 * output = spfi_clk * (BITCLK / 512), where BITCLK must be a 466 * output = spfi_clk * (BITCLK / 512), where BITCLK must be a
408 * power of 2 up to 256 (where 255 == 256 since BITCLK is 8 bits) 467 * power of 2 up to 128
409 */ 468 */
410 div = DIV_ROUND_UP(master->max_speed_hz, xfer->speed_hz); 469 div = DIV_ROUND_UP(clk_get_rate(spfi->spfi_clk), xfer->speed_hz);
411 div = clamp(512 / (1 << get_count_order(div)), 1, 255); 470 div = clamp(512 / (1 << get_count_order(div)), 1, 128);
412 471
413 val = spfi_readl(spfi, SPFI_DEVICE_PARAMETER(spi->chip_select)); 472 val = spfi_readl(spfi, SPFI_DEVICE_PARAMETER(spi->chip_select));
414 val &= ~(SPFI_DEVICE_PARAMETER_BITCLK_MASK << 473 val &= ~(SPFI_DEVICE_PARAMETER_BITCLK_MASK <<
@@ -416,6 +475,9 @@ static void img_spfi_config(struct spi_master *master, struct spi_device *spi,
416 val |= div << SPFI_DEVICE_PARAMETER_BITCLK_SHIFT; 475 val |= div << SPFI_DEVICE_PARAMETER_BITCLK_SHIFT;
417 spfi_writel(spfi, val, SPFI_DEVICE_PARAMETER(spi->chip_select)); 476 spfi_writel(spfi, val, SPFI_DEVICE_PARAMETER(spi->chip_select));
418 477
478 spfi_writel(spfi, xfer->len << SPFI_TRANSACTION_TSIZE_SHIFT,
479 SPFI_TRANSACTION);
480
419 val = spfi_readl(spfi, SPFI_CONTROL); 481 val = spfi_readl(spfi, SPFI_CONTROL);
420 val &= ~(SPFI_CONTROL_SEND_DMA | SPFI_CONTROL_GET_DMA); 482 val &= ~(SPFI_CONTROL_SEND_DMA | SPFI_CONTROL_GET_DMA);
421 if (xfer->tx_buf) 483 if (xfer->tx_buf)
@@ -429,25 +491,7 @@ static void img_spfi_config(struct spi_master *master, struct spi_device *spi,
429 else if (xfer->tx_nbits == SPI_NBITS_QUAD && 491 else if (xfer->tx_nbits == SPI_NBITS_QUAD &&
430 xfer->rx_nbits == SPI_NBITS_QUAD) 492 xfer->rx_nbits == SPI_NBITS_QUAD)
431 val |= SPFI_CONTROL_TMODE_QUAD << SPFI_CONTROL_TMODE_SHIFT; 493 val |= SPFI_CONTROL_TMODE_QUAD << SPFI_CONTROL_TMODE_SHIFT;
432 val &= ~SPFI_CONTROL_CONTINUE;
433 if (!xfer->cs_change && !list_is_last(&xfer->transfer_list,
434 &master->cur_msg->transfers))
435 val |= SPFI_CONTROL_CONTINUE;
436 spfi_writel(spfi, val, SPFI_CONTROL); 494 spfi_writel(spfi, val, SPFI_CONTROL);
437
438 val = spfi_readl(spfi, SPFI_PORT_STATE);
439 if (spi->mode & SPI_CPHA)
440 val |= SPFI_PORT_STATE_CK_PHASE(spi->chip_select);
441 else
442 val &= ~SPFI_PORT_STATE_CK_PHASE(spi->chip_select);
443 if (spi->mode & SPI_CPOL)
444 val |= SPFI_PORT_STATE_CK_POL(spi->chip_select);
445 else
446 val &= ~SPFI_PORT_STATE_CK_POL(spi->chip_select);
447 spfi_writel(spfi, val, SPFI_PORT_STATE);
448
449 spfi_writel(spfi, xfer->len << SPFI_TRANSACTION_TSIZE_SHIFT,
450 SPFI_TRANSACTION);
451} 495}
452 496
453static int img_spfi_transfer_one(struct spi_master *master, 497static int img_spfi_transfer_one(struct spi_master *master,
@@ -455,25 +499,13 @@ static int img_spfi_transfer_one(struct spi_master *master,
455 struct spi_transfer *xfer) 499 struct spi_transfer *xfer)
456{ 500{
457 struct img_spfi *spfi = spi_master_get_devdata(spi->master); 501 struct img_spfi *spfi = spi_master_get_devdata(spi->master);
458 bool dma_reset = false;
459 unsigned long flags;
460 int ret; 502 int ret;
461 503
462 /* 504 if (xfer->len > SPFI_TRANSACTION_TSIZE_MASK) {
463 * Stop all DMA and reset the controller if the previous transaction 505 dev_err(spfi->dev,
464 * timed-out and never completed it's DMA. 506 "Transfer length (%d) is greater than the max supported (%d)",
465 */ 507 xfer->len, SPFI_TRANSACTION_TSIZE_MASK);
466 spin_lock_irqsave(&spfi->lock, flags); 508 return -EINVAL;
467 if (spfi->tx_dma_busy || spfi->rx_dma_busy) {
468 dev_err(spfi->dev, "SPI DMA still busy\n");
469 dma_reset = true;
470 }
471 spin_unlock_irqrestore(&spfi->lock, flags);
472
473 if (dma_reset) {
474 dmaengine_terminate_all(spfi->tx_ch);
475 dmaengine_terminate_all(spfi->rx_ch);
476 spfi_reset(spfi);
477 } 509 }
478 510
479 img_spfi_config(master, spi, xfer); 511 img_spfi_config(master, spi, xfer);
@@ -485,17 +517,6 @@ static int img_spfi_transfer_one(struct spi_master *master,
485 return ret; 517 return ret;
486} 518}
487 519
488static void img_spfi_set_cs(struct spi_device *spi, bool enable)
489{
490 struct img_spfi *spfi = spi_master_get_devdata(spi->master);
491 u32 val;
492
493 val = spfi_readl(spfi, SPFI_PORT_STATE);
494 val &= ~(SPFI_PORT_STATE_DEV_SEL_MASK << SPFI_PORT_STATE_DEV_SEL_SHIFT);
495 val |= spi->chip_select << SPFI_PORT_STATE_DEV_SEL_SHIFT;
496 spfi_writel(spfi, val, SPFI_PORT_STATE);
497}
498
499static bool img_spfi_can_dma(struct spi_master *master, struct spi_device *spi, 520static bool img_spfi_can_dma(struct spi_master *master, struct spi_device *spi,
500 struct spi_transfer *xfer) 521 struct spi_transfer *xfer)
501{ 522{
@@ -584,14 +605,17 @@ static int img_spfi_probe(struct platform_device *pdev)
584 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_TX_DUAL | SPI_RX_DUAL; 605 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_TX_DUAL | SPI_RX_DUAL;
585 if (of_property_read_bool(spfi->dev->of_node, "img,supports-quad-mode")) 606 if (of_property_read_bool(spfi->dev->of_node, "img,supports-quad-mode"))
586 master->mode_bits |= SPI_TX_QUAD | SPI_RX_QUAD; 607 master->mode_bits |= SPI_TX_QUAD | SPI_RX_QUAD;
587 master->num_chipselect = 5;
588 master->dev.of_node = pdev->dev.of_node; 608 master->dev.of_node = pdev->dev.of_node;
589 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(8); 609 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(8);
590 master->max_speed_hz = clk_get_rate(spfi->spfi_clk); 610 master->max_speed_hz = clk_get_rate(spfi->spfi_clk) / 4;
591 master->min_speed_hz = master->max_speed_hz / 512; 611 master->min_speed_hz = clk_get_rate(spfi->spfi_clk) / 512;
592 612
593 master->set_cs = img_spfi_set_cs; 613 master->setup = img_spfi_setup;
614 master->cleanup = img_spfi_cleanup;
594 master->transfer_one = img_spfi_transfer_one; 615 master->transfer_one = img_spfi_transfer_one;
616 master->prepare_message = img_spfi_prepare;
617 master->unprepare_message = img_spfi_unprepare;
618 master->handle_err = img_spfi_handle_err;
595 619
596 spfi->tx_ch = dma_request_slave_channel(spfi->dev, "tx"); 620 spfi->tx_ch = dma_request_slave_channel(spfi->dev, "tx");
597 spfi->rx_ch = dma_request_slave_channel(spfi->dev, "rx"); 621 spfi->rx_ch = dma_request_slave_channel(spfi->dev, "rx");
diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
index 6fea4af51c41..f08e812b2984 100644
--- a/drivers/spi/spi-imx.c
+++ b/drivers/spi/spi-imx.c
@@ -370,8 +370,6 @@ static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx,
370 if (spi_imx->dma_is_inited) { 370 if (spi_imx->dma_is_inited) {
371 dma = readl(spi_imx->base + MX51_ECSPI_DMA); 371 dma = readl(spi_imx->base + MX51_ECSPI_DMA);
372 372
373 spi_imx->tx_wml = spi_imx_get_fifosize(spi_imx) / 2;
374 spi_imx->rx_wml = spi_imx_get_fifosize(spi_imx) / 2;
375 spi_imx->rxt_wml = spi_imx_get_fifosize(spi_imx) / 2; 373 spi_imx->rxt_wml = spi_imx_get_fifosize(spi_imx) / 2;
376 rx_wml_cfg = spi_imx->rx_wml << MX51_ECSPI_DMA_RX_WML_OFFSET; 374 rx_wml_cfg = spi_imx->rx_wml << MX51_ECSPI_DMA_RX_WML_OFFSET;
377 tx_wml_cfg = spi_imx->tx_wml << MX51_ECSPI_DMA_TX_WML_OFFSET; 375 tx_wml_cfg = spi_imx->tx_wml << MX51_ECSPI_DMA_TX_WML_OFFSET;
@@ -868,6 +866,8 @@ static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx,
868 master->max_dma_len = MAX_SDMA_BD_BYTES; 866 master->max_dma_len = MAX_SDMA_BD_BYTES;
869 spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX | 867 spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX |
870 SPI_MASTER_MUST_TX; 868 SPI_MASTER_MUST_TX;
869 spi_imx->tx_wml = spi_imx_get_fifosize(spi_imx) / 2;
870 spi_imx->rx_wml = spi_imx_get_fifosize(spi_imx) / 2;
871 spi_imx->dma_is_inited = 1; 871 spi_imx->dma_is_inited = 1;
872 872
873 return 0; 873 return 0;
@@ -903,7 +903,7 @@ static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx,
903 903
904 if (tx) { 904 if (tx) {
905 desc_tx = dmaengine_prep_slave_sg(master->dma_tx, 905 desc_tx = dmaengine_prep_slave_sg(master->dma_tx,
906 tx->sgl, tx->nents, DMA_TO_DEVICE, 906 tx->sgl, tx->nents, DMA_MEM_TO_DEV,
907 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 907 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
908 if (!desc_tx) 908 if (!desc_tx)
909 goto no_dma; 909 goto no_dma;
@@ -915,7 +915,7 @@ static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx,
915 915
916 if (rx) { 916 if (rx) {
917 desc_rx = dmaengine_prep_slave_sg(master->dma_rx, 917 desc_rx = dmaengine_prep_slave_sg(master->dma_rx,
918 rx->sgl, rx->nents, DMA_FROM_DEVICE, 918 rx->sgl, rx->nents, DMA_DEV_TO_MEM,
919 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 919 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
920 if (!desc_rx) 920 if (!desc_rx)
921 goto no_dma; 921 goto no_dma;
diff --git a/drivers/spi/spi-mpc512x-psc.c b/drivers/spi/spi-mpc512x-psc.c
index ecae0d4e2945..965d2bdcfdcc 100644
--- a/drivers/spi/spi-mpc512x-psc.c
+++ b/drivers/spi/spi-mpc512x-psc.c
@@ -588,7 +588,7 @@ static int mpc512x_psc_spi_of_remove(struct platform_device *op)
588 return mpc512x_psc_spi_do_remove(&op->dev); 588 return mpc512x_psc_spi_do_remove(&op->dev);
589} 589}
590 590
591static struct of_device_id mpc512x_psc_spi_of_match[] = { 591static const struct of_device_id mpc512x_psc_spi_of_match[] = {
592 { .compatible = "fsl,mpc5121-psc-spi", }, 592 { .compatible = "fsl,mpc5121-psc-spi", },
593 {}, 593 {},
594}; 594};
diff --git a/drivers/spi/spi-octeon.c b/drivers/spi/spi-octeon.c
index b283d537d16a..e99d6a93d394 100644
--- a/drivers/spi/spi-octeon.c
+++ b/drivers/spi/spi-octeon.c
@@ -238,7 +238,7 @@ static int octeon_spi_remove(struct platform_device *pdev)
238 return 0; 238 return 0;
239} 239}
240 240
241static struct of_device_id octeon_spi_match[] = { 241static const struct of_device_id octeon_spi_match[] = {
242 { .compatible = "cavium,octeon-3010-spi", }, 242 { .compatible = "cavium,octeon-3010-spi", },
243 {}, 243 {},
244}; 244};
diff --git a/drivers/spi/spi-omap-100k.c b/drivers/spi/spi-omap-100k.c
index d890d309dff9..35b332dacb13 100644
--- a/drivers/spi/spi-omap-100k.c
+++ b/drivers/spi/spi-omap-100k.c
@@ -24,6 +24,7 @@
24#include <linux/device.h> 24#include <linux/device.h>
25#include <linux/delay.h> 25#include <linux/delay.h>
26#include <linux/platform_device.h> 26#include <linux/platform_device.h>
27#include <linux/pm_runtime.h>
27#include <linux/err.h> 28#include <linux/err.h>
28#include <linux/clk.h> 29#include <linux/clk.h>
29#include <linux/io.h> 30#include <linux/io.h>
@@ -294,16 +295,6 @@ static int omap1_spi100k_setup(struct spi_device *spi)
294 return ret; 295 return ret;
295} 296}
296 297
297static int omap1_spi100k_prepare_hardware(struct spi_master *master)
298{
299 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
300
301 clk_prepare_enable(spi100k->ick);
302 clk_prepare_enable(spi100k->fck);
303
304 return 0;
305}
306
307static int omap1_spi100k_transfer_one_message(struct spi_master *master, 298static int omap1_spi100k_transfer_one_message(struct spi_master *master,
308 struct spi_message *m) 299 struct spi_message *m)
309{ 300{
@@ -372,16 +363,6 @@ static int omap1_spi100k_transfer_one_message(struct spi_master *master,
372 return status; 363 return status;
373} 364}
374 365
375static int omap1_spi100k_unprepare_hardware(struct spi_master *master)
376{
377 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
378
379 clk_disable_unprepare(spi100k->ick);
380 clk_disable_unprepare(spi100k->fck);
381
382 return 0;
383}
384
385static int omap1_spi100k_probe(struct platform_device *pdev) 366static int omap1_spi100k_probe(struct platform_device *pdev)
386{ 367{
387 struct spi_master *master; 368 struct spi_master *master;
@@ -402,14 +383,12 @@ static int omap1_spi100k_probe(struct platform_device *pdev)
402 383
403 master->setup = omap1_spi100k_setup; 384 master->setup = omap1_spi100k_setup;
404 master->transfer_one_message = omap1_spi100k_transfer_one_message; 385 master->transfer_one_message = omap1_spi100k_transfer_one_message;
405 master->prepare_transfer_hardware = omap1_spi100k_prepare_hardware;
406 master->unprepare_transfer_hardware = omap1_spi100k_unprepare_hardware;
407 master->cleanup = NULL;
408 master->num_chipselect = 2; 386 master->num_chipselect = 2;
409 master->mode_bits = MODEBITS; 387 master->mode_bits = MODEBITS;
410 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); 388 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
411 master->min_speed_hz = OMAP1_SPI100K_MAX_FREQ/(1<<16); 389 master->min_speed_hz = OMAP1_SPI100K_MAX_FREQ/(1<<16);
412 master->max_speed_hz = OMAP1_SPI100K_MAX_FREQ; 390 master->max_speed_hz = OMAP1_SPI100K_MAX_FREQ;
391 master->auto_runtime_pm = true;
413 392
414 spi100k = spi_master_get_devdata(master); 393 spi100k = spi_master_get_devdata(master);
415 394
@@ -434,22 +413,96 @@ static int omap1_spi100k_probe(struct platform_device *pdev)
434 goto err; 413 goto err;
435 } 414 }
436 415
416 status = clk_prepare_enable(spi100k->ick);
417 if (status != 0) {
418 dev_err(&pdev->dev, "failed to enable ick: %d\n", status);
419 goto err;
420 }
421
422 status = clk_prepare_enable(spi100k->fck);
423 if (status != 0) {
424 dev_err(&pdev->dev, "failed to enable fck: %d\n", status);
425 goto err_ick;
426 }
427
428 pm_runtime_enable(&pdev->dev);
429 pm_runtime_set_active(&pdev->dev);
430
437 status = devm_spi_register_master(&pdev->dev, master); 431 status = devm_spi_register_master(&pdev->dev, master);
438 if (status < 0) 432 if (status < 0)
439 goto err; 433 goto err_fck;
440 434
441 return status; 435 return status;
442 436
437err_fck:
438 clk_disable_unprepare(spi100k->fck);
439err_ick:
440 clk_disable_unprepare(spi100k->ick);
443err: 441err:
444 spi_master_put(master); 442 spi_master_put(master);
445 return status; 443 return status;
446} 444}
447 445
446static int omap1_spi100k_remove(struct platform_device *pdev)
447{
448 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
449 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
450
451 pm_runtime_disable(&pdev->dev);
452
453 clk_disable_unprepare(spi100k->fck);
454 clk_disable_unprepare(spi100k->ick);
455
456 return 0;
457}
458
459#ifdef CONFIG_PM
460static int omap1_spi100k_runtime_suspend(struct device *dev)
461{
462 struct spi_master *master = spi_master_get(dev_get_drvdata(dev));
463 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
464
465 clk_disable_unprepare(spi100k->ick);
466 clk_disable_unprepare(spi100k->fck);
467
468 return 0;
469}
470
471static int omap1_spi100k_runtime_resume(struct device *dev)
472{
473 struct spi_master *master = spi_master_get(dev_get_drvdata(dev));
474 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
475 int ret;
476
477 ret = clk_prepare_enable(spi100k->ick);
478 if (ret != 0) {
479 dev_err(dev, "Failed to enable ick: %d\n", ret);
480 return ret;
481 }
482
483 ret = clk_prepare_enable(spi100k->fck);
484 if (ret != 0) {
485 dev_err(dev, "Failed to enable fck: %d\n", ret);
486 clk_disable_unprepare(spi100k->ick);
487 return ret;
488 }
489
490 return 0;
491}
492#endif
493
494static const struct dev_pm_ops omap1_spi100k_pm = {
495 SET_RUNTIME_PM_OPS(omap1_spi100k_runtime_suspend,
496 omap1_spi100k_runtime_resume, NULL)
497};
498
448static struct platform_driver omap1_spi100k_driver = { 499static struct platform_driver omap1_spi100k_driver = {
449 .driver = { 500 .driver = {
450 .name = "omap1_spi100k", 501 .name = "omap1_spi100k",
502 .pm = &omap1_spi100k_pm,
451 }, 503 },
452 .probe = omap1_spi100k_probe, 504 .probe = omap1_spi100k_probe,
505 .remove = omap1_spi100k_remove,
453}; 506};
454 507
455module_platform_driver(omap1_spi100k_driver); 508module_platform_driver(omap1_spi100k_driver);
diff --git a/drivers/spi/spi-omap-uwire.c b/drivers/spi/spi-omap-uwire.c
index 3c0844457c07..55576db31549 100644
--- a/drivers/spi/spi-omap-uwire.c
+++ b/drivers/spi/spi-omap-uwire.c
@@ -44,7 +44,6 @@
44#include <linux/module.h> 44#include <linux/module.h>
45#include <linux/io.h> 45#include <linux/io.h>
46 46
47#include <asm/irq.h>
48#include <mach/hardware.h> 47#include <mach/hardware.h>
49#include <asm/mach-types.h> 48#include <asm/mach-types.h>
50 49
diff --git a/drivers/spi/spi-pl022.c b/drivers/spi/spi-pl022.c
index 89ca162801da..94af80676684 100644
--- a/drivers/spi/spi-pl022.c
+++ b/drivers/spi/spi-pl022.c
@@ -285,7 +285,12 @@
285 */ 285 */
286#define DEFAULT_SSP_REG_IMSC 0x0UL 286#define DEFAULT_SSP_REG_IMSC 0x0UL
287#define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC 287#define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC
288#define ENABLE_ALL_INTERRUPTS (~DEFAULT_SSP_REG_IMSC) 288#define ENABLE_ALL_INTERRUPTS ( \
289 SSP_IMSC_MASK_RORIM | \
290 SSP_IMSC_MASK_RTIM | \
291 SSP_IMSC_MASK_RXIM | \
292 SSP_IMSC_MASK_TXIM \
293)
289 294
290#define CLEAR_ALL_INTERRUPTS 0x3 295#define CLEAR_ALL_INTERRUPTS 0x3
291 296
@@ -534,12 +539,12 @@ static void giveback(struct pl022 *pl022)
534 pl022->cur_msg = NULL; 539 pl022->cur_msg = NULL;
535 pl022->cur_transfer = NULL; 540 pl022->cur_transfer = NULL;
536 pl022->cur_chip = NULL; 541 pl022->cur_chip = NULL;
537 spi_finalize_current_message(pl022->master);
538 542
539 /* disable the SPI/SSP operation */ 543 /* disable the SPI/SSP operation */
540 writew((readw(SSP_CR1(pl022->virtbase)) & 544 writew((readw(SSP_CR1(pl022->virtbase)) &
541 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); 545 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
542 546
547 spi_finalize_current_message(pl022->master);
543} 548}
544 549
545/** 550/**
@@ -1251,7 +1256,6 @@ static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id)
1251 struct pl022 *pl022 = dev_id; 1256 struct pl022 *pl022 = dev_id;
1252 struct spi_message *msg = pl022->cur_msg; 1257 struct spi_message *msg = pl022->cur_msg;
1253 u16 irq_status = 0; 1258 u16 irq_status = 0;
1254 u16 flag = 0;
1255 1259
1256 if (unlikely(!msg)) { 1260 if (unlikely(!msg)) {
1257 dev_err(&pl022->adev->dev, 1261 dev_err(&pl022->adev->dev,
@@ -1280,9 +1284,6 @@ static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id)
1280 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF) 1284 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF)
1281 dev_err(&pl022->adev->dev, 1285 dev_err(&pl022->adev->dev,
1282 "RXFIFO is full\n"); 1286 "RXFIFO is full\n");
1283 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_TNF)
1284 dev_err(&pl022->adev->dev,
1285 "TXFIFO is full\n");
1286 1287
1287 /* 1288 /*
1288 * Disable and clear interrupts, disable SSP, 1289 * Disable and clear interrupts, disable SSP,
@@ -1303,8 +1304,7 @@ static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id)
1303 1304
1304 readwriter(pl022); 1305 readwriter(pl022);
1305 1306
1306 if ((pl022->tx == pl022->tx_end) && (flag == 0)) { 1307 if (pl022->tx == pl022->tx_end) {
1307 flag = 1;
1308 /* Disable Transmit interrupt, enable receive interrupt */ 1308 /* Disable Transmit interrupt, enable receive interrupt */
1309 writew((readw(SSP_IMSC(pl022->virtbase)) & 1309 writew((readw(SSP_IMSC(pl022->virtbase)) &
1310 ~SSP_IMSC_MASK_TXIM) | SSP_IMSC_MASK_RXIM, 1310 ~SSP_IMSC_MASK_TXIM) | SSP_IMSC_MASK_RXIM,
diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c
index 6f72ad01e041..e3223ac75a7c 100644
--- a/drivers/spi/spi-pxa2xx.c
+++ b/drivers/spi/spi-pxa2xx.c
@@ -20,6 +20,7 @@
20#include <linux/errno.h> 20#include <linux/errno.h>
21#include <linux/err.h> 21#include <linux/err.h>
22#include <linux/interrupt.h> 22#include <linux/interrupt.h>
23#include <linux/kernel.h>
23#include <linux/platform_device.h> 24#include <linux/platform_device.h>
24#include <linux/spi/pxa2xx_spi.h> 25#include <linux/spi/pxa2xx_spi.h>
25#include <linux/spi/spi.h> 26#include <linux/spi/spi.h>
@@ -30,10 +31,6 @@
30#include <linux/pm_runtime.h> 31#include <linux/pm_runtime.h>
31#include <linux/acpi.h> 32#include <linux/acpi.h>
32 33
33#include <asm/io.h>
34#include <asm/irq.h>
35#include <asm/delay.h>
36
37#include "spi-pxa2xx.h" 34#include "spi-pxa2xx.h"
38 35
39MODULE_AUTHOR("Stephen Street"); 36MODULE_AUTHOR("Stephen Street");
@@ -67,54 +64,6 @@ MODULE_ALIAS("platform:pxa2xx-spi");
67#define LPSS_TX_LOTHRESH_DFLT 160 64#define LPSS_TX_LOTHRESH_DFLT 160
68#define LPSS_TX_HITHRESH_DFLT 224 65#define LPSS_TX_HITHRESH_DFLT 224
69 66
70struct quark_spi_rate {
71 u32 bitrate;
72 u32 dds_clk_rate;
73 u32 clk_div;
74};
75
76/*
77 * 'rate', 'dds', 'clk_div' lookup table, which is defined in
78 * the Quark SPI datasheet.
79 */
80static const struct quark_spi_rate quark_spi_rate_table[] = {
81/* bitrate, dds_clk_rate, clk_div */
82 {50000000, 0x800000, 0},
83 {40000000, 0x666666, 0},
84 {25000000, 0x400000, 0},
85 {20000000, 0x666666, 1},
86 {16667000, 0x800000, 2},
87 {13333000, 0x666666, 2},
88 {12500000, 0x200000, 0},
89 {10000000, 0x800000, 4},
90 {8000000, 0x666666, 4},
91 {6250000, 0x400000, 3},
92 {5000000, 0x400000, 4},
93 {4000000, 0x666666, 9},
94 {3125000, 0x80000, 0},
95 {2500000, 0x400000, 9},
96 {2000000, 0x666666, 19},
97 {1563000, 0x40000, 0},
98 {1250000, 0x200000, 9},
99 {1000000, 0x400000, 24},
100 {800000, 0x666666, 49},
101 {781250, 0x20000, 0},
102 {625000, 0x200000, 19},
103 {500000, 0x400000, 49},
104 {400000, 0x666666, 99},
105 {390625, 0x10000, 0},
106 {250000, 0x400000, 99},
107 {200000, 0x666666, 199},
108 {195313, 0x8000, 0},
109 {125000, 0x100000, 49},
110 {100000, 0x200000, 124},
111 {50000, 0x100000, 124},
112 {25000, 0x80000, 124},
113 {10016, 0x20000, 77},
114 {5040, 0x20000, 154},
115 {1002, 0x8000, 194},
116};
117
118/* Offset from drv_data->lpss_base */ 67/* Offset from drv_data->lpss_base */
119#define GENERAL_REG 0x08 68#define GENERAL_REG 0x08
120#define GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24) 69#define GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24)
@@ -701,25 +650,124 @@ static irqreturn_t ssp_int(int irq, void *dev_id)
701} 650}
702 651
703/* 652/*
704 * The Quark SPI data sheet gives a table, and for the given 'rate', 653 * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply
705 * the 'dds' and 'clk_div' can be found in the table. 654 * input frequency by fractions of 2^24. It also has a divider by 5.
655 *
656 * There are formulas to get baud rate value for given input frequency and
657 * divider parameters, such as DDS_CLK_RATE and SCR:
658 *
659 * Fsys = 200MHz
660 *
661 * Fssp = Fsys * DDS_CLK_RATE / 2^24 (1)
662 * Baud rate = Fsclk = Fssp / (2 * (SCR + 1)) (2)
663 *
664 * DDS_CLK_RATE either 2^n or 2^n / 5.
665 * SCR is in range 0 .. 255
666 *
667 * Divisor = 5^i * 2^j * 2 * k
668 * i = [0, 1] i = 1 iff j = 0 or j > 3
669 * j = [0, 23] j = 0 iff i = 1
670 * k = [1, 256]
671 * Special case: j = 0, i = 1: Divisor = 2 / 5
672 *
673 * Accordingly to the specification the recommended values for DDS_CLK_RATE
674 * are:
675 * Case 1: 2^n, n = [0, 23]
676 * Case 2: 2^24 * 2 / 5 (0x666666)
677 * Case 3: less than or equal to 2^24 / 5 / 16 (0x33333)
678 *
679 * In all cases the lowest possible value is better.
680 *
681 * The function calculates parameters for all cases and chooses the one closest
682 * to the asked baud rate.
706 */ 683 */
707static u32 quark_x1000_set_clk_regvals(u32 rate, u32 *dds, u32 *clk_div) 684static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds)
708{ 685{
709 unsigned int i; 686 unsigned long xtal = 200000000;
710 687 unsigned long fref = xtal / 2; /* mandatory division by 2,
711 for (i = 0; i < ARRAY_SIZE(quark_spi_rate_table); i++) { 688 see (2) */
712 if (rate >= quark_spi_rate_table[i].bitrate) { 689 /* case 3 */
713 *dds = quark_spi_rate_table[i].dds_clk_rate; 690 unsigned long fref1 = fref / 2; /* case 1 */
714 *clk_div = quark_spi_rate_table[i].clk_div; 691 unsigned long fref2 = fref * 2 / 5; /* case 2 */
715 return quark_spi_rate_table[i].bitrate; 692 unsigned long scale;
693 unsigned long q, q1, q2;
694 long r, r1, r2;
695 u32 mul;
696
697 /* Case 1 */
698
699 /* Set initial value for DDS_CLK_RATE */
700 mul = (1 << 24) >> 1;
701
702 /* Calculate initial quot */
703 q1 = DIV_ROUND_CLOSEST(fref1, rate);
704
705 /* Scale q1 if it's too big */
706 if (q1 > 256) {
707 /* Scale q1 to range [1, 512] */
708 scale = fls_long(q1 - 1);
709 if (scale > 9) {
710 q1 >>= scale - 9;
711 mul >>= scale - 9;
716 } 712 }
713
714 /* Round the result if we have a remainder */
715 q1 += q1 & 1;
717 } 716 }
718 717
719 *dds = quark_spi_rate_table[i-1].dds_clk_rate; 718 /* Decrease DDS_CLK_RATE as much as we can without loss in precision */
720 *clk_div = quark_spi_rate_table[i-1].clk_div; 719 scale = __ffs(q1);
720 q1 >>= scale;
721 mul >>= scale;
722
723 /* Get the remainder */
724 r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate);
725
726 /* Case 2 */
727
728 q2 = DIV_ROUND_CLOSEST(fref2, rate);
729 r2 = abs(fref2 / q2 - rate);
721 730
722 return quark_spi_rate_table[i-1].bitrate; 731 /*
732 * Choose the best between two: less remainder we have the better. We
733 * can't go case 2 if q2 is greater than 256 since SCR register can
734 * hold only values 0 .. 255.
735 */
736 if (r2 >= r1 || q2 > 256) {
737 /* case 1 is better */
738 r = r1;
739 q = q1;
740 } else {
741 /* case 2 is better */
742 r = r2;
743 q = q2;
744 mul = (1 << 24) * 2 / 5;
745 }
746
747 /* Check case 3 only If the divisor is big enough */
748 if (fref / rate >= 80) {
749 u64 fssp;
750 u32 m;
751
752 /* Calculate initial quot */
753 q1 = DIV_ROUND_CLOSEST(fref, rate);
754 m = (1 << 24) / q1;
755
756 /* Get the remainder */
757 fssp = (u64)fref * m;
758 do_div(fssp, 1 << 24);
759 r1 = abs(fssp - rate);
760
761 /* Choose this one if it suits better */
762 if (r1 < r) {
763 /* case 3 is better */
764 q = 1;
765 mul = m;
766 }
767 }
768
769 *dds = mul;
770 return q - 1;
723} 771}
724 772
725static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate) 773static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
@@ -730,23 +778,25 @@ static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
730 rate = min_t(int, ssp_clk, rate); 778 rate = min_t(int, ssp_clk, rate);
731 779
732 if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP) 780 if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
733 return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8; 781 return (ssp_clk / (2 * rate) - 1) & 0xff;
734 else 782 else
735 return ((ssp_clk / rate - 1) & 0xfff) << 8; 783 return (ssp_clk / rate - 1) & 0xfff;
736} 784}
737 785
738static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data, 786static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data,
739 struct chip_data *chip, int rate) 787 struct chip_data *chip, int rate)
740{ 788{
741 u32 clk_div; 789 unsigned int clk_div;
742 790
743 switch (drv_data->ssp_type) { 791 switch (drv_data->ssp_type) {
744 case QUARK_X1000_SSP: 792 case QUARK_X1000_SSP:
745 quark_x1000_set_clk_regvals(rate, &chip->dds_rate, &clk_div); 793 clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate);
746 return clk_div << 8; 794 break;
747 default: 795 default:
748 return ssp_get_clk_div(drv_data, rate); 796 clk_div = ssp_get_clk_div(drv_data, rate);
797 break;
749 } 798 }
799 return clk_div << 8;
750} 800}
751 801
752static void pump_transfers(unsigned long data) 802static void pump_transfers(unsigned long data)
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
index ff9cdbdb6672..810a7fae3479 100644
--- a/drivers/spi/spi-qup.c
+++ b/drivers/spi/spi-qup.c
@@ -22,6 +22,8 @@
22#include <linux/platform_device.h> 22#include <linux/platform_device.h>
23#include <linux/pm_runtime.h> 23#include <linux/pm_runtime.h>
24#include <linux/spi/spi.h> 24#include <linux/spi/spi.h>
25#include <linux/dmaengine.h>
26#include <linux/dma-mapping.h>
25 27
26#define QUP_CONFIG 0x0000 28#define QUP_CONFIG 0x0000
27#define QUP_STATE 0x0004 29#define QUP_STATE 0x0004
@@ -116,6 +118,8 @@
116 118
117#define SPI_NUM_CHIPSELECTS 4 119#define SPI_NUM_CHIPSELECTS 4
118 120
121#define SPI_MAX_DMA_XFER (SZ_64K - 64)
122
119/* high speed mode is when bus rate is greater then 26MHz */ 123/* high speed mode is when bus rate is greater then 26MHz */
120#define SPI_HS_MIN_RATE 26000000 124#define SPI_HS_MIN_RATE 26000000
121#define SPI_MAX_RATE 50000000 125#define SPI_MAX_RATE 50000000
@@ -140,9 +144,14 @@ struct spi_qup {
140 struct completion done; 144 struct completion done;
141 int error; 145 int error;
142 int w_size; /* bytes per SPI word */ 146 int w_size; /* bytes per SPI word */
147 int n_words;
143 int tx_bytes; 148 int tx_bytes;
144 int rx_bytes; 149 int rx_bytes;
145 int qup_v1; 150 int qup_v1;
151
152 int use_dma;
153 struct dma_slave_config rx_conf;
154 struct dma_slave_config tx_conf;
146}; 155};
147 156
148 157
@@ -198,7 +207,6 @@ static int spi_qup_set_state(struct spi_qup *controller, u32 state)
198 return 0; 207 return 0;
199} 208}
200 209
201
202static void spi_qup_fifo_read(struct spi_qup *controller, 210static void spi_qup_fifo_read(struct spi_qup *controller,
203 struct spi_transfer *xfer) 211 struct spi_transfer *xfer)
204{ 212{
@@ -266,6 +274,107 @@ static void spi_qup_fifo_write(struct spi_qup *controller,
266 } 274 }
267} 275}
268 276
277static void spi_qup_dma_done(void *data)
278{
279 struct spi_qup *qup = data;
280
281 complete(&qup->done);
282}
283
284static int spi_qup_prep_sg(struct spi_master *master, struct spi_transfer *xfer,
285 enum dma_transfer_direction dir,
286 dma_async_tx_callback callback)
287{
288 struct spi_qup *qup = spi_master_get_devdata(master);
289 unsigned long flags = DMA_PREP_INTERRUPT | DMA_PREP_FENCE;
290 struct dma_async_tx_descriptor *desc;
291 struct scatterlist *sgl;
292 struct dma_chan *chan;
293 dma_cookie_t cookie;
294 unsigned int nents;
295
296 if (dir == DMA_MEM_TO_DEV) {
297 chan = master->dma_tx;
298 nents = xfer->tx_sg.nents;
299 sgl = xfer->tx_sg.sgl;
300 } else {
301 chan = master->dma_rx;
302 nents = xfer->rx_sg.nents;
303 sgl = xfer->rx_sg.sgl;
304 }
305
306 desc = dmaengine_prep_slave_sg(chan, sgl, nents, dir, flags);
307 if (!desc)
308 return -EINVAL;
309
310 desc->callback = callback;
311 desc->callback_param = qup;
312
313 cookie = dmaengine_submit(desc);
314
315 return dma_submit_error(cookie);
316}
317
318static void spi_qup_dma_terminate(struct spi_master *master,
319 struct spi_transfer *xfer)
320{
321 if (xfer->tx_buf)
322 dmaengine_terminate_all(master->dma_tx);
323 if (xfer->rx_buf)
324 dmaengine_terminate_all(master->dma_rx);
325}
326
327static int spi_qup_do_dma(struct spi_master *master, struct spi_transfer *xfer)
328{
329 dma_async_tx_callback rx_done = NULL, tx_done = NULL;
330 int ret;
331
332 if (xfer->rx_buf)
333 rx_done = spi_qup_dma_done;
334 else if (xfer->tx_buf)
335 tx_done = spi_qup_dma_done;
336
337 if (xfer->rx_buf) {
338 ret = spi_qup_prep_sg(master, xfer, DMA_DEV_TO_MEM, rx_done);
339 if (ret)
340 return ret;
341
342 dma_async_issue_pending(master->dma_rx);
343 }
344
345 if (xfer->tx_buf) {
346 ret = spi_qup_prep_sg(master, xfer, DMA_MEM_TO_DEV, tx_done);
347 if (ret)
348 return ret;
349
350 dma_async_issue_pending(master->dma_tx);
351 }
352
353 return 0;
354}
355
356static int spi_qup_do_pio(struct spi_master *master, struct spi_transfer *xfer)
357{
358 struct spi_qup *qup = spi_master_get_devdata(master);
359 int ret;
360
361 ret = spi_qup_set_state(qup, QUP_STATE_RUN);
362 if (ret) {
363 dev_warn(qup->dev, "cannot set RUN state\n");
364 return ret;
365 }
366
367 ret = spi_qup_set_state(qup, QUP_STATE_PAUSE);
368 if (ret) {
369 dev_warn(qup->dev, "cannot set PAUSE state\n");
370 return ret;
371 }
372
373 spi_qup_fifo_write(qup, xfer);
374
375 return 0;
376}
377
269static irqreturn_t spi_qup_qup_irq(int irq, void *dev_id) 378static irqreturn_t spi_qup_qup_irq(int irq, void *dev_id)
270{ 379{
271 struct spi_qup *controller = dev_id; 380 struct spi_qup *controller = dev_id;
@@ -315,11 +424,13 @@ static irqreturn_t spi_qup_qup_irq(int irq, void *dev_id)
315 error = -EIO; 424 error = -EIO;
316 } 425 }
317 426
318 if (opflags & QUP_OP_IN_SERVICE_FLAG) 427 if (!controller->use_dma) {
319 spi_qup_fifo_read(controller, xfer); 428 if (opflags & QUP_OP_IN_SERVICE_FLAG)
429 spi_qup_fifo_read(controller, xfer);
320 430
321 if (opflags & QUP_OP_OUT_SERVICE_FLAG) 431 if (opflags & QUP_OP_OUT_SERVICE_FLAG)
322 spi_qup_fifo_write(controller, xfer); 432 spi_qup_fifo_write(controller, xfer);
433 }
323 434
324 spin_lock_irqsave(&controller->lock, flags); 435 spin_lock_irqsave(&controller->lock, flags);
325 controller->error = error; 436 controller->error = error;
@@ -332,13 +443,35 @@ static irqreturn_t spi_qup_qup_irq(int irq, void *dev_id)
332 return IRQ_HANDLED; 443 return IRQ_HANDLED;
333} 444}
334 445
446static u32
447spi_qup_get_mode(struct spi_master *master, struct spi_transfer *xfer)
448{
449 struct spi_qup *qup = spi_master_get_devdata(master);
450 u32 mode;
451
452 qup->w_size = 4;
453
454 if (xfer->bits_per_word <= 8)
455 qup->w_size = 1;
456 else if (xfer->bits_per_word <= 16)
457 qup->w_size = 2;
458
459 qup->n_words = xfer->len / qup->w_size;
460
461 if (qup->n_words <= (qup->in_fifo_sz / sizeof(u32)))
462 mode = QUP_IO_M_MODE_FIFO;
463 else
464 mode = QUP_IO_M_MODE_BLOCK;
465
466 return mode;
467}
335 468
336/* set clock freq ... bits per word */ 469/* set clock freq ... bits per word */
337static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer) 470static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
338{ 471{
339 struct spi_qup *controller = spi_master_get_devdata(spi->master); 472 struct spi_qup *controller = spi_master_get_devdata(spi->master);
340 u32 config, iomode, mode, control; 473 u32 config, iomode, mode, control;
341 int ret, n_words, w_size; 474 int ret, n_words;
342 475
343 if (spi->mode & SPI_LOOP && xfer->len > controller->in_fifo_sz) { 476 if (spi->mode & SPI_LOOP && xfer->len > controller->in_fifo_sz) {
344 dev_err(controller->dev, "too big size for loopback %d > %d\n", 477 dev_err(controller->dev, "too big size for loopback %d > %d\n",
@@ -358,35 +491,54 @@ static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
358 return -EIO; 491 return -EIO;
359 } 492 }
360 493
361 w_size = 4; 494 mode = spi_qup_get_mode(spi->master, xfer);
362 if (xfer->bits_per_word <= 8) 495 n_words = controller->n_words;
363 w_size = 1;
364 else if (xfer->bits_per_word <= 16)
365 w_size = 2;
366 496
367 n_words = xfer->len / w_size; 497 if (mode == QUP_IO_M_MODE_FIFO) {
368 controller->w_size = w_size;
369
370 if (n_words <= (controller->in_fifo_sz / sizeof(u32))) {
371 mode = QUP_IO_M_MODE_FIFO;
372 writel_relaxed(n_words, controller->base + QUP_MX_READ_CNT); 498 writel_relaxed(n_words, controller->base + QUP_MX_READ_CNT);
373 writel_relaxed(n_words, controller->base + QUP_MX_WRITE_CNT); 499 writel_relaxed(n_words, controller->base + QUP_MX_WRITE_CNT);
374 /* must be zero for FIFO */ 500 /* must be zero for FIFO */
375 writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT); 501 writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT);
376 writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT); 502 writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
377 } else { 503 } else if (!controller->use_dma) {
378 mode = QUP_IO_M_MODE_BLOCK;
379 writel_relaxed(n_words, controller->base + QUP_MX_INPUT_CNT); 504 writel_relaxed(n_words, controller->base + QUP_MX_INPUT_CNT);
380 writel_relaxed(n_words, controller->base + QUP_MX_OUTPUT_CNT); 505 writel_relaxed(n_words, controller->base + QUP_MX_OUTPUT_CNT);
381 /* must be zero for BLOCK and BAM */ 506 /* must be zero for BLOCK and BAM */
382 writel_relaxed(0, controller->base + QUP_MX_READ_CNT); 507 writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
383 writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT); 508 writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
509 } else {
510 mode = QUP_IO_M_MODE_BAM;
511 writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
512 writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
513
514 if (!controller->qup_v1) {
515 void __iomem *input_cnt;
516
517 input_cnt = controller->base + QUP_MX_INPUT_CNT;
518 /*
519 * for DMA transfers, both QUP_MX_INPUT_CNT and
520 * QUP_MX_OUTPUT_CNT must be zero to all cases but one.
521 * That case is a non-balanced transfer when there is
522 * only a rx_buf.
523 */
524 if (xfer->tx_buf)
525 writel_relaxed(0, input_cnt);
526 else
527 writel_relaxed(n_words, input_cnt);
528
529 writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
530 }
384 } 531 }
385 532
386 iomode = readl_relaxed(controller->base + QUP_IO_M_MODES); 533 iomode = readl_relaxed(controller->base + QUP_IO_M_MODES);
387 /* Set input and output transfer mode */ 534 /* Set input and output transfer mode */
388 iomode &= ~(QUP_IO_M_INPUT_MODE_MASK | QUP_IO_M_OUTPUT_MODE_MASK); 535 iomode &= ~(QUP_IO_M_INPUT_MODE_MASK | QUP_IO_M_OUTPUT_MODE_MASK);
389 iomode &= ~(QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN); 536
537 if (!controller->use_dma)
538 iomode &= ~(QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN);
539 else
540 iomode |= QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN;
541
390 iomode |= (mode << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT); 542 iomode |= (mode << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT);
391 iomode |= (mode << QUP_IO_M_INPUT_MODE_MASK_SHIFT); 543 iomode |= (mode << QUP_IO_M_INPUT_MODE_MASK_SHIFT);
392 544
@@ -428,11 +580,31 @@ static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
428 config &= ~(QUP_CONFIG_NO_INPUT | QUP_CONFIG_NO_OUTPUT | QUP_CONFIG_N); 580 config &= ~(QUP_CONFIG_NO_INPUT | QUP_CONFIG_NO_OUTPUT | QUP_CONFIG_N);
429 config |= xfer->bits_per_word - 1; 581 config |= xfer->bits_per_word - 1;
430 config |= QUP_CONFIG_SPI_MODE; 582 config |= QUP_CONFIG_SPI_MODE;
583
584 if (controller->use_dma) {
585 if (!xfer->tx_buf)
586 config |= QUP_CONFIG_NO_OUTPUT;
587 if (!xfer->rx_buf)
588 config |= QUP_CONFIG_NO_INPUT;
589 }
590
431 writel_relaxed(config, controller->base + QUP_CONFIG); 591 writel_relaxed(config, controller->base + QUP_CONFIG);
432 592
433 /* only write to OPERATIONAL_MASK when register is present */ 593 /* only write to OPERATIONAL_MASK when register is present */
434 if (!controller->qup_v1) 594 if (!controller->qup_v1) {
435 writel_relaxed(0, controller->base + QUP_OPERATIONAL_MASK); 595 u32 mask = 0;
596
597 /*
598 * mask INPUT and OUTPUT service flags to prevent IRQs on FIFO
599 * status change in BAM mode
600 */
601
602 if (mode == QUP_IO_M_MODE_BAM)
603 mask = QUP_OP_IN_SERVICE_FLAG | QUP_OP_OUT_SERVICE_FLAG;
604
605 writel_relaxed(mask, controller->base + QUP_OPERATIONAL_MASK);
606 }
607
436 return 0; 608 return 0;
437} 609}
438 610
@@ -461,17 +633,13 @@ static int spi_qup_transfer_one(struct spi_master *master,
461 controller->tx_bytes = 0; 633 controller->tx_bytes = 0;
462 spin_unlock_irqrestore(&controller->lock, flags); 634 spin_unlock_irqrestore(&controller->lock, flags);
463 635
464 if (spi_qup_set_state(controller, QUP_STATE_RUN)) { 636 if (controller->use_dma)
465 dev_warn(controller->dev, "cannot set RUN state\n"); 637 ret = spi_qup_do_dma(master, xfer);
466 goto exit; 638 else
467 } 639 ret = spi_qup_do_pio(master, xfer);
468 640
469 if (spi_qup_set_state(controller, QUP_STATE_PAUSE)) { 641 if (ret)
470 dev_warn(controller->dev, "cannot set PAUSE state\n");
471 goto exit; 642 goto exit;
472 }
473
474 spi_qup_fifo_write(controller, xfer);
475 643
476 if (spi_qup_set_state(controller, QUP_STATE_RUN)) { 644 if (spi_qup_set_state(controller, QUP_STATE_RUN)) {
477 dev_warn(controller->dev, "cannot set EXECUTE state\n"); 645 dev_warn(controller->dev, "cannot set EXECUTE state\n");
@@ -480,6 +648,7 @@ static int spi_qup_transfer_one(struct spi_master *master,
480 648
481 if (!wait_for_completion_timeout(&controller->done, timeout)) 649 if (!wait_for_completion_timeout(&controller->done, timeout))
482 ret = -ETIMEDOUT; 650 ret = -ETIMEDOUT;
651
483exit: 652exit:
484 spi_qup_set_state(controller, QUP_STATE_RESET); 653 spi_qup_set_state(controller, QUP_STATE_RESET);
485 spin_lock_irqsave(&controller->lock, flags); 654 spin_lock_irqsave(&controller->lock, flags);
@@ -487,6 +656,97 @@ exit:
487 if (!ret) 656 if (!ret)
488 ret = controller->error; 657 ret = controller->error;
489 spin_unlock_irqrestore(&controller->lock, flags); 658 spin_unlock_irqrestore(&controller->lock, flags);
659
660 if (ret && controller->use_dma)
661 spi_qup_dma_terminate(master, xfer);
662
663 return ret;
664}
665
666static bool spi_qup_can_dma(struct spi_master *master, struct spi_device *spi,
667 struct spi_transfer *xfer)
668{
669 struct spi_qup *qup = spi_master_get_devdata(master);
670 size_t dma_align = dma_get_cache_alignment();
671 u32 mode;
672
673 qup->use_dma = 0;
674
675 if (xfer->rx_buf && (xfer->len % qup->in_blk_sz ||
676 IS_ERR_OR_NULL(master->dma_rx) ||
677 !IS_ALIGNED((size_t)xfer->rx_buf, dma_align)))
678 return false;
679
680 if (xfer->tx_buf && (xfer->len % qup->out_blk_sz ||
681 IS_ERR_OR_NULL(master->dma_tx) ||
682 !IS_ALIGNED((size_t)xfer->tx_buf, dma_align)))
683 return false;
684
685 mode = spi_qup_get_mode(master, xfer);
686 if (mode == QUP_IO_M_MODE_FIFO)
687 return false;
688
689 qup->use_dma = 1;
690
691 return true;
692}
693
694static void spi_qup_release_dma(struct spi_master *master)
695{
696 if (!IS_ERR_OR_NULL(master->dma_rx))
697 dma_release_channel(master->dma_rx);
698 if (!IS_ERR_OR_NULL(master->dma_tx))
699 dma_release_channel(master->dma_tx);
700}
701
702static int spi_qup_init_dma(struct spi_master *master, resource_size_t base)
703{
704 struct spi_qup *spi = spi_master_get_devdata(master);
705 struct dma_slave_config *rx_conf = &spi->rx_conf,
706 *tx_conf = &spi->tx_conf;
707 struct device *dev = spi->dev;
708 int ret;
709
710 /* allocate dma resources, if available */
711 master->dma_rx = dma_request_slave_channel_reason(dev, "rx");
712 if (IS_ERR(master->dma_rx))
713 return PTR_ERR(master->dma_rx);
714
715 master->dma_tx = dma_request_slave_channel_reason(dev, "tx");
716 if (IS_ERR(master->dma_tx)) {
717 ret = PTR_ERR(master->dma_tx);
718 goto err_tx;
719 }
720
721 /* set DMA parameters */
722 rx_conf->direction = DMA_DEV_TO_MEM;
723 rx_conf->device_fc = 1;
724 rx_conf->src_addr = base + QUP_INPUT_FIFO;
725 rx_conf->src_maxburst = spi->in_blk_sz;
726
727 tx_conf->direction = DMA_MEM_TO_DEV;
728 tx_conf->device_fc = 1;
729 tx_conf->dst_addr = base + QUP_OUTPUT_FIFO;
730 tx_conf->dst_maxburst = spi->out_blk_sz;
731
732 ret = dmaengine_slave_config(master->dma_rx, rx_conf);
733 if (ret) {
734 dev_err(dev, "failed to configure RX channel\n");
735 goto err;
736 }
737
738 ret = dmaengine_slave_config(master->dma_tx, tx_conf);
739 if (ret) {
740 dev_err(dev, "failed to configure TX channel\n");
741 goto err;
742 }
743
744 return 0;
745
746err:
747 dma_release_channel(master->dma_tx);
748err_tx:
749 dma_release_channel(master->dma_rx);
490 return ret; 750 return ret;
491} 751}
492 752
@@ -498,7 +758,7 @@ static int spi_qup_probe(struct platform_device *pdev)
498 struct resource *res; 758 struct resource *res;
499 struct device *dev; 759 struct device *dev;
500 void __iomem *base; 760 void __iomem *base;
501 u32 max_freq, iomode; 761 u32 max_freq, iomode, num_cs;
502 int ret, irq, size; 762 int ret, irq, size;
503 763
504 dev = &pdev->dev; 764 dev = &pdev->dev;
@@ -550,10 +810,11 @@ static int spi_qup_probe(struct platform_device *pdev)
550 } 810 }
551 811
552 /* use num-cs unless not present or out of range */ 812 /* use num-cs unless not present or out of range */
553 if (of_property_read_u16(dev->of_node, "num-cs", 813 if (of_property_read_u32(dev->of_node, "num-cs", &num_cs) ||
554 &master->num_chipselect) || 814 num_cs > SPI_NUM_CHIPSELECTS)
555 (master->num_chipselect > SPI_NUM_CHIPSELECTS))
556 master->num_chipselect = SPI_NUM_CHIPSELECTS; 815 master->num_chipselect = SPI_NUM_CHIPSELECTS;
816 else
817 master->num_chipselect = num_cs;
557 818
558 master->bus_num = pdev->id; 819 master->bus_num = pdev->id;
559 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; 820 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
@@ -562,6 +823,8 @@ static int spi_qup_probe(struct platform_device *pdev)
562 master->transfer_one = spi_qup_transfer_one; 823 master->transfer_one = spi_qup_transfer_one;
563 master->dev.of_node = pdev->dev.of_node; 824 master->dev.of_node = pdev->dev.of_node;
564 master->auto_runtime_pm = true; 825 master->auto_runtime_pm = true;
826 master->dma_alignment = dma_get_cache_alignment();
827 master->max_dma_len = SPI_MAX_DMA_XFER;
565 828
566 platform_set_drvdata(pdev, master); 829 platform_set_drvdata(pdev, master);
567 830
@@ -573,6 +836,12 @@ static int spi_qup_probe(struct platform_device *pdev)
573 controller->cclk = cclk; 836 controller->cclk = cclk;
574 controller->irq = irq; 837 controller->irq = irq;
575 838
839 ret = spi_qup_init_dma(master, res->start);
840 if (ret == -EPROBE_DEFER)
841 goto error;
842 else if (!ret)
843 master->can_dma = spi_qup_can_dma;
844
576 /* set v1 flag if device is version 1 */ 845 /* set v1 flag if device is version 1 */
577 if (of_device_is_compatible(dev->of_node, "qcom,spi-qup-v1.1.1")) 846 if (of_device_is_compatible(dev->of_node, "qcom,spi-qup-v1.1.1"))
578 controller->qup_v1 = 1; 847 controller->qup_v1 = 1;
@@ -609,7 +878,7 @@ static int spi_qup_probe(struct platform_device *pdev)
609 ret = spi_qup_set_state(controller, QUP_STATE_RESET); 878 ret = spi_qup_set_state(controller, QUP_STATE_RESET);
610 if (ret) { 879 if (ret) {
611 dev_err(dev, "cannot set RESET state\n"); 880 dev_err(dev, "cannot set RESET state\n");
612 goto error; 881 goto error_dma;
613 } 882 }
614 883
615 writel_relaxed(0, base + QUP_OPERATIONAL); 884 writel_relaxed(0, base + QUP_OPERATIONAL);
@@ -633,7 +902,7 @@ static int spi_qup_probe(struct platform_device *pdev)
633 ret = devm_request_irq(dev, irq, spi_qup_qup_irq, 902 ret = devm_request_irq(dev, irq, spi_qup_qup_irq,
634 IRQF_TRIGGER_HIGH, pdev->name, controller); 903 IRQF_TRIGGER_HIGH, pdev->name, controller);
635 if (ret) 904 if (ret)
636 goto error; 905 goto error_dma;
637 906
638 pm_runtime_set_autosuspend_delay(dev, MSEC_PER_SEC); 907 pm_runtime_set_autosuspend_delay(dev, MSEC_PER_SEC);
639 pm_runtime_use_autosuspend(dev); 908 pm_runtime_use_autosuspend(dev);
@@ -648,6 +917,8 @@ static int spi_qup_probe(struct platform_device *pdev)
648 917
649disable_pm: 918disable_pm:
650 pm_runtime_disable(&pdev->dev); 919 pm_runtime_disable(&pdev->dev);
920error_dma:
921 spi_qup_release_dma(master);
651error: 922error:
652 clk_disable_unprepare(cclk); 923 clk_disable_unprepare(cclk);
653 clk_disable_unprepare(iclk); 924 clk_disable_unprepare(iclk);
@@ -739,6 +1010,8 @@ static int spi_qup_remove(struct platform_device *pdev)
739 if (ret) 1010 if (ret)
740 return ret; 1011 return ret;
741 1012
1013 spi_qup_release_dma(master);
1014
742 clk_disable_unprepare(controller->cclk); 1015 clk_disable_unprepare(controller->cclk);
743 clk_disable_unprepare(controller->iclk); 1016 clk_disable_unprepare(controller->iclk);
744 1017
diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c
index 1a777dc261d6..68e7efeb9a27 100644
--- a/drivers/spi/spi-rockchip.c
+++ b/drivers/spi/spi-rockchip.c
@@ -179,6 +179,7 @@ struct rockchip_spi {
179 u8 tmode; 179 u8 tmode;
180 u8 bpw; 180 u8 bpw;
181 u8 n_bytes; 181 u8 n_bytes;
182 u8 rsd_nsecs;
182 unsigned len; 183 unsigned len;
183 u32 speed; 184 u32 speed;
184 185
@@ -302,8 +303,8 @@ static int rockchip_spi_prepare_message(struct spi_master *master,
302 return 0; 303 return 0;
303} 304}
304 305
305static int rockchip_spi_unprepare_message(struct spi_master *master, 306static void rockchip_spi_handle_err(struct spi_master *master,
306 struct spi_message *msg) 307 struct spi_message *msg)
307{ 308{
308 unsigned long flags; 309 unsigned long flags;
309 struct rockchip_spi *rs = spi_master_get_devdata(master); 310 struct rockchip_spi *rs = spi_master_get_devdata(master);
@@ -313,8 +314,8 @@ static int rockchip_spi_unprepare_message(struct spi_master *master,
313 /* 314 /*
314 * For DMA mode, we need terminate DMA channel and flush 315 * For DMA mode, we need terminate DMA channel and flush
315 * fifo for the next transfer if DMA thansfer timeout. 316 * fifo for the next transfer if DMA thansfer timeout.
316 * unprepare_message() was called by core if transfer complete 317 * handle_err() was called by core if transfer failed.
317 * or timeout. Maybe it is reasonable for error handling here. 318 * Maybe it is reasonable for error handling here.
318 */ 319 */
319 if (rs->use_dma) { 320 if (rs->use_dma) {
320 if (rs->state & RXBUSY) { 321 if (rs->state & RXBUSY) {
@@ -327,6 +328,12 @@ static int rockchip_spi_unprepare_message(struct spi_master *master,
327 } 328 }
328 329
329 spin_unlock_irqrestore(&rs->lock, flags); 330 spin_unlock_irqrestore(&rs->lock, flags);
331}
332
333static int rockchip_spi_unprepare_message(struct spi_master *master,
334 struct spi_message *msg)
335{
336 struct rockchip_spi *rs = spi_master_get_devdata(master);
330 337
331 spi_enable_chip(rs, 0); 338 spi_enable_chip(rs, 0);
332 339
@@ -493,6 +500,7 @@ static void rockchip_spi_config(struct rockchip_spi *rs)
493{ 500{
494 u32 div = 0; 501 u32 div = 0;
495 u32 dmacr = 0; 502 u32 dmacr = 0;
503 int rsd = 0;
496 504
497 u32 cr0 = (CR0_BHT_8BIT << CR0_BHT_OFFSET) 505 u32 cr0 = (CR0_BHT_8BIT << CR0_BHT_OFFSET)
498 | (CR0_SSD_ONE << CR0_SSD_OFFSET); 506 | (CR0_SSD_ONE << CR0_SSD_OFFSET);
@@ -519,9 +527,23 @@ static void rockchip_spi_config(struct rockchip_spi *rs)
519 } 527 }
520 528
521 /* div doesn't support odd number */ 529 /* div doesn't support odd number */
522 div = max_t(u32, rs->max_freq / rs->speed, 1); 530 div = DIV_ROUND_UP(rs->max_freq, rs->speed);
523 div = (div + 1) & 0xfffe; 531 div = (div + 1) & 0xfffe;
524 532
533 /* Rx sample delay is expressed in parent clock cycles (max 3) */
534 rsd = DIV_ROUND_CLOSEST(rs->rsd_nsecs * (rs->max_freq >> 8),
535 1000000000 >> 8);
536 if (!rsd && rs->rsd_nsecs) {
537 pr_warn_once("rockchip-spi: %u Hz are too slow to express %u ns delay\n",
538 rs->max_freq, rs->rsd_nsecs);
539 } else if (rsd > 3) {
540 rsd = 3;
541 pr_warn_once("rockchip-spi: %u Hz are too fast to express %u ns delay, clamping at %u ns\n",
542 rs->max_freq, rs->rsd_nsecs,
543 rsd * 1000000000U / rs->max_freq);
544 }
545 cr0 |= rsd << CR0_RSD_OFFSET;
546
525 writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0); 547 writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
526 548
527 writel_relaxed(rs->len - 1, rs->regs + ROCKCHIP_SPI_CTRLR1); 549 writel_relaxed(rs->len - 1, rs->regs + ROCKCHIP_SPI_CTRLR1);
@@ -614,6 +636,7 @@ static int rockchip_spi_probe(struct platform_device *pdev)
614 struct rockchip_spi *rs; 636 struct rockchip_spi *rs;
615 struct spi_master *master; 637 struct spi_master *master;
616 struct resource *mem; 638 struct resource *mem;
639 u32 rsd_nsecs;
617 640
618 master = spi_alloc_master(&pdev->dev, sizeof(struct rockchip_spi)); 641 master = spi_alloc_master(&pdev->dev, sizeof(struct rockchip_spi));
619 if (!master) 642 if (!master)
@@ -665,6 +688,10 @@ static int rockchip_spi_probe(struct platform_device *pdev)
665 rs->dev = &pdev->dev; 688 rs->dev = &pdev->dev;
666 rs->max_freq = clk_get_rate(rs->spiclk); 689 rs->max_freq = clk_get_rate(rs->spiclk);
667 690
691 if (!of_property_read_u32(pdev->dev.of_node, "rx-sample-delay-ns",
692 &rsd_nsecs))
693 rs->rsd_nsecs = rsd_nsecs;
694
668 rs->fifo_len = get_fifo_len(rs); 695 rs->fifo_len = get_fifo_len(rs);
669 if (!rs->fifo_len) { 696 if (!rs->fifo_len) {
670 dev_err(&pdev->dev, "Failed to get fifo length\n"); 697 dev_err(&pdev->dev, "Failed to get fifo length\n");
@@ -688,6 +715,7 @@ static int rockchip_spi_probe(struct platform_device *pdev)
688 master->prepare_message = rockchip_spi_prepare_message; 715 master->prepare_message = rockchip_spi_prepare_message;
689 master->unprepare_message = rockchip_spi_unprepare_message; 716 master->unprepare_message = rockchip_spi_unprepare_message;
690 master->transfer_one = rockchip_spi_transfer_one; 717 master->transfer_one = rockchip_spi_transfer_one;
718 master->handle_err = rockchip_spi_handle_err;
691 719
692 rs->dma_tx.ch = dma_request_slave_channel(rs->dev, "tx"); 720 rs->dma_tx.ch = dma_request_slave_channel(rs->dev, "tx");
693 if (!rs->dma_tx.ch) 721 if (!rs->dma_tx.ch)
diff --git a/drivers/spi/spi-rspi.c b/drivers/spi/spi-rspi.c
index 46ce47076e63..186924aa4740 100644
--- a/drivers/spi/spi-rspi.c
+++ b/drivers/spi/spi-rspi.c
@@ -177,6 +177,13 @@
177#define SPBFCR_RXRST 0x40 /* Receive Buffer Data Reset */ 177#define SPBFCR_RXRST 0x40 /* Receive Buffer Data Reset */
178#define SPBFCR_TXTRG_MASK 0x30 /* Transmit Buffer Data Triggering Number */ 178#define SPBFCR_TXTRG_MASK 0x30 /* Transmit Buffer Data Triggering Number */
179#define SPBFCR_RXTRG_MASK 0x07 /* Receive Buffer Data Triggering Number */ 179#define SPBFCR_RXTRG_MASK 0x07 /* Receive Buffer Data Triggering Number */
180/* QSPI on R-Car Gen2 */
181#define SPBFCR_TXTRG_1B 0x00 /* 31 bytes (1 byte available) */
182#define SPBFCR_TXTRG_32B 0x30 /* 0 byte (32 bytes available) */
183#define SPBFCR_RXTRG_1B 0x00 /* 1 byte (31 bytes available) */
184#define SPBFCR_RXTRG_32B 0x07 /* 32 bytes (0 byte available) */
185
186#define QSPI_BUFFER_SIZE 32u
180 187
181struct rspi_data { 188struct rspi_data {
182 void __iomem *addr; 189 void __iomem *addr;
@@ -366,6 +373,52 @@ static int qspi_set_config_register(struct rspi_data *rspi, int access_size)
366 return 0; 373 return 0;
367} 374}
368 375
376static void qspi_update(const struct rspi_data *rspi, u8 mask, u8 val, u8 reg)
377{
378 u8 data;
379
380 data = rspi_read8(rspi, reg);
381 data &= ~mask;
382 data |= (val & mask);
383 rspi_write8(rspi, data, reg);
384}
385
386static int qspi_set_send_trigger(struct rspi_data *rspi, unsigned int len)
387{
388 unsigned int n;
389
390 n = min(len, QSPI_BUFFER_SIZE);
391
392 if (len >= QSPI_BUFFER_SIZE) {
393 /* sets triggering number to 32 bytes */
394 qspi_update(rspi, SPBFCR_TXTRG_MASK,
395 SPBFCR_TXTRG_32B, QSPI_SPBFCR);
396 } else {
397 /* sets triggering number to 1 byte */
398 qspi_update(rspi, SPBFCR_TXTRG_MASK,
399 SPBFCR_TXTRG_1B, QSPI_SPBFCR);
400 }
401
402 return n;
403}
404
405static void qspi_set_receive_trigger(struct rspi_data *rspi, unsigned int len)
406{
407 unsigned int n;
408
409 n = min(len, QSPI_BUFFER_SIZE);
410
411 if (len >= QSPI_BUFFER_SIZE) {
412 /* sets triggering number to 32 bytes */
413 qspi_update(rspi, SPBFCR_RXTRG_MASK,
414 SPBFCR_RXTRG_32B, QSPI_SPBFCR);
415 } else {
416 /* sets triggering number to 1 byte */
417 qspi_update(rspi, SPBFCR_RXTRG_MASK,
418 SPBFCR_RXTRG_1B, QSPI_SPBFCR);
419 }
420}
421
369#define set_config_register(spi, n) spi->ops->set_config_register(spi, n) 422#define set_config_register(spi, n) spi->ops->set_config_register(spi, n)
370 423
371static void rspi_enable_irq(const struct rspi_data *rspi, u8 enable) 424static void rspi_enable_irq(const struct rspi_data *rspi, u8 enable)
@@ -609,19 +662,29 @@ static bool rspi_can_dma(struct spi_master *master, struct spi_device *spi,
609 return __rspi_can_dma(rspi, xfer); 662 return __rspi_can_dma(rspi, xfer);
610} 663}
611 664
612static int rspi_common_transfer(struct rspi_data *rspi, 665static int rspi_dma_check_then_transfer(struct rspi_data *rspi,
613 struct spi_transfer *xfer) 666 struct spi_transfer *xfer)
614{ 667{
615 int ret;
616
617 if (rspi->master->can_dma && __rspi_can_dma(rspi, xfer)) { 668 if (rspi->master->can_dma && __rspi_can_dma(rspi, xfer)) {
618 /* rx_buf can be NULL on RSPI on SH in TX-only Mode */ 669 /* rx_buf can be NULL on RSPI on SH in TX-only Mode */
619 ret = rspi_dma_transfer(rspi, &xfer->tx_sg, 670 int ret = rspi_dma_transfer(rspi, &xfer->tx_sg,
620 xfer->rx_buf ? &xfer->rx_sg : NULL); 671 xfer->rx_buf ? &xfer->rx_sg : NULL);
621 if (ret != -EAGAIN) 672 if (ret != -EAGAIN)
622 return ret; 673 return 0;
623 } 674 }
624 675
676 return -EAGAIN;
677}
678
679static int rspi_common_transfer(struct rspi_data *rspi,
680 struct spi_transfer *xfer)
681{
682 int ret;
683
684 ret = rspi_dma_check_then_transfer(rspi, xfer);
685 if (ret != -EAGAIN)
686 return ret;
687
625 ret = rspi_pio_transfer(rspi, xfer->tx_buf, xfer->rx_buf, xfer->len); 688 ret = rspi_pio_transfer(rspi, xfer->tx_buf, xfer->rx_buf, xfer->len);
626 if (ret < 0) 689 if (ret < 0)
627 return ret; 690 return ret;
@@ -661,12 +724,59 @@ static int rspi_rz_transfer_one(struct spi_master *master,
661 return rspi_common_transfer(rspi, xfer); 724 return rspi_common_transfer(rspi, xfer);
662} 725}
663 726
727static int qspi_trigger_transfer_out_int(struct rspi_data *rspi, const u8 *tx,
728 u8 *rx, unsigned int len)
729{
730 int i, n, ret;
731 int error;
732
733 while (len > 0) {
734 n = qspi_set_send_trigger(rspi, len);
735 qspi_set_receive_trigger(rspi, len);
736 if (n == QSPI_BUFFER_SIZE) {
737 error = rspi_wait_for_tx_empty(rspi);
738 if (error < 0) {
739 dev_err(&rspi->master->dev, "transmit timeout\n");
740 return error;
741 }
742 for (i = 0; i < n; i++)
743 rspi_write_data(rspi, *tx++);
744
745 error = rspi_wait_for_rx_full(rspi);
746 if (error < 0) {
747 dev_err(&rspi->master->dev, "receive timeout\n");
748 return error;
749 }
750 for (i = 0; i < n; i++)
751 *rx++ = rspi_read_data(rspi);
752 } else {
753 ret = rspi_pio_transfer(rspi, tx, rx, n);
754 if (ret < 0)
755 return ret;
756 }
757 len -= n;
758 }
759
760 return 0;
761}
762
664static int qspi_transfer_out_in(struct rspi_data *rspi, 763static int qspi_transfer_out_in(struct rspi_data *rspi,
665 struct spi_transfer *xfer) 764 struct spi_transfer *xfer)
666{ 765{
766 int ret;
767
667 qspi_receive_init(rspi); 768 qspi_receive_init(rspi);
668 769
669 return rspi_common_transfer(rspi, xfer); 770 ret = rspi_dma_check_then_transfer(rspi, xfer);
771 if (ret != -EAGAIN)
772 return ret;
773
774 ret = qspi_trigger_transfer_out_int(rspi, xfer->tx_buf,
775 xfer->rx_buf, xfer->len);
776 if (ret < 0)
777 return ret;
778
779 return 0;
670} 780}
671 781
672static int qspi_transfer_out(struct rspi_data *rspi, struct spi_transfer *xfer) 782static int qspi_transfer_out(struct rspi_data *rspi, struct spi_transfer *xfer)
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index 9231c34b5a5c..b1c6731fbf27 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -324,7 +324,7 @@ static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
324 324
325 /* Acquire DMA channels */ 325 /* Acquire DMA channels */
326 sdd->rx_dma.ch = dma_request_slave_channel_compat(mask, filter, 326 sdd->rx_dma.ch = dma_request_slave_channel_compat(mask, filter,
327 (void *)sdd->rx_dma.dmach, dev, "rx"); 327 (void *)(long)sdd->rx_dma.dmach, dev, "rx");
328 if (!sdd->rx_dma.ch) { 328 if (!sdd->rx_dma.ch) {
329 dev_err(dev, "Failed to get RX DMA channel\n"); 329 dev_err(dev, "Failed to get RX DMA channel\n");
330 ret = -EBUSY; 330 ret = -EBUSY;
@@ -333,7 +333,7 @@ static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
333 spi->dma_rx = sdd->rx_dma.ch; 333 spi->dma_rx = sdd->rx_dma.ch;
334 334
335 sdd->tx_dma.ch = dma_request_slave_channel_compat(mask, filter, 335 sdd->tx_dma.ch = dma_request_slave_channel_compat(mask, filter,
336 (void *)sdd->tx_dma.dmach, dev, "tx"); 336 (void *)(long)sdd->tx_dma.dmach, dev, "tx");
337 if (!sdd->tx_dma.ch) { 337 if (!sdd->tx_dma.ch) {
338 dev_err(dev, "Failed to get TX DMA channel\n"); 338 dev_err(dev, "Failed to get TX DMA channel\n");
339 ret = -EBUSY; 339 ret = -EBUSY;
diff --git a/drivers/spi/spi-sc18is602.c b/drivers/spi/spi-sc18is602.c
index 5a56acf8a43e..36af4d48a700 100644
--- a/drivers/spi/spi-sc18is602.c
+++ b/drivers/spi/spi-sc18is602.c
@@ -286,7 +286,7 @@ static int sc18is602_probe(struct i2c_client *client,
286 hw->freq = SC18IS602_CLOCK; 286 hw->freq = SC18IS602_CLOCK;
287 break; 287 break;
288 } 288 }
289 master->bus_num = client->adapter->nr; 289 master->bus_num = np ? -1 : client->adapter->nr;
290 master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_LSB_FIRST; 290 master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_LSB_FIRST;
291 master->bits_per_word_mask = SPI_BPW_MASK(8); 291 master->bits_per_word_mask = SPI_BPW_MASK(8);
292 master->setup = sc18is602_setup; 292 master->setup = sc18is602_setup;
diff --git a/drivers/spi/spi-st-ssc4.c b/drivers/spi/spi-st-ssc4.c
index 2faeaa7b57a8..f17c0abe299f 100644
--- a/drivers/spi/spi-st-ssc4.c
+++ b/drivers/spi/spi-st-ssc4.c
@@ -482,7 +482,7 @@ static const struct dev_pm_ops spi_st_pm = {
482 SET_RUNTIME_PM_OPS(spi_st_runtime_suspend, spi_st_runtime_resume, NULL) 482 SET_RUNTIME_PM_OPS(spi_st_runtime_suspend, spi_st_runtime_resume, NULL)
483}; 483};
484 484
485static struct of_device_id stm_spi_match[] = { 485static const struct of_device_id stm_spi_match[] = {
486 { .compatible = "st,comms-ssc4-spi", }, 486 { .compatible = "st,comms-ssc4-spi", },
487 {}, 487 {},
488}; 488};
diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
index 884a716e50cb..5c0616870358 100644
--- a/drivers/spi/spi-ti-qspi.c
+++ b/drivers/spi/spi-ti-qspi.c
@@ -101,6 +101,7 @@ struct ti_qspi {
101#define QSPI_FLEN(n) ((n - 1) << 0) 101#define QSPI_FLEN(n) ((n - 1) << 0)
102 102
103/* STATUS REGISTER */ 103/* STATUS REGISTER */
104#define BUSY 0x01
104#define WC 0x02 105#define WC 0x02
105 106
106/* INTERRUPT REGISTER */ 107/* INTERRUPT REGISTER */
@@ -199,6 +200,21 @@ static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
199 ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG); 200 ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG);
200} 201}
201 202
203static inline u32 qspi_is_busy(struct ti_qspi *qspi)
204{
205 u32 stat;
206 unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;
207
208 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
209 while ((stat & BUSY) && time_after(timeout, jiffies)) {
210 cpu_relax();
211 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
212 }
213
214 WARN(stat & BUSY, "qspi busy\n");
215 return stat & BUSY;
216}
217
202static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t) 218static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t)
203{ 219{
204 int wlen, count; 220 int wlen, count;
@@ -211,6 +227,9 @@ static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t)
211 wlen = t->bits_per_word >> 3; /* in bytes */ 227 wlen = t->bits_per_word >> 3; /* in bytes */
212 228
213 while (count) { 229 while (count) {
230 if (qspi_is_busy(qspi))
231 return -EBUSY;
232
214 switch (wlen) { 233 switch (wlen) {
215 case 1: 234 case 1:
216 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n", 235 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n",
@@ -266,6 +285,9 @@ static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t)
266 285
267 while (count) { 286 while (count) {
268 dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc); 287 dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc);
288 if (qspi_is_busy(qspi))
289 return -EBUSY;
290
269 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG); 291 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
270 if (!wait_for_completion_timeout(&qspi->transfer_complete, 292 if (!wait_for_completion_timeout(&qspi->transfer_complete,
271 QSPI_COMPLETION_TIMEOUT)) { 293 QSPI_COMPLETION_TIMEOUT)) {
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index c64a3e59fce3..d5d7d2235163 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -16,7 +16,6 @@
16 */ 16 */
17 17
18#include <linux/kernel.h> 18#include <linux/kernel.h>
19#include <linux/kmod.h>
20#include <linux/device.h> 19#include <linux/device.h>
21#include <linux/init.h> 20#include <linux/init.h>
22#include <linux/cache.h> 21#include <linux/cache.h>
@@ -129,125 +128,11 @@ static int spi_uevent(struct device *dev, struct kobj_uevent_env *env)
129 return 0; 128 return 0;
130} 129}
131 130
132#ifdef CONFIG_PM_SLEEP
133static int spi_legacy_suspend(struct device *dev, pm_message_t message)
134{
135 int value = 0;
136 struct spi_driver *drv = to_spi_driver(dev->driver);
137
138 /* suspend will stop irqs and dma; no more i/o */
139 if (drv) {
140 if (drv->suspend)
141 value = drv->suspend(to_spi_device(dev), message);
142 else
143 dev_dbg(dev, "... can't suspend\n");
144 }
145 return value;
146}
147
148static int spi_legacy_resume(struct device *dev)
149{
150 int value = 0;
151 struct spi_driver *drv = to_spi_driver(dev->driver);
152
153 /* resume may restart the i/o queue */
154 if (drv) {
155 if (drv->resume)
156 value = drv->resume(to_spi_device(dev));
157 else
158 dev_dbg(dev, "... can't resume\n");
159 }
160 return value;
161}
162
163static int spi_pm_suspend(struct device *dev)
164{
165 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL;
166
167 if (pm)
168 return pm_generic_suspend(dev);
169 else
170 return spi_legacy_suspend(dev, PMSG_SUSPEND);
171}
172
173static int spi_pm_resume(struct device *dev)
174{
175 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL;
176
177 if (pm)
178 return pm_generic_resume(dev);
179 else
180 return spi_legacy_resume(dev);
181}
182
183static int spi_pm_freeze(struct device *dev)
184{
185 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL;
186
187 if (pm)
188 return pm_generic_freeze(dev);
189 else
190 return spi_legacy_suspend(dev, PMSG_FREEZE);
191}
192
193static int spi_pm_thaw(struct device *dev)
194{
195 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL;
196
197 if (pm)
198 return pm_generic_thaw(dev);
199 else
200 return spi_legacy_resume(dev);
201}
202
203static int spi_pm_poweroff(struct device *dev)
204{
205 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL;
206
207 if (pm)
208 return pm_generic_poweroff(dev);
209 else
210 return spi_legacy_suspend(dev, PMSG_HIBERNATE);
211}
212
213static int spi_pm_restore(struct device *dev)
214{
215 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL;
216
217 if (pm)
218 return pm_generic_restore(dev);
219 else
220 return spi_legacy_resume(dev);
221}
222#else
223#define spi_pm_suspend NULL
224#define spi_pm_resume NULL
225#define spi_pm_freeze NULL
226#define spi_pm_thaw NULL
227#define spi_pm_poweroff NULL
228#define spi_pm_restore NULL
229#endif
230
231static const struct dev_pm_ops spi_pm = {
232 .suspend = spi_pm_suspend,
233 .resume = spi_pm_resume,
234 .freeze = spi_pm_freeze,
235 .thaw = spi_pm_thaw,
236 .poweroff = spi_pm_poweroff,
237 .restore = spi_pm_restore,
238 SET_RUNTIME_PM_OPS(
239 pm_generic_runtime_suspend,
240 pm_generic_runtime_resume,
241 NULL
242 )
243};
244
245struct bus_type spi_bus_type = { 131struct bus_type spi_bus_type = {
246 .name = "spi", 132 .name = "spi",
247 .dev_groups = spi_dev_groups, 133 .dev_groups = spi_dev_groups,
248 .match = spi_match_device, 134 .match = spi_match_device,
249 .uevent = spi_uevent, 135 .uevent = spi_uevent,
250 .pm = &spi_pm,
251}; 136};
252EXPORT_SYMBOL_GPL(spi_bus_type); 137EXPORT_SYMBOL_GPL(spi_bus_type);
253 138
@@ -851,6 +736,9 @@ out:
851 if (msg->status == -EINPROGRESS) 736 if (msg->status == -EINPROGRESS)
852 msg->status = ret; 737 msg->status = ret;
853 738
739 if (msg->status && master->handle_err)
740 master->handle_err(master, msg);
741
854 spi_finalize_current_message(master); 742 spi_finalize_current_message(master);
855 743
856 return ret; 744 return ret;
@@ -1105,13 +993,14 @@ void spi_finalize_current_message(struct spi_master *master)
1105 "failed to unprepare message: %d\n", ret); 993 "failed to unprepare message: %d\n", ret);
1106 } 994 }
1107 } 995 }
996
997 trace_spi_message_done(mesg);
998
1108 master->cur_msg_prepared = false; 999 master->cur_msg_prepared = false;
1109 1000
1110 mesg->state = NULL; 1001 mesg->state = NULL;
1111 if (mesg->complete) 1002 if (mesg->complete)
1112 mesg->complete(mesg->context); 1003 mesg->complete(mesg->context);
1113
1114 trace_spi_message_done(mesg);
1115} 1004}
1116EXPORT_SYMBOL_GPL(spi_finalize_current_message); 1005EXPORT_SYMBOL_GPL(spi_finalize_current_message);
1117 1006
@@ -1359,7 +1248,6 @@ of_register_spi_device(struct spi_master *master, struct device_node *nc)
1359 spi->dev.of_node = nc; 1248 spi->dev.of_node = nc;
1360 1249
1361 /* Register the new device */ 1250 /* Register the new device */
1362 request_module("%s%s", SPI_MODULE_PREFIX, spi->modalias);
1363 rc = spi_add_device(spi); 1251 rc = spi_add_device(spi);
1364 if (rc) { 1252 if (rc) {
1365 dev_err(&master->dev, "spi_device register error %s\n", 1253 dev_err(&master->dev, "spi_device register error %s\n",
@@ -1893,6 +1781,8 @@ int spi_setup(struct spi_device *spi)
1893 if (!spi->max_speed_hz) 1781 if (!spi->max_speed_hz)
1894 spi->max_speed_hz = spi->master->max_speed_hz; 1782 spi->max_speed_hz = spi->master->max_speed_hz;
1895 1783
1784 spi_set_cs(spi, false);
1785
1896 if (spi->master->setup) 1786 if (spi->master->setup)
1897 status = spi->master->setup(spi); 1787 status = spi->master->setup(spi);
1898 1788
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-04 22:35:09 -0500