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-rw-r--r--drivers/spi/Kconfig17
-rw-r--r--drivers/spi/Makefile2
-rw-r--r--drivers/spi/amba-pl022.c250
-rw-r--r--drivers/spi/davinci_spi.c12
-rw-r--r--drivers/spi/ep93xx_spi.c938
-rw-r--r--drivers/spi/mpc512x_psc_spi.c576
-rw-r--r--drivers/spi/omap2_mcspi.c153
-rw-r--r--drivers/spi/spi_bitbang_txrx.h93
-rw-r--r--drivers/spi/spi_butterfly.c3
-rw-r--r--drivers/spi/spi_gpio.c3
-rw-r--r--drivers/spi/spi_lm70llp.c3
-rw-r--r--drivers/spi/spi_mpc8xxx.c110
-rw-r--r--drivers/spi/spi_s3c24xx_gpio.c3
-rw-r--r--drivers/spi/spi_sh_sci.c3
-rw-r--r--drivers/spi/xilinx_spi_of.c8
15 files changed, 2028 insertions, 146 deletions
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index f950b6316949..91c2f4f3af10 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -117,6 +117,16 @@ config SPI_DAVINCI
117 help 117 help
118 SPI master controller for DaVinci and DA8xx SPI modules. 118 SPI master controller for DaVinci and DA8xx SPI modules.
119 119
120config SPI_EP93XX
121 tristate "Cirrus Logic EP93xx SPI controller"
122 depends on ARCH_EP93XX
123 help
124 This enables using the Cirrus EP93xx SPI controller in master
125 mode.
126
127 To compile this driver as a module, choose M here. The module will be
128 called ep93xx_spi.
129
120config SPI_GPIO 130config SPI_GPIO
121 tristate "GPIO-based bitbanging SPI Master" 131 tristate "GPIO-based bitbanging SPI Master"
122 depends on GENERIC_GPIO 132 depends on GENERIC_GPIO
@@ -165,6 +175,13 @@ config SPI_MPC52xx_PSC
165 This enables using the Freescale MPC52xx Programmable Serial 175 This enables using the Freescale MPC52xx Programmable Serial
166 Controller in master SPI mode. 176 Controller in master SPI mode.
167 177
178config SPI_MPC512x_PSC
179 tristate "Freescale MPC512x PSC SPI controller"
180 depends on SPI_MASTER && PPC_MPC512x
181 help
182 This enables using the Freescale MPC5121 Programmable Serial
183 Controller in SPI master mode.
184
168config SPI_MPC8xxx 185config SPI_MPC8xxx
169 tristate "Freescale MPC8xxx SPI controller" 186 tristate "Freescale MPC8xxx SPI controller"
170 depends on FSL_SOC 187 depends on FSL_SOC
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index d7d0f89b797b..e9cbd18217a0 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_SPI_DAVINCI) += davinci_spi.o
21obj-$(CONFIG_SPI_DESIGNWARE) += dw_spi.o 21obj-$(CONFIG_SPI_DESIGNWARE) += dw_spi.o
22obj-$(CONFIG_SPI_DW_PCI) += dw_spi_pci.o 22obj-$(CONFIG_SPI_DW_PCI) += dw_spi_pci.o
23obj-$(CONFIG_SPI_DW_MMIO) += dw_spi_mmio.o 23obj-$(CONFIG_SPI_DW_MMIO) += dw_spi_mmio.o
24obj-$(CONFIG_SPI_EP93XX) += ep93xx_spi.o
24obj-$(CONFIG_SPI_GPIO) += spi_gpio.o 25obj-$(CONFIG_SPI_GPIO) += spi_gpio.o
25obj-$(CONFIG_SPI_IMX) += spi_imx.o 26obj-$(CONFIG_SPI_IMX) += spi_imx.o
26obj-$(CONFIG_SPI_LM70_LLP) += spi_lm70llp.o 27obj-$(CONFIG_SPI_LM70_LLP) += spi_lm70llp.o
@@ -30,6 +31,7 @@ obj-$(CONFIG_SPI_OMAP24XX) += omap2_mcspi.o
30obj-$(CONFIG_SPI_OMAP_100K) += omap_spi_100k.o 31obj-$(CONFIG_SPI_OMAP_100K) += omap_spi_100k.o
31obj-$(CONFIG_SPI_ORION) += orion_spi.o 32obj-$(CONFIG_SPI_ORION) += orion_spi.o
32obj-$(CONFIG_SPI_PL022) += amba-pl022.o 33obj-$(CONFIG_SPI_PL022) += amba-pl022.o
34obj-$(CONFIG_SPI_MPC512x_PSC) += mpc512x_psc_spi.o
33obj-$(CONFIG_SPI_MPC52xx_PSC) += mpc52xx_psc_spi.o 35obj-$(CONFIG_SPI_MPC52xx_PSC) += mpc52xx_psc_spi.o
34obj-$(CONFIG_SPI_MPC52xx) += mpc52xx_spi.o 36obj-$(CONFIG_SPI_MPC52xx) += mpc52xx_spi.o
35obj-$(CONFIG_SPI_MPC8xxx) += spi_mpc8xxx.o 37obj-$(CONFIG_SPI_MPC8xxx) += spi_mpc8xxx.o
diff --git a/drivers/spi/amba-pl022.c b/drivers/spi/amba-pl022.c
index e9aeee16d922..f0a1418ce660 100644
--- a/drivers/spi/amba-pl022.c
+++ b/drivers/spi/amba-pl022.c
@@ -102,13 +102,21 @@
102/* 102/*
103 * SSP Control Register 0 - SSP_CR0 103 * SSP Control Register 0 - SSP_CR0
104 */ 104 */
105#define SSP_CR0_MASK_DSS (0x1FUL << 0) 105#define SSP_CR0_MASK_DSS (0x0FUL << 0)
106#define SSP_CR0_MASK_HALFDUP (0x1UL << 5) 106#define SSP_CR0_MASK_FRF (0x3UL << 4)
107#define SSP_CR0_MASK_SPO (0x1UL << 6) 107#define SSP_CR0_MASK_SPO (0x1UL << 6)
108#define SSP_CR0_MASK_SPH (0x1UL << 7) 108#define SSP_CR0_MASK_SPH (0x1UL << 7)
109#define SSP_CR0_MASK_SCR (0xFFUL << 8) 109#define SSP_CR0_MASK_SCR (0xFFUL << 8)
110#define SSP_CR0_MASK_CSS (0x1FUL << 16) 110
111#define SSP_CR0_MASK_FRF (0x3UL << 21) 111/*
112 * The ST version of this block moves som bits
113 * in SSP_CR0 and extends it to 32 bits
114 */
115#define SSP_CR0_MASK_DSS_ST (0x1FUL << 0)
116#define SSP_CR0_MASK_HALFDUP_ST (0x1UL << 5)
117#define SSP_CR0_MASK_CSS_ST (0x1FUL << 16)
118#define SSP_CR0_MASK_FRF_ST (0x3UL << 21)
119
112 120
113/* 121/*
114 * SSP Control Register 0 - SSP_CR1 122 * SSP Control Register 0 - SSP_CR1
@@ -117,16 +125,18 @@
117#define SSP_CR1_MASK_SSE (0x1UL << 1) 125#define SSP_CR1_MASK_SSE (0x1UL << 1)
118#define SSP_CR1_MASK_MS (0x1UL << 2) 126#define SSP_CR1_MASK_MS (0x1UL << 2)
119#define SSP_CR1_MASK_SOD (0x1UL << 3) 127#define SSP_CR1_MASK_SOD (0x1UL << 3)
120#define SSP_CR1_MASK_RENDN (0x1UL << 4)
121#define SSP_CR1_MASK_TENDN (0x1UL << 5)
122#define SSP_CR1_MASK_MWAIT (0x1UL << 6)
123#define SSP_CR1_MASK_RXIFLSEL (0x7UL << 7)
124#define SSP_CR1_MASK_TXIFLSEL (0x7UL << 10)
125 128
126/* 129/*
127 * SSP Data Register - SSP_DR 130 * The ST version of this block adds some bits
131 * in SSP_CR1
128 */ 132 */
129#define SSP_DR_MASK_DATA 0xFFFFFFFF 133#define SSP_CR1_MASK_RENDN_ST (0x1UL << 4)
134#define SSP_CR1_MASK_TENDN_ST (0x1UL << 5)
135#define SSP_CR1_MASK_MWAIT_ST (0x1UL << 6)
136#define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7)
137#define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10)
138/* This one is only in the PL023 variant */
139#define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13)
130 140
131/* 141/*
132 * SSP Status Register - SSP_SR 142 * SSP Status Register - SSP_SR
@@ -134,7 +144,7 @@
134#define SSP_SR_MASK_TFE (0x1UL << 0) /* Transmit FIFO empty */ 144#define SSP_SR_MASK_TFE (0x1UL << 0) /* Transmit FIFO empty */
135#define SSP_SR_MASK_TNF (0x1UL << 1) /* Transmit FIFO not full */ 145#define SSP_SR_MASK_TNF (0x1UL << 1) /* Transmit FIFO not full */
136#define SSP_SR_MASK_RNE (0x1UL << 2) /* Receive FIFO not empty */ 146#define SSP_SR_MASK_RNE (0x1UL << 2) /* Receive FIFO not empty */
137#define SSP_SR_MASK_RFF (0x1UL << 3) /* Receive FIFO full */ 147#define SSP_SR_MASK_RFF (0x1UL << 3) /* Receive FIFO full */
138#define SSP_SR_MASK_BSY (0x1UL << 4) /* Busy Flag */ 148#define SSP_SR_MASK_BSY (0x1UL << 4) /* Busy Flag */
139 149
140/* 150/*
@@ -227,7 +237,7 @@
227/* 237/*
228 * SSP Test Data Register - SSP_TDR 238 * SSP Test Data Register - SSP_TDR
229 */ 239 */
230#define TDR_MASK_TESTDATA (0xFFFFFFFF) 240#define TDR_MASK_TESTDATA (0xFFFFFFFF)
231 241
232/* 242/*
233 * Message State 243 * Message State
@@ -235,33 +245,33 @@
235 * hold a single state value, that's why all this 245 * hold a single state value, that's why all this
236 * (void *) casting is done here. 246 * (void *) casting is done here.
237 */ 247 */
238#define STATE_START ((void *) 0) 248#define STATE_START ((void *) 0)
239#define STATE_RUNNING ((void *) 1) 249#define STATE_RUNNING ((void *) 1)
240#define STATE_DONE ((void *) 2) 250#define STATE_DONE ((void *) 2)
241#define STATE_ERROR ((void *) -1) 251#define STATE_ERROR ((void *) -1)
242 252
243/* 253/*
244 * Queue State 254 * Queue State
245 */ 255 */
246#define QUEUE_RUNNING (0) 256#define QUEUE_RUNNING (0)
247#define QUEUE_STOPPED (1) 257#define QUEUE_STOPPED (1)
248/* 258/*
249 * SSP State - Whether Enabled or Disabled 259 * SSP State - Whether Enabled or Disabled
250 */ 260 */
251#define SSP_DISABLED (0) 261#define SSP_DISABLED (0)
252#define SSP_ENABLED (1) 262#define SSP_ENABLED (1)
253 263
254/* 264/*
255 * SSP DMA State - Whether DMA Enabled or Disabled 265 * SSP DMA State - Whether DMA Enabled or Disabled
256 */ 266 */
257#define SSP_DMA_DISABLED (0) 267#define SSP_DMA_DISABLED (0)
258#define SSP_DMA_ENABLED (1) 268#define SSP_DMA_ENABLED (1)
259 269
260/* 270/*
261 * SSP Clock Defaults 271 * SSP Clock Defaults
262 */ 272 */
263#define NMDK_SSP_DEFAULT_CLKRATE 0x2 273#define SSP_DEFAULT_CLKRATE 0x2
264#define NMDK_SSP_DEFAULT_PRESCALE 0x40 274#define SSP_DEFAULT_PRESCALE 0x40
265 275
266/* 276/*
267 * SSP Clock Parameter ranges 277 * SSP Clock Parameter ranges
@@ -307,16 +317,22 @@ enum ssp_writing {
307 * @fifodepth: depth of FIFOs (both) 317 * @fifodepth: depth of FIFOs (both)
308 * @max_bpw: maximum number of bits per word 318 * @max_bpw: maximum number of bits per word
309 * @unidir: supports unidirection transfers 319 * @unidir: supports unidirection transfers
320 * @extended_cr: 32 bit wide control register 0 with extra
321 * features and extra features in CR1 as found in the ST variants
322 * @pl023: supports a subset of the ST extensions called "PL023"
310 */ 323 */
311struct vendor_data { 324struct vendor_data {
312 int fifodepth; 325 int fifodepth;
313 int max_bpw; 326 int max_bpw;
314 bool unidir; 327 bool unidir;
328 bool extended_cr;
329 bool pl023;
315}; 330};
316 331
317/** 332/**
318 * struct pl022 - This is the private SSP driver data structure 333 * struct pl022 - This is the private SSP driver data structure
319 * @adev: AMBA device model hookup 334 * @adev: AMBA device model hookup
335 * @vendor: Vendor data for the IP block
320 * @phybase: The physical memory where the SSP device resides 336 * @phybase: The physical memory where the SSP device resides
321 * @virtbase: The virtual memory where the SSP is mapped 337 * @virtbase: The virtual memory where the SSP is mapped
322 * @master: SPI framework hookup 338 * @master: SPI framework hookup
@@ -369,7 +385,8 @@ struct pl022 {
369 385
370/** 386/**
371 * struct chip_data - To maintain runtime state of SSP for each client chip 387 * struct chip_data - To maintain runtime state of SSP for each client chip
372 * @cr0: Value of control register CR0 of SSP 388 * @cr0: Value of control register CR0 of SSP - on later ST variants this
389 * register is 32 bits wide rather than just 16
373 * @cr1: Value of control register CR1 of SSP 390 * @cr1: Value of control register CR1 of SSP
374 * @dmacr: Value of DMA control Register of SSP 391 * @dmacr: Value of DMA control Register of SSP
375 * @cpsr: Value of Clock prescale register 392 * @cpsr: Value of Clock prescale register
@@ -384,7 +401,7 @@ struct pl022 {
384 * This would be set according to the current message that would be served 401 * This would be set according to the current message that would be served
385 */ 402 */
386struct chip_data { 403struct chip_data {
387 u16 cr0; 404 u32 cr0;
388 u16 cr1; 405 u16 cr1;
389 u16 dmacr; 406 u16 dmacr;
390 u16 cpsr; 407 u16 cpsr;
@@ -517,7 +534,10 @@ static void restore_state(struct pl022 *pl022)
517{ 534{
518 struct chip_data *chip = pl022->cur_chip; 535 struct chip_data *chip = pl022->cur_chip;
519 536
520 writew(chip->cr0, SSP_CR0(pl022->virtbase)); 537 if (pl022->vendor->extended_cr)
538 writel(chip->cr0, SSP_CR0(pl022->virtbase));
539 else
540 writew(chip->cr0, SSP_CR0(pl022->virtbase));
521 writew(chip->cr1, SSP_CR1(pl022->virtbase)); 541 writew(chip->cr1, SSP_CR1(pl022->virtbase));
522 writew(chip->dmacr, SSP_DMACR(pl022->virtbase)); 542 writew(chip->dmacr, SSP_DMACR(pl022->virtbase));
523 writew(chip->cpsr, SSP_CPSR(pl022->virtbase)); 543 writew(chip->cpsr, SSP_CPSR(pl022->virtbase));
@@ -525,38 +545,70 @@ static void restore_state(struct pl022 *pl022)
525 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 545 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
526} 546}
527 547
528/**
529 * load_ssp_default_config - Load default configuration for SSP
530 * @pl022: SSP driver private data structure
531 */
532
533/* 548/*
534 * Default SSP Register Values 549 * Default SSP Register Values
535 */ 550 */
536#define DEFAULT_SSP_REG_CR0 ( \ 551#define DEFAULT_SSP_REG_CR0 ( \
537 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \ 552 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \
538 GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP, 5) | \ 553 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \
539 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 554 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
540 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 555 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
541 GEN_MASK_BITS(NMDK_SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \ 556 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
542 GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS, 16) | \ 557)
543 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 21) \ 558
559/* ST versions have slightly different bit layout */
560#define DEFAULT_SSP_REG_CR0_ST ( \
561 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \
562 GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \
563 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
564 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
565 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \
566 GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16) | \
567 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \
568)
569
570/* The PL023 version is slightly different again */
571#define DEFAULT_SSP_REG_CR0_ST_PL023 ( \
572 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \
573 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
574 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
575 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
544) 576)
545 577
546#define DEFAULT_SSP_REG_CR1 ( \ 578#define DEFAULT_SSP_REG_CR1 ( \
547 GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \ 579 GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \
548 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ 580 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
549 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ 581 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
582 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \
583)
584
585/* ST versions extend this register to use all 16 bits */
586#define DEFAULT_SSP_REG_CR1_ST ( \
587 DEFAULT_SSP_REG_CR1 | \
588 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
589 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
590 GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\
591 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
592 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \
593)
594
595/*
596 * The PL023 variant has further differences: no loopback mode, no microwire
597 * support, and a new clock feedback delay setting.
598 */
599#define DEFAULT_SSP_REG_CR1_ST_PL023 ( \
600 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
601 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
550 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \ 602 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \
551 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN, 4) | \ 603 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
552 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN, 5) | \ 604 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
553 GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT, 6) |\ 605 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
554 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL, 7) | \ 606 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \
555 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL, 10) \ 607 GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \
556) 608)
557 609
558#define DEFAULT_SSP_REG_CPSR ( \ 610#define DEFAULT_SSP_REG_CPSR ( \
559 GEN_MASK_BITS(NMDK_SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \ 611 GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \
560) 612)
561 613
562#define DEFAULT_SSP_REG_DMACR (\ 614#define DEFAULT_SSP_REG_DMACR (\
@@ -564,11 +616,22 @@ static void restore_state(struct pl022 *pl022)
564 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \ 616 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \
565) 617)
566 618
567 619/**
620 * load_ssp_default_config - Load default configuration for SSP
621 * @pl022: SSP driver private data structure
622 */
568static void load_ssp_default_config(struct pl022 *pl022) 623static void load_ssp_default_config(struct pl022 *pl022)
569{ 624{
570 writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase)); 625 if (pl022->vendor->pl023) {
571 writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase)); 626 writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase));
627 writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase));
628 } else if (pl022->vendor->extended_cr) {
629 writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase));
630 writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase));
631 } else {
632 writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase));
633 writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase));
634 }
572 writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase)); 635 writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase));
573 writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase)); 636 writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase));
574 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); 637 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
@@ -1008,7 +1071,7 @@ static void do_polling_transfer(void *data)
1008 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), 1071 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
1009 SSP_CR1(pl022->virtbase)); 1072 SSP_CR1(pl022->virtbase));
1010 1073
1011 dev_dbg(&pl022->adev->dev, "POLLING TRANSFER ONGOING ... \n"); 1074 dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n");
1012 /* FIXME: insert a timeout so we don't hang here indefinately */ 1075 /* FIXME: insert a timeout so we don't hang here indefinately */
1013 while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) 1076 while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end)
1014 readwriter(pl022); 1077 readwriter(pl022);
@@ -1148,7 +1211,6 @@ static int stop_queue(struct pl022 *pl022)
1148 * A wait_queue on the pl022->busy could be used, but then the common 1211 * A wait_queue on the pl022->busy could be used, but then the common
1149 * execution path (pump_messages) would be required to call wake_up or 1212 * execution path (pump_messages) would be required to call wake_up or
1150 * friends on every SPI message. Do this instead */ 1213 * friends on every SPI message. Do this instead */
1151 pl022->run = QUEUE_STOPPED;
1152 while (!list_empty(&pl022->queue) && pl022->busy && limit--) { 1214 while (!list_empty(&pl022->queue) && pl022->busy && limit--) {
1153 spin_unlock_irqrestore(&pl022->queue_lock, flags); 1215 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1154 msleep(10); 1216 msleep(10);
@@ -1157,6 +1219,7 @@ static int stop_queue(struct pl022 *pl022)
1157 1219
1158 if (!list_empty(&pl022->queue) || pl022->busy) 1220 if (!list_empty(&pl022->queue) || pl022->busy)
1159 status = -EBUSY; 1221 status = -EBUSY;
1222 else pl022->run = QUEUE_STOPPED;
1160 1223
1161 spin_unlock_irqrestore(&pl022->queue_lock, flags); 1224 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1162 1225
@@ -1280,11 +1343,21 @@ static int verify_controller_parameters(struct pl022 *pl022,
1280 "Wait State is configured incorrectly\n"); 1343 "Wait State is configured incorrectly\n");
1281 return -EINVAL; 1344 return -EINVAL;
1282 } 1345 }
1283 if ((chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) 1346 /* Half duplex is only available in the ST Micro version */
1284 && (chip_info->duplex != 1347 if (pl022->vendor->extended_cr) {
1285 SSP_MICROWIRE_CHANNEL_HALF_DUPLEX)) { 1348 if ((chip_info->duplex !=
1286 dev_err(chip_info->dev, 1349 SSP_MICROWIRE_CHANNEL_FULL_DUPLEX)
1287 "DUPLEX is configured incorrectly\n"); 1350 && (chip_info->duplex !=
1351 SSP_MICROWIRE_CHANNEL_HALF_DUPLEX))
1352 dev_err(chip_info->dev,
1353 "Microwire duplex mode is configured incorrectly\n");
1354 return -EINVAL;
1355 } else {
1356 if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX)
1357 dev_err(chip_info->dev,
1358 "Microwire half duplex mode requested,"
1359 " but this is only available in the"
1360 " ST version of PL022\n");
1288 return -EINVAL; 1361 return -EINVAL;
1289 } 1362 }
1290 } 1363 }
@@ -1581,22 +1654,49 @@ static int pl022_setup(struct spi_device *spi)
1581 1654
1582 chip->cpsr = chip_info->clk_freq.cpsdvsr; 1655 chip->cpsr = chip_info->clk_freq.cpsdvsr;
1583 1656
1584 SSP_WRITE_BITS(chip->cr0, chip_info->data_size, SSP_CR0_MASK_DSS, 0); 1657 /* Special setup for the ST micro extended control registers */
1585 SSP_WRITE_BITS(chip->cr0, chip_info->duplex, SSP_CR0_MASK_HALFDUP, 5); 1658 if (pl022->vendor->extended_cr) {
1659 if (pl022->vendor->pl023) {
1660 /* These bits are only in the PL023 */
1661 SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay,
1662 SSP_CR1_MASK_FBCLKDEL_ST, 13);
1663 } else {
1664 /* These bits are in the PL022 but not PL023 */
1665 SSP_WRITE_BITS(chip->cr0, chip_info->duplex,
1666 SSP_CR0_MASK_HALFDUP_ST, 5);
1667 SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len,
1668 SSP_CR0_MASK_CSS_ST, 16);
1669 SSP_WRITE_BITS(chip->cr0, chip_info->iface,
1670 SSP_CR0_MASK_FRF_ST, 21);
1671 SSP_WRITE_BITS(chip->cr1, chip_info->wait_state,
1672 SSP_CR1_MASK_MWAIT_ST, 6);
1673 }
1674 SSP_WRITE_BITS(chip->cr0, chip_info->data_size,
1675 SSP_CR0_MASK_DSS_ST, 0);
1676 SSP_WRITE_BITS(chip->cr1, chip_info->endian_rx,
1677 SSP_CR1_MASK_RENDN_ST, 4);
1678 SSP_WRITE_BITS(chip->cr1, chip_info->endian_tx,
1679 SSP_CR1_MASK_TENDN_ST, 5);
1680 SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig,
1681 SSP_CR1_MASK_RXIFLSEL_ST, 7);
1682 SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig,
1683 SSP_CR1_MASK_TXIFLSEL_ST, 10);
1684 } else {
1685 SSP_WRITE_BITS(chip->cr0, chip_info->data_size,
1686 SSP_CR0_MASK_DSS, 0);
1687 SSP_WRITE_BITS(chip->cr0, chip_info->iface,
1688 SSP_CR0_MASK_FRF, 4);
1689 }
1690 /* Stuff that is common for all versions */
1586 SSP_WRITE_BITS(chip->cr0, chip_info->clk_pol, SSP_CR0_MASK_SPO, 6); 1691 SSP_WRITE_BITS(chip->cr0, chip_info->clk_pol, SSP_CR0_MASK_SPO, 6);
1587 SSP_WRITE_BITS(chip->cr0, chip_info->clk_phase, SSP_CR0_MASK_SPH, 7); 1692 SSP_WRITE_BITS(chip->cr0, chip_info->clk_phase, SSP_CR0_MASK_SPH, 7);
1588 SSP_WRITE_BITS(chip->cr0, chip_info->clk_freq.scr, SSP_CR0_MASK_SCR, 8); 1693 SSP_WRITE_BITS(chip->cr0, chip_info->clk_freq.scr, SSP_CR0_MASK_SCR, 8);
1589 SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len, SSP_CR0_MASK_CSS, 16); 1694 /* Loopback is available on all versions except PL023 */
1590 SSP_WRITE_BITS(chip->cr0, chip_info->iface, SSP_CR0_MASK_FRF, 21); 1695 if (!pl022->vendor->pl023)
1591 SSP_WRITE_BITS(chip->cr1, chip_info->lbm, SSP_CR1_MASK_LBM, 0); 1696 SSP_WRITE_BITS(chip->cr1, chip_info->lbm, SSP_CR1_MASK_LBM, 0);
1592 SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1); 1697 SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1);
1593 SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2); 1698 SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2);
1594 SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD, 3); 1699 SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD, 3);
1595 SSP_WRITE_BITS(chip->cr1, chip_info->endian_rx, SSP_CR1_MASK_RENDN, 4);
1596 SSP_WRITE_BITS(chip->cr1, chip_info->endian_tx, SSP_CR1_MASK_TENDN, 5);
1597 SSP_WRITE_BITS(chip->cr1, chip_info->wait_state, SSP_CR1_MASK_MWAIT, 6);
1598 SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig, SSP_CR1_MASK_RXIFLSEL, 7);
1599 SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig, SSP_CR1_MASK_TXIFLSEL, 10);
1600 1700
1601 /* Save controller_state */ 1701 /* Save controller_state */
1602 spi_set_ctldata(spi, chip); 1702 spi_set_ctldata(spi, chip);
@@ -1809,6 +1909,8 @@ static struct vendor_data vendor_arm = {
1809 .fifodepth = 8, 1909 .fifodepth = 8,
1810 .max_bpw = 16, 1910 .max_bpw = 16,
1811 .unidir = false, 1911 .unidir = false,
1912 .extended_cr = false,
1913 .pl023 = false,
1812}; 1914};
1813 1915
1814 1916
@@ -1816,6 +1918,16 @@ static struct vendor_data vendor_st = {
1816 .fifodepth = 32, 1918 .fifodepth = 32,
1817 .max_bpw = 32, 1919 .max_bpw = 32,
1818 .unidir = false, 1920 .unidir = false,
1921 .extended_cr = true,
1922 .pl023 = false,
1923};
1924
1925static struct vendor_data vendor_st_pl023 = {
1926 .fifodepth = 32,
1927 .max_bpw = 32,
1928 .unidir = false,
1929 .extended_cr = true,
1930 .pl023 = true,
1819}; 1931};
1820 1932
1821static struct amba_id pl022_ids[] = { 1933static struct amba_id pl022_ids[] = {
@@ -1837,6 +1949,18 @@ static struct amba_id pl022_ids[] = {
1837 .mask = 0xffffffff, 1949 .mask = 0xffffffff,
1838 .data = &vendor_st, 1950 .data = &vendor_st,
1839 }, 1951 },
1952 {
1953 /*
1954 * ST-Ericsson derivative "PL023" (this is not
1955 * an official ARM number), this is a PL022 SSP block
1956 * stripped to SPI mode only, it has 32bit wide
1957 * and 32 locations deep TX/RX FIFO but no extended
1958 * CR0/CR1 register
1959 */
1960 .id = 0x00080023,
1961 .mask = 0xffffffff,
1962 .data = &vendor_st_pl023,
1963 },
1840 { 0, 0 }, 1964 { 0, 0 },
1841}; 1965};
1842 1966
diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c
index 95afb6b77395..b85090caf7cf 100644
--- a/drivers/spi/davinci_spi.c
+++ b/drivers/spi/davinci_spi.c
@@ -301,7 +301,7 @@ static int davinci_spi_setup_transfer(struct spi_device *spi,
301 struct davinci_spi *davinci_spi; 301 struct davinci_spi *davinci_spi;
302 struct davinci_spi_platform_data *pdata; 302 struct davinci_spi_platform_data *pdata;
303 u8 bits_per_word = 0; 303 u8 bits_per_word = 0;
304 u32 hz = 0, prescale; 304 u32 hz = 0, prescale = 0, clkspeed;
305 305
306 davinci_spi = spi_master_get_devdata(spi->master); 306 davinci_spi = spi_master_get_devdata(spi->master);
307 pdata = davinci_spi->pdata; 307 pdata = davinci_spi->pdata;
@@ -338,10 +338,16 @@ static int davinci_spi_setup_transfer(struct spi_device *spi,
338 set_fmt_bits(davinci_spi->base, bits_per_word & 0x1f, 338 set_fmt_bits(davinci_spi->base, bits_per_word & 0x1f,
339 spi->chip_select); 339 spi->chip_select);
340 340
341 prescale = ((clk_get_rate(davinci_spi->clk) / hz) - 1) & 0xff; 341 clkspeed = clk_get_rate(davinci_spi->clk);
342 if (hz > clkspeed / 2)
343 prescale = 1 << 8;
344 if (hz < clkspeed / 256)
345 prescale = 255 << 8;
346 if (!prescale)
347 prescale = ((clkspeed / hz - 1) << 8) & 0x0000ff00;
342 348
343 clear_fmt_bits(davinci_spi->base, 0x0000ff00, spi->chip_select); 349 clear_fmt_bits(davinci_spi->base, 0x0000ff00, spi->chip_select);
344 set_fmt_bits(davinci_spi->base, prescale << 8, spi->chip_select); 350 set_fmt_bits(davinci_spi->base, prescale, spi->chip_select);
345 351
346 return 0; 352 return 0;
347} 353}
diff --git a/drivers/spi/ep93xx_spi.c b/drivers/spi/ep93xx_spi.c
new file mode 100644
index 000000000000..0ba35df9a6df
--- /dev/null
+++ b/drivers/spi/ep93xx_spi.c
@@ -0,0 +1,938 @@
1/*
2 * Driver for Cirrus Logic EP93xx SPI controller.
3 *
4 * Copyright (c) 2010 Mika Westerberg
5 *
6 * Explicit FIFO handling code was inspired by amba-pl022 driver.
7 *
8 * Chip select support using other than built-in GPIOs by H. Hartley Sweeten.
9 *
10 * For more information about the SPI controller see documentation on Cirrus
11 * Logic web site:
12 * http://www.cirrus.com/en/pubs/manual/EP93xx_Users_Guide_UM1.pdf
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19#include <linux/io.h>
20#include <linux/clk.h>
21#include <linux/err.h>
22#include <linux/delay.h>
23#include <linux/device.h>
24#include <linux/bitops.h>
25#include <linux/interrupt.h>
26#include <linux/platform_device.h>
27#include <linux/workqueue.h>
28#include <linux/sched.h>
29#include <linux/spi/spi.h>
30
31#include <mach/ep93xx_spi.h>
32
33#define SSPCR0 0x0000
34#define SSPCR0_MODE_SHIFT 6
35#define SSPCR0_SCR_SHIFT 8
36
37#define SSPCR1 0x0004
38#define SSPCR1_RIE BIT(0)
39#define SSPCR1_TIE BIT(1)
40#define SSPCR1_RORIE BIT(2)
41#define SSPCR1_LBM BIT(3)
42#define SSPCR1_SSE BIT(4)
43#define SSPCR1_MS BIT(5)
44#define SSPCR1_SOD BIT(6)
45
46#define SSPDR 0x0008
47
48#define SSPSR 0x000c
49#define SSPSR_TFE BIT(0)
50#define SSPSR_TNF BIT(1)
51#define SSPSR_RNE BIT(2)
52#define SSPSR_RFF BIT(3)
53#define SSPSR_BSY BIT(4)
54#define SSPCPSR 0x0010
55
56#define SSPIIR 0x0014
57#define SSPIIR_RIS BIT(0)
58#define SSPIIR_TIS BIT(1)
59#define SSPIIR_RORIS BIT(2)
60#define SSPICR SSPIIR
61
62/* timeout in milliseconds */
63#define SPI_TIMEOUT 5
64/* maximum depth of RX/TX FIFO */
65#define SPI_FIFO_SIZE 8
66
67/**
68 * struct ep93xx_spi - EP93xx SPI controller structure
69 * @lock: spinlock that protects concurrent accesses to fields @running,
70 * @current_msg and @msg_queue
71 * @pdev: pointer to platform device
72 * @clk: clock for the controller
73 * @regs_base: pointer to ioremap()'d registers
74 * @irq: IRQ number used by the driver
75 * @min_rate: minimum clock rate (in Hz) supported by the controller
76 * @max_rate: maximum clock rate (in Hz) supported by the controller
77 * @running: is the queue running
78 * @wq: workqueue used by the driver
79 * @msg_work: work that is queued for the driver
80 * @wait: wait here until given transfer is completed
81 * @msg_queue: queue for the messages
82 * @current_msg: message that is currently processed (or %NULL if none)
83 * @tx: current byte in transfer to transmit
84 * @rx: current byte in transfer to receive
85 * @fifo_level: how full is FIFO (%0..%SPI_FIFO_SIZE - %1). Receiving one
86 * frame decreases this level and sending one frame increases it.
87 *
88 * This structure holds EP93xx SPI controller specific information. When
89 * @running is %true, driver accepts transfer requests from protocol drivers.
90 * @current_msg is used to hold pointer to the message that is currently
91 * processed. If @current_msg is %NULL, it means that no processing is going
92 * on.
93 *
94 * Most of the fields are only written once and they can be accessed without
95 * taking the @lock. Fields that are accessed concurrently are: @current_msg,
96 * @running, and @msg_queue.
97 */
98struct ep93xx_spi {
99 spinlock_t lock;
100 const struct platform_device *pdev;
101 struct clk *clk;
102 void __iomem *regs_base;
103 int irq;
104 unsigned long min_rate;
105 unsigned long max_rate;
106 bool running;
107 struct workqueue_struct *wq;
108 struct work_struct msg_work;
109 struct completion wait;
110 struct list_head msg_queue;
111 struct spi_message *current_msg;
112 size_t tx;
113 size_t rx;
114 size_t fifo_level;
115};
116
117/**
118 * struct ep93xx_spi_chip - SPI device hardware settings
119 * @spi: back pointer to the SPI device
120 * @rate: max rate in hz this chip supports
121 * @div_cpsr: cpsr (pre-scaler) divider
122 * @div_scr: scr divider
123 * @dss: bits per word (4 - 16 bits)
124 * @ops: private chip operations
125 *
126 * This structure is used to store hardware register specific settings for each
127 * SPI device. Settings are written to hardware by function
128 * ep93xx_spi_chip_setup().
129 */
130struct ep93xx_spi_chip {
131 const struct spi_device *spi;
132 unsigned long rate;
133 u8 div_cpsr;
134 u8 div_scr;
135 u8 dss;
136 struct ep93xx_spi_chip_ops *ops;
137};
138
139/* converts bits per word to CR0.DSS value */
140#define bits_per_word_to_dss(bpw) ((bpw) - 1)
141
142static inline void
143ep93xx_spi_write_u8(const struct ep93xx_spi *espi, u16 reg, u8 value)
144{
145 __raw_writeb(value, espi->regs_base + reg);
146}
147
148static inline u8
149ep93xx_spi_read_u8(const struct ep93xx_spi *spi, u16 reg)
150{
151 return __raw_readb(spi->regs_base + reg);
152}
153
154static inline void
155ep93xx_spi_write_u16(const struct ep93xx_spi *espi, u16 reg, u16 value)
156{
157 __raw_writew(value, espi->regs_base + reg);
158}
159
160static inline u16
161ep93xx_spi_read_u16(const struct ep93xx_spi *spi, u16 reg)
162{
163 return __raw_readw(spi->regs_base + reg);
164}
165
166static int ep93xx_spi_enable(const struct ep93xx_spi *espi)
167{
168 u8 regval;
169 int err;
170
171 err = clk_enable(espi->clk);
172 if (err)
173 return err;
174
175 regval = ep93xx_spi_read_u8(espi, SSPCR1);
176 regval |= SSPCR1_SSE;
177 ep93xx_spi_write_u8(espi, SSPCR1, regval);
178
179 return 0;
180}
181
182static void ep93xx_spi_disable(const struct ep93xx_spi *espi)
183{
184 u8 regval;
185
186 regval = ep93xx_spi_read_u8(espi, SSPCR1);
187 regval &= ~SSPCR1_SSE;
188 ep93xx_spi_write_u8(espi, SSPCR1, regval);
189
190 clk_disable(espi->clk);
191}
192
193static void ep93xx_spi_enable_interrupts(const struct ep93xx_spi *espi)
194{
195 u8 regval;
196
197 regval = ep93xx_spi_read_u8(espi, SSPCR1);
198 regval |= (SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE);
199 ep93xx_spi_write_u8(espi, SSPCR1, regval);
200}
201
202static void ep93xx_spi_disable_interrupts(const struct ep93xx_spi *espi)
203{
204 u8 regval;
205
206 regval = ep93xx_spi_read_u8(espi, SSPCR1);
207 regval &= ~(SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE);
208 ep93xx_spi_write_u8(espi, SSPCR1, regval);
209}
210
211/**
212 * ep93xx_spi_calc_divisors() - calculates SPI clock divisors
213 * @espi: ep93xx SPI controller struct
214 * @chip: divisors are calculated for this chip
215 * @rate: desired SPI output clock rate
216 *
217 * Function calculates cpsr (clock pre-scaler) and scr divisors based on
218 * given @rate and places them to @chip->div_cpsr and @chip->div_scr. If,
219 * for some reason, divisors cannot be calculated nothing is stored and
220 * %-EINVAL is returned.
221 */
222static int ep93xx_spi_calc_divisors(const struct ep93xx_spi *espi,
223 struct ep93xx_spi_chip *chip,
224 unsigned long rate)
225{
226 unsigned long spi_clk_rate = clk_get_rate(espi->clk);
227 int cpsr, scr;
228
229 /*
230 * Make sure that max value is between values supported by the
231 * controller. Note that minimum value is already checked in
232 * ep93xx_spi_transfer().
233 */
234 rate = clamp(rate, espi->min_rate, espi->max_rate);
235
236 /*
237 * Calculate divisors so that we can get speed according the
238 * following formula:
239 * rate = spi_clock_rate / (cpsr * (1 + scr))
240 *
241 * cpsr must be even number and starts from 2, scr can be any number
242 * between 0 and 255.
243 */
244 for (cpsr = 2; cpsr <= 254; cpsr += 2) {
245 for (scr = 0; scr <= 255; scr++) {
246 if ((spi_clk_rate / (cpsr * (scr + 1))) <= rate) {
247 chip->div_scr = (u8)scr;
248 chip->div_cpsr = (u8)cpsr;
249 return 0;
250 }
251 }
252 }
253
254 return -EINVAL;
255}
256
257static void ep93xx_spi_cs_control(struct spi_device *spi, bool control)
258{
259 struct ep93xx_spi_chip *chip = spi_get_ctldata(spi);
260 int value = (spi->mode & SPI_CS_HIGH) ? control : !control;
261
262 if (chip->ops && chip->ops->cs_control)
263 chip->ops->cs_control(spi, value);
264}
265
266/**
267 * ep93xx_spi_setup() - setup an SPI device
268 * @spi: SPI device to setup
269 *
270 * This function sets up SPI device mode, speed etc. Can be called multiple
271 * times for a single device. Returns %0 in case of success, negative error in
272 * case of failure. When this function returns success, the device is
273 * deselected.
274 */
275static int ep93xx_spi_setup(struct spi_device *spi)
276{
277 struct ep93xx_spi *espi = spi_master_get_devdata(spi->master);
278 struct ep93xx_spi_chip *chip;
279
280 if (spi->bits_per_word < 4 || spi->bits_per_word > 16) {
281 dev_err(&espi->pdev->dev, "invalid bits per word %d\n",
282 spi->bits_per_word);
283 return -EINVAL;
284 }
285
286 chip = spi_get_ctldata(spi);
287 if (!chip) {
288 dev_dbg(&espi->pdev->dev, "initial setup for %s\n",
289 spi->modalias);
290
291 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
292 if (!chip)
293 return -ENOMEM;
294
295 chip->spi = spi;
296 chip->ops = spi->controller_data;
297
298 if (chip->ops && chip->ops->setup) {
299 int ret = chip->ops->setup(spi);
300 if (ret) {
301 kfree(chip);
302 return ret;
303 }
304 }
305
306 spi_set_ctldata(spi, chip);
307 }
308
309 if (spi->max_speed_hz != chip->rate) {
310 int err;
311
312 err = ep93xx_spi_calc_divisors(espi, chip, spi->max_speed_hz);
313 if (err != 0) {
314 spi_set_ctldata(spi, NULL);
315 kfree(chip);
316 return err;
317 }
318 chip->rate = spi->max_speed_hz;
319 }
320
321 chip->dss = bits_per_word_to_dss(spi->bits_per_word);
322
323 ep93xx_spi_cs_control(spi, false);
324 return 0;
325}
326
327/**
328 * ep93xx_spi_transfer() - queue message to be transferred
329 * @spi: target SPI device
330 * @msg: message to be transferred
331 *
332 * This function is called by SPI device drivers when they are going to transfer
333 * a new message. It simply puts the message in the queue and schedules
334 * workqueue to perform the actual transfer later on.
335 *
336 * Returns %0 on success and negative error in case of failure.
337 */
338static int ep93xx_spi_transfer(struct spi_device *spi, struct spi_message *msg)
339{
340 struct ep93xx_spi *espi = spi_master_get_devdata(spi->master);
341 struct spi_transfer *t;
342 unsigned long flags;
343
344 if (!msg || !msg->complete)
345 return -EINVAL;
346
347 /* first validate each transfer */
348 list_for_each_entry(t, &msg->transfers, transfer_list) {
349 if (t->bits_per_word) {
350 if (t->bits_per_word < 4 || t->bits_per_word > 16)
351 return -EINVAL;
352 }
353 if (t->speed_hz && t->speed_hz < espi->min_rate)
354 return -EINVAL;
355 }
356
357 /*
358 * Now that we own the message, let's initialize it so that it is
359 * suitable for us. We use @msg->status to signal whether there was
360 * error in transfer and @msg->state is used to hold pointer to the
361 * current transfer (or %NULL if no active current transfer).
362 */
363 msg->state = NULL;
364 msg->status = 0;
365 msg->actual_length = 0;
366
367 spin_lock_irqsave(&espi->lock, flags);
368 if (!espi->running) {
369 spin_unlock_irqrestore(&espi->lock, flags);
370 return -ESHUTDOWN;
371 }
372 list_add_tail(&msg->queue, &espi->msg_queue);
373 queue_work(espi->wq, &espi->msg_work);
374 spin_unlock_irqrestore(&espi->lock, flags);
375
376 return 0;
377}
378
379/**
380 * ep93xx_spi_cleanup() - cleans up master controller specific state
381 * @spi: SPI device to cleanup
382 *
383 * This function releases master controller specific state for given @spi
384 * device.
385 */
386static void ep93xx_spi_cleanup(struct spi_device *spi)
387{
388 struct ep93xx_spi_chip *chip;
389
390 chip = spi_get_ctldata(spi);
391 if (chip) {
392 if (chip->ops && chip->ops->cleanup)
393 chip->ops->cleanup(spi);
394 spi_set_ctldata(spi, NULL);
395 kfree(chip);
396 }
397}
398
399/**
400 * ep93xx_spi_chip_setup() - configures hardware according to given @chip
401 * @espi: ep93xx SPI controller struct
402 * @chip: chip specific settings
403 *
404 * This function sets up the actual hardware registers with settings given in
405 * @chip. Note that no validation is done so make sure that callers validate
406 * settings before calling this.
407 */
408static void ep93xx_spi_chip_setup(const struct ep93xx_spi *espi,
409 const struct ep93xx_spi_chip *chip)
410{
411 u16 cr0;
412
413 cr0 = chip->div_scr << SSPCR0_SCR_SHIFT;
414 cr0 |= (chip->spi->mode & (SPI_CPHA|SPI_CPOL)) << SSPCR0_MODE_SHIFT;
415 cr0 |= chip->dss;
416
417 dev_dbg(&espi->pdev->dev, "setup: mode %d, cpsr %d, scr %d, dss %d\n",
418 chip->spi->mode, chip->div_cpsr, chip->div_scr, chip->dss);
419 dev_dbg(&espi->pdev->dev, "setup: cr0 %#x", cr0);
420
421 ep93xx_spi_write_u8(espi, SSPCPSR, chip->div_cpsr);
422 ep93xx_spi_write_u16(espi, SSPCR0, cr0);
423}
424
425static inline int bits_per_word(const struct ep93xx_spi *espi)
426{
427 struct spi_message *msg = espi->current_msg;
428 struct spi_transfer *t = msg->state;
429
430 return t->bits_per_word ? t->bits_per_word : msg->spi->bits_per_word;
431}
432
433static void ep93xx_do_write(struct ep93xx_spi *espi, struct spi_transfer *t)
434{
435 if (bits_per_word(espi) > 8) {
436 u16 tx_val = 0;
437
438 if (t->tx_buf)
439 tx_val = ((u16 *)t->tx_buf)[espi->tx];
440 ep93xx_spi_write_u16(espi, SSPDR, tx_val);
441 espi->tx += sizeof(tx_val);
442 } else {
443 u8 tx_val = 0;
444
445 if (t->tx_buf)
446 tx_val = ((u8 *)t->tx_buf)[espi->tx];
447 ep93xx_spi_write_u8(espi, SSPDR, tx_val);
448 espi->tx += sizeof(tx_val);
449 }
450}
451
452static void ep93xx_do_read(struct ep93xx_spi *espi, struct spi_transfer *t)
453{
454 if (bits_per_word(espi) > 8) {
455 u16 rx_val;
456
457 rx_val = ep93xx_spi_read_u16(espi, SSPDR);
458 if (t->rx_buf)
459 ((u16 *)t->rx_buf)[espi->rx] = rx_val;
460 espi->rx += sizeof(rx_val);
461 } else {
462 u8 rx_val;
463
464 rx_val = ep93xx_spi_read_u8(espi, SSPDR);
465 if (t->rx_buf)
466 ((u8 *)t->rx_buf)[espi->rx] = rx_val;
467 espi->rx += sizeof(rx_val);
468 }
469}
470
471/**
472 * ep93xx_spi_read_write() - perform next RX/TX transfer
473 * @espi: ep93xx SPI controller struct
474 *
475 * This function transfers next bytes (or half-words) to/from RX/TX FIFOs. If
476 * called several times, the whole transfer will be completed. Returns
477 * %-EINPROGRESS when current transfer was not yet completed otherwise %0.
478 *
479 * When this function is finished, RX FIFO should be empty and TX FIFO should be
480 * full.
481 */
482static int ep93xx_spi_read_write(struct ep93xx_spi *espi)
483{
484 struct spi_message *msg = espi->current_msg;
485 struct spi_transfer *t = msg->state;
486
487 /* read as long as RX FIFO has frames in it */
488 while ((ep93xx_spi_read_u8(espi, SSPSR) & SSPSR_RNE)) {
489 ep93xx_do_read(espi, t);
490 espi->fifo_level--;
491 }
492
493 /* write as long as TX FIFO has room */
494 while (espi->fifo_level < SPI_FIFO_SIZE && espi->tx < t->len) {
495 ep93xx_do_write(espi, t);
496 espi->fifo_level++;
497 }
498
499 if (espi->rx == t->len) {
500 msg->actual_length += t->len;
501 return 0;
502 }
503
504 return -EINPROGRESS;
505}
506
507/**
508 * ep93xx_spi_process_transfer() - processes one SPI transfer
509 * @espi: ep93xx SPI controller struct
510 * @msg: current message
511 * @t: transfer to process
512 *
513 * This function processes one SPI transfer given in @t. Function waits until
514 * transfer is complete (may sleep) and updates @msg->status based on whether
515 * transfer was succesfully processed or not.
516 */
517static void ep93xx_spi_process_transfer(struct ep93xx_spi *espi,
518 struct spi_message *msg,
519 struct spi_transfer *t)
520{
521 struct ep93xx_spi_chip *chip = spi_get_ctldata(msg->spi);
522
523 msg->state = t;
524
525 /*
526 * Handle any transfer specific settings if needed. We use
527 * temporary chip settings here and restore original later when
528 * the transfer is finished.
529 */
530 if (t->speed_hz || t->bits_per_word) {
531 struct ep93xx_spi_chip tmp_chip = *chip;
532
533 if (t->speed_hz) {
534 int err;
535
536 err = ep93xx_spi_calc_divisors(espi, &tmp_chip,
537 t->speed_hz);
538 if (err) {
539 dev_err(&espi->pdev->dev,
540 "failed to adjust speed\n");
541 msg->status = err;
542 return;
543 }
544 }
545
546 if (t->bits_per_word)
547 tmp_chip.dss = bits_per_word_to_dss(t->bits_per_word);
548
549 /*
550 * Set up temporary new hw settings for this transfer.
551 */
552 ep93xx_spi_chip_setup(espi, &tmp_chip);
553 }
554
555 espi->rx = 0;
556 espi->tx = 0;
557
558 /*
559 * Now everything is set up for the current transfer. We prime the TX
560 * FIFO, enable interrupts, and wait for the transfer to complete.
561 */
562 if (ep93xx_spi_read_write(espi)) {
563 ep93xx_spi_enable_interrupts(espi);
564 wait_for_completion(&espi->wait);
565 }
566
567 /*
568 * In case of error during transmit, we bail out from processing
569 * the message.
570 */
571 if (msg->status)
572 return;
573
574 /*
575 * After this transfer is finished, perform any possible
576 * post-transfer actions requested by the protocol driver.
577 */
578 if (t->delay_usecs) {
579 set_current_state(TASK_UNINTERRUPTIBLE);
580 schedule_timeout(usecs_to_jiffies(t->delay_usecs));
581 }
582 if (t->cs_change) {
583 if (!list_is_last(&t->transfer_list, &msg->transfers)) {
584 /*
585 * In case protocol driver is asking us to drop the
586 * chipselect briefly, we let the scheduler to handle
587 * any "delay" here.
588 */
589 ep93xx_spi_cs_control(msg->spi, false);
590 cond_resched();
591 ep93xx_spi_cs_control(msg->spi, true);
592 }
593 }
594
595 if (t->speed_hz || t->bits_per_word)
596 ep93xx_spi_chip_setup(espi, chip);
597}
598
599/*
600 * ep93xx_spi_process_message() - process one SPI message
601 * @espi: ep93xx SPI controller struct
602 * @msg: message to process
603 *
604 * This function processes a single SPI message. We go through all transfers in
605 * the message and pass them to ep93xx_spi_process_transfer(). Chipselect is
606 * asserted during the whole message (unless per transfer cs_change is set).
607 *
608 * @msg->status contains %0 in case of success or negative error code in case of
609 * failure.
610 */
611static void ep93xx_spi_process_message(struct ep93xx_spi *espi,
612 struct spi_message *msg)
613{
614 unsigned long timeout;
615 struct spi_transfer *t;
616 int err;
617
618 /*
619 * Enable the SPI controller and its clock.
620 */
621 err = ep93xx_spi_enable(espi);
622 if (err) {
623 dev_err(&espi->pdev->dev, "failed to enable SPI controller\n");
624 msg->status = err;
625 return;
626 }
627
628 /*
629 * Just to be sure: flush any data from RX FIFO.
630 */
631 timeout = jiffies + msecs_to_jiffies(SPI_TIMEOUT);
632 while (ep93xx_spi_read_u16(espi, SSPSR) & SSPSR_RNE) {
633 if (time_after(jiffies, timeout)) {
634 dev_warn(&espi->pdev->dev,
635 "timeout while flushing RX FIFO\n");
636 msg->status = -ETIMEDOUT;
637 return;
638 }
639 ep93xx_spi_read_u16(espi, SSPDR);
640 }
641
642 /*
643 * We explicitly handle FIFO level. This way we don't have to check TX
644 * FIFO status using %SSPSR_TNF bit which may cause RX FIFO overruns.
645 */
646 espi->fifo_level = 0;
647
648 /*
649 * Update SPI controller registers according to spi device and assert
650 * the chipselect.
651 */
652 ep93xx_spi_chip_setup(espi, spi_get_ctldata(msg->spi));
653 ep93xx_spi_cs_control(msg->spi, true);
654
655 list_for_each_entry(t, &msg->transfers, transfer_list) {
656 ep93xx_spi_process_transfer(espi, msg, t);
657 if (msg->status)
658 break;
659 }
660
661 /*
662 * Now the whole message is transferred (or failed for some reason). We
663 * deselect the device and disable the SPI controller.
664 */
665 ep93xx_spi_cs_control(msg->spi, false);
666 ep93xx_spi_disable(espi);
667}
668
669#define work_to_espi(work) (container_of((work), struct ep93xx_spi, msg_work))
670
671/**
672 * ep93xx_spi_work() - EP93xx SPI workqueue worker function
673 * @work: work struct
674 *
675 * Workqueue worker function. This function is called when there are new
676 * SPI messages to be processed. Message is taken out from the queue and then
677 * passed to ep93xx_spi_process_message().
678 *
679 * After message is transferred, protocol driver is notified by calling
680 * @msg->complete(). In case of error, @msg->status is set to negative error
681 * number, otherwise it contains zero (and @msg->actual_length is updated).
682 */
683static void ep93xx_spi_work(struct work_struct *work)
684{
685 struct ep93xx_spi *espi = work_to_espi(work);
686 struct spi_message *msg;
687
688 spin_lock_irq(&espi->lock);
689 if (!espi->running || espi->current_msg ||
690 list_empty(&espi->msg_queue)) {
691 spin_unlock_irq(&espi->lock);
692 return;
693 }
694 msg = list_first_entry(&espi->msg_queue, struct spi_message, queue);
695 list_del_init(&msg->queue);
696 espi->current_msg = msg;
697 spin_unlock_irq(&espi->lock);
698
699 ep93xx_spi_process_message(espi, msg);
700
701 /*
702 * Update the current message and re-schedule ourselves if there are
703 * more messages in the queue.
704 */
705 spin_lock_irq(&espi->lock);
706 espi->current_msg = NULL;
707 if (espi->running && !list_empty(&espi->msg_queue))
708 queue_work(espi->wq, &espi->msg_work);
709 spin_unlock_irq(&espi->lock);
710
711 /* notify the protocol driver that we are done with this message */
712 msg->complete(msg->context);
713}
714
715static irqreturn_t ep93xx_spi_interrupt(int irq, void *dev_id)
716{
717 struct ep93xx_spi *espi = dev_id;
718 u8 irq_status = ep93xx_spi_read_u8(espi, SSPIIR);
719
720 /*
721 * If we got ROR (receive overrun) interrupt we know that something is
722 * wrong. Just abort the message.
723 */
724 if (unlikely(irq_status & SSPIIR_RORIS)) {
725 /* clear the overrun interrupt */
726 ep93xx_spi_write_u8(espi, SSPICR, 0);
727 dev_warn(&espi->pdev->dev,
728 "receive overrun, aborting the message\n");
729 espi->current_msg->status = -EIO;
730 } else {
731 /*
732 * Interrupt is either RX (RIS) or TX (TIS). For both cases we
733 * simply execute next data transfer.
734 */
735 if (ep93xx_spi_read_write(espi)) {
736 /*
737 * In normal case, there still is some processing left
738 * for current transfer. Let's wait for the next
739 * interrupt then.
740 */
741 return IRQ_HANDLED;
742 }
743 }
744
745 /*
746 * Current transfer is finished, either with error or with success. In
747 * any case we disable interrupts and notify the worker to handle
748 * any post-processing of the message.
749 */
750 ep93xx_spi_disable_interrupts(espi);
751 complete(&espi->wait);
752 return IRQ_HANDLED;
753}
754
755static int __init ep93xx_spi_probe(struct platform_device *pdev)
756{
757 struct spi_master *master;
758 struct ep93xx_spi_info *info;
759 struct ep93xx_spi *espi;
760 struct resource *res;
761 int error;
762
763 info = pdev->dev.platform_data;
764
765 master = spi_alloc_master(&pdev->dev, sizeof(*espi));
766 if (!master) {
767 dev_err(&pdev->dev, "failed to allocate spi master\n");
768 return -ENOMEM;
769 }
770
771 master->setup = ep93xx_spi_setup;
772 master->transfer = ep93xx_spi_transfer;
773 master->cleanup = ep93xx_spi_cleanup;
774 master->bus_num = pdev->id;
775 master->num_chipselect = info->num_chipselect;
776 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
777
778 platform_set_drvdata(pdev, master);
779
780 espi = spi_master_get_devdata(master);
781
782 espi->clk = clk_get(&pdev->dev, NULL);
783 if (IS_ERR(espi->clk)) {
784 dev_err(&pdev->dev, "unable to get spi clock\n");
785 error = PTR_ERR(espi->clk);
786 goto fail_release_master;
787 }
788
789 spin_lock_init(&espi->lock);
790 init_completion(&espi->wait);
791
792 /*
793 * Calculate maximum and minimum supported clock rates
794 * for the controller.
795 */
796 espi->max_rate = clk_get_rate(espi->clk) / 2;
797 espi->min_rate = clk_get_rate(espi->clk) / (254 * 256);
798 espi->pdev = pdev;
799
800 espi->irq = platform_get_irq(pdev, 0);
801 if (espi->irq < 0) {
802 error = -EBUSY;
803 dev_err(&pdev->dev, "failed to get irq resources\n");
804 goto fail_put_clock;
805 }
806
807 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
808 if (!res) {
809 dev_err(&pdev->dev, "unable to get iomem resource\n");
810 error = -ENODEV;
811 goto fail_put_clock;
812 }
813
814 res = request_mem_region(res->start, resource_size(res), pdev->name);
815 if (!res) {
816 dev_err(&pdev->dev, "unable to request iomem resources\n");
817 error = -EBUSY;
818 goto fail_put_clock;
819 }
820
821 espi->regs_base = ioremap(res->start, resource_size(res));
822 if (!espi->regs_base) {
823 dev_err(&pdev->dev, "failed to map resources\n");
824 error = -ENODEV;
825 goto fail_free_mem;
826 }
827
828 error = request_irq(espi->irq, ep93xx_spi_interrupt, 0,
829 "ep93xx-spi", espi);
830 if (error) {
831 dev_err(&pdev->dev, "failed to request irq\n");
832 goto fail_unmap_regs;
833 }
834
835 espi->wq = create_singlethread_workqueue("ep93xx_spid");
836 if (!espi->wq) {
837 dev_err(&pdev->dev, "unable to create workqueue\n");
838 goto fail_free_irq;
839 }
840 INIT_WORK(&espi->msg_work, ep93xx_spi_work);
841 INIT_LIST_HEAD(&espi->msg_queue);
842 espi->running = true;
843
844 /* make sure that the hardware is disabled */
845 ep93xx_spi_write_u8(espi, SSPCR1, 0);
846
847 error = spi_register_master(master);
848 if (error) {
849 dev_err(&pdev->dev, "failed to register SPI master\n");
850 goto fail_free_queue;
851 }
852
853 dev_info(&pdev->dev, "EP93xx SPI Controller at 0x%08lx irq %d\n",
854 (unsigned long)res->start, espi->irq);
855
856 return 0;
857
858fail_free_queue:
859 destroy_workqueue(espi->wq);
860fail_free_irq:
861 free_irq(espi->irq, espi);
862fail_unmap_regs:
863 iounmap(espi->regs_base);
864fail_free_mem:
865 release_mem_region(res->start, resource_size(res));
866fail_put_clock:
867 clk_put(espi->clk);
868fail_release_master:
869 spi_master_put(master);
870 platform_set_drvdata(pdev, NULL);
871
872 return error;
873}
874
875static int __exit ep93xx_spi_remove(struct platform_device *pdev)
876{
877 struct spi_master *master = platform_get_drvdata(pdev);
878 struct ep93xx_spi *espi = spi_master_get_devdata(master);
879 struct resource *res;
880
881 spin_lock_irq(&espi->lock);
882 espi->running = false;
883 spin_unlock_irq(&espi->lock);
884
885 destroy_workqueue(espi->wq);
886
887 /*
888 * Complete remaining messages with %-ESHUTDOWN status.
889 */
890 spin_lock_irq(&espi->lock);
891 while (!list_empty(&espi->msg_queue)) {
892 struct spi_message *msg;
893
894 msg = list_first_entry(&espi->msg_queue,
895 struct spi_message, queue);
896 list_del_init(&msg->queue);
897 msg->status = -ESHUTDOWN;
898 spin_unlock_irq(&espi->lock);
899 msg->complete(msg->context);
900 spin_lock_irq(&espi->lock);
901 }
902 spin_unlock_irq(&espi->lock);
903
904 free_irq(espi->irq, espi);
905 iounmap(espi->regs_base);
906 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
907 release_mem_region(res->start, resource_size(res));
908 clk_put(espi->clk);
909 platform_set_drvdata(pdev, NULL);
910
911 spi_unregister_master(master);
912 return 0;
913}
914
915static struct platform_driver ep93xx_spi_driver = {
916 .driver = {
917 .name = "ep93xx-spi",
918 .owner = THIS_MODULE,
919 },
920 .remove = __exit_p(ep93xx_spi_remove),
921};
922
923static int __init ep93xx_spi_init(void)
924{
925 return platform_driver_probe(&ep93xx_spi_driver, ep93xx_spi_probe);
926}
927module_init(ep93xx_spi_init);
928
929static void __exit ep93xx_spi_exit(void)
930{
931 platform_driver_unregister(&ep93xx_spi_driver);
932}
933module_exit(ep93xx_spi_exit);
934
935MODULE_DESCRIPTION("EP93xx SPI Controller driver");
936MODULE_AUTHOR("Mika Westerberg <mika.westerberg@iki.fi>");
937MODULE_LICENSE("GPL");
938MODULE_ALIAS("platform:ep93xx-spi");
diff --git a/drivers/spi/mpc512x_psc_spi.c b/drivers/spi/mpc512x_psc_spi.c
new file mode 100644
index 000000000000..28a126d2742b
--- /dev/null
+++ b/drivers/spi/mpc512x_psc_spi.c
@@ -0,0 +1,576 @@
1/*
2 * MPC512x PSC in SPI mode driver.
3 *
4 * Copyright (C) 2007,2008 Freescale Semiconductor Inc.
5 * Original port from 52xx driver:
6 * Hongjun Chen <hong-jun.chen@freescale.com>
7 *
8 * Fork of mpc52xx_psc_spi.c:
9 * Copyright (C) 2006 TOPTICA Photonics AG., Dragos Carp
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16
17#include <linux/module.h>
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/errno.h>
21#include <linux/interrupt.h>
22#include <linux/of_platform.h>
23#include <linux/workqueue.h>
24#include <linux/completion.h>
25#include <linux/io.h>
26#include <linux/delay.h>
27#include <linux/clk.h>
28#include <linux/spi/spi.h>
29#include <linux/fsl_devices.h>
30#include <asm/mpc52xx_psc.h>
31
32struct mpc512x_psc_spi {
33 void (*cs_control)(struct spi_device *spi, bool on);
34 u32 sysclk;
35
36 /* driver internal data */
37 struct mpc52xx_psc __iomem *psc;
38 struct mpc512x_psc_fifo __iomem *fifo;
39 unsigned int irq;
40 u8 bits_per_word;
41 u8 busy;
42 u32 mclk;
43 u8 eofbyte;
44
45 struct workqueue_struct *workqueue;
46 struct work_struct work;
47
48 struct list_head queue;
49 spinlock_t lock; /* Message queue lock */
50
51 struct completion done;
52};
53
54/* controller state */
55struct mpc512x_psc_spi_cs {
56 int bits_per_word;
57 int speed_hz;
58};
59
60/* set clock freq, clock ramp, bits per work
61 * if t is NULL then reset the values to the default values
62 */
63static int mpc512x_psc_spi_transfer_setup(struct spi_device *spi,
64 struct spi_transfer *t)
65{
66 struct mpc512x_psc_spi_cs *cs = spi->controller_state;
67
68 cs->speed_hz = (t && t->speed_hz)
69 ? t->speed_hz : spi->max_speed_hz;
70 cs->bits_per_word = (t && t->bits_per_word)
71 ? t->bits_per_word : spi->bits_per_word;
72 cs->bits_per_word = ((cs->bits_per_word + 7) / 8) * 8;
73 return 0;
74}
75
76static void mpc512x_psc_spi_activate_cs(struct spi_device *spi)
77{
78 struct mpc512x_psc_spi_cs *cs = spi->controller_state;
79 struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master);
80 struct mpc52xx_psc __iomem *psc = mps->psc;
81 u32 sicr;
82 u32 ccr;
83 u16 bclkdiv;
84
85 sicr = in_be32(&psc->sicr);
86
87 /* Set clock phase and polarity */
88 if (spi->mode & SPI_CPHA)
89 sicr |= 0x00001000;
90 else
91 sicr &= ~0x00001000;
92
93 if (spi->mode & SPI_CPOL)
94 sicr |= 0x00002000;
95 else
96 sicr &= ~0x00002000;
97
98 if (spi->mode & SPI_LSB_FIRST)
99 sicr |= 0x10000000;
100 else
101 sicr &= ~0x10000000;
102 out_be32(&psc->sicr, sicr);
103
104 ccr = in_be32(&psc->ccr);
105 ccr &= 0xFF000000;
106 if (cs->speed_hz)
107 bclkdiv = (mps->mclk / cs->speed_hz) - 1;
108 else
109 bclkdiv = (mps->mclk / 1000000) - 1; /* default 1MHz */
110
111 ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8));
112 out_be32(&psc->ccr, ccr);
113 mps->bits_per_word = cs->bits_per_word;
114
115 if (mps->cs_control)
116 mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 1 : 0);
117}
118
119static void mpc512x_psc_spi_deactivate_cs(struct spi_device *spi)
120{
121 struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master);
122
123 if (mps->cs_control)
124 mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 0 : 1);
125
126}
127
128/* extract and scale size field in txsz or rxsz */
129#define MPC512x_PSC_FIFO_SZ(sz) ((sz & 0x7ff) << 2);
130
131#define EOFBYTE 1
132
133static int mpc512x_psc_spi_transfer_rxtx(struct spi_device *spi,
134 struct spi_transfer *t)
135{
136 struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master);
137 struct mpc52xx_psc __iomem *psc = mps->psc;
138 struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
139 size_t len = t->len;
140 u8 *tx_buf = (u8 *)t->tx_buf;
141 u8 *rx_buf = (u8 *)t->rx_buf;
142
143 if (!tx_buf && !rx_buf && t->len)
144 return -EINVAL;
145
146 /* Zero MR2 */
147 in_8(&psc->mode);
148 out_8(&psc->mode, 0x0);
149
150 while (len) {
151 int count;
152 int i;
153 u8 data;
154 size_t fifosz;
155 int rxcount;
156
157 /*
158 * The number of bytes that can be sent at a time
159 * depends on the fifo size.
160 */
161 fifosz = MPC512x_PSC_FIFO_SZ(in_be32(&fifo->txsz));
162 count = min(fifosz, len);
163
164 for (i = count; i > 0; i--) {
165 data = tx_buf ? *tx_buf++ : 0;
166 if (len == EOFBYTE)
167 setbits32(&fifo->txcmd, MPC512x_PSC_FIFO_EOF);
168 out_8(&fifo->txdata_8, data);
169 len--;
170 }
171
172 INIT_COMPLETION(mps->done);
173
174 /* interrupt on tx fifo empty */
175 out_be32(&fifo->txisr, MPC512x_PSC_FIFO_EMPTY);
176 out_be32(&fifo->tximr, MPC512x_PSC_FIFO_EMPTY);
177
178 /* enable transmiter/receiver */
179 out_8(&psc->command,
180 MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE);
181
182 wait_for_completion(&mps->done);
183
184 mdelay(1);
185
186 /* rx fifo should have count bytes in it */
187 rxcount = in_be32(&fifo->rxcnt);
188 if (rxcount != count)
189 mdelay(1);
190
191 rxcount = in_be32(&fifo->rxcnt);
192 if (rxcount != count) {
193 dev_warn(&spi->dev, "expected %d bytes in rx fifo "
194 "but got %d\n", count, rxcount);
195 }
196
197 rxcount = min(rxcount, count);
198 for (i = rxcount; i > 0; i--) {
199 data = in_8(&fifo->rxdata_8);
200 if (rx_buf)
201 *rx_buf++ = data;
202 }
203 while (in_be32(&fifo->rxcnt)) {
204 in_8(&fifo->rxdata_8);
205 }
206
207 out_8(&psc->command,
208 MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
209 }
210 /* disable transmiter/receiver and fifo interrupt */
211 out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
212 out_be32(&fifo->tximr, 0);
213 return 0;
214}
215
216static void mpc512x_psc_spi_work(struct work_struct *work)
217{
218 struct mpc512x_psc_spi *mps = container_of(work,
219 struct mpc512x_psc_spi,
220 work);
221
222 spin_lock_irq(&mps->lock);
223 mps->busy = 1;
224 while (!list_empty(&mps->queue)) {
225 struct spi_message *m;
226 struct spi_device *spi;
227 struct spi_transfer *t = NULL;
228 unsigned cs_change;
229 int status;
230
231 m = container_of(mps->queue.next, struct spi_message, queue);
232 list_del_init(&m->queue);
233 spin_unlock_irq(&mps->lock);
234
235 spi = m->spi;
236 cs_change = 1;
237 status = 0;
238 list_for_each_entry(t, &m->transfers, transfer_list) {
239 if (t->bits_per_word || t->speed_hz) {
240 status = mpc512x_psc_spi_transfer_setup(spi, t);
241 if (status < 0)
242 break;
243 }
244
245 if (cs_change)
246 mpc512x_psc_spi_activate_cs(spi);
247 cs_change = t->cs_change;
248
249 status = mpc512x_psc_spi_transfer_rxtx(spi, t);
250 if (status)
251 break;
252 m->actual_length += t->len;
253
254 if (t->delay_usecs)
255 udelay(t->delay_usecs);
256
257 if (cs_change)
258 mpc512x_psc_spi_deactivate_cs(spi);
259 }
260
261 m->status = status;
262 m->complete(m->context);
263
264 if (status || !cs_change)
265 mpc512x_psc_spi_deactivate_cs(spi);
266
267 mpc512x_psc_spi_transfer_setup(spi, NULL);
268
269 spin_lock_irq(&mps->lock);
270 }
271 mps->busy = 0;
272 spin_unlock_irq(&mps->lock);
273}
274
275static int mpc512x_psc_spi_setup(struct spi_device *spi)
276{
277 struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master);
278 struct mpc512x_psc_spi_cs *cs = spi->controller_state;
279 unsigned long flags;
280
281 if (spi->bits_per_word % 8)
282 return -EINVAL;
283
284 if (!cs) {
285 cs = kzalloc(sizeof *cs, GFP_KERNEL);
286 if (!cs)
287 return -ENOMEM;
288 spi->controller_state = cs;
289 }
290
291 cs->bits_per_word = spi->bits_per_word;
292 cs->speed_hz = spi->max_speed_hz;
293
294 spin_lock_irqsave(&mps->lock, flags);
295 if (!mps->busy)
296 mpc512x_psc_spi_deactivate_cs(spi);
297 spin_unlock_irqrestore(&mps->lock, flags);
298
299 return 0;
300}
301
302static int mpc512x_psc_spi_transfer(struct spi_device *spi,
303 struct spi_message *m)
304{
305 struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master);
306 unsigned long flags;
307
308 m->actual_length = 0;
309 m->status = -EINPROGRESS;
310
311 spin_lock_irqsave(&mps->lock, flags);
312 list_add_tail(&m->queue, &mps->queue);
313 queue_work(mps->workqueue, &mps->work);
314 spin_unlock_irqrestore(&mps->lock, flags);
315
316 return 0;
317}
318
319static void mpc512x_psc_spi_cleanup(struct spi_device *spi)
320{
321 kfree(spi->controller_state);
322}
323
324static int mpc512x_psc_spi_port_config(struct spi_master *master,
325 struct mpc512x_psc_spi *mps)
326{
327 struct mpc52xx_psc __iomem *psc = mps->psc;
328 struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
329 struct clk *spiclk;
330 int ret = 0;
331 char name[32];
332 u32 sicr;
333 u32 ccr;
334 u16 bclkdiv;
335
336 sprintf(name, "psc%d_mclk", master->bus_num);
337 spiclk = clk_get(&master->dev, name);
338 clk_enable(spiclk);
339 mps->mclk = clk_get_rate(spiclk);
340 clk_put(spiclk);
341
342 /* Reset the PSC into a known state */
343 out_8(&psc->command, MPC52xx_PSC_RST_RX);
344 out_8(&psc->command, MPC52xx_PSC_RST_TX);
345 out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
346
347 /* Disable psc interrupts all useful interrupts are in fifo */
348 out_be16(&psc->isr_imr.imr, 0);
349
350 /* Disable fifo interrupts, will be enabled later */
351 out_be32(&fifo->tximr, 0);
352 out_be32(&fifo->rximr, 0);
353
354 /* Setup fifo slice address and size */
355 /*out_be32(&fifo->txsz, 0x0fe00004);*/
356 /*out_be32(&fifo->rxsz, 0x0ff00004);*/
357
358 sicr = 0x01000000 | /* SIM = 0001 -- 8 bit */
359 0x00800000 | /* GenClk = 1 -- internal clk */
360 0x00008000 | /* SPI = 1 */
361 0x00004000 | /* MSTR = 1 -- SPI master */
362 0x00000800; /* UseEOF = 1 -- SS low until EOF */
363
364 out_be32(&psc->sicr, sicr);
365
366 ccr = in_be32(&psc->ccr);
367 ccr &= 0xFF000000;
368 bclkdiv = (mps->mclk / 1000000) - 1; /* default 1MHz */
369 ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8));
370 out_be32(&psc->ccr, ccr);
371
372 /* Set 2ms DTL delay */
373 out_8(&psc->ctur, 0x00);
374 out_8(&psc->ctlr, 0x82);
375
376 /* we don't use the alarms */
377 out_be32(&fifo->rxalarm, 0xfff);
378 out_be32(&fifo->txalarm, 0);
379
380 /* Enable FIFO slices for Rx/Tx */
381 out_be32(&fifo->rxcmd,
382 MPC512x_PSC_FIFO_ENABLE_SLICE | MPC512x_PSC_FIFO_ENABLE_DMA);
383 out_be32(&fifo->txcmd,
384 MPC512x_PSC_FIFO_ENABLE_SLICE | MPC512x_PSC_FIFO_ENABLE_DMA);
385
386 mps->bits_per_word = 8;
387
388 return ret;
389}
390
391static irqreturn_t mpc512x_psc_spi_isr(int irq, void *dev_id)
392{
393 struct mpc512x_psc_spi *mps = (struct mpc512x_psc_spi *)dev_id;
394 struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
395
396 /* clear interrupt and wake up the work queue */
397 if (in_be32(&fifo->txisr) &
398 in_be32(&fifo->tximr) & MPC512x_PSC_FIFO_EMPTY) {
399 out_be32(&fifo->txisr, MPC512x_PSC_FIFO_EMPTY);
400 out_be32(&fifo->tximr, 0);
401 complete(&mps->done);
402 return IRQ_HANDLED;
403 }
404 return IRQ_NONE;
405}
406
407/* bus_num is used only for the case dev->platform_data == NULL */
408static int __init mpc512x_psc_spi_do_probe(struct device *dev, u32 regaddr,
409 u32 size, unsigned int irq,
410 s16 bus_num)
411{
412 struct fsl_spi_platform_data *pdata = dev->platform_data;
413 struct mpc512x_psc_spi *mps;
414 struct spi_master *master;
415 int ret;
416 void *tempp;
417
418 master = spi_alloc_master(dev, sizeof *mps);
419 if (master == NULL)
420 return -ENOMEM;
421
422 dev_set_drvdata(dev, master);
423 mps = spi_master_get_devdata(master);
424 mps->irq = irq;
425
426 if (pdata == NULL) {
427 dev_err(dev, "probe called without platform data, no "
428 "cs_control function will be called\n");
429 mps->cs_control = NULL;
430 mps->sysclk = 0;
431 master->bus_num = bus_num;
432 master->num_chipselect = 255;
433 } else {
434 mps->cs_control = pdata->cs_control;
435 mps->sysclk = pdata->sysclk;
436 master->bus_num = pdata->bus_num;
437 master->num_chipselect = pdata->max_chipselect;
438 }
439
440 master->setup = mpc512x_psc_spi_setup;
441 master->transfer = mpc512x_psc_spi_transfer;
442 master->cleanup = mpc512x_psc_spi_cleanup;
443
444 tempp = ioremap(regaddr, size);
445 if (!tempp) {
446 dev_err(dev, "could not ioremap I/O port range\n");
447 ret = -EFAULT;
448 goto free_master;
449 }
450 mps->psc = tempp;
451 mps->fifo =
452 (struct mpc512x_psc_fifo *)(tempp + sizeof(struct mpc52xx_psc));
453
454 ret = request_irq(mps->irq, mpc512x_psc_spi_isr, IRQF_SHARED,
455 "mpc512x-psc-spi", mps);
456 if (ret)
457 goto free_master;
458
459 ret = mpc512x_psc_spi_port_config(master, mps);
460 if (ret < 0)
461 goto free_irq;
462
463 spin_lock_init(&mps->lock);
464 init_completion(&mps->done);
465 INIT_WORK(&mps->work, mpc512x_psc_spi_work);
466 INIT_LIST_HEAD(&mps->queue);
467
468 mps->workqueue =
469 create_singlethread_workqueue(dev_name(master->dev.parent));
470 if (mps->workqueue == NULL) {
471 ret = -EBUSY;
472 goto free_irq;
473 }
474
475 ret = spi_register_master(master);
476 if (ret < 0)
477 goto unreg_master;
478
479 return ret;
480
481unreg_master:
482 destroy_workqueue(mps->workqueue);
483free_irq:
484 free_irq(mps->irq, mps);
485free_master:
486 if (mps->psc)
487 iounmap(mps->psc);
488 spi_master_put(master);
489
490 return ret;
491}
492
493static int __exit mpc512x_psc_spi_do_remove(struct device *dev)
494{
495 struct spi_master *master = dev_get_drvdata(dev);
496 struct mpc512x_psc_spi *mps = spi_master_get_devdata(master);
497
498 flush_workqueue(mps->workqueue);
499 destroy_workqueue(mps->workqueue);
500 spi_unregister_master(master);
501 free_irq(mps->irq, mps);
502 if (mps->psc)
503 iounmap(mps->psc);
504
505 return 0;
506}
507
508static int __init mpc512x_psc_spi_of_probe(struct of_device *op,
509 const struct of_device_id *match)
510{
511 const u32 *regaddr_p;
512 u64 regaddr64, size64;
513 s16 id = -1;
514
515 regaddr_p = of_get_address(op->node, 0, &size64, NULL);
516 if (!regaddr_p) {
517 dev_err(&op->dev, "Invalid PSC address\n");
518 return -EINVAL;
519 }
520 regaddr64 = of_translate_address(op->node, regaddr_p);
521
522 /* get PSC id (0..11, used by port_config) */
523 if (op->dev.platform_data == NULL) {
524 const u32 *psc_nump;
525
526 psc_nump = of_get_property(op->node, "cell-index", NULL);
527 if (!psc_nump || *psc_nump > 11) {
528 dev_err(&op->dev, "mpc512x_psc_spi: Device node %s "
529 "has invalid cell-index property\n",
530 op->node->full_name);
531 return -EINVAL;
532 }
533 id = *psc_nump;
534 }
535
536 return mpc512x_psc_spi_do_probe(&op->dev, (u32) regaddr64, (u32) size64,
537 irq_of_parse_and_map(op->node, 0), id);
538}
539
540static int __exit mpc512x_psc_spi_of_remove(struct of_device *op)
541{
542 return mpc512x_psc_spi_do_remove(&op->dev);
543}
544
545static struct of_device_id mpc512x_psc_spi_of_match[] = {
546 { .compatible = "fsl,mpc5121-psc-spi", },
547 {},
548};
549
550MODULE_DEVICE_TABLE(of, mpc512x_psc_spi_of_match);
551
552static struct of_platform_driver mpc512x_psc_spi_of_driver = {
553 .match_table = mpc512x_psc_spi_of_match,
554 .probe = mpc512x_psc_spi_of_probe,
555 .remove = __exit_p(mpc512x_psc_spi_of_remove),
556 .driver = {
557 .name = "mpc512x-psc-spi",
558 .owner = THIS_MODULE,
559 },
560};
561
562static int __init mpc512x_psc_spi_init(void)
563{
564 return of_register_platform_driver(&mpc512x_psc_spi_of_driver);
565}
566module_init(mpc512x_psc_spi_init);
567
568static void __exit mpc512x_psc_spi_exit(void)
569{
570 of_unregister_platform_driver(&mpc512x_psc_spi_of_driver);
571}
572module_exit(mpc512x_psc_spi_exit);
573
574MODULE_AUTHOR("John Rigby");
575MODULE_DESCRIPTION("MPC512x PSC SPI Driver");
576MODULE_LICENSE("GPL");
diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c
index e0de0d0eedea..b3a94ca0a75a 100644
--- a/drivers/spi/omap2_mcspi.c
+++ b/drivers/spi/omap2_mcspi.c
@@ -38,7 +38,7 @@
38 38
39#include <plat/dma.h> 39#include <plat/dma.h>
40#include <plat/clock.h> 40#include <plat/clock.h>
41 41#include <plat/mcspi.h>
42 42
43#define OMAP2_MCSPI_MAX_FREQ 48000000 43#define OMAP2_MCSPI_MAX_FREQ 48000000
44 44
@@ -113,7 +113,7 @@ struct omap2_mcspi_dma {
113/* use PIO for small transfers, avoiding DMA setup/teardown overhead and 113/* use PIO for small transfers, avoiding DMA setup/teardown overhead and
114 * cache operations; better heuristics consider wordsize and bitrate. 114 * cache operations; better heuristics consider wordsize and bitrate.
115 */ 115 */
116#define DMA_MIN_BYTES 8 116#define DMA_MIN_BYTES 160
117 117
118 118
119struct omap2_mcspi { 119struct omap2_mcspi {
@@ -229,6 +229,8 @@ static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
229 229
230 l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0; 230 l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0;
231 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l); 231 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l);
232 /* Flash post-writes */
233 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
232} 234}
233 235
234static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active) 236static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
@@ -303,11 +305,14 @@ omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
303 unsigned int count, c; 305 unsigned int count, c;
304 unsigned long base, tx_reg, rx_reg; 306 unsigned long base, tx_reg, rx_reg;
305 int word_len, data_type, element_count; 307 int word_len, data_type, element_count;
308 int elements;
309 u32 l;
306 u8 * rx; 310 u8 * rx;
307 const u8 * tx; 311 const u8 * tx;
308 312
309 mcspi = spi_master_get_devdata(spi->master); 313 mcspi = spi_master_get_devdata(spi->master);
310 mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 314 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
315 l = mcspi_cached_chconf0(spi);
311 316
312 count = xfer->len; 317 count = xfer->len;
313 c = count; 318 c = count;
@@ -346,8 +351,12 @@ omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
346 } 351 }
347 352
348 if (rx != NULL) { 353 if (rx != NULL) {
354 elements = element_count - 1;
355 if (l & OMAP2_MCSPI_CHCONF_TURBO)
356 elements--;
357
349 omap_set_dma_transfer_params(mcspi_dma->dma_rx_channel, 358 omap_set_dma_transfer_params(mcspi_dma->dma_rx_channel,
350 data_type, element_count - 1, 1, 359 data_type, elements, 1,
351 OMAP_DMA_SYNC_ELEMENT, 360 OMAP_DMA_SYNC_ELEMENT,
352 mcspi_dma->dma_rx_sync_dev, 1); 361 mcspi_dma->dma_rx_sync_dev, 1);
353 362
@@ -379,17 +388,42 @@ omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
379 wait_for_completion(&mcspi_dma->dma_rx_completion); 388 wait_for_completion(&mcspi_dma->dma_rx_completion);
380 dma_unmap_single(NULL, xfer->rx_dma, count, DMA_FROM_DEVICE); 389 dma_unmap_single(NULL, xfer->rx_dma, count, DMA_FROM_DEVICE);
381 omap2_mcspi_set_enable(spi, 0); 390 omap2_mcspi_set_enable(spi, 0);
391
392 if (l & OMAP2_MCSPI_CHCONF_TURBO) {
393
394 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
395 & OMAP2_MCSPI_CHSTAT_RXS)) {
396 u32 w;
397
398 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
399 if (word_len <= 8)
400 ((u8 *)xfer->rx_buf)[elements++] = w;
401 else if (word_len <= 16)
402 ((u16 *)xfer->rx_buf)[elements++] = w;
403 else /* word_len <= 32 */
404 ((u32 *)xfer->rx_buf)[elements++] = w;
405 } else {
406 dev_err(&spi->dev,
407 "DMA RX penultimate word empty");
408 count -= (word_len <= 8) ? 2 :
409 (word_len <= 16) ? 4 :
410 /* word_len <= 32 */ 8;
411 omap2_mcspi_set_enable(spi, 1);
412 return count;
413 }
414 }
415
382 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) 416 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
383 & OMAP2_MCSPI_CHSTAT_RXS)) { 417 & OMAP2_MCSPI_CHSTAT_RXS)) {
384 u32 w; 418 u32 w;
385 419
386 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); 420 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
387 if (word_len <= 8) 421 if (word_len <= 8)
388 ((u8 *)xfer->rx_buf)[element_count - 1] = w; 422 ((u8 *)xfer->rx_buf)[elements] = w;
389 else if (word_len <= 16) 423 else if (word_len <= 16)
390 ((u16 *)xfer->rx_buf)[element_count - 1] = w; 424 ((u16 *)xfer->rx_buf)[elements] = w;
391 else /* word_len <= 32 */ 425 else /* word_len <= 32 */
392 ((u32 *)xfer->rx_buf)[element_count - 1] = w; 426 ((u32 *)xfer->rx_buf)[elements] = w;
393 } else { 427 } else {
394 dev_err(&spi->dev, "DMA RX last word empty"); 428 dev_err(&spi->dev, "DMA RX last word empty");
395 count -= (word_len <= 8) ? 1 : 429 count -= (word_len <= 8) ? 1 :
@@ -433,7 +467,6 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
433 word_len = cs->word_len; 467 word_len = cs->word_len;
434 468
435 l = mcspi_cached_chconf0(spi); 469 l = mcspi_cached_chconf0(spi);
436 l &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
437 470
438 /* We store the pre-calculated register addresses on stack to speed 471 /* We store the pre-calculated register addresses on stack to speed
439 * up the transfer loop. */ 472 * up the transfer loop. */
@@ -468,11 +501,26 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
468 dev_err(&spi->dev, "RXS timed out\n"); 501 dev_err(&spi->dev, "RXS timed out\n");
469 goto out; 502 goto out;
470 } 503 }
471 /* prevent last RX_ONLY read from triggering 504
472 * more word i/o: switch to rx+tx 505 if (c == 1 && tx == NULL &&
473 */ 506 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
474 if (c == 0 && tx == NULL) 507 omap2_mcspi_set_enable(spi, 0);
475 mcspi_write_chconf0(spi, l); 508 *rx++ = __raw_readl(rx_reg);
509#ifdef VERBOSE
510 dev_dbg(&spi->dev, "read-%d %02x\n",
511 word_len, *(rx - 1));
512#endif
513 if (mcspi_wait_for_reg_bit(chstat_reg,
514 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
515 dev_err(&spi->dev,
516 "RXS timed out\n");
517 goto out;
518 }
519 c = 0;
520 } else if (c == 0 && tx == NULL) {
521 omap2_mcspi_set_enable(spi, 0);
522 }
523
476 *rx++ = __raw_readl(rx_reg); 524 *rx++ = __raw_readl(rx_reg);
477#ifdef VERBOSE 525#ifdef VERBOSE
478 dev_dbg(&spi->dev, "read-%d %02x\n", 526 dev_dbg(&spi->dev, "read-%d %02x\n",
@@ -506,11 +554,26 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
506 dev_err(&spi->dev, "RXS timed out\n"); 554 dev_err(&spi->dev, "RXS timed out\n");
507 goto out; 555 goto out;
508 } 556 }
509 /* prevent last RX_ONLY read from triggering 557
510 * more word i/o: switch to rx+tx 558 if (c == 2 && tx == NULL &&
511 */ 559 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
512 if (c == 0 && tx == NULL) 560 omap2_mcspi_set_enable(spi, 0);
513 mcspi_write_chconf0(spi, l); 561 *rx++ = __raw_readl(rx_reg);
562#ifdef VERBOSE
563 dev_dbg(&spi->dev, "read-%d %04x\n",
564 word_len, *(rx - 1));
565#endif
566 if (mcspi_wait_for_reg_bit(chstat_reg,
567 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
568 dev_err(&spi->dev,
569 "RXS timed out\n");
570 goto out;
571 }
572 c = 0;
573 } else if (c == 0 && tx == NULL) {
574 omap2_mcspi_set_enable(spi, 0);
575 }
576
514 *rx++ = __raw_readl(rx_reg); 577 *rx++ = __raw_readl(rx_reg);
515#ifdef VERBOSE 578#ifdef VERBOSE
516 dev_dbg(&spi->dev, "read-%d %04x\n", 579 dev_dbg(&spi->dev, "read-%d %04x\n",
@@ -544,11 +607,26 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
544 dev_err(&spi->dev, "RXS timed out\n"); 607 dev_err(&spi->dev, "RXS timed out\n");
545 goto out; 608 goto out;
546 } 609 }
547 /* prevent last RX_ONLY read from triggering 610
548 * more word i/o: switch to rx+tx 611 if (c == 4 && tx == NULL &&
549 */ 612 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
550 if (c == 0 && tx == NULL) 613 omap2_mcspi_set_enable(spi, 0);
551 mcspi_write_chconf0(spi, l); 614 *rx++ = __raw_readl(rx_reg);
615#ifdef VERBOSE
616 dev_dbg(&spi->dev, "read-%d %08x\n",
617 word_len, *(rx - 1));
618#endif
619 if (mcspi_wait_for_reg_bit(chstat_reg,
620 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
621 dev_err(&spi->dev,
622 "RXS timed out\n");
623 goto out;
624 }
625 c = 0;
626 } else if (c == 0 && tx == NULL) {
627 omap2_mcspi_set_enable(spi, 0);
628 }
629
552 *rx++ = __raw_readl(rx_reg); 630 *rx++ = __raw_readl(rx_reg);
553#ifdef VERBOSE 631#ifdef VERBOSE
554 dev_dbg(&spi->dev, "read-%d %08x\n", 632 dev_dbg(&spi->dev, "read-%d %08x\n",
@@ -568,6 +646,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
568 dev_err(&spi->dev, "EOT timed out\n"); 646 dev_err(&spi->dev, "EOT timed out\n");
569 } 647 }
570out: 648out:
649 omap2_mcspi_set_enable(spi, 1);
571 return count - c; 650 return count - c;
572} 651}
573 652
@@ -755,7 +834,6 @@ static void omap2_mcspi_cleanup(struct spi_device *spi)
755 struct omap2_mcspi_cs *cs; 834 struct omap2_mcspi_cs *cs;
756 835
757 mcspi = spi_master_get_devdata(spi->master); 836 mcspi = spi_master_get_devdata(spi->master);
758 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
759 837
760 if (spi->controller_state) { 838 if (spi->controller_state) {
761 /* Unlink controller state from context save list */ 839 /* Unlink controller state from context save list */
@@ -765,13 +843,17 @@ static void omap2_mcspi_cleanup(struct spi_device *spi)
765 kfree(spi->controller_state); 843 kfree(spi->controller_state);
766 } 844 }
767 845
768 if (mcspi_dma->dma_rx_channel != -1) { 846 if (spi->chip_select < spi->master->num_chipselect) {
769 omap_free_dma(mcspi_dma->dma_rx_channel); 847 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
770 mcspi_dma->dma_rx_channel = -1; 848
771 } 849 if (mcspi_dma->dma_rx_channel != -1) {
772 if (mcspi_dma->dma_tx_channel != -1) { 850 omap_free_dma(mcspi_dma->dma_rx_channel);
773 omap_free_dma(mcspi_dma->dma_tx_channel); 851 mcspi_dma->dma_rx_channel = -1;
774 mcspi_dma->dma_tx_channel = -1; 852 }
853 if (mcspi_dma->dma_tx_channel != -1) {
854 omap_free_dma(mcspi_dma->dma_tx_channel);
855 mcspi_dma->dma_tx_channel = -1;
856 }
775 } 857 }
776} 858}
777 859
@@ -797,6 +879,7 @@ static void omap2_mcspi_work(struct work_struct *work)
797 struct spi_transfer *t = NULL; 879 struct spi_transfer *t = NULL;
798 int cs_active = 0; 880 int cs_active = 0;
799 struct omap2_mcspi_cs *cs; 881 struct omap2_mcspi_cs *cs;
882 struct omap2_mcspi_device_config *cd;
800 int par_override = 0; 883 int par_override = 0;
801 int status = 0; 884 int status = 0;
802 u32 chconf; 885 u32 chconf;
@@ -809,6 +892,7 @@ static void omap2_mcspi_work(struct work_struct *work)
809 892
810 spi = m->spi; 893 spi = m->spi;
811 cs = spi->controller_state; 894 cs = spi->controller_state;
895 cd = spi->controller_data;
812 896
813 omap2_mcspi_set_enable(spi, 1); 897 omap2_mcspi_set_enable(spi, 1);
814 list_for_each_entry(t, &m->transfers, transfer_list) { 898 list_for_each_entry(t, &m->transfers, transfer_list) {
@@ -832,10 +916,19 @@ static void omap2_mcspi_work(struct work_struct *work)
832 916
833 chconf = mcspi_cached_chconf0(spi); 917 chconf = mcspi_cached_chconf0(spi);
834 chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK; 918 chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
919 chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
920
835 if (t->tx_buf == NULL) 921 if (t->tx_buf == NULL)
836 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY; 922 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
837 else if (t->rx_buf == NULL) 923 else if (t->rx_buf == NULL)
838 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY; 924 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
925
926 if (cd && cd->turbo_mode && t->tx_buf == NULL) {
927 /* Turbo mode is for more than one word */
928 if (t->len > ((cs->word_len + 7) >> 3))
929 chconf |= OMAP2_MCSPI_CHCONF_TURBO;
930 }
931
839 mcspi_write_chconf0(spi, chconf); 932 mcspi_write_chconf0(spi, chconf);
840 933
841 if (t->len) { 934 if (t->len) {
diff --git a/drivers/spi/spi_bitbang_txrx.h b/drivers/spi/spi_bitbang_txrx.h
new file mode 100644
index 000000000000..fc033bbf9180
--- /dev/null
+++ b/drivers/spi/spi_bitbang_txrx.h
@@ -0,0 +1,93 @@
1/*
2 * Mix this utility code with some glue code to get one of several types of
3 * simple SPI master driver. Two do polled word-at-a-time I/O:
4 *
5 * - GPIO/parport bitbangers. Provide chipselect() and txrx_word[](),
6 * expanding the per-word routines from the inline templates below.
7 *
8 * - Drivers for controllers resembling bare shift registers. Provide
9 * chipselect() and txrx_word[](), with custom setup()/cleanup() methods
10 * that use your controller's clock and chipselect registers.
11 *
12 * Some hardware works well with requests at spi_transfer scope:
13 *
14 * - Drivers leveraging smarter hardware, with fifos or DMA; or for half
15 * duplex (MicroWire) controllers. Provide chipselect() and txrx_bufs(),
16 * and custom setup()/cleanup() methods.
17 */
18
19/*
20 * The code that knows what GPIO pins do what should have declared four
21 * functions, ideally as inlines, before including this header:
22 *
23 * void setsck(struct spi_device *, int is_on);
24 * void setmosi(struct spi_device *, int is_on);
25 * int getmiso(struct spi_device *);
26 * void spidelay(unsigned);
27 *
28 * setsck()'s is_on parameter is a zero/nonzero boolean.
29 *
30 * setmosi()'s is_on parameter is a zero/nonzero boolean.
31 *
32 * getmiso() is required to return 0 or 1 only. Any other value is invalid
33 * and will result in improper operation.
34 *
35 * A non-inlined routine would call bitbang_txrx_*() routines. The
36 * main loop could easily compile down to a handful of instructions,
37 * especially if the delay is a NOP (to run at peak speed).
38 *
39 * Since this is software, the timings may not be exactly what your board's
40 * chips need ... there may be several reasons you'd need to tweak timings
41 * in these routines, not just make to make it faster or slower to match a
42 * particular CPU clock rate.
43 */
44
45static inline u32
46bitbang_txrx_be_cpha0(struct spi_device *spi,
47 unsigned nsecs, unsigned cpol,
48 u32 word, u8 bits)
49{
50 /* if (cpol == 0) this is SPI_MODE_0; else this is SPI_MODE_2 */
51
52 /* clock starts at inactive polarity */
53 for (word <<= (32 - bits); likely(bits); bits--) {
54
55 /* setup MSB (to slave) on trailing edge */
56 setmosi(spi, word & (1 << 31));
57 spidelay(nsecs); /* T(setup) */
58
59 setsck(spi, !cpol);
60 spidelay(nsecs);
61
62 /* sample MSB (from slave) on leading edge */
63 word <<= 1;
64 word |= getmiso(spi);
65 setsck(spi, cpol);
66 }
67 return word;
68}
69
70static inline u32
71bitbang_txrx_be_cpha1(struct spi_device *spi,
72 unsigned nsecs, unsigned cpol,
73 u32 word, u8 bits)
74{
75 /* if (cpol == 0) this is SPI_MODE_1; else this is SPI_MODE_3 */
76
77 /* clock starts at inactive polarity */
78 for (word <<= (32 - bits); likely(bits); bits--) {
79
80 /* setup MSB (to slave) on leading edge */
81 setsck(spi, !cpol);
82 setmosi(spi, word & (1 << 31));
83 spidelay(nsecs); /* T(setup) */
84
85 setsck(spi, cpol);
86 spidelay(nsecs);
87
88 /* sample MSB (from slave) on trailing edge */
89 word <<= 1;
90 word |= getmiso(spi);
91 }
92 return word;
93}
diff --git a/drivers/spi/spi_butterfly.c b/drivers/spi/spi_butterfly.c
index c2184866fa9c..8b5281281111 100644
--- a/drivers/spi/spi_butterfly.c
+++ b/drivers/spi/spi_butterfly.c
@@ -149,8 +149,7 @@ static void butterfly_chipselect(struct spi_device *spi, int value)
149#define spidelay(X) do{}while(0) 149#define spidelay(X) do{}while(0)
150//#define spidelay ndelay 150//#define spidelay ndelay
151 151
152#define EXPAND_BITBANG_TXRX 152#include "spi_bitbang_txrx.h"
153#include <linux/spi/spi_bitbang.h>
154 153
155static u32 154static u32
156butterfly_txrx_word_mode0(struct spi_device *spi, 155butterfly_txrx_word_mode0(struct spi_device *spi,
diff --git a/drivers/spi/spi_gpio.c b/drivers/spi/spi_gpio.c
index 26bd03e61855..7edbd5807e0e 100644
--- a/drivers/spi/spi_gpio.c
+++ b/drivers/spi/spi_gpio.c
@@ -127,8 +127,7 @@ static inline int getmiso(const struct spi_device *spi)
127 */ 127 */
128#define spidelay(nsecs) do {} while (0) 128#define spidelay(nsecs) do {} while (0)
129 129
130#define EXPAND_BITBANG_TXRX 130#include "spi_bitbang_txrx.h"
131#include <linux/spi/spi_bitbang.h>
132 131
133/* 132/*
134 * These functions can leverage inline expansion of GPIO calls to shrink 133 * These functions can leverage inline expansion of GPIO calls to shrink
diff --git a/drivers/spi/spi_lm70llp.c b/drivers/spi/spi_lm70llp.c
index 568c781ad91c..86fb7b5993db 100644
--- a/drivers/spi/spi_lm70llp.c
+++ b/drivers/spi/spi_lm70llp.c
@@ -174,8 +174,7 @@ static inline int getmiso(struct spi_device *s)
174} 174}
175/*--------------------------------------------------------------------*/ 175/*--------------------------------------------------------------------*/
176 176
177#define EXPAND_BITBANG_TXRX 1 177#include "spi_bitbang_txrx.h"
178#include <linux/spi/spi_bitbang.h>
179 178
180static void lm70_chipselect(struct spi_device *spi, int value) 179static void lm70_chipselect(struct spi_device *spi, int value)
181{ 180{
diff --git a/drivers/spi/spi_mpc8xxx.c b/drivers/spi/spi_mpc8xxx.c
index 75b7f8c0babc..ffa111a7e9d4 100644
--- a/drivers/spi/spi_mpc8xxx.c
+++ b/drivers/spi/spi_mpc8xxx.c
@@ -241,7 +241,6 @@ static void mpc8xxx_spi_change_mode(struct spi_device *spi)
241 241
242 /* Turn off SPI unit prior changing mode */ 242 /* Turn off SPI unit prior changing mode */
243 mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE); 243 mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE);
244 mpc8xxx_spi_write_reg(mode, cs->hw_mode);
245 244
246 /* When in CPM mode, we need to reinit tx and rx. */ 245 /* When in CPM mode, we need to reinit tx and rx. */
247 if (mspi->flags & SPI_CPM_MODE) { 246 if (mspi->flags & SPI_CPM_MODE) {
@@ -258,7 +257,7 @@ static void mpc8xxx_spi_change_mode(struct spi_device *spi)
258 } 257 }
259 } 258 }
260 } 259 }
261 260 mpc8xxx_spi_write_reg(mode, cs->hw_mode);
262 local_irq_restore(flags); 261 local_irq_restore(flags);
263} 262}
264 263
@@ -287,36 +286,12 @@ static void mpc8xxx_spi_chipselect(struct spi_device *spi, int value)
287 } 286 }
288} 287}
289 288
290static 289static int
291int mpc8xxx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t) 290mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs,
291 struct spi_device *spi,
292 struct mpc8xxx_spi *mpc8xxx_spi,
293 int bits_per_word)
292{ 294{
293 struct mpc8xxx_spi *mpc8xxx_spi;
294 u8 bits_per_word, pm;
295 u32 hz;
296 struct spi_mpc8xxx_cs *cs = spi->controller_state;
297
298 mpc8xxx_spi = spi_master_get_devdata(spi->master);
299
300 if (t) {
301 bits_per_word = t->bits_per_word;
302 hz = t->speed_hz;
303 } else {
304 bits_per_word = 0;
305 hz = 0;
306 }
307
308 /* spi_transfer level calls that work per-word */
309 if (!bits_per_word)
310 bits_per_word = spi->bits_per_word;
311
312 /* Make sure its a bit width we support [4..16, 32] */
313 if ((bits_per_word < 4)
314 || ((bits_per_word > 16) && (bits_per_word != 32)))
315 return -EINVAL;
316
317 if (!hz)
318 hz = spi->max_speed_hz;
319
320 cs->rx_shift = 0; 295 cs->rx_shift = 0;
321 cs->tx_shift = 0; 296 cs->tx_shift = 0;
322 if (bits_per_word <= 8) { 297 if (bits_per_word <= 8) {
@@ -340,19 +315,82 @@ int mpc8xxx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
340 return -EINVAL; 315 return -EINVAL;
341 316
342 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE && 317 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE &&
343 spi->mode & SPI_LSB_FIRST) { 318 spi->mode & SPI_LSB_FIRST) {
344 cs->tx_shift = 0; 319 cs->tx_shift = 0;
345 if (bits_per_word <= 8) 320 if (bits_per_word <= 8)
346 cs->rx_shift = 8; 321 cs->rx_shift = 8;
347 else 322 else
348 cs->rx_shift = 0; 323 cs->rx_shift = 0;
349 } 324 }
350
351 mpc8xxx_spi->rx_shift = cs->rx_shift; 325 mpc8xxx_spi->rx_shift = cs->rx_shift;
352 mpc8xxx_spi->tx_shift = cs->tx_shift; 326 mpc8xxx_spi->tx_shift = cs->tx_shift;
353 mpc8xxx_spi->get_rx = cs->get_rx; 327 mpc8xxx_spi->get_rx = cs->get_rx;
354 mpc8xxx_spi->get_tx = cs->get_tx; 328 mpc8xxx_spi->get_tx = cs->get_tx;
355 329
330 return bits_per_word;
331}
332
333static int
334mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs,
335 struct spi_device *spi,
336 int bits_per_word)
337{
338 /* QE uses Little Endian for words > 8
339 * so transform all words > 8 into 8 bits
340 * Unfortnatly that doesn't work for LSB so
341 * reject these for now */
342 /* Note: 32 bits word, LSB works iff
343 * tfcr/rfcr is set to CPMFCR_GBL */
344 if (spi->mode & SPI_LSB_FIRST &&
345 bits_per_word > 8)
346 return -EINVAL;
347 if (bits_per_word > 8)
348 return 8; /* pretend its 8 bits */
349 return bits_per_word;
350}
351
352static
353int mpc8xxx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
354{
355 struct mpc8xxx_spi *mpc8xxx_spi;
356 int bits_per_word;
357 u8 pm;
358 u32 hz;
359 struct spi_mpc8xxx_cs *cs = spi->controller_state;
360
361 mpc8xxx_spi = spi_master_get_devdata(spi->master);
362
363 if (t) {
364 bits_per_word = t->bits_per_word;
365 hz = t->speed_hz;
366 } else {
367 bits_per_word = 0;
368 hz = 0;
369 }
370
371 /* spi_transfer level calls that work per-word */
372 if (!bits_per_word)
373 bits_per_word = spi->bits_per_word;
374
375 /* Make sure its a bit width we support [4..16, 32] */
376 if ((bits_per_word < 4)
377 || ((bits_per_word > 16) && (bits_per_word != 32)))
378 return -EINVAL;
379
380 if (!hz)
381 hz = spi->max_speed_hz;
382
383 if (!(mpc8xxx_spi->flags & SPI_CPM_MODE))
384 bits_per_word = mspi_apply_cpu_mode_quirks(cs, spi,
385 mpc8xxx_spi,
386 bits_per_word);
387 else if (mpc8xxx_spi->flags & SPI_QE)
388 bits_per_word = mspi_apply_qe_mode_quirks(cs, spi,
389 bits_per_word);
390
391 if (bits_per_word < 0)
392 return bits_per_word;
393
356 if (bits_per_word == 32) 394 if (bits_per_word == 32)
357 bits_per_word = 0; 395 bits_per_word = 0;
358 else 396 else
@@ -438,7 +476,7 @@ static int mpc8xxx_spi_cpm_bufs(struct mpc8xxx_spi *mspi,
438 dev_err(dev, "unable to map tx dma\n"); 476 dev_err(dev, "unable to map tx dma\n");
439 return -ENOMEM; 477 return -ENOMEM;
440 } 478 }
441 } else { 479 } else if (t->tx_buf) {
442 mspi->tx_dma = t->tx_dma; 480 mspi->tx_dma = t->tx_dma;
443 } 481 }
444 482
@@ -449,7 +487,7 @@ static int mpc8xxx_spi_cpm_bufs(struct mpc8xxx_spi *mspi,
449 dev_err(dev, "unable to map rx dma\n"); 487 dev_err(dev, "unable to map rx dma\n");
450 goto err_rx_dma; 488 goto err_rx_dma;
451 } 489 }
452 } else { 490 } else if (t->rx_buf) {
453 mspi->rx_dma = t->rx_dma; 491 mspi->rx_dma = t->rx_dma;
454 } 492 }
455 493
@@ -477,7 +515,7 @@ static void mpc8xxx_spi_cpm_bufs_complete(struct mpc8xxx_spi *mspi)
477 515
478 if (mspi->map_tx_dma) 516 if (mspi->map_tx_dma)
479 dma_unmap_single(dev, mspi->tx_dma, t->len, DMA_TO_DEVICE); 517 dma_unmap_single(dev, mspi->tx_dma, t->len, DMA_TO_DEVICE);
480 if (mspi->map_tx_dma) 518 if (mspi->map_rx_dma)
481 dma_unmap_single(dev, mspi->rx_dma, t->len, DMA_FROM_DEVICE); 519 dma_unmap_single(dev, mspi->rx_dma, t->len, DMA_FROM_DEVICE);
482 mspi->xfer_in_progress = NULL; 520 mspi->xfer_in_progress = NULL;
483} 521}
diff --git a/drivers/spi/spi_s3c24xx_gpio.c b/drivers/spi/spi_s3c24xx_gpio.c
index bbf9371cd284..8979a75dbd7b 100644
--- a/drivers/spi/spi_s3c24xx_gpio.c
+++ b/drivers/spi/spi_s3c24xx_gpio.c
@@ -58,8 +58,7 @@ static inline u32 getmiso(struct spi_device *dev)
58 58
59#define spidelay(x) ndelay(x) 59#define spidelay(x) ndelay(x)
60 60
61#define EXPAND_BITBANG_TXRX 61#include "spi_bitbang_txrx.h"
62#include <linux/spi/spi_bitbang.h>
63 62
64 63
65static u32 s3c2410_spigpio_txrx_mode0(struct spi_device *spi, 64static u32 s3c2410_spigpio_txrx_mode0(struct spi_device *spi,
diff --git a/drivers/spi/spi_sh_sci.c b/drivers/spi/spi_sh_sci.c
index a65c12ffa733..a511be7961a0 100644
--- a/drivers/spi/spi_sh_sci.c
+++ b/drivers/spi/spi_sh_sci.c
@@ -78,8 +78,7 @@ static inline u32 getmiso(struct spi_device *dev)
78 78
79#define spidelay(x) ndelay(x) 79#define spidelay(x) ndelay(x)
80 80
81#define EXPAND_BITBANG_TXRX 81#include "spi_bitbang_txrx.h"
82#include <linux/spi/spi_bitbang.h>
83 82
84static u32 sh_sci_spi_txrx_mode0(struct spi_device *spi, 83static u32 sh_sci_spi_txrx_mode0(struct spi_device *spi,
85 unsigned nsecs, u32 word, u8 bits) 84 unsigned nsecs, u32 word, u8 bits)
diff --git a/drivers/spi/xilinx_spi_of.c b/drivers/spi/xilinx_spi_of.c
index 55c58012a028..4654805b08d8 100644
--- a/drivers/spi/xilinx_spi_of.c
+++ b/drivers/spi/xilinx_spi_of.c
@@ -48,13 +48,13 @@ static int __devinit xilinx_spi_of_probe(struct of_device *ofdev,
48 const u32 *prop; 48 const u32 *prop;
49 int len; 49 int len;
50 50
51 rc = of_address_to_resource(ofdev->node, 0, &r_mem); 51 rc = of_address_to_resource(ofdev->dev.of_node, 0, &r_mem);
52 if (rc) { 52 if (rc) {
53 dev_warn(&ofdev->dev, "invalid address\n"); 53 dev_warn(&ofdev->dev, "invalid address\n");
54 return rc; 54 return rc;
55 } 55 }
56 56
57 rc = of_irq_to_resource(ofdev->node, 0, &r_irq); 57 rc = of_irq_to_resource(ofdev->dev.of_node, 0, &r_irq);
58 if (rc == NO_IRQ) { 58 if (rc == NO_IRQ) {
59 dev_warn(&ofdev->dev, "no IRQ found\n"); 59 dev_warn(&ofdev->dev, "no IRQ found\n");
60 return -ENODEV; 60 return -ENODEV;
@@ -67,7 +67,7 @@ static int __devinit xilinx_spi_of_probe(struct of_device *ofdev,
67 return -ENOMEM; 67 return -ENOMEM;
68 68
69 /* number of slave select bits is required */ 69 /* number of slave select bits is required */
70 prop = of_get_property(ofdev->node, "xlnx,num-ss-bits", &len); 70 prop = of_get_property(ofdev->dev.of_node, "xlnx,num-ss-bits", &len);
71 if (!prop || len < sizeof(*prop)) { 71 if (!prop || len < sizeof(*prop)) {
72 dev_warn(&ofdev->dev, "no 'xlnx,num-ss-bits' property\n"); 72 dev_warn(&ofdev->dev, "no 'xlnx,num-ss-bits' property\n");
73 return -EINVAL; 73 return -EINVAL;
@@ -81,7 +81,7 @@ static int __devinit xilinx_spi_of_probe(struct of_device *ofdev,
81 dev_set_drvdata(&ofdev->dev, master); 81 dev_set_drvdata(&ofdev->dev, master);
82 82
83 /* Add any subnodes on the SPI bus */ 83 /* Add any subnodes on the SPI bus */
84 of_register_spi_devices(master, ofdev->node); 84 of_register_spi_devices(master, ofdev->dev.of_node);
85 85
86 return 0; 86 return 0;
87} 87}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-15 08:09:56 -0500