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path: root/drivers/spi/spi_bfin5xx.c
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Diffstat (limited to 'drivers/spi/spi_bfin5xx.c')
-rw-r--r--drivers/spi/spi_bfin5xx.c78
1 files changed, 39 insertions, 39 deletions
diff --git a/drivers/spi/spi_bfin5xx.c b/drivers/spi/spi_bfin5xx.c
index a85bcb306590..0e33b5aa35fb 100644
--- a/drivers/spi/spi_bfin5xx.c
+++ b/drivers/spi/spi_bfin5xx.c
@@ -186,7 +186,7 @@ static int flush(struct driver_data *drv_data)
186 186
187 /* wait for stop and clear stat */ 187 /* wait for stop and clear stat */
188 while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && limit--) 188 while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && limit--)
189 continue; 189 cpu_relax();
190 190
191 write_STAT(drv_data, BIT_STAT_CLR); 191 write_STAT(drv_data, BIT_STAT_CLR);
192 192
@@ -262,7 +262,7 @@ static void null_writer(struct driver_data *drv_data)
262 while (drv_data->tx < drv_data->tx_end) { 262 while (drv_data->tx < drv_data->tx_end) {
263 write_TDBR(drv_data, 0); 263 write_TDBR(drv_data, 0);
264 while ((read_STAT(drv_data) & BIT_STAT_TXS)) 264 while ((read_STAT(drv_data) & BIT_STAT_TXS))
265 continue; 265 cpu_relax();
266 drv_data->tx += n_bytes; 266 drv_data->tx += n_bytes;
267 } 267 }
268} 268}
@@ -274,7 +274,7 @@ static void null_reader(struct driver_data *drv_data)
274 274
275 while (drv_data->rx < drv_data->rx_end) { 275 while (drv_data->rx < drv_data->rx_end) {
276 while (!(read_STAT(drv_data) & BIT_STAT_RXS)) 276 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
277 continue; 277 cpu_relax();
278 dummy_read(drv_data); 278 dummy_read(drv_data);
279 drv_data->rx += n_bytes; 279 drv_data->rx += n_bytes;
280 } 280 }
@@ -287,12 +287,12 @@ static void u8_writer(struct driver_data *drv_data)
287 287
288 /* poll for SPI completion before start */ 288 /* poll for SPI completion before start */
289 while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) 289 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
290 continue; 290 cpu_relax();
291 291
292 while (drv_data->tx < drv_data->tx_end) { 292 while (drv_data->tx < drv_data->tx_end) {
293 write_TDBR(drv_data, (*(u8 *) (drv_data->tx))); 293 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
294 while (read_STAT(drv_data) & BIT_STAT_TXS) 294 while (read_STAT(drv_data) & BIT_STAT_TXS)
295 continue; 295 cpu_relax();
296 ++drv_data->tx; 296 ++drv_data->tx;
297 } 297 }
298} 298}
@@ -303,14 +303,14 @@ static void u8_cs_chg_writer(struct driver_data *drv_data)
303 303
304 /* poll for SPI completion before start */ 304 /* poll for SPI completion before start */
305 while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) 305 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
306 continue; 306 cpu_relax();
307 307
308 while (drv_data->tx < drv_data->tx_end) { 308 while (drv_data->tx < drv_data->tx_end) {
309 cs_active(drv_data, chip); 309 cs_active(drv_data, chip);
310 310
311 write_TDBR(drv_data, (*(u8 *) (drv_data->tx))); 311 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
312 while (read_STAT(drv_data) & BIT_STAT_TXS) 312 while (read_STAT(drv_data) & BIT_STAT_TXS)
313 continue; 313 cpu_relax();
314 314
315 cs_deactive(drv_data, chip); 315 cs_deactive(drv_data, chip);
316 316
@@ -325,7 +325,7 @@ static void u8_reader(struct driver_data *drv_data)
325 325
326 /* poll for SPI completion before start */ 326 /* poll for SPI completion before start */
327 while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) 327 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
328 continue; 328 cpu_relax();
329 329
330 /* clear TDBR buffer before read(else it will be shifted out) */ 330 /* clear TDBR buffer before read(else it will be shifted out) */
331 write_TDBR(drv_data, 0xFFFF); 331 write_TDBR(drv_data, 0xFFFF);
@@ -334,13 +334,13 @@ static void u8_reader(struct driver_data *drv_data)
334 334
335 while (drv_data->rx < drv_data->rx_end - 1) { 335 while (drv_data->rx < drv_data->rx_end - 1) {
336 while (!(read_STAT(drv_data) & BIT_STAT_RXS)) 336 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
337 continue; 337 cpu_relax();
338 *(u8 *) (drv_data->rx) = read_RDBR(drv_data); 338 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
339 ++drv_data->rx; 339 ++drv_data->rx;
340 } 340 }
341 341
342 while (!(read_STAT(drv_data) & BIT_STAT_RXS)) 342 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
343 continue; 343 cpu_relax();
344 *(u8 *) (drv_data->rx) = read_SHAW(drv_data); 344 *(u8 *) (drv_data->rx) = read_SHAW(drv_data);
345 ++drv_data->rx; 345 ++drv_data->rx;
346} 346}
@@ -351,7 +351,7 @@ static void u8_cs_chg_reader(struct driver_data *drv_data)
351 351
352 /* poll for SPI completion before start */ 352 /* poll for SPI completion before start */
353 while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) 353 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
354 continue; 354 cpu_relax();
355 355
356 /* clear TDBR buffer before read(else it will be shifted out) */ 356 /* clear TDBR buffer before read(else it will be shifted out) */
357 write_TDBR(drv_data, 0xFFFF); 357 write_TDBR(drv_data, 0xFFFF);
@@ -363,7 +363,7 @@ static void u8_cs_chg_reader(struct driver_data *drv_data)
363 cs_deactive(drv_data, chip); 363 cs_deactive(drv_data, chip);
364 364
365 while (!(read_STAT(drv_data) & BIT_STAT_RXS)) 365 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
366 continue; 366 cpu_relax();
367 cs_active(drv_data, chip); 367 cs_active(drv_data, chip);
368 *(u8 *) (drv_data->rx) = read_RDBR(drv_data); 368 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
369 ++drv_data->rx; 369 ++drv_data->rx;
@@ -371,7 +371,7 @@ static void u8_cs_chg_reader(struct driver_data *drv_data)
371 cs_deactive(drv_data, chip); 371 cs_deactive(drv_data, chip);
372 372
373 while (!(read_STAT(drv_data) & BIT_STAT_RXS)) 373 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
374 continue; 374 cpu_relax();
375 *(u8 *) (drv_data->rx) = read_SHAW(drv_data); 375 *(u8 *) (drv_data->rx) = read_SHAW(drv_data);
376 ++drv_data->rx; 376 ++drv_data->rx;
377} 377}
@@ -380,15 +380,15 @@ static void u8_duplex(struct driver_data *drv_data)
380{ 380{
381 /* poll for SPI completion before start */ 381 /* poll for SPI completion before start */
382 while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) 382 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
383 continue; 383 cpu_relax();
384 384
385 /* in duplex mode, clk is triggered by writing of TDBR */ 385 /* in duplex mode, clk is triggered by writing of TDBR */
386 while (drv_data->rx < drv_data->rx_end) { 386 while (drv_data->rx < drv_data->rx_end) {
387 write_TDBR(drv_data, (*(u8 *) (drv_data->tx))); 387 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
388 while (read_STAT(drv_data) & BIT_STAT_TXS) 388 while (read_STAT(drv_data) & BIT_STAT_TXS)
389 continue; 389 cpu_relax();
390 while (!(read_STAT(drv_data) & BIT_STAT_RXS)) 390 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
391 continue; 391 cpu_relax();
392 *(u8 *) (drv_data->rx) = read_RDBR(drv_data); 392 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
393 ++drv_data->rx; 393 ++drv_data->rx;
394 ++drv_data->tx; 394 ++drv_data->tx;
@@ -401,16 +401,16 @@ static void u8_cs_chg_duplex(struct driver_data *drv_data)
401 401
402 /* poll for SPI completion before start */ 402 /* poll for SPI completion before start */
403 while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) 403 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
404 continue; 404 cpu_relax();
405 405
406 while (drv_data->rx < drv_data->rx_end) { 406 while (drv_data->rx < drv_data->rx_end) {
407 cs_active(drv_data, chip); 407 cs_active(drv_data, chip);
408 408
409 write_TDBR(drv_data, (*(u8 *) (drv_data->tx))); 409 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
410 while (read_STAT(drv_data) & BIT_STAT_TXS) 410 while (read_STAT(drv_data) & BIT_STAT_TXS)
411 continue; 411 cpu_relax();
412 while (!(read_STAT(drv_data) & BIT_STAT_RXS)) 412 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
413 continue; 413 cpu_relax();
414 *(u8 *) (drv_data->rx) = read_RDBR(drv_data); 414 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
415 415
416 cs_deactive(drv_data, chip); 416 cs_deactive(drv_data, chip);
@@ -427,12 +427,12 @@ static void u16_writer(struct driver_data *drv_data)
427 427
428 /* poll for SPI completion before start */ 428 /* poll for SPI completion before start */
429 while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) 429 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
430 continue; 430 cpu_relax();
431 431
432 while (drv_data->tx < drv_data->tx_end) { 432 while (drv_data->tx < drv_data->tx_end) {
433 write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); 433 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
434 while ((read_STAT(drv_data) & BIT_STAT_TXS)) 434 while ((read_STAT(drv_data) & BIT_STAT_TXS))
435 continue; 435 cpu_relax();
436 drv_data->tx += 2; 436 drv_data->tx += 2;
437 } 437 }
438} 438}
@@ -443,14 +443,14 @@ static void u16_cs_chg_writer(struct driver_data *drv_data)
443 443
444 /* poll for SPI completion before start */ 444 /* poll for SPI completion before start */
445 while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) 445 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
446 continue; 446 cpu_relax();
447 447
448 while (drv_data->tx < drv_data->tx_end) { 448 while (drv_data->tx < drv_data->tx_end) {
449 cs_active(drv_data, chip); 449 cs_active(drv_data, chip);
450 450
451 write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); 451 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
452 while ((read_STAT(drv_data) & BIT_STAT_TXS)) 452 while ((read_STAT(drv_data) & BIT_STAT_TXS))
453 continue; 453 cpu_relax();
454 454
455 cs_deactive(drv_data, chip); 455 cs_deactive(drv_data, chip);
456 456
@@ -465,7 +465,7 @@ static void u16_reader(struct driver_data *drv_data)
465 465
466 /* poll for SPI completion before start */ 466 /* poll for SPI completion before start */
467 while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) 467 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
468 continue; 468 cpu_relax();
469 469
470 /* clear TDBR buffer before read(else it will be shifted out) */ 470 /* clear TDBR buffer before read(else it will be shifted out) */
471 write_TDBR(drv_data, 0xFFFF); 471 write_TDBR(drv_data, 0xFFFF);
@@ -474,13 +474,13 @@ static void u16_reader(struct driver_data *drv_data)
474 474
475 while (drv_data->rx < (drv_data->rx_end - 2)) { 475 while (drv_data->rx < (drv_data->rx_end - 2)) {
476 while (!(read_STAT(drv_data) & BIT_STAT_RXS)) 476 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
477 continue; 477 cpu_relax();
478 *(u16 *) (drv_data->rx) = read_RDBR(drv_data); 478 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
479 drv_data->rx += 2; 479 drv_data->rx += 2;
480 } 480 }
481 481
482 while (!(read_STAT(drv_data) & BIT_STAT_RXS)) 482 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
483 continue; 483 cpu_relax();
484 *(u16 *) (drv_data->rx) = read_SHAW(drv_data); 484 *(u16 *) (drv_data->rx) = read_SHAW(drv_data);
485 drv_data->rx += 2; 485 drv_data->rx += 2;
486} 486}
@@ -491,7 +491,7 @@ static void u16_cs_chg_reader(struct driver_data *drv_data)
491 491
492 /* poll for SPI completion before start */ 492 /* poll for SPI completion before start */
493 while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) 493 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
494 continue; 494 cpu_relax();
495 495
496 /* clear TDBR buffer before read(else it will be shifted out) */ 496 /* clear TDBR buffer before read(else it will be shifted out) */
497 write_TDBR(drv_data, 0xFFFF); 497 write_TDBR(drv_data, 0xFFFF);
@@ -503,7 +503,7 @@ static void u16_cs_chg_reader(struct driver_data *drv_data)
503 cs_deactive(drv_data, chip); 503 cs_deactive(drv_data, chip);
504 504
505 while (!(read_STAT(drv_data) & BIT_STAT_RXS)) 505 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
506 continue; 506 cpu_relax();
507 cs_active(drv_data, chip); 507 cs_active(drv_data, chip);
508 *(u16 *) (drv_data->rx) = read_RDBR(drv_data); 508 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
509 drv_data->rx += 2; 509 drv_data->rx += 2;
@@ -511,7 +511,7 @@ static void u16_cs_chg_reader(struct driver_data *drv_data)
511 cs_deactive(drv_data, chip); 511 cs_deactive(drv_data, chip);
512 512
513 while (!(read_STAT(drv_data) & BIT_STAT_RXS)) 513 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
514 continue; 514 cpu_relax();
515 *(u16 *) (drv_data->rx) = read_SHAW(drv_data); 515 *(u16 *) (drv_data->rx) = read_SHAW(drv_data);
516 drv_data->rx += 2; 516 drv_data->rx += 2;
517} 517}
@@ -520,15 +520,15 @@ static void u16_duplex(struct driver_data *drv_data)
520{ 520{
521 /* poll for SPI completion before start */ 521 /* poll for SPI completion before start */
522 while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) 522 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
523 continue; 523 cpu_relax();
524 524
525 /* in duplex mode, clk is triggered by writing of TDBR */ 525 /* in duplex mode, clk is triggered by writing of TDBR */
526 while (drv_data->tx < drv_data->tx_end) { 526 while (drv_data->tx < drv_data->tx_end) {
527 write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); 527 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
528 while (read_STAT(drv_data) & BIT_STAT_TXS) 528 while (read_STAT(drv_data) & BIT_STAT_TXS)
529 continue; 529 cpu_relax();
530 while (!(read_STAT(drv_data) & BIT_STAT_RXS)) 530 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
531 continue; 531 cpu_relax();
532 *(u16 *) (drv_data->rx) = read_RDBR(drv_data); 532 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
533 drv_data->rx += 2; 533 drv_data->rx += 2;
534 drv_data->tx += 2; 534 drv_data->tx += 2;
@@ -541,16 +541,16 @@ static void u16_cs_chg_duplex(struct driver_data *drv_data)
541 541
542 /* poll for SPI completion before start */ 542 /* poll for SPI completion before start */
543 while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) 543 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
544 continue; 544 cpu_relax();
545 545
546 while (drv_data->tx < drv_data->tx_end) { 546 while (drv_data->tx < drv_data->tx_end) {
547 cs_active(drv_data, chip); 547 cs_active(drv_data, chip);
548 548
549 write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); 549 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
550 while (read_STAT(drv_data) & BIT_STAT_TXS) 550 while (read_STAT(drv_data) & BIT_STAT_TXS)
551 continue; 551 cpu_relax();
552 while (!(read_STAT(drv_data) & BIT_STAT_RXS)) 552 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
553 continue; 553 cpu_relax();
554 *(u16 *) (drv_data->rx) = read_RDBR(drv_data); 554 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
555 555
556 cs_deactive(drv_data, chip); 556 cs_deactive(drv_data, chip);
@@ -624,7 +624,7 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id)
624 624
625 /* Wait for DMA to complete */ 625 /* Wait for DMA to complete */
626 while (get_dma_curr_irqstat(drv_data->dma_channel) & DMA_RUN) 626 while (get_dma_curr_irqstat(drv_data->dma_channel) & DMA_RUN)
627 continue; 627 cpu_relax();
628 628
629 /* 629 /*
630 * wait for the last transaction shifted out. HRM states: 630 * wait for the last transaction shifted out. HRM states:
@@ -635,11 +635,11 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id)
635 if (drv_data->tx != NULL) { 635 if (drv_data->tx != NULL) {
636 while ((read_STAT(drv_data) & TXS) || 636 while ((read_STAT(drv_data) & TXS) ||
637 (read_STAT(drv_data) & TXS)) 637 (read_STAT(drv_data) & TXS))
638 continue; 638 cpu_relax();
639 } 639 }
640 640
641 while (!(read_STAT(drv_data) & SPIF)) 641 while (!(read_STAT(drv_data) & SPIF))
642 continue; 642 cpu_relax();
643 643
644 msg->actual_length += drv_data->len_in_bytes; 644 msg->actual_length += drv_data->len_in_bytes;
645 645
@@ -783,7 +783,7 @@ static void pump_transfers(unsigned long data)
783 783
784 /* poll for SPI completion before start */ 784 /* poll for SPI completion before start */
785 while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) 785 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
786 continue; 786 cpu_relax();
787 787
788 /* dirty hack for autobuffer DMA mode */ 788 /* dirty hack for autobuffer DMA mode */
789 if (drv_data->tx_dma == 0xFFFF) { 789 if (drv_data->tx_dma == 0xFFFF) {