diff options
Diffstat (limited to 'drivers/spi/spi-xilinx.c')
-rw-r--r-- | drivers/spi/spi-xilinx.c | 298 |
1 files changed, 163 insertions, 135 deletions
diff --git a/drivers/spi/spi-xilinx.c b/drivers/spi/spi-xilinx.c index 79bd84f43430..133f53a9c1d4 100644 --- a/drivers/spi/spi-xilinx.c +++ b/drivers/spi/spi-xilinx.c | |||
@@ -22,6 +22,8 @@ | |||
22 | #include <linux/spi/xilinx_spi.h> | 22 | #include <linux/spi/xilinx_spi.h> |
23 | #include <linux/io.h> | 23 | #include <linux/io.h> |
24 | 24 | ||
25 | #define XILINX_SPI_MAX_CS 32 | ||
26 | |||
25 | #define XILINX_SPI_NAME "xilinx_spi" | 27 | #define XILINX_SPI_NAME "xilinx_spi" |
26 | 28 | ||
27 | /* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e) | 29 | /* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e) |
@@ -34,7 +36,8 @@ | |||
34 | #define XSPI_CR_MASTER_MODE 0x04 | 36 | #define XSPI_CR_MASTER_MODE 0x04 |
35 | #define XSPI_CR_CPOL 0x08 | 37 | #define XSPI_CR_CPOL 0x08 |
36 | #define XSPI_CR_CPHA 0x10 | 38 | #define XSPI_CR_CPHA 0x10 |
37 | #define XSPI_CR_MODE_MASK (XSPI_CR_CPHA | XSPI_CR_CPOL) | 39 | #define XSPI_CR_MODE_MASK (XSPI_CR_CPHA | XSPI_CR_CPOL | \ |
40 | XSPI_CR_LSB_FIRST | XSPI_CR_LOOP) | ||
38 | #define XSPI_CR_TXFIFO_RESET 0x20 | 41 | #define XSPI_CR_TXFIFO_RESET 0x20 |
39 | #define XSPI_CR_RXFIFO_RESET 0x40 | 42 | #define XSPI_CR_RXFIFO_RESET 0x40 |
40 | #define XSPI_CR_MANUAL_SSELECT 0x80 | 43 | #define XSPI_CR_MANUAL_SSELECT 0x80 |
@@ -85,12 +88,11 @@ struct xilinx_spi { | |||
85 | 88 | ||
86 | u8 *rx_ptr; /* pointer in the Tx buffer */ | 89 | u8 *rx_ptr; /* pointer in the Tx buffer */ |
87 | const u8 *tx_ptr; /* pointer in the Rx buffer */ | 90 | const u8 *tx_ptr; /* pointer in the Rx buffer */ |
88 | int remaining_bytes; /* the number of bytes left to transfer */ | 91 | u8 bytes_per_word; |
89 | u8 bits_per_word; | 92 | int buffer_size; /* buffer size in words */ |
93 | u32 cs_inactive; /* Level of the CS pins when inactive*/ | ||
90 | unsigned int (*read_fn)(void __iomem *); | 94 | unsigned int (*read_fn)(void __iomem *); |
91 | void (*write_fn)(u32, void __iomem *); | 95 | void (*write_fn)(u32, void __iomem *); |
92 | void (*tx_fn)(struct xilinx_spi *); | ||
93 | void (*rx_fn)(struct xilinx_spi *); | ||
94 | }; | 96 | }; |
95 | 97 | ||
96 | static void xspi_write32(u32 val, void __iomem *addr) | 98 | static void xspi_write32(u32 val, void __iomem *addr) |
@@ -113,49 +115,51 @@ static unsigned int xspi_read32_be(void __iomem *addr) | |||
113 | return ioread32be(addr); | 115 | return ioread32be(addr); |
114 | } | 116 | } |
115 | 117 | ||
116 | static void xspi_tx8(struct xilinx_spi *xspi) | 118 | static void xilinx_spi_tx(struct xilinx_spi *xspi) |
117 | { | 119 | { |
118 | xspi->write_fn(*xspi->tx_ptr, xspi->regs + XSPI_TXD_OFFSET); | 120 | u32 data = 0; |
119 | xspi->tx_ptr++; | ||
120 | } | ||
121 | |||
122 | static void xspi_tx16(struct xilinx_spi *xspi) | ||
123 | { | ||
124 | xspi->write_fn(*(u16 *)(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET); | ||
125 | xspi->tx_ptr += 2; | ||
126 | } | ||
127 | 121 | ||
128 | static void xspi_tx32(struct xilinx_spi *xspi) | 122 | if (!xspi->tx_ptr) { |
129 | { | 123 | xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET); |
130 | xspi->write_fn(*(u32 *)(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET); | 124 | return; |
131 | xspi->tx_ptr += 4; | ||
132 | } | ||
133 | |||
134 | static void xspi_rx8(struct xilinx_spi *xspi) | ||
135 | { | ||
136 | u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET); | ||
137 | if (xspi->rx_ptr) { | ||
138 | *xspi->rx_ptr = data & 0xff; | ||
139 | xspi->rx_ptr++; | ||
140 | } | 125 | } |
141 | } | ||
142 | 126 | ||
143 | static void xspi_rx16(struct xilinx_spi *xspi) | 127 | switch (xspi->bytes_per_word) { |
144 | { | 128 | case 1: |
145 | u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET); | 129 | data = *(u8 *)(xspi->tx_ptr); |
146 | if (xspi->rx_ptr) { | 130 | break; |
147 | *(u16 *)(xspi->rx_ptr) = data & 0xffff; | 131 | case 2: |
148 | xspi->rx_ptr += 2; | 132 | data = *(u16 *)(xspi->tx_ptr); |
133 | break; | ||
134 | case 4: | ||
135 | data = *(u32 *)(xspi->tx_ptr); | ||
136 | break; | ||
149 | } | 137 | } |
138 | |||
139 | xspi->write_fn(data, xspi->regs + XSPI_TXD_OFFSET); | ||
140 | xspi->tx_ptr += xspi->bytes_per_word; | ||
150 | } | 141 | } |
151 | 142 | ||
152 | static void xspi_rx32(struct xilinx_spi *xspi) | 143 | static void xilinx_spi_rx(struct xilinx_spi *xspi) |
153 | { | 144 | { |
154 | u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET); | 145 | u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET); |
155 | if (xspi->rx_ptr) { | 146 | |
147 | if (!xspi->rx_ptr) | ||
148 | return; | ||
149 | |||
150 | switch (xspi->bytes_per_word) { | ||
151 | case 1: | ||
152 | *(u8 *)(xspi->rx_ptr) = data; | ||
153 | break; | ||
154 | case 2: | ||
155 | *(u16 *)(xspi->rx_ptr) = data; | ||
156 | break; | ||
157 | case 4: | ||
156 | *(u32 *)(xspi->rx_ptr) = data; | 158 | *(u32 *)(xspi->rx_ptr) = data; |
157 | xspi->rx_ptr += 4; | 159 | break; |
158 | } | 160 | } |
161 | |||
162 | xspi->rx_ptr += xspi->bytes_per_word; | ||
159 | } | 163 | } |
160 | 164 | ||
161 | static void xspi_init_hw(struct xilinx_spi *xspi) | 165 | static void xspi_init_hw(struct xilinx_spi *xspi) |
@@ -165,46 +169,56 @@ static void xspi_init_hw(struct xilinx_spi *xspi) | |||
165 | /* Reset the SPI device */ | 169 | /* Reset the SPI device */ |
166 | xspi->write_fn(XIPIF_V123B_RESET_MASK, | 170 | xspi->write_fn(XIPIF_V123B_RESET_MASK, |
167 | regs_base + XIPIF_V123B_RESETR_OFFSET); | 171 | regs_base + XIPIF_V123B_RESETR_OFFSET); |
168 | /* Disable all the interrupts just in case */ | 172 | /* Enable the transmit empty interrupt, which we use to determine |
169 | xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET); | 173 | * progress on the transmission. |
170 | /* Enable the global IPIF interrupt */ | 174 | */ |
171 | xspi->write_fn(XIPIF_V123B_GINTR_ENABLE, | 175 | xspi->write_fn(XSPI_INTR_TX_EMPTY, |
172 | regs_base + XIPIF_V123B_DGIER_OFFSET); | 176 | regs_base + XIPIF_V123B_IIER_OFFSET); |
177 | /* Disable the global IPIF interrupt */ | ||
178 | xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET); | ||
173 | /* Deselect the slave on the SPI bus */ | 179 | /* Deselect the slave on the SPI bus */ |
174 | xspi->write_fn(0xffff, regs_base + XSPI_SSR_OFFSET); | 180 | xspi->write_fn(0xffff, regs_base + XSPI_SSR_OFFSET); |
175 | /* Disable the transmitter, enable Manual Slave Select Assertion, | 181 | /* Disable the transmitter, enable Manual Slave Select Assertion, |
176 | * put SPI controller into master mode, and enable it */ | 182 | * put SPI controller into master mode, and enable it */ |
177 | xspi->write_fn(XSPI_CR_TRANS_INHIBIT | XSPI_CR_MANUAL_SSELECT | | 183 | xspi->write_fn(XSPI_CR_MANUAL_SSELECT | XSPI_CR_MASTER_MODE | |
178 | XSPI_CR_MASTER_MODE | XSPI_CR_ENABLE | XSPI_CR_TXFIFO_RESET | | 184 | XSPI_CR_ENABLE | XSPI_CR_TXFIFO_RESET | XSPI_CR_RXFIFO_RESET, |
179 | XSPI_CR_RXFIFO_RESET, regs_base + XSPI_CR_OFFSET); | 185 | regs_base + XSPI_CR_OFFSET); |
180 | } | 186 | } |
181 | 187 | ||
182 | static void xilinx_spi_chipselect(struct spi_device *spi, int is_on) | 188 | static void xilinx_spi_chipselect(struct spi_device *spi, int is_on) |
183 | { | 189 | { |
184 | struct xilinx_spi *xspi = spi_master_get_devdata(spi->master); | 190 | struct xilinx_spi *xspi = spi_master_get_devdata(spi->master); |
191 | u16 cr; | ||
192 | u32 cs; | ||
185 | 193 | ||
186 | if (is_on == BITBANG_CS_INACTIVE) { | 194 | if (is_on == BITBANG_CS_INACTIVE) { |
187 | /* Deselect the slave on the SPI bus */ | 195 | /* Deselect the slave on the SPI bus */ |
188 | xspi->write_fn(0xffff, xspi->regs + XSPI_SSR_OFFSET); | 196 | xspi->write_fn(xspi->cs_inactive, xspi->regs + XSPI_SSR_OFFSET); |
189 | } else if (is_on == BITBANG_CS_ACTIVE) { | 197 | return; |
190 | /* Set the SPI clock phase and polarity */ | ||
191 | u16 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) | ||
192 | & ~XSPI_CR_MODE_MASK; | ||
193 | if (spi->mode & SPI_CPHA) | ||
194 | cr |= XSPI_CR_CPHA; | ||
195 | if (spi->mode & SPI_CPOL) | ||
196 | cr |= XSPI_CR_CPOL; | ||
197 | xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET); | ||
198 | |||
199 | /* We do not check spi->max_speed_hz here as the SPI clock | ||
200 | * frequency is not software programmable (the IP block design | ||
201 | * parameter) | ||
202 | */ | ||
203 | |||
204 | /* Activate the chip select */ | ||
205 | xspi->write_fn(~(0x0001 << spi->chip_select), | ||
206 | xspi->regs + XSPI_SSR_OFFSET); | ||
207 | } | 198 | } |
199 | |||
200 | /* Set the SPI clock phase and polarity */ | ||
201 | cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) & ~XSPI_CR_MODE_MASK; | ||
202 | if (spi->mode & SPI_CPHA) | ||
203 | cr |= XSPI_CR_CPHA; | ||
204 | if (spi->mode & SPI_CPOL) | ||
205 | cr |= XSPI_CR_CPOL; | ||
206 | if (spi->mode & SPI_LSB_FIRST) | ||
207 | cr |= XSPI_CR_LSB_FIRST; | ||
208 | if (spi->mode & SPI_LOOP) | ||
209 | cr |= XSPI_CR_LOOP; | ||
210 | xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET); | ||
211 | |||
212 | /* We do not check spi->max_speed_hz here as the SPI clock | ||
213 | * frequency is not software programmable (the IP block design | ||
214 | * parameter) | ||
215 | */ | ||
216 | |||
217 | cs = xspi->cs_inactive; | ||
218 | cs ^= BIT(spi->chip_select); | ||
219 | |||
220 | /* Activate the chip select */ | ||
221 | xspi->write_fn(cs, xspi->regs + XSPI_SSR_OFFSET); | ||
208 | } | 222 | } |
209 | 223 | ||
210 | /* spi_bitbang requires custom setup_transfer() to be defined if there is a | 224 | /* spi_bitbang requires custom setup_transfer() to be defined if there is a |
@@ -213,85 +227,85 @@ static void xilinx_spi_chipselect(struct spi_device *spi, int is_on) | |||
213 | static int xilinx_spi_setup_transfer(struct spi_device *spi, | 227 | static int xilinx_spi_setup_transfer(struct spi_device *spi, |
214 | struct spi_transfer *t) | 228 | struct spi_transfer *t) |
215 | { | 229 | { |
216 | return 0; | 230 | struct xilinx_spi *xspi = spi_master_get_devdata(spi->master); |
217 | } | ||
218 | 231 | ||
219 | static void xilinx_spi_fill_tx_fifo(struct xilinx_spi *xspi) | 232 | if (spi->mode & SPI_CS_HIGH) |
220 | { | 233 | xspi->cs_inactive &= ~BIT(spi->chip_select); |
221 | u8 sr; | 234 | else |
235 | xspi->cs_inactive |= BIT(spi->chip_select); | ||
222 | 236 | ||
223 | /* Fill the Tx FIFO with as many bytes as possible */ | 237 | return 0; |
224 | sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); | ||
225 | while ((sr & XSPI_SR_TX_FULL_MASK) == 0 && xspi->remaining_bytes > 0) { | ||
226 | if (xspi->tx_ptr) | ||
227 | xspi->tx_fn(xspi); | ||
228 | else | ||
229 | xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET); | ||
230 | xspi->remaining_bytes -= xspi->bits_per_word / 8; | ||
231 | sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); | ||
232 | } | ||
233 | } | 238 | } |
234 | 239 | ||
235 | static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) | 240 | static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) |
236 | { | 241 | { |
237 | struct xilinx_spi *xspi = spi_master_get_devdata(spi->master); | 242 | struct xilinx_spi *xspi = spi_master_get_devdata(spi->master); |
238 | u32 ipif_ier; | 243 | int remaining_words; /* the number of words left to transfer */ |
244 | bool use_irq = false; | ||
245 | u16 cr = 0; | ||
239 | 246 | ||
240 | /* We get here with transmitter inhibited */ | 247 | /* We get here with transmitter inhibited */ |
241 | 248 | ||
242 | xspi->tx_ptr = t->tx_buf; | 249 | xspi->tx_ptr = t->tx_buf; |
243 | xspi->rx_ptr = t->rx_buf; | 250 | xspi->rx_ptr = t->rx_buf; |
244 | xspi->remaining_bytes = t->len; | 251 | remaining_words = t->len / xspi->bytes_per_word; |
245 | reinit_completion(&xspi->done); | 252 | reinit_completion(&xspi->done); |
246 | 253 | ||
254 | if (xspi->irq >= 0 && remaining_words > xspi->buffer_size) { | ||
255 | use_irq = true; | ||
256 | xspi->write_fn(XSPI_INTR_TX_EMPTY, | ||
257 | xspi->regs + XIPIF_V123B_IISR_OFFSET); | ||
258 | /* Enable the global IPIF interrupt */ | ||
259 | xspi->write_fn(XIPIF_V123B_GINTR_ENABLE, | ||
260 | xspi->regs + XIPIF_V123B_DGIER_OFFSET); | ||
261 | /* Inhibit irq to avoid spurious irqs on tx_empty*/ | ||
262 | cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET); | ||
263 | xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT, | ||
264 | xspi->regs + XSPI_CR_OFFSET); | ||
265 | } | ||
247 | 266 | ||
248 | /* Enable the transmit empty interrupt, which we use to determine | 267 | while (remaining_words) { |
249 | * progress on the transmission. | 268 | int n_words, tx_words, rx_words; |
250 | */ | ||
251 | ipif_ier = xspi->read_fn(xspi->regs + XIPIF_V123B_IIER_OFFSET); | ||
252 | xspi->write_fn(ipif_ier | XSPI_INTR_TX_EMPTY, | ||
253 | xspi->regs + XIPIF_V123B_IIER_OFFSET); | ||
254 | 269 | ||
255 | for (;;) { | 270 | n_words = min(remaining_words, xspi->buffer_size); |
256 | u16 cr; | ||
257 | u8 sr; | ||
258 | 271 | ||
259 | xilinx_spi_fill_tx_fifo(xspi); | 272 | tx_words = n_words; |
273 | while (tx_words--) | ||
274 | xilinx_spi_tx(xspi); | ||
260 | 275 | ||
261 | /* Start the transfer by not inhibiting the transmitter any | 276 | /* Start the transfer by not inhibiting the transmitter any |
262 | * longer | 277 | * longer |
263 | */ | 278 | */ |
264 | cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) & | ||
265 | ~XSPI_CR_TRANS_INHIBIT; | ||
266 | xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET); | ||
267 | 279 | ||
268 | wait_for_completion(&xspi->done); | 280 | if (use_irq) { |
281 | xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET); | ||
282 | wait_for_completion(&xspi->done); | ||
283 | } else | ||
284 | while (!(xspi->read_fn(xspi->regs + XSPI_SR_OFFSET) & | ||
285 | XSPI_SR_TX_EMPTY_MASK)) | ||
286 | ; | ||
269 | 287 | ||
270 | /* A transmit has just completed. Process received data and | 288 | /* A transmit has just completed. Process received data and |
271 | * check for more data to transmit. Always inhibit the | 289 | * check for more data to transmit. Always inhibit the |
272 | * transmitter while the Isr refills the transmit register/FIFO, | 290 | * transmitter while the Isr refills the transmit register/FIFO, |
273 | * or make sure it is stopped if we're done. | 291 | * or make sure it is stopped if we're done. |
274 | */ | 292 | */ |
275 | cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET); | 293 | if (use_irq) |
276 | xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT, | 294 | xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT, |
277 | xspi->regs + XSPI_CR_OFFSET); | 295 | xspi->regs + XSPI_CR_OFFSET); |
278 | 296 | ||
279 | /* Read out all the data from the Rx FIFO */ | 297 | /* Read out all the data from the Rx FIFO */ |
280 | sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); | 298 | rx_words = n_words; |
281 | while ((sr & XSPI_SR_RX_EMPTY_MASK) == 0) { | 299 | while (rx_words--) |
282 | xspi->rx_fn(xspi); | 300 | xilinx_spi_rx(xspi); |
283 | sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); | 301 | |
284 | } | 302 | remaining_words -= n_words; |
285 | |||
286 | /* See if there is more data to send */ | ||
287 | if (xspi->remaining_bytes <= 0) | ||
288 | break; | ||
289 | } | 303 | } |
290 | 304 | ||
291 | /* Disable the transmit empty interrupt */ | 305 | if (use_irq) |
292 | xspi->write_fn(ipif_ier, xspi->regs + XIPIF_V123B_IIER_OFFSET); | 306 | xspi->write_fn(0, xspi->regs + XIPIF_V123B_DGIER_OFFSET); |
293 | 307 | ||
294 | return t->len - xspi->remaining_bytes; | 308 | return t->len; |
295 | } | 309 | } |
296 | 310 | ||
297 | 311 | ||
@@ -316,6 +330,28 @@ static irqreturn_t xilinx_spi_irq(int irq, void *dev_id) | |||
316 | return IRQ_HANDLED; | 330 | return IRQ_HANDLED; |
317 | } | 331 | } |
318 | 332 | ||
333 | static int xilinx_spi_find_buffer_size(struct xilinx_spi *xspi) | ||
334 | { | ||
335 | u8 sr; | ||
336 | int n_words = 0; | ||
337 | |||
338 | /* | ||
339 | * Before the buffer_size detection we reset the core | ||
340 | * to make sure we start with a clean state. | ||
341 | */ | ||
342 | xspi->write_fn(XIPIF_V123B_RESET_MASK, | ||
343 | xspi->regs + XIPIF_V123B_RESETR_OFFSET); | ||
344 | |||
345 | /* Fill the Tx FIFO with as many words as possible */ | ||
346 | do { | ||
347 | xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET); | ||
348 | sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); | ||
349 | n_words++; | ||
350 | } while (!(sr & XSPI_SR_TX_FULL_MASK)); | ||
351 | |||
352 | return n_words; | ||
353 | } | ||
354 | |||
319 | static const struct of_device_id xilinx_spi_of_match[] = { | 355 | static const struct of_device_id xilinx_spi_of_match[] = { |
320 | { .compatible = "xlnx,xps-spi-2.00.a", }, | 356 | { .compatible = "xlnx,xps-spi-2.00.a", }, |
321 | { .compatible = "xlnx,xps-spi-2.00.b", }, | 357 | { .compatible = "xlnx,xps-spi-2.00.b", }, |
@@ -348,14 +384,21 @@ static int xilinx_spi_probe(struct platform_device *pdev) | |||
348 | return -EINVAL; | 384 | return -EINVAL; |
349 | } | 385 | } |
350 | 386 | ||
387 | if (num_cs > XILINX_SPI_MAX_CS) { | ||
388 | dev_err(&pdev->dev, "Invalid number of spi slaves\n"); | ||
389 | return -EINVAL; | ||
390 | } | ||
391 | |||
351 | master = spi_alloc_master(&pdev->dev, sizeof(struct xilinx_spi)); | 392 | master = spi_alloc_master(&pdev->dev, sizeof(struct xilinx_spi)); |
352 | if (!master) | 393 | if (!master) |
353 | return -ENODEV; | 394 | return -ENODEV; |
354 | 395 | ||
355 | /* the spi->mode bits understood by this driver: */ | 396 | /* the spi->mode bits understood by this driver: */ |
356 | master->mode_bits = SPI_CPOL | SPI_CPHA; | 397 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_LOOP | |
398 | SPI_CS_HIGH; | ||
357 | 399 | ||
358 | xspi = spi_master_get_devdata(master); | 400 | xspi = spi_master_get_devdata(master); |
401 | xspi->cs_inactive = 0xffffffff; | ||
359 | xspi->bitbang.master = master; | 402 | xspi->bitbang.master = master; |
360 | xspi->bitbang.chipselect = xilinx_spi_chipselect; | 403 | xspi->bitbang.chipselect = xilinx_spi_chipselect; |
361 | xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer; | 404 | xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer; |
@@ -392,35 +435,20 @@ static int xilinx_spi_probe(struct platform_device *pdev) | |||
392 | } | 435 | } |
393 | 436 | ||
394 | master->bits_per_word_mask = SPI_BPW_MASK(bits_per_word); | 437 | master->bits_per_word_mask = SPI_BPW_MASK(bits_per_word); |
395 | xspi->bits_per_word = bits_per_word; | 438 | xspi->bytes_per_word = bits_per_word / 8; |
396 | if (xspi->bits_per_word == 8) { | 439 | xspi->buffer_size = xilinx_spi_find_buffer_size(xspi); |
397 | xspi->tx_fn = xspi_tx8; | ||
398 | xspi->rx_fn = xspi_rx8; | ||
399 | } else if (xspi->bits_per_word == 16) { | ||
400 | xspi->tx_fn = xspi_tx16; | ||
401 | xspi->rx_fn = xspi_rx16; | ||
402 | } else if (xspi->bits_per_word == 32) { | ||
403 | xspi->tx_fn = xspi_tx32; | ||
404 | xspi->rx_fn = xspi_rx32; | ||
405 | } else { | ||
406 | ret = -EINVAL; | ||
407 | goto put_master; | ||
408 | } | ||
409 | |||
410 | /* SPI controller initializations */ | ||
411 | xspi_init_hw(xspi); | ||
412 | 440 | ||
413 | xspi->irq = platform_get_irq(pdev, 0); | 441 | xspi->irq = platform_get_irq(pdev, 0); |
414 | if (xspi->irq < 0) { | 442 | if (xspi->irq >= 0) { |
415 | ret = xspi->irq; | 443 | /* Register for SPI Interrupt */ |
416 | goto put_master; | 444 | ret = devm_request_irq(&pdev->dev, xspi->irq, xilinx_spi_irq, 0, |
445 | dev_name(&pdev->dev), xspi); | ||
446 | if (ret) | ||
447 | goto put_master; | ||
417 | } | 448 | } |
418 | 449 | ||
419 | /* Register for SPI Interrupt */ | 450 | /* SPI controller initializations */ |
420 | ret = devm_request_irq(&pdev->dev, xspi->irq, xilinx_spi_irq, 0, | 451 | xspi_init_hw(xspi); |
421 | dev_name(&pdev->dev), xspi); | ||
422 | if (ret) | ||
423 | goto put_master; | ||
424 | 452 | ||
425 | ret = spi_bitbang_start(&xspi->bitbang); | 453 | ret = spi_bitbang_start(&xspi->bitbang); |
426 | if (ret) { | 454 | if (ret) { |