diff options
Diffstat (limited to 'drivers/spi/spi-tegra20-slink.c')
-rw-r--r-- | drivers/spi/spi-tegra20-slink.c | 66 |
1 files changed, 30 insertions, 36 deletions
diff --git a/drivers/spi/spi-tegra20-slink.c b/drivers/spi/spi-tegra20-slink.c index e66715ba37ed..a728bb82090f 100644 --- a/drivers/spi/spi-tegra20-slink.c +++ b/drivers/spi/spi-tegra20-slink.c | |||
@@ -33,8 +33,8 @@ | |||
33 | #include <linux/pm_runtime.h> | 33 | #include <linux/pm_runtime.h> |
34 | #include <linux/of.h> | 34 | #include <linux/of.h> |
35 | #include <linux/of_device.h> | 35 | #include <linux/of_device.h> |
36 | #include <linux/reset.h> | ||
36 | #include <linux/spi/spi.h> | 37 | #include <linux/spi/spi.h> |
37 | #include <linux/clk/tegra.h> | ||
38 | 38 | ||
39 | #define SLINK_COMMAND 0x000 | 39 | #define SLINK_COMMAND 0x000 |
40 | #define SLINK_BIT_LENGTH(x) (((x) & 0x1f) << 0) | 40 | #define SLINK_BIT_LENGTH(x) (((x) & 0x1f) << 0) |
@@ -167,10 +167,10 @@ struct tegra_slink_data { | |||
167 | spinlock_t lock; | 167 | spinlock_t lock; |
168 | 168 | ||
169 | struct clk *clk; | 169 | struct clk *clk; |
170 | struct reset_control *rst; | ||
170 | void __iomem *base; | 171 | void __iomem *base; |
171 | phys_addr_t phys; | 172 | phys_addr_t phys; |
172 | unsigned irq; | 173 | unsigned irq; |
173 | int dma_req_sel; | ||
174 | u32 spi_max_frequency; | 174 | u32 spi_max_frequency; |
175 | u32 cur_speed; | 175 | u32 cur_speed; |
176 | 176 | ||
@@ -629,15 +629,15 @@ static int tegra_slink_init_dma_param(struct tegra_slink_data *tspi, | |||
629 | dma_addr_t dma_phys; | 629 | dma_addr_t dma_phys; |
630 | int ret; | 630 | int ret; |
631 | struct dma_slave_config dma_sconfig; | 631 | struct dma_slave_config dma_sconfig; |
632 | dma_cap_mask_t mask; | ||
633 | 632 | ||
634 | dma_cap_zero(mask); | 633 | dma_chan = dma_request_slave_channel_reason(tspi->dev, |
635 | dma_cap_set(DMA_SLAVE, mask); | 634 | dma_to_memory ? "rx" : "tx"); |
636 | dma_chan = dma_request_channel(mask, NULL, NULL); | 635 | if (IS_ERR(dma_chan)) { |
637 | if (!dma_chan) { | 636 | ret = PTR_ERR(dma_chan); |
638 | dev_err(tspi->dev, | 637 | if (ret != -EPROBE_DEFER) |
639 | "Dma channel is not available, will try later\n"); | 638 | dev_err(tspi->dev, |
640 | return -EPROBE_DEFER; | 639 | "Dma channel is not available: %d\n", ret); |
640 | return ret; | ||
641 | } | 641 | } |
642 | 642 | ||
643 | dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size, | 643 | dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size, |
@@ -648,7 +648,6 @@ static int tegra_slink_init_dma_param(struct tegra_slink_data *tspi, | |||
648 | return -ENOMEM; | 648 | return -ENOMEM; |
649 | } | 649 | } |
650 | 650 | ||
651 | dma_sconfig.slave_id = tspi->dma_req_sel; | ||
652 | if (dma_to_memory) { | 651 | if (dma_to_memory) { |
653 | dma_sconfig.src_addr = tspi->phys + SLINK_RX_FIFO; | 652 | dma_sconfig.src_addr = tspi->phys + SLINK_RX_FIFO; |
654 | dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | 653 | dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
@@ -884,9 +883,9 @@ static irqreturn_t handle_cpu_based_xfer(struct tegra_slink_data *tspi) | |||
884 | dev_err(tspi->dev, | 883 | dev_err(tspi->dev, |
885 | "CpuXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg, | 884 | "CpuXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg, |
886 | tspi->command2_reg, tspi->dma_control_reg); | 885 | tspi->command2_reg, tspi->dma_control_reg); |
887 | tegra_periph_reset_assert(tspi->clk); | 886 | reset_control_assert(tspi->rst); |
888 | udelay(2); | 887 | udelay(2); |
889 | tegra_periph_reset_deassert(tspi->clk); | 888 | reset_control_deassert(tspi->rst); |
890 | complete(&tspi->xfer_completion); | 889 | complete(&tspi->xfer_completion); |
891 | goto exit; | 890 | goto exit; |
892 | } | 891 | } |
@@ -957,9 +956,9 @@ static irqreturn_t handle_dma_based_xfer(struct tegra_slink_data *tspi) | |||
957 | dev_err(tspi->dev, | 956 | dev_err(tspi->dev, |
958 | "DmaXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg, | 957 | "DmaXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg, |
959 | tspi->command2_reg, tspi->dma_control_reg); | 958 | tspi->command2_reg, tspi->dma_control_reg); |
960 | tegra_periph_reset_assert(tspi->clk); | 959 | reset_control_assert(tspi->rst); |
961 | udelay(2); | 960 | udelay(2); |
962 | tegra_periph_reset_deassert(tspi->clk); | 961 | reset_control_assert(tspi->rst); |
963 | complete(&tspi->xfer_completion); | 962 | complete(&tspi->xfer_completion); |
964 | spin_unlock_irqrestore(&tspi->lock, flags); | 963 | spin_unlock_irqrestore(&tspi->lock, flags); |
965 | return IRQ_HANDLED; | 964 | return IRQ_HANDLED; |
@@ -1020,11 +1019,6 @@ static irqreturn_t tegra_slink_isr(int irq, void *context_data) | |||
1020 | static void tegra_slink_parse_dt(struct tegra_slink_data *tspi) | 1019 | static void tegra_slink_parse_dt(struct tegra_slink_data *tspi) |
1021 | { | 1020 | { |
1022 | struct device_node *np = tspi->dev->of_node; | 1021 | struct device_node *np = tspi->dev->of_node; |
1023 | u32 of_dma[2]; | ||
1024 | |||
1025 | if (of_property_read_u32_array(np, "nvidia,dma-request-selector", | ||
1026 | of_dma, 2) >= 0) | ||
1027 | tspi->dma_req_sel = of_dma[1]; | ||
1028 | 1022 | ||
1029 | if (of_property_read_u32(np, "spi-max-frequency", | 1023 | if (of_property_read_u32(np, "spi-max-frequency", |
1030 | &tspi->spi_max_frequency)) | 1024 | &tspi->spi_max_frequency)) |
@@ -1118,25 +1112,25 @@ static int tegra_slink_probe(struct platform_device *pdev) | |||
1118 | goto exit_free_irq; | 1112 | goto exit_free_irq; |
1119 | } | 1113 | } |
1120 | 1114 | ||
1115 | tspi->rst = devm_reset_control_get(&pdev->dev, "spi"); | ||
1116 | if (IS_ERR(tspi->rst)) { | ||
1117 | dev_err(&pdev->dev, "can not get reset\n"); | ||
1118 | ret = PTR_ERR(tspi->rst); | ||
1119 | goto exit_free_irq; | ||
1120 | } | ||
1121 | |||
1121 | tspi->max_buf_size = SLINK_FIFO_DEPTH << 2; | 1122 | tspi->max_buf_size = SLINK_FIFO_DEPTH << 2; |
1122 | tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN; | 1123 | tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN; |
1123 | 1124 | ||
1124 | if (tspi->dma_req_sel) { | 1125 | ret = tegra_slink_init_dma_param(tspi, true); |
1125 | ret = tegra_slink_init_dma_param(tspi, true); | 1126 | if (ret < 0) |
1126 | if (ret < 0) { | 1127 | goto exit_free_irq; |
1127 | dev_err(&pdev->dev, "RxDma Init failed, err %d\n", ret); | 1128 | ret = tegra_slink_init_dma_param(tspi, false); |
1128 | goto exit_free_irq; | 1129 | if (ret < 0) |
1129 | } | 1130 | goto exit_rx_dma_free; |
1130 | 1131 | tspi->max_buf_size = tspi->dma_buf_size; | |
1131 | ret = tegra_slink_init_dma_param(tspi, false); | 1132 | init_completion(&tspi->tx_dma_complete); |
1132 | if (ret < 0) { | 1133 | init_completion(&tspi->rx_dma_complete); |
1133 | dev_err(&pdev->dev, "TxDma Init failed, err %d\n", ret); | ||
1134 | goto exit_rx_dma_free; | ||
1135 | } | ||
1136 | tspi->max_buf_size = tspi->dma_buf_size; | ||
1137 | init_completion(&tspi->tx_dma_complete); | ||
1138 | init_completion(&tspi->rx_dma_complete); | ||
1139 | } | ||
1140 | 1134 | ||
1141 | init_completion(&tspi->xfer_completion); | 1135 | init_completion(&tspi->xfer_completion); |
1142 | 1136 | ||