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path: root/drivers/spi/spi-tegra114.c
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Diffstat (limited to 'drivers/spi/spi-tegra114.c')
-rw-r--r--drivers/spi/spi-tegra114.c66
1 files changed, 30 insertions, 36 deletions
diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c
index aaecfb3ebf58..c8604981a058 100644
--- a/drivers/spi/spi-tegra114.c
+++ b/drivers/spi/spi-tegra114.c
@@ -17,7 +17,6 @@
17 */ 17 */
18 18
19#include <linux/clk.h> 19#include <linux/clk.h>
20#include <linux/clk/tegra.h>
21#include <linux/completion.h> 20#include <linux/completion.h>
22#include <linux/delay.h> 21#include <linux/delay.h>
23#include <linux/dmaengine.h> 22#include <linux/dmaengine.h>
@@ -34,6 +33,7 @@
34#include <linux/pm_runtime.h> 33#include <linux/pm_runtime.h>
35#include <linux/of.h> 34#include <linux/of.h>
36#include <linux/of_device.h> 35#include <linux/of_device.h>
36#include <linux/reset.h>
37#include <linux/spi/spi.h> 37#include <linux/spi/spi.h>
38 38
39#define SPI_COMMAND1 0x000 39#define SPI_COMMAND1 0x000
@@ -174,10 +174,10 @@ struct tegra_spi_data {
174 spinlock_t lock; 174 spinlock_t lock;
175 175
176 struct clk *clk; 176 struct clk *clk;
177 struct reset_control *rst;
177 void __iomem *base; 178 void __iomem *base;
178 phys_addr_t phys; 179 phys_addr_t phys;
179 unsigned irq; 180 unsigned irq;
180 int dma_req_sel;
181 u32 spi_max_frequency; 181 u32 spi_max_frequency;
182 u32 cur_speed; 182 u32 cur_speed;
183 183
@@ -600,15 +600,15 @@ static int tegra_spi_init_dma_param(struct tegra_spi_data *tspi,
600 dma_addr_t dma_phys; 600 dma_addr_t dma_phys;
601 int ret; 601 int ret;
602 struct dma_slave_config dma_sconfig; 602 struct dma_slave_config dma_sconfig;
603 dma_cap_mask_t mask;
604 603
605 dma_cap_zero(mask); 604 dma_chan = dma_request_slave_channel_reason(tspi->dev,
606 dma_cap_set(DMA_SLAVE, mask); 605 dma_to_memory ? "rx" : "tx");
607 dma_chan = dma_request_channel(mask, NULL, NULL); 606 if (IS_ERR(dma_chan)) {
608 if (!dma_chan) { 607 ret = PTR_ERR(dma_chan);
609 dev_err(tspi->dev, 608 if (ret != -EPROBE_DEFER)
610 "Dma channel is not available, will try later\n"); 609 dev_err(tspi->dev,
611 return -EPROBE_DEFER; 610 "Dma channel is not available: %d\n", ret);
611 return ret;
612 } 612 }
613 613
614 dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size, 614 dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size,
@@ -619,7 +619,6 @@ static int tegra_spi_init_dma_param(struct tegra_spi_data *tspi,
619 return -ENOMEM; 619 return -ENOMEM;
620 } 620 }
621 621
622 dma_sconfig.slave_id = tspi->dma_req_sel;
623 if (dma_to_memory) { 622 if (dma_to_memory) {
624 dma_sconfig.src_addr = tspi->phys + SPI_RX_FIFO; 623 dma_sconfig.src_addr = tspi->phys + SPI_RX_FIFO;
625 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 624 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
@@ -918,9 +917,9 @@ static irqreturn_t handle_cpu_based_xfer(struct tegra_spi_data *tspi)
918 tspi->status_reg); 917 tspi->status_reg);
919 dev_err(tspi->dev, "CpuXfer 0x%08x:0x%08x\n", 918 dev_err(tspi->dev, "CpuXfer 0x%08x:0x%08x\n",
920 tspi->command1_reg, tspi->dma_control_reg); 919 tspi->command1_reg, tspi->dma_control_reg);
921 tegra_periph_reset_assert(tspi->clk); 920 reset_control_assert(tspi->rst);
922 udelay(2); 921 udelay(2);
923 tegra_periph_reset_deassert(tspi->clk); 922 reset_control_deassert(tspi->rst);
924 complete(&tspi->xfer_completion); 923 complete(&tspi->xfer_completion);
925 goto exit; 924 goto exit;
926 } 925 }
@@ -990,9 +989,9 @@ static irqreturn_t handle_dma_based_xfer(struct tegra_spi_data *tspi)
990 tspi->status_reg); 989 tspi->status_reg);
991 dev_err(tspi->dev, "DmaXfer 0x%08x:0x%08x\n", 990 dev_err(tspi->dev, "DmaXfer 0x%08x:0x%08x\n",
992 tspi->command1_reg, tspi->dma_control_reg); 991 tspi->command1_reg, tspi->dma_control_reg);
993 tegra_periph_reset_assert(tspi->clk); 992 reset_control_assert(tspi->rst);
994 udelay(2); 993 udelay(2);
995 tegra_periph_reset_deassert(tspi->clk); 994 reset_control_deassert(tspi->rst);
996 complete(&tspi->xfer_completion); 995 complete(&tspi->xfer_completion);
997 spin_unlock_irqrestore(&tspi->lock, flags); 996 spin_unlock_irqrestore(&tspi->lock, flags);
998 return IRQ_HANDLED; 997 return IRQ_HANDLED;
@@ -1054,11 +1053,6 @@ static void tegra_spi_parse_dt(struct platform_device *pdev,
1054 struct tegra_spi_data *tspi) 1053 struct tegra_spi_data *tspi)
1055{ 1054{
1056 struct device_node *np = pdev->dev.of_node; 1055 struct device_node *np = pdev->dev.of_node;
1057 u32 of_dma[2];
1058
1059 if (of_property_read_u32_array(np, "nvidia,dma-request-selector",
1060 of_dma, 2) >= 0)
1061 tspi->dma_req_sel = of_dma[1];
1062 1056
1063 if (of_property_read_u32(np, "spi-max-frequency", 1057 if (of_property_read_u32(np, "spi-max-frequency",
1064 &tspi->spi_max_frequency)) 1058 &tspi->spi_max_frequency))
@@ -1127,25 +1121,25 @@ static int tegra_spi_probe(struct platform_device *pdev)
1127 goto exit_free_irq; 1121 goto exit_free_irq;
1128 } 1122 }
1129 1123
1124 tspi->rst = devm_reset_control_get(&pdev->dev, "spi");
1125 if (IS_ERR(tspi->rst)) {
1126 dev_err(&pdev->dev, "can not get reset\n");
1127 ret = PTR_ERR(tspi->rst);
1128 goto exit_free_irq;
1129 }
1130
1130 tspi->max_buf_size = SPI_FIFO_DEPTH << 2; 1131 tspi->max_buf_size = SPI_FIFO_DEPTH << 2;
1131 tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN; 1132 tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN;
1132 1133
1133 if (tspi->dma_req_sel) { 1134 ret = tegra_spi_init_dma_param(tspi, true);
1134 ret = tegra_spi_init_dma_param(tspi, true); 1135 if (ret < 0)
1135 if (ret < 0) { 1136 goto exit_free_irq;
1136 dev_err(&pdev->dev, "RxDma Init failed, err %d\n", ret); 1137 ret = tegra_spi_init_dma_param(tspi, false);
1137 goto exit_free_irq; 1138 if (ret < 0)
1138 } 1139 goto exit_rx_dma_free;
1139 1140 tspi->max_buf_size = tspi->dma_buf_size;
1140 ret = tegra_spi_init_dma_param(tspi, false); 1141 init_completion(&tspi->tx_dma_complete);
1141 if (ret < 0) { 1142 init_completion(&tspi->rx_dma_complete);
1142 dev_err(&pdev->dev, "TxDma Init failed, err %d\n", ret);
1143 goto exit_rx_dma_free;
1144 }
1145 tspi->max_buf_size = tspi->dma_buf_size;
1146 init_completion(&tspi->tx_dma_complete);
1147 init_completion(&tspi->rx_dma_complete);
1148 }
1149 1143
1150 init_completion(&tspi->xfer_completion); 1144 init_completion(&tspi->xfer_completion);
1151 1145