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path: root/drivers/spi/spi-tegra114.c
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Diffstat (limited to 'drivers/spi/spi-tegra114.c')
-rw-r--r--drivers/spi/spi-tegra114.c18
1 files changed, 13 insertions, 5 deletions
diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c
index aaecfb3ebf58..f62e6e5e90e3 100644
--- a/drivers/spi/spi-tegra114.c
+++ b/drivers/spi/spi-tegra114.c
@@ -17,7 +17,6 @@
17 */ 17 */
18 18
19#include <linux/clk.h> 19#include <linux/clk.h>
20#include <linux/clk/tegra.h>
21#include <linux/completion.h> 20#include <linux/completion.h>
22#include <linux/delay.h> 21#include <linux/delay.h>
23#include <linux/dmaengine.h> 22#include <linux/dmaengine.h>
@@ -34,6 +33,7 @@
34#include <linux/pm_runtime.h> 33#include <linux/pm_runtime.h>
35#include <linux/of.h> 34#include <linux/of.h>
36#include <linux/of_device.h> 35#include <linux/of_device.h>
36#include <linux/reset.h>
37#include <linux/spi/spi.h> 37#include <linux/spi/spi.h>
38 38
39#define SPI_COMMAND1 0x000 39#define SPI_COMMAND1 0x000
@@ -174,6 +174,7 @@ struct tegra_spi_data {
174 spinlock_t lock; 174 spinlock_t lock;
175 175
176 struct clk *clk; 176 struct clk *clk;
177 struct reset_control *rst;
177 void __iomem *base; 178 void __iomem *base;
178 phys_addr_t phys; 179 phys_addr_t phys;
179 unsigned irq; 180 unsigned irq;
@@ -918,9 +919,9 @@ static irqreturn_t handle_cpu_based_xfer(struct tegra_spi_data *tspi)
918 tspi->status_reg); 919 tspi->status_reg);
919 dev_err(tspi->dev, "CpuXfer 0x%08x:0x%08x\n", 920 dev_err(tspi->dev, "CpuXfer 0x%08x:0x%08x\n",
920 tspi->command1_reg, tspi->dma_control_reg); 921 tspi->command1_reg, tspi->dma_control_reg);
921 tegra_periph_reset_assert(tspi->clk); 922 reset_control_assert(tspi->rst);
922 udelay(2); 923 udelay(2);
923 tegra_periph_reset_deassert(tspi->clk); 924 reset_control_deassert(tspi->rst);
924 complete(&tspi->xfer_completion); 925 complete(&tspi->xfer_completion);
925 goto exit; 926 goto exit;
926 } 927 }
@@ -990,9 +991,9 @@ static irqreturn_t handle_dma_based_xfer(struct tegra_spi_data *tspi)
990 tspi->status_reg); 991 tspi->status_reg);
991 dev_err(tspi->dev, "DmaXfer 0x%08x:0x%08x\n", 992 dev_err(tspi->dev, "DmaXfer 0x%08x:0x%08x\n",
992 tspi->command1_reg, tspi->dma_control_reg); 993 tspi->command1_reg, tspi->dma_control_reg);
993 tegra_periph_reset_assert(tspi->clk); 994 reset_control_assert(tspi->rst);
994 udelay(2); 995 udelay(2);
995 tegra_periph_reset_deassert(tspi->clk); 996 reset_control_deassert(tspi->rst);
996 complete(&tspi->xfer_completion); 997 complete(&tspi->xfer_completion);
997 spin_unlock_irqrestore(&tspi->lock, flags); 998 spin_unlock_irqrestore(&tspi->lock, flags);
998 return IRQ_HANDLED; 999 return IRQ_HANDLED;
@@ -1127,6 +1128,13 @@ static int tegra_spi_probe(struct platform_device *pdev)
1127 goto exit_free_irq; 1128 goto exit_free_irq;
1128 } 1129 }
1129 1130
1131 tspi->rst = devm_reset_control_get(&pdev->dev, "spi");
1132 if (IS_ERR(tspi->rst)) {
1133 dev_err(&pdev->dev, "can not get reset\n");
1134 ret = PTR_ERR(tspi->rst);
1135 goto exit_free_irq;
1136 }
1137
1130 tspi->max_buf_size = SPI_FIFO_DEPTH << 2; 1138 tspi->max_buf_size = SPI_FIFO_DEPTH << 2;
1131 tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN; 1139 tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN;
1132 1140