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path: root/drivers/spi/spi-sirf.c
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Diffstat (limited to 'drivers/spi/spi-sirf.c')
-rw-r--r--drivers/spi/spi-sirf.c321
1 files changed, 186 insertions, 135 deletions
diff --git a/drivers/spi/spi-sirf.c b/drivers/spi/spi-sirf.c
index 1a77ad52812f..95ac276eaafe 100644
--- a/drivers/spi/spi-sirf.c
+++ b/drivers/spi/spi-sirf.c
@@ -10,6 +10,7 @@
10#include <linux/kernel.h> 10#include <linux/kernel.h>
11#include <linux/slab.h> 11#include <linux/slab.h>
12#include <linux/clk.h> 12#include <linux/clk.h>
13#include <linux/completion.h>
13#include <linux/interrupt.h> 14#include <linux/interrupt.h>
14#include <linux/io.h> 15#include <linux/io.h>
15#include <linux/of.h> 16#include <linux/of.h>
@@ -85,6 +86,7 @@
85#define SIRFSOC_SPI_TX_DONE BIT(1) 86#define SIRFSOC_SPI_TX_DONE BIT(1)
86#define SIRFSOC_SPI_RX_OFLOW BIT(2) 87#define SIRFSOC_SPI_RX_OFLOW BIT(2)
87#define SIRFSOC_SPI_TX_UFLOW BIT(3) 88#define SIRFSOC_SPI_TX_UFLOW BIT(3)
89#define SIRFSOC_SPI_RX_IO_DMA BIT(4)
88#define SIRFSOC_SPI_RX_FIFO_FULL BIT(6) 90#define SIRFSOC_SPI_RX_FIFO_FULL BIT(6)
89#define SIRFSOC_SPI_TXFIFO_EMPTY BIT(7) 91#define SIRFSOC_SPI_TXFIFO_EMPTY BIT(7)
90#define SIRFSOC_SPI_RXFIFO_THD_REACH BIT(8) 92#define SIRFSOC_SPI_RXFIFO_THD_REACH BIT(8)
@@ -264,41 +266,34 @@ static irqreturn_t spi_sirfsoc_irq(int irq, void *dev_id)
264{ 266{
265 struct sirfsoc_spi *sspi = dev_id; 267 struct sirfsoc_spi *sspi = dev_id;
266 u32 spi_stat = readl(sspi->base + SIRFSOC_SPI_INT_STATUS); 268 u32 spi_stat = readl(sspi->base + SIRFSOC_SPI_INT_STATUS);
267
268 writel(spi_stat, sspi->base + SIRFSOC_SPI_INT_STATUS);
269
270 if (sspi->tx_by_cmd && (spi_stat & SIRFSOC_SPI_FRM_END)) { 269 if (sspi->tx_by_cmd && (spi_stat & SIRFSOC_SPI_FRM_END)) {
271 complete(&sspi->tx_done); 270 complete(&sspi->tx_done);
272 writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN); 271 writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN);
272 writel(SIRFSOC_SPI_INT_MASK_ALL,
273 sspi->base + SIRFSOC_SPI_INT_STATUS);
273 return IRQ_HANDLED; 274 return IRQ_HANDLED;
274 } 275 }
275 276
276 /* Error Conditions */ 277 /* Error Conditions */
277 if (spi_stat & SIRFSOC_SPI_RX_OFLOW || 278 if (spi_stat & SIRFSOC_SPI_RX_OFLOW ||
278 spi_stat & SIRFSOC_SPI_TX_UFLOW) { 279 spi_stat & SIRFSOC_SPI_TX_UFLOW) {
280 complete(&sspi->tx_done);
279 complete(&sspi->rx_done); 281 complete(&sspi->rx_done);
280 writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN); 282 writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN);
283 writel(SIRFSOC_SPI_INT_MASK_ALL,
284 sspi->base + SIRFSOC_SPI_INT_STATUS);
285 return IRQ_HANDLED;
281 } 286 }
287 if (spi_stat & SIRFSOC_SPI_TXFIFO_EMPTY)
288 complete(&sspi->tx_done);
289 while (!(readl(sspi->base + SIRFSOC_SPI_INT_STATUS) &
290 SIRFSOC_SPI_RX_IO_DMA))
291 cpu_relax();
292 complete(&sspi->rx_done);
293 writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN);
294 writel(SIRFSOC_SPI_INT_MASK_ALL,
295 sspi->base + SIRFSOC_SPI_INT_STATUS);
282 296
283 if (spi_stat & (SIRFSOC_SPI_FRM_END
284 | SIRFSOC_SPI_RXFIFO_THD_REACH))
285 while (!((readl(sspi->base + SIRFSOC_SPI_RXFIFO_STATUS)
286 & SIRFSOC_SPI_FIFO_EMPTY)) &&
287 sspi->left_rx_word)
288 sspi->rx_word(sspi);
289
290 if (spi_stat & (SIRFSOC_SPI_FIFO_EMPTY
291 | SIRFSOC_SPI_TXFIFO_THD_REACH))
292 while (!((readl(sspi->base + SIRFSOC_SPI_TXFIFO_STATUS)
293 & SIRFSOC_SPI_FIFO_FULL)) &&
294 sspi->left_tx_word)
295 sspi->tx_word(sspi);
296
297 /* Received all words */
298 if ((sspi->left_rx_word == 0) && (sspi->left_tx_word == 0)) {
299 complete(&sspi->rx_done);
300 writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN);
301 }
302 return IRQ_HANDLED; 297 return IRQ_HANDLED;
303} 298}
304 299
@@ -309,59 +304,51 @@ static void spi_sirfsoc_dma_fini_callback(void *data)
309 complete(dma_complete); 304 complete(dma_complete);
310} 305}
311 306
312static int spi_sirfsoc_transfer(struct spi_device *spi, struct spi_transfer *t) 307static int spi_sirfsoc_cmd_transfer(struct spi_device *spi,
308 struct spi_transfer *t)
313{ 309{
314 struct sirfsoc_spi *sspi; 310 struct sirfsoc_spi *sspi;
315 int timeout = t->len * 10; 311 int timeout = t->len * 10;
316 sspi = spi_master_get_devdata(spi->master); 312 u32 cmd;
317
318 sspi->tx = t->tx_buf ? t->tx_buf : sspi->dummypage;
319 sspi->rx = t->rx_buf ? t->rx_buf : sspi->dummypage;
320 sspi->left_tx_word = sspi->left_rx_word = t->len / sspi->word_width;
321 reinit_completion(&sspi->rx_done);
322 reinit_completion(&sspi->tx_done);
323 313
324 writel(SIRFSOC_SPI_INT_MASK_ALL, sspi->base + SIRFSOC_SPI_INT_STATUS); 314 sspi = spi_master_get_devdata(spi->master);
325 315 memcpy(&cmd, sspi->tx, t->len);
326 /* 316 if (sspi->word_width == 1 && !(spi->mode & SPI_LSB_FIRST))
327 * fill tx_buf into command register and wait for its completion 317 cmd = cpu_to_be32(cmd) >>
328 */ 318 ((SIRFSOC_MAX_CMD_BYTES - t->len) * 8);
329 if (sspi->tx_by_cmd) { 319 if (sspi->word_width == 2 && t->len == 4 &&
330 u32 cmd; 320 (!(spi->mode & SPI_LSB_FIRST)))
331 memcpy(&cmd, sspi->tx, t->len); 321 cmd = ((cmd & 0xffff) << 16) | (cmd >> 16);
332 322 writel(cmd, sspi->base + SIRFSOC_SPI_CMD);
333 if (sspi->word_width == 1 && !(spi->mode & SPI_LSB_FIRST)) 323 writel(SIRFSOC_SPI_FRM_END_INT_EN,
334 cmd = cpu_to_be32(cmd) >> 324 sspi->base + SIRFSOC_SPI_INT_EN);
335 ((SIRFSOC_MAX_CMD_BYTES - t->len) * 8); 325 writel(SIRFSOC_SPI_CMD_TX_EN,
336 if (sspi->word_width == 2 && t->len == 4 && 326 sspi->base + SIRFSOC_SPI_TX_RX_EN);
337 (!(spi->mode & SPI_LSB_FIRST))) 327 if (wait_for_completion_timeout(&sspi->tx_done, timeout) == 0) {
338 cmd = ((cmd & 0xffff) << 16) | (cmd >> 16); 328 dev_err(&spi->dev, "cmd transfer timeout\n");
339 329 return 0;
340 writel(cmd, sspi->base + SIRFSOC_SPI_CMD); 330 }
341 writel(SIRFSOC_SPI_FRM_END_INT_EN,
342 sspi->base + SIRFSOC_SPI_INT_EN);
343 writel(SIRFSOC_SPI_CMD_TX_EN,
344 sspi->base + SIRFSOC_SPI_TX_RX_EN);
345 331
346 if (wait_for_completion_timeout(&sspi->tx_done, timeout) == 0) { 332 return t->len;
347 dev_err(&spi->dev, "transfer timeout\n"); 333}
348 return 0;
349 }
350 334
351 return t->len; 335static void spi_sirfsoc_dma_transfer(struct spi_device *spi,
352 } 336 struct spi_transfer *t)
337{
338 struct sirfsoc_spi *sspi;
339 struct dma_async_tx_descriptor *rx_desc, *tx_desc;
340 int timeout = t->len * 10;
353 341
354 if (sspi->left_tx_word == 1) { 342 sspi = spi_master_get_devdata(spi->master);
355 writel(readl(sspi->base + SIRFSOC_SPI_CTRL) | 343 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
356 SIRFSOC_SPI_ENA_AUTO_CLR, 344 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
357 sspi->base + SIRFSOC_SPI_CTRL); 345 writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
358 writel(0, sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN); 346 writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
359 writel(0, sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN); 347 writel(0, sspi->base + SIRFSOC_SPI_INT_EN);
360 } else if ((sspi->left_tx_word > 1) && (sspi->left_tx_word < 348 writel(SIRFSOC_SPI_INT_MASK_ALL, sspi->base + SIRFSOC_SPI_INT_STATUS);
361 SIRFSOC_SPI_DAT_FRM_LEN_MAX)) { 349 if (sspi->left_tx_word < SIRFSOC_SPI_DAT_FRM_LEN_MAX) {
362 writel(readl(sspi->base + SIRFSOC_SPI_CTRL) | 350 writel(readl(sspi->base + SIRFSOC_SPI_CTRL) |
363 SIRFSOC_SPI_MUL_DAT_MODE | 351 SIRFSOC_SPI_ENA_AUTO_CLR | SIRFSOC_SPI_MUL_DAT_MODE,
364 SIRFSOC_SPI_ENA_AUTO_CLR,
365 sspi->base + SIRFSOC_SPI_CTRL); 352 sspi->base + SIRFSOC_SPI_CTRL);
366 writel(sspi->left_tx_word - 1, 353 writel(sspi->left_tx_word - 1,
367 sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN); 354 sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN);
@@ -373,76 +360,122 @@ static int spi_sirfsoc_transfer(struct spi_device *spi, struct spi_transfer *t)
373 writel(0, sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN); 360 writel(0, sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN);
374 writel(0, sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN); 361 writel(0, sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN);
375 } 362 }
376 363 sspi->dst_start = dma_map_single(&spi->dev, sspi->rx, t->len,
377 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP); 364 (t->tx_buf != t->rx_buf) ?
378 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP); 365 DMA_FROM_DEVICE : DMA_BIDIRECTIONAL);
379 writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP); 366 rx_desc = dmaengine_prep_slave_single(sspi->rx_chan,
380 writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP); 367 sspi->dst_start, t->len, DMA_DEV_TO_MEM,
381 368 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
382 if (IS_DMA_VALID(t)) { 369 rx_desc->callback = spi_sirfsoc_dma_fini_callback;
383 struct dma_async_tx_descriptor *rx_desc, *tx_desc; 370 rx_desc->callback_param = &sspi->rx_done;
384 371
385 sspi->dst_start = dma_map_single(&spi->dev, sspi->rx, t->len, DMA_FROM_DEVICE); 372 sspi->src_start = dma_map_single(&spi->dev, (void *)sspi->tx, t->len,
386 rx_desc = dmaengine_prep_slave_single(sspi->rx_chan, 373 (t->tx_buf != t->rx_buf) ?
387 sspi->dst_start, t->len, DMA_DEV_TO_MEM, 374 DMA_TO_DEVICE : DMA_BIDIRECTIONAL);
388 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 375 tx_desc = dmaengine_prep_slave_single(sspi->tx_chan,
389 rx_desc->callback = spi_sirfsoc_dma_fini_callback; 376 sspi->src_start, t->len, DMA_MEM_TO_DEV,
390 rx_desc->callback_param = &sspi->rx_done; 377 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
391 378 tx_desc->callback = spi_sirfsoc_dma_fini_callback;
392 sspi->src_start = dma_map_single(&spi->dev, (void *)sspi->tx, t->len, DMA_TO_DEVICE); 379 tx_desc->callback_param = &sspi->tx_done;
393 tx_desc = dmaengine_prep_slave_single(sspi->tx_chan, 380
394 sspi->src_start, t->len, DMA_MEM_TO_DEV, 381 dmaengine_submit(tx_desc);
395 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 382 dmaengine_submit(rx_desc);
396 tx_desc->callback = spi_sirfsoc_dma_fini_callback; 383 dma_async_issue_pending(sspi->tx_chan);
397 tx_desc->callback_param = &sspi->tx_done; 384 dma_async_issue_pending(sspi->rx_chan);
398 385 writel(SIRFSOC_SPI_RX_EN | SIRFSOC_SPI_TX_EN,
399 dmaengine_submit(tx_desc); 386 sspi->base + SIRFSOC_SPI_TX_RX_EN);
400 dmaengine_submit(rx_desc); 387 if (wait_for_completion_timeout(&sspi->rx_done, timeout) == 0) {
401 dma_async_issue_pending(sspi->tx_chan);
402 dma_async_issue_pending(sspi->rx_chan);
403 } else {
404 /* Send the first word to trigger the whole tx/rx process */
405 sspi->tx_word(sspi);
406
407 writel(SIRFSOC_SPI_RX_OFLOW_INT_EN | SIRFSOC_SPI_TX_UFLOW_INT_EN |
408 SIRFSOC_SPI_RXFIFO_THD_INT_EN | SIRFSOC_SPI_TXFIFO_THD_INT_EN |
409 SIRFSOC_SPI_FRM_END_INT_EN | SIRFSOC_SPI_RXFIFO_FULL_INT_EN |
410 SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN, sspi->base + SIRFSOC_SPI_INT_EN);
411 }
412
413 writel(SIRFSOC_SPI_RX_EN | SIRFSOC_SPI_TX_EN, sspi->base + SIRFSOC_SPI_TX_RX_EN);
414
415 if (!IS_DMA_VALID(t)) { /* for PIO */
416 if (wait_for_completion_timeout(&sspi->rx_done, timeout) == 0)
417 dev_err(&spi->dev, "transfer timeout\n");
418 } else if (wait_for_completion_timeout(&sspi->rx_done, timeout) == 0) {
419 dev_err(&spi->dev, "transfer timeout\n"); 388 dev_err(&spi->dev, "transfer timeout\n");
420 dmaengine_terminate_all(sspi->rx_chan); 389 dmaengine_terminate_all(sspi->rx_chan);
421 } else 390 } else
422 sspi->left_rx_word = 0; 391 sspi->left_rx_word = 0;
423
424 /* 392 /*
425 * we only wait tx-done event if transferring by DMA. for PIO, 393 * we only wait tx-done event if transferring by DMA. for PIO,
426 * we get rx data by writing tx data, so if rx is done, tx has 394 * we get rx data by writing tx data, so if rx is done, tx has
427 * done earlier 395 * done earlier
428 */ 396 */
429 if (IS_DMA_VALID(t)) { 397 if (wait_for_completion_timeout(&sspi->tx_done, timeout) == 0) {
430 if (wait_for_completion_timeout(&sspi->tx_done, timeout) == 0) { 398 dev_err(&spi->dev, "transfer timeout\n");
431 dev_err(&spi->dev, "transfer timeout\n"); 399 dmaengine_terminate_all(sspi->tx_chan);
432 dmaengine_terminate_all(sspi->tx_chan);
433 }
434 }
435
436 if (IS_DMA_VALID(t)) {
437 dma_unmap_single(&spi->dev, sspi->src_start, t->len, DMA_TO_DEVICE);
438 dma_unmap_single(&spi->dev, sspi->dst_start, t->len, DMA_FROM_DEVICE);
439 } 400 }
440 401 dma_unmap_single(&spi->dev, sspi->src_start, t->len, DMA_TO_DEVICE);
402 dma_unmap_single(&spi->dev, sspi->dst_start, t->len, DMA_FROM_DEVICE);
441 /* TX, RX FIFO stop */ 403 /* TX, RX FIFO stop */
442 writel(0, sspi->base + SIRFSOC_SPI_RXFIFO_OP); 404 writel(0, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
443 writel(0, sspi->base + SIRFSOC_SPI_TXFIFO_OP); 405 writel(0, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
444 writel(0, sspi->base + SIRFSOC_SPI_TX_RX_EN); 406 if (sspi->left_tx_word >= SIRFSOC_SPI_DAT_FRM_LEN_MAX)
445 writel(0, sspi->base + SIRFSOC_SPI_INT_EN); 407 writel(0, sspi->base + SIRFSOC_SPI_TX_RX_EN);
408}
409
410static void spi_sirfsoc_pio_transfer(struct spi_device *spi,
411 struct spi_transfer *t)
412{
413 struct sirfsoc_spi *sspi;
414 int timeout = t->len * 10;
415
416 sspi = spi_master_get_devdata(spi->master);
417 do {
418 writel(SIRFSOC_SPI_FIFO_RESET,
419 sspi->base + SIRFSOC_SPI_RXFIFO_OP);
420 writel(SIRFSOC_SPI_FIFO_RESET,
421 sspi->base + SIRFSOC_SPI_TXFIFO_OP);
422 writel(SIRFSOC_SPI_FIFO_START,
423 sspi->base + SIRFSOC_SPI_RXFIFO_OP);
424 writel(SIRFSOC_SPI_FIFO_START,
425 sspi->base + SIRFSOC_SPI_TXFIFO_OP);
426 writel(0, sspi->base + SIRFSOC_SPI_INT_EN);
427 writel(SIRFSOC_SPI_INT_MASK_ALL,
428 sspi->base + SIRFSOC_SPI_INT_STATUS);
429 writel(readl(sspi->base + SIRFSOC_SPI_CTRL) |
430 SIRFSOC_SPI_MUL_DAT_MODE | SIRFSOC_SPI_ENA_AUTO_CLR,
431 sspi->base + SIRFSOC_SPI_CTRL);
432 writel(min(sspi->left_tx_word, (u32)(256 / sspi->word_width))
433 - 1, sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN);
434 writel(min(sspi->left_rx_word, (u32)(256 / sspi->word_width))
435 - 1, sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN);
436 while (!((readl(sspi->base + SIRFSOC_SPI_TXFIFO_STATUS)
437 & SIRFSOC_SPI_FIFO_FULL)) && sspi->left_tx_word)
438 sspi->tx_word(sspi);
439 writel(SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN |
440 SIRFSOC_SPI_TX_UFLOW_INT_EN |
441 SIRFSOC_SPI_RX_OFLOW_INT_EN,
442 sspi->base + SIRFSOC_SPI_INT_EN);
443 writel(SIRFSOC_SPI_RX_EN | SIRFSOC_SPI_TX_EN,
444 sspi->base + SIRFSOC_SPI_TX_RX_EN);
445 if (!wait_for_completion_timeout(&sspi->tx_done, timeout) ||
446 !wait_for_completion_timeout(&sspi->rx_done, timeout)) {
447 dev_err(&spi->dev, "transfer timeout\n");
448 break;
449 }
450 while (!((readl(sspi->base + SIRFSOC_SPI_RXFIFO_STATUS)
451 & SIRFSOC_SPI_FIFO_EMPTY)) && sspi->left_rx_word)
452 sspi->rx_word(sspi);
453 writel(0, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
454 writel(0, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
455 } while (sspi->left_tx_word != 0 || sspi->left_rx_word != 0);
456}
457
458static int spi_sirfsoc_transfer(struct spi_device *spi, struct spi_transfer *t)
459{
460 struct sirfsoc_spi *sspi;
461 sspi = spi_master_get_devdata(spi->master);
462
463 sspi->tx = t->tx_buf ? t->tx_buf : sspi->dummypage;
464 sspi->rx = t->rx_buf ? t->rx_buf : sspi->dummypage;
465 sspi->left_tx_word = sspi->left_rx_word = t->len / sspi->word_width;
466 reinit_completion(&sspi->rx_done);
467 reinit_completion(&sspi->tx_done);
468 /*
469 * in the transfer, if transfer data using command register with rx_buf
470 * null, just fill command data into command register and wait for its
471 * completion.
472 */
473 if (sspi->tx_by_cmd)
474 spi_sirfsoc_cmd_transfer(spi, t);
475 else if (IS_DMA_VALID(t))
476 spi_sirfsoc_dma_transfer(spi, t);
477 else
478 spi_sirfsoc_pio_transfer(spi, t);
446 479
447 return t->len - sspi->left_rx_word * sspi->word_width; 480 return t->len - sspi->left_rx_word * sspi->word_width;
448} 481}
@@ -470,7 +503,16 @@ static void spi_sirfsoc_chipselect(struct spi_device *spi, int value)
470 writel(regval, sspi->base + SIRFSOC_SPI_CTRL); 503 writel(regval, sspi->base + SIRFSOC_SPI_CTRL);
471 } else { 504 } else {
472 int gpio = sspi->chipselect[spi->chip_select]; 505 int gpio = sspi->chipselect[spi->chip_select];
473 gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1); 506 switch (value) {
507 case BITBANG_CS_ACTIVE:
508 gpio_direction_output(gpio,
509 spi->mode & SPI_CS_HIGH ? 1 : 0);
510 break;
511 case BITBANG_CS_INACTIVE:
512 gpio_direction_output(gpio,
513 spi->mode & SPI_CS_HIGH ? 0 : 1);
514 break;
515 }
474 } 516 }
475} 517}
476 518
@@ -503,7 +545,8 @@ spi_sirfsoc_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
503 break; 545 break;
504 case 12: 546 case 12:
505 case 16: 547 case 16:
506 regval |= (bits_per_word == 12) ? SIRFSOC_SPI_TRAN_DAT_FORMAT_12 : 548 regval |= (bits_per_word == 12) ?
549 SIRFSOC_SPI_TRAN_DAT_FORMAT_12 :
507 SIRFSOC_SPI_TRAN_DAT_FORMAT_16; 550 SIRFSOC_SPI_TRAN_DAT_FORMAT_16;
508 sspi->rx_word = spi_sirfsoc_rx_word_u16; 551 sspi->rx_word = spi_sirfsoc_rx_word_u16;
509 sspi->tx_word = spi_sirfsoc_tx_word_u16; 552 sspi->tx_word = spi_sirfsoc_tx_word_u16;
@@ -531,8 +574,8 @@ spi_sirfsoc_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
531 regval |= SIRFSOC_SPI_CLK_IDLE_STAT; 574 regval |= SIRFSOC_SPI_CLK_IDLE_STAT;
532 575
533 /* 576 /*
534 * Data should be driven at least 1/2 cycle before the fetch edge to make 577 * Data should be driven at least 1/2 cycle before the fetch edge
535 * sure that data gets stable at the fetch edge. 578 * to make sure that data gets stable at the fetch edge.
536 */ 579 */
537 if (((spi->mode & SPI_CPOL) && (spi->mode & SPI_CPHA)) || 580 if (((spi->mode & SPI_CPOL) && (spi->mode & SPI_CPHA)) ||
538 (!(spi->mode & SPI_CPOL) && !(spi->mode & SPI_CPHA))) 581 (!(spi->mode & SPI_CPOL) && !(spi->mode & SPI_CPHA)))
@@ -559,16 +602,24 @@ spi_sirfsoc_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
559 regval &= ~SIRFSOC_SPI_CMD_MODE; 602 regval &= ~SIRFSOC_SPI_CMD_MODE;
560 sspi->tx_by_cmd = false; 603 sspi->tx_by_cmd = false;
561 } 604 }
605 /*
606 * set spi controller in RISC chipselect mode, we are controlling CS by
607 * software BITBANG_CS_ACTIVE and BITBANG_CS_INACTIVE.
608 */
609 regval |= SIRFSOC_SPI_CS_IO_MODE;
562 writel(regval, sspi->base + SIRFSOC_SPI_CTRL); 610 writel(regval, sspi->base + SIRFSOC_SPI_CTRL);
563 611
564 if (IS_DMA_VALID(t)) { 612 if (IS_DMA_VALID(t)) {
565 /* Enable DMA mode for RX, TX */ 613 /* Enable DMA mode for RX, TX */
566 writel(0, sspi->base + SIRFSOC_SPI_TX_DMA_IO_CTRL); 614 writel(0, sspi->base + SIRFSOC_SPI_TX_DMA_IO_CTRL);
567 writel(SIRFSOC_SPI_RX_DMA_FLUSH, sspi->base + SIRFSOC_SPI_RX_DMA_IO_CTRL); 615 writel(SIRFSOC_SPI_RX_DMA_FLUSH,
616 sspi->base + SIRFSOC_SPI_RX_DMA_IO_CTRL);
568 } else { 617 } else {
569 /* Enable IO mode for RX, TX */ 618 /* Enable IO mode for RX, TX */
570 writel(SIRFSOC_SPI_IO_MODE_SEL, sspi->base + SIRFSOC_SPI_TX_DMA_IO_CTRL); 619 writel(SIRFSOC_SPI_IO_MODE_SEL,
571 writel(SIRFSOC_SPI_IO_MODE_SEL, sspi->base + SIRFSOC_SPI_RX_DMA_IO_CTRL); 620 sspi->base + SIRFSOC_SPI_TX_DMA_IO_CTRL);
621 writel(SIRFSOC_SPI_IO_MODE_SEL,
622 sspi->base + SIRFSOC_SPI_RX_DMA_IO_CTRL);
572 } 623 }
573 624
574 return 0; 625 return 0;
@@ -598,7 +649,8 @@ static int spi_sirfsoc_probe(struct platform_device *pdev)
598 goto err_cs; 649 goto err_cs;
599 } 650 }
600 651
601 master = spi_alloc_master(&pdev->dev, sizeof(*sspi) + sizeof(int) * num_cs); 652 master = spi_alloc_master(&pdev->dev,
653 sizeof(*sspi) + sizeof(int) * num_cs);
602 if (!master) { 654 if (!master) {
603 dev_err(&pdev->dev, "Unable to allocate SPI master\n"); 655 dev_err(&pdev->dev, "Unable to allocate SPI master\n");
604 return -ENOMEM; 656 return -ENOMEM;
@@ -794,8 +846,7 @@ static struct platform_driver spi_sirfsoc_driver = {
794 .remove = spi_sirfsoc_remove, 846 .remove = spi_sirfsoc_remove,
795}; 847};
796module_platform_driver(spi_sirfsoc_driver); 848module_platform_driver(spi_sirfsoc_driver);
797
798MODULE_DESCRIPTION("SiRF SoC SPI master driver"); 849MODULE_DESCRIPTION("SiRF SoC SPI master driver");
799MODULE_AUTHOR("Zhiwu Song <Zhiwu.Song@csr.com>, " 850MODULE_AUTHOR("Zhiwu Song <Zhiwu.Song@csr.com>");
800 "Barry Song <Baohua.Song@csr.com>"); 851MODULE_AUTHOR("Barry Song <Baohua.Song@csr.com>");
801MODULE_LICENSE("GPL v2"); 852MODULE_LICENSE("GPL v2");
generated by cgit v1.2.2 (git 2.25.0) at 2025-05-29 10:17:26 -0400