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-rw-r--r--drivers/spi/spi-rspi.c363
1 files changed, 195 insertions, 168 deletions
diff --git a/drivers/spi/spi-rspi.c b/drivers/spi/spi-rspi.c
index 9e829cee7357..28987d9fcfe5 100644
--- a/drivers/spi/spi-rspi.c
+++ b/drivers/spi/spi-rspi.c
@@ -37,117 +37,145 @@
37#include <linux/spi/spi.h> 37#include <linux/spi/spi.h>
38#include <linux/spi/rspi.h> 38#include <linux/spi/rspi.h>
39 39
40#define RSPI_SPCR 0x00 40#define RSPI_SPCR 0x00 /* Control Register */
41#define RSPI_SSLP 0x01 41#define RSPI_SSLP 0x01 /* Slave Select Polarity Register */
42#define RSPI_SPPCR 0x02 42#define RSPI_SPPCR 0x02 /* Pin Control Register */
43#define RSPI_SPSR 0x03 43#define RSPI_SPSR 0x03 /* Status Register */
44#define RSPI_SPDR 0x04 44#define RSPI_SPDR 0x04 /* Data Register */
45#define RSPI_SPSCR 0x08 45#define RSPI_SPSCR 0x08 /* Sequence Control Register */
46#define RSPI_SPSSR 0x09 46#define RSPI_SPSSR 0x09 /* Sequence Status Register */
47#define RSPI_SPBR 0x0a 47#define RSPI_SPBR 0x0a /* Bit Rate Register */
48#define RSPI_SPDCR 0x0b 48#define RSPI_SPDCR 0x0b /* Data Control Register */
49#define RSPI_SPCKD 0x0c 49#define RSPI_SPCKD 0x0c /* Clock Delay Register */
50#define RSPI_SSLND 0x0d 50#define RSPI_SSLND 0x0d /* Slave Select Negation Delay Register */
51#define RSPI_SPND 0x0e 51#define RSPI_SPND 0x0e /* Next-Access Delay Register */
52#define RSPI_SPCR2 0x0f 52#define RSPI_SPCR2 0x0f /* Control Register 2 */
53#define RSPI_SPCMD0 0x10 53#define RSPI_SPCMD0 0x10 /* Command Register 0 */
54#define RSPI_SPCMD1 0x12 54#define RSPI_SPCMD1 0x12 /* Command Register 1 */
55#define RSPI_SPCMD2 0x14 55#define RSPI_SPCMD2 0x14 /* Command Register 2 */
56#define RSPI_SPCMD3 0x16 56#define RSPI_SPCMD3 0x16 /* Command Register 3 */
57#define RSPI_SPCMD4 0x18 57#define RSPI_SPCMD4 0x18 /* Command Register 4 */
58#define RSPI_SPCMD5 0x1a 58#define RSPI_SPCMD5 0x1a /* Command Register 5 */
59#define RSPI_SPCMD6 0x1c 59#define RSPI_SPCMD6 0x1c /* Command Register 6 */
60#define RSPI_SPCMD7 0x1e 60#define RSPI_SPCMD7 0x1e /* Command Register 7 */
61#define RSPI_SPBFCR 0x20 /* Buffer Control Register */
62#define RSPI_SPBFDR 0x22 /* Buffer Data Count Setting Register */
61 63
62/*qspi only */ 64/*qspi only */
63#define QSPI_SPBFCR 0x18 65#define QSPI_SPBFCR 0x18 /* Buffer Control Register */
64#define QSPI_SPBDCR 0x1a 66#define QSPI_SPBDCR 0x1a /* Buffer Data Count Register */
65#define QSPI_SPBMUL0 0x1c 67#define QSPI_SPBMUL0 0x1c /* Transfer Data Length Multiplier Setting Register 0 */
66#define QSPI_SPBMUL1 0x20 68#define QSPI_SPBMUL1 0x20 /* Transfer Data Length Multiplier Setting Register 1 */
67#define QSPI_SPBMUL2 0x24 69#define QSPI_SPBMUL2 0x24 /* Transfer Data Length Multiplier Setting Register 2 */
68#define QSPI_SPBMUL3 0x28 70#define QSPI_SPBMUL3 0x28 /* Transfer Data Length Multiplier Setting Register 3 */
69 71
70/* SPCR */ 72/* SPCR - Control Register */
71#define SPCR_SPRIE 0x80 73#define SPCR_SPRIE 0x80 /* Receive Interrupt Enable */
72#define SPCR_SPE 0x40 74#define SPCR_SPE 0x40 /* Function Enable */
73#define SPCR_SPTIE 0x20 75#define SPCR_SPTIE 0x20 /* Transmit Interrupt Enable */
74#define SPCR_SPEIE 0x10 76#define SPCR_SPEIE 0x10 /* Error Interrupt Enable */
75#define SPCR_MSTR 0x08 77#define SPCR_MSTR 0x08 /* Master/Slave Mode Select */
76#define SPCR_MODFEN 0x04 78#define SPCR_MODFEN 0x04 /* Mode Fault Error Detection Enable */
77#define SPCR_TXMD 0x02 79/* RSPI on SH only */
78#define SPCR_SPMS 0x01 80#define SPCR_TXMD 0x02 /* TX Only Mode (vs. Full Duplex) */
79 81#define SPCR_SPMS 0x01 /* 3-wire Mode (vs. 4-wire) */
80/* SSLP */ 82/* QSPI on R-Car M2 only */
81#define SSLP_SSL1P 0x02 83#define SPCR_WSWAP 0x02 /* Word Swap of read-data for DMAC */
82#define SSLP_SSL0P 0x01 84#define SPCR_BSWAP 0x01 /* Byte Swap of read-data for DMAC */
83 85
84/* SPPCR */ 86/* SSLP - Slave Select Polarity Register */
85#define SPPCR_MOIFE 0x20 87#define SSLP_SSL1P 0x02 /* SSL1 Signal Polarity Setting */
86#define SPPCR_MOIFV 0x10 88#define SSLP_SSL0P 0x01 /* SSL0 Signal Polarity Setting */
89
90/* SPPCR - Pin Control Register */
91#define SPPCR_MOIFE 0x20 /* MOSI Idle Value Fixing Enable */
92#define SPPCR_MOIFV 0x10 /* MOSI Idle Fixed Value */
87#define SPPCR_SPOM 0x04 93#define SPPCR_SPOM 0x04
88#define SPPCR_SPLP2 0x02 94#define SPPCR_SPLP2 0x02 /* Loopback Mode 2 (non-inverting) */
89#define SPPCR_SPLP 0x01 95#define SPPCR_SPLP 0x01 /* Loopback Mode (inverting) */
90 96
91/* SPSR */ 97#define SPPCR_IO3FV 0x04 /* Single-/Dual-SPI Mode IO3 Output Fixed Value */
92#define SPSR_SPRF 0x80 98#define SPPCR_IO2FV 0x04 /* Single-/Dual-SPI Mode IO2 Output Fixed Value */
93#define SPSR_SPTEF 0x20 99
94#define SPSR_PERF 0x08 100/* SPSR - Status Register */
95#define SPSR_MODF 0x04 101#define SPSR_SPRF 0x80 /* Receive Buffer Full Flag */
96#define SPSR_IDLNF 0x02 102#define SPSR_TEND 0x40 /* Transmit End */
97#define SPSR_OVRF 0x01 103#define SPSR_SPTEF 0x20 /* Transmit Buffer Empty Flag */
98 104#define SPSR_PERF 0x08 /* Parity Error Flag */
99/* SPSCR */ 105#define SPSR_MODF 0x04 /* Mode Fault Error Flag */
100#define SPSCR_SPSLN_MASK 0x07 106#define SPSR_IDLNF 0x02 /* RSPI Idle Flag */
101 107#define SPSR_OVRF 0x01 /* Overrun Error Flag */
102/* SPSSR */ 108
103#define SPSSR_SPECM_MASK 0x70 109/* SPSCR - Sequence Control Register */
104#define SPSSR_SPCP_MASK 0x07 110#define SPSCR_SPSLN_MASK 0x07 /* Sequence Length Specification */
105 111
106/* SPDCR */ 112/* SPSSR - Sequence Status Register */
107#define SPDCR_SPLW 0x20 113#define SPSSR_SPECM_MASK 0x70 /* Command Error Mask */
108#define SPDCR_SPRDTD 0x10 114#define SPSSR_SPCP_MASK 0x07 /* Command Pointer Mask */
115
116/* SPDCR - Data Control Register */
117#define SPDCR_TXDMY 0x80 /* Dummy Data Transmission Enable */
118#define SPDCR_SPLW1 0x40 /* Access Width Specification (RZ) */
119#define SPDCR_SPLW0 0x20 /* Access Width Specification (RZ) */
120#define SPDCR_SPLLWORD (SPDCR_SPLW1 | SPDCR_SPLW0)
121#define SPDCR_SPLWORD SPDCR_SPLW1
122#define SPDCR_SPLBYTE SPDCR_SPLW0
123#define SPDCR_SPLW 0x20 /* Access Width Specification (SH) */
124#define SPDCR_SPRDTD 0x10 /* Receive Transmit Data Select */
109#define SPDCR_SLSEL1 0x08 125#define SPDCR_SLSEL1 0x08
110#define SPDCR_SLSEL0 0x04 126#define SPDCR_SLSEL0 0x04
111#define SPDCR_SLSEL_MASK 0x0c 127#define SPDCR_SLSEL_MASK 0x0c /* SSL1 Output Select */
112#define SPDCR_SPFC1 0x02 128#define SPDCR_SPFC1 0x02
113#define SPDCR_SPFC0 0x01 129#define SPDCR_SPFC0 0x01
130#define SPDCR_SPFC_MASK 0x03 /* Frame Count Setting (1-4) */
114 131
115/* SPCKD */ 132/* SPCKD - Clock Delay Register */
116#define SPCKD_SCKDL_MASK 0x07 133#define SPCKD_SCKDL_MASK 0x07 /* Clock Delay Setting (1-8) */
117 134
118/* SSLND */ 135/* SSLND - Slave Select Negation Delay Register */
119#define SSLND_SLNDL_MASK 0x07 136#define SSLND_SLNDL_MASK 0x07 /* SSL Negation Delay Setting (1-8) */
120 137
121/* SPND */ 138/* SPND - Next-Access Delay Register */
122#define SPND_SPNDL_MASK 0x07 139#define SPND_SPNDL_MASK 0x07 /* Next-Access Delay Setting (1-8) */
123 140
124/* SPCR2 */ 141/* SPCR2 - Control Register 2 */
125#define SPCR2_PTE 0x08 142#define SPCR2_PTE 0x08 /* Parity Self-Test Enable */
126#define SPCR2_SPIE 0x04 143#define SPCR2_SPIE 0x04 /* Idle Interrupt Enable */
127#define SPCR2_SPOE 0x02 144#define SPCR2_SPOE 0x02 /* Odd Parity Enable (vs. Even) */
128#define SPCR2_SPPE 0x01 145#define SPCR2_SPPE 0x01 /* Parity Enable */
129 146
130/* SPCMDn */ 147/* SPCMDn - Command Registers */
131#define SPCMD_SCKDEN 0x8000 148#define SPCMD_SCKDEN 0x8000 /* Clock Delay Setting Enable */
132#define SPCMD_SLNDEN 0x4000 149#define SPCMD_SLNDEN 0x4000 /* SSL Negation Delay Setting Enable */
133#define SPCMD_SPNDEN 0x2000 150#define SPCMD_SPNDEN 0x2000 /* Next-Access Delay Enable */
134#define SPCMD_LSBF 0x1000 151#define SPCMD_LSBF 0x1000 /* LSB First */
135#define SPCMD_SPB_MASK 0x0f00 152#define SPCMD_SPB_MASK 0x0f00 /* Data Length Setting */
136#define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK) 153#define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK)
137#define SPCMD_SPB_8BIT 0x0000 /* qspi only */ 154#define SPCMD_SPB_8BIT 0x0000 /* qspi only */
138#define SPCMD_SPB_16BIT 0x0100 155#define SPCMD_SPB_16BIT 0x0100
139#define SPCMD_SPB_20BIT 0x0000 156#define SPCMD_SPB_20BIT 0x0000
140#define SPCMD_SPB_24BIT 0x0100 157#define SPCMD_SPB_24BIT 0x0100
141#define SPCMD_SPB_32BIT 0x0200 158#define SPCMD_SPB_32BIT 0x0200
142#define SPCMD_SSLKP 0x0080 159#define SPCMD_SSLKP 0x0080 /* SSL Signal Level Keeping */
143#define SPCMD_SSLA_MASK 0x0030 160#define SPCMD_SPIMOD_MASK 0x0060 /* SPI Operating Mode (QSPI only) */
144#define SPCMD_BRDV_MASK 0x000c 161#define SPCMD_SPIMOD1 0x0040
145#define SPCMD_CPOL 0x0002 162#define SPCMD_SPIMOD0 0x0020
146#define SPCMD_CPHA 0x0001 163#define SPCMD_SPIMOD_SINGLE 0
147 164#define SPCMD_SPIMOD_DUAL SPCMD_SPIMOD0
148/* SPBFCR */ 165#define SPCMD_SPIMOD_QUAD SPCMD_SPIMOD1
149#define SPBFCR_TXRST 0x80 /* qspi only */ 166#define SPCMD_SPRW 0x0010 /* SPI Read/Write Access (Dual/Quad) */
150#define SPBFCR_RXRST 0x40 /* qspi only */ 167#define SPCMD_SSLA_MASK 0x0030 /* SSL Assert Signal Setting (RSPI) */
168#define SPCMD_BRDV_MASK 0x000c /* Bit Rate Division Setting */
169#define SPCMD_CPOL 0x0002 /* Clock Polarity Setting */
170#define SPCMD_CPHA 0x0001 /* Clock Phase Setting */
171
172/* SPBFCR - Buffer Control Register */
173#define SPBFCR_TXRST 0x80 /* Transmit Buffer Data Reset (qspi only) */
174#define SPBFCR_RXRST 0x40 /* Receive Buffer Data Reset (qspi only) */
175#define SPBFCR_TXTRG_MASK 0x30 /* Transmit Buffer Data Triggering Number */
176#define SPBFCR_RXTRG_MASK 0x07 /* Receive Buffer Data Triggering Number */
177
178#define DUMMY_DATA 0x00
151 179
152struct rspi_data { 180struct rspi_data {
153 void __iomem *addr; 181 void __iomem *addr;
@@ -158,7 +186,8 @@ struct rspi_data {
158 wait_queue_head_t wait; 186 wait_queue_head_t wait;
159 spinlock_t lock; 187 spinlock_t lock;
160 struct clk *clk; 188 struct clk *clk;
161 unsigned char spsr; 189 u8 spsr;
190 u16 spcmd;
162 const struct spi_ops *ops; 191 const struct spi_ops *ops;
163 192
164 /* for dmaengine */ 193 /* for dmaengine */
@@ -170,34 +199,35 @@ struct rspi_data {
170 unsigned dma_callbacked:1; 199 unsigned dma_callbacked:1;
171}; 200};
172 201
173static void rspi_write8(struct rspi_data *rspi, u8 data, u16 offset) 202static void rspi_write8(const struct rspi_data *rspi, u8 data, u16 offset)
174{ 203{
175 iowrite8(data, rspi->addr + offset); 204 iowrite8(data, rspi->addr + offset);
176} 205}
177 206
178static void rspi_write16(struct rspi_data *rspi, u16 data, u16 offset) 207static void rspi_write16(const struct rspi_data *rspi, u16 data, u16 offset)
179{ 208{
180 iowrite16(data, rspi->addr + offset); 209 iowrite16(data, rspi->addr + offset);
181} 210}
182 211
183static void rspi_write32(struct rspi_data *rspi, u32 data, u16 offset) 212static void rspi_write32(const struct rspi_data *rspi, u32 data, u16 offset)
184{ 213{
185 iowrite32(data, rspi->addr + offset); 214 iowrite32(data, rspi->addr + offset);
186} 215}
187 216
188static u8 rspi_read8(struct rspi_data *rspi, u16 offset) 217static u8 rspi_read8(const struct rspi_data *rspi, u16 offset)
189{ 218{
190 return ioread8(rspi->addr + offset); 219 return ioread8(rspi->addr + offset);
191} 220}
192 221
193static u16 rspi_read16(struct rspi_data *rspi, u16 offset) 222static u16 rspi_read16(const struct rspi_data *rspi, u16 offset)
194{ 223{
195 return ioread16(rspi->addr + offset); 224 return ioread16(rspi->addr + offset);
196} 225}
197 226
198/* optional functions */ 227/* optional functions */
199struct spi_ops { 228struct spi_ops {
200 int (*set_config_register)(struct rspi_data *rspi, int access_size); 229 int (*set_config_register)(const struct rspi_data *rspi,
230 int access_size);
201 int (*send_pio)(struct rspi_data *rspi, struct spi_message *mesg, 231 int (*send_pio)(struct rspi_data *rspi, struct spi_message *mesg,
202 struct spi_transfer *t); 232 struct spi_transfer *t);
203 int (*receive_pio)(struct rspi_data *rspi, struct spi_message *mesg, 233 int (*receive_pio)(struct rspi_data *rspi, struct spi_message *mesg,
@@ -208,7 +238,8 @@ struct spi_ops {
208/* 238/*
209 * functions for RSPI 239 * functions for RSPI
210 */ 240 */
211static int rspi_set_config_register(struct rspi_data *rspi, int access_size) 241static int rspi_set_config_register(const struct rspi_data *rspi,
242 int access_size)
212{ 243{
213 int spbr; 244 int spbr;
214 245
@@ -231,7 +262,7 @@ static int rspi_set_config_register(struct rspi_data *rspi, int access_size)
231 rspi_write8(rspi, 0x00, RSPI_SPCR2); 262 rspi_write8(rspi, 0x00, RSPI_SPCR2);
232 263
233 /* Sets SPCMD */ 264 /* Sets SPCMD */
234 rspi_write16(rspi, SPCMD_SPB_8_TO_16(access_size) | SPCMD_SSLKP, 265 rspi_write16(rspi, SPCMD_SPB_8_TO_16(access_size) | rspi->spcmd,
235 RSPI_SPCMD0); 266 RSPI_SPCMD0);
236 267
237 /* Sets RSPI mode */ 268 /* Sets RSPI mode */
@@ -243,7 +274,8 @@ static int rspi_set_config_register(struct rspi_data *rspi, int access_size)
243/* 274/*
244 * functions for QSPI 275 * functions for QSPI
245 */ 276 */
246static int qspi_set_config_register(struct rspi_data *rspi, int access_size) 277static int qspi_set_config_register(const struct rspi_data *rspi,
278 int access_size)
247{ 279{
248 u16 spcmd; 280 u16 spcmd;
249 int spbr; 281 int spbr;
@@ -268,10 +300,10 @@ static int qspi_set_config_register(struct rspi_data *rspi, int access_size)
268 spcmd = SPCMD_SPB_8BIT; 300 spcmd = SPCMD_SPB_8BIT;
269 else if (access_size == 16) 301 else if (access_size == 16)
270 spcmd = SPCMD_SPB_16BIT; 302 spcmd = SPCMD_SPB_16BIT;
271 else if (access_size == 32) 303 else
272 spcmd = SPCMD_SPB_32BIT; 304 spcmd = SPCMD_SPB_32BIT;
273 305
274 spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | SPCMD_SSLKP | SPCMD_SPNDEN; 306 spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | rspi->spcmd | SPCMD_SPNDEN;
275 307
276 /* Resets transfer data length */ 308 /* Resets transfer data length */
277 rspi_write32(rspi, 0, QSPI_SPBMUL0); 309 rspi_write32(rspi, 0, QSPI_SPBMUL0);
@@ -292,12 +324,12 @@ static int qspi_set_config_register(struct rspi_data *rspi, int access_size)
292 324
293#define set_config_register(spi, n) spi->ops->set_config_register(spi, n) 325#define set_config_register(spi, n) spi->ops->set_config_register(spi, n)
294 326
295static void rspi_enable_irq(struct rspi_data *rspi, u8 enable) 327static void rspi_enable_irq(const struct rspi_data *rspi, u8 enable)
296{ 328{
297 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR); 329 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR);
298} 330}
299 331
300static void rspi_disable_irq(struct rspi_data *rspi, u8 disable) 332static void rspi_disable_irq(const struct rspi_data *rspi, u8 disable)
301{ 333{
302 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR); 334 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR);
303} 335}
@@ -316,12 +348,12 @@ static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask,
316 return 0; 348 return 0;
317} 349}
318 350
319static void rspi_assert_ssl(struct rspi_data *rspi) 351static void rspi_assert_ssl(const struct rspi_data *rspi)
320{ 352{
321 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR); 353 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR);
322} 354}
323 355
324static void rspi_negate_ssl(struct rspi_data *rspi) 356static void rspi_negate_ssl(const struct rspi_data *rspi)
325{ 357{
326 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR); 358 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR);
327} 359}
@@ -330,9 +362,7 @@ static int rspi_send_pio(struct rspi_data *rspi, struct spi_message *mesg,
330 struct spi_transfer *t) 362 struct spi_transfer *t)
331{ 363{
332 int remain = t->len; 364 int remain = t->len;
333 u8 *data; 365 const u8 *data = t->tx_buf;
334
335 data = (u8 *)t->tx_buf;
336 while (remain > 0) { 366 while (remain > 0) {
337 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_TXMD, 367 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_TXMD,
338 RSPI_SPCR); 368 RSPI_SPCR);
@@ -348,7 +378,7 @@ static int rspi_send_pio(struct rspi_data *rspi, struct spi_message *mesg,
348 remain--; 378 remain--;
349 } 379 }
350 380
351 /* Waiting for the last transmition */ 381 /* Waiting for the last transmission */
352 rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE); 382 rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
353 383
354 return 0; 384 return 0;
@@ -358,12 +388,11 @@ static int qspi_send_pio(struct rspi_data *rspi, struct spi_message *mesg,
358 struct spi_transfer *t) 388 struct spi_transfer *t)
359{ 389{
360 int remain = t->len; 390 int remain = t->len;
361 u8 *data; 391 const u8 *data = t->tx_buf;
362 392
363 rspi_write8(rspi, SPBFCR_TXRST, QSPI_SPBFCR); 393 rspi_write8(rspi, SPBFCR_TXRST, QSPI_SPBFCR);
364 rspi_write8(rspi, 0x00, QSPI_SPBFCR); 394 rspi_write8(rspi, 0x00, QSPI_SPBFCR);
365 395
366 data = (u8 *)t->tx_buf;
367 while (remain > 0) { 396 while (remain > 0) {
368 397
369 if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) { 398 if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) {
@@ -383,7 +412,7 @@ static int qspi_send_pio(struct rspi_data *rspi, struct spi_message *mesg,
383 remain--; 412 remain--;
384 } 413 }
385 414
386 /* Waiting for the last transmition */ 415 /* Waiting for the last transmission */
387 rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE); 416 rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
388 417
389 return 0; 418 return 0;
@@ -399,8 +428,8 @@ static void rspi_dma_complete(void *arg)
399 wake_up_interruptible(&rspi->wait); 428 wake_up_interruptible(&rspi->wait);
400} 429}
401 430
402static int rspi_dma_map_sg(struct scatterlist *sg, void *buf, unsigned len, 431static int rspi_dma_map_sg(struct scatterlist *sg, const void *buf,
403 struct dma_chan *chan, 432 unsigned len, struct dma_chan *chan,
404 enum dma_transfer_direction dir) 433 enum dma_transfer_direction dir)
405{ 434{
406 sg_init_table(sg, 1); 435 sg_init_table(sg, 1);
@@ -440,12 +469,13 @@ static void rspi_memory_from_8bit(void *buf, const void *data, unsigned len)
440static int rspi_send_dma(struct rspi_data *rspi, struct spi_transfer *t) 469static int rspi_send_dma(struct rspi_data *rspi, struct spi_transfer *t)
441{ 470{
442 struct scatterlist sg; 471 struct scatterlist sg;
443 void *buf = NULL; 472 const void *buf = NULL;
444 struct dma_async_tx_descriptor *desc; 473 struct dma_async_tx_descriptor *desc;
445 unsigned len; 474 unsigned len;
446 int ret = 0; 475 int ret = 0;
447 476
448 if (rspi->dma_width_16bit) { 477 if (rspi->dma_width_16bit) {
478 void *tmp;
449 /* 479 /*
450 * If DMAC bus width is 16-bit, the driver allocates a dummy 480 * If DMAC bus width is 16-bit, the driver allocates a dummy
451 * buffer. And, the driver converts original data into the 481 * buffer. And, the driver converts original data into the
@@ -454,13 +484,14 @@ static int rspi_send_dma(struct rspi_data *rspi, struct spi_transfer *t)
454 * DMAC data: 1st byte, dummy, 2nd byte, dummy ... 484 * DMAC data: 1st byte, dummy, 2nd byte, dummy ...
455 */ 485 */
456 len = t->len * 2; 486 len = t->len * 2;
457 buf = kmalloc(len, GFP_KERNEL); 487 tmp = kmalloc(len, GFP_KERNEL);
458 if (!buf) 488 if (!tmp)
459 return -ENOMEM; 489 return -ENOMEM;
460 rspi_memory_to_8bit(buf, t->tx_buf, t->len); 490 rspi_memory_to_8bit(tmp, t->tx_buf, t->len);
491 buf = tmp;
461 } else { 492 } else {
462 len = t->len; 493 len = t->len;
463 buf = (void *)t->tx_buf; 494 buf = t->tx_buf;
464 } 495 }
465 496
466 if (!rspi_dma_map_sg(&sg, buf, len, rspi->chan_tx, DMA_TO_DEVICE)) { 497 if (!rspi_dma_map_sg(&sg, buf, len, rspi->chan_tx, DMA_TO_DEVICE)) {
@@ -508,16 +539,16 @@ end_nomap:
508 return ret; 539 return ret;
509} 540}
510 541
511static void rspi_receive_init(struct rspi_data *rspi) 542static void rspi_receive_init(const struct rspi_data *rspi)
512{ 543{
513 unsigned char spsr; 544 u8 spsr;
514 545
515 spsr = rspi_read8(rspi, RSPI_SPSR); 546 spsr = rspi_read8(rspi, RSPI_SPSR);
516 if (spsr & SPSR_SPRF) 547 if (spsr & SPSR_SPRF)
517 rspi_read16(rspi, RSPI_SPDR); /* dummy read */ 548 rspi_read16(rspi, RSPI_SPDR); /* dummy read */
518 if (spsr & SPSR_OVRF) 549 if (spsr & SPSR_OVRF)
519 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF, 550 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF,
520 RSPI_SPCR); 551 RSPI_SPSR);
521} 552}
522 553
523static int rspi_receive_pio(struct rspi_data *rspi, struct spi_message *mesg, 554static int rspi_receive_pio(struct rspi_data *rspi, struct spi_message *mesg,
@@ -528,7 +559,7 @@ static int rspi_receive_pio(struct rspi_data *rspi, struct spi_message *mesg,
528 559
529 rspi_receive_init(rspi); 560 rspi_receive_init(rspi);
530 561
531 data = (u8 *)t->rx_buf; 562 data = t->rx_buf;
532 while (remain > 0) { 563 while (remain > 0) {
533 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_TXMD, 564 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_TXMD,
534 RSPI_SPCR); 565 RSPI_SPCR);
@@ -539,7 +570,7 @@ static int rspi_receive_pio(struct rspi_data *rspi, struct spi_message *mesg,
539 return -ETIMEDOUT; 570 return -ETIMEDOUT;
540 } 571 }
541 /* dummy write for generate clock */ 572 /* dummy write for generate clock */
542 rspi_write16(rspi, 0x00, RSPI_SPDR); 573 rspi_write16(rspi, DUMMY_DATA, RSPI_SPDR);
543 574
544 if (rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE) < 0) { 575 if (rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE) < 0) {
545 dev_err(&rspi->master->dev, 576 dev_err(&rspi->master->dev,
@@ -556,9 +587,9 @@ static int rspi_receive_pio(struct rspi_data *rspi, struct spi_message *mesg,
556 return 0; 587 return 0;
557} 588}
558 589
559static void qspi_receive_init(struct rspi_data *rspi) 590static void qspi_receive_init(const struct rspi_data *rspi)
560{ 591{
561 unsigned char spsr; 592 u8 spsr;
562 593
563 spsr = rspi_read8(rspi, RSPI_SPSR); 594 spsr = rspi_read8(rspi, RSPI_SPSR);
564 if (spsr & SPSR_SPRF) 595 if (spsr & SPSR_SPRF)
@@ -575,7 +606,7 @@ static int qspi_receive_pio(struct rspi_data *rspi, struct spi_message *mesg,
575 606
576 qspi_receive_init(rspi); 607 qspi_receive_init(rspi);
577 608
578 data = (u8 *)t->rx_buf; 609 data = t->rx_buf;
579 while (remain > 0) { 610 while (remain > 0) {
580 611
581 if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) { 612 if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) {
@@ -584,7 +615,7 @@ static int qspi_receive_pio(struct rspi_data *rspi, struct spi_message *mesg,
584 return -ETIMEDOUT; 615 return -ETIMEDOUT;
585 } 616 }
586 /* dummy write for generate clock */ 617 /* dummy write for generate clock */
587 rspi_write8(rspi, 0x00, RSPI_SPDR); 618 rspi_write8(rspi, DUMMY_DATA, RSPI_SPDR);
588 619
589 if (rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE) < 0) { 620 if (rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE) < 0) {
590 dev_err(&rspi->master->dev, 621 dev_err(&rspi->master->dev,
@@ -704,7 +735,7 @@ end_nomap:
704 return ret; 735 return ret;
705} 736}
706 737
707static int rspi_is_dma(struct rspi_data *rspi, struct spi_transfer *t) 738static int rspi_is_dma(const struct rspi_data *rspi, struct spi_transfer *t)
708{ 739{
709 if (t->tx_buf && rspi->chan_tx) 740 if (t->tx_buf && rspi->chan_tx)
710 return 1; 741 return 1;
@@ -771,10 +802,14 @@ static int rspi_setup(struct spi_device *spi)
771{ 802{
772 struct rspi_data *rspi = spi_master_get_devdata(spi->master); 803 struct rspi_data *rspi = spi_master_get_devdata(spi->master);
773 804
774 if (!spi->bits_per_word)
775 spi->bits_per_word = 8;
776 rspi->max_speed_hz = spi->max_speed_hz; 805 rspi->max_speed_hz = spi->max_speed_hz;
777 806
807 rspi->spcmd = SPCMD_SSLKP;
808 if (spi->mode & SPI_CPOL)
809 rspi->spcmd |= SPCMD_CPOL;
810 if (spi->mode & SPI_CPHA)
811 rspi->spcmd |= SPCMD_CPHA;
812
778 set_config_register(rspi, 8); 813 set_config_register(rspi, 8);
779 814
780 return 0; 815 return 0;
@@ -802,10 +837,10 @@ static void rspi_cleanup(struct spi_device *spi)
802 837
803static irqreturn_t rspi_irq(int irq, void *_sr) 838static irqreturn_t rspi_irq(int irq, void *_sr)
804{ 839{
805 struct rspi_data *rspi = (struct rspi_data *)_sr; 840 struct rspi_data *rspi = _sr;
806 unsigned long spsr; 841 u8 spsr;
807 irqreturn_t ret = IRQ_NONE; 842 irqreturn_t ret = IRQ_NONE;
808 unsigned char disable_irq = 0; 843 u8 disable_irq = 0;
809 844
810 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); 845 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
811 if (spsr & SPSR_SPRF) 846 if (spsr & SPSR_SPRF)
@@ -825,7 +860,7 @@ static irqreturn_t rspi_irq(int irq, void *_sr)
825static int rspi_request_dma(struct rspi_data *rspi, 860static int rspi_request_dma(struct rspi_data *rspi,
826 struct platform_device *pdev) 861 struct platform_device *pdev)
827{ 862{
828 struct rspi_plat_data *rspi_pd = dev_get_platdata(&pdev->dev); 863 const struct rspi_plat_data *rspi_pd = dev_get_platdata(&pdev->dev);
829 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 864 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
830 dma_cap_mask_t mask; 865 dma_cap_mask_t mask;
831 struct dma_slave_config cfg; 866 struct dma_slave_config cfg;
@@ -887,11 +922,8 @@ static int rspi_remove(struct platform_device *pdev)
887{ 922{
888 struct rspi_data *rspi = platform_get_drvdata(pdev); 923 struct rspi_data *rspi = platform_get_drvdata(pdev);
889 924
890 spi_unregister_master(rspi->master);
891 rspi_release_dma(rspi); 925 rspi_release_dma(rspi);
892 free_irq(platform_get_irq(pdev, 0), rspi); 926 clk_disable(rspi->clk);
893 clk_put(rspi->clk);
894 iounmap(rspi->addr);
895 927
896 return 0; 928 return 0;
897} 929}
@@ -903,7 +935,7 @@ static int rspi_probe(struct platform_device *pdev)
903 struct rspi_data *rspi; 935 struct rspi_data *rspi;
904 int ret, irq; 936 int ret, irq;
905 char clk_name[16]; 937 char clk_name[16];
906 struct rspi_plat_data *rspi_pd = pdev->dev.platform_data; 938 const struct rspi_plat_data *rspi_pd = dev_get_platdata(&pdev->dev);
907 const struct spi_ops *ops; 939 const struct spi_ops *ops;
908 const struct platform_device_id *id_entry = pdev->id_entry; 940 const struct platform_device_id *id_entry = pdev->id_entry;
909 941
@@ -913,12 +945,6 @@ static int rspi_probe(struct platform_device *pdev)
913 dev_err(&pdev->dev, "there is no set_config_register\n"); 945 dev_err(&pdev->dev, "there is no set_config_register\n");
914 return -ENODEV; 946 return -ENODEV;
915 } 947 }
916 /* get base addr */
917 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
918 if (unlikely(res == NULL)) {
919 dev_err(&pdev->dev, "invalid resource\n");
920 return -EINVAL;
921 }
922 948
923 irq = platform_get_irq(pdev, 0); 949 irq = platform_get_irq(pdev, 0);
924 if (irq < 0) { 950 if (irq < 0) {
@@ -936,19 +962,20 @@ static int rspi_probe(struct platform_device *pdev)
936 platform_set_drvdata(pdev, rspi); 962 platform_set_drvdata(pdev, rspi);
937 rspi->ops = ops; 963 rspi->ops = ops;
938 rspi->master = master; 964 rspi->master = master;
939 rspi->addr = ioremap(res->start, resource_size(res)); 965
940 if (rspi->addr == NULL) { 966 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
941 dev_err(&pdev->dev, "ioremap error.\n"); 967 rspi->addr = devm_ioremap_resource(&pdev->dev, res);
942 ret = -ENOMEM; 968 if (IS_ERR(rspi->addr)) {
969 ret = PTR_ERR(rspi->addr);
943 goto error1; 970 goto error1;
944 } 971 }
945 972
946 snprintf(clk_name, sizeof(clk_name), "%s%d", id_entry->name, pdev->id); 973 snprintf(clk_name, sizeof(clk_name), "%s%d", id_entry->name, pdev->id);
947 rspi->clk = clk_get(&pdev->dev, clk_name); 974 rspi->clk = devm_clk_get(&pdev->dev, clk_name);
948 if (IS_ERR(rspi->clk)) { 975 if (IS_ERR(rspi->clk)) {
949 dev_err(&pdev->dev, "cannot get clock\n"); 976 dev_err(&pdev->dev, "cannot get clock\n");
950 ret = PTR_ERR(rspi->clk); 977 ret = PTR_ERR(rspi->clk);
951 goto error2; 978 goto error1;
952 } 979 }
953 clk_enable(rspi->clk); 980 clk_enable(rspi->clk);
954 981
@@ -957,45 +984,45 @@ static int rspi_probe(struct platform_device *pdev)
957 INIT_WORK(&rspi->ws, rspi_work); 984 INIT_WORK(&rspi->ws, rspi_work);
958 init_waitqueue_head(&rspi->wait); 985 init_waitqueue_head(&rspi->wait);
959 986
960 master->num_chipselect = rspi_pd->num_chipselect; 987 if (rspi_pd && rspi_pd->num_chipselect)
961 if (!master->num_chipselect) 988 master->num_chipselect = rspi_pd->num_chipselect;
989 else
962 master->num_chipselect = 2; /* default */ 990 master->num_chipselect = 2; /* default */
963 991
964 master->bus_num = pdev->id; 992 master->bus_num = pdev->id;
965 master->setup = rspi_setup; 993 master->setup = rspi_setup;
966 master->transfer = rspi_transfer; 994 master->transfer = rspi_transfer;
967 master->cleanup = rspi_cleanup; 995 master->cleanup = rspi_cleanup;
996 master->mode_bits = SPI_CPHA | SPI_CPOL;
968 997
969 ret = request_irq(irq, rspi_irq, 0, dev_name(&pdev->dev), rspi); 998 ret = devm_request_irq(&pdev->dev, irq, rspi_irq, 0,
999 dev_name(&pdev->dev), rspi);
970 if (ret < 0) { 1000 if (ret < 0) {
971 dev_err(&pdev->dev, "request_irq error\n"); 1001 dev_err(&pdev->dev, "request_irq error\n");
972 goto error3; 1002 goto error2;
973 } 1003 }
974 1004
975 rspi->irq = irq; 1005 rspi->irq = irq;
976 ret = rspi_request_dma(rspi, pdev); 1006 ret = rspi_request_dma(rspi, pdev);
977 if (ret < 0) { 1007 if (ret < 0) {
978 dev_err(&pdev->dev, "rspi_request_dma failed.\n"); 1008 dev_err(&pdev->dev, "rspi_request_dma failed.\n");
979 goto error4; 1009 goto error3;
980 } 1010 }
981 1011
982 ret = spi_register_master(master); 1012 ret = devm_spi_register_master(&pdev->dev, master);
983 if (ret < 0) { 1013 if (ret < 0) {
984 dev_err(&pdev->dev, "spi_register_master error.\n"); 1014 dev_err(&pdev->dev, "spi_register_master error.\n");
985 goto error4; 1015 goto error3;
986 } 1016 }
987 1017
988 dev_info(&pdev->dev, "probed\n"); 1018 dev_info(&pdev->dev, "probed\n");
989 1019
990 return 0; 1020 return 0;
991 1021
992error4:
993 rspi_release_dma(rspi);
994 free_irq(irq, rspi);
995error3: 1022error3:
996 clk_put(rspi->clk); 1023 rspi_release_dma(rspi);
997error2: 1024error2:
998 iounmap(rspi->addr); 1025 clk_disable(rspi->clk);
999error1: 1026error1:
1000 spi_master_put(master); 1027 spi_master_put(master);
1001 1028
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-10 06:22:02 -0500