aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/spi/spi-pxa2xx-pxadma.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/spi/spi-pxa2xx-pxadma.c')
-rw-r--r--drivers/spi/spi-pxa2xx-pxadma.c34
1 files changed, 16 insertions, 18 deletions
diff --git a/drivers/spi/spi-pxa2xx-pxadma.c b/drivers/spi/spi-pxa2xx-pxadma.c
index e8a26f25d5c0..2e0796a0003f 100644
--- a/drivers/spi/spi-pxa2xx-pxadma.c
+++ b/drivers/spi/spi-pxa2xx-pxadma.c
@@ -12,10 +12,6 @@
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */ 15 */
20 16
21#include <linux/delay.h> 17#include <linux/delay.h>
@@ -25,6 +21,7 @@
25#include <linux/spi/spi.h> 21#include <linux/spi/spi.h>
26#include <linux/spi/pxa2xx_spi.h> 22#include <linux/spi/pxa2xx_spi.h>
27 23
24#include <mach/dma.h>
28#include "spi-pxa2xx.h" 25#include "spi-pxa2xx.h"
29 26
30#define DMA_INT_MASK (DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERR) 27#define DMA_INT_MASK (DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERR)
@@ -118,11 +115,11 @@ static void pxa2xx_spi_unmap_dma_buffers(struct driver_data *drv_data)
118 drv_data->dma_mapped = 0; 115 drv_data->dma_mapped = 0;
119} 116}
120 117
121static int wait_ssp_rx_stall(void const __iomem *ioaddr) 118static int wait_ssp_rx_stall(struct driver_data *drv_data)
122{ 119{
123 unsigned long limit = loops_per_jiffy << 1; 120 unsigned long limit = loops_per_jiffy << 1;
124 121
125 while ((read_SSSR(ioaddr) & SSSR_BSY) && --limit) 122 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit)
126 cpu_relax(); 123 cpu_relax();
127 124
128 return limit; 125 return limit;
@@ -141,17 +138,18 @@ static int wait_dma_channel_stop(int channel)
141static void pxa2xx_spi_dma_error_stop(struct driver_data *drv_data, 138static void pxa2xx_spi_dma_error_stop(struct driver_data *drv_data,
142 const char *msg) 139 const char *msg)
143{ 140{
144 void __iomem *reg = drv_data->ioaddr;
145
146 /* Stop and reset */ 141 /* Stop and reset */
147 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL; 142 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
148 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL; 143 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
149 write_SSSR_CS(drv_data, drv_data->clear_sr); 144 write_SSSR_CS(drv_data, drv_data->clear_sr);
150 write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg); 145 pxa2xx_spi_write(drv_data, SSCR1,
146 pxa2xx_spi_read(drv_data, SSCR1)
147 & ~drv_data->dma_cr1);
151 if (!pxa25x_ssp_comp(drv_data)) 148 if (!pxa25x_ssp_comp(drv_data))
152 write_SSTO(0, reg); 149 pxa2xx_spi_write(drv_data, SSTO, 0);
153 pxa2xx_spi_flush(drv_data); 150 pxa2xx_spi_flush(drv_data);
154 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); 151 pxa2xx_spi_write(drv_data, SSCR0,
152 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
155 153
156 pxa2xx_spi_unmap_dma_buffers(drv_data); 154 pxa2xx_spi_unmap_dma_buffers(drv_data);
157 155
@@ -163,11 +161,12 @@ static void pxa2xx_spi_dma_error_stop(struct driver_data *drv_data,
163 161
164static void pxa2xx_spi_dma_transfer_complete(struct driver_data *drv_data) 162static void pxa2xx_spi_dma_transfer_complete(struct driver_data *drv_data)
165{ 163{
166 void __iomem *reg = drv_data->ioaddr;
167 struct spi_message *msg = drv_data->cur_msg; 164 struct spi_message *msg = drv_data->cur_msg;
168 165
169 /* Clear and disable interrupts on SSP and DMA channels*/ 166 /* Clear and disable interrupts on SSP and DMA channels*/
170 write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg); 167 pxa2xx_spi_write(drv_data, SSCR1,
168 pxa2xx_spi_read(drv_data, SSCR1)
169 & ~drv_data->dma_cr1);
171 write_SSSR_CS(drv_data, drv_data->clear_sr); 170 write_SSSR_CS(drv_data, drv_data->clear_sr);
172 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL; 171 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
173 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL; 172 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
@@ -228,7 +227,7 @@ void pxa2xx_spi_dma_handler(int channel, void *data)
228 && (drv_data->ssp_type == PXA25x_SSP)) { 227 && (drv_data->ssp_type == PXA25x_SSP)) {
229 228
230 /* Wait for rx to stall */ 229 /* Wait for rx to stall */
231 if (wait_ssp_rx_stall(drv_data->ioaddr) == 0) 230 if (wait_ssp_rx_stall(drv_data) == 0)
232 dev_err(&drv_data->pdev->dev, 231 dev_err(&drv_data->pdev->dev,
233 "dma_handler: ssp rx stall failed\n"); 232 "dma_handler: ssp rx stall failed\n");
234 233
@@ -240,9 +239,8 @@ void pxa2xx_spi_dma_handler(int channel, void *data)
240irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data) 239irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data)
241{ 240{
242 u32 irq_status; 241 u32 irq_status;
243 void __iomem *reg = drv_data->ioaddr;
244 242
245 irq_status = read_SSSR(reg) & drv_data->mask_sr; 243 irq_status = pxa2xx_spi_read(drv_data, SSSR) & drv_data->mask_sr;
246 if (irq_status & SSSR_ROR) { 244 if (irq_status & SSSR_ROR) {
247 pxa2xx_spi_dma_error_stop(drv_data, 245 pxa2xx_spi_dma_error_stop(drv_data,
248 "dma_transfer: fifo overrun"); 246 "dma_transfer: fifo overrun");
@@ -252,7 +250,7 @@ irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data)
252 /* Check for false positive timeout */ 250 /* Check for false positive timeout */
253 if ((irq_status & SSSR_TINT) 251 if ((irq_status & SSSR_TINT)
254 && (DCSR(drv_data->tx_channel) & DCSR_RUN)) { 252 && (DCSR(drv_data->tx_channel) & DCSR_RUN)) {
255 write_SSSR(SSSR_TINT, reg); 253 pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT);
256 return IRQ_HANDLED; 254 return IRQ_HANDLED;
257 } 255 }
258 256
@@ -261,7 +259,7 @@ irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data)
261 /* Clear and disable timeout interrupt, do the rest in 259 /* Clear and disable timeout interrupt, do the rest in
262 * dma_transfer_complete */ 260 * dma_transfer_complete */
263 if (!pxa25x_ssp_comp(drv_data)) 261 if (!pxa25x_ssp_comp(drv_data))
264 write_SSTO(0, reg); 262 pxa2xx_spi_write(drv_data, SSTO, 0);
265 263
266 /* finish this transfer, start the next */ 264 /* finish this transfer, start the next */
267 pxa2xx_spi_dma_transfer_complete(drv_data); 265 pxa2xx_spi_dma_transfer_complete(drv_data);