diff options
Diffstat (limited to 'drivers/spi/spi-mpc512x-psc.c')
-rw-r--r-- | drivers/spi/spi-mpc512x-psc.c | 341 |
1 files changed, 186 insertions, 155 deletions
diff --git a/drivers/spi/spi-mpc512x-psc.c b/drivers/spi/spi-mpc512x-psc.c index dfddf336912d..29fce6af5145 100644 --- a/drivers/spi/spi-mpc512x-psc.c +++ b/drivers/spi/spi-mpc512x-psc.c | |||
@@ -21,7 +21,6 @@ | |||
21 | #include <linux/interrupt.h> | 21 | #include <linux/interrupt.h> |
22 | #include <linux/of_address.h> | 22 | #include <linux/of_address.h> |
23 | #include <linux/of_platform.h> | 23 | #include <linux/of_platform.h> |
24 | #include <linux/workqueue.h> | ||
25 | #include <linux/completion.h> | 24 | #include <linux/completion.h> |
26 | #include <linux/io.h> | 25 | #include <linux/io.h> |
27 | #include <linux/delay.h> | 26 | #include <linux/delay.h> |
@@ -33,24 +32,15 @@ | |||
33 | 32 | ||
34 | struct mpc512x_psc_spi { | 33 | struct mpc512x_psc_spi { |
35 | void (*cs_control)(struct spi_device *spi, bool on); | 34 | void (*cs_control)(struct spi_device *spi, bool on); |
36 | u32 sysclk; | ||
37 | 35 | ||
38 | /* driver internal data */ | 36 | /* driver internal data */ |
39 | struct mpc52xx_psc __iomem *psc; | 37 | struct mpc52xx_psc __iomem *psc; |
40 | struct mpc512x_psc_fifo __iomem *fifo; | 38 | struct mpc512x_psc_fifo __iomem *fifo; |
41 | unsigned int irq; | 39 | unsigned int irq; |
42 | u8 bits_per_word; | 40 | u8 bits_per_word; |
43 | u8 busy; | ||
44 | u32 mclk; | 41 | u32 mclk; |
45 | u8 eofbyte; | ||
46 | 42 | ||
47 | struct workqueue_struct *workqueue; | 43 | struct completion txisrdone; |
48 | struct work_struct work; | ||
49 | |||
50 | struct list_head queue; | ||
51 | spinlock_t lock; /* Message queue lock */ | ||
52 | |||
53 | struct completion done; | ||
54 | }; | 44 | }; |
55 | 45 | ||
56 | /* controller state */ | 46 | /* controller state */ |
@@ -136,145 +126,223 @@ static int mpc512x_psc_spi_transfer_rxtx(struct spi_device *spi, | |||
136 | struct spi_transfer *t) | 126 | struct spi_transfer *t) |
137 | { | 127 | { |
138 | struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master); | 128 | struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master); |
139 | struct mpc52xx_psc __iomem *psc = mps->psc; | ||
140 | struct mpc512x_psc_fifo __iomem *fifo = mps->fifo; | 129 | struct mpc512x_psc_fifo __iomem *fifo = mps->fifo; |
141 | size_t len = t->len; | 130 | size_t tx_len = t->len; |
131 | size_t rx_len = t->len; | ||
142 | u8 *tx_buf = (u8 *)t->tx_buf; | 132 | u8 *tx_buf = (u8 *)t->tx_buf; |
143 | u8 *rx_buf = (u8 *)t->rx_buf; | 133 | u8 *rx_buf = (u8 *)t->rx_buf; |
144 | 134 | ||
145 | if (!tx_buf && !rx_buf && t->len) | 135 | if (!tx_buf && !rx_buf && t->len) |
146 | return -EINVAL; | 136 | return -EINVAL; |
147 | 137 | ||
148 | /* Zero MR2 */ | 138 | while (rx_len || tx_len) { |
149 | in_8(&psc->mode); | 139 | size_t txcount; |
150 | out_8(&psc->mode, 0x0); | ||
151 | |||
152 | /* enable transmiter/receiver */ | ||
153 | out_8(&psc->command, MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE); | ||
154 | |||
155 | while (len) { | ||
156 | int count; | ||
157 | int i; | ||
158 | u8 data; | 140 | u8 data; |
159 | size_t fifosz; | 141 | size_t fifosz; |
160 | int rxcount; | 142 | size_t rxcount; |
143 | int rxtries; | ||
161 | 144 | ||
162 | /* | 145 | /* |
163 | * The number of bytes that can be sent at a time | 146 | * send the TX bytes in as large a chunk as possible |
164 | * depends on the fifo size. | 147 | * but neither exceed the TX nor the RX FIFOs |
165 | */ | 148 | */ |
166 | fifosz = MPC512x_PSC_FIFO_SZ(in_be32(&fifo->txsz)); | 149 | fifosz = MPC512x_PSC_FIFO_SZ(in_be32(&fifo->txsz)); |
167 | count = min(fifosz, len); | 150 | txcount = min(fifosz, tx_len); |
168 | 151 | fifosz = MPC512x_PSC_FIFO_SZ(in_be32(&fifo->rxsz)); | |
169 | for (i = count; i > 0; i--) { | 152 | fifosz -= in_be32(&fifo->rxcnt) + 1; |
170 | data = tx_buf ? *tx_buf++ : 0; | 153 | txcount = min(fifosz, txcount); |
171 | if (len == EOFBYTE && t->cs_change) | 154 | if (txcount) { |
172 | setbits32(&fifo->txcmd, MPC512x_PSC_FIFO_EOF); | 155 | |
173 | out_8(&fifo->txdata_8, data); | 156 | /* fill the TX FIFO */ |
174 | len--; | 157 | while (txcount-- > 0) { |
158 | data = tx_buf ? *tx_buf++ : 0; | ||
159 | if (tx_len == EOFBYTE && t->cs_change) | ||
160 | setbits32(&fifo->txcmd, | ||
161 | MPC512x_PSC_FIFO_EOF); | ||
162 | out_8(&fifo->txdata_8, data); | ||
163 | tx_len--; | ||
164 | } | ||
165 | |||
166 | /* have the ISR trigger when the TX FIFO is empty */ | ||
167 | INIT_COMPLETION(mps->txisrdone); | ||
168 | out_be32(&fifo->txisr, MPC512x_PSC_FIFO_EMPTY); | ||
169 | out_be32(&fifo->tximr, MPC512x_PSC_FIFO_EMPTY); | ||
170 | wait_for_completion(&mps->txisrdone); | ||
175 | } | 171 | } |
176 | 172 | ||
177 | INIT_COMPLETION(mps->done); | 173 | /* |
174 | * consume as much RX data as the FIFO holds, while we | ||
175 | * iterate over the transfer's TX data length | ||
176 | * | ||
177 | * only insist in draining all the remaining RX bytes | ||
178 | * when the TX bytes were exhausted (that's at the very | ||
179 | * end of this transfer, not when still iterating over | ||
180 | * the transfer's chunks) | ||
181 | */ | ||
182 | rxtries = 50; | ||
183 | do { | ||
184 | |||
185 | /* | ||
186 | * grab whatever was in the FIFO when we started | ||
187 | * looking, don't bother fetching what was added to | ||
188 | * the FIFO while we read from it -- we'll return | ||
189 | * here eventually and prefer sending out remaining | ||
190 | * TX data | ||
191 | */ | ||
192 | fifosz = in_be32(&fifo->rxcnt); | ||
193 | rxcount = min(fifosz, rx_len); | ||
194 | while (rxcount-- > 0) { | ||
195 | data = in_8(&fifo->rxdata_8); | ||
196 | if (rx_buf) | ||
197 | *rx_buf++ = data; | ||
198 | rx_len--; | ||
199 | } | ||
178 | 200 | ||
179 | /* interrupt on tx fifo empty */ | 201 | /* |
180 | out_be32(&fifo->txisr, MPC512x_PSC_FIFO_EMPTY); | 202 | * come back later if there still is TX data to send, |
181 | out_be32(&fifo->tximr, MPC512x_PSC_FIFO_EMPTY); | 203 | * bail out of the RX drain loop if all of the TX data |
204 | * was sent and all of the RX data was received (i.e. | ||
205 | * when the transmission has completed) | ||
206 | */ | ||
207 | if (tx_len) | ||
208 | break; | ||
209 | if (!rx_len) | ||
210 | break; | ||
182 | 211 | ||
183 | wait_for_completion(&mps->done); | 212 | /* |
213 | * TX data transmission has completed while RX data | ||
214 | * is still pending -- that's a transient situation | ||
215 | * which depends on wire speed and specific | ||
216 | * hardware implementation details (buffering) yet | ||
217 | * should resolve very quickly | ||
218 | * | ||
219 | * just yield for a moment to not hog the CPU for | ||
220 | * too long when running SPI at low speed | ||
221 | * | ||
222 | * the timeout range is rather arbitrary and tries | ||
223 | * to balance throughput against system load; the | ||
224 | * chosen values result in a minimal timeout of 50 | ||
225 | * times 10us and thus work at speeds as low as | ||
226 | * some 20kbps, while the maximum timeout at the | ||
227 | * transfer's end could be 5ms _if_ nothing else | ||
228 | * ticks in the system _and_ RX data still wasn't | ||
229 | * received, which only occurs in situations that | ||
230 | * are exceptional; removing the unpredictability | ||
231 | * of the timeout either decreases throughput | ||
232 | * (longer timeouts), or puts more load on the | ||
233 | * system (fixed short timeouts) or requires the | ||
234 | * use of a timeout API instead of a counter and an | ||
235 | * unknown inner delay | ||
236 | */ | ||
237 | usleep_range(10, 100); | ||
238 | |||
239 | } while (--rxtries > 0); | ||
240 | if (!tx_len && rx_len && !rxtries) { | ||
241 | /* | ||
242 | * not enough RX bytes even after several retries | ||
243 | * and the resulting rather long timeout? | ||
244 | */ | ||
245 | rxcount = in_be32(&fifo->rxcnt); | ||
246 | dev_warn(&spi->dev, | ||
247 | "short xfer, missing %zd RX bytes, FIFO level %zd\n", | ||
248 | rx_len, rxcount); | ||
249 | } | ||
184 | 250 | ||
185 | mdelay(1); | 251 | /* |
252 | * drain and drop RX data which "should not be there" in | ||
253 | * the first place, for undisturbed transmission this turns | ||
254 | * into a NOP (except for the FIFO level fetch) | ||
255 | */ | ||
256 | if (!tx_len && !rx_len) { | ||
257 | while (in_be32(&fifo->rxcnt)) | ||
258 | in_8(&fifo->rxdata_8); | ||
259 | } | ||
186 | 260 | ||
187 | /* rx fifo should have count bytes in it */ | 261 | } |
188 | rxcount = in_be32(&fifo->rxcnt); | 262 | return 0; |
189 | if (rxcount != count) | 263 | } |
190 | mdelay(1); | ||
191 | 264 | ||
192 | rxcount = in_be32(&fifo->rxcnt); | 265 | static int mpc512x_psc_spi_msg_xfer(struct spi_master *master, |
193 | if (rxcount != count) { | 266 | struct spi_message *m) |
194 | dev_warn(&spi->dev, "expected %d bytes in rx fifo " | 267 | { |
195 | "but got %d\n", count, rxcount); | 268 | struct spi_device *spi; |
269 | unsigned cs_change; | ||
270 | int status; | ||
271 | struct spi_transfer *t; | ||
272 | |||
273 | spi = m->spi; | ||
274 | cs_change = 1; | ||
275 | status = 0; | ||
276 | list_for_each_entry(t, &m->transfers, transfer_list) { | ||
277 | if (t->bits_per_word || t->speed_hz) { | ||
278 | status = mpc512x_psc_spi_transfer_setup(spi, t); | ||
279 | if (status < 0) | ||
280 | break; | ||
196 | } | 281 | } |
197 | 282 | ||
198 | rxcount = min(rxcount, count); | 283 | if (cs_change) |
199 | for (i = rxcount; i > 0; i--) { | 284 | mpc512x_psc_spi_activate_cs(spi); |
200 | data = in_8(&fifo->rxdata_8); | 285 | cs_change = t->cs_change; |
201 | if (rx_buf) | 286 | |
202 | *rx_buf++ = data; | 287 | status = mpc512x_psc_spi_transfer_rxtx(spi, t); |
203 | } | 288 | if (status) |
204 | while (in_be32(&fifo->rxcnt)) { | 289 | break; |
205 | in_8(&fifo->rxdata_8); | 290 | m->actual_length += t->len; |
206 | } | 291 | |
292 | if (t->delay_usecs) | ||
293 | udelay(t->delay_usecs); | ||
294 | |||
295 | if (cs_change) | ||
296 | mpc512x_psc_spi_deactivate_cs(spi); | ||
207 | } | 297 | } |
208 | /* disable transmiter/receiver and fifo interrupt */ | 298 | |
209 | out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE); | 299 | m->status = status; |
210 | out_be32(&fifo->tximr, 0); | 300 | m->complete(m->context); |
211 | return 0; | 301 | |
302 | if (status || !cs_change) | ||
303 | mpc512x_psc_spi_deactivate_cs(spi); | ||
304 | |||
305 | mpc512x_psc_spi_transfer_setup(spi, NULL); | ||
306 | |||
307 | spi_finalize_current_message(master); | ||
308 | return status; | ||
212 | } | 309 | } |
213 | 310 | ||
214 | static void mpc512x_psc_spi_work(struct work_struct *work) | 311 | static int mpc512x_psc_spi_prep_xfer_hw(struct spi_master *master) |
215 | { | 312 | { |
216 | struct mpc512x_psc_spi *mps = container_of(work, | 313 | struct mpc512x_psc_spi *mps = spi_master_get_devdata(master); |
217 | struct mpc512x_psc_spi, | 314 | struct mpc52xx_psc __iomem *psc = mps->psc; |
218 | work); | ||
219 | |||
220 | spin_lock_irq(&mps->lock); | ||
221 | mps->busy = 1; | ||
222 | while (!list_empty(&mps->queue)) { | ||
223 | struct spi_message *m; | ||
224 | struct spi_device *spi; | ||
225 | struct spi_transfer *t = NULL; | ||
226 | unsigned cs_change; | ||
227 | int status; | ||
228 | |||
229 | m = container_of(mps->queue.next, struct spi_message, queue); | ||
230 | list_del_init(&m->queue); | ||
231 | spin_unlock_irq(&mps->lock); | ||
232 | |||
233 | spi = m->spi; | ||
234 | cs_change = 1; | ||
235 | status = 0; | ||
236 | list_for_each_entry(t, &m->transfers, transfer_list) { | ||
237 | if (t->bits_per_word || t->speed_hz) { | ||
238 | status = mpc512x_psc_spi_transfer_setup(spi, t); | ||
239 | if (status < 0) | ||
240 | break; | ||
241 | } | ||
242 | 315 | ||
243 | if (cs_change) | 316 | dev_dbg(&master->dev, "%s()\n", __func__); |
244 | mpc512x_psc_spi_activate_cs(spi); | ||
245 | cs_change = t->cs_change; | ||
246 | 317 | ||
247 | status = mpc512x_psc_spi_transfer_rxtx(spi, t); | 318 | /* Zero MR2 */ |
248 | if (status) | 319 | in_8(&psc->mode); |
249 | break; | 320 | out_8(&psc->mode, 0x0); |
250 | m->actual_length += t->len; | ||
251 | 321 | ||
252 | if (t->delay_usecs) | 322 | /* enable transmitter/receiver */ |
253 | udelay(t->delay_usecs); | 323 | out_8(&psc->command, MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE); |
254 | 324 | ||
255 | if (cs_change) | 325 | return 0; |
256 | mpc512x_psc_spi_deactivate_cs(spi); | 326 | } |
257 | } | ||
258 | 327 | ||
259 | m->status = status; | 328 | static int mpc512x_psc_spi_unprep_xfer_hw(struct spi_master *master) |
260 | m->complete(m->context); | 329 | { |
330 | struct mpc512x_psc_spi *mps = spi_master_get_devdata(master); | ||
331 | struct mpc52xx_psc __iomem *psc = mps->psc; | ||
332 | struct mpc512x_psc_fifo __iomem *fifo = mps->fifo; | ||
261 | 333 | ||
262 | if (status || !cs_change) | 334 | dev_dbg(&master->dev, "%s()\n", __func__); |
263 | mpc512x_psc_spi_deactivate_cs(spi); | ||
264 | 335 | ||
265 | mpc512x_psc_spi_transfer_setup(spi, NULL); | 336 | /* disable transmitter/receiver and fifo interrupt */ |
337 | out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE); | ||
338 | out_be32(&fifo->tximr, 0); | ||
266 | 339 | ||
267 | spin_lock_irq(&mps->lock); | 340 | return 0; |
268 | } | ||
269 | mps->busy = 0; | ||
270 | spin_unlock_irq(&mps->lock); | ||
271 | } | 341 | } |
272 | 342 | ||
273 | static int mpc512x_psc_spi_setup(struct spi_device *spi) | 343 | static int mpc512x_psc_spi_setup(struct spi_device *spi) |
274 | { | 344 | { |
275 | struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master); | ||
276 | struct mpc512x_psc_spi_cs *cs = spi->controller_state; | 345 | struct mpc512x_psc_spi_cs *cs = spi->controller_state; |
277 | unsigned long flags; | ||
278 | int ret; | 346 | int ret; |
279 | 347 | ||
280 | if (spi->bits_per_word % 8) | 348 | if (spi->bits_per_word % 8) |
@@ -303,28 +371,6 @@ static int mpc512x_psc_spi_setup(struct spi_device *spi) | |||
303 | cs->bits_per_word = spi->bits_per_word; | 371 | cs->bits_per_word = spi->bits_per_word; |
304 | cs->speed_hz = spi->max_speed_hz; | 372 | cs->speed_hz = spi->max_speed_hz; |
305 | 373 | ||
306 | spin_lock_irqsave(&mps->lock, flags); | ||
307 | if (!mps->busy) | ||
308 | mpc512x_psc_spi_deactivate_cs(spi); | ||
309 | spin_unlock_irqrestore(&mps->lock, flags); | ||
310 | |||
311 | return 0; | ||
312 | } | ||
313 | |||
314 | static int mpc512x_psc_spi_transfer(struct spi_device *spi, | ||
315 | struct spi_message *m) | ||
316 | { | ||
317 | struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master); | ||
318 | unsigned long flags; | ||
319 | |||
320 | m->actual_length = 0; | ||
321 | m->status = -EINPROGRESS; | ||
322 | |||
323 | spin_lock_irqsave(&mps->lock, flags); | ||
324 | list_add_tail(&m->queue, &mps->queue); | ||
325 | queue_work(mps->workqueue, &mps->work); | ||
326 | spin_unlock_irqrestore(&mps->lock, flags); | ||
327 | |||
328 | return 0; | 374 | return 0; |
329 | } | 375 | } |
330 | 376 | ||
@@ -407,12 +453,12 @@ static irqreturn_t mpc512x_psc_spi_isr(int irq, void *dev_id) | |||
407 | struct mpc512x_psc_spi *mps = (struct mpc512x_psc_spi *)dev_id; | 453 | struct mpc512x_psc_spi *mps = (struct mpc512x_psc_spi *)dev_id; |
408 | struct mpc512x_psc_fifo __iomem *fifo = mps->fifo; | 454 | struct mpc512x_psc_fifo __iomem *fifo = mps->fifo; |
409 | 455 | ||
410 | /* clear interrupt and wake up the work queue */ | 456 | /* clear interrupt and wake up the rx/tx routine */ |
411 | if (in_be32(&fifo->txisr) & | 457 | if (in_be32(&fifo->txisr) & |
412 | in_be32(&fifo->tximr) & MPC512x_PSC_FIFO_EMPTY) { | 458 | in_be32(&fifo->tximr) & MPC512x_PSC_FIFO_EMPTY) { |
413 | out_be32(&fifo->txisr, MPC512x_PSC_FIFO_EMPTY); | 459 | out_be32(&fifo->txisr, MPC512x_PSC_FIFO_EMPTY); |
414 | out_be32(&fifo->tximr, 0); | 460 | out_be32(&fifo->tximr, 0); |
415 | complete(&mps->done); | 461 | complete(&mps->txisrdone); |
416 | return IRQ_HANDLED; | 462 | return IRQ_HANDLED; |
417 | } | 463 | } |
418 | return IRQ_NONE; | 464 | return IRQ_NONE; |
@@ -444,18 +490,18 @@ static int mpc512x_psc_spi_do_probe(struct device *dev, u32 regaddr, | |||
444 | 490 | ||
445 | if (pdata == NULL) { | 491 | if (pdata == NULL) { |
446 | mps->cs_control = mpc512x_spi_cs_control; | 492 | mps->cs_control = mpc512x_spi_cs_control; |
447 | mps->sysclk = 0; | ||
448 | master->bus_num = bus_num; | 493 | master->bus_num = bus_num; |
449 | } else { | 494 | } else { |
450 | mps->cs_control = pdata->cs_control; | 495 | mps->cs_control = pdata->cs_control; |
451 | mps->sysclk = pdata->sysclk; | ||
452 | master->bus_num = pdata->bus_num; | 496 | master->bus_num = pdata->bus_num; |
453 | master->num_chipselect = pdata->max_chipselect; | 497 | master->num_chipselect = pdata->max_chipselect; |
454 | } | 498 | } |
455 | 499 | ||
456 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST; | 500 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST; |
457 | master->setup = mpc512x_psc_spi_setup; | 501 | master->setup = mpc512x_psc_spi_setup; |
458 | master->transfer = mpc512x_psc_spi_transfer; | 502 | master->prepare_transfer_hardware = mpc512x_psc_spi_prep_xfer_hw; |
503 | master->transfer_one_message = mpc512x_psc_spi_msg_xfer; | ||
504 | master->unprepare_transfer_hardware = mpc512x_psc_spi_unprep_xfer_hw; | ||
459 | master->cleanup = mpc512x_psc_spi_cleanup; | 505 | master->cleanup = mpc512x_psc_spi_cleanup; |
460 | master->dev.of_node = dev->of_node; | 506 | master->dev.of_node = dev->of_node; |
461 | 507 | ||
@@ -473,31 +519,18 @@ static int mpc512x_psc_spi_do_probe(struct device *dev, u32 regaddr, | |||
473 | "mpc512x-psc-spi", mps); | 519 | "mpc512x-psc-spi", mps); |
474 | if (ret) | 520 | if (ret) |
475 | goto free_master; | 521 | goto free_master; |
522 | init_completion(&mps->txisrdone); | ||
476 | 523 | ||
477 | ret = mpc512x_psc_spi_port_config(master, mps); | 524 | ret = mpc512x_psc_spi_port_config(master, mps); |
478 | if (ret < 0) | 525 | if (ret < 0) |
479 | goto free_irq; | 526 | goto free_irq; |
480 | 527 | ||
481 | spin_lock_init(&mps->lock); | ||
482 | init_completion(&mps->done); | ||
483 | INIT_WORK(&mps->work, mpc512x_psc_spi_work); | ||
484 | INIT_LIST_HEAD(&mps->queue); | ||
485 | |||
486 | mps->workqueue = | ||
487 | create_singlethread_workqueue(dev_name(master->dev.parent)); | ||
488 | if (mps->workqueue == NULL) { | ||
489 | ret = -EBUSY; | ||
490 | goto free_irq; | ||
491 | } | ||
492 | |||
493 | ret = spi_register_master(master); | 528 | ret = spi_register_master(master); |
494 | if (ret < 0) | 529 | if (ret < 0) |
495 | goto unreg_master; | 530 | goto free_irq; |
496 | 531 | ||
497 | return ret; | 532 | return ret; |
498 | 533 | ||
499 | unreg_master: | ||
500 | destroy_workqueue(mps->workqueue); | ||
501 | free_irq: | 534 | free_irq: |
502 | free_irq(mps->irq, mps); | 535 | free_irq(mps->irq, mps); |
503 | free_master: | 536 | free_master: |
@@ -513,8 +546,6 @@ static int mpc512x_psc_spi_do_remove(struct device *dev) | |||
513 | struct spi_master *master = spi_master_get(dev_get_drvdata(dev)); | 546 | struct spi_master *master = spi_master_get(dev_get_drvdata(dev)); |
514 | struct mpc512x_psc_spi *mps = spi_master_get_devdata(master); | 547 | struct mpc512x_psc_spi *mps = spi_master_get_devdata(master); |
515 | 548 | ||
516 | flush_workqueue(mps->workqueue); | ||
517 | destroy_workqueue(mps->workqueue); | ||
518 | spi_unregister_master(master); | 549 | spi_unregister_master(master); |
519 | free_irq(mps->irq, mps); | 550 | free_irq(mps->irq, mps); |
520 | if (mps->psc) | 551 | if (mps->psc) |