1 files changed, 8 insertions, 7 deletions

diff --git a/drivers/spi/spi-dw-mid.c b/drivers/spi/spi-dw-mid.c
index a67d37c7e3c0..a0197fd4e95c 100644
--- a/drivers/spi/spi-dw-mid.c
+++ b/drivers/spi/spi-dw-mid.c
@@ -247,9 +247,9 @@ static struct dw_spi_dma_ops mid_dma_ops = {
 
 /* Some specific info for SPI0 controller on Intel MID */
 
-/* HW info for MRST CLk Control Unit, one 32b reg */
+/* HW info for MRST Clk Control Unit, 32b reg per controller */
 #define MRST_SPI_CLK_BASE       100000000       /* 100m */
-#define MRST_CLK_SPI0_REG       0xff11d86c
+#define MRST_CLK_SPI_REG        0xff11d86c
 #define CLK_SPI_BDIV_OFFSET     0
 #define CLK_SPI_BDIV_MASK       0x00000007
 #define CLK_SPI_CDIV_OFFSET     9
@@ -261,16 +261,17 @@ int dw_spi_mid_init(struct dw_spi *dws)
         void __iomem *clk_reg;
         u32 clk_cdiv;
 
-        clk_reg = ioremap_nocache(MRST_CLK_SPI0_REG, 16);
+        clk_reg = ioremap_nocache(MRST_CLK_SPI_REG, 16);
         if (!clk_reg)
                 return -ENOMEM;
 
-        /* get SPI controller operating freq info */
-        clk_cdiv  = (readl(clk_reg) & CLK_SPI_CDIV_MASK) >> CLK_SPI_CDIV_OFFSET;
+        /* Get SPI controller operating freq info */
+        clk_cdiv = readl(clk_reg + dws->bus_num * sizeof(u32));
+        clk_cdiv &= CLK_SPI_CDIV_MASK;
+        clk_cdiv >>= CLK_SPI_CDIV_OFFSET;
         dws->max_freq = MRST_SPI_CLK_BASE / (clk_cdiv + 1);
-        iounmap(clk_reg);
 
-        dws->num_cs = 16;
+        iounmap(clk_reg);
 
 #ifdef CONFIG_SPI_DW_MID_DMA
         dws->dma_priv = kzalloc(sizeof(struct mid_dma), GFP_KERNEL);