diff options
Diffstat (limited to 'drivers/spi/spi-atmel.c')
-rw-r--r-- | drivers/spi/spi-atmel.c | 25 |
1 files changed, 12 insertions, 13 deletions
diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c index af3dbab600d5..26c126bfe02a 100644 --- a/drivers/spi/spi-atmel.c +++ b/drivers/spi/spi-atmel.c | |||
@@ -255,11 +255,6 @@ static bool atmel_spi_is_v2(struct atmel_spi *as) | |||
255 | * Master on Chip Select 0.") No workaround exists for that ... so for | 255 | * Master on Chip Select 0.") No workaround exists for that ... so for |
256 | * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH, | 256 | * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH, |
257 | * and (c) will trigger that first erratum in some cases. | 257 | * and (c) will trigger that first erratum in some cases. |
258 | * | ||
259 | * TODO: Test if the atmel_spi_is_v2() branch below works on | ||
260 | * AT91RM9200 if we use some other register than CSR0. However, don't | ||
261 | * do this unconditionally since AP7000 has an errata where the BITS | ||
262 | * field in CSR0 overrides all other CSRs. | ||
263 | */ | 258 | */ |
264 | 259 | ||
265 | static void cs_activate(struct atmel_spi *as, struct spi_device *spi) | 260 | static void cs_activate(struct atmel_spi *as, struct spi_device *spi) |
@@ -269,18 +264,22 @@ static void cs_activate(struct atmel_spi *as, struct spi_device *spi) | |||
269 | u32 mr; | 264 | u32 mr; |
270 | 265 | ||
271 | if (atmel_spi_is_v2(as)) { | 266 | if (atmel_spi_is_v2(as)) { |
272 | /* | 267 | spi_writel(as, CSR0 + 4 * spi->chip_select, asd->csr); |
273 | * Always use CSR0. This ensures that the clock | 268 | /* For the low SPI version, there is a issue that PDC transfer |
274 | * switches to the correct idle polarity before we | 269 | * on CS1,2,3 needs SPI_CSR0.BITS config as SPI_CSR1,2,3.BITS |
275 | * toggle the CS. | ||
276 | */ | 270 | */ |
277 | spi_writel(as, CSR0, asd->csr); | 271 | spi_writel(as, CSR0, asd->csr); |
278 | if (as->caps.has_wdrbt) { | 272 | if (as->caps.has_wdrbt) { |
279 | spi_writel(as, MR, SPI_BF(PCS, 0x0e) | SPI_BIT(WDRBT) | 273 | spi_writel(as, MR, |
280 | | SPI_BIT(MODFDIS) | SPI_BIT(MSTR)); | 274 | SPI_BF(PCS, ~(0x01 << spi->chip_select)) |
275 | | SPI_BIT(WDRBT) | ||
276 | | SPI_BIT(MODFDIS) | ||
277 | | SPI_BIT(MSTR)); | ||
281 | } else { | 278 | } else { |
282 | spi_writel(as, MR, SPI_BF(PCS, 0x0e) | SPI_BIT(MODFDIS) | 279 | spi_writel(as, MR, |
283 | | SPI_BIT(MSTR)); | 280 | SPI_BF(PCS, ~(0x01 << spi->chip_select)) |
281 | | SPI_BIT(MODFDIS) | ||
282 | | SPI_BIT(MSTR)); | ||
284 | } | 283 | } |
285 | mr = spi_readl(as, MR); | 284 | mr = spi_readl(as, MR); |
286 | gpio_set_value(asd->npcs_pin, active); | 285 | gpio_set_value(asd->npcs_pin, active); |