diff options
Diffstat (limited to 'drivers/spi/omap2_mcspi.c')
-rw-r--r-- | drivers/spi/omap2_mcspi.c | 222 |
1 files changed, 68 insertions, 154 deletions
diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c index abb1ffbf3d20..36501adc125d 100644 --- a/drivers/spi/omap2_mcspi.c +++ b/drivers/spi/omap2_mcspi.c | |||
@@ -3,7 +3,7 @@ | |||
3 | * | 3 | * |
4 | * Copyright (C) 2005, 2006 Nokia Corporation | 4 | * Copyright (C) 2005, 2006 Nokia Corporation |
5 | * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and | 5 | * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and |
6 | * Juha Yrj�l� <juha.yrjola@nokia.com> | 6 | * Juha Yrj�l� <juha.yrjola@nokia.com> |
7 | * | 7 | * |
8 | * This program is free software; you can redistribute it and/or modify | 8 | * This program is free software; you can redistribute it and/or modify |
9 | * it under the terms of the GNU General Public License as published by | 9 | * it under the terms of the GNU General Public License as published by |
@@ -33,6 +33,7 @@ | |||
33 | #include <linux/clk.h> | 33 | #include <linux/clk.h> |
34 | #include <linux/io.h> | 34 | #include <linux/io.h> |
35 | #include <linux/slab.h> | 35 | #include <linux/slab.h> |
36 | #include <linux/pm_runtime.h> | ||
36 | 37 | ||
37 | #include <linux/spi/spi.h> | 38 | #include <linux/spi/spi.h> |
38 | 39 | ||
@@ -46,7 +47,6 @@ | |||
46 | #define OMAP2_MCSPI_MAX_CTRL 4 | 47 | #define OMAP2_MCSPI_MAX_CTRL 4 |
47 | 48 | ||
48 | #define OMAP2_MCSPI_REVISION 0x00 | 49 | #define OMAP2_MCSPI_REVISION 0x00 |
49 | #define OMAP2_MCSPI_SYSCONFIG 0x10 | ||
50 | #define OMAP2_MCSPI_SYSSTATUS 0x14 | 50 | #define OMAP2_MCSPI_SYSSTATUS 0x14 |
51 | #define OMAP2_MCSPI_IRQSTATUS 0x18 | 51 | #define OMAP2_MCSPI_IRQSTATUS 0x18 |
52 | #define OMAP2_MCSPI_IRQENABLE 0x1c | 52 | #define OMAP2_MCSPI_IRQENABLE 0x1c |
@@ -63,13 +63,6 @@ | |||
63 | 63 | ||
64 | /* per-register bitmasks: */ | 64 | /* per-register bitmasks: */ |
65 | 65 | ||
66 | #define OMAP2_MCSPI_SYSCONFIG_SMARTIDLE BIT(4) | ||
67 | #define OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2) | ||
68 | #define OMAP2_MCSPI_SYSCONFIG_AUTOIDLE BIT(0) | ||
69 | #define OMAP2_MCSPI_SYSCONFIG_SOFTRESET BIT(1) | ||
70 | |||
71 | #define OMAP2_MCSPI_SYSSTATUS_RESETDONE BIT(0) | ||
72 | |||
73 | #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0) | 66 | #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0) |
74 | #define OMAP2_MCSPI_MODULCTRL_MS BIT(2) | 67 | #define OMAP2_MCSPI_MODULCTRL_MS BIT(2) |
75 | #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3) | 68 | #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3) |
@@ -122,13 +115,12 @@ struct omap2_mcspi { | |||
122 | spinlock_t lock; | 115 | spinlock_t lock; |
123 | struct list_head msg_queue; | 116 | struct list_head msg_queue; |
124 | struct spi_master *master; | 117 | struct spi_master *master; |
125 | struct clk *ick; | ||
126 | struct clk *fck; | ||
127 | /* Virtual base address of the controller */ | 118 | /* Virtual base address of the controller */ |
128 | void __iomem *base; | 119 | void __iomem *base; |
129 | unsigned long phys; | 120 | unsigned long phys; |
130 | /* SPI1 has 4 channels, while SPI2 has 2 */ | 121 | /* SPI1 has 4 channels, while SPI2 has 2 */ |
131 | struct omap2_mcspi_dma *dma_channels; | 122 | struct omap2_mcspi_dma *dma_channels; |
123 | struct device *dev; | ||
132 | }; | 124 | }; |
133 | 125 | ||
134 | struct omap2_mcspi_cs { | 126 | struct omap2_mcspi_cs { |
@@ -144,7 +136,6 @@ struct omap2_mcspi_cs { | |||
144 | * corresponding registers are modified. | 136 | * corresponding registers are modified. |
145 | */ | 137 | */ |
146 | struct omap2_mcspi_regs { | 138 | struct omap2_mcspi_regs { |
147 | u32 sysconfig; | ||
148 | u32 modulctrl; | 139 | u32 modulctrl; |
149 | u32 wakeupenable; | 140 | u32 wakeupenable; |
150 | struct list_head cs; | 141 | struct list_head cs; |
@@ -268,9 +259,6 @@ static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi) | |||
268 | mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, | 259 | mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, |
269 | omap2_mcspi_ctx[spi_cntrl->bus_num - 1].modulctrl); | 260 | omap2_mcspi_ctx[spi_cntrl->bus_num - 1].modulctrl); |
270 | 261 | ||
271 | mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_SYSCONFIG, | ||
272 | omap2_mcspi_ctx[spi_cntrl->bus_num - 1].sysconfig); | ||
273 | |||
274 | mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, | 262 | mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, |
275 | omap2_mcspi_ctx[spi_cntrl->bus_num - 1].wakeupenable); | 263 | omap2_mcspi_ctx[spi_cntrl->bus_num - 1].wakeupenable); |
276 | 264 | ||
@@ -280,20 +268,12 @@ static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi) | |||
280 | } | 268 | } |
281 | static void omap2_mcspi_disable_clocks(struct omap2_mcspi *mcspi) | 269 | static void omap2_mcspi_disable_clocks(struct omap2_mcspi *mcspi) |
282 | { | 270 | { |
283 | clk_disable(mcspi->ick); | 271 | pm_runtime_put_sync(mcspi->dev); |
284 | clk_disable(mcspi->fck); | ||
285 | } | 272 | } |
286 | 273 | ||
287 | static int omap2_mcspi_enable_clocks(struct omap2_mcspi *mcspi) | 274 | static int omap2_mcspi_enable_clocks(struct omap2_mcspi *mcspi) |
288 | { | 275 | { |
289 | if (clk_enable(mcspi->ick)) | 276 | return pm_runtime_get_sync(mcspi->dev); |
290 | return -ENODEV; | ||
291 | if (clk_enable(mcspi->fck)) | ||
292 | return -ENODEV; | ||
293 | |||
294 | omap2_mcspi_restore_ctx(mcspi); | ||
295 | |||
296 | return 0; | ||
297 | } | 277 | } |
298 | 278 | ||
299 | static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit) | 279 | static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit) |
@@ -819,8 +799,9 @@ static int omap2_mcspi_setup(struct spi_device *spi) | |||
819 | return ret; | 799 | return ret; |
820 | } | 800 | } |
821 | 801 | ||
822 | if (omap2_mcspi_enable_clocks(mcspi)) | 802 | ret = omap2_mcspi_enable_clocks(mcspi); |
823 | return -ENODEV; | 803 | if (ret < 0) |
804 | return ret; | ||
824 | 805 | ||
825 | ret = omap2_mcspi_setup_transfer(spi, NULL); | 806 | ret = omap2_mcspi_setup_transfer(spi, NULL); |
826 | omap2_mcspi_disable_clocks(mcspi); | 807 | omap2_mcspi_disable_clocks(mcspi); |
@@ -863,10 +844,11 @@ static void omap2_mcspi_work(struct work_struct *work) | |||
863 | struct omap2_mcspi *mcspi; | 844 | struct omap2_mcspi *mcspi; |
864 | 845 | ||
865 | mcspi = container_of(work, struct omap2_mcspi, work); | 846 | mcspi = container_of(work, struct omap2_mcspi, work); |
866 | spin_lock_irq(&mcspi->lock); | ||
867 | 847 | ||
868 | if (omap2_mcspi_enable_clocks(mcspi)) | 848 | if (omap2_mcspi_enable_clocks(mcspi) < 0) |
869 | goto out; | 849 | return; |
850 | |||
851 | spin_lock_irq(&mcspi->lock); | ||
870 | 852 | ||
871 | /* We only enable one channel at a time -- the one whose message is | 853 | /* We only enable one channel at a time -- the one whose message is |
872 | * at the head of the queue -- although this controller would gladly | 854 | * at the head of the queue -- although this controller would gladly |
@@ -979,10 +961,9 @@ static void omap2_mcspi_work(struct work_struct *work) | |||
979 | spin_lock_irq(&mcspi->lock); | 961 | spin_lock_irq(&mcspi->lock); |
980 | } | 962 | } |
981 | 963 | ||
982 | omap2_mcspi_disable_clocks(mcspi); | ||
983 | |||
984 | out: | ||
985 | spin_unlock_irq(&mcspi->lock); | 964 | spin_unlock_irq(&mcspi->lock); |
965 | |||
966 | omap2_mcspi_disable_clocks(mcspi); | ||
986 | } | 967 | } |
987 | 968 | ||
988 | static int omap2_mcspi_transfer(struct spi_device *spi, struct spi_message *m) | 969 | static int omap2_mcspi_transfer(struct spi_device *spi, struct spi_message *m) |
@@ -1058,25 +1039,15 @@ static int omap2_mcspi_transfer(struct spi_device *spi, struct spi_message *m) | |||
1058 | return 0; | 1039 | return 0; |
1059 | } | 1040 | } |
1060 | 1041 | ||
1061 | static int __init omap2_mcspi_reset(struct omap2_mcspi *mcspi) | 1042 | static int __init omap2_mcspi_master_setup(struct omap2_mcspi *mcspi) |
1062 | { | 1043 | { |
1063 | struct spi_master *master = mcspi->master; | 1044 | struct spi_master *master = mcspi->master; |
1064 | u32 tmp; | 1045 | u32 tmp; |
1046 | int ret = 0; | ||
1065 | 1047 | ||
1066 | if (omap2_mcspi_enable_clocks(mcspi)) | 1048 | ret = omap2_mcspi_enable_clocks(mcspi); |
1067 | return -1; | 1049 | if (ret < 0) |
1068 | 1050 | return ret; | |
1069 | mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG, | ||
1070 | OMAP2_MCSPI_SYSCONFIG_SOFTRESET); | ||
1071 | do { | ||
1072 | tmp = mcspi_read_reg(master, OMAP2_MCSPI_SYSSTATUS); | ||
1073 | } while (!(tmp & OMAP2_MCSPI_SYSSTATUS_RESETDONE)); | ||
1074 | |||
1075 | tmp = OMAP2_MCSPI_SYSCONFIG_AUTOIDLE | | ||
1076 | OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP | | ||
1077 | OMAP2_MCSPI_SYSCONFIG_SMARTIDLE; | ||
1078 | mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG, tmp); | ||
1079 | omap2_mcspi_ctx[master->bus_num - 1].sysconfig = tmp; | ||
1080 | 1051 | ||
1081 | tmp = OMAP2_MCSPI_WAKEUPENABLE_WKEN; | 1052 | tmp = OMAP2_MCSPI_WAKEUPENABLE_WKEN; |
1082 | mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, tmp); | 1053 | mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, tmp); |
@@ -1087,91 +1058,26 @@ static int __init omap2_mcspi_reset(struct omap2_mcspi *mcspi) | |||
1087 | return 0; | 1058 | return 0; |
1088 | } | 1059 | } |
1089 | 1060 | ||
1090 | static u8 __initdata spi1_rxdma_id [] = { | 1061 | static int omap_mcspi_runtime_resume(struct device *dev) |
1091 | OMAP24XX_DMA_SPI1_RX0, | 1062 | { |
1092 | OMAP24XX_DMA_SPI1_RX1, | 1063 | struct omap2_mcspi *mcspi; |
1093 | OMAP24XX_DMA_SPI1_RX2, | 1064 | struct spi_master *master; |
1094 | OMAP24XX_DMA_SPI1_RX3, | ||
1095 | }; | ||
1096 | |||
1097 | static u8 __initdata spi1_txdma_id [] = { | ||
1098 | OMAP24XX_DMA_SPI1_TX0, | ||
1099 | OMAP24XX_DMA_SPI1_TX1, | ||
1100 | OMAP24XX_DMA_SPI1_TX2, | ||
1101 | OMAP24XX_DMA_SPI1_TX3, | ||
1102 | }; | ||
1103 | |||
1104 | static u8 __initdata spi2_rxdma_id[] = { | ||
1105 | OMAP24XX_DMA_SPI2_RX0, | ||
1106 | OMAP24XX_DMA_SPI2_RX1, | ||
1107 | }; | ||
1108 | |||
1109 | static u8 __initdata spi2_txdma_id[] = { | ||
1110 | OMAP24XX_DMA_SPI2_TX0, | ||
1111 | OMAP24XX_DMA_SPI2_TX1, | ||
1112 | }; | ||
1113 | |||
1114 | #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) \ | ||
1115 | || defined(CONFIG_ARCH_OMAP4) | ||
1116 | static u8 __initdata spi3_rxdma_id[] = { | ||
1117 | OMAP24XX_DMA_SPI3_RX0, | ||
1118 | OMAP24XX_DMA_SPI3_RX1, | ||
1119 | }; | ||
1120 | 1065 | ||
1121 | static u8 __initdata spi3_txdma_id[] = { | 1066 | master = dev_get_drvdata(dev); |
1122 | OMAP24XX_DMA_SPI3_TX0, | 1067 | mcspi = spi_master_get_devdata(master); |
1123 | OMAP24XX_DMA_SPI3_TX1, | 1068 | omap2_mcspi_restore_ctx(mcspi); |
1124 | }; | ||
1125 | #endif | ||
1126 | 1069 | ||
1127 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) | 1070 | return 0; |
1128 | static u8 __initdata spi4_rxdma_id[] = { | 1071 | } |
1129 | OMAP34XX_DMA_SPI4_RX0, | ||
1130 | }; | ||
1131 | 1072 | ||
1132 | static u8 __initdata spi4_txdma_id[] = { | ||
1133 | OMAP34XX_DMA_SPI4_TX0, | ||
1134 | }; | ||
1135 | #endif | ||
1136 | 1073 | ||
1137 | static int __init omap2_mcspi_probe(struct platform_device *pdev) | 1074 | static int __init omap2_mcspi_probe(struct platform_device *pdev) |
1138 | { | 1075 | { |
1139 | struct spi_master *master; | 1076 | struct spi_master *master; |
1077 | struct omap2_mcspi_platform_config *pdata = pdev->dev.platform_data; | ||
1140 | struct omap2_mcspi *mcspi; | 1078 | struct omap2_mcspi *mcspi; |
1141 | struct resource *r; | 1079 | struct resource *r; |
1142 | int status = 0, i; | 1080 | int status = 0, i; |
1143 | const u8 *rxdma_id, *txdma_id; | ||
1144 | unsigned num_chipselect; | ||
1145 | |||
1146 | switch (pdev->id) { | ||
1147 | case 1: | ||
1148 | rxdma_id = spi1_rxdma_id; | ||
1149 | txdma_id = spi1_txdma_id; | ||
1150 | num_chipselect = 4; | ||
1151 | break; | ||
1152 | case 2: | ||
1153 | rxdma_id = spi2_rxdma_id; | ||
1154 | txdma_id = spi2_txdma_id; | ||
1155 | num_chipselect = 2; | ||
1156 | break; | ||
1157 | #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) \ | ||
1158 | || defined(CONFIG_ARCH_OMAP4) | ||
1159 | case 3: | ||
1160 | rxdma_id = spi3_rxdma_id; | ||
1161 | txdma_id = spi3_txdma_id; | ||
1162 | num_chipselect = 2; | ||
1163 | break; | ||
1164 | #endif | ||
1165 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) | ||
1166 | case 4: | ||
1167 | rxdma_id = spi4_rxdma_id; | ||
1168 | txdma_id = spi4_txdma_id; | ||
1169 | num_chipselect = 1; | ||
1170 | break; | ||
1171 | #endif | ||
1172 | default: | ||
1173 | return -EINVAL; | ||
1174 | } | ||
1175 | 1081 | ||
1176 | master = spi_alloc_master(&pdev->dev, sizeof *mcspi); | 1082 | master = spi_alloc_master(&pdev->dev, sizeof *mcspi); |
1177 | if (master == NULL) { | 1083 | if (master == NULL) { |
@@ -1188,7 +1094,7 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev) | |||
1188 | master->setup = omap2_mcspi_setup; | 1094 | master->setup = omap2_mcspi_setup; |
1189 | master->transfer = omap2_mcspi_transfer; | 1095 | master->transfer = omap2_mcspi_transfer; |
1190 | master->cleanup = omap2_mcspi_cleanup; | 1096 | master->cleanup = omap2_mcspi_cleanup; |
1191 | master->num_chipselect = num_chipselect; | 1097 | master->num_chipselect = pdata->num_cs; |
1192 | 1098 | ||
1193 | dev_set_drvdata(&pdev->dev, master); | 1099 | dev_set_drvdata(&pdev->dev, master); |
1194 | 1100 | ||
@@ -1206,49 +1112,62 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev) | |||
1206 | goto err1; | 1112 | goto err1; |
1207 | } | 1113 | } |
1208 | 1114 | ||
1115 | r->start += pdata->regs_offset; | ||
1116 | r->end += pdata->regs_offset; | ||
1209 | mcspi->phys = r->start; | 1117 | mcspi->phys = r->start; |
1210 | mcspi->base = ioremap(r->start, r->end - r->start + 1); | 1118 | mcspi->base = ioremap(r->start, r->end - r->start + 1); |
1211 | if (!mcspi->base) { | 1119 | if (!mcspi->base) { |
1212 | dev_dbg(&pdev->dev, "can't ioremap MCSPI\n"); | 1120 | dev_dbg(&pdev->dev, "can't ioremap MCSPI\n"); |
1213 | status = -ENOMEM; | 1121 | status = -ENOMEM; |
1214 | goto err1aa; | 1122 | goto err2; |
1215 | } | 1123 | } |
1216 | 1124 | ||
1125 | mcspi->dev = &pdev->dev; | ||
1217 | INIT_WORK(&mcspi->work, omap2_mcspi_work); | 1126 | INIT_WORK(&mcspi->work, omap2_mcspi_work); |
1218 | 1127 | ||
1219 | spin_lock_init(&mcspi->lock); | 1128 | spin_lock_init(&mcspi->lock); |
1220 | INIT_LIST_HEAD(&mcspi->msg_queue); | 1129 | INIT_LIST_HEAD(&mcspi->msg_queue); |
1221 | INIT_LIST_HEAD(&omap2_mcspi_ctx[master->bus_num - 1].cs); | 1130 | INIT_LIST_HEAD(&omap2_mcspi_ctx[master->bus_num - 1].cs); |
1222 | 1131 | ||
1223 | mcspi->ick = clk_get(&pdev->dev, "ick"); | ||
1224 | if (IS_ERR(mcspi->ick)) { | ||
1225 | dev_dbg(&pdev->dev, "can't get mcspi_ick\n"); | ||
1226 | status = PTR_ERR(mcspi->ick); | ||
1227 | goto err1a; | ||
1228 | } | ||
1229 | mcspi->fck = clk_get(&pdev->dev, "fck"); | ||
1230 | if (IS_ERR(mcspi->fck)) { | ||
1231 | dev_dbg(&pdev->dev, "can't get mcspi_fck\n"); | ||
1232 | status = PTR_ERR(mcspi->fck); | ||
1233 | goto err2; | ||
1234 | } | ||
1235 | |||
1236 | mcspi->dma_channels = kcalloc(master->num_chipselect, | 1132 | mcspi->dma_channels = kcalloc(master->num_chipselect, |
1237 | sizeof(struct omap2_mcspi_dma), | 1133 | sizeof(struct omap2_mcspi_dma), |
1238 | GFP_KERNEL); | 1134 | GFP_KERNEL); |
1239 | 1135 | ||
1240 | if (mcspi->dma_channels == NULL) | 1136 | if (mcspi->dma_channels == NULL) |
1241 | goto err3; | 1137 | goto err2; |
1138 | |||
1139 | for (i = 0; i < master->num_chipselect; i++) { | ||
1140 | char dma_ch_name[14]; | ||
1141 | struct resource *dma_res; | ||
1142 | |||
1143 | sprintf(dma_ch_name, "rx%d", i); | ||
1144 | dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA, | ||
1145 | dma_ch_name); | ||
1146 | if (!dma_res) { | ||
1147 | dev_dbg(&pdev->dev, "cannot get DMA RX channel\n"); | ||
1148 | status = -ENODEV; | ||
1149 | break; | ||
1150 | } | ||
1242 | 1151 | ||
1243 | for (i = 0; i < num_chipselect; i++) { | ||
1244 | mcspi->dma_channels[i].dma_rx_channel = -1; | 1152 | mcspi->dma_channels[i].dma_rx_channel = -1; |
1245 | mcspi->dma_channels[i].dma_rx_sync_dev = rxdma_id[i]; | 1153 | mcspi->dma_channels[i].dma_rx_sync_dev = dma_res->start; |
1154 | sprintf(dma_ch_name, "tx%d", i); | ||
1155 | dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA, | ||
1156 | dma_ch_name); | ||
1157 | if (!dma_res) { | ||
1158 | dev_dbg(&pdev->dev, "cannot get DMA TX channel\n"); | ||
1159 | status = -ENODEV; | ||
1160 | break; | ||
1161 | } | ||
1162 | |||
1246 | mcspi->dma_channels[i].dma_tx_channel = -1; | 1163 | mcspi->dma_channels[i].dma_tx_channel = -1; |
1247 | mcspi->dma_channels[i].dma_tx_sync_dev = txdma_id[i]; | 1164 | mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start; |
1248 | } | 1165 | } |
1249 | 1166 | ||
1250 | if (omap2_mcspi_reset(mcspi) < 0) | 1167 | pm_runtime_enable(&pdev->dev); |
1251 | goto err4; | 1168 | |
1169 | if (status || omap2_mcspi_master_setup(mcspi) < 0) | ||
1170 | goto err3; | ||
1252 | 1171 | ||
1253 | status = spi_register_master(master); | 1172 | status = spi_register_master(master); |
1254 | if (status < 0) | 1173 | if (status < 0) |
@@ -1257,17 +1176,13 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev) | |||
1257 | return status; | 1176 | return status; |
1258 | 1177 | ||
1259 | err4: | 1178 | err4: |
1260 | kfree(mcspi->dma_channels); | 1179 | spi_master_put(master); |
1261 | err3: | 1180 | err3: |
1262 | clk_put(mcspi->fck); | 1181 | kfree(mcspi->dma_channels); |
1263 | err2: | 1182 | err2: |
1264 | clk_put(mcspi->ick); | ||
1265 | err1a: | ||
1266 | iounmap(mcspi->base); | ||
1267 | err1aa: | ||
1268 | release_mem_region(r->start, (r->end - r->start) + 1); | 1183 | release_mem_region(r->start, (r->end - r->start) + 1); |
1184 | iounmap(mcspi->base); | ||
1269 | err1: | 1185 | err1: |
1270 | spi_master_put(master); | ||
1271 | return status; | 1186 | return status; |
1272 | } | 1187 | } |
1273 | 1188 | ||
@@ -1283,9 +1198,7 @@ static int __exit omap2_mcspi_remove(struct platform_device *pdev) | |||
1283 | mcspi = spi_master_get_devdata(master); | 1198 | mcspi = spi_master_get_devdata(master); |
1284 | dma_channels = mcspi->dma_channels; | 1199 | dma_channels = mcspi->dma_channels; |
1285 | 1200 | ||
1286 | clk_put(mcspi->fck); | 1201 | omap2_mcspi_disable_clocks(mcspi); |
1287 | clk_put(mcspi->ick); | ||
1288 | |||
1289 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 1202 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1290 | release_mem_region(r->start, (r->end - r->start) + 1); | 1203 | release_mem_region(r->start, (r->end - r->start) + 1); |
1291 | 1204 | ||
@@ -1336,6 +1249,7 @@ static int omap2_mcspi_resume(struct device *dev) | |||
1336 | 1249 | ||
1337 | static const struct dev_pm_ops omap2_mcspi_pm_ops = { | 1250 | static const struct dev_pm_ops omap2_mcspi_pm_ops = { |
1338 | .resume = omap2_mcspi_resume, | 1251 | .resume = omap2_mcspi_resume, |
1252 | .runtime_resume = omap_mcspi_runtime_resume, | ||
1339 | }; | 1253 | }; |
1340 | 1254 | ||
1341 | static struct platform_driver omap2_mcspi_driver = { | 1255 | static struct platform_driver omap2_mcspi_driver = { |