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-rw-r--r--drivers/spi/dw_spi.c944
1 files changed, 944 insertions, 0 deletions
diff --git a/drivers/spi/dw_spi.c b/drivers/spi/dw_spi.c
new file mode 100644
index 000000000000..31620fae77be
--- /dev/null
+++ b/drivers/spi/dw_spi.c
@@ -0,0 +1,944 @@
1/*
2 * dw_spi.c - Designware SPI core controller driver (refer pxa2xx_spi.c)
3 *
4 * Copyright (c) 2009, Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 */
19
20#include <linux/dma-mapping.h>
21#include <linux/interrupt.h>
22#include <linux/highmem.h>
23#include <linux/delay.h>
24
25#include <linux/spi/dw_spi.h>
26#include <linux/spi/spi.h>
27
28#ifdef CONFIG_DEBUG_FS
29#include <linux/debugfs.h>
30#endif
31
32#define START_STATE ((void *)0)
33#define RUNNING_STATE ((void *)1)
34#define DONE_STATE ((void *)2)
35#define ERROR_STATE ((void *)-1)
36
37#define QUEUE_RUNNING 0
38#define QUEUE_STOPPED 1
39
40#define MRST_SPI_DEASSERT 0
41#define MRST_SPI_ASSERT 1
42
43/* Slave spi_dev related */
44struct chip_data {
45 u16 cr0;
46 u8 cs; /* chip select pin */
47 u8 n_bytes; /* current is a 1/2/4 byte op */
48 u8 tmode; /* TR/TO/RO/EEPROM */
49 u8 type; /* SPI/SSP/MicroWire */
50
51 u8 poll_mode; /* 1 means use poll mode */
52
53 u32 dma_width;
54 u32 rx_threshold;
55 u32 tx_threshold;
56 u8 enable_dma;
57 u8 bits_per_word;
58 u16 clk_div; /* baud rate divider */
59 u32 speed_hz; /* baud rate */
60 int (*write)(struct dw_spi *dws);
61 int (*read)(struct dw_spi *dws);
62 void (*cs_control)(u32 command);
63};
64
65#ifdef CONFIG_DEBUG_FS
66static int spi_show_regs_open(struct inode *inode, struct file *file)
67{
68 file->private_data = inode->i_private;
69 return 0;
70}
71
72#define SPI_REGS_BUFSIZE 1024
73static ssize_t spi_show_regs(struct file *file, char __user *user_buf,
74 size_t count, loff_t *ppos)
75{
76 struct dw_spi *dws;
77 char *buf;
78 u32 len = 0;
79 ssize_t ret;
80
81 dws = file->private_data;
82
83 buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
84 if (!buf)
85 return 0;
86
87 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
88 "MRST SPI0 registers:\n");
89 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
90 "=================================\n");
91 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
92 "CTRL0: \t\t0x%08x\n", dw_readl(dws, ctrl0));
93 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
94 "CTRL1: \t\t0x%08x\n", dw_readl(dws, ctrl1));
95 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
96 "SSIENR: \t0x%08x\n", dw_readl(dws, ssienr));
97 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
98 "SER: \t\t0x%08x\n", dw_readl(dws, ser));
99 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
100 "BAUDR: \t\t0x%08x\n", dw_readl(dws, baudr));
101 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
102 "TXFTLR: \t0x%08x\n", dw_readl(dws, txfltr));
103 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
104 "RXFTLR: \t0x%08x\n", dw_readl(dws, rxfltr));
105 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
106 "TXFLR: \t\t0x%08x\n", dw_readl(dws, txflr));
107 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
108 "RXFLR: \t\t0x%08x\n", dw_readl(dws, rxflr));
109 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
110 "SR: \t\t0x%08x\n", dw_readl(dws, sr));
111 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
112 "IMR: \t\t0x%08x\n", dw_readl(dws, imr));
113 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
114 "ISR: \t\t0x%08x\n", dw_readl(dws, isr));
115 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
116 "DMACR: \t\t0x%08x\n", dw_readl(dws, dmacr));
117 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
118 "DMATDLR: \t0x%08x\n", dw_readl(dws, dmatdlr));
119 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
120 "DMARDLR: \t0x%08x\n", dw_readl(dws, dmardlr));
121 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
122 "=================================\n");
123
124 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
125 kfree(buf);
126 return ret;
127}
128
129static const struct file_operations mrst_spi_regs_ops = {
130 .owner = THIS_MODULE,
131 .open = spi_show_regs_open,
132 .read = spi_show_regs,
133};
134
135static int mrst_spi_debugfs_init(struct dw_spi *dws)
136{
137 dws->debugfs = debugfs_create_dir("mrst_spi", NULL);
138 if (!dws->debugfs)
139 return -ENOMEM;
140
141 debugfs_create_file("registers", S_IFREG | S_IRUGO,
142 dws->debugfs, (void *)dws, &mrst_spi_regs_ops);
143 return 0;
144}
145
146static void mrst_spi_debugfs_remove(struct dw_spi *dws)
147{
148 if (dws->debugfs)
149 debugfs_remove_recursive(dws->debugfs);
150}
151
152#else
153static inline int mrst_spi_debugfs_init(struct dw_spi *dws)
154{
155}
156
157static inline void mrst_spi_debugfs_remove(struct dw_spi *dws)
158{
159}
160#endif /* CONFIG_DEBUG_FS */
161
162static void wait_till_not_busy(struct dw_spi *dws)
163{
164 unsigned long end = jiffies + usecs_to_jiffies(1000);
165
166 while (time_before(jiffies, end)) {
167 if (!(dw_readw(dws, sr) & SR_BUSY))
168 return;
169 }
170 dev_err(&dws->master->dev,
171 "DW SPI: Stutus keeps busy for 1000us after a read/write!\n");
172}
173
174static void flush(struct dw_spi *dws)
175{
176 while (dw_readw(dws, sr) & SR_RF_NOT_EMPT)
177 dw_readw(dws, dr);
178
179 wait_till_not_busy(dws);
180}
181
182static void null_cs_control(u32 command)
183{
184}
185
186static int null_writer(struct dw_spi *dws)
187{
188 u8 n_bytes = dws->n_bytes;
189
190 if (!(dw_readw(dws, sr) & SR_TF_NOT_FULL)
191 || (dws->tx == dws->tx_end))
192 return 0;
193 dw_writew(dws, dr, 0);
194 dws->tx += n_bytes;
195
196 wait_till_not_busy(dws);
197 return 1;
198}
199
200static int null_reader(struct dw_spi *dws)
201{
202 u8 n_bytes = dws->n_bytes;
203
204 while ((dw_readw(dws, sr) & SR_RF_NOT_EMPT)
205 && (dws->rx < dws->rx_end)) {
206 dw_readw(dws, dr);
207 dws->rx += n_bytes;
208 }
209 wait_till_not_busy(dws);
210 return dws->rx == dws->rx_end;
211}
212
213static int u8_writer(struct dw_spi *dws)
214{
215 if (!(dw_readw(dws, sr) & SR_TF_NOT_FULL)
216 || (dws->tx == dws->tx_end))
217 return 0;
218
219 dw_writew(dws, dr, *(u8 *)(dws->tx));
220 ++dws->tx;
221
222 wait_till_not_busy(dws);
223 return 1;
224}
225
226static int u8_reader(struct dw_spi *dws)
227{
228 while ((dw_readw(dws, sr) & SR_RF_NOT_EMPT)
229 && (dws->rx < dws->rx_end)) {
230 *(u8 *)(dws->rx) = dw_readw(dws, dr);
231 ++dws->rx;
232 }
233
234 wait_till_not_busy(dws);
235 return dws->rx == dws->rx_end;
236}
237
238static int u16_writer(struct dw_spi *dws)
239{
240 if (!(dw_readw(dws, sr) & SR_TF_NOT_FULL)
241 || (dws->tx == dws->tx_end))
242 return 0;
243
244 dw_writew(dws, dr, *(u16 *)(dws->tx));
245 dws->tx += 2;
246
247 wait_till_not_busy(dws);
248 return 1;
249}
250
251static int u16_reader(struct dw_spi *dws)
252{
253 u16 temp;
254
255 while ((dw_readw(dws, sr) & SR_RF_NOT_EMPT)
256 && (dws->rx < dws->rx_end)) {
257 temp = dw_readw(dws, dr);
258 *(u16 *)(dws->rx) = temp;
259 dws->rx += 2;
260 }
261
262 wait_till_not_busy(dws);
263 return dws->rx == dws->rx_end;
264}
265
266static void *next_transfer(struct dw_spi *dws)
267{
268 struct spi_message *msg = dws->cur_msg;
269 struct spi_transfer *trans = dws->cur_transfer;
270
271 /* Move to next transfer */
272 if (trans->transfer_list.next != &msg->transfers) {
273 dws->cur_transfer =
274 list_entry(trans->transfer_list.next,
275 struct spi_transfer,
276 transfer_list);
277 return RUNNING_STATE;
278 } else
279 return DONE_STATE;
280}
281
282/*
283 * Note: first step is the protocol driver prepares
284 * a dma-capable memory, and this func just need translate
285 * the virt addr to physical
286 */
287static int map_dma_buffers(struct dw_spi *dws)
288{
289 if (!dws->cur_msg->is_dma_mapped || !dws->dma_inited
290 || !dws->cur_chip->enable_dma)
291 return 0;
292
293 if (dws->cur_transfer->tx_dma)
294 dws->tx_dma = dws->cur_transfer->tx_dma;
295
296 if (dws->cur_transfer->rx_dma)
297 dws->rx_dma = dws->cur_transfer->rx_dma;
298
299 return 1;
300}
301
302/* Caller already set message->status; dma and pio irqs are blocked */
303static void giveback(struct dw_spi *dws)
304{
305 struct spi_transfer *last_transfer;
306 unsigned long flags;
307 struct spi_message *msg;
308
309 spin_lock_irqsave(&dws->lock, flags);
310 msg = dws->cur_msg;
311 dws->cur_msg = NULL;
312 dws->cur_transfer = NULL;
313 dws->prev_chip = dws->cur_chip;
314 dws->cur_chip = NULL;
315 dws->dma_mapped = 0;
316 queue_work(dws->workqueue, &dws->pump_messages);
317 spin_unlock_irqrestore(&dws->lock, flags);
318
319 last_transfer = list_entry(msg->transfers.prev,
320 struct spi_transfer,
321 transfer_list);
322
323 if (!last_transfer->cs_change)
324 dws->cs_control(MRST_SPI_DEASSERT);
325
326 msg->state = NULL;
327 if (msg->complete)
328 msg->complete(msg->context);
329}
330
331static void int_error_stop(struct dw_spi *dws, const char *msg)
332{
333 /* Stop and reset hw */
334 flush(dws);
335 spi_enable_chip(dws, 0);
336
337 dev_err(&dws->master->dev, "%s\n", msg);
338 dws->cur_msg->state = ERROR_STATE;
339 tasklet_schedule(&dws->pump_transfers);
340}
341
342static void transfer_complete(struct dw_spi *dws)
343{
344 /* Update total byte transfered return count actual bytes read */
345 dws->cur_msg->actual_length += dws->len;
346
347 /* Move to next transfer */
348 dws->cur_msg->state = next_transfer(dws);
349
350 /* Handle end of message */
351 if (dws->cur_msg->state == DONE_STATE) {
352 dws->cur_msg->status = 0;
353 giveback(dws);
354 } else
355 tasklet_schedule(&dws->pump_transfers);
356}
357
358static irqreturn_t interrupt_transfer(struct dw_spi *dws)
359{
360 u16 irq_status, irq_mask = 0x3f;
361
362 irq_status = dw_readw(dws, isr) & irq_mask;
363 /* Error handling */
364 if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
365 dw_readw(dws, txoicr);
366 dw_readw(dws, rxoicr);
367 dw_readw(dws, rxuicr);
368 int_error_stop(dws, "interrupt_transfer: fifo overrun");
369 return IRQ_HANDLED;
370 }
371
372 /* INT comes from tx */
373 if (dws->tx && (irq_status & SPI_INT_TXEI)) {
374 while (dws->tx < dws->tx_end)
375 dws->write(dws);
376
377 if (dws->tx == dws->tx_end) {
378 spi_mask_intr(dws, SPI_INT_TXEI);
379 transfer_complete(dws);
380 }
381 }
382
383 /* INT comes from rx */
384 if (dws->rx && (irq_status & SPI_INT_RXFI)) {
385 if (dws->read(dws))
386 transfer_complete(dws);
387 }
388 return IRQ_HANDLED;
389}
390
391static irqreturn_t dw_spi_irq(int irq, void *dev_id)
392{
393 struct dw_spi *dws = dev_id;
394
395 if (!dws->cur_msg) {
396 spi_mask_intr(dws, SPI_INT_TXEI);
397 /* Never fail */
398 return IRQ_HANDLED;
399 }
400
401 return dws->transfer_handler(dws);
402}
403
404/* Must be called inside pump_transfers() */
405static void poll_transfer(struct dw_spi *dws)
406{
407 if (dws->tx) {
408 while (dws->write(dws))
409 dws->read(dws);
410 }
411
412 dws->read(dws);
413 transfer_complete(dws);
414}
415
416static void dma_transfer(struct dw_spi *dws, int cs_change)
417{
418}
419
420static void pump_transfers(unsigned long data)
421{
422 struct dw_spi *dws = (struct dw_spi *)data;
423 struct spi_message *message = NULL;
424 struct spi_transfer *transfer = NULL;
425 struct spi_transfer *previous = NULL;
426 struct spi_device *spi = NULL;
427 struct chip_data *chip = NULL;
428 u8 bits = 0;
429 u8 imask = 0;
430 u8 cs_change = 0;
431 u16 clk_div = 0;
432 u32 speed = 0;
433 u32 cr0 = 0;
434
435 /* Get current state information */
436 message = dws->cur_msg;
437 transfer = dws->cur_transfer;
438 chip = dws->cur_chip;
439 spi = message->spi;
440
441 if (message->state == ERROR_STATE) {
442 message->status = -EIO;
443 goto early_exit;
444 }
445
446 /* Handle end of message */
447 if (message->state == DONE_STATE) {
448 message->status = 0;
449 goto early_exit;
450 }
451
452 /* Delay if requested at end of transfer*/
453 if (message->state == RUNNING_STATE) {
454 previous = list_entry(transfer->transfer_list.prev,
455 struct spi_transfer,
456 transfer_list);
457 if (previous->delay_usecs)
458 udelay(previous->delay_usecs);
459 }
460
461 dws->n_bytes = chip->n_bytes;
462 dws->dma_width = chip->dma_width;
463 dws->cs_control = chip->cs_control;
464
465 dws->rx_dma = transfer->rx_dma;
466 dws->tx_dma = transfer->tx_dma;
467 dws->tx = (void *)transfer->tx_buf;
468 dws->tx_end = dws->tx + transfer->len;
469 dws->rx = transfer->rx_buf;
470 dws->rx_end = dws->rx + transfer->len;
471 dws->write = dws->tx ? chip->write : null_writer;
472 dws->read = dws->rx ? chip->read : null_reader;
473 dws->cs_change = transfer->cs_change;
474 dws->len = dws->cur_transfer->len;
475 if (chip != dws->prev_chip)
476 cs_change = 1;
477
478 cr0 = chip->cr0;
479
480 /* Handle per transfer options for bpw and speed */
481 if (transfer->speed_hz) {
482 speed = chip->speed_hz;
483
484 if (transfer->speed_hz != speed) {
485 speed = transfer->speed_hz;
486 if (speed > dws->max_freq) {
487 printk(KERN_ERR "MRST SPI0: unsupported"
488 "freq: %dHz\n", speed);
489 message->status = -EIO;
490 goto early_exit;
491 }
492
493 /* clk_div doesn't support odd number */
494 clk_div = dws->max_freq / speed;
495 clk_div = (clk_div >> 1) << 1;
496
497 chip->speed_hz = speed;
498 chip->clk_div = clk_div;
499 }
500 }
501 if (transfer->bits_per_word) {
502 bits = transfer->bits_per_word;
503
504 switch (bits) {
505 case 8:
506 dws->n_bytes = 1;
507 dws->dma_width = 1;
508 dws->read = (dws->read != null_reader) ?
509 u8_reader : null_reader;
510 dws->write = (dws->write != null_writer) ?
511 u8_writer : null_writer;
512 break;
513 case 16:
514 dws->n_bytes = 2;
515 dws->dma_width = 2;
516 dws->read = (dws->read != null_reader) ?
517 u16_reader : null_reader;
518 dws->write = (dws->write != null_writer) ?
519 u16_writer : null_writer;
520 break;
521 default:
522 printk(KERN_ERR "MRST SPI0: unsupported bits:"
523 "%db\n", bits);
524 message->status = -EIO;
525 goto early_exit;
526 }
527
528 cr0 = (bits - 1)
529 | (chip->type << SPI_FRF_OFFSET)
530 | (spi->mode << SPI_MODE_OFFSET)
531 | (chip->tmode << SPI_TMOD_OFFSET);
532 }
533 message->state = RUNNING_STATE;
534
535 /* Check if current transfer is a DMA transaction */
536 dws->dma_mapped = map_dma_buffers(dws);
537
538 if (!dws->dma_mapped && !chip->poll_mode) {
539 if (dws->rx)
540 imask |= SPI_INT_RXFI;
541 if (dws->tx)
542 imask |= SPI_INT_TXEI;
543 dws->transfer_handler = interrupt_transfer;
544 }
545
546 /*
547 * Reprogram registers only if
548 * 1. chip select changes
549 * 2. clk_div is changed
550 * 3. control value changes
551 */
552 if (dw_readw(dws, ctrl0) != cr0 || cs_change || clk_div) {
553 spi_enable_chip(dws, 0);
554
555 if (dw_readw(dws, ctrl0) != cr0)
556 dw_writew(dws, ctrl0, cr0);
557
558 /* Set the interrupt mask, for poll mode just diable all int */
559 spi_mask_intr(dws, 0xff);
560 if (!chip->poll_mode)
561 spi_umask_intr(dws, imask);
562
563 spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);
564 spi_chip_sel(dws, spi->chip_select);
565 spi_enable_chip(dws, 1);
566
567 if (cs_change)
568 dws->prev_chip = chip;
569 }
570
571 if (dws->dma_mapped)
572 dma_transfer(dws, cs_change);
573
574 if (chip->poll_mode)
575 poll_transfer(dws);
576
577 return;
578
579early_exit:
580 giveback(dws);
581 return;
582}
583
584static void pump_messages(struct work_struct *work)
585{
586 struct dw_spi *dws =
587 container_of(work, struct dw_spi, pump_messages);
588 unsigned long flags;
589
590 /* Lock queue and check for queue work */
591 spin_lock_irqsave(&dws->lock, flags);
592 if (list_empty(&dws->queue) || dws->run == QUEUE_STOPPED) {
593 dws->busy = 0;
594 spin_unlock_irqrestore(&dws->lock, flags);
595 return;
596 }
597
598 /* Make sure we are not already running a message */
599 if (dws->cur_msg) {
600 spin_unlock_irqrestore(&dws->lock, flags);
601 return;
602 }
603
604 /* Extract head of queue */
605 dws->cur_msg = list_entry(dws->queue.next, struct spi_message, queue);
606 list_del_init(&dws->cur_msg->queue);
607
608 /* Initial message state*/
609 dws->cur_msg->state = START_STATE;
610 dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,
611 struct spi_transfer,
612 transfer_list);
613 dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);
614
615 /* Mark as busy and launch transfers */
616 tasklet_schedule(&dws->pump_transfers);
617
618 dws->busy = 1;
619 spin_unlock_irqrestore(&dws->lock, flags);
620}
621
622/* spi_device use this to queue in their spi_msg */
623static int dw_spi_transfer(struct spi_device *spi, struct spi_message *msg)
624{
625 struct dw_spi *dws = spi_master_get_devdata(spi->master);
626 unsigned long flags;
627
628 spin_lock_irqsave(&dws->lock, flags);
629
630 if (dws->run == QUEUE_STOPPED) {
631 spin_unlock_irqrestore(&dws->lock, flags);
632 return -ESHUTDOWN;
633 }
634
635 msg->actual_length = 0;
636 msg->status = -EINPROGRESS;
637 msg->state = START_STATE;
638
639 list_add_tail(&msg->queue, &dws->queue);
640
641 if (dws->run == QUEUE_RUNNING && !dws->busy) {
642
643 if (dws->cur_transfer || dws->cur_msg)
644 queue_work(dws->workqueue,
645 &dws->pump_messages);
646 else {
647 /* If no other data transaction in air, just go */
648 spin_unlock_irqrestore(&dws->lock, flags);
649 pump_messages(&dws->pump_messages);
650 return 0;
651 }
652 }
653
654 spin_unlock_irqrestore(&dws->lock, flags);
655 return 0;
656}
657
658/* This may be called twice for each spi dev */
659static int dw_spi_setup(struct spi_device *spi)
660{
661 struct dw_spi_chip *chip_info = NULL;
662 struct chip_data *chip;
663
664 if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
665 return -EINVAL;
666
667 /* Only alloc on first setup */
668 chip = spi_get_ctldata(spi);
669 if (!chip) {
670 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
671 if (!chip)
672 return -ENOMEM;
673
674 chip->cs_control = null_cs_control;
675 chip->enable_dma = 0;
676 }
677
678 /*
679 * Protocol drivers may change the chip settings, so...
680 * if chip_info exists, use it
681 */
682 chip_info = spi->controller_data;
683
684 /* chip_info doesn't always exist */
685 if (chip_info) {
686 if (chip_info->cs_control)
687 chip->cs_control = chip_info->cs_control;
688
689 chip->poll_mode = chip_info->poll_mode;
690 chip->type = chip_info->type;
691
692 chip->rx_threshold = 0;
693 chip->tx_threshold = 0;
694
695 chip->enable_dma = chip_info->enable_dma;
696 }
697
698 if (spi->bits_per_word <= 8) {
699 chip->n_bytes = 1;
700 chip->dma_width = 1;
701 chip->read = u8_reader;
702 chip->write = u8_writer;
703 } else if (spi->bits_per_word <= 16) {
704 chip->n_bytes = 2;
705 chip->dma_width = 2;
706 chip->read = u16_reader;
707 chip->write = u16_writer;
708 } else {
709 /* Never take >16b case for MRST SPIC */
710 dev_err(&spi->dev, "invalid wordsize\n");
711 return -EINVAL;
712 }
713 chip->bits_per_word = spi->bits_per_word;
714
715 chip->speed_hz = spi->max_speed_hz;
716 if (chip->speed_hz)
717 chip->clk_div = 25000000 / chip->speed_hz;
718 else
719 chip->clk_div = 8; /* default value */
720
721 chip->tmode = 0; /* Tx & Rx */
722 /* Default SPI mode is SCPOL = 0, SCPH = 0 */
723 chip->cr0 = (chip->bits_per_word - 1)
724 | (chip->type << SPI_FRF_OFFSET)
725 | (spi->mode << SPI_MODE_OFFSET)
726 | (chip->tmode << SPI_TMOD_OFFSET);
727
728 spi_set_ctldata(spi, chip);
729 return 0;
730}
731
732static void dw_spi_cleanup(struct spi_device *spi)
733{
734 struct chip_data *chip = spi_get_ctldata(spi);
735 kfree(chip);
736}
737
738static int __init init_queue(struct dw_spi *dws)
739{
740 INIT_LIST_HEAD(&dws->queue);
741 spin_lock_init(&dws->lock);
742
743 dws->run = QUEUE_STOPPED;
744 dws->busy = 0;
745
746 tasklet_init(&dws->pump_transfers,
747 pump_transfers, (unsigned long)dws);
748
749 INIT_WORK(&dws->pump_messages, pump_messages);
750 dws->workqueue = create_singlethread_workqueue(
751 dev_name(dws->master->dev.parent));
752 if (dws->workqueue == NULL)
753 return -EBUSY;
754
755 return 0;
756}
757
758static int start_queue(struct dw_spi *dws)
759{
760 unsigned long flags;
761
762 spin_lock_irqsave(&dws->lock, flags);
763
764 if (dws->run == QUEUE_RUNNING || dws->busy) {
765 spin_unlock_irqrestore(&dws->lock, flags);
766 return -EBUSY;
767 }
768
769 dws->run = QUEUE_RUNNING;
770 dws->cur_msg = NULL;
771 dws->cur_transfer = NULL;
772 dws->cur_chip = NULL;
773 dws->prev_chip = NULL;
774 spin_unlock_irqrestore(&dws->lock, flags);
775
776 queue_work(dws->workqueue, &dws->pump_messages);
777
778 return 0;
779}
780
781static int stop_queue(struct dw_spi *dws)
782{
783 unsigned long flags;
784 unsigned limit = 50;
785 int status = 0;
786
787 spin_lock_irqsave(&dws->lock, flags);
788 dws->run = QUEUE_STOPPED;
789 while (!list_empty(&dws->queue) && dws->busy && limit--) {
790 spin_unlock_irqrestore(&dws->lock, flags);
791 msleep(10);
792 spin_lock_irqsave(&dws->lock, flags);
793 }
794
795 if (!list_empty(&dws->queue) || dws->busy)
796 status = -EBUSY;
797 spin_unlock_irqrestore(&dws->lock, flags);
798
799 return status;
800}
801
802static int destroy_queue(struct dw_spi *dws)
803{
804 int status;
805
806 status = stop_queue(dws);
807 if (status != 0)
808 return status;
809 destroy_workqueue(dws->workqueue);
810 return 0;
811}
812
813/* Restart the controller, disable all interrupts, clean rx fifo */
814static void spi_hw_init(struct dw_spi *dws)
815{
816 spi_enable_chip(dws, 0);
817 spi_mask_intr(dws, 0xff);
818 spi_enable_chip(dws, 1);
819 flush(dws);
820}
821
822int __devinit dw_spi_add_host(struct dw_spi *dws)
823{
824 struct spi_master *master;
825 int ret;
826
827 BUG_ON(dws == NULL);
828
829 master = spi_alloc_master(dws->parent_dev, 0);
830 if (!master) {
831 ret = -ENOMEM;
832 goto exit;
833 }
834
835 dws->master = master;
836 dws->type = SSI_MOTO_SPI;
837 dws->prev_chip = NULL;
838 dws->dma_inited = 0;
839 dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60);
840
841 ret = request_irq(dws->irq, dw_spi_irq, 0,
842 "dw_spi", dws);
843 if (ret < 0) {
844 dev_err(&master->dev, "can not get IRQ\n");
845 goto err_free_master;
846 }
847
848 master->mode_bits = SPI_CPOL | SPI_CPHA;
849 master->bus_num = dws->bus_num;
850 master->num_chipselect = dws->num_cs;
851 master->cleanup = dw_spi_cleanup;
852 master->setup = dw_spi_setup;
853 master->transfer = dw_spi_transfer;
854
855 dws->dma_inited = 0;
856
857 /* Basic HW init */
858 spi_hw_init(dws);
859
860 /* Initial and start queue */
861 ret = init_queue(dws);
862 if (ret) {
863 dev_err(&master->dev, "problem initializing queue\n");
864 goto err_diable_hw;
865 }
866 ret = start_queue(dws);
867 if (ret) {
868 dev_err(&master->dev, "problem starting queue\n");
869 goto err_diable_hw;
870 }
871
872 spi_master_set_devdata(master, dws);
873 ret = spi_register_master(master);
874 if (ret) {
875 dev_err(&master->dev, "problem registering spi master\n");
876 goto err_queue_alloc;
877 }
878
879 mrst_spi_debugfs_init(dws);
880 return 0;
881
882err_queue_alloc:
883 destroy_queue(dws);
884err_diable_hw:
885 spi_enable_chip(dws, 0);
886 free_irq(dws->irq, dws);
887err_free_master:
888 spi_master_put(master);
889exit:
890 return ret;
891}
892EXPORT_SYMBOL(dw_spi_add_host);
893
894void __devexit dw_spi_remove_host(struct dw_spi *dws)
895{
896 int status = 0;
897
898 if (!dws)
899 return;
900 mrst_spi_debugfs_remove(dws);
901
902 /* Remove the queue */
903 status = destroy_queue(dws);
904 if (status != 0)
905 dev_err(&dws->master->dev, "dw_spi_remove: workqueue will not "
906 "complete, message memory not freed\n");
907
908 spi_enable_chip(dws, 0);
909 /* Disable clk */
910 spi_set_clk(dws, 0);
911 free_irq(dws->irq, dws);
912
913 /* Disconnect from the SPI framework */
914 spi_unregister_master(dws->master);
915}
916
917int dw_spi_suspend_host(struct dw_spi *dws)
918{
919 int ret = 0;
920
921 ret = stop_queue(dws);
922 if (ret)
923 return ret;
924 spi_enable_chip(dws, 0);
925 spi_set_clk(dws, 0);
926 return ret;
927}
928EXPORT_SYMBOL(dw_spi_suspend_host);
929
930int dw_spi_resume_host(struct dw_spi *dws)
931{
932 int ret;
933
934 spi_hw_init(dws);
935 ret = start_queue(dws);
936 if (ret)
937 dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);
938 return ret;
939}
940EXPORT_SYMBOL(dw_spi_resume_host);
941
942MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
943MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
944MODULE_LICENSE("GPL v2");
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-24 15:08:16 -0500