diff options
Diffstat (limited to 'drivers/spi/amba-pl022.c')
-rw-r--r-- | drivers/spi/amba-pl022.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/spi/amba-pl022.c b/drivers/spi/amba-pl022.c index c0f950a7cbec..ff5bbb9c43c9 100644 --- a/drivers/spi/amba-pl022.c +++ b/drivers/spi/amba-pl022.c | |||
@@ -532,7 +532,7 @@ static void restore_state(struct pl022 *pl022) | |||
532 | GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \ | 532 | GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \ |
533 | GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP, 5) | \ | 533 | GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP, 5) | \ |
534 | GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ | 534 | GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ |
535 | GEN_MASK_BITS(SSP_CLK_FALLING_EDGE, SSP_CR0_MASK_SPH, 7) | \ | 535 | GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ |
536 | GEN_MASK_BITS(NMDK_SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \ | 536 | GEN_MASK_BITS(NMDK_SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \ |
537 | GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS, 16) | \ | 537 | GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS, 16) | \ |
538 | GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 21) \ | 538 | GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 21) \ |
@@ -1247,8 +1247,8 @@ static int verify_controller_parameters(struct pl022 *pl022, | |||
1247 | return -EINVAL; | 1247 | return -EINVAL; |
1248 | } | 1248 | } |
1249 | if (chip_info->iface == SSP_INTERFACE_MOTOROLA_SPI) { | 1249 | if (chip_info->iface == SSP_INTERFACE_MOTOROLA_SPI) { |
1250 | if ((chip_info->clk_phase != SSP_CLK_RISING_EDGE) | 1250 | if ((chip_info->clk_phase != SSP_CLK_FIRST_EDGE) |
1251 | && (chip_info->clk_phase != SSP_CLK_FALLING_EDGE)) { | 1251 | && (chip_info->clk_phase != SSP_CLK_SECOND_EDGE)) { |
1252 | dev_err(chip_info->dev, | 1252 | dev_err(chip_info->dev, |
1253 | "Clock Phase is configured incorrectly\n"); | 1253 | "Clock Phase is configured incorrectly\n"); |
1254 | return -EINVAL; | 1254 | return -EINVAL; |
@@ -1485,7 +1485,7 @@ static int pl022_setup(struct spi_device *spi) | |||
1485 | chip_info->data_size = SSP_DATA_BITS_12; | 1485 | chip_info->data_size = SSP_DATA_BITS_12; |
1486 | chip_info->rx_lev_trig = SSP_RX_1_OR_MORE_ELEM; | 1486 | chip_info->rx_lev_trig = SSP_RX_1_OR_MORE_ELEM; |
1487 | chip_info->tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC; | 1487 | chip_info->tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC; |
1488 | chip_info->clk_phase = SSP_CLK_FALLING_EDGE; | 1488 | chip_info->clk_phase = SSP_CLK_SECOND_EDGE; |
1489 | chip_info->clk_pol = SSP_CLK_POL_IDLE_LOW; | 1489 | chip_info->clk_pol = SSP_CLK_POL_IDLE_LOW; |
1490 | chip_info->ctrl_len = SSP_BITS_8; | 1490 | chip_info->ctrl_len = SSP_BITS_8; |
1491 | chip_info->wait_state = SSP_MWIRE_WAIT_ZERO; | 1491 | chip_info->wait_state = SSP_MWIRE_WAIT_ZERO; |
@@ -1826,7 +1826,7 @@ static struct amba_id pl022_ids[] = { | |||
1826 | * ST Micro derivative, this has 32bit wide | 1826 | * ST Micro derivative, this has 32bit wide |
1827 | * and 32 locations deep TX/RX FIFO | 1827 | * and 32 locations deep TX/RX FIFO |
1828 | */ | 1828 | */ |
1829 | .id = 0x00108022, | 1829 | .id = 0x01080022, |
1830 | .mask = 0xffffffff, | 1830 | .mask = 0xffffffff, |
1831 | .data = &vendor_st, | 1831 | .data = &vendor_st, |
1832 | }, | 1832 | }, |