diff options
Diffstat (limited to 'drivers/sh')
-rw-r--r-- | drivers/sh/clk/cpg.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/sh/clk/cpg.c b/drivers/sh/clk/cpg.c index 9dea32907795..9386bd21c003 100644 --- a/drivers/sh/clk/cpg.c +++ b/drivers/sh/clk/cpg.c | |||
@@ -111,7 +111,7 @@ static unsigned long sh_clk_div6_recalc(struct clk *clk) | |||
111 | clk_rate_table_build(clk, clk->freq_table, table->nr_divisors, | 111 | clk_rate_table_build(clk, clk->freq_table, table->nr_divisors, |
112 | table, NULL); | 112 | table, NULL); |
113 | 113 | ||
114 | idx = sh_clk_read(clk) & 0x003f; | 114 | idx = sh_clk_read(clk) & clk->div_mask; |
115 | 115 | ||
116 | return clk->freq_table[idx].frequency; | 116 | return clk->freq_table[idx].frequency; |
117 | } | 117 | } |
@@ -159,7 +159,7 @@ static int sh_clk_div6_set_rate(struct clk *clk, unsigned long rate) | |||
159 | return idx; | 159 | return idx; |
160 | 160 | ||
161 | value = sh_clk_read(clk); | 161 | value = sh_clk_read(clk); |
162 | value &= ~0x3f; | 162 | value &= ~clk->div_mask; |
163 | value |= idx; | 163 | value |= idx; |
164 | sh_clk_write(value, clk); | 164 | sh_clk_write(value, clk); |
165 | return 0; | 165 | return 0; |
@@ -185,7 +185,7 @@ static void sh_clk_div6_disable(struct clk *clk) | |||
185 | 185 | ||
186 | value = sh_clk_read(clk); | 186 | value = sh_clk_read(clk); |
187 | value |= 0x100; /* stop clock */ | 187 | value |= 0x100; /* stop clock */ |
188 | value |= 0x3f; /* VDIV bits must be non-zero, overwrite divider */ | 188 | value |= clk->div_mask; /* VDIV bits must be non-zero, overwrite divider */ |
189 | sh_clk_write(value, clk); | 189 | sh_clk_write(value, clk); |
190 | } | 190 | } |
191 | 191 | ||
@@ -295,7 +295,7 @@ static unsigned long sh_clk_div4_recalc(struct clk *clk) | |||
295 | clk_rate_table_build(clk, clk->freq_table, table->nr_divisors, | 295 | clk_rate_table_build(clk, clk->freq_table, table->nr_divisors, |
296 | table, &clk->arch_flags); | 296 | table, &clk->arch_flags); |
297 | 297 | ||
298 | idx = (sh_clk_read(clk) >> clk->enable_bit) & 0x000f; | 298 | idx = (sh_clk_read(clk) >> clk->enable_bit) & clk->div_mask; |
299 | 299 | ||
300 | return clk->freq_table[idx].frequency; | 300 | return clk->freq_table[idx].frequency; |
301 | } | 301 | } |
@@ -338,7 +338,7 @@ static int sh_clk_div4_set_rate(struct clk *clk, unsigned long rate) | |||
338 | return idx; | 338 | return idx; |
339 | 339 | ||
340 | value = sh_clk_read(clk); | 340 | value = sh_clk_read(clk); |
341 | value &= ~(0xf << clk->enable_bit); | 341 | value &= ~(clk->div_mask << clk->enable_bit); |
342 | value |= (idx << clk->enable_bit); | 342 | value |= (idx << clk->enable_bit); |
343 | sh_clk_write(value, clk); | 343 | sh_clk_write(value, clk); |
344 | 344 | ||