diff options
Diffstat (limited to 'drivers/sh/intc.c')
| -rw-r--r-- | drivers/sh/intc.c | 266 |
1 files changed, 194 insertions, 72 deletions
diff --git a/drivers/sh/intc.c b/drivers/sh/intc.c index d5d7f23c19a5..3a5a17db9474 100644 --- a/drivers/sh/intc.c +++ b/drivers/sh/intc.c | |||
| @@ -259,6 +259,43 @@ static void intc_disable(unsigned int irq) | |||
| 259 | } | 259 | } |
| 260 | } | 260 | } |
| 261 | 261 | ||
| 262 | static void (*intc_enable_noprio_fns[])(unsigned long addr, | ||
| 263 | unsigned long handle, | ||
| 264 | void (*fn)(unsigned long, | ||
| 265 | unsigned long, | ||
| 266 | unsigned long), | ||
| 267 | unsigned int irq) = { | ||
| 268 | [MODE_ENABLE_REG] = intc_mode_field, | ||
| 269 | [MODE_MASK_REG] = intc_mode_zero, | ||
| 270 | [MODE_DUAL_REG] = intc_mode_field, | ||
| 271 | [MODE_PRIO_REG] = intc_mode_field, | ||
| 272 | [MODE_PCLR_REG] = intc_mode_field, | ||
| 273 | }; | ||
| 274 | |||
| 275 | static void intc_enable_disable(struct intc_desc_int *d, | ||
| 276 | unsigned long handle, int do_enable) | ||
| 277 | { | ||
| 278 | unsigned long addr; | ||
| 279 | unsigned int cpu; | ||
| 280 | void (*fn)(unsigned long, unsigned long, | ||
| 281 | void (*)(unsigned long, unsigned long, unsigned long), | ||
| 282 | unsigned int); | ||
| 283 | |||
| 284 | if (do_enable) { | ||
| 285 | for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) { | ||
| 286 | addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu); | ||
| 287 | fn = intc_enable_noprio_fns[_INTC_MODE(handle)]; | ||
| 288 | fn(addr, handle, intc_reg_fns[_INTC_FN(handle)], 0); | ||
| 289 | } | ||
| 290 | } else { | ||
| 291 | for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) { | ||
| 292 | addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu); | ||
| 293 | fn = intc_disable_fns[_INTC_MODE(handle)]; | ||
| 294 | fn(addr, handle, intc_reg_fns[_INTC_FN(handle)], 0); | ||
| 295 | } | ||
| 296 | } | ||
| 297 | } | ||
| 298 | |||
| 262 | static int intc_set_wake(unsigned int irq, unsigned int on) | 299 | static int intc_set_wake(unsigned int irq, unsigned int on) |
| 263 | { | 300 | { |
| 264 | return 0; /* allow wakeup, but setup hardware in intc_suspend() */ | 301 | return 0; /* allow wakeup, but setup hardware in intc_suspend() */ |
| @@ -400,11 +437,11 @@ static unsigned int __init intc_get_reg(struct intc_desc_int *d, | |||
| 400 | static intc_enum __init intc_grp_id(struct intc_desc *desc, | 437 | static intc_enum __init intc_grp_id(struct intc_desc *desc, |
| 401 | intc_enum enum_id) | 438 | intc_enum enum_id) |
| 402 | { | 439 | { |
| 403 | struct intc_group *g = desc->groups; | 440 | struct intc_group *g = desc->hw.groups; |
| 404 | unsigned int i, j; | 441 | unsigned int i, j; |
| 405 | 442 | ||
| 406 | for (i = 0; g && enum_id && i < desc->nr_groups; i++) { | 443 | for (i = 0; g && enum_id && i < desc->hw.nr_groups; i++) { |
| 407 | g = desc->groups + i; | 444 | g = desc->hw.groups + i; |
| 408 | 445 | ||
| 409 | for (j = 0; g->enum_ids[j]; j++) { | 446 | for (j = 0; g->enum_ids[j]; j++) { |
| 410 | if (g->enum_ids[j] != enum_id) | 447 | if (g->enum_ids[j] != enum_id) |
| @@ -417,19 +454,21 @@ static intc_enum __init intc_grp_id(struct intc_desc *desc, | |||
| 417 | return 0; | 454 | return 0; |
| 418 | } | 455 | } |
| 419 | 456 | ||
| 420 | static unsigned int __init intc_mask_data(struct intc_desc *desc, | 457 | static unsigned int __init _intc_mask_data(struct intc_desc *desc, |
| 421 | struct intc_desc_int *d, | 458 | struct intc_desc_int *d, |
| 422 | intc_enum enum_id, int do_grps) | 459 | intc_enum enum_id, |
| 460 | unsigned int *reg_idx, | ||
| 461 | unsigned int *fld_idx) | ||
| 423 | { | 462 | { |
| 424 | struct intc_mask_reg *mr = desc->mask_regs; | 463 | struct intc_mask_reg *mr = desc->hw.mask_regs; |
| 425 | unsigned int i, j, fn, mode; | 464 | unsigned int fn, mode; |
| 426 | unsigned long reg_e, reg_d; | 465 | unsigned long reg_e, reg_d; |
| 427 | 466 | ||
| 428 | for (i = 0; mr && enum_id && i < desc->nr_mask_regs; i++) { | 467 | while (mr && enum_id && *reg_idx < desc->hw.nr_mask_regs) { |
| 429 | mr = desc->mask_regs + i; | 468 | mr = desc->hw.mask_regs + *reg_idx; |
| 430 | 469 | ||
| 431 | for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) { | 470 | for (; *fld_idx < ARRAY_SIZE(mr->enum_ids); (*fld_idx)++) { |
| 432 | if (mr->enum_ids[j] != enum_id) | 471 | if (mr->enum_ids[*fld_idx] != enum_id) |
| 433 | continue; | 472 | continue; |
| 434 | 473 | ||
| 435 | if (mr->set_reg && mr->clr_reg) { | 474 | if (mr->set_reg && mr->clr_reg) { |
| @@ -455,29 +494,49 @@ static unsigned int __init intc_mask_data(struct intc_desc *desc, | |||
| 455 | intc_get_reg(d, reg_e), | 494 | intc_get_reg(d, reg_e), |
| 456 | intc_get_reg(d, reg_d), | 495 | intc_get_reg(d, reg_d), |
| 457 | 1, | 496 | 1, |
| 458 | (mr->reg_width - 1) - j); | 497 | (mr->reg_width - 1) - *fld_idx); |
| 459 | } | 498 | } |
| 499 | |||
| 500 | *fld_idx = 0; | ||
| 501 | (*reg_idx)++; | ||
| 460 | } | 502 | } |
| 461 | 503 | ||
| 504 | return 0; | ||
| 505 | } | ||
| 506 | |||
| 507 | static unsigned int __init intc_mask_data(struct intc_desc *desc, | ||
| 508 | struct intc_desc_int *d, | ||
| 509 | intc_enum enum_id, int do_grps) | ||
| 510 | { | ||
| 511 | unsigned int i = 0; | ||
| 512 | unsigned int j = 0; | ||
| 513 | unsigned int ret; | ||
| 514 | |||
| 515 | ret = _intc_mask_data(desc, d, enum_id, &i, &j); | ||
| 516 | if (ret) | ||
| 517 | return ret; | ||
| 518 | |||
| 462 | if (do_grps) | 519 | if (do_grps) |
| 463 | return intc_mask_data(desc, d, intc_grp_id(desc, enum_id), 0); | 520 | return intc_mask_data(desc, d, intc_grp_id(desc, enum_id), 0); |
| 464 | 521 | ||
| 465 | return 0; | 522 | return 0; |
| 466 | } | 523 | } |
| 467 | 524 | ||
| 468 | static unsigned int __init intc_prio_data(struct intc_desc *desc, | 525 | static unsigned int __init _intc_prio_data(struct intc_desc *desc, |
| 469 | struct intc_desc_int *d, | 526 | struct intc_desc_int *d, |
| 470 | intc_enum enum_id, int do_grps) | 527 | intc_enum enum_id, |
| 528 | unsigned int *reg_idx, | ||
| 529 | unsigned int *fld_idx) | ||
| 471 | { | 530 | { |
| 472 | struct intc_prio_reg *pr = desc->prio_regs; | 531 | struct intc_prio_reg *pr = desc->hw.prio_regs; |
| 473 | unsigned int i, j, fn, mode, bit; | 532 | unsigned int fn, n, mode, bit; |
| 474 | unsigned long reg_e, reg_d; | 533 | unsigned long reg_e, reg_d; |
| 475 | 534 | ||
| 476 | for (i = 0; pr && enum_id && i < desc->nr_prio_regs; i++) { | 535 | while (pr && enum_id && *reg_idx < desc->hw.nr_prio_regs) { |
| 477 | pr = desc->prio_regs + i; | 536 | pr = desc->hw.prio_regs + *reg_idx; |
| 478 | 537 | ||
| 479 | for (j = 0; j < ARRAY_SIZE(pr->enum_ids); j++) { | 538 | for (; *fld_idx < ARRAY_SIZE(pr->enum_ids); (*fld_idx)++) { |
| 480 | if (pr->enum_ids[j] != enum_id) | 539 | if (pr->enum_ids[*fld_idx] != enum_id) |
| 481 | continue; | 540 | continue; |
| 482 | 541 | ||
| 483 | if (pr->set_reg && pr->clr_reg) { | 542 | if (pr->set_reg && pr->clr_reg) { |
| @@ -495,34 +554,79 @@ static unsigned int __init intc_prio_data(struct intc_desc *desc, | |||
| 495 | } | 554 | } |
| 496 | 555 | ||
| 497 | fn += (pr->reg_width >> 3) - 1; | 556 | fn += (pr->reg_width >> 3) - 1; |
| 557 | n = *fld_idx + 1; | ||
| 498 | 558 | ||
| 499 | BUG_ON((j + 1) * pr->field_width > pr->reg_width); | 559 | BUG_ON(n * pr->field_width > pr->reg_width); |
| 500 | 560 | ||
| 501 | bit = pr->reg_width - ((j + 1) * pr->field_width); | 561 | bit = pr->reg_width - (n * pr->field_width); |
| 502 | 562 | ||
| 503 | return _INTC_MK(fn, mode, | 563 | return _INTC_MK(fn, mode, |
| 504 | intc_get_reg(d, reg_e), | 564 | intc_get_reg(d, reg_e), |
| 505 | intc_get_reg(d, reg_d), | 565 | intc_get_reg(d, reg_d), |
| 506 | pr->field_width, bit); | 566 | pr->field_width, bit); |
| 507 | } | 567 | } |
| 568 | |||
| 569 | *fld_idx = 0; | ||
| 570 | (*reg_idx)++; | ||
| 508 | } | 571 | } |
| 509 | 572 | ||
| 573 | return 0; | ||
| 574 | } | ||
| 575 | |||
| 576 | static unsigned int __init intc_prio_data(struct intc_desc *desc, | ||
| 577 | struct intc_desc_int *d, | ||
| 578 | intc_enum enum_id, int do_grps) | ||
| 579 | { | ||
| 580 | unsigned int i = 0; | ||
| 581 | unsigned int j = 0; | ||
| 582 | unsigned int ret; | ||
| 583 | |||
| 584 | ret = _intc_prio_data(desc, d, enum_id, &i, &j); | ||
| 585 | if (ret) | ||
| 586 | return ret; | ||
| 587 | |||
| 510 | if (do_grps) | 588 | if (do_grps) |
| 511 | return intc_prio_data(desc, d, intc_grp_id(desc, enum_id), 0); | 589 | return intc_prio_data(desc, d, intc_grp_id(desc, enum_id), 0); |
| 512 | 590 | ||
| 513 | return 0; | 591 | return 0; |
| 514 | } | 592 | } |
| 515 | 593 | ||
| 594 | static void __init intc_enable_disable_enum(struct intc_desc *desc, | ||
| 595 | struct intc_desc_int *d, | ||
| 596 | intc_enum enum_id, int enable) | ||
| 597 | { | ||
| 598 | unsigned int i, j, data; | ||
| 599 | |||
| 600 | /* go through and enable/disable all mask bits */ | ||
| 601 | i = j = 0; | ||
| 602 | do { | ||
| 603 | data = _intc_mask_data(desc, d, enum_id, &i, &j); | ||
| 604 | if (data) | ||
| 605 | intc_enable_disable(d, data, enable); | ||
| 606 | j++; | ||
| 607 | } while (data); | ||
| 608 | |||
| 609 | /* go through and enable/disable all priority fields */ | ||
| 610 | i = j = 0; | ||
| 611 | do { | ||
| 612 | data = _intc_prio_data(desc, d, enum_id, &i, &j); | ||
| 613 | if (data) | ||
| 614 | intc_enable_disable(d, data, enable); | ||
| 615 | |||
| 616 | j++; | ||
| 617 | } while (data); | ||
| 618 | } | ||
| 619 | |||
| 516 | static unsigned int __init intc_ack_data(struct intc_desc *desc, | 620 | static unsigned int __init intc_ack_data(struct intc_desc *desc, |
| 517 | struct intc_desc_int *d, | 621 | struct intc_desc_int *d, |
| 518 | intc_enum enum_id) | 622 | intc_enum enum_id) |
| 519 | { | 623 | { |
| 520 | struct intc_mask_reg *mr = desc->ack_regs; | 624 | struct intc_mask_reg *mr = desc->hw.ack_regs; |
| 521 | unsigned int i, j, fn, mode; | 625 | unsigned int i, j, fn, mode; |
| 522 | unsigned long reg_e, reg_d; | 626 | unsigned long reg_e, reg_d; |
| 523 | 627 | ||
| 524 | for (i = 0; mr && enum_id && i < desc->nr_ack_regs; i++) { | 628 | for (i = 0; mr && enum_id && i < desc->hw.nr_ack_regs; i++) { |
| 525 | mr = desc->ack_regs + i; | 629 | mr = desc->hw.ack_regs + i; |
| 526 | 630 | ||
| 527 | for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) { | 631 | for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) { |
| 528 | if (mr->enum_ids[j] != enum_id) | 632 | if (mr->enum_ids[j] != enum_id) |
| @@ -549,11 +653,11 @@ static unsigned int __init intc_sense_data(struct intc_desc *desc, | |||
| 549 | struct intc_desc_int *d, | 653 | struct intc_desc_int *d, |
| 550 | intc_enum enum_id) | 654 | intc_enum enum_id) |
| 551 | { | 655 | { |
| 552 | struct intc_sense_reg *sr = desc->sense_regs; | 656 | struct intc_sense_reg *sr = desc->hw.sense_regs; |
| 553 | unsigned int i, j, fn, bit; | 657 | unsigned int i, j, fn, bit; |
| 554 | 658 | ||
| 555 | for (i = 0; sr && enum_id && i < desc->nr_sense_regs; i++) { | 659 | for (i = 0; sr && enum_id && i < desc->hw.nr_sense_regs; i++) { |
| 556 | sr = desc->sense_regs + i; | 660 | sr = desc->hw.sense_regs + i; |
| 557 | 661 | ||
| 558 | for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) { | 662 | for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) { |
| 559 | if (sr->enum_ids[j] != enum_id) | 663 | if (sr->enum_ids[j] != enum_id) |
| @@ -656,7 +760,7 @@ static void __init intc_register_irq(struct intc_desc *desc, | |||
| 656 | /* irq should be disabled by default */ | 760 | /* irq should be disabled by default */ |
| 657 | d->chip.mask(irq); | 761 | d->chip.mask(irq); |
| 658 | 762 | ||
| 659 | if (desc->ack_regs) | 763 | if (desc->hw.ack_regs) |
| 660 | ack_handle[irq] = intc_ack_data(desc, d, enum_id); | 764 | ack_handle[irq] = intc_ack_data(desc, d, enum_id); |
| 661 | } | 765 | } |
| 662 | 766 | ||
| @@ -684,6 +788,7 @@ static void intc_redirect_irq(unsigned int irq, struct irq_desc *desc) | |||
| 684 | void __init register_intc_controller(struct intc_desc *desc) | 788 | void __init register_intc_controller(struct intc_desc *desc) |
| 685 | { | 789 | { |
| 686 | unsigned int i, k, smp; | 790 | unsigned int i, k, smp; |
| 791 | struct intc_hw_desc *hw = &desc->hw; | ||
| 687 | struct intc_desc_int *d; | 792 | struct intc_desc_int *d; |
| 688 | 793 | ||
| 689 | d = kzalloc(sizeof(*d), GFP_NOWAIT); | 794 | d = kzalloc(sizeof(*d), GFP_NOWAIT); |
| @@ -691,10 +796,10 @@ void __init register_intc_controller(struct intc_desc *desc) | |||
| 691 | INIT_LIST_HEAD(&d->list); | 796 | INIT_LIST_HEAD(&d->list); |
| 692 | list_add(&d->list, &intc_list); | 797 | list_add(&d->list, &intc_list); |
| 693 | 798 | ||
| 694 | d->nr_reg = desc->mask_regs ? desc->nr_mask_regs * 2 : 0; | 799 | d->nr_reg = hw->mask_regs ? hw->nr_mask_regs * 2 : 0; |
| 695 | d->nr_reg += desc->prio_regs ? desc->nr_prio_regs * 2 : 0; | 800 | d->nr_reg += hw->prio_regs ? hw->nr_prio_regs * 2 : 0; |
| 696 | d->nr_reg += desc->sense_regs ? desc->nr_sense_regs : 0; | 801 | d->nr_reg += hw->sense_regs ? hw->nr_sense_regs : 0; |
| 697 | d->nr_reg += desc->ack_regs ? desc->nr_ack_regs : 0; | 802 | d->nr_reg += hw->ack_regs ? hw->nr_ack_regs : 0; |
| 698 | 803 | ||
| 699 | d->reg = kzalloc(d->nr_reg * sizeof(*d->reg), GFP_NOWAIT); | 804 | d->reg = kzalloc(d->nr_reg * sizeof(*d->reg), GFP_NOWAIT); |
| 700 | #ifdef CONFIG_SMP | 805 | #ifdef CONFIG_SMP |
| @@ -702,30 +807,31 @@ void __init register_intc_controller(struct intc_desc *desc) | |||
| 702 | #endif | 807 | #endif |
| 703 | k = 0; | 808 | k = 0; |
| 704 | 809 | ||
| 705 | if (desc->mask_regs) { | 810 | if (hw->mask_regs) { |
| 706 | for (i = 0; i < desc->nr_mask_regs; i++) { | 811 | for (i = 0; i < hw->nr_mask_regs; i++) { |
| 707 | smp = IS_SMP(desc->mask_regs[i]); | 812 | smp = IS_SMP(hw->mask_regs[i]); |
| 708 | k += save_reg(d, k, desc->mask_regs[i].set_reg, smp); | 813 | k += save_reg(d, k, hw->mask_regs[i].set_reg, smp); |
| 709 | k += save_reg(d, k, desc->mask_regs[i].clr_reg, smp); | 814 | k += save_reg(d, k, hw->mask_regs[i].clr_reg, smp); |
| 710 | } | 815 | } |
| 711 | } | 816 | } |
| 712 | 817 | ||
| 713 | if (desc->prio_regs) { | 818 | if (hw->prio_regs) { |
| 714 | d->prio = kzalloc(desc->nr_vectors * sizeof(*d->prio), GFP_NOWAIT); | 819 | d->prio = kzalloc(hw->nr_vectors * sizeof(*d->prio), |
| 820 | GFP_NOWAIT); | ||
| 715 | 821 | ||
| 716 | for (i = 0; i < desc->nr_prio_regs; i++) { | 822 | for (i = 0; i < hw->nr_prio_regs; i++) { |
| 717 | smp = IS_SMP(desc->prio_regs[i]); | 823 | smp = IS_SMP(hw->prio_regs[i]); |
| 718 | k += save_reg(d, k, desc->prio_regs[i].set_reg, smp); | 824 | k += save_reg(d, k, hw->prio_regs[i].set_reg, smp); |
| 719 | k += save_reg(d, k, desc->prio_regs[i].clr_reg, smp); | 825 | k += save_reg(d, k, hw->prio_regs[i].clr_reg, smp); |
| 720 | } | 826 | } |
| 721 | } | 827 | } |
| 722 | 828 | ||
| 723 | if (desc->sense_regs) { | 829 | if (hw->sense_regs) { |
| 724 | d->sense = kzalloc(desc->nr_vectors * sizeof(*d->sense), GFP_NOWAIT); | 830 | d->sense = kzalloc(hw->nr_vectors * sizeof(*d->sense), |
| 831 | GFP_NOWAIT); | ||
| 725 | 832 | ||
| 726 | for (i = 0; i < desc->nr_sense_regs; i++) { | 833 | for (i = 0; i < hw->nr_sense_regs; i++) |
| 727 | k += save_reg(d, k, desc->sense_regs[i].reg, 0); | 834 | k += save_reg(d, k, hw->sense_regs[i].reg, 0); |
| 728 | } | ||
| 729 | } | 835 | } |
| 730 | 836 | ||
| 731 | d->chip.name = desc->name; | 837 | d->chip.name = desc->name; |
| @@ -738,18 +844,26 @@ void __init register_intc_controller(struct intc_desc *desc) | |||
| 738 | d->chip.set_type = intc_set_sense; | 844 | d->chip.set_type = intc_set_sense; |
| 739 | d->chip.set_wake = intc_set_wake; | 845 | d->chip.set_wake = intc_set_wake; |
| 740 | 846 | ||
| 741 | if (desc->ack_regs) { | 847 | if (hw->ack_regs) { |
| 742 | for (i = 0; i < desc->nr_ack_regs; i++) | 848 | for (i = 0; i < hw->nr_ack_regs; i++) |
| 743 | k += save_reg(d, k, desc->ack_regs[i].set_reg, 0); | 849 | k += save_reg(d, k, hw->ack_regs[i].set_reg, 0); |
| 744 | 850 | ||
| 745 | d->chip.mask_ack = intc_mask_ack; | 851 | d->chip.mask_ack = intc_mask_ack; |
| 746 | } | 852 | } |
| 747 | 853 | ||
| 854 | /* disable bits matching force_disable before registering irqs */ | ||
| 855 | if (desc->force_disable) | ||
| 856 | intc_enable_disable_enum(desc, d, desc->force_disable, 0); | ||
| 857 | |||
| 858 | /* disable bits matching force_enable before registering irqs */ | ||
| 859 | if (desc->force_enable) | ||
| 860 | intc_enable_disable_enum(desc, d, desc->force_enable, 0); | ||
| 861 | |||
| 748 | BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */ | 862 | BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */ |
| 749 | 863 | ||
| 750 | /* register the vectors one by one */ | 864 | /* register the vectors one by one */ |
| 751 | for (i = 0; i < desc->nr_vectors; i++) { | 865 | for (i = 0; i < hw->nr_vectors; i++) { |
| 752 | struct intc_vect *vect = desc->vectors + i; | 866 | struct intc_vect *vect = hw->vectors + i; |
| 753 | unsigned int irq = evt2irq(vect->vect); | 867 | unsigned int irq = evt2irq(vect->vect); |
| 754 | struct irq_desc *irq_desc; | 868 | struct irq_desc *irq_desc; |
| 755 | 869 | ||
| @@ -764,8 +878,8 @@ void __init register_intc_controller(struct intc_desc *desc) | |||
| 764 | 878 | ||
| 765 | intc_register_irq(desc, d, vect->enum_id, irq); | 879 | intc_register_irq(desc, d, vect->enum_id, irq); |
| 766 | 880 | ||
| 767 | for (k = i + 1; k < desc->nr_vectors; k++) { | 881 | for (k = i + 1; k < hw->nr_vectors; k++) { |
| 768 | struct intc_vect *vect2 = desc->vectors + k; | 882 | struct intc_vect *vect2 = hw->vectors + k; |
| 769 | unsigned int irq2 = evt2irq(vect2->vect); | 883 | unsigned int irq2 = evt2irq(vect2->vect); |
| 770 | 884 | ||
| 771 | if (vect->enum_id != vect2->enum_id) | 885 | if (vect->enum_id != vect2->enum_id) |
| @@ -785,11 +899,15 @@ void __init register_intc_controller(struct intc_desc *desc) | |||
| 785 | vect2->enum_id = 0; | 899 | vect2->enum_id = 0; |
| 786 | 900 | ||
| 787 | /* redirect this interrupts to the first one */ | 901 | /* redirect this interrupts to the first one */ |
| 788 | set_irq_chip_and_handler_name(irq2, &d->chip, | 902 | set_irq_chip(irq2, &dummy_irq_chip); |
| 789 | intc_redirect_irq, "redirect"); | 903 | set_irq_chained_handler(irq2, intc_redirect_irq); |
| 790 | set_irq_data(irq2, (void *)irq); | 904 | set_irq_data(irq2, (void *)irq); |
| 791 | } | 905 | } |
| 792 | } | 906 | } |
| 907 | |||
| 908 | /* enable bits matching force_enable after registering irqs */ | ||
| 909 | if (desc->force_enable) | ||
| 910 | intc_enable_disable_enum(desc, d, desc->force_enable, 1); | ||
| 793 | } | 911 | } |
| 794 | 912 | ||
| 795 | static int intc_suspend(struct sys_device *dev, pm_message_t state) | 913 | static int intc_suspend(struct sys_device *dev, pm_message_t state) |
| @@ -872,7 +990,7 @@ device_initcall(register_intc_sysdevs); | |||
| 872 | /* | 990 | /* |
| 873 | * Dynamic IRQ allocation and deallocation | 991 | * Dynamic IRQ allocation and deallocation |
| 874 | */ | 992 | */ |
| 875 | static unsigned int create_irq_on_node(unsigned int irq_want, int node) | 993 | unsigned int create_irq_nr(unsigned int irq_want, int node) |
| 876 | { | 994 | { |
| 877 | unsigned int irq = 0, new; | 995 | unsigned int irq = 0, new; |
| 878 | unsigned long flags; | 996 | unsigned long flags; |
| @@ -881,24 +999,28 @@ static unsigned int create_irq_on_node(unsigned int irq_want, int node) | |||
| 881 | spin_lock_irqsave(&vector_lock, flags); | 999 | spin_lock_irqsave(&vector_lock, flags); |
| 882 | 1000 | ||
| 883 | /* | 1001 | /* |
| 884 | * First try the wanted IRQ, then scan. | 1002 | * First try the wanted IRQ |
| 885 | */ | 1003 | */ |
| 886 | if (test_and_set_bit(irq_want, intc_irq_map)) { | 1004 | if (test_and_set_bit(irq_want, intc_irq_map) == 0) { |
| 1005 | new = irq_want; | ||
| 1006 | } else { | ||
| 1007 | /* .. then fall back to scanning. */ | ||
| 887 | new = find_first_zero_bit(intc_irq_map, nr_irqs); | 1008 | new = find_first_zero_bit(intc_irq_map, nr_irqs); |
| 888 | if (unlikely(new == nr_irqs)) | 1009 | if (unlikely(new == nr_irqs)) |
| 889 | goto out_unlock; | 1010 | goto out_unlock; |
| 890 | 1011 | ||
| 891 | desc = irq_to_desc_alloc_node(new, node); | ||
| 892 | if (unlikely(!desc)) { | ||
| 893 | pr_info("can't get irq_desc for %d\n", new); | ||
| 894 | goto out_unlock; | ||
| 895 | } | ||
| 896 | |||
| 897 | desc = move_irq_desc(desc, node); | ||
| 898 | __set_bit(new, intc_irq_map); | 1012 | __set_bit(new, intc_irq_map); |
| 899 | irq = new; | ||
| 900 | } | 1013 | } |
| 901 | 1014 | ||
| 1015 | desc = irq_to_desc_alloc_node(new, node); | ||
| 1016 | if (unlikely(!desc)) { | ||
| 1017 | pr_info("can't get irq_desc for %d\n", new); | ||
| 1018 | goto out_unlock; | ||
| 1019 | } | ||
| 1020 | |||
| 1021 | desc = move_irq_desc(desc, node); | ||
| 1022 | irq = new; | ||
| 1023 | |||
| 902 | out_unlock: | 1024 | out_unlock: |
| 903 | spin_unlock_irqrestore(&vector_lock, flags); | 1025 | spin_unlock_irqrestore(&vector_lock, flags); |
| 904 | 1026 | ||
| @@ -913,7 +1035,7 @@ int create_irq(void) | |||
| 913 | int nid = cpu_to_node(smp_processor_id()); | 1035 | int nid = cpu_to_node(smp_processor_id()); |
| 914 | int irq; | 1036 | int irq; |
| 915 | 1037 | ||
| 916 | irq = create_irq_on_node(NR_IRQS_LEGACY, nid); | 1038 | irq = create_irq_nr(NR_IRQS_LEGACY, nid); |
| 917 | if (irq == 0) | 1039 | if (irq == 0) |
| 918 | irq = -1; | 1040 | irq = -1; |
| 919 | 1041 | ||
