diff options
Diffstat (limited to 'drivers/sh/clk')
-rw-r--r-- | drivers/sh/clk/core.c | 16 | ||||
-rw-r--r-- | drivers/sh/clk/cpg.c | 7 |
2 files changed, 9 insertions, 14 deletions
diff --git a/drivers/sh/clk/core.c b/drivers/sh/clk/core.c index cb12a8e1466b..3f5e387ed564 100644 --- a/drivers/sh/clk/core.c +++ b/drivers/sh/clk/core.c | |||
@@ -418,8 +418,11 @@ int clk_register(struct clk *clk) | |||
418 | list_add(&clk->sibling, &root_clks); | 418 | list_add(&clk->sibling, &root_clks); |
419 | 419 | ||
420 | list_add(&clk->node, &clock_list); | 420 | list_add(&clk->node, &clock_list); |
421 | |||
422 | #ifdef CONFIG_SH_CLK_CPG_LEGACY | ||
421 | if (clk->ops && clk->ops->init) | 423 | if (clk->ops && clk->ops->init) |
422 | clk->ops->init(clk); | 424 | clk->ops->init(clk); |
425 | #endif | ||
423 | 426 | ||
424 | out_unlock: | 427 | out_unlock: |
425 | mutex_unlock(&clock_list_sem); | 428 | mutex_unlock(&clock_list_sem); |
@@ -455,19 +458,13 @@ EXPORT_SYMBOL_GPL(clk_get_rate); | |||
455 | 458 | ||
456 | int clk_set_rate(struct clk *clk, unsigned long rate) | 459 | int clk_set_rate(struct clk *clk, unsigned long rate) |
457 | { | 460 | { |
458 | return clk_set_rate_ex(clk, rate, 0); | ||
459 | } | ||
460 | EXPORT_SYMBOL_GPL(clk_set_rate); | ||
461 | |||
462 | int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id) | ||
463 | { | ||
464 | int ret = -EOPNOTSUPP; | 461 | int ret = -EOPNOTSUPP; |
465 | unsigned long flags; | 462 | unsigned long flags; |
466 | 463 | ||
467 | spin_lock_irqsave(&clock_lock, flags); | 464 | spin_lock_irqsave(&clock_lock, flags); |
468 | 465 | ||
469 | if (likely(clk->ops && clk->ops->set_rate)) { | 466 | if (likely(clk->ops && clk->ops->set_rate)) { |
470 | ret = clk->ops->set_rate(clk, rate, algo_id); | 467 | ret = clk->ops->set_rate(clk, rate); |
471 | if (ret != 0) | 468 | if (ret != 0) |
472 | goto out_unlock; | 469 | goto out_unlock; |
473 | } else { | 470 | } else { |
@@ -485,7 +482,7 @@ out_unlock: | |||
485 | 482 | ||
486 | return ret; | 483 | return ret; |
487 | } | 484 | } |
488 | EXPORT_SYMBOL_GPL(clk_set_rate_ex); | 485 | EXPORT_SYMBOL_GPL(clk_set_rate); |
489 | 486 | ||
490 | int clk_set_parent(struct clk *clk, struct clk *parent) | 487 | int clk_set_parent(struct clk *clk, struct clk *parent) |
491 | { | 488 | { |
@@ -653,8 +650,7 @@ static int clks_sysdev_suspend(struct sys_device *dev, pm_message_t state) | |||
653 | clkp->ops->set_parent(clkp, | 650 | clkp->ops->set_parent(clkp, |
654 | clkp->parent); | 651 | clkp->parent); |
655 | if (likely(clkp->ops->set_rate)) | 652 | if (likely(clkp->ops->set_rate)) |
656 | clkp->ops->set_rate(clkp, | 653 | clkp->ops->set_rate(clkp, rate); |
657 | rate, NO_CHANGE); | ||
658 | else if (likely(clkp->ops->recalc)) | 654 | else if (likely(clkp->ops->recalc)) |
659 | clkp->rate = clkp->ops->recalc(clkp); | 655 | clkp->rate = clkp->ops->recalc(clkp); |
660 | } | 656 | } |
diff --git a/drivers/sh/clk/cpg.c b/drivers/sh/clk/cpg.c index 3aea5f0ceb09..6172335ae323 100644 --- a/drivers/sh/clk/cpg.c +++ b/drivers/sh/clk/cpg.c | |||
@@ -110,8 +110,7 @@ static int sh_clk_div6_set_parent(struct clk *clk, struct clk *parent) | |||
110 | return 0; | 110 | return 0; |
111 | } | 111 | } |
112 | 112 | ||
113 | static int sh_clk_div6_set_rate(struct clk *clk, | 113 | static int sh_clk_div6_set_rate(struct clk *clk, unsigned long rate) |
114 | unsigned long rate, int algo_id) | ||
115 | { | 114 | { |
116 | unsigned long value; | 115 | unsigned long value; |
117 | int idx; | 116 | int idx; |
@@ -132,7 +131,7 @@ static int sh_clk_div6_enable(struct clk *clk) | |||
132 | unsigned long value; | 131 | unsigned long value; |
133 | int ret; | 132 | int ret; |
134 | 133 | ||
135 | ret = sh_clk_div6_set_rate(clk, clk->rate, 0); | 134 | ret = sh_clk_div6_set_rate(clk, clk->rate); |
136 | if (ret == 0) { | 135 | if (ret == 0) { |
137 | value = __raw_readl(clk->enable_reg); | 136 | value = __raw_readl(clk->enable_reg); |
138 | value &= ~0x100; /* clear stop bit to enable clock */ | 137 | value &= ~0x100; /* clear stop bit to enable clock */ |
@@ -253,7 +252,7 @@ static int sh_clk_div4_set_parent(struct clk *clk, struct clk *parent) | |||
253 | return 0; | 252 | return 0; |
254 | } | 253 | } |
255 | 254 | ||
256 | static int sh_clk_div4_set_rate(struct clk *clk, unsigned long rate, int algo_id) | 255 | static int sh_clk_div4_set_rate(struct clk *clk, unsigned long rate) |
257 | { | 256 | { |
258 | struct clk_div4_table *d4t = clk->priv; | 257 | struct clk_div4_table *d4t = clk->priv; |
259 | unsigned long value; | 258 | unsigned long value; |